diff --git a/.gitignore b/.gitignore
index ecee2c932e..c33368219b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,6 +9,7 @@
 *.pdb
 *.idb
 *.ilk
+*.old
 build
 Debug
 documentation/html
diff --git a/bsp/apollo2/README.md b/bsp/apollo2/README.md
new file mode 100644
index 0000000000..871cad2fb5
--- /dev/null
+++ b/bsp/apollo2/README.md
@@ -0,0 +1,45 @@
+Apollo2 MCU是基于Ambiq Micro的Apollo MCU产品系列的第二代控制器。
+Ambiq使用专利亚阈值功率优化技术（Subthreshold Power Optimized Technology， SPOT）平台来实现惊人的功耗降低，其功耗通常比性能相近的其它MCU产品降低5至10倍。
+Apollo2 MCU采用32位ARM Cortex-M4F微控制器，集成了高达1 MB的闪存和256 KB的RAM，以适应无线电和传感器开销，同时仍留有足够的应用代码空间。该微控制器还包括串行主机和UART端口，用于与无线电和传感器通信，包括加速度计，陀螺仪和磁力计。
+
+Features
+Ultra-low supply current
+    10 μA/MHz executing from flash at 3.3 V
+    10 μA/MHz executing from RAM at 3.3 V
+
+High-performance ARM Cortex-M4 Processor
+    Up to 48 MHz clock frequency
+    Floating point unit
+    Memory protection unit
+    Wake-up interrupt controller with 32 interrupts
+    
+Ultra-low power memory:
+    Up to 1 MB of flash memory for code/data
+    Up to 256 KB of low leakage RAM for code/data
+    16kB 1 or 2-way Associative Cache
+
+Ultra-low power interface for off-chip sensors:
+    14 bit, 15-channel, up to 1.2 MS/s ADC
+    Voltage Comparator
+    Temperature sensor with +/-2C accuracy
+
+Flexible serial peripherals:
+    6x I2C/SPI master for communication with sensors,?radios, and other peripherals
+    1x I2C/SPI slave for host communications
+    2x UART for communication with peripherals and?legacy devices
+    PDM for mono and stereo audio microphone
+
+Rich set of clock sources:
+    32.768 kHz XTAL oscillator
+    Low frequency RC oscillator – 1.024 kHz
+    High frequency RC oscillator – 48 MHz
+    RTC based on Ambiq’s AM08X5/18X5 families
+
+Wide operating range: 1.8-3.6 V, –40 to 85°C
+
+Compact package options:
+    2.5 x 2.5 mm 49-pin CSP with 34 GPIO
+    4.5 x 4.5 mm 64-pin BGA with 50 GPIO
+
+Board info
+    Apollo2 Evaluation Board（http://ambiqmicro.com/apollo-ultra-low-power-mcu/apollo2-mcu-20170703/）
\ No newline at end of file
diff --git a/bsp/apollo2/SConscript b/bsp/apollo2/SConscript
new file mode 100644
index 0000000000..744d8d7821
--- /dev/null
+++ b/bsp/apollo2/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/apollo2/SConstruct b/bsp/apollo2/SConstruct
new file mode 100644
index 0000000000..1f57277560
--- /dev/null
+++ b/bsp/apollo2/SConstruct
@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread_apollo2.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/apollo2/apollo2 evaluation board skt.jpg b/bsp/apollo2/apollo2 evaluation board skt.jpg
new file mode 100644
index 0000000000..67bf9c23ff
Binary files /dev/null and b/bsp/apollo2/apollo2 evaluation board skt.jpg differ
diff --git a/bsp/apollo2/applications/SConscript b/bsp/apollo2/applications/SConscript
new file mode 100644
index 0000000000..fc2501998c
--- /dev/null
+++ b/bsp/apollo2/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/apollo2/applications/main.c b/bsp/apollo2/applications/main.c
new file mode 100644
index 0000000000..b058fc7711
--- /dev/null
+++ b/bsp/apollo2/applications/main.c
@@ -0,0 +1,81 @@
+/*
+ * File      : main.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        the first version
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+#include "led.h"
+
+static rt_uint8_t led_stack[ 512 ];
+static struct rt_thread led_thread;
+
+static void led_thread_entry(void* parameter)
+{
+    unsigned int count=0;
+
+    while (1)
+    {
+        /* led1 on */
+#ifndef RT_USING_FINSH
+        rt_kprintf("led on, count : %d\r\n",count);
+#endif
+        count++;
+        rt_hw_led_on(0);
+        rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
+
+        /* led1 off */
+#ifndef RT_USING_FINSH
+        rt_kprintf("led off\r\n");
+#endif
+        rt_hw_led_off(0);
+        rt_thread_delay( RT_TICK_PER_SECOND/2 );
+    }
+}
+
+int main(void)
+{
+    rt_err_t result;
+
+    /* init led thread */
+    result = rt_thread_init(&led_thread,
+                            "led",
+                            led_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t*)&led_stack[0],
+                            sizeof(led_stack),
+                            RT_THREAD_PRIORITY_MAX/3,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&led_thread);
+    }
+
+    return 0;
+}
+
+/*@}*/
diff --git a/bsp/apollo2/board/Sconscript b/bsp/apollo2/board/Sconscript
new file mode 100644
index 0000000000..2f2dc9eb48
--- /dev/null
+++ b/bsp/apollo2/board/Sconscript
@@ -0,0 +1,14 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
\ No newline at end of file
diff --git a/bsp/apollo2/board/board.c b/bsp/apollo2/board/board.c
new file mode 100644
index 0000000000..d9e202570b
--- /dev/null
+++ b/bsp/apollo2/board/board.c
@@ -0,0 +1,181 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        first implementation
+ */
+#include "board.h"
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "am_mcu_apollo.h"
+#include "hal/am_hal_clkgen.h"
+#include "hal/am_hal_cachectrl.h"
+#include "uart.h"
+#include "led.h"
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define AM_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define AM_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define NRF_SRAM_BEGIN    (&__bss_end)
+#endif
+
+#define TICK_RATE_HZ  RT_TICK_PER_SECOND
+#define SYSTICK_CLOCK_HZ  ( 32768UL )
+#define WAKE_INTERVAL ( (uint32_t) ((SYSTICK_CLOCK_HZ / TICK_RATE_HZ)))
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void am_stimer_cmpr0_isr(void)
+{
+    /* Check the timer interrupt status */
+    am_hal_stimer_int_clear(AM_HAL_STIMER_INT_COMPAREA);
+    am_hal_stimer_compare_delta_set(0, WAKE_INTERVAL);
+
+    if (rt_thread_self() != RT_NULL)
+    {
+        /* enter interrupt */
+        rt_interrupt_enter();
+
+        rt_tick_increase();
+
+        /* leave interrupt */
+        rt_interrupt_leave();
+    }
+}
+
+/**
+ * This is the SysTick Configure.
+ *
+ */
+void SysTick_Configuration(void)
+{
+    /* Enable compare A interrupt in STIMER */
+    am_hal_stimer_int_enable(AM_HAL_STIMER_INT_COMPAREA);
+
+    /* Enable the timer interrupt in the NVIC, making sure to use the appropriate priority level */
+    am_hal_interrupt_enable(AM_HAL_INTERRUPT_STIMER_CMPR0);
+
+    /* Configure the STIMER and run */
+    am_hal_stimer_config(AM_HAL_STIMER_CFG_CLEAR | AM_HAL_STIMER_CFG_FREEZE);
+    am_hal_stimer_compare_delta_set(0, WAKE_INTERVAL);
+    am_hal_stimer_config(AM_HAL_STIMER_XTAL_32KHZ |
+                         AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
+}
+
+/**
+ * This is the low power operation.
+ * This function enables several power-saving features of the MCU, and
+ * disables some of the less-frequently used peripherals. It also sets the
+ * system clock to 24 MHz.
+ */
+void am_low_power_init(void)
+{
+    /* Enable internal buck converters */
+    am_hal_pwrctrl_bucks_init();
+
+    /* Initialize for low power in the power control block */
+    am_hal_pwrctrl_low_power_init();
+
+    /* Turn off the voltage comparator as this is enabled on reset */
+    am_hal_vcomp_disable();
+
+    /* Run the RTC off the LFRC */
+    am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC);
+
+    /* Stop the XT and LFRC */
+    am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_XT);
+    am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_LFRC);
+
+    /* Disable the RTC */
+    am_hal_rtc_osc_disable();
+}
+
+/**
+ * This is the deep power save.
+ *
+ */
+void deep_power_save(void)
+{
+    am_hal_interrupt_master_disable();
+
+    am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP);
+
+    am_hal_interrupt_master_enable();
+}
+
+/**
+ * This function will initial APOLLO2 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* Set the system clock to maximum frequency */
+    am_hal_clkgen_sysclk_select(AM_HAL_CLKGEN_SYSCLK_MAX);
+
+    /* Set the default cache configuration */
+    am_hal_cachectrl_enable(&am_hal_cachectrl_defaults);
+
+    /* Configure the board for low power operation */
+    am_low_power_init();
+
+    /* Config SysTick */
+    SysTick_Configuration();
+
+#ifdef RT_USING_IDLE_HOOK
+    /* Set sleep deep mode */
+    rt_thread_idle_sethook(deep_power_save);
+
+#ifndef NO_FPU
+    /* Enable the floating point module, and configure the core for lazy stacking */
+    am_hal_sysctrl_fpu_enable();
+    am_hal_sysctrl_fpu_stacking_enable(true);
+#else
+    am_hal_sysctrl_fpu_disable();
+#endif
+
+    /* Turn off unused Flash & SRAM */
+    am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_FLASH512K);
+    am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_SRAM32K);
+
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void*)AM_SRAM_BEGIN, (void*)AM_SRAM_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/apollo2/board/board.h b/bsp/apollo2/board/board.h
new file mode 100644
index 0000000000..a93892c3b2
--- /dev/null
+++ b/bsp/apollo2/board/board.h
@@ -0,0 +1,46 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        first implementation
+ */
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include <rtthread.h>
+
+// <o> Internal SRAM memory size[Kbytes] <8-256>
+// <i>Default: 256
+#define AM_SRAM_SIZE         256
+#define AM_SRAM_END          (0x10000000 + AM_SRAM_SIZE * 1024)
+
+/* USART driver select. */
+#define RT_USING_UART0
+//#define RT_USING_UART1
+
+/* LED driver select. */
+#define RT_USING_LED0
+//#define RT_USING_LED1
+//#define RT_USING_LED2
+//#define RT_USING_LED3
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/apollo2/board/gpio.c b/bsp/apollo2/board/gpio.c
new file mode 100644
index 0000000000..5c5b5b506c
--- /dev/null
+++ b/bsp/apollo2/board/gpio.c
@@ -0,0 +1,99 @@
+/*
+ * File      : gpio.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-16     Haley        the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "am_mcu_apollo.h"
+
+#ifdef RT_USING_PIN
+
+void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        am_hal_gpio_pin_config(pin, AM_HAL_GPIO_OUTPUT);
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        am_hal_gpio_pin_config(pin, AM_HAL_GPIO_INPUT);
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        am_hal_gpio_pin_config(pin, AM_HAL_GPIO_OPENDRAIN);
+    }
+    else
+    {
+        /* input setting:default. */
+        am_hal_gpio_pin_config(pin, AM_HAL_GPIO_INPUT);
+    }
+}
+
+void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    if (value == PIN_LOW)
+    {
+        am_hal_gpio_out_bit_clear(pin);
+    }
+    else
+    {
+        am_hal_gpio_out_bit_set(pin);
+    }
+}
+
+int am_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value = PIN_LOW;
+
+    if (am_hal_gpio_input_bit_read(pin) == 0)
+    {
+        value = PIN_LOW;
+    }
+    else
+    {
+        value = PIN_HIGH;
+    }
+
+    return value;
+}
+
+const static struct rt_pin_ops _am_pin_ops =
+{
+    am_pin_mode,
+    am_pin_write,
+    am_pin_read,
+};
+
+int hw_pin_init(void)
+{
+    rt_device_pin_register("pin", &_am_pin_ops, RT_NULL);
+    return 0;
+}
+
+INIT_BOARD_EXPORT(hw_pin_init);
+#endif
+
+/*@}*/
diff --git a/bsp/apollo2/board/gpio.h b/bsp/apollo2/board/gpio.h
new file mode 100644
index 0000000000..455c262224
--- /dev/null
+++ b/bsp/apollo2/board/gpio.h
@@ -0,0 +1,30 @@
+/*
+ * File      : gpio.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-16     Haley        the first version
+ */
+ 
+#ifndef __GPIO_H
+#define __GPIO_H
+
+int hw_pin_init(void);
+
+#endif // __GPIO_H
diff --git a/bsp/apollo2/board/led.c b/bsp/apollo2/board/led.c
new file mode 100644
index 0000000000..1cf68b5605
--- /dev/null
+++ b/bsp/apollo2/board/led.c
@@ -0,0 +1,157 @@
+/*
+ * File      :_led.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "am_mcu_apollo.h"
+#include "board.h"
+
+#define AM_GPIO_LED0                46
+#define AM_GPIO_LED1                47
+#define AM_GPIO_LED2                48
+#define AM_GPIO_LED3                49
+
+/**
+ * @brief Turns on the requested LED.
+ *
+ * @param LEDNum is the LED number for the light to turn on.
+ *
+ * This function turns on a single LED.
+ *
+ * @return None.
+ */
+void rt_hw_led_on(rt_uint8_t LEDNum)
+{
+#ifdef RT_USING_PIN
+    if(LEDNum == 0)
+        rt_pin_write(AM_GPIO_LED0, PIN_LOW);
+
+    else if(LEDNum == 1)
+        rt_pin_write(AM_GPIO_LED1, PIN_LOW);
+
+    else if(LEDNum == 2)
+        rt_pin_write(AM_GPIO_LED2, PIN_LOW);
+
+    else if(LEDNum == 3)
+        rt_pin_write(AM_GPIO_LED3, PIN_LOW);
+#endif
+}
+
+/**
+ * @brief Turns off the requested LED.
+ *
+ * @param LEDNum is the LED number for the light to turn off.
+ *
+ * This function turns off a single LED.
+ *
+ * @return None.
+ */
+void rt_hw_led_off(rt_uint8_t LEDNum)
+{
+#ifdef RT_USING_PIN
+    if(LEDNum == 0)
+        rt_pin_write(AM_GPIO_LED0, PIN_HIGH);
+
+    else if(LEDNum == 1)
+        rt_pin_write(AM_GPIO_LED1, PIN_HIGH);
+
+    else if(LEDNum == 2)
+        rt_pin_write(AM_GPIO_LED2, PIN_HIGH);
+
+    else if(LEDNum == 3)
+        rt_pin_write(AM_GPIO_LED3, PIN_HIGH);
+#endif
+}
+
+/**
+ * @brief Configures the necessary pins for an array of LEDs
+ *
+ * @param None.
+ *
+ * This function configures a GPIO to drive an LED in a low-power way.
+ *
+ * @return None.
+ */
+int rt_hw_led_init(void)
+{
+#ifdef RT_USING_PIN
+#if defined(RT_USING_LED0)
+    /* config led */
+    rt_pin_mode(AM_GPIO_LED0, PIN_MODE_OUTPUT);
+
+    /* turns off the led */
+    rt_hw_led_off(0);
+#endif /* RT_USING_LED0 */
+
+#if defined(RT_USING_LED1)
+    /* config led */
+    rt_pin_mode(AM_GPIO_LED1, PIN_MODE_OUTPUT);
+
+    /* turns off the led */
+    rt_hw_led_off(1);
+#endif /* RT_USING_LED1 */
+
+#if defined(RT_USING_LED2)
+    /* config led */
+    rt_pin_mode(AM_GPIO_LED2, PIN_MODE_OUTPUT);
+
+    /* turns off the led */
+    rt_hw_led_off(2);
+#endif /* RT_USING_LED0 */
+
+#if defined(RT_USING_LED3)
+    /* config led */
+    rt_pin_mode(AM_GPIO_LED3, PIN_MODE_OUTPUT);
+
+    /* turns off the led */
+    rt_hw_led_off(3);
+#endif /* RT_USING_LED1 */
+#endif
+    return 0;
+}
+#ifdef RT_USING_COMPONENTS_INIT
+INIT_BOARD_EXPORT(rt_hw_led_init);
+#endif
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+void led(rt_uint32_t led, rt_uint32_t state)
+{
+    /* set led status */
+    switch (state)
+    {
+    case 0:
+        rt_hw_led_off(led);
+        break;
+    case 1:
+        rt_hw_led_on(led);
+        break;
+    default:
+        break;
+    }
+}
+FINSH_FUNCTION_EXPORT(led, turn led (0 - 3) on (1) or off (0).)
+#endif
+
+/*@}*/
diff --git a/bsp/apollo2/board/led.h b/bsp/apollo2/board/led.h
new file mode 100644
index 0000000000..e080e250cb
--- /dev/null
+++ b/bsp/apollo2/board/led.h
@@ -0,0 +1,38 @@
+/*
+ * File      : led.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        the first version
+ */
+ 
+#ifndef __HW_LED_H
+#define __HW_LED_H
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+void rt_hw_led_init(void);
+void rt_hw_led_on(rt_uint8_t LEDNum);
+void rt_hw_led_off(rt_uint8_t LEDNum);
+
+#endif // __HW_LED_H
diff --git a/bsp/apollo2/board/uart.c b/bsp/apollo2/board/uart.c
new file mode 100644
index 0000000000..3a9242ab55
--- /dev/null
+++ b/bsp/apollo2/board/uart.c
@@ -0,0 +1,422 @@
+/*
+ * File      : uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-15     Haley        the first version
+ */
+ 
+#include <rtdevice.h>
+#include "am_mcu_apollo.h"
+#include "board.h"
+
+/* USART0 */
+#define AM_UART0_INST         0
+
+#define UART0_GPIO_RX         2
+#define UART0_GPIO_CFG_RX     AM_HAL_PIN_2_UART0RX
+#define UART0_GPIO_TX         1
+#define UART0_GPIO_CFG_TX     AM_HAL_PIN_1_UART0TX
+
+/* USART1 */
+#define AM_UART1_INST         1
+
+#define UART1_GPIO_RX         9
+#define UART1_GPIO_CFG_RX     AM_HAL_PIN_9_UART1RX
+#define UART1_GPIO_TX         8
+#define UART1_GPIO_CFG_TX     AM_HAL_PIN_8_UART1TX
+
+/* AM uart driver */
+struct am_uart
+{
+    uint32_t uart_device;
+    uint32_t uart_interrupt;
+};
+
+/**
+ * @brief UART configuration settings
+ *
+ */
+am_hal_uart_config_t g_sUartConfig =
+{
+    115200, // ui32BaudRate
+    AM_HAL_UART_DATA_BITS_8, // ui32DataBits
+    false, // bTwoStopBits
+    AM_HAL_UART_PARITY_NONE, // ui32Parity
+    AM_HAL_UART_FLOW_CTRL_NONE, // ui32FlowCtrl
+};
+
+/**
+ * @brief Enable the UART
+ *
+ * @param Uart driver
+ *
+ * This function is Enable the UART
+ *
+ * @return None.
+ */
+static void rt_hw_uart_enable(struct am_uart* uart)
+{
+    /* Enable the UART clock */
+    am_hal_uart_clock_enable(uart->uart_device);
+
+    /* Enable the UART */
+    am_hal_uart_enable(uart->uart_device);
+
+#if defined(RT_USING_UART0)
+    /* Make sure the UART RX and TX pins are enabled */
+    am_hal_gpio_pin_config(UART0_GPIO_TX, UART0_GPIO_CFG_TX);
+    am_hal_gpio_pin_config(UART0_GPIO_RX, UART0_GPIO_CFG_RX | AM_HAL_GPIO_PULL12K);
+#endif /* RT_USING_UART0 */
+
+#if defined(RT_USING_UART1)
+    /* Make sure the UART RX and TX pins are enabled */
+    am_hal_gpio_pin_config(UART1_GPIO_TX, UART1_GPIO_CFG_TX);
+    am_hal_gpio_pin_config(UART1_GPIO_RX, UART1_GPIO_CFG_RX | AM_HAL_GPIO_PULL12K);
+#endif /* RT_USING_UART1 */
+}
+
+/**
+ * @brief Disable the UART
+ *
+ * @param Uart driver
+ *
+ * This function is Disable the UART
+ *
+ * @return None.
+ */
+static void rt_hw_uart_disable(struct am_uart* uart)
+{
+    /* Clear all interrupts before sleeping as having a pending UART interrupt burns power */
+    am_hal_uart_int_clear(uart->uart_device, 0xFFFFFFFF);
+
+    /* Disable the UART */
+    am_hal_uart_disable(uart->uart_device);
+
+#if defined(RT_USING_UART0)
+    /* Disable the UART pins */
+    am_hal_gpio_pin_config(UART0_GPIO_TX, AM_HAL_PIN_DISABLE);
+    am_hal_gpio_pin_config(UART0_GPIO_RX, AM_HAL_PIN_DISABLE);
+#endif /* RT_USING_UART0 */
+
+#if defined(RT_USING_UART1)
+    /* Disable the UART pins */
+    am_hal_gpio_pin_config(UART1_GPIO_TX, AM_HAL_PIN_DISABLE);
+    am_hal_gpio_pin_config(UART1_GPIO_RX, AM_HAL_PIN_DISABLE);
+#endif /* RT_USING_UART1 */
+
+    /* Disable the UART clock */
+    am_hal_uart_clock_disable(uart->uart_device);
+}
+
+/**
+ * @brief UART-based string print function.
+ *
+ * @param Send buff
+ *
+ * This function is used for printing a string via the UART, which for some
+ * MCU devices may be multi-module.
+ *
+ * @return None.
+ */
+void rt_hw_uart_send_string(char *pcString)
+{
+    am_hal_uart_string_transmit_polled(AM_UART0_INST, pcString);
+
+    /* Wait until busy bit clears to make sure UART fully transmitted last byte */
+    while ( am_hal_uart_flags_get(AM_UART0_INST) & AM_HAL_UART_FR_BUSY );
+}
+
+static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct am_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = (struct am_uart *)serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    /* Get the configure */
+    g_sUartConfig.ui32BaudRate = cfg->baud_rate;
+    g_sUartConfig.ui32DataBits = cfg->data_bits;
+
+    if (cfg->stop_bits == STOP_BITS_1)
+        g_sUartConfig.bTwoStopBits = false;
+    else if (cfg->stop_bits == STOP_BITS_2)
+        g_sUartConfig.bTwoStopBits = true;
+
+    g_sUartConfig.ui32Parity = cfg->parity;
+    g_sUartConfig.ui32FlowCtrl = AM_HAL_UART_PARITY_NONE;
+
+    /* Configure the UART */
+    am_hal_uart_config(uart->uart_device, &g_sUartConfig);
+
+    /* Enable the UART */
+    am_hal_uart_enable(uart->uart_device);
+
+    return RT_EOK;
+}
+
+static rt_err_t am_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct am_uart* uart;
+    //rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct am_uart *)serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    switch (cmd)
+    {
+        /* disable interrupt */
+        case RT_DEVICE_CTRL_CLR_INT:
+            rt_hw_uart_disable(uart);
+            break;
+        /* enable interrupt */
+        case RT_DEVICE_CTRL_SET_INT:
+            rt_hw_uart_enable(uart);
+            break;
+        /* UART config */
+        case RT_DEVICE_CTRL_CONFIG :
+            break;
+    }
+
+    return RT_EOK;
+}
+
+static int am_putc(struct rt_serial_device *serial, char c)
+{
+    struct am_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct am_uart *)serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    am_hal_uart_char_transmit_polled(uart->uart_device, c);
+
+    return 1;
+}
+
+static int am_getc(struct rt_serial_device *serial)
+{
+    char c;
+    int ch;
+    struct am_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct am_uart *)serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    ch = -1;
+    if ((am_hal_uart_flags_get(uart->uart_device) & AM_HAL_UART_FR_RX_EMPTY) == 0)
+    {
+        am_hal_uart_char_receive_polled(uart->uart_device, &c);
+        ch = c & 0xff;
+    }
+
+    return ch;
+}
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+    uint32_t status;
+    struct am_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct am_uart *) serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    /* Read the interrupt status */
+    status = am_hal_uart_int_status_get(uart->uart_device, false);
+
+    //rt_kprintf("status is %d\r\n", status);
+
+    /* Clear the UART interrupt */
+    am_hal_uart_int_clear(uart->uart_device, status);
+
+    if (status & (AM_HAL_UART_INT_RX_TMOUT))
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    if (status & AM_HAL_UART_INT_RX)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    if (status & AM_HAL_UART_INT_TX)
+    {
+        // rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
+    }
+}
+
+static const struct rt_uart_ops am_uart_ops =
+{
+    am_configure,
+    am_control,
+    am_putc,
+    am_getc,
+};
+
+#if defined(RT_USING_UART0)
+/* UART0 device driver structure */
+struct am_uart uart0 =
+{
+    AM_UART0_INST,
+    AM_HAL_INTERRUPT_UART0
+};
+static struct rt_serial_device serial0;
+
+void am_uart0_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial0);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_USING_UART0 */
+
+#if defined(RT_USING_UART1)
+/* UART1 device driver structure */
+struct am_uart uart1 =
+{
+    AM_UART1_INST,
+    AM_HAL_INTERRUPT_UART1
+};
+static struct rt_serial_device serial1;
+
+void am_uart1_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial1);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_USING_UART1 */
+
+static void GPIO_Configuration(void)
+{
+#if defined(RT_USING_UART0)
+    /* Make sure the UART RX and TX pins are enabled */
+    am_hal_gpio_pin_config(UART0_GPIO_TX, UART0_GPIO_CFG_TX);
+    am_hal_gpio_pin_config(UART0_GPIO_RX, UART0_GPIO_CFG_RX | AM_HAL_GPIO_PULL12K);
+#endif /* RT_USING_UART0 */
+
+#if defined(RT_USING_UART1)
+    /* Make sure the UART RX and TX pins are enabled */
+    am_hal_gpio_pin_config(UART1_GPIO_TX, UART1_GPIO_CFG_TX);
+    am_hal_gpio_pin_config(UART1_GPIO_RX, UART1_GPIO_CFG_RX | AM_HAL_GPIO_PULL12K);
+#endif /* RT_USING_UART1 */
+}
+
+static void RCC_Configuration(struct am_uart* uart)
+{
+    /* Power on the selected UART */
+    am_hal_uart_pwrctrl_enable(uart->uart_device);
+
+    /* Start the UART interface, apply the desired configuration settings */
+    am_hal_uart_clock_enable(uart->uart_device);
+
+    /* Disable the UART before configuring it */
+    am_hal_uart_disable(uart->uart_device);
+
+    /* Configure the UART */
+    am_hal_uart_config(uart->uart_device, &g_sUartConfig);
+
+    /* Enable the UART */
+    am_hal_uart_enable(uart->uart_device);
+
+    /* Enable the UART FIFO */
+    am_hal_uart_fifo_config(uart->uart_device, AM_HAL_UART_TX_FIFO_1_2 | AM_HAL_UART_RX_FIFO_1_2);
+}
+
+static void NVIC_Configuration(struct am_uart* uart)
+{
+    /* Enable interrupts */
+    am_hal_uart_int_enable(uart->uart_device, AM_HAL_UART_INT_RX_TMOUT | AM_HAL_UART_INT_RX);
+
+    /* Enable the uart interrupt in the NVIC */
+    am_hal_interrupt_enable(uart->uart_interrupt);
+}
+
+/**
+ * @brief Initialize the UART
+ *
+ * This function initialize the UART
+ *
+ * @return None.
+ */
+void rt_hw_uart_init(void)
+{
+    struct am_uart* uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    GPIO_Configuration();
+
+#if defined(RT_USING_UART0)
+    uart = &uart0;
+    config.baud_rate = BAUD_RATE_115200;
+
+    RCC_Configuration(uart);
+    NVIC_Configuration(uart);
+
+    serial0.ops    = &am_uart_ops;
+    serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+                          RT_DEVICE_FLAG_INT_TX, uart);
+#endif /* RT_USING_UART0 */
+
+#if defined(RT_USING_UART1)
+    uart = &uart1;
+    config.baud_rate = BAUD_RATE_115200;
+
+    RCC_Configuration(uart);
+    NVIC_Configuration(uart);
+
+    serial1.ops    = &am_uart_ops;
+    serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+                          RT_DEVICE_FLAG_INT_TX, uart);
+#endif /* RT_USING_UART1 */
+}
+
+/*@}*/
diff --git a/bsp/apollo2/board/uart.h b/bsp/apollo2/board/uart.h
new file mode 100644
index 0000000000..49fff8a9f7
--- /dev/null
+++ b/bsp/apollo2/board/uart.h
@@ -0,0 +1,30 @@
+/*
+ * File      : uart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        the first version
+ */
+ 
+#ifndef __UART_H_
+#define __UART_H_
+
+void rt_hw_uart_init(void);
+
+#endif // __UART_H_
diff --git a/bsp/apollo2/libraries/SConscript b/bsp/apollo2/libraries/SConscript
new file mode 100644
index 0000000000..744d8d7821
--- /dev/null
+++ b/bsp/apollo2/libraries/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/apollo2/libraries/drivers/SConscript b/bsp/apollo2/libraries/drivers/SConscript
new file mode 100644
index 0000000000..c190a8d8be
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/SConscript
@@ -0,0 +1,29 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Split("""
+hal/am_hal_clkgen.c
+hal/am_hal_debug.c
+hal/am_hal_cachectrl.c
+hal/am_hal_pwrctrl.c
+hal/am_hal_sysctrl.c
+hal/am_hal_stimer.c
+hal/am_hal_ctimer.c
+hal/am_hal_rtc.c
+hal/am_hal_interrupt.c
+hal/am_hal_queue.c
+hal/am_hal_vcomp.c
+hal/am_hal_flash.c
+hal/am_hal_gpio.c
+hal/am_hal_uart.c
+""")
+
+path = [cwd]
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/apollo2/libraries/drivers/am_mcu_apollo.h b/bsp/apollo2/libraries/drivers/am_mcu_apollo.h
new file mode 100644
index 0000000000..bf46aa61bb
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/am_mcu_apollo.h
@@ -0,0 +1,132 @@
+//*****************************************************************************
+//
+//! @file
+//!
+//! @brief Top Include for Apollo2 class devices.
+//!
+//! This file provides all the includes necessary for an apollo device.
+//!
+//! @addtogroup hal Hardware Abstraction Layer (HAL)
+//
+//! @defgroup apollo2hal HAL for Apollo2
+//! @ingroup hal
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_MCU_APOLLO_H
+#define AM_MCU_APOLLO_H
+
+//*****************************************************************************
+//
+// C99
+//
+//*****************************************************************************
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#ifdef __IAR_SYSTEMS_ICC__
+#include "intrinsics.h"     // __CLZ() and other intrinsics
+#endif
+
+//*****************************************************************************
+//
+// Registers
+//
+//*****************************************************************************
+#include "regs/am_reg_base_addresses.h"
+
+#include "regs/am_reg_macros.h"
+
+#include "regs/am_reg_adc.h"
+#include "regs/am_reg_cachectrl.h"
+#include "regs/am_reg_clkgen.h"
+#include "regs/am_reg_ctimer.h"
+#include "regs/am_reg_gpio.h"
+#include "regs/am_reg_iomstr.h"
+#include "regs/am_reg_ioslave.h"
+#include "regs/am_reg_itm.h"
+#include "regs/am_reg_jedec.h"
+#include "regs/am_reg_mcuctrl.h"
+#include "regs/am_reg_nvic.h"
+#include "regs/am_reg_pdm.h"
+#include "regs/am_reg_pwrctrl.h"
+#include "regs/am_reg_rstgen.h"
+#include "regs/am_reg_rtc.h"
+#include "regs/am_reg_sysctrl.h"
+#include "regs/am_reg_systick.h"
+#include "regs/am_reg_tpiu.h"
+#include "regs/am_reg_uart.h"
+#include "regs/am_reg_vcomp.h"
+#include "regs/am_reg_wdt.h"
+
+//*****************************************************************************
+//
+// HAL
+//
+//*****************************************************************************
+#include "hal/am_hal_adc.h"
+#include "hal/am_hal_cachectrl.h"
+#include "hal/am_hal_clkgen.h"
+#include "hal/am_hal_ctimer.h"
+#include "hal/am_hal_debug.h"
+#include "hal/am_hal_flash.h"
+#include "hal/am_hal_global.h"
+#include "hal/am_hal_gpio.h"
+#include "hal/am_hal_i2c_bit_bang.h"
+#include "hal/am_hal_interrupt.h"
+#include "hal/am_hal_iom.h"
+#include "hal/am_hal_ios.h"
+#include "hal/am_hal_itm.h"
+#include "hal/am_hal_mcuctrl.h"
+#include "hal/am_hal_otp.h"
+#include "hal/am_hal_pdm.h"
+#include "hal/am_hal_pin.h"
+#include "hal/am_hal_pwrctrl.h"
+#include "hal/am_hal_queue.h"
+#include "hal/am_hal_reset.h"
+#include "hal/am_hal_rtc.h"
+#include "hal/am_hal_stimer.h"
+#include "hal/am_hal_sysctrl.h"
+#include "hal/am_hal_systick.h"
+#include "hal/am_hal_tpiu.h"
+#include "hal/am_hal_uart.h"
+#include "hal/am_hal_vcomp.h"
+#include "hal/am_hal_wdt.h"
+
+#endif // AM_MCU_APOLLO_H
+
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c
new file mode 100644
index 0000000000..957408d0e5
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c
@@ -0,0 +1,553 @@
+//*****************************************************************************
+//
+//  am_hal_adc.c
+//! @file
+//!
+//! @brief Functions for interfacing with the Analog to Digital Converter.
+//!
+//! @addtogroup adc2 Analog-to-Digital Converter (ADC)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Private SRAM view of temperature trims.
+//!
+//! This static SRAM union is private to the ADC HAL functions.
+//
+//*****************************************************************************
+static union
+{
+    //! These trim values are loaded as uint32_t values.
+    struct
+    {
+              //! Temperature of the package test head (in degrees Kelvin)
+              uint32_t ui32CalibrationTemperature;
+
+              //! Voltage corresponding to temperature measured on test head.
+              uint32_t ui32CalibrationVoltage;
+
+              //! ADC offset voltage measured on the package test head.
+              uint32_t ui32CalibrationOffset;
+
+              //! Flag if default (guess) or measured.
+              bool bMeasured;
+    } ui32;
+    //! These trim values are accessed as floats when used in temp calculations.
+    struct
+    {
+              //! Temperature of the package test head in degrees Kelvin
+              float    fCalibrationTemperature;
+
+              //! Voltage corresponding to temperature measured on test head.
+              float    fCalibrationVoltage;
+
+              //! ADC offset voltage measured on the package test head.
+              float    fCalibrationOffset;
+
+              //! Flag if default (guess) or measured.
+              float fMeasuredFlag;
+    } flt;
+} priv_temp_trims;
+
+//*****************************************************************************
+//
+//! @brief Configure the ADC.
+//!
+//! @param psConfig - pointer to the configuration structure for the ADC.
+//!
+//! This function may be used to perform the initial setup of the ADC based on
+//! setting found in a configuration structure.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_config(am_hal_adc_config_t *psConfig)
+{
+    //
+    // Set general ADC configuration parameters.
+    //
+    AM_REG(ADC, CFG) = (psConfig->ui32Clock |
+                        psConfig->ui32TriggerConfig |
+                        psConfig->ui32Reference |
+                        psConfig->ui32ClockMode |
+                        psConfig->ui32PowerMode |
+                        psConfig->ui32Repeat |
+                        AM_REG_ADC_CFG_ADCEN(1));
+
+    //
+    // Grab the temperature trims.
+    //
+    priv_temp_trims.ui32.ui32CalibrationTemperature =
+                  am_hal_flash_load_ui32(AM_HAL_ADC_CALIB_TEMP_ADDR);
+    priv_temp_trims.ui32.ui32CalibrationVoltage     =
+                  am_hal_flash_load_ui32(AM_HAL_ADC_CALIB_AMBIENT_ADDR);
+    priv_temp_trims.ui32.ui32CalibrationOffset      =
+                  am_hal_flash_load_ui32(AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR);
+
+    if ( (priv_temp_trims.ui32.ui32CalibrationTemperature == 0xffffffff)    ||
+         (priv_temp_trims.ui32.ui32CalibrationVoltage     == 0xffffffff)    ||
+         (priv_temp_trims.ui32.ui32CalibrationOffset      == 0xffffffff) )
+    {
+        //
+        // Since the device has not been calibrated on the tester, we'll load
+        // default calibration values.  These default values should result
+        // in worst-case temperature measurements of +-6 degress C.
+        //
+        priv_temp_trims.flt.fCalibrationTemperature = AM_HAL_ADC_CALIB_TEMP_DEFAULT;
+        priv_temp_trims.flt.fCalibrationVoltage     = AM_HAL_ADC_CALIB_AMBIENT_DEFAULT;
+        priv_temp_trims.flt.fCalibrationOffset      = AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT;
+        priv_temp_trims.ui32.bMeasured = false;
+    }
+    else
+    {
+        priv_temp_trims.ui32.bMeasured = true;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Get the temperature trim parameters after configuring the ADC.
+//!
+//! @param pfTemp - pointer to a location to store the calibration temperature.
+//! @param pfVoltage - pointer to a location to store the calibration voltage.
+//! @param pfOffsetV - pointer to a location to store the calibration offset.
+//!
+//! This function may be used to access the actual temperature sensor trim
+//! values from the private structure.
+//!
+//! WARNING: only call this after the ADC has been configured with
+//!          am_hal_adc_config.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_temp_trims_get(float * pfTemp, float * pfVoltage, float * pfOffsetV)
+{
+    //
+    // Return trim temperature as a float, if you can.
+    //
+    if ( pfTemp != NULL )
+    {
+        *pfTemp = priv_temp_trims.flt.fCalibrationTemperature;
+    }
+
+    //
+    // Return trim voltage as a float, if you can.
+    //
+    if ( pfVoltage != NULL )
+    {
+        *pfVoltage = priv_temp_trims.flt.fCalibrationVoltage;
+    }
+
+    //
+    // Return trim ADC offset voltage as a float, if you can.
+    //
+    if ( pfOffsetV != NULL )
+    {
+        *pfOffsetV = priv_temp_trims.flt.fCalibrationOffset;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Set the ADC window parameters.
+//!
+//! @param ui32Upper - the upper limit for the ADC window.
+//! @param ui32Upper - the lower limit for the ADC window.
+//!
+//! This function may be used to change the ADC window parameters. Please note
+//! that the upper and lower limits are only 16-bits wide in the ADC hardware.
+//! This function will ignore the upper 16 bits of these arguments.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_window_set(uint32_t ui32Upper, uint32_t ui32Lower)
+{
+    //
+    // Set the window limits for the ADC.
+    //
+     AM_BFW(ADC, WULIM, ULIM, ui32Upper);
+     AM_BFW(ADC, WLLIM, LLIM, ui32Lower);
+}
+
+//*****************************************************************************
+//
+//! @brief Configure a single ADC slot.
+//!
+//! @param ui32SlotNumber - the number of the ADC slot to be configured.
+//! @param ui32SlotConfig - contains slot-specific options.
+//!
+//! This function may be used to configure the settings for an individual ADC
+//! slot. The parameter \b ui32SlotConfig should be the logical 'OR' of a slot
+//! average macro, a slot hold-time macro, a slot channel macro, and
+//! optionally, the slot window enable macro.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_slot_config(uint32_t ui32SlotNumber, uint32_t ui32SlotConfig)
+{
+    uint32_t ui32RegOffset;
+
+    //
+    // Make sure we're accessing a real slot.
+    //
+    am_hal_debug_assert_msg((ui32SlotNumber & 0xFFFFFFFF0) == 0,
+                            "Trying to configure an ADC slot that doesn't exist.");
+
+    //
+    // Locate the correct register for this ADC slot.
+    //
+    ui32RegOffset = (AM_REG_ADCn(0) + AM_REG_ADC_SL0CFG_O + (4 * ui32SlotNumber));
+
+    //
+    // Write the register with the caller's configuration value.
+    //
+    AM_REGVAL(ui32RegOffset) = ui32SlotConfig;
+}
+
+//*****************************************************************************
+//
+//! @brief Peek at the next fifo entry.
+//!
+//! This function reads the oldest value in the ADC sample fifo but doesn't
+//! actually advance the fifo to the next entry. This function is useful when
+//! you need information from the fifo but you don't want to also empty the
+//! fifo. This could be helpful if you want to check the FIFO depth without
+//! pulling any data out.
+//!
+//! The value returned by this function is the raw 32-bit value provided by the
+//! ADC hardware. In order to interpret this value, you will need to use one of
+//! the following macros.
+//!
+//! @return 32-bit FIFO entry.
+//!
+//
+//*****************************************************************************
+uint32_t
+am_hal_adc_fifo_peek(void)
+{
+    uint32_t ui32FIFOValue;
+
+    //
+    // Grab a value from the ADC FIFO.
+    //
+    ui32FIFOValue = AM_REG(ADC, FIFO);
+
+    //
+    // Return FIFO entry.
+    //
+    return ui32FIFOValue;
+}
+
+//*****************************************************************************
+//
+//! @brief
+//!
+//! This function reads the oldest value in the ADC fifo and then pops the
+//! fifo. Use this function when you actually want to pull data out of the
+//! fifo.
+//!
+//! @return 32-bit FIFO entry.
+//!
+//
+//*****************************************************************************
+uint32_t
+am_hal_adc_fifo_pop(void)
+{
+    uint32_t ui32FIFOValue;
+
+    //
+    // Grab a value from the ADC FIFO.
+    //
+    ui32FIFOValue = AM_REG(ADC, FIFO);
+
+    //
+    // Pop the FIFO.
+    //
+    AM_REG(ADC, FIFO) = 0;
+
+    //
+    // Return FIFO valid bits.
+    //
+    return ui32FIFOValue;
+}
+
+//*****************************************************************************
+//
+//! @brief Issue Software Trigger to the ADC.
+//!
+//! This function issues the software trigger to the ADC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_trigger(void)
+{
+    //
+    // Write to the Software trigger register in the ADC.
+    //
+    AM_REG(ADC, SWT) = 0x37;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the ADC.
+//!
+//! Use this function to enable the ADC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_enable(void)
+{
+    //
+    // Enable the ADC.
+    //
+    AM_BFW(ADC, CFG, ADCEN, 0x1);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the ADC.
+//!
+//! Use this function to disable the ADC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_disable(void)
+{
+    //
+    // Disable the ADC.
+    //
+    AM_BFW(ADC, CFG, ADCEN, 0x0);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable selected ADC Interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_adc.h.
+//!
+//! Use this function to enable the ADC interrupts.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_int_enable(uint32_t ui32Interrupt)
+{
+    //
+    // Enable the interrupts.
+    //
+    AM_REG(ADC, INTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return enabled ADC Interrupts.
+//!
+//! Use this function to get all enabled ADC interrupts.
+//!
+//! @return enabled ADC Interrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_adc_int_enable_get(void)
+{
+    //
+    // Return enabled interrupts.
+    //
+    return AM_REG(ADC, INTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable selected ADC Interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_adc.h.
+//!
+//! Use this function to disable the ADC interrupts.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_int_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Disable the interrupts.
+    //
+    AM_REG(ADC, INTEN) &= ~ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Clear selected ADC Interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_adc.h.
+//!
+//! Use this function to clear the ADC interrupts.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Clear the interrupts.
+    //
+    AM_REG(ADC, INTCLR) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Set selected ADC Interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_adc.h.
+//!
+//! Use this function to set the ADC interrupts.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_adc_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Set the interrupts.
+    //
+    AM_REG(ADC, INTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return either enabled or raw selected ADC interrupt status.
+//!
+//! @param bEnabledOnly - return the status of only the enabled interrupts.
+//!
+//! Use this function to get the ADC interrupt status.
+//!
+//! @return enabled or raw ADC interrupt status.
+//
+//*****************************************************************************
+uint32_t
+am_hal_adc_int_status_get(bool bEnabledOnly)
+{
+    //
+    // Return the status.
+    //
+    if (bEnabledOnly)
+    {
+        uint32_t u32RetVal = AM_REG(ADC, INTEN);
+        u32RetVal &= AM_REG(ADC, INTSTAT);
+        return u32RetVal;
+    }
+    else
+    {
+        return AM_REG(ADC, INTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Return temperature in degrees C of supplied voltage.
+//!
+//! @param fVoltage - return the temperature corresponding to this voltage.
+//!
+//! Use this function to convert volts from the temperature sensor into degrees
+//! C.  Caller converts ADC binary code to volts based on reference used.
+//! This routine looks up the trim parameters and returns corrected temperature.
+//!
+//! The computation is based on a line running through 0 degrees K.
+//! We find the slope from the trimmed temperature calibration point.
+//!
+//!
+//! @return the temperature in degrees C.
+//
+//*****************************************************************************
+float
+am_hal_adc_volts_to_celsius(float fVoltage)
+{
+    float fTemp;
+
+    //
+    // Get calibration temperature from trimmed values & convert to degrees K.
+    //
+    float fCalibration_temp = priv_temp_trims.flt.fCalibrationTemperature;
+
+    //
+    // Get remaining trimmed values.
+    //
+    float fCalibration_voltage = priv_temp_trims.flt.fCalibrationVoltage;
+    float fCalibration_offset  = priv_temp_trims.flt.fCalibrationOffset;
+
+    //
+    // Compute the temperature.
+    //
+    fTemp  = fCalibration_temp;
+    fTemp /= (fCalibration_voltage - fCalibration_offset);
+    fTemp *= (fVoltage - fCalibration_offset);
+
+    //
+    // Give it back to the caller in Celsius.
+    //
+    return fTemp - 273.15f;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h
new file mode 100644
index 0000000000..86b48b162c
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h
@@ -0,0 +1,348 @@
+//*****************************************************************************
+//
+//  am_hal_adc.h
+//! @file
+//!
+//! @brief Functions for interfacing with the Analog to Digital Converter
+//!
+//! @addtogroup adc2 Analog-to-Digital Converter (ADC)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_ADC_H
+#define AM_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name Clock Selection
+//! @brief These macros may be used to set the ADC module's clock source.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_CLOCK_OFF                AM_REG_ADC_CFG_CLKSEL_OFF
+#define AM_HAL_ADC_CLOCK_HFRC               AM_REG_ADC_CFG_CLKSEL_HFRC
+#define AM_HAL_ADC_CLOCK_DIV2               AM_REG_ADC_CFG_CLKSEL_HFRC_DIV2
+//! @}
+
+//*****************************************************************************
+//
+//! @name Trigger Settings
+//! @brief ADC trigger setting macros.
+//!
+//! These macros alter the ADC's trigger source and trigger polarity. Note that
+//! the external trigger setting needs to be ORed with a POS or NEG option to
+//! define the desired trigger polarity.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_TRIGGER_SOFT             AM_REG_ADC_CFG_TRIGSEL_SWT
+#define AM_HAL_ADC_TRIGGER_VCOMP            AM_REG_ADC_CFG_TRIGSEL_VCOMP
+#define AM_HAL_ADC_TRIGGER_EXT0             AM_REG_ADC_CFG_TRIGSEL_EXT0
+#define AM_HAL_ADC_TRIGGER_EXT1             AM_REG_ADC_CFG_TRIGSEL_EXT1
+#define AM_HAL_ADC_TRIGGER_EXT2             AM_REG_ADC_CFG_TRIGSEL_EXT2
+#define AM_HAL_ADC_TRIGGER_EXT3             AM_REG_ADC_CFG_TRIGSEL_EXT3
+#define AM_HAL_ADC_TRIGGER_FALL             AM_REG_ADC_CFG_TRIGPOL_FALLING_EDGE
+#define AM_HAL_ADC_TRIGGER_RISE             AM_REG_ADC_CFG_TRIGPOL_RISING_EDGE
+//! @}
+
+//*****************************************************************************
+//
+//! @name Reference Settings
+//! @brief ADC reference voltage setting macros.
+//!
+//! These macros control the ADC reference voltage source.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_REF_EXT_2P0              AM_REG_ADC_CFG_REFSEL_EXT2P0
+#define AM_HAL_ADC_REF_EXT_1P5              AM_REG_ADC_CFG_REFSEL_EXT1P5
+#define AM_HAL_ADC_REF_INT_2P0              AM_REG_ADC_CFG_REFSEL_INT2P0
+#define AM_HAL_ADC_REF_INT_1P5              AM_REG_ADC_CFG_REFSEL_INT1P5
+//! @}
+
+//*****************************************************************************
+//
+//! @name Clock Mode
+//! @brief ADC clock mode settings
+//!
+//! These macros determine whether the ADC shuts down its clock between
+//! samples. Shutting down the clock will reduce power consumption, but
+//! increase latency. This setting is only valid for LPMODE 0. For other modes,
+//! it will be ignored.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_CK_LOW_POWER             AM_REG_ADC_CFG_CKMODE_LPCKMODE
+#define AM_HAL_ADC_CK_LOW_LATENCY           AM_REG_ADC_CFG_CKMODE_LLCKMODE
+//! @}
+
+//*****************************************************************************
+//
+//! @name Low Power Mode
+//! @brief ADC power conservation settings.
+//!
+//! These macros select the power state to enter between active scans. Each low
+//! power mode has its own set of timing constraints. Please see the datasheet
+//! for additional timing information on each power mode.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_LPMODE_0                 AM_REG_ADC_CFG_LPMODE_MODE0
+#define AM_HAL_ADC_LPMODE_1                 AM_REG_ADC_CFG_LPMODE_MODE1
+//! @}
+
+//*****************************************************************************
+//
+//! @name Repeat Mode
+//! @brief Enable repeating scan mode.
+//!
+//! Use this macro to enable repeating scans using timer 3.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_REPEAT                   AM_REG_ADC_CFG_RPTEN(1)
+#define AM_HAL_ADC_NO_REPEAT                AM_REG_ADC_CFG_RPTEN(0)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Slot configuration
+//! @brief Slot configuration macros
+//!
+//! These macros may be used to configure an individual ADC slot.
+//! @{
+//
+//*****************************************************************************
+
+// Set number of samples to average.
+#define AM_HAL_ADC_SLOT_AVG_1               AM_REG_ADC_SL0CFG_ADSEL0(0)
+#define AM_HAL_ADC_SLOT_AVG_2               AM_REG_ADC_SL0CFG_ADSEL0(1)
+#define AM_HAL_ADC_SLOT_AVG_4               AM_REG_ADC_SL0CFG_ADSEL0(2)
+#define AM_HAL_ADC_SLOT_AVG_8               AM_REG_ADC_SL0CFG_ADSEL0(3)
+#define AM_HAL_ADC_SLOT_AVG_16              AM_REG_ADC_SL0CFG_ADSEL0(4)
+#define AM_HAL_ADC_SLOT_AVG_32              AM_REG_ADC_SL0CFG_ADSEL0(5)
+#define AM_HAL_ADC_SLOT_AVG_64              AM_REG_ADC_SL0CFG_ADSEL0(6)
+#define AM_HAL_ADC_SLOT_AVG_128             AM_REG_ADC_SL0CFG_ADSEL0(7)
+
+// Set slot precision mode.
+#define AM_HAL_ADC_SLOT_14BIT               AM_REG_ADC_SL0CFG_PRMODE0_P14B
+#define AM_HAL_ADC_SLOT_12BIT               AM_REG_ADC_SL0CFG_PRMODE0_P14B
+#define AM_HAL_ADC_SLOT_10BIT               AM_REG_ADC_SL0CFG_PRMODE0_P14B
+#define AM_HAL_ADC_SLOT_8BIT                AM_REG_ADC_SL0CFG_PRMODE0_P14B
+
+// Select a channel by number.
+#define AM_HAL_ADC_SLOT_CHANNEL(n)          AM_REG_ADC_SL0CFG_CHSEL0(n)
+
+// Single-ended channels
+#define AM_HAL_ADC_SLOT_CHSEL_SE0           AM_REG_ADC_SL0CFG_CHSEL0_SE0
+#define AM_HAL_ADC_SLOT_CHSEL_SE1           AM_REG_ADC_SL0CFG_CHSEL0_SE1
+#define AM_HAL_ADC_SLOT_CHSEL_SE2           AM_REG_ADC_SL0CFG_CHSEL0_SE2
+#define AM_HAL_ADC_SLOT_CHSEL_SE3           AM_REG_ADC_SL0CFG_CHSEL0_SE3
+#define AM_HAL_ADC_SLOT_CHSEL_SE4           AM_REG_ADC_SL0CFG_CHSEL0_SE4
+#define AM_HAL_ADC_SLOT_CHSEL_SE5           AM_REG_ADC_SL0CFG_CHSEL0_SE5
+#define AM_HAL_ADC_SLOT_CHSEL_SE6           AM_REG_ADC_SL0CFG_CHSEL0_SE6
+#define AM_HAL_ADC_SLOT_CHSEL_SE7           AM_REG_ADC_SL0CFG_CHSEL0_SE7
+#define AM_HAL_ADC_SLOT_CHSEL_SE8           AM_REG_ADC_SL0CFG_CHSEL0_SE8
+#define AM_HAL_ADC_SLOT_CHSEL_SE9           AM_REG_ADC_SL0CFG_CHSEL0_SE9
+
+// Differential channels.
+#define AM_HAL_ADC_SLOT_CHSEL_DF0           AM_REG_ADC_SL0CFG_CHSEL0_DF0
+#define AM_HAL_ADC_SLOT_CHSEL_DF1           AM_REG_ADC_SL0CFG_CHSEL0_DF1
+
+// Miscellaneous other signals.
+#define AM_HAL_ADC_SLOT_CHSEL_TEMP          AM_REG_ADC_SL0CFG_CHSEL0_TEMP
+#define AM_HAL_ADC_SLOT_CHSEL_VSS           AM_REG_ADC_SL0CFG_CHSEL0_VSS
+#define AM_HAL_ADC_SLOT_CHSEL_VBATT         AM_REG_ADC_SL0CFG_CHSEL0_BATT
+
+// Window enable.
+#define AM_HAL_ADC_SLOT_WINDOW_EN           AM_REG_ADC_SL0CFG_WCEN0(1)
+
+// Enable the slot.
+#define AM_HAL_ADC_SLOT_ENABLE              AM_REG_ADC_SL0CFG_SLEN0(1)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Interrupt Status Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to enable an individual ADC interrupt cause.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_INT_WCINC              AM_REG_ADC_INTEN_WCINC(1)
+#define AM_HAL_ADC_INT_WCEXC              AM_REG_ADC_INTEN_WCEXC(1)
+#define AM_HAL_ADC_INT_FIFOOVR2           AM_REG_ADC_INTEN_FIFOOVR2(1)
+#define AM_HAL_ADC_INT_FIFOOVR1           AM_REG_ADC_INTEN_FIFOOVR1(1)
+#define AM_HAL_ADC_INT_SCNCMP             AM_REG_ADC_INTEN_SCNCMP(1)
+#define AM_HAL_ADC_INT_CNVCMP             AM_REG_ADC_INTEN_CNVCMP(1)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Temperature Trim Value Locations
+//! @brief Temperature calibration cofficients are stored in readable space.
+//!
+//! These macros are used to access the temperature trim values in readable
+//! space.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_CALIB_TEMP_ADDR          (0x50023010)
+#define AM_HAL_ADC_CALIB_AMBIENT_ADDR       (0x50023014)
+#define AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR    (0x50023018)
+
+//
+// Default coefficients (used when trims not provided):
+//  TEMP_DEFAULT    = Temperature in deg K (e.g. 299.5 - 273.15 = 26.35)
+//  AMBIENT_DEFAULT = Voltage measurement at default temperature.
+//  OFFSET_DEFAULT  = Default ADC offset at 1v.
+//
+#define AM_HAL_ADC_CALIB_TEMP_DEFAULT       (299.5F)
+#define AM_HAL_ADC_CALIB_AMBIENT_DEFAULT    (1.02809F)
+#define AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT (-0.004281F)
+//! @}
+
+//*****************************************************************************
+//
+//! @brief Configuration structure for the ADC.
+//
+//*****************************************************************************
+typedef struct
+{
+    //! Select the ADC Clock source using one of the clock source macros.
+    uint32_t ui32Clock;
+
+    //! Select the ADC trigger source using a trigger source macro.
+    uint32_t ui32TriggerConfig;
+
+    //! Use a macro to select the ADC reference voltage.
+    uint32_t ui32Reference;
+
+    //! Use a macro to decide whether to disable clocks between samples.
+    uint32_t ui32ClockMode;
+
+    //! Use a macro to select the ADC power mode.
+    uint32_t ui32PowerMode;
+
+    //! Select whether the ADC will re-trigger based on a signal from timer 3.
+    uint32_t ui32Repeat;
+}
+am_hal_adc_config_t;
+
+//*****************************************************************************
+//
+//! @brief ADC Fifo Read macros
+//!
+//! These are helper macros for interpreting FIFO data. Each ADC FIFO entry
+//! contains information about the slot number and the FIFO depth alongside the
+//! current sample. These macros perform the correct masking and shifting to
+//! read those values.
+//!
+//! The SAMPLE and FULL_SAMPLE options refer to the fractional part of averaged
+//! samples. If you are not using hardware averaging or don't need the
+//! fractional part of the ADC sample, you should just use
+//! AM_HAL_ADC_FIFO_SAMPLE.
+//!
+//! If you do need the fractional part, use AM_HAL_ADC_FIFO_FULL_SAMPLE. This
+//! macro will keep six bits of precision past the decimal point. Depending on
+//! the number of averaged samples, anywhere between 1 and 6 of these bits will
+//! be valid. Please consult the datasheet to find out how many bits of data
+//! are valid for your chosen averaging settings.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_FIFO_SAMPLE(value)                                         \
+    ((((value) & AM_REG_ADC_FIFO_DATA_M) >> AM_REG_ADC_FIFO_DATA_S) >> 6)
+
+#define AM_HAL_ADC_FIFO_FULL_SAMPLE(value)                                    \
+    (((value) & AM_REG_ADC_FIFO_DATA_M) >> AM_REG_ADC_FIFO_DATA_S )
+
+#define AM_HAL_ADC_FIFO_SLOT(value)                                           \
+    (((value) & AM_REG_ADC_FIFO_SLOTNUM_M) >> AM_REG_ADC_FIFO_SLOTNUM_S)
+
+#define AM_HAL_ADC_FIFO_COUNT(value)                                          \
+    (((value) & AM_REG_ADC_FIFO_COUNT_M) >> AM_REG_ADC_FIFO_COUNT_S)
+//! @}
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_adc_config(am_hal_adc_config_t *psConfig);
+extern void am_hal_adc_window_set(uint32_t ui32Upper, uint32_t ui32Lower);
+extern void am_hal_adc_slot_config(uint32_t ui32SlotNumber,
+                                   uint32_t ui32SlotConfig);
+
+extern uint32_t am_hal_adc_fifo_peek(void);
+extern uint32_t am_hal_adc_fifo_pop(void);
+
+extern void am_hal_adc_trigger(void);
+extern void am_hal_adc_enable(void);
+extern void am_hal_adc_disable(void);
+extern void am_hal_adc_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_adc_int_enable_get(void);
+extern void am_hal_adc_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_adc_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_adc_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_adc_int_status_get(bool bEnabledOnly);
+extern float am_hal_adc_volts_to_celsius(float fVoltage);
+extern void am_hal_adc_temp_trims_get(float * pfTemp, float * pfVoltage, float * pfOffsetV);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_ADC_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c
new file mode 100644
index 0000000000..26c41a22e3
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c
@@ -0,0 +1,576 @@
+//*****************************************************************************
+//
+//  am_hal_cachectrl.c
+//! @file
+//!
+//! @brief Functions for interfacing with the CACHE controller.
+//!
+//! @addtogroup clkgen2 Clock Generator (CACHE)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Default settings for the cache.
+//
+//*****************************************************************************
+const am_hal_cachectrl_config_t am_hal_cachectrl_defaults =
+{
+    1, // ui32EnableCache
+    0, // ui32LRU
+    0, // ui32EnableNCregions
+    AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512, // ui32Config
+    0, // ui32SerialCacheMode
+    3, // ui32FlashCachingEnables
+    1, // ui32EnableCacheClockGating
+    0, // ui32EnableLightSleep
+    1, // ui32Dly
+    1, // ui32SMDly
+    1, // ui32EnableDataClockGating
+    0, // ui32EnableCacheMonitoring
+};
+
+//*****************************************************************************
+//
+//! @brief Enable the cache using the supplied settings
+//!
+//! @param psConfig - pointer to a config structure containing cache settings.
+//!
+//! This function takes in a structure of cache settings, and uses them to
+//! enable the cache. This function will take care of the necessary register
+//! writes both in this module and in the power control module, so a separate
+//! powerctrl call is not necessary.
+//!
+//! For most applications, the default cache settings will be the most
+//! efficient choice. To use the default cache settings with this function, use
+//! the address of the global am_hal_cachectrl_defaults structure as the
+//! psConfig argument.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig)
+{
+    uint32_t ui32ConfigValue;
+    uint32_t ui32Timeout;
+
+    //
+    // Pull the configuration data from the structure, and prepare to write the
+    // cache configuration register.
+    //
+    // NOTE: ICACHE and DCACHE settings were left out from this step. This is a
+    // workaround for a timing issue with early versions of Apollo2 that caused
+    // the cache to incorrectly mark itself valid during the startup sequence.
+    // The workaround calls for us to start the cache, manually invalidate it,
+    // and then enable ICACHE and DCACHE operation.
+    //
+    ui32ConfigValue = (AM_REG_CACHECTRL_CACHECFG_ENABLE( 1 )                                                |
+                       AM_REG_CACHECTRL_CACHECFG_LRU( psConfig->ui32LRU )                                   |
+                       AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0( (psConfig->ui32EnableNCregions & 0x1) >> 0 )   |
+                       AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1( (psConfig->ui32EnableNCregions & 0x2) >> 1 )   |
+                       psConfig->ui32Config                                                                 |
+                       AM_REG_CACHECTRL_CACHECFG_SERIAL(psConfig->ui32SerialCacheMode)                      |
+                       AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE( psConfig->ui32EnableCacheClockGating )      |
+                       AM_REG_CACHECTRL_CACHECFG_CACHE_LS(psConfig->ui32EnableLightSleep )                  |
+                       AM_REG_CACHECTRL_CACHECFG_DLY( psConfig->ui32Dly )                                   |
+                       AM_REG_CACHECTRL_CACHECFG_SMDLY( psConfig->ui32SMDly )                               |
+                       AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(psConfig->ui32EnableDataClockGating)          |
+                       AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(psConfig->ui32EnableCacheMonitoring) );
+
+    //
+    // Make sure the cache is enabled in the power control block.
+    //
+    am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE);
+
+    //
+    // Set the initial cache settings.
+    //
+    AM_REG(CACHECTRL, CACHECFG) = ui32ConfigValue;
+
+    //
+    // Wait for the cache ready signal.
+    //
+    for (ui32Timeout = 0; ui32Timeout < 50; ui32Timeout++)
+    {
+        if (AM_BFM(CACHECTRL, CACHECTRL, CACHE_READY))
+        {
+            break;
+        }
+    }
+
+    //
+    // Manually invalidate the cache (workaround for the issue described above.)
+    //
+    AM_BFW(CACHECTRL, CACHECTRL, INVALIDATE, 1);
+
+    //
+    // Wait for the cache ready signal again.
+    //
+    for (ui32Timeout = 0; ui32Timeout < 50; ui32Timeout++)
+    {
+        if (AM_BFM(CACHECTRL, CACHECTRL, CACHE_READY))
+        {
+            break;
+        }
+    }
+
+    //
+    // Now that the cache is running, and correctly marked invalid, we can OR in
+    // the ICACHE and DCACHE settings.
+    //
+    ui32ConfigValue |= (AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE( (psConfig->ui32FlashCachingEnables & 0x1) >> 0 )   |
+                        AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE( (psConfig->ui32FlashCachingEnables & 0x2) >> 1 ) );
+
+    //
+    // Write the final configuration settings to the CACHECTRL register.
+    //
+    AM_REG(CACHECTRL, CACHECFG) = ui32ConfigValue;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the cache.
+//!
+//! Call this function to completely shut down cache features.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_cachectrl_disable(void)
+{
+    uint32_t ui32CacheCfg;
+
+    //
+    // Save the cache settings.
+    //
+    ui32CacheCfg = AM_REG(CACHECTRL, CACHECFG);
+
+    //
+    // Remove the ICACHE and DCACHE settings.
+    //
+    ui32CacheCfg &= (AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(0) |
+                     AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(0));
+
+    //
+    // Write the resulting value back to the register.
+    //
+    AM_REG(CACHECTRL, CACHECFG) = ui32CacheCfg;
+
+    //
+    // Read the CACHECTRL register a few times
+    //
+    AM_REG(CACHECTRL, CACHECTRL);
+    AM_REG(CACHECTRL, CACHECTRL);
+    AM_REG(CACHECTRL, CACHECTRL);
+
+    //
+    // Disable the cache completely.
+    //
+    AM_BFW(CACHECTRL, CACHECFG, ENABLE, 0);
+
+    //
+    // Power the cache down in the powerctrl block.
+    //
+    am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE_DIS);
+}
+
+//*****************************************************************************
+//
+//! @brief Set a default cache configuration.
+//!
+//! This function is used to set a default cache configuration.
+//
+//*****************************************************************************
+void
+am_hal_cachectrl_config_default(void)
+{
+    //
+    // Set PWRCTRL
+    //
+    am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE);
+
+    //
+    // Write a default configuration to the CACHECFG register.
+    //
+    AM_REG(CACHECTRL, CACHECFG) =                                   \
+        AM_REG_CACHECTRL_CACHECFG_ENABLE( 1 )                   |   \
+        AM_REG_CACHECTRL_CACHECFG_LRU( 0 )                      |   \
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0( 0 )               |   \
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1( 0 )               |   \
+        AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E           |   \
+        AM_REG_CACHECTRL_CACHECFG_SERIAL( 0 )                   |   \
+        AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE( 1 )            |   \
+        AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE( 1 )            |   \
+        AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE( 1 )            |   \
+        AM_REG_CACHECTRL_CACHECFG_CACHE_LS( 0 )                 |   \
+        AM_REG_CACHECTRL_CACHECFG_DLY( 1 )                      |   \
+        AM_REG_CACHECTRL_CACHECFG_SMDLY( 1 )                    |   \
+        AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE( 1 )             |   \
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR( 0 );
+
+    //
+    // Write a default configuration to the FLASHCFG register.
+    //
+    AM_REG(CACHECTRL, FLASHCFG) = AM_REG_CACHECTRL_FLASHCFG_RD_WAIT(1);
+
+    //
+    // Write a default configuration to the CACHECTRL register.
+    //
+    AM_REG(CACHECTRL, CACHECTRL) =                                  \
+        AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE(1)         |   \
+        AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE(0)        |   \
+        AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE(1)         |   \
+        AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE(0)        |   \
+        AM_REG_CACHECTRL_CACHECTRL_RESET_STAT(0)                |   \
+        AM_REG_CACHECTRL_CACHECTRL_INVALIDATE(0);
+
+    //
+    // Write a default configuration to the NCR0START and NCR0END registers.
+    //
+    AM_REG(CACHECTRL, NCR0START) =                          \
+        AM_REG_CACHECTRL_NCR0START_ADDR(0);
+    AM_REG(CACHECTRL, NCR0END) =                            \
+        AM_REG_CACHECTRL_NCR0END_ADDR(0);
+
+    //
+    // Write a default configuration to the NCR1START and NCR1END registers.
+    //
+    AM_REG(CACHECTRL, NCR1START) =                          \
+        AM_REG_CACHECTRL_NCR1START_ADDR(0);
+    AM_REG(CACHECTRL, NCR1END) =                            \
+        AM_REG_CACHECTRL_NCR1END_ADDR(0);
+
+    //
+    // Write a default configuration to the DMONn and IMONn registers.
+    //
+    AM_REG(CACHECTRL, DMON0) =                                      \
+        AM_REG_CACHECTRL_DMON0_DACCESS_COUNT(0);
+    AM_REG(CACHECTRL, DMON1)  =                                     \
+        AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT(0);
+    AM_REG(CACHECTRL, DMON2)  =                                     \
+        AM_REG_CACHECTRL_DMON2_DHIT_COUNT(0);
+    AM_REG(CACHECTRL, DMON3)  =                                     \
+        AM_REG_CACHECTRL_DMON3_DLINE_COUNT(0);
+    AM_REG(CACHECTRL, IMON0)  =                                     \
+        AM_REG_CACHECTRL_IMON0_IACCESS_COUNT(0);
+    AM_REG(CACHECTRL, IMON1)  =                                     \
+        AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT(0);
+    AM_REG(CACHECTRL, IMON2)  =                                     \
+        AM_REG_CACHECTRL_IMON2_IHIT_COUNT(0);
+    AM_REG(CACHECTRL, IMON3)  =                                     \
+        AM_REG_CACHECTRL_IMON3_ILINE_COUNT(0);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the flash cache controller via a configuration structure.
+//!
+//! @param psConfig - Pointer to a data structure containing all of the data
+//      necessary to configure the CACHECFG register.
+//!
+//! This function is used to configure all fields of the CACHECFG.
+//
+//*****************************************************************************
+void
+am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig)
+{
+    uint32_t u32ConfigValue;
+
+    //
+    // Arrange all of the members of the data structure into a single u32 that
+    //  can be written to the register.
+    //
+    u32ConfigValue =
+        AM_REG_CACHECTRL_CACHECFG_ENABLE( psConfig->ui32EnableCache )       |
+        AM_REG_CACHECTRL_CACHECFG_LRU( psConfig->ui32LRU )                  |
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0(
+            (psConfig->ui32EnableNCregions & 0x1) >> 0 )                    |
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1(
+            (psConfig->ui32EnableNCregions & 0x2) >> 1 )                    |
+        psConfig->ui32Config                                                |
+        AM_REG_CACHECTRL_CACHECFG_SERIAL(psConfig->ui32SerialCacheMode)     |
+        AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(
+            (psConfig->ui32FlashCachingEnables & 0x1) >> 0 )                |
+        AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(
+            (psConfig->ui32FlashCachingEnables & 0x2) >> 1 )                |
+        AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE(
+            psConfig->ui32EnableCacheClockGating )                          |
+        AM_REG_CACHECTRL_CACHECFG_CACHE_LS(
+            psConfig->ui32EnableLightSleep )                                |
+        AM_REG_CACHECTRL_CACHECFG_DLY( psConfig->ui32Dly )                  |
+        AM_REG_CACHECTRL_CACHECFG_SMDLY( psConfig->ui32SMDly )              |
+        AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(
+            psConfig->ui32EnableDataClockGating )                           |
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(
+            psConfig->ui32EnableCacheMonitoring );
+
+    //
+    // Write the configuration value to the CACHECFG register.
+    //
+    AM_REG(CACHECTRL, CACHECFG) = u32ConfigValue;
+}
+
+//*****************************************************************************
+//
+//! @brief Configure the various flash cache controller enables.
+//!
+//! @param u32EnableMask  - Mask of features to be enabled.
+//! @param u32DisableMask - Mask of features to be disabled.
+//!
+//! This function is used to enable or disable the various flash cache
+//! controller configuration enables which consist of the following:
+//!     AM_HAL_CACHECTRL_CACHECFG_ENABLE                Flash cache controller
+//!     AM_HAL_CACHECTRL_CACHECFG_LRU_ENABLE            LRU (disabled = LRR)
+//!     AM_HAL_CACHECTRL_CACHECFG_NC0_ENABLE            Non-cacheable region 0
+//!     AM_HAL_CACHECTRL_CACHECFG_NC1_ENABLE            Non-cacheable region 1
+//!     AM_HAL_CACHECTRL_CACHECFG_SERIAL_ENABLE         Serial cache mode
+//!     AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE         Instruction caching
+//!     AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE         Data caching.
+//!     AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE  Cache clock gating
+//!     AM_HAL_CACHECTRL_CACHECFG_LS_ENABLE             Light sleep cache RAMs
+//!     AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE   Data clock gating
+//!     AM_HAL_CACHECTRL_CACHECFG_MONITOR_ENABLE        Cache Monitoring Stats
+//!
+//! Note that if both an enable and disable are provided in their respective
+//! masks, the enable will take precendence.
+//!
+//! @return The previous status of the flash cache controller enables.
+//
+//*****************************************************************************
+#define CACHECTRL_VALID_ENABLES                         (   \
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_M              |   \
+        AM_REG_CACHECTRL_CACHECFG_LRU_M                 |   \
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M          |   \
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M          |   \
+        AM_REG_CACHECTRL_CACHECFG_SERIAL_M              |   \
+        AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M       |   \
+        AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M       |   \
+        AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M       |   \
+        AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M            |   \
+        AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M        |   \
+        AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M )
+
+uint32_t
+am_hal_cachectrl_cache_enables(uint32_t u32EnableMask, uint32_t u32DisableMask)
+{
+    uint32_t ui32RetVal = AM_BFR(CACHECTRL, CACHECFG, ENABLE) &
+                          CACHECTRL_VALID_ENABLES;
+
+    //
+    // Make sure the enable masks include only valid bits.
+    //
+    u32EnableMask  &= CACHECTRL_VALID_ENABLES;
+    u32DisableMask &= CACHECTRL_VALID_ENABLES;
+
+    //
+    // First, do the disables.
+    //
+    AM_REG(CACHECTRL, CACHECFG) &= ~u32DisableMask;
+
+    //
+    // Now set the enables.
+    //
+    AM_REG(CACHECTRL, CACHECFG) |= u32EnableMask;
+
+    return ui32RetVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Select the cache configuration type.
+//!
+//! This functions only sets the CACHECFG CONFIG field.
+//!
+//! @param ui32CacheConfig - The cache configuration value.
+//!
+//! This function can be used to select the type of cache.frequency of the main
+//! system clock.  The ui32CacheConfig parameter should be set to one of the
+//! following values:
+//!
+//!     AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 : Direct mapped,
+//!         128-bit linesize, 256 entries (2 SRAMs active).
+//!     AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256   : Two-way set associative,
+//!         128-bit linesize, 256 entries (4 SRAMs active).
+//!     AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512   : Two-way set associative,
+//!         128-bit linesize, 512 entries (8 SRAMs active).
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_cachectrl_cache_config(uint32_t ui32CacheConfig)
+{
+    //
+    // Clear the bitfield
+    //
+    AM_REG(CACHECTRL, CACHECFG) &= ~AM_REG_CACHECTRL_CACHECFG_CONFIG_M;
+
+    //
+    // Write the new value to the bitfield.
+    //
+    AM_REG(CACHECTRL, CACHECFG) |= ui32CacheConfig &
+                                   AM_REG_CACHECTRL_CACHECFG_CONFIG_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Invalidate the flash cache.
+//!
+//! This function is used to invalidate the flash cache.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_cachectrl_invalidate_flash_cache(void)
+{
+    //
+    // Write the bit to invalidate the flash cache.
+    // Note - this bit is not sticky, no need to write it back to 0.
+    //
+    AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_GO;
+}
+
+//*****************************************************************************
+//
+//! @brief Reset cache statistics.
+//!
+//! This function is used to reset cache statistics.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_cachectrl_reset_statistics(void)
+{
+    //
+    // Write the bit to reset flash statistics.
+    // Note - this bit is not sticky, no need to write it back to 0.
+    //
+    AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_CLEAR;
+}
+
+//*****************************************************************************
+//
+//! @brief Get flash cache sleep mode status.
+//!
+//! This function returns flash cache sleep mode statuses.
+//!
+//! @return
+//!     bit0 indicates that flash0 flash sleep mode is enabled.
+//!     bit1 indicates that flash1 flash sleep mode is enabled.
+//
+//*****************************************************************************
+uint32_t
+am_hal_cachectrl_sleep_mode_status(void)
+{
+    uint32_t ui32Status, ui32Ret;
+
+    //
+    // Get the current sleep mode status bits.
+    //
+    ui32Status = AM_REG(CACHECTRL, CACHECTRL);
+    ui32Ret = (ui32Status &                                                 \
+                AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_M) >>          \
+                (AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_S - 0);
+    ui32Ret |= (ui32Status &                                                \
+                AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_M) >>          \
+                (AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_S - 1);
+
+    return ui32Ret;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable or disable flash cache sleep mode.
+//!
+//! This function enables or disables flash cache sleep mode.
+//! @param ui32EnableMask  - bit0 for flash0, bit1 for flash1.
+//! @param ui32DisableMask - bit0 for flash0, bit1 for flash1.
+//!
+//! Note that if both an enable and disable are provided in their respective
+//! masks, the enable will take precedence.
+//!
+//! @return Previous status.
+//!     bit0 indicates that flash0 flash sleep mode was previously enabled.
+//!     bit1 indicates that flash1 flash sleep mode was previously enabled.
+//
+//*****************************************************************************
+uint32_t
+am_hal_cachectrl_sleep_mode_enable(uint32_t ui32EnableMask,
+                                   uint32_t ui32DisableMask)
+{
+    uint32_t ui32Ret = am_hal_cachectrl_sleep_mode_status();
+
+    if ( ui32DisableMask & 0x1 )
+    {
+        AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE_M;
+    }
+
+    if ( ui32DisableMask & 0x2 )
+    {
+        AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE_M;
+    }
+
+    if ( ui32EnableMask & 0x1 )
+    {
+        AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE_M;
+    }
+
+    if ( ui32EnableMask & 0x2 )
+    {
+        AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE_M;
+    }
+
+    return ui32Ret;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h
new file mode 100644
index 0000000000..b8ce914b94
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h
@@ -0,0 +1,211 @@
+//*****************************************************************************
+//
+//  am_hal_cachectrl.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the CACHE controller.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_CACHECTRL_H
+#define AM_HAL_CACHECTRL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Cache configuration structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Set to 1 to enable the cache.
+    //
+    uint8_t ui32EnableCache;
+
+    //
+    //! Set to 1 to enable the LRU cache replacement policy.
+    //! Set to 0 to enable the LRR (least recently used) replacement policy.
+    //! LEE minimizes writes to the TAG SRAM.
+    //
+    uint8_t ui32LRU;
+
+    //
+    //! Set to 3 to enable non-cachable region 1 and non-cachable region 0.
+    //! Set to 2 to enable non-cachable region 1.
+    //! Set to 1 to enable non-cachable region 0.
+    //! Set to 0 to make all regions cacheable.
+    //
+    uint8_t ui32EnableNCregions;
+
+    //
+    //! Set to:
+    //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 for direct-mapped,
+    //!     128-bit linesize, 256 entries (2 SRAMs active)
+    //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 for two-way set associative,
+    //!     128-bit linesize, 256 entries (4 SRAMs active)
+    //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 for two-way set associative,
+    //!     128-bit linesize, 512 entries (8 SRAMs active)
+    //
+    uint8_t ui32Config;
+
+    //
+    //! Set to 1 to enable serial cache mode.
+    //
+    uint8_t ui32SerialCacheMode;
+
+    //
+    //! Set to 3 to enable flash data caching and flash instruction caching.
+    //! Set to 2 to enable flash data caching.
+    //! Set to 1 to enable flash instruction caching.
+    //! Set to 0 to disable flash data caching and flash instruction caching.
+    //
+    uint8_t ui32FlashCachingEnables;
+
+    //
+    //! Set to 1 to enable clock gating of cache RAMs.
+    //
+    uint8_t ui32EnableCacheClockGating;
+
+    //
+    //! Set to 1 to enable light sleep of cache RAMs.
+    //
+    uint8_t ui32EnableLightSleep;
+
+    //
+    //! Set Data RAM delay value (0x0 - 0xF).
+    //
+    uint8_t ui32Dly;
+
+    //
+    //! Set SM Data RAM delay value (0x0 - 0xF).
+    //
+    uint8_t ui32SMDly;
+
+    //
+    //! Set to 1 to enable clock gating of the entire data array.
+    //
+    uint8_t ui32EnableDataClockGating;
+
+    //
+    //! Set to 1 to enable cache monitor statistics.
+    //
+    uint8_t ui32EnableCacheMonitoring;
+}
+am_hal_cachectrl_config_t;
+
+extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults;
+
+//*****************************************************************************
+//
+//! @name Cache enables
+//! @brief Configuration selection for the various cache enables.
+//!
+//! These macros may be used in conjunction with the
+//!  am_hal_cachectrl_cache_enable() function to enable various cache features.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CACHECTRL_CACHECFG_ENABLE                AM_REG_CACHECTRL_CACHECFG_ENABLE_M
+#define AM_HAL_CACHECTRL_CACHECFG_LRU_ENABLE            AM_REG_CACHECTRL_CACHECFG_LRU_M
+#define AM_HAL_CACHECTRL_CACHECFG_NC0_ENABLE            AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M
+#define AM_HAL_CACHECTRL_CACHECFG_NC1_ENABLE            AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M
+#define AM_HAL_CACHECTRL_CACHECFG_SERIAL_ENABLE         AM_REG_CACHECTRL_CACHECFG_SERIAL_M
+#define AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE         AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M
+#define AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE         AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M
+#define AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE  AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M
+#define AM_HAL_CACHECTRL_CACHECFG_LS_ENABLE             AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M
+#define AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE   AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M
+#define AM_HAL_CACHECTRL_CACHECFG_MONITOR_ENABLE        AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M
+//! @}
+
+//*****************************************************************************
+//
+//! @name Cache Config
+//! @brief Configuration selection for the cache.
+//!
+//! These macros may be used in conjunction with the
+//!  am_hal_cachectrl_cache_config() function to select the cache type.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 AM_REG_CACHECTRL_CACHECFG_CONFIG_W1_128B_256E
+#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256   AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_256E
+#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512   AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E
+//! @}
+
+//*****************************************************************************
+//
+// Default cache settings
+//
+//*****************************************************************************
+#define AM_HAL_CACHECTRL_DEFAULTS                                             \
+    (AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE |                                \
+     AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE |                                \
+     AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE |                         \
+     AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE |                          \
+     AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512)
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig);
+extern void am_hal_cachectrl_disable(void);
+extern void am_hal_cachectrl_config_default(void);
+extern void am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig);
+extern uint32_t am_hal_cachectrl_cache_enables(uint32_t u32EnableMask,
+                                               uint32_t u32DisableMask);
+extern void am_hal_cachectrl_cache_config(uint32_t ui32CacheConfig);
+extern void am_hal_cachectrl_invalidate_flash_cache(void);
+extern void am_hal_cachectrl_reset_statistics(void);
+extern uint32_t am_hal_cachectrl_sleep_mode_status(void);
+extern uint32_t am_hal_cachectrl_sleep_mode_enable(uint32_t ui32EnableMask,
+                                                   uint32_t ui32DisableMask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_CACHECTRL_H
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c
new file mode 100644
index 0000000000..d60d7e47b5
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c
@@ -0,0 +1,491 @@
+//*****************************************************************************
+//
+//  am_hal_clkgen.c
+//! @file
+//!
+//! @brief Functions for interfacing with the CLKGEN.
+//!
+//! @addtogroup clkgen2 Clock Generator (CLKGEN)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// CLKGEN HFADJ register
+//
+//*****************************************************************************
+#define AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT         0x5B8
+
+//*****************************************************************************
+//
+//! @brief Select the clock divisor for the main system clock.
+//!
+//! @param ui32ClockSetting - The divisor value for the system clock.
+//!
+//! This function can be used to select the frequency of the main system clock.
+//! The \e ui32ClockSetting parameter should be set to one of the following
+//! values:
+//!
+//!     AM_HAL_CLKGEN_SYSCLK_MAX
+//!     AM_HAL_CLKGEN_SYSCLK_48MHZ
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_sysclk_select(uint32_t ui32ClockSetting)
+{
+    am_hal_debug_assert_msg(ui32ClockSetting == AM_HAL_CLKGEN_SYSCLK_48MHZ,
+        "am_hal_clkgen_sysclk_select(): invalid clock setting.");
+
+    //
+    // Unlock the clock control register.
+    //
+    AM_REG(CLKGEN, CLKKEY) = AM_REG_CLKGEN_CLKKEY_KEYVAL;
+
+    //
+    // Set the HFRC divisor to the user-selected value.
+    //
+    AM_REG(CLKGEN, CCTRL) = ui32ClockSetting;
+
+    //
+    // Lock the clock configuration registers.
+    //
+    AM_REG(CLKGEN, CLKKEY) = 0;
+}
+
+//*****************************************************************************
+//
+//! @brief Get the current system clock frequency.
+//!
+//! This function can be used to determine the frequency of the main system
+//! clock. The return value is the system clock frequency measured in hertz.
+//!
+//! @return System clock frequency in Hz
+//
+//*****************************************************************************
+uint32_t
+am_hal_clkgen_sysclk_get(void)
+{
+    uint32_t ui32ClockSetting;
+
+    //
+    // Read the value of the clock divider.
+    //
+    ui32ClockSetting = AM_REG(CLKGEN, CCTRL) & AM_REG_CLKGEN_CCTRL_CORESEL_M;
+
+    switch ( ui32ClockSetting )
+    {
+        case AM_REG_CLKGEN_CCTRL_CORESEL_HFRC:
+            return 48000000;
+        case AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2:
+            return 24000000;
+        default:
+            return 0xFFFFFFFF;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Enable selected CLKGEN Interrupts.
+//!
+//! Use this function to enable the interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_clkgen.h
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_clkgen_int_enable(uint32_t ui32Interrupt)
+{
+    //
+    // Enable the interrupts.
+    //
+    AM_REG(CLKGEN, INTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return enabled CLKGEN Interrupts.
+//!
+//! Use this function to get all enabled CLKGEN interrupts.
+//!
+//! @return enabled CLKGEN interrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_clkgen_int_enable_get(void)
+{
+    //
+    // Return the enabled interrupts.
+    //
+    return AM_REG(CLKGEN, INTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable selected CLKGEN Interrupts.
+//!
+//! Use this function to disable the CLKGEN interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_clkgen.h
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_clkgen_int_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Disable the interrupts.
+    //
+    AM_REG(CLKGEN, INTEN) &= ~ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Sets the interrupt status.
+//!
+//! @param ui32IntFlags interrupts to be enabled.
+//!
+//! This function sets the interrupts.
+//!
+//! Valid values for ui32IntFlags are:
+//!
+//!     AM_HAL_CLKGEN_INT_RTC_ALARM
+//!     AM_HAL_CLKGEN_INT_XT_FAIL
+//!     AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE
+//!     AM_HAL_CLKGEN_INT AUTOCAL_FAIL
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Set the interrupt status.
+    //
+    AM_REG(CLKGEN, INTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Gets the interrupt configuration.
+//!
+//! @param bEnabledOnly - return the status of only the enabled interrupts.
+//!
+//! This function gets the currently configured interrupts.
+//!
+//! @return the configured interrupts.
+//!
+//! Possible values for the return are:
+//!
+//!     AM_HAL_CLKGEN_INT_RTC_ALARM
+//!     AM_HAL_CLKGEN_INT_XT_FAIL
+//!     AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE
+//!     AM_HAL_CLKGEN_INT AUTOCAL_FAIL
+//
+//*****************************************************************************
+uint32_t
+am_hal_clkgen_int_status_get(bool bEnabledOnly)
+{
+    //
+    // Return the status.
+    //
+    if ( bEnabledOnly )
+    {
+        uint32_t u32RetVal = AM_REG(CLKGEN, INTSTAT);
+        u32RetVal &= AM_REG(CLKGEN, INTEN);
+        return u32RetVal;
+    }
+    else
+    {
+        return AM_REG(CLKGEN, INTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Clears the interrupts.
+//!
+//! @param ui32IntFlags interrupts to be cleared.
+//!
+//! This function clears the interrupts.
+//!
+//! Valid values for ui32IntFlags are:
+//!
+//!     AM_HAL_CLKGEN_INT_RTC_ALARM
+//!     AM_HAL_CLKGEN_INT_XT_FAIL
+//!     AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE
+//!     AM_HAL_CLKGEN_INT AUTOCAL_FAIL
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Clear the interrupts.
+    //
+    AM_REG(CLKGEN, INTCLR) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Starts the desired oscillator(s) (OSC).
+//!
+//! @param ui32OscFlags oscillator(s) to start.
+//!
+//! This function starts the desired oscillator(s) (OSC).
+//!
+//! Valid values for ui32OscFlags are:
+//!
+//!     AM_HAL_CLKGEN_OSC_LFRC
+//!     AM_HAL_CLKGEN_OSC_XT
+//!
+//! @return 0 None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_osc_start(uint32_t ui32OscFlags)
+{
+    //
+    // Start the oscillator(s).
+    //
+    AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags;
+}
+
+//*****************************************************************************
+//
+//! @brief Stops the desired oscillator(s) (OSC).
+//!
+//! @param ui32OscFlags oscillator(s) to stop.
+//!
+//! This function stops the desired oscillator(s) (OSC).
+//!
+//! Valid values for ui32OscFlags are:
+//!
+//!     AM_HAL_CLKGEN_OSC_LFRC
+//!     AM_HAL_CLKGEN_OSC_XT
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_osc_stop(uint32_t ui32OscFlags)
+{
+    //
+    // Stop the oscillator(s).
+    //
+    AM_REG(CLKGEN, OCTRL) |= ui32OscFlags;
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the clock out signal.
+//!
+//! @param ui32Signal desired location for the clock out signal.
+//!
+//! This function enables the clock out signal. See am_hal_clkgen.h for
+//! available signals.
+//!
+//! e.g. AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC
+//!      AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4
+//!      AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_clkout_enable(uint32_t ui32Signal)
+{
+    //
+    // Enable the clock out on desired signal.
+    //
+    AM_REG(CLKGEN, CLKOUT) = AM_REG_CLKGEN_CLKOUT_CKEN_M | ui32Signal;
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the clock out signal.
+//!
+//! This function disables the clock out signal.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_clkout_disable(void)
+{
+    //
+    // Disable the clock out.
+    //
+    AM_REG(CLKGEN, CLKOUT) = 0;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable UART system clock.
+//!
+//! This function enables or disables the UART system clock.
+//!
+//! @param ui32Module is 0 or 1 for Apollo2.
+//! @param ui32UartEn is one of the following.
+//!     AM_HAL_CLKGEN_UARTEN_DIS
+//!     AM_HAL_CLKGEN_UARTEN_EN
+//!     AM_HAL_CLKGEN_UARTEN_REDUCE_FREQ
+//!     AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_uarten_set(uint32_t ui32Module, uint32_t ui32UartEn)
+{
+    uint32_t ui32Mask;
+
+    if ( (ui32Module >= AM_REG_UART_NUM_MODULES)        ||
+         (ui32UartEn > AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV) )
+    {
+        return;
+    }
+
+    ui32UartEn <<= (ui32Module * AM_HAL_CLKGEN_UARTEN_UARTENn_S(ui32Module));
+    ui32Mask = ~(AM_HAL_CLKGEN_UARTEN_UARTENn_M(ui32Module));
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Set the UART clock
+    //
+    AM_REG(CLKGEN, UARTEN) &= ui32Mask;
+    AM_REG(CLKGEN, UARTEN) |= ui32UartEn;
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_END_ASM
+}
+
+//*****************************************************************************
+//
+//! @brief Enables HFRC auto-adjustment at the specified interval.
+//!
+//! @param ui32Warmup - How long to give the HFRC to stabilize during each
+//! calibration attempt.
+//! @param ui32Frequency - How often the auto-adjustment should happen.
+//!
+//! This function enables HFRC auto-adjustment from an external crystal
+//! oscillator even when the crystal is not normally being used.
+//!
+//! ui32Warmup should be one of the following values:
+//!
+//!     AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC
+//!     AM_REG_CLKGEN_HFADJ_HFWARMUP_2SEC
+//!
+//! ui32Frequency should be one of the following values:
+//!
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_16SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_32SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_64SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_128SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_256SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_512SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_1024SEC
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_hfrc_adjust_enable(uint32_t ui32Warmup, uint32_t ui32Frequency)
+{
+    //
+    // Set the HFRC Auto-adjust register for the user's chosen settings. Assume
+    // that the HFRC should be calibrated to 48 MHz and that the crystal is
+    // running at 32.768 kHz.
+    //
+    AM_REG(CLKGEN, HFADJ) =
+         AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2                      |
+         ui32Warmup                                                         |
+         AM_REG_CLKGEN_HFADJ_HFXTADJ(AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT)   |
+         ui32Frequency                                                      |
+         AM_REG_CLKGEN_HFADJ_HFADJEN_EN;
+}
+
+//*****************************************************************************
+//
+//! @brief Disables HFRC auto-adjustment.
+//!
+//! This function disables HFRC auto-adjustment.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_hfrc_adjust_disable(void)
+{
+    //
+    // Disable the clock out.
+    //
+    AM_REG(CLKGEN, HFADJ) =
+        AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2                       |
+        AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC                                   |
+        AM_REG_CLKGEN_HFADJ_HFXTADJ(AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT)    |
+        AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC                                    |
+        AM_REG_CLKGEN_HFADJ_HFADJEN_DIS;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h
new file mode 100644
index 0000000000..fc50cb9b43
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h
@@ -0,0 +1,206 @@
+//*****************************************************************************
+//
+//  am_hal_clkgen.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the CLKGEN.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_CLKGEN_H
+#define AM_HAL_CLKGEN_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name System Clock max frequency
+//! @brief Defines the maximum clock frequency for this device.
+//!
+//! These macros provide a definition of the maximum clock frequency.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_FREQ_MAX_HZ       48000000
+#define AM_HAL_CLKGEN_FREQ_MAX_MHZ      (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000000)
+//! @}
+
+//*****************************************************************************
+//
+//! @name System Clock Selection
+//! @brief Divisor selection for the main system clock.
+//!
+//! These macros may be used along with the am_hal_clkgen_sysctl_select()
+//! function to select the frequency of the main system clock.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_SYSCLK_MAX        AM_REG_CLKGEN_CCTRL_CORESEL_HFRC
+#define AM_HAL_CLKGEN_SYSCLK_48MHZ      AM_REG_CLKGEN_CCTRL_CORESEL_HFRC
+//! @}
+
+//*****************************************************************************
+//
+//! @name Interrupt Status Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to set and clear interrupt bits.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_INT_ALM           AM_REG_CLKGEN_INTEN_ALM_M
+#define AM_HAL_CLKGEN_INT_OF            AM_REG_CLKGEN_INTEN_OF_M
+#define AM_HAL_CLKGEN_INT_ACC           AM_REG_CLKGEN_INTEN_ACC_M
+#define AM_HAL_CLKGEN_INT_ACF           AM_REG_CLKGEN_INTEN_ACF_M
+//! @}
+
+//*****************************************************************************
+//
+//! @name OSC Start and Stop
+//! @brief OSC Start and Stop defines.
+//!
+//! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x().
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_OSC_LFRC          AM_REG_CLKGEN_OCTRL_STOPRC_M
+#define AM_HAL_CLKGEN_OSC_XT            AM_REG_CLKGEN_OCTRL_STOPXT_M
+//! @}
+
+//*****************************************************************************
+//
+// OSC Start, Stop, Select defines
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC         AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV4      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV16     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV32     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_RTC_100Hz    AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_100Hz
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2M     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT           AM_REG_CLKGEN_CLKOUT_CKSEL_XT
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CG_100Hz     AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC         AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4    AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8    AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32   AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64   AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLK     AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLK
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_FLASH_CLK    AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2    AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32   AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512  AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K  AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV256    AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8K     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV64K    AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz    AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M   AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE       AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE   AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE         AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16   AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_FCLKNE       AM_REG_CLKGEN_CLKOUT_CKSEL_FCLKNE
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE       AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE
+
+//*****************************************************************************
+//
+// UARTEN
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_UARTEN_DIS          AM_REG_CLKGEN_UARTEN_UART0EN_DIS
+#define AM_HAL_CLKGEN_UARTEN_EN           AM_REG_CLKGEN_UARTEN_UART0EN_EN
+#define AM_HAL_CLKGEN_UARTEN_REDUCE_FREQ  AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ
+#define AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV
+
+#define AM_HAL_CLKGEN_UARTEN_UARTENn_S(module)                                  \
+        ((module) *                                                             \
+        (AM_REG_CLKGEN_UARTEN_UART1EN_S - AM_REG_CLKGEN_UARTEN_UART0EN_S))
+
+#define AM_HAL_CLKGEN_UARTEN_UARTENn_M(module)                                  \
+        (AM_REG_CLKGEN_UARTEN_UART0EN_M << AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
+
+//
+// UARTEN: entype is one of DIS, EN, REDUCE_FREQ, EN_POWER_SAV.
+//
+#define AM_HAL_CLKGEN_UARTEN_UARTENn(module, entype)                            \
+        (AM_REG_CLKGEN_UARTEN_UART0EN_##entype <<                               \
+         AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_clkgen_sysclk_select(uint32_t ui32ClockSetting);
+extern uint32_t am_hal_clkgen_sysclk_get(void);
+extern void am_hal_clkgen_osc_start(uint32_t ui32OscFlags);
+extern void am_hal_clkgen_osc_stop(uint32_t ui32OscFlags);
+extern void am_hal_clkgen_clkout_enable(uint32_t ui32Signal);
+extern void am_hal_clkgen_clkout_disable(void);
+extern void am_hal_clkgen_uarten_set(uint32_t ui32Module, uint32_t ui32UartEn);
+extern void am_hal_clkgen_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_clkgen_int_enable_get(void);
+extern void am_hal_clkgen_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_clkgen_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_clkgen_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_clkgen_int_status_get(bool bEnabledOnly);
+extern void am_hal_clkgen_hfrc_adjust_enable(uint32_t ui32Warmup, uint32_t ui32Frequency);
+extern void am_hal_clkgen_hfrc_adjust_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_CLKGEN_H
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c
new file mode 100644
index 0000000000..13fc3c07cc
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c
@@ -0,0 +1,1687 @@
+//*****************************************************************************
+//
+//  am_hal_ctimer.c
+//! @file
+//!
+//! @brief Functions for interfacing with the Counter/Timer module.
+//!
+//! @addtogroup ctimer2 Counter/Timer (CTIMER)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Address space distance between timer configuration registers.
+//
+//*****************************************************************************
+#define MAX_CTIMERS         4
+#define TIMER_OFFSET        (AM_REG_CTIMER_TMR1_O - AM_REG_CTIMER_TMR0_O)
+#define CTIMER_CMPR_OFFSET  (AM_REG_CTIMER_CMPRB0_O - AM_REG_CTIMER_CMPRA0_O)
+
+//*****************************************************************************
+//
+// Adjacency check
+//
+// This is related to the timer read workaround. This macro checks to see if
+// the two supplied count values are within one "tick" of eachother. It should
+// still pass in the event of a timer rollover.
+//
+//*****************************************************************************
+#define adjacent(A, B)      (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0))
+
+//*****************************************************************************
+//
+// Array of function pointers for handling CTimer interrupts.
+//
+//*****************************************************************************
+am_hal_ctimer_handler_t am_hal_ctimer_ppfnHandlers[16];
+
+//*****************************************************************************
+//
+// Static function for reading the timer value.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+__attribute__((naked))
+static
+void
+back2back_reads(uint32_t u32TimerAddr, uint32_t u32Data[])
+{
+    // u32TimerAddr = address of the timer to be read.
+    // u32Data[] is a pointer to a 3 word data array provided by the caller.
+    __asm
+    (
+        // Do 3 back-to-back reads of the register
+        "   push    {r4}\n"                     // Save r4
+        "   push    {r1}\n"                     // Save the data array ptr for later
+        "   mov     r2, r0\n"                   // Get Timer Addr
+        "   mrs     r4, PRIMASK\n"              // Save PRIMASK
+        "   cpsid   i\n"                        // __disable_irq()
+        "   nop\n"                              // Give the disable a cycle to take affect (but almost certainly not really needed)
+        "   ldr     r0, [r2, #0]\n"             // Get TMRn register value
+        "   ldr     r1, [r2, #0]\n"             // Get TMRn register value again
+        "   ldr     r3, [r2, #0]\n"             // Get TMRn register value for a third time
+        "   msr     PRIMASK, r4\n"              // Restore PRIMASK
+        "   pop     {r2}\n"                     // Get the array ptr
+        "   str     r0, [r2, #0]\n"             // Store register value to variable
+        "   str     r1, [r2, #4]\n"             // Store register value to variable
+        "   str     r3, [r2, #8]\n"             // Store register value to variable
+        "   pop     {r4}\n"                     // restore r4
+        "   bx      lr\n"
+    );
+}
+
+#elif defined(__ARMCC_VERSION)
+__asm static uint32_t
+back2back_reads( uint32_t u32TimerAddr, uint32_t u32Data[])
+{
+    push    {r4}                     // Save r4
+    push    {r1}                     // Save the data array ptr for later
+    mov     r2, r0                   // Get Timer Addr
+    mrs     r4, PRIMASK              // Save PRIMASK
+    cpsid   i                        // __disable_irq()
+    nop                              // Give the disable a cycle to take affect (but almost certainly not really needed)
+    ldr     r0, [r2, #0]             // Get TMRn register value
+    ldr     r1, [r2, #0]             // Get TMRn register value again
+    ldr     r3, [r2, #0]             // Get TMRn register value for a third time
+    msr     PRIMASK, r4              // Restore PRIMASK
+    pop     {r2}                     // Get the array ptr
+    str     r0, [r2, #0]             // Store register value to variable
+    str     r1, [r2, #4]             // Store register value to variable
+    str     r3, [r2, #8]             // Store register value to variable
+    pop     {r4}                     // Restore r4
+    bx      lr
+}
+
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma diag_suppress = Pe940   // Suppress IAR compiler warning about missing
+                                // return statement on a non-void function
+__stackless static uint32_t
+back2back_reads( uint32_t u32TimerAddr, uint32_t u32Data[])
+{
+    __asm("    push    {r4}");          // Save r4
+    __asm("    push    {r1}");          // Save the data array ptr for later
+    __asm("    mov     r2, r0");        // Get Timer Addr
+    __asm("    mrs     r4, PRIMASK");   // Save PRIMASK"
+    __asm("    cpsid   i");             // __disable_irq()
+    __asm("    nop");                   // Give the disable a cycle to take affect (but almost certainly not really needed)
+    __asm("    ldr     r0, [r2, #0]");  // Get TMRn register value
+    __asm("    ldr     r1, [r2, #0]");  // Get TMRn register value again
+    __asm("    ldr     r3, [r2, #0]");  // Get TMRn register value for a third time
+    __asm("    msr     PRIMASK, r4");   // Restore PRIMASK
+    __asm("    pop     {r2}");          // Get the array ptr
+    __asm("    str     r0, [r2, #0]");  // Store register value to variable
+    __asm("    str     r1, [r2, #4]");  // Store register value to variable
+    __asm("    str     r3, [r2, #8]");  // Store register value to variable
+    __asm("    pop     {r4}");          // Restore r4
+    __asm("    bx      lr");
+}
+#pragma diag_default = Pe940    // Restore IAR compiler warning
+#endif
+
+//*****************************************************************************
+//
+// @brief Check to see if the given CTimer is using the HFRC
+//
+//  Note - Calls to this function should be from inside a critical section.
+//
+//! @return None.
+//
+//*****************************************************************************
+static bool
+ctimer_source_hfrc(uint32_t ui32CtimerNum)
+{
+    uint32_t *pui32ConfigReg;
+    uint32_t ui32TimerASrc, ui32TimerBSrc;
+
+    //
+    // Find the correct register to write.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32CtimerNum * TIMER_OFFSET));
+
+    //
+    // Determine if this timer is using HFRC as the clock source.
+    // The value we are looking for is HFRC_DIV4 to HFRC_DIV4K.
+    // Get the clock sources and 0-base the extracted value.
+    //
+    ui32TimerASrc = AM_BFX(CTIMER, CTRL0, TMRA0CLK, *pui32ConfigReg) -
+                    AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4);
+    ui32TimerBSrc = AM_BFX(CTIMER, CTRL0, TMRB0CLK, *pui32ConfigReg) -
+                    AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4);
+
+    //
+    // If the source value is 0 to (HFRC_DIV4K - HFRC_DIV4), then it's HFRC.
+    //
+    if ( (ui32TimerASrc <= (AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4K) -
+                            AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4)))  ||
+         (ui32TimerBSrc <= (AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4K) -
+                            AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4))) )
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+
+} // ctimer_source_hfrc()
+
+//*****************************************************************************
+//
+// @brief Check to see if any of the CTimers or STimer are using the HFRC.
+//
+//  This function should be used to check if the HFRC is being used in order
+//  to correctly establish power related settings.
+//
+//  Note - Calls to this function should be from inside a critical section.
+//
+//! @return None.
+//
+//*****************************************************************************
+static bool
+timers_use_hfrc(void)
+{
+    uint32_t ui32TimerASrc, ui32CtimerNum;
+
+    //
+    // Check STimer to see if it is using HFRC.
+    //
+    ui32TimerASrc = AM_BFR(CTIMER, STCFG, CLKSEL);
+    if ( (ui32TimerASrc == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16)   ||
+         (ui32TimerASrc == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256) )
+    {
+        return true;
+    }
+
+    //
+    // Check the CTimers to see if any are using HFRC as their clock source.
+    //
+    for ( ui32CtimerNum = 0; ui32CtimerNum < MAX_CTIMERS; ui32CtimerNum++ )
+    {
+        if ( ctimer_source_hfrc(ui32CtimerNum) )
+        {
+            return true;
+        }
+    }
+
+    return false;
+
+} // timers_use_hfrc()
+
+//*****************************************************************************
+//
+//! @brief Convenience function for responding to CTimer interrupts.
+//!
+//! @param ui32Status is the interrupt status as returned by
+//! am_hal_ctimer_int_status_get()
+//!
+//! This function may be called from am_ctimer_isr() to read the status of
+//! the CTimer interrupts, determine which source caused the most recent
+//! interrupt, and call an interrupt handler function to respond. The interrupt
+//! handler to be called must be first registered with the
+//! am_hal_ctimer_int_register() function.
+//!
+//! In the event that multiple sources are active, the corresponding
+//! interrupt handlers will be called in numerical order based on interrupt def.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_int_service(uint32_t ui32Status)
+{
+    uint32_t ui32Clz;
+
+    am_hal_ctimer_handler_t pfnHandler;
+
+    ui32Status &= 0xFFFF;
+
+    while ( ui32Status )
+    {
+        //
+        // Pick one of any remaining active interrupt bits
+        //
+#ifdef __IAR_SYSTEMS_ICC__
+        ui32Clz = __CLZ(ui32Status);
+#else
+        ui32Clz = __builtin_clz(ui32Status);
+#endif
+
+        //
+        // Turn off the bit we picked in the working copy
+        //
+        ui32Status &= ~(0x80000000 >> ui32Clz);
+
+        //
+        // Check the bit handler table to see if there is an interrupt handler
+        // registered for this particular bit.
+        //
+        pfnHandler = am_hal_ctimer_ppfnHandlers[31 - ui32Clz];
+        if ( pfnHandler )
+        {
+            //
+            // If we found an interrupt handler routine, call it now.
+            //
+            pfnHandler();
+        }
+    }
+} // am_hal_ctimer_int_service()
+
+//*****************************************************************************
+//
+//! @brief Register an interrupt handler for CTimer.
+//!
+//! @param ui32Interrupt - interrupt number to assign this interrupt handler to.
+//! @param pfnHandler - Function to call when this interrupt is received.
+//!
+//! This function allows the caller to specify a function that should be called
+//! any time a Ctimer interrupt is received. Registering an
+//! interrupt handler using this function adds the function pointer to an array
+//! in SRAM. This interrupt handler will be called by am_hal_ctimer_int_service()
+//! whenever the ui32Status parameter indicates that the corresponding interrupt.
+//!
+//! To remove an interrupt handler that has already been registered, the
+//! pfnHandler parameter may be set to zero.
+//!
+//! @note This function will not have any effect unless the
+//! am_hal_ctimer_int_service() function is being used.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_int_register(uint32_t ui32Interrupt,
+                           am_hal_ctimer_handler_t pfnHandler)
+{
+    uint32_t intIdx = 0;
+
+    //
+    // Check to make sure the interrupt number is valid. (Debug builds only)
+    //
+    switch (ui32Interrupt)
+    {
+        case AM_REG_CTIMER_INTEN_CTMRA0C0INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRA0C0INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRB0C0INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRB0C0INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRA1C0INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRA1C0INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRB1C0INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRB1C0INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRA2C0INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRA2C0INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRB2C0INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRB2C0INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRA3C0INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRA3C0INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRB3C0INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRB3C0INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRA0C1INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRA0C1INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRB0C1INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRB0C1INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRA1C1INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRA1C1INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRB1C1INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRB1C1INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRA2C1INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRA2C1INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRB2C1INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRB2C1INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRA3C1INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRA3C1INT_S;
+            break;
+
+        case AM_REG_CTIMER_INTEN_CTMRB3C1INT_M:
+            intIdx = AM_REG_CTIMER_INTEN_CTMRB3C1INT_S;
+            break;
+
+        default:
+            am_hal_debug_assert_msg(false, "CTimer interrupt number out of range.");
+    }
+
+    am_hal_ctimer_ppfnHandlers[intIdx] = pfnHandler;
+
+} // am_hal_ctimer_int_register()
+
+//*****************************************************************************
+//
+//! @brief Set up the counter/timer.
+//!
+//! @param ui32TimerNumber is the number of the Timer that should be
+//! configured.
+//!
+//! @param psConfig is a pointer to a structure that holds important settings
+//! for the timer.
+//!
+//! This function should be used to perform the initial set-up of the
+//! counter-timer.
+//!
+//! @note This function will eventually be replaced by
+//! am_hal_ctimer_config_single(), which performs the same configuration
+//! without requiring a structure. Please use am_hal_ctimer_config_single() for
+//! new development.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_config(uint32_t ui32TimerNumber,
+                     am_hal_ctimer_config_t *psConfig)
+{
+    uint32_t *pui32ConfigReg;
+    uint32_t ui32ConfigVal;
+
+    //
+    // Start preparing the configuration word for this timer. The configuration
+    // values for Timer A and Timer B provided in the config structure should
+    // match the register definitions already, so we will mostly just need to
+    // OR them together.
+    //
+    ui32ConfigVal = ( (psConfig->ui32TimerAConfig)  |
+                      (psConfig->ui32TimerBConfig << 16) );
+
+    //
+    // OR in the Link bit if the timers need to be linked.
+    //
+    ui32ConfigVal |= psConfig->ui32Link ? AM_HAL_CTIMER_LINK : 0;
+
+    //
+    // Begin critical section while config registers are read and modified.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Find the correct register to write.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Write our configuration value.
+    //
+    AM_REGVAL(pui32ConfigReg) = ui32ConfigVal;
+
+    //
+    // If all of the clock sources are not HRFC disable LDO when sleeping if timers are enabled.
+    //
+    if ( timers_use_hfrc() )
+    {
+        AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 0);
+    }
+    else
+    {
+        AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 1);
+    }
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+
+} // am_hal_ctimer_config()
+
+//*****************************************************************************
+//
+//! @brief Set up the counter/timer.
+//!
+//! @param ui32TimerNumber is the number of the Timer that should be
+//! configured.
+//!
+//! @param ui32TimerSegment specifies which segment of the timer should be
+//! enabled.
+//!
+//! @param ui32Configval specifies the configuration options for the selected
+//! timer.
+//!
+//! This function should be used to perform the initial set-up of the
+//! counter-timer. It can be used to configure either a 16-bit timer (A or B) or a
+//! 32-bit timer using the BOTH option.
+//!
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! The timer's clock source, mode, interrupt, and external pin behavior are
+//! all controlled through the \e ui32Configval parameter. The valid options
+//! for ui32ConfigVal include any ORed together combination of the following:
+//!
+//! Clock configuration macros:
+//!
+//!     AM_HAL_CTIMER_HFRC_24MHZ
+//!     AM_HAL_CTIMER_LFRC_512HZ
+//!     ... etc. (See am_hal_ctimer.h for the full set of options.)
+//!
+//! Mode selection macros:
+//!
+//!     AM_HAL_CTIMER_FN_ONCE
+//!     AM_HAL_CTIMER_FN_REPEAT
+//!     AM_HAL_CTIMER_FN_PWM_ONCE
+//!     AM_HAL_CTIMER_FN_PWM_REPEAT
+//!     AM_HAL_CTIMER_FN_CONTINUOUS
+//!
+//! Interrupt control:
+//!
+//!     AM_HAL_CTIMER_INT_ENABLE
+//!
+//! Pin control:
+//!
+//!     AM_HAL_CTIMER_PIN_ENABLE
+//!     AM_HAL_CTIMER_PIN_INVERT
+//!
+//! ADC trigger (Timer 3 only):
+//!
+//!     AM_HAL_CTIMER_ADC_TRIG
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_config_single(uint32_t ui32TimerNumber,
+                            uint32_t ui32TimerSegment,
+                            uint32_t ui32ConfigVal)
+{
+    volatile uint32_t *pui32ConfigReg;
+    uint32_t ui32WriteVal;
+
+    //
+    // Find the correct register to write based on the timer number.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Begin critical section while config registers are read and modified.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Save the value that's already in the register.
+    //
+    ui32WriteVal = AM_REGVAL(pui32ConfigReg);
+
+    //
+    // If we're working with TIMERB, we need to shift our configuration value
+    // up by 16 bits.
+    //
+
+    if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB )
+    {
+        ui32ConfigVal = ((ui32ConfigVal & 0xFFFF) << 16);
+    }
+
+    //
+    // Replace part of the saved register value with the configuration value
+    // from the caller.
+    //
+    ui32WriteVal = (ui32WriteVal & ~(ui32TimerSegment)) | ui32ConfigVal;
+
+    //
+    // If we're configuring both timers, we need to set the "link" bit.
+    //
+    if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH )
+    {
+        ui32WriteVal |= AM_HAL_CTIMER_LINK;
+    }
+
+    //
+    // Write our completed configuration value.
+    //
+    AM_REGVAL(pui32ConfigReg) = ui32WriteVal;
+
+    //
+    // If all of the clock sources are not HRFC disable LDO when sleeping if timers are enabled.
+    //
+    if ( timers_use_hfrc() )
+    {
+        AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 0);
+    }
+    else
+    {
+        AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 1);
+    }
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+
+} // am_hal_ctimer_config_single()
+
+//*****************************************************************************
+//
+//! @brief Start a timer
+//!
+//! @param ui32TimerNumber is the number of the timer to enable
+//!
+//! @param ui32TimerSegment specifies which segment of the timer should be
+//! enabled.  Valid values for ui32TimerSegment are:
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! This function will enable a timer to begin incrementing. The \e
+//! ui32TimerNumber parameter selects the timer that should be enabled, for
+//! example, a 0 would target TIMER0. The \e ui32TimerSegment parameter allows
+//! the caller to individually select a segment within a timer to be enabled,
+//! such as TIMER0A, TIMER0B, or both.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_start(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
+{
+    volatile uint32_t *pui32ConfigReg;
+    uint32_t ui32ConfigVal;
+
+    //
+    // Find the correct control register.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Begin critical section while config registers are read and modified.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Read the current value.
+    //
+    ui32ConfigVal = *pui32ConfigReg;
+
+    //
+    // Clear out the "clear" bit.
+    //
+    ui32ConfigVal &= ~(ui32TimerSegment & (AM_REG_CTIMER_CTRL0_TMRA0CLR_M |
+                                           AM_REG_CTIMER_CTRL0_TMRB0CLR_M));
+
+    //
+    // Set the "enable bit"
+    //
+    ui32ConfigVal |= (ui32TimerSegment & (AM_REG_CTIMER_CTRL0_TMRA0EN_M |
+                                          AM_REG_CTIMER_CTRL0_TMRB0EN_M));
+
+    //
+    // Write the value back to the register.
+    //
+    AM_REGVAL(pui32ConfigReg) = ui32ConfigVal;
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_start()
+
+//*****************************************************************************
+//
+//! @brief Stop a timer
+//!
+//! @param ui32TimerNumber is the number of the timer to disable.
+//!
+//! @param ui32TimerSegment specifies which segment of the timer should be
+//! disabled.
+//!
+//! This function will stop the selected timer from incrementing. The \e
+//! ui32TimerNumber parameter selects the timer that should be disabled, for
+//! example, a 0 would target TIMER0. The \e ui32TimerSegment parameter allows
+//! the caller to individually select a segment within a timer to be disabled,
+//! such as TIMER0A, TIMER0B, or both.
+//!
+//! This function will stop a counter/timer from counting, but does not return
+//! the count value to 'zero'. If you would like to reset the counter back to
+//! zero, try the am_hal_ctimer_clear() function instead.
+//!
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_stop(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
+{
+    volatile uint32_t *pui32ConfigReg;
+
+    //
+    // Find the correct control register.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Clear the "enable" bit
+    //
+    AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment &
+                                   (AM_REG_CTIMER_CTRL0_TMRA0EN_M |
+                                    AM_REG_CTIMER_CTRL0_TMRB0EN_M));
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_stop()
+
+//*****************************************************************************
+//
+//! @brief Stops a timer and resets its value back to zero.
+//!
+//! @param ui32TimerNumber is the number of the timer to clear.
+//!
+//! @param ui32TimerSegment specifies which segment of the timer should be
+//! cleared.
+//!
+//! This function will stop a free-running counter-timer, reset its value to
+//! zero, and leave the timer disabled. When you would like to restart the
+//! counter, you will need to call am_hal_ctimer_start().
+//!
+//! The \e ui32TimerSegment parameter allows the caller to individually select
+//! a segment within, such as TIMER0A, TIMER0B, or both.
+//!
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_clear(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
+{
+    volatile uint32_t *pui32ConfigReg;
+
+    //
+    // Find the correct control register.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Set the "clear" bit
+    //
+    AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment &
+                                  (AM_REG_CTIMER_CTRL0_TMRA0CLR_M |
+                                   AM_REG_CTIMER_CTRL0_TMRB0CLR_M));
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_clear()
+
+//*****************************************************************************
+//
+//! @brief Returns the current free-running value of the selected timer.
+//!
+//! @param ui32TimerNumber is the number of the timer to read.
+//! @param ui32TimerSegment specifies which segment of the timer should be
+//! read.
+//!
+//! This function returns the current free-running value of the selected timer.
+//!
+//! @note When reading from a linked timer, be sure to use AM_HAL_CTIMER both
+//! for the segment argument.
+//!
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! @return Current timer value.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ctimer_read(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
+{
+    volatile uint32_t ui32Value = 0;
+    uint32_t ui32Values[3] = {0};
+    uint32_t ui32TimerAddrTbl[4] =
+    {
+        REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR0_O,
+        REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR1_O,
+        REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR2_O,
+        REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR3_O
+    };
+
+    //
+    // Read the timer with back2back reads. This is a workaround for a clock
+    // domain synchronization issue. Some timer bits may be slow to increment,
+    // which means that the value in the timer register will sometimes be
+    // wrong.
+    //
+    // The architecture guarantees that:
+    //
+    // 1) If the timer is running at a speed close to the core frequency, the
+    // core and timer clock domains will be synchronized, and no "bad" reads
+    // will happen.
+    //
+    // 2) Bad reads will only happen if the core reads the timer register while
+    // the timer value is transitioning from one count to the next.
+    //
+    // 3) The timer will resolve to the correct value within one 24 MHz clock
+    // cycle.
+    //
+    // If we read the timer three times in a row with back-to-back load
+    // instructions, then we can guarantee that the timer will only have time
+    // to increment once, and that only one of the three reads can be wrong.
+    // This routine will perform the back-to-back reads and return all three
+    // values. The rest of this fuction determines which value we should
+    // actually use.
+    //
+    back2back_reads(ui32TimerAddrTbl[ui32TimerNumber], ui32Values);
+
+    //
+    // Shift or mask the values based on the given timer segment.
+    //
+    if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB )
+    {
+        ui32Values[0] >>= 16;
+        ui32Values[1] >>= 16;
+        ui32Values[2] >>= 16;
+    }
+    else if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA )
+    {
+        ui32Values[0] &= 0xFFFF;
+        ui32Values[1] &= 0xFFFF;
+        ui32Values[2] &= 0xFFFF;
+    }
+
+    //
+    // Now, we'll figure out which of the three values is the correct time.
+    //
+    if (ui32Values[0] == ui32Values[1])
+    {
+        //
+        // If the first two values match, then neither one was a bad read.
+        // We'll take this as the current time.
+        //
+        ui32Value = ui32Values[1];
+    }
+    else
+    {
+        //
+        // If the first two values didn't match, then one of them might be bad.
+        // If one of the first two values is bad, then the third one should
+        // always be correct. We'll take the third value as the correct time.
+        //
+        ui32Value = ui32Values[2];
+
+        //
+        // If all of the statements about the architecture are true, the third
+        // value should be correct, and it should always be within one count of
+        // either the first or the second value.
+        //
+        // Just in case, we'll check against the previous two values to make
+        // sure that our final answer was reasonable. If it isn't, we will
+        // flag it as a "bad read", and fail this assert statement.
+        //
+        // This shouldn't ever happen, and it hasn't ever happened in any of
+        // our tests so far.
+        //
+        am_hal_debug_assert_msg((adjacent(ui32Values[1], ui32Values[2]) ||
+                                 adjacent(ui32Values[0], ui32Values[2])),
+                                "Bad CTIMER read");
+    }
+
+    return ui32Value;
+} // am_hal_ctimer_read()
+
+//*****************************************************************************
+//
+//! @brief Enable output to the timer pin
+//!
+//! @param ui32TimerNumber is the number of the timer to configure.
+//!
+//! @param ui32TimerSegment specifies which segment of the timer to use.
+//!
+//! This function will enable the output pin for the selected timer. The \e
+//! ui32TimerSegment parameter allows the caller to individually select a
+//! segment within, such as TIMER0A, TIMER0B, or both.
+//!
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_pin_enable(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
+{
+    volatile uint32_t *pui32ConfigReg;
+
+    //
+    // Find the correct control register.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Set the pin enable bit
+    //
+    AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment &
+                                  (AM_REG_CTIMER_CTRL0_TMRA0PE_M |
+                                   AM_REG_CTIMER_CTRL0_TMRB0PE_M));
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_pin_enable()
+
+//*****************************************************************************
+//
+//! @brief Disable the output pin.
+//!
+//! @param ui32TimerNumber is the number of the timer to configure.
+//!
+//! @param ui32TimerSegment specifies which segment of the timer to use.
+//!
+//! This function will disable the output pin for the selected timer. The \e
+//! ui32TimerSegment parameter allows the caller to individually select a
+//! segment within, such as TIMER0A, TIMER0B, or both.
+//!
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
+{
+    volatile uint32_t *pui32ConfigReg;
+
+    //
+    // Find the correct control register.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Clear the pin enable bit
+    //
+    AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment &
+                                   (AM_REG_CTIMER_CTRL0_TMRA0PE_M |
+                                    AM_REG_CTIMER_CTRL0_TMRB0PE_M));
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_pin_disable()
+
+//*****************************************************************************
+//
+//! @brief Set the polarity of the output pin.
+//!
+//! @param ui32TimerNumber is the number of the timer to configure.
+//!
+//! @param ui32TimerSegment specifies which segment of the timer to use.
+//!
+//! @param bInvertOutpt determines whether the output should be inverted. If
+//! true, the timer output pin for the selected timer segment will be
+//! inverted.
+//!
+//! This function will set the polarity of the the output pin for the selected
+//! timer. The \e ui32TimerSegment parameter allows the caller to individually
+//! select a segment within, such as TIMER0A, TIMER0B, or both.
+//!
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_pin_invert(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment,
+                         bool bInvertOutput)
+{
+    volatile uint32_t *pui32ConfigReg;
+
+    //
+    // Find the correct control register.
+    //
+    pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                  (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Figure out if we're supposed to be setting or clearing the polarity bit.
+    //
+    if ( bInvertOutput )
+    {
+        //
+        // Set the polarity bit to invert the output.
+        //
+        AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment &
+                                      (AM_REG_CTIMER_CTRL0_TMRA0POL_M |
+                                       AM_REG_CTIMER_CTRL0_TMRB0POL_M));
+    }
+    else
+    {
+        //
+        // Clear the polarity bit.
+        //
+        AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment &
+                                       (AM_REG_CTIMER_CTRL0_TMRA0POL_M |
+                                        AM_REG_CTIMER_CTRL0_TMRB0POL_M));
+    }
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_pin_invert()
+
+//*****************************************************************************
+//
+//! @brief Set a compare register.
+//!
+//! @param ui32TimerNumber is the number of the timer to configure.
+//!
+//! @param ui32TimerSegment specifies which segment of the timer to use.
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! @param ui32CompareReg specifies which compare register should be set
+//! (either 0 or 1)
+//!
+//! @param ui32Value is the value that should be written to the compare
+//! register.
+//!
+//! This function allows the caller to set the values in the compare registers
+//! for a timer. These registers control the period and duty cycle of the
+//! timers and their associated output pins. Please see the datasheet for
+//! further information on the operation of the compare registers. The \e
+//! ui32TimerSegment parameter allows the caller to individually select a
+//! segment within, such as TIMER0A, TIMER0B, or both.
+//!
+//! @note For simple manipulations of period or duty cycle for timers and PWMs,
+//! you may find it easier to use the am_hal_ctimer_period_set() function.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment,
+                          uint32_t ui32CompareReg, uint32_t ui32Value)
+{
+    volatile uint32_t *pui32CmprRegA, *pui32CmprRegB;
+    uint32_t ui32CmprRegA, ui32CmprRegB;
+
+    //
+    // Find the correct compare register to write.
+    // Assume A or BOTH.  We'll change later if B.
+    //
+    pui32CmprRegA = (uint32_t *)(AM_REG_CTIMERn(0) +
+                                 AM_REG_CTIMER_CMPRA0_O +
+                                 (ui32TimerNumber * TIMER_OFFSET));
+    pui32CmprRegB = pui32CmprRegA + CTIMER_CMPR_OFFSET;
+
+    //
+    // Write the compare register with the selected value.
+    // Begin critical section while CMPR registers are modified.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    ui32CmprRegA = *pui32CmprRegA;
+    ui32CmprRegB = *pui32CmprRegB;
+
+    if ( ui32CompareReg == 1 )
+    {
+        //
+        // CMPR reg 1
+        // Get the lower 16b (but may not be used if TIMERB).
+        //
+        ui32CmprRegA = ( (ui32CmprRegA & AM_REG_CTIMER_CMPRA0_CMPR0A0_M) |
+                          AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Value & 0xFFFF) );
+
+        //
+        // Get the upper 16b (but may not be used if TIMERA)
+        //
+        ui32CmprRegB = ( (ui32CmprRegB & AM_REG_CTIMER_CMPRA0_CMPR0A0_M) |
+                          AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Value >> 16) );
+    }
+    else
+    {
+        //
+        // CMPR reg 0
+        // Get the lower 16b (but may not be used if TIMERB)
+        //
+        ui32CmprRegA = ( (ui32CmprRegA & AM_REG_CTIMER_CMPRA0_CMPR1A0_M) |
+                         AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Value & 0xFFFF) );
+
+        //
+        // Set the upper 16b (but may not be used if TIMERA)
+        //
+        ui32CmprRegB = ( (ui32CmprRegB & AM_REG_CTIMER_CMPRA0_CMPR1A0_M) |
+                         AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Value >> 16) );
+    }
+
+    if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB )
+    {
+        *pui32CmprRegB = ui32CmprRegB;
+    }
+    else
+    {
+        //
+        // It's TIMERA or BOTH.
+        //
+        *pui32CmprRegA = ui32CmprRegA;
+
+        if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH )
+        {
+            *pui32CmprRegB = ui32CmprRegB;
+        }
+    }
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_compare_set()
+
+//*****************************************************************************
+//
+//! @brief Set the period and duty cycle of a timer.
+//!
+//! @param ui32TimerNumber is the number of the timer to configure.
+//!
+//! @param ui32TimerSegment specifies which segment of the timer to use.
+//!
+//! @param ui32Period specifies the desired period.  This parameter effectively
+//! specifies the CTIMER CMPR field(s). The CMPR fields are handled in hardware
+//! as (n+1) values, therefore ui32Period is actually specified as 1 less than
+//! the desired period. Finally, as mentioned in the data sheet, the CMPR fields
+//! cannot be 0 (a value of 1), so neither can ui32Period be 0.
+//!
+//! @param ui32OnTime set the number of clocks where the output signal is high.
+//!
+//! This function should be used for simple manipulations of the period and
+//! duty cycle of a counter/timer. To set the period and/or duty cycle of a
+//! linked timer pair, use AM_HAL_CTIMER_BOTH as the timer segment argument. If
+//! you would like to set the period and/or duty cycle for both TIMERA and
+//! TIMERB you will need to call this function twice: once for TIMERA, and once
+//! for TIMERB.
+//!
+//! Valid values for ui32TimerSegment are:
+//!
+//!     AM_HAL_CTIMER_TIMERA
+//!     AM_HAL_CTIMER_TIMERB
+//!     AM_HAL_CTIMER_BOTH
+//!
+//! @note The ui32OnTime parameter will only work if the timer is currently
+//! operating in one of the PWM modes.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_period_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment,
+                         uint32_t ui32Period, uint32_t ui32OnTime)
+{
+    volatile uint32_t *pui32ControlReg;
+    volatile uint32_t *pui32CompareRegA;
+    volatile uint32_t *pui32CompareRegB;
+    uint32_t ui32Mode, ui32Comp0, ui32Comp1;
+
+    //
+    // Find the correct control register to pull the function select field
+    // from.
+    //
+    pui32ControlReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O +
+                                   (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Find the correct compare registers to write.
+    //
+    pui32CompareRegA = (uint32_t *)(AM_REG_CTIMERn(0) +
+                                    AM_REG_CTIMER_CMPRA0_O +
+                                    (ui32TimerNumber * TIMER_OFFSET));
+
+    pui32CompareRegB = (uint32_t *)(AM_REG_CTIMERn(0) +
+                                    AM_REG_CTIMER_CMPRB0_O +
+                                    (ui32TimerNumber * TIMER_OFFSET));
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Extract the timer mode from the register based on the ui32TimerSegment
+    // selected by the user.
+    //
+    ui32Mode = *pui32ControlReg;
+    if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB )
+    {
+        ui32Mode = ui32Mode >> 16;
+    }
+
+    //
+    // Mask to get to the bits we're interested in.
+    //
+    ui32Mode = ui32Mode & AM_REG_CTIMER_CTRL0_TMRA0FN_M;
+
+    //
+    // If the mode is a PWM mode, we'll need to calculate the correct CMPR0 and
+    // CMPR1 values here.
+    //
+    if (ui32Mode == AM_HAL_CTIMER_FN_PWM_ONCE   ||
+        ui32Mode == AM_HAL_CTIMER_FN_PWM_REPEAT)
+    {
+        ui32Comp0 = ui32Period - ui32OnTime;
+        ui32Comp1 = ui32Period;
+    }
+    else
+    {
+        ui32Comp0 = ui32Period;
+        ui32Comp1 = 0;
+    }
+
+    //
+    // Based on the timer segment argument, write the calculated Compare 0 and
+    // Compare 1 values to the correct halves of the correct registers.
+    //
+    if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA )
+    {
+        //
+        // For timer A, write the values to the TIMERA compare register.
+        //
+        *pui32CompareRegA = (AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Comp0) |
+                             AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Comp1));
+    }
+    else if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB )
+    {
+        //
+        // For timer B, write the values to the TIMERA compare register.
+        //
+        *pui32CompareRegB = (AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Comp0) |
+                             AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Comp1));
+    }
+    else
+    {
+        //
+        // For the linked case, write the lower halves of the values to the
+        // TIMERA compare register, and the upper halves to the TIMERB compare
+        // register.
+        //
+        *pui32CompareRegA = (AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Comp0) |
+                             AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Comp1));
+
+        *pui32CompareRegB = (AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Comp0 >> 16) |
+                             AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Comp1 >> 16));
+    }
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_period_set()
+
+//*****************************************************************************
+//
+//! @brief Enable the TIMERA3 ADC trigger
+//!
+//! This function enables the ADC trigger within TIMERA3.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_adc_trigger_enable(void)
+{
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Enable the ADC trigger.
+    //
+    AM_REGn(CTIMER, 0, CTRL3) |= AM_REG_CTIMER_CTRL3_ADCEN_M;
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_adc_trigger_enable()
+
+//*****************************************************************************
+//
+//! @brief Disable the TIMERA3 ADC trigger
+//!
+//! This function disables the ADC trigger within TIMERA3.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_adc_trigger_disable(void)
+{
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Disable the ADC trigger.
+    //
+    AM_REGn(CTIMER, 0, CTRL3) &= ~AM_REG_CTIMER_CTRL3_ADCEN_M;
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_adc_trigger_disable()
+
+//*****************************************************************************
+//
+//! @brief Enables the selected timer interrupt.
+//!
+//! @param ui32Interrupt is the interrupt to be used.
+//!
+//! This function will enable the selected interrupts in the main CTIMER
+//! interrupt enable register. In order to receive an interrupt from a timer,
+//! you will need to enable the interrupt for that timer in this main register,
+//! as well as in the timer control register (accessible though
+//! am_hal_ctimer_config()), and in the NVIC.
+//!
+//! ui32Interrupt should be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_CTIMER_INT_TIMERA0C0
+//!     AM_HAL_CTIMER_INT_TIMERA0C1
+//!     AM_HAL_CTIMER_INT_TIMERB0C0
+//!     AM_HAL_CTIMER_INT_TIMERB0C1
+//!     AM_HAL_CTIMER_INT_TIMERA1C0
+//!     AM_HAL_CTIMER_INT_TIMERA1C1
+//!     AM_HAL_CTIMER_INT_TIMERB1C0
+//!     AM_HAL_CTIMER_INT_TIMERB1C1
+//!     AM_HAL_CTIMER_INT_TIMERA2C0
+//!     AM_HAL_CTIMER_INT_TIMERA2C1
+//!     AM_HAL_CTIMER_INT_TIMERB2C0
+//!     AM_HAL_CTIMER_INT_TIMERB2C1
+//!     AM_HAL_CTIMER_INT_TIMERA3C0
+//!     AM_HAL_CTIMER_INT_TIMERA3C1
+//!     AM_HAL_CTIMER_INT_TIMERB3C0
+//!     AM_HAL_CTIMER_INT_TIMERB3C1
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_int_enable(uint32_t ui32Interrupt)
+{
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Enable the interrupt at the module level.
+    //
+    AM_REGn(CTIMER, 0, INTEN) |= ui32Interrupt;
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_int_enable()
+
+//*****************************************************************************
+//
+//! @brief Return the enabled timer interrupts.
+//!
+//! This function will return all enabled interrupts in the main CTIMER
+//! interrupt enable register.
+//!
+//! @return return enabled interrupts. This will be a logical or of:
+//!
+//!     AM_HAL_CTIMER_INT_TIMERA0C0
+//!     AM_HAL_CTIMER_INT_TIMERA0C1
+//!     AM_HAL_CTIMER_INT_TIMERB0C0
+//!     AM_HAL_CTIMER_INT_TIMERB0C1
+//!     AM_HAL_CTIMER_INT_TIMERA1C0
+//!     AM_HAL_CTIMER_INT_TIMERA1C1
+//!     AM_HAL_CTIMER_INT_TIMERB1C0
+//!     AM_HAL_CTIMER_INT_TIMERB1C1
+//!     AM_HAL_CTIMER_INT_TIMERA2C0
+//!     AM_HAL_CTIMER_INT_TIMERA2C1
+//!     AM_HAL_CTIMER_INT_TIMERB2C0
+//!     AM_HAL_CTIMER_INT_TIMERB2C1
+//!     AM_HAL_CTIMER_INT_TIMERA3C0
+//!     AM_HAL_CTIMER_INT_TIMERA3C1
+//!     AM_HAL_CTIMER_INT_TIMERB3C0
+//!     AM_HAL_CTIMER_INT_TIMERB3C1
+//!
+//! @return Return the enabled timer interrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ctimer_int_enable_get(void)
+{
+    //
+    // Return enabled interrupts.
+    //
+    return AM_REGn(CTIMER, 0, INTEN);
+} // am_hal_ctimer_int_enable_get()
+
+//*****************************************************************************
+//
+//! @brief Disables the selected timer interrupt.
+//!
+//! @param ui32Interrupt is the interrupt to be used.
+//!
+//! This function will disable the selected interrupts in the main CTIMER
+//! interrupt register.
+//!
+//! ui32Interrupt should be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_CTIMER_INT_TIMERA0C0
+//!     AM_HAL_CTIMER_INT_TIMERA0C1
+//!     AM_HAL_CTIMER_INT_TIMERB0C0
+//!     AM_HAL_CTIMER_INT_TIMERB0C1
+//!     AM_HAL_CTIMER_INT_TIMERA1C0
+//!     AM_HAL_CTIMER_INT_TIMERA1C1
+//!     AM_HAL_CTIMER_INT_TIMERB1C0
+//!     AM_HAL_CTIMER_INT_TIMERB1C1
+//!     AM_HAL_CTIMER_INT_TIMERA2C0
+//!     AM_HAL_CTIMER_INT_TIMERA2C1
+//!     AM_HAL_CTIMER_INT_TIMERB2C0
+//!     AM_HAL_CTIMER_INT_TIMERB2C1
+//!     AM_HAL_CTIMER_INT_TIMERA3C0
+//!     AM_HAL_CTIMER_INT_TIMERA3C1
+//!     AM_HAL_CTIMER_INT_TIMERB3C0
+//!     AM_HAL_CTIMER_INT_TIMERB3C1
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_int_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Disable the interrupt at the module level.
+    //
+    AM_REGn(CTIMER, 0, INTEN) &= ~ui32Interrupt;
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+} // am_hal_ctimer_int_disable()
+
+//*****************************************************************************
+//
+//! @brief Clears the selected timer interrupt.
+//!
+//! @param ui32Interrupt is the interrupt to be used.
+//!
+//! This function will clear the selected interrupts in the main CTIMER
+//! interrupt register.
+//!
+//! ui32Interrupt should be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_CTIMER_INT_TIMERA0C0
+//!     AM_HAL_CTIMER_INT_TIMERA0C1
+//!     AM_HAL_CTIMER_INT_TIMERB0C0
+//!     AM_HAL_CTIMER_INT_TIMERB0C1
+//!     AM_HAL_CTIMER_INT_TIMERA1C0
+//!     AM_HAL_CTIMER_INT_TIMERA1C1
+//!     AM_HAL_CTIMER_INT_TIMERB1C0
+//!     AM_HAL_CTIMER_INT_TIMERB1C1
+//!     AM_HAL_CTIMER_INT_TIMERA2C0
+//!     AM_HAL_CTIMER_INT_TIMERA2C1
+//!     AM_HAL_CTIMER_INT_TIMERB2C0
+//!     AM_HAL_CTIMER_INT_TIMERB2C1
+//!     AM_HAL_CTIMER_INT_TIMERA3C0
+//!     AM_HAL_CTIMER_INT_TIMERA3C1
+//!     AM_HAL_CTIMER_INT_TIMERB3C0
+//!     AM_HAL_CTIMER_INT_TIMERB3C1
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Disable the interrupt at the module level.
+    //
+    AM_REGn(CTIMER, 0, INTCLR) = ui32Interrupt;
+} // am_hal_ctimer_int_clear()
+
+//*****************************************************************************
+//
+//! @brief Sets the selected timer interrupt.
+//!
+//! @param ui32Interrupt is the interrupt to be used.
+//!
+//! This function will set the selected interrupts in the main CTIMER
+//! interrupt register.
+//!
+//! ui32Interrupt should be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_CTIMER_INT_TIMERA0C0
+//!     AM_HAL_CTIMER_INT_TIMERA0C1
+//!     AM_HAL_CTIMER_INT_TIMERB0C0
+//!     AM_HAL_CTIMER_INT_TIMERB0C1
+//!     AM_HAL_CTIMER_INT_TIMERA1C0
+//!     AM_HAL_CTIMER_INT_TIMERA1C1
+//!     AM_HAL_CTIMER_INT_TIMERB1C0
+//!     AM_HAL_CTIMER_INT_TIMERB1C1
+//!     AM_HAL_CTIMER_INT_TIMERA2C0
+//!     AM_HAL_CTIMER_INT_TIMERA2C1
+//!     AM_HAL_CTIMER_INT_TIMERB2C0
+//!     AM_HAL_CTIMER_INT_TIMERB2C1
+//!     AM_HAL_CTIMER_INT_TIMERA3C0
+//!     AM_HAL_CTIMER_INT_TIMERA3C1
+//!     AM_HAL_CTIMER_INT_TIMERB3C0
+//!     AM_HAL_CTIMER_INT_TIMERB3C1
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ctimer_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Set the interrupts.
+    //
+    AM_REGn(CTIMER, 0, INTSET) = ui32Interrupt;
+} // am_hal_ctimer_int_set()
+
+//*****************************************************************************
+//
+//! @brief Returns either the enabled or raw timer interrupt status.
+//!
+//! This function will return the timer interrupt status.
+//!
+//! @return bEnabledOnly if true returns the status of the enabled interrupts
+//! only.
+//!
+//! The return value will be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_CTIMER_INT_TIMERA0C0
+//!     AM_HAL_CTIMER_INT_TIMERA0C1
+//!     AM_HAL_CTIMER_INT_TIMERB0C0
+//!     AM_HAL_CTIMER_INT_TIMERB0C1
+//!     AM_HAL_CTIMER_INT_TIMERA1C0
+//!     AM_HAL_CTIMER_INT_TIMERA1C1
+//!     AM_HAL_CTIMER_INT_TIMERB1C0
+//!     AM_HAL_CTIMER_INT_TIMERB1C1
+//!     AM_HAL_CTIMER_INT_TIMERA2C0
+//!     AM_HAL_CTIMER_INT_TIMERA2C1
+//!     AM_HAL_CTIMER_INT_TIMERB2C0
+//!     AM_HAL_CTIMER_INT_TIMERB2C1
+//!     AM_HAL_CTIMER_INT_TIMERA3C0
+//!     AM_HAL_CTIMER_INT_TIMERA3C1
+//!     AM_HAL_CTIMER_INT_TIMERB3C0
+//!     AM_HAL_CTIMER_INT_TIMERB3C1
+//!
+//! @return Returns either the timer interrupt status.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ctimer_int_status_get(bool bEnabledOnly)
+{
+    //
+    // Return the desired status.
+    //
+
+    if ( bEnabledOnly )
+    {
+        uint32_t u32RetVal;
+
+        //
+        // Begin critical section.
+        //
+        AM_CRITICAL_BEGIN_ASM
+
+        u32RetVal  = AM_REGn(CTIMER, 0, INTSTAT);
+        u32RetVal &= AM_REGn(CTIMER, 0, INTEN);
+
+        //
+        // Done with critical section.
+        //
+        AM_CRITICAL_END_ASM
+
+        return u32RetVal;
+    }
+    else
+    {
+        return AM_REGn(CTIMER, 0, INTSTAT);
+    }
+} // am_hal_ctimer_int_status_get()
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h
new file mode 100644
index 0000000000..fa1ebe16c4
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h
@@ -0,0 +1,278 @@
+//*****************************************************************************
+//
+//  am_hal_ctimer.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the CTIMER.
+//!
+//! @addtogroup ctimer2 Counter/Timer (CTIMER)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_CTIMER_H
+#define AM_HAL_CTIMER_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! Number of timers
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_TIMERS_NUM    4
+
+//*****************************************************************************
+//
+//! Timer offset value
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_TIMER_OFFSET  (AM_REG_CTIMER_TMR1_O - AM_REG_CTIMER_TMR0_O)
+
+//*****************************************************************************
+//
+//! @name Interrupt Status Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to set and clear interrupt bits
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_INT_TIMERA0C0         AM_REG_CTIMER_INTEN_CTMRA0C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERA0C1         AM_REG_CTIMER_INTEN_CTMRA0C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERA1C0         AM_REG_CTIMER_INTEN_CTMRA1C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERA1C1         AM_REG_CTIMER_INTEN_CTMRA1C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERA2C0         AM_REG_CTIMER_INTEN_CTMRA2C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERA2C1         AM_REG_CTIMER_INTEN_CTMRA2C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERA3C0         AM_REG_CTIMER_INTEN_CTMRA3C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERA3C1         AM_REG_CTIMER_INTEN_CTMRA3C1INT_M
+
+#define AM_HAL_CTIMER_INT_TIMERB0C0         AM_REG_CTIMER_INTEN_CTMRB0C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERB0C1         AM_REG_CTIMER_INTEN_CTMRB0C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERB1C0         AM_REG_CTIMER_INTEN_CTMRB1C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERB1C1         AM_REG_CTIMER_INTEN_CTMRB1C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERB2C0         AM_REG_CTIMER_INTEN_CTMRB2C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERB2C1         AM_REG_CTIMER_INTEN_CTMRB2C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERB3C0         AM_REG_CTIMER_INTEN_CTMRB3C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERB3C1         AM_REG_CTIMER_INTEN_CTMRB3C1INT_M
+
+//
+// Deprecated, use the newer macros above.
+//
+#define AM_HAL_CTIMER_INT_TIMERA0           AM_HAL_CTIMER_INT_TIMERA0C0
+#define AM_HAL_CTIMER_INT_TIMERB0           AM_HAL_CTIMER_INT_TIMERB0C0
+#define AM_HAL_CTIMER_INT_TIMERA1           AM_HAL_CTIMER_INT_TIMERA1C0
+#define AM_HAL_CTIMER_INT_TIMERB1           AM_HAL_CTIMER_INT_TIMERB1C0
+#define AM_HAL_CTIMER_INT_TIMERA2           AM_HAL_CTIMER_INT_TIMERA2C0
+#define AM_HAL_CTIMER_INT_TIMERB2           AM_HAL_CTIMER_INT_TIMERB2C0
+#define AM_HAL_CTIMER_INT_TIMERA3           AM_HAL_CTIMER_INT_TIMERA3C0
+#define AM_HAL_CTIMER_INT_TIMERB3           AM_HAL_CTIMER_INT_TIMERB3C0
+//! @}
+
+//*****************************************************************************
+//
+//! @name Configuration options
+//! @brief Configuration options for \e am_hal_ctimer_config_t
+//!
+//! These options are to be used with the \e am_hal_ctimer_config_t structure
+//! used by \e am_hal_ctimer_config
+//!  @{
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_CLK_PIN               AM_REG_CTIMER_CTRL0_TMRA0CLK(0x0)
+#define AM_HAL_CTIMER_HFRC_12MHZ            AM_REG_CTIMER_CTRL0_TMRA0CLK(0x1)
+#define AM_HAL_CTIMER_HFRC_3MHZ             AM_REG_CTIMER_CTRL0_TMRA0CLK(0x2)
+#define AM_HAL_CTIMER_HFRC_187_5KHZ         AM_REG_CTIMER_CTRL0_TMRA0CLK(0x3)
+#define AM_HAL_CTIMER_HFRC_47KHZ            AM_REG_CTIMER_CTRL0_TMRA0CLK(0x4)
+#define AM_HAL_CTIMER_HFRC_12KHZ            AM_REG_CTIMER_CTRL0_TMRA0CLK(0x5)
+#define AM_HAL_CTIMER_XT_32_768KHZ          AM_REG_CTIMER_CTRL0_TMRA0CLK(0x6)
+#define AM_HAL_CTIMER_XT_16_384KHZ          AM_REG_CTIMER_CTRL0_TMRA0CLK(0x7)
+#define AM_HAL_CTIMER_XT_2_048KHZ           AM_REG_CTIMER_CTRL0_TMRA0CLK(0x8)
+#define AM_HAL_CTIMER_XT_256HZ              AM_REG_CTIMER_CTRL0_TMRA0CLK(0x9)
+#define AM_HAL_CTIMER_LFRC_512HZ            AM_REG_CTIMER_CTRL0_TMRA0CLK(0xA)
+#define AM_HAL_CTIMER_LFRC_32HZ             AM_REG_CTIMER_CTRL0_TMRA0CLK(0xB)
+#define AM_HAL_CTIMER_LFRC_1HZ              AM_REG_CTIMER_CTRL0_TMRA0CLK(0xC)
+#define AM_HAL_CTIMER_LFRC_1_16HZ           AM_REG_CTIMER_CTRL0_TMRA0CLK(0xD)
+#define AM_HAL_CTIMER_RTC_100HZ             AM_REG_CTIMER_CTRL0_TMRA0CLK(0xE)
+#define AM_HAL_CTIMER_HCLK                  AM_REG_CTIMER_CTRL0_TMRA0CLK(0xF)
+#define AM_HAL_CTIMER_BUCK                  AM_REG_CTIMER_CTRL0_TMRA0CLK(0x10)
+//! @}
+
+//*****************************************************************************
+//
+// Timer function macros.
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_FN_ONCE               AM_REG_CTIMER_CTRL0_TMRA0FN(0)
+#define AM_HAL_CTIMER_FN_REPEAT             AM_REG_CTIMER_CTRL0_TMRA0FN(1)
+#define AM_HAL_CTIMER_FN_PWM_ONCE           AM_REG_CTIMER_CTRL0_TMRA0FN(2)
+#define AM_HAL_CTIMER_FN_PWM_REPEAT         AM_REG_CTIMER_CTRL0_TMRA0FN(3)
+#define AM_HAL_CTIMER_FN_CONTINUOUS         AM_REG_CTIMER_CTRL0_TMRA0FN(4)
+
+//*****************************************************************************
+//
+// Half-timer options.
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_INT_ENABLE            AM_REG_CTIMER_CTRL0_TMRA0IE0_M
+#define AM_HAL_CTIMER_PIN_ENABLE            AM_REG_CTIMER_CTRL0_TMRA0PE_M
+#define AM_HAL_CTIMER_PIN_INVERT            AM_REG_CTIMER_CTRL0_TMRA0POL_M
+#define AM_HAL_CTIMER_CLEAR                 AM_REG_CTIMER_CTRL0_TMRA0CLR_M
+
+//*****************************************************************************
+//
+// Additional timer options.
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_LINK                  AM_REG_CTIMER_CTRL0_CTLINK0_M
+#define AM_HAL_CTIMER_ADC_TRIG              AM_REG_CTIMER_CTRL3_ADCEN_M
+
+//*****************************************************************************
+//
+// Timer selection macros.
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_TIMERA                0x0000FFFF
+#define AM_HAL_CTIMER_TIMERB                0xFFFF0000
+#define AM_HAL_CTIMER_BOTH                  0xFFFFFFFF
+//! @}
+
+//*****************************************************************************
+//
+// Timer configuration structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Set to 1 to operate this timer as a 32-bit timer instead of two 16-bit
+    //! timers.
+    //
+    uint32_t ui32Link;
+
+    //
+    //! Configuration options for TIMERA
+    //
+    uint32_t ui32TimerAConfig;
+
+    //
+    //! Configuration options for TIMERB
+    //
+    uint32_t ui32TimerBConfig;
+
+}
+am_hal_ctimer_config_t;
+
+//*****************************************************************************
+//
+// Function pointer type for CTimer interrupt handlers.
+//
+//*****************************************************************************
+typedef void (*am_hal_ctimer_handler_t)(void);
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_ctimer_config(uint32_t ui32TimerNumber,
+                                 am_hal_ctimer_config_t *psConfig);
+
+extern void am_hal_ctimer_config_single(uint32_t ui32TimerNumber,
+                                        uint32_t ui32TimerSegment,
+                                        uint32_t ui32ConfigVal);
+
+extern void am_hal_ctimer_start(uint32_t ui32TimerNumber,
+                                uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_stop(uint32_t ui32TimerNumber,
+                               uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_clear(uint32_t ui32TimerNumber,
+                                uint32_t ui32TimerSegment);
+
+extern uint32_t am_hal_ctimer_read(uint32_t ui32TimerNumber,
+                                   uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_pin_enable(uint32_t ui32TimerNumber,
+                                     uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber,
+                                      uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_pin_invert(uint32_t ui32TimerNumber,
+                                     uint32_t ui32TimerSegment,
+                                     bool bInvertOutput);
+
+extern void am_hal_ctimer_compare_set(uint32_t ui32TimerNumber,
+                                      uint32_t ui32TimerSegment,
+                                      uint32_t ui32CompareReg,
+                                      uint32_t ui32Value);
+
+extern void am_hal_ctimer_period_set(uint32_t ui32TimerNumber,
+                                     uint32_t ui32TimerSegment,
+                                     uint32_t ui32Period,
+                                     uint32_t ui32OnTime);
+
+extern void am_hal_ctimer_adc_trigger_enable(void);
+extern void am_hal_ctimer_adc_trigger_disable(void);
+extern void am_hal_ctimer_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ctimer_int_enable_get(void);
+extern void am_hal_ctimer_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_ctimer_int_set(uint32_t ui32Interrupt);
+extern void am_hal_ctimer_int_clear(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ctimer_int_status_get(bool bEnabledOnly);
+extern void am_hal_ctimer_int_register(uint32_t ui32Interrupt,
+                                       am_hal_ctimer_handler_t pfnHandler);
+extern void am_hal_ctimer_int_service(uint32_t ui32Status);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_CTIMER_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c
new file mode 100644
index 0000000000..4078b5a5a0
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c
@@ -0,0 +1,81 @@
+//*****************************************************************************
+//
+//  am_hal_debug.c
+//! @file
+//!
+//! @brief Useful functions for debugging.
+//!
+//! These functions and macros were created to assist with debugging. They are
+//! intended to be as unintrusive as possible and designed to be removed from
+//! the compilation of a project when they are no longer needed.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Default implementation of a failed ASSERT statement.
+//!
+//! @param pcFile is the name of the source file where the error occurred.
+//! @param ui32Line is the line number where the error occurred.
+//! @param pcMessage is an optional message describing the failure.
+//!
+//! This function is called by am_hal_debug_assert() macro when the supplied
+//! condition is not true. The implementation here simply halts the application
+//! for further analysis. Individual applications may define their own
+//! implementations of am_hal_debug_error() to provide more detailed feedback
+//! about the failed am_hal_debug_assert() statement.
+//!
+//! @return
+//
+//*****************************************************************************
+#if defined (__IAR_SYSTEMS_ICC__)
+__weak void
+#else
+void __attribute__((weak))
+#endif
+am_hal_debug_error(const char *pcFile, uint32_t ui32Line, const char *pcMessage)
+{
+    //
+    // Halt for analysis.
+    //
+    while(1);
+}
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h
new file mode 100644
index 0000000000..a482799c4f
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h
@@ -0,0 +1,89 @@
+//*****************************************************************************
+//
+//  am_hal_debug.h
+//! @file
+//!
+//! @brief Useful macros for debugging.
+//!
+//! These functions and macros were created to assist with debugging. They are
+//! intended to be as unintrusive as possible and designed to be removed from
+//! the compilation of a project when they are no longer needed.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_DEBUG_H
+#define AM_HAL_DEBUG_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Debug assert macros.
+//
+//*****************************************************************************
+#ifndef AM_HAL_DEBUG_NO_ASSERT
+
+#define am_hal_debug_assert_msg(bCondition, pcMessage)                        \
+    if ( !(bCondition))  am_hal_debug_error(__FILE__, __LINE__, pcMessage)
+
+#define am_hal_debug_assert(bCondition)                                       \
+    if ( !(bCondition))  am_hal_debug_error(__FILE__, __LINE__, 0)
+
+#else
+
+#define am_hal_debug_assert_msg(bCondition, pcMessage)
+#define am_hal_debug_assert(bCondition)
+
+#endif // AM_DEBUG_ASSERT
+
+//*****************************************************************************
+//
+// External function prototypes.
+//
+//*****************************************************************************
+extern void am_hal_debug_error(const char *pcFile, uint32_t ui32Line,
+                               const char *pcMessage);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_DEBUG_H
+
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c
new file mode 100644
index 0000000000..cd38da812c
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c
@@ -0,0 +1,1449 @@
+//*****************************************************************************
+//
+//  am_hal_flash.c
+//! @file
+//!
+//! @brief Functions for performing Flash operations.
+//!
+//! @addtogroup flash2 Flash
+//! @ingroup apollo2hal
+//!
+//! IMPORTANT: Interrupts are active during execution of all HAL flash
+//! functions. If an interrupt occurs during execution of a flash function
+//! that programs or erases flash or INFO space, errors will occur if the
+//! interrupt service routine (ISR) is located in on-chip flash.
+//! If interrupts are expected during execution of a flash function that
+//! programs or erases either flash or INFO space:
+//! - Interrupts must be disabled via a critical section handler prior to
+//!   calling the flash function.
+//! - Alternatively, applicable ISRs must be located in non-flash address space
+//!   (i.e. SRAM, off-chip ROM, etc.).
+//!
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//
+// Look-up table
+//
+g_am_hal_flash_t g_am_hal_flash =
+{
+    //
+    // The basics.
+    //
+    // flash_mass_erase()
+    ((int  (*) (uint32_t, uint32_t)) 0x0800004d),
+    // flash_page_erase()
+    ((int  (*) (uint32_t, uint32_t, uint32_t))  0x08000051),
+    // flash_program_main()
+    ((int  (*) (uint32_t, uint32_t *, uint32_t *, uint32_t))  0x08000055),
+    // flash_program_info()
+    ((int  (*) (uint32_t, uint32_t, uint32_t *, uint32_t, uint32_t)) 0x08000059),
+
+    //
+    // Non-blocking variants, but be careful these are not interrupt safe so
+    // mask interrupts while these very long operations proceed.
+    //
+    // flash_mass_erase_nb()
+    ((int      (*)(uint32_t, uint32_t)) 0x0800006d),
+    // flash_page_erase_nb()
+    ((int      (*)(uint32_t, uint32_t, uint32_t)) 0x08000071),
+    // flash_nb_operation_complete()
+    ((bool     (*)(void)) 0x0800007d),
+
+    //
+    // Essentially these are recovery options.
+    //
+    // flash_erase_info()
+    ((int      (*)(uint32_t, uint32_t)) 0x08000081),
+    // flash_erase_main_plus_info()
+    ((int      (*)(uint32_t, uint32_t)) 0x08000089),
+    // flash_erase_main_plus_info_both_instances()
+    ((int      (*)(uint32_t)) 0x08000091),
+    // flash_recovery()
+    ((void     (*)(uint32_t)) 0x08000099),
+
+    //
+    // Useful utilities.
+    //
+    // flash_util_read_word()
+    ((uint32_t (*)(uint32_t*)) 0x08000075),
+    // flash_util_write_word()
+    ((void     (*)(uint32_t*, uint32_t)) 0x08000079),
+    // delay_cycles()
+    ((void     (*)(uint32_t)) 0x0800009d),
+
+    //
+    // The following functions pointers must never be called from user
+    // programs. They are here primarily to document these entry points
+    // which are usable from a debugger or debugger script.
+    //
+    // flash_program_main_sram()
+    ((void (*) (void))  0x0800005d),
+    // flash_program_info_sram()
+    ((void (*) (void))  0x08000061),
+    // flash_erase_main_pages_sram()
+    ((void (*) (void))  0x08000065),
+    // flash_mass_erase_sram()
+    ((void (*) (void))  0x08000069),
+    // flash_erase_info_sram()
+    ((void     (*)(void)) 0x08000085),
+    // flash_erase_main_plus_info_sram()
+    ((void     (*)(void)) 0x0800008d)
+};
+
+//*****************************************************************************
+//
+//! @brief This function performs a mass erase on a flash instance.
+//!
+//! @param ui32Value - The flash program key.
+//! @param ui32FlashInst - The flash instance to erase.
+//!
+//! This function will erase the desired instance of flash.
+//!
+//! @note For Apollo2, each flash instance contains a maximum of 512KB.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return 0 for success, non-zero for failure.
+//
+//*****************************************************************************
+int
+am_hal_flash_mass_erase(uint32_t ui32Value, uint32_t ui32FlashInst)
+{
+    return g_am_hal_flash.flash_mass_erase(ui32Value, ui32FlashInst);
+}
+
+//*****************************************************************************
+//
+//! @brief This function performs a page erase on a flash instance.
+//!
+//! @param ui32Value - The flash program key.
+//! @param ui32FlashInst - The flash instance to reference the page number with.
+//! @param ui32PageNum - The flash page relative to the specified instance.
+//!
+//! This function will erase the desired flash page in the desired instance of
+//! flash.
+//!
+//! @note For Apollo2, each flash page is 8KB (or AM_HAL_FLASH_PAGE_SIZE).
+//! Each flash instance contains a maximum of 64 pages (or
+//! AM_HAL_FLASH_INSTANCE_PAGES).
+//!
+//! @note When given an absolute flash address, a couple of helpful macros can
+//! be utilized when calling this function.
+//! For example:
+//!     am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY,
+//!                             AM_HAL_FLASH_ADDR2INST(ui32Addr),
+//!                             AM_HAL_FLASH_ADDR2PAGE(ui32Addr) );
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return 0 for success, non-zero for failure.
+//
+//*****************************************************************************
+int
+am_hal_flash_page_erase(uint32_t ui32Value, uint32_t ui32FlashInst,
+                        uint32_t ui32PageNum)
+{
+    return g_am_hal_flash.flash_page_erase(ui32Value,
+                                           ui32FlashInst,
+                                           ui32PageNum);
+}
+
+//*****************************************************************************
+//
+//! @brief This programs up to N words of the Main array on one flash instance.
+//!
+//! @param ui32Value - The programming key, AM_HAL_FLASH_PROGRAM_KEY.
+//! @param pui32Src - Pointer to word aligned array of data to program into
+//! the flash instance.
+//! @param pui32Dst - Pointer to the word aligned flash location where
+//! programming of the flash instance is to begin.
+//! @param ui32NumWords - The number of words to be programmed.
+//!
+//! This function will program multiple words in main flash.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return 0 for success, non-zero for failure.
+//
+//*****************************************************************************
+int
+am_hal_flash_program_main(uint32_t ui32Value, uint32_t *pui32Src,
+                          uint32_t *pui32Dst, uint32_t ui32NumWords)
+{
+    return g_am_hal_flash.flash_program_main(ui32Value, pui32Src,
+                                             pui32Dst, ui32NumWords);
+}
+
+//*****************************************************************************
+//
+//! @brief This function programs multiple words in the customer INFO space.
+//!
+//! @param ui32Value - The customer INFO space key.
+//! @param ui32InfoInst - The INFO space instance, 0 or 1.
+//! @param *pui32Src - Pointer to word aligned array of data to program into
+//! the customer INFO space.
+//! @param ui32Offset - Word offset into customer INFO space (offset of 0 is
+//! the first word, 1 is second word, etc.).
+//! @param ui32NumWords - The number of words to be programmed, must not
+//! exceed AM_HAL_FLASH_INFO_SIZE/4.
+//!
+//! This function will program multiple words in the customer INFO space.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return 0 for success, non-zero for failure.
+//
+//*****************************************************************************
+int
+am_hal_flash_program_info(uint32_t ui32Value, uint32_t ui32InfoInst,
+                          uint32_t *pui32Src, uint32_t ui32Offset,
+                          uint32_t ui32NumWords)
+{
+    return g_am_hal_flash.flash_program_info(ui32Value, 0, pui32Src,
+                                             ui32Offset, ui32NumWords);
+}
+
+//*****************************************************************************
+//
+//! @brief This function erases an instance of the customer INFO space.
+//!
+//! @param ui32ProgramKey - The customer INFO space programming key
+//! (AM_HAL_FLASH_PROGRAM_KEY).
+//! @param ui32Inst - The flash instance, either 0 or 1.
+//!
+//! This function will erase the the customer INFO space of the specified
+//! instance.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return 0 for success, non-zero for failure.
+//
+//*****************************************************************************
+int
+am_hal_flash_erase_info(uint32_t ui32ProgramKey,
+                        uint32_t ui32Inst)
+{
+    return g_am_hal_flash.flash_erase_info(ui32ProgramKey, ui32Inst);
+}
+
+//*****************************************************************************
+//
+//! @brief This function erases the main instance + the customer INFO space.
+//!
+//! @param ui32ProgramKey - The customer INFO space key.
+//! @param ui32Inst      - The flash instance, either 0 or 1.
+//!
+//! This function will erase the main flash + the customer INFO space of the
+//! specified instance.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return 0 for success, non-zero for failure.
+//
+//*****************************************************************************
+int
+am_hal_flash_erase_main_plus_info(uint32_t ui32ProgramKey,
+                                  uint32_t ui32Inst)
+{
+    return g_am_hal_flash.flash_erase_main_plus_info(ui32ProgramKey,
+                                                     ui32Inst);
+}
+
+//*****************************************************************************
+//
+//! @brief This function erases the main flash + the customer INFO space.
+//!
+//! @param ui32ProgramKey - The customer INFO space key.
+//!
+//! This function will erase both instances the main flash + the
+//! customer INFO space.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return 0 for success, non-zero for failure.
+//
+//*****************************************************************************
+int
+am_hal_flash_erase_main_plus_info_both_instances(uint32_t ui32ProgramKey)
+{
+    return g_am_hal_flash.flash_erase_main_plus_info_both_instances(
+                                                               ui32ProgramKey);
+}
+
+//*****************************************************************************
+//
+//! @brief This function erases both main flash instances + both customer INFO
+//! space instances.
+//!
+//! @param ui32RecoveryKey - The recovery key.
+//!
+//! This function erases both main instances and both customer INFOinstances
+//! even if the customer INFO space is programmed to not be erasable. This
+//! function completely erases the flash main and info instances and wipes the
+//! SRAM. Upon completion of the erasure operations, it does a POI (power on
+//! initialization) reset.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return Never Returns!!!
+//
+//*****************************************************************************
+void
+am_hal_flash_recovery(uint32_t ui32RecoveryKey)
+{
+    g_am_hal_flash.flash_recovery(ui32RecoveryKey);
+}
+
+//*****************************************************************************
+//
+//! @brief Return ui32 value obtained from anywhere in D Code or System Bus
+//!
+//! @param ui32Address - return the value corresponding to this location.
+//!
+//! Use this function to read a value from various peripheral locations
+//! that must be read from code running external to flash.
+//!
+//! @return the value found
+//
+//*****************************************************************************
+uint32_t
+am_hal_flash_load_ui32(uint32_t ui32Address)
+{
+    return g_am_hal_flash.flash_util_read_word((uint32_t*)ui32Address);
+}
+
+//*****************************************************************************
+//
+//! @brief Use the bootrom to write to a location in SRAM or the system bus.
+//!
+//! @param ui32Address - Store the data value corresponding to this location.
+//! @param ui32Data    - 32-bit Data to be stored.
+//!
+//! Use this function to store a value to various peripheral or SRAM locations
+//! that can not be touched from code running in SRAM or FLASH.  There is no
+//! known need for this function in Apollo2 at this time.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_flash_store_ui32(uint32_t ui32Address, uint32_t ui32Data)
+{
+    g_am_hal_flash.flash_util_write_word((uint32_t*)ui32Address,
+                                                ui32Data);
+}
+
+//*****************************************************************************
+//
+//! @brief Use the bootrom to implement a spin loop.
+//!
+//! @param ui32Iterations - Number of iterations to delay.
+//!
+//! Use this function to implement a CPU busy waiting spin loop without cache
+//! or delay uncertainties.
+//!
+//! Note that the ROM-based function executes at 3 cycles per iteration plus
+//! the regular function call, entry, and exit overhead.
+//! The call and return overhead, including the call to this function, is
+//! somewhere in the neighborhood of 14 cycles, or 4.7 iterations.
+//!
+//! Example:
+//! - MCU operating at 48MHz -> 20.83 ns / cycle
+//! - Therefore each iteration (once inside the bootrom function) will consume
+//!   62.5ns.
+//! - The total overhead (assuming 14 cycles) is 292ns.
+//! - For ui32Iterations=28: Total delay time = 0.292 + (0.0625 * 28) = 2.04us.
+//!
+//! The FLASH_CYCLES_US(n) macro can be used with am_hal_flash_delay() to
+//! get an approximate microsecond delay.
+//! e.g. For a 2us delay, use:
+//!      am_hal_flash_delay( FLASH_CYCLES_US(2) );
+//!
+//! @note Interrupts are active during execution of this function.  Therefore,
+//! any interrupt taken will affect the delay timing.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_flash_delay(uint32_t ui32Iterations)
+{
+    g_am_hal_flash.delay_cycles(ui32Iterations);
+}
+
+//*****************************************************************************
+//
+//! @brief Static Helper Function to check customer info valid bits erasure.
+//!
+//! Use this function to test the state of the 128 valid bits at the beginning
+//! of customer info space. If these are all erased then return true.
+//!
+//! @return true if the customer info bits are currently erased.
+//
+//*****************************************************************************
+static bool
+customer_info_signature_erased(void)
+{
+    uint32_t *pui32Signature = (uint32_t *) AM_HAL_FLASH_INFO_ADDR;
+
+    return ( (pui32Signature[3] == 0xFFFFFFFF)  &&
+             (pui32Signature[2] == 0xFFFFFFFF)  &&
+             (pui32Signature[1] == 0xFFFFFFFF)  &&
+             (pui32Signature[0] == 0xFFFFFFFF) ) ? true : false;
+}
+
+//*****************************************************************************
+//
+//! @brief Static Helper Function to set customer info valid bits
+//!
+//! Use this function to set the state of the 128 valid bits at the beginning
+//! of customer info space. If these bits are not set correctly then the
+//! customer protection bits in the INFO space will not be honored by the
+//! hardware.
+//!
+//! @return Zero for success. Non-Zero for errors.
+//
+//*****************************************************************************
+static int
+customer_info_signature_set(void)
+{
+    uint32_t ui32Valid[4];
+    int iRC;
+
+    //
+    // If they are already set then we are done.
+    //
+    if ( am_hal_flash_customer_info_signature_check() )
+    {
+        return 0;
+    }
+
+    //
+    // If they are not erased at this point we have an error.
+    //
+    if ( !customer_info_signature_erased() )
+    {
+        return (2 << 16);
+    }
+
+    //
+    // OK they need to be set so do it.
+    //
+    ui32Valid[3] = AM_HAL_FLASH_INFO_SIGNATURE3;
+    ui32Valid[2] = AM_HAL_FLASH_INFO_SIGNATURE2;
+    ui32Valid[1] = AM_HAL_FLASH_INFO_SIGNATURE1;
+    ui32Valid[0] = AM_HAL_FLASH_INFO_SIGNATURE0;
+
+    iRC = g_am_hal_flash.flash_program_info(AM_HAL_FLASH_PROGRAM_KEY,
+                                            0,         // instance
+                                            ui32Valid, // source data
+                                            0,         // offset
+                                            4);        // number of words
+    return iRC | ((iRC) ? (1 << 16) : 0);
+}
+
+//*****************************************************************************
+//
+//! @brief Check that the customer info bits are valid.
+//!
+//! Use this function to test the state of the 128 valid bits at the beginning
+//! of customer info space. If these are not set correctly then the customer
+//! protection bits in the INFO space will not be honored by the hardware.
+//!
+//! @return true if valid.
+//
+//*****************************************************************************
+bool
+am_hal_flash_customer_info_signature_check(void)
+{
+    uint32_t *pui32Signature = (uint32_t *)AM_HAL_FLASH_INFO_ADDR;
+
+    return ( (pui32Signature[3] == AM_HAL_FLASH_INFO_SIGNATURE3)    &&
+             (pui32Signature[2] == AM_HAL_FLASH_INFO_SIGNATURE2)    &&
+             (pui32Signature[1] == AM_HAL_FLASH_INFO_SIGNATURE1)    &&
+             (pui32Signature[0] == AM_HAL_FLASH_INFO_SIGNATURE0) );
+}
+
+//*****************************************************************************
+//
+//! @brief INFO signature set.
+//!
+//! Use this function to set the state of the 128 valid bits at the beginning
+//! of customer info space, if needed.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return Zero for success. Non-Zero for errors.
+//
+//*****************************************************************************
+bool
+am_hal_flash_info_signature_set(void)
+{
+    //
+    // Check and set signature.
+    //
+    return customer_info_signature_set() ? false : true;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable FLASH INFO space.
+//!
+//! Use this function to set the state of the 128 valid bits at the beginning
+//! of customer info space, if needed. Then disable FLASH erasure.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return Zero for success. Non-Zero for errors.
+//
+//*****************************************************************************
+int32_t
+am_hal_flash_info_erase_disable(void)
+{
+    int iRC;
+    uint32_t ui32SecurityValue;
+
+    //
+    // Security protection only works if the signature data is correct.
+    //
+    iRC = customer_info_signature_set();
+    if ( iRC )
+    {
+        return iRC;
+    }
+
+    //
+    // Clear bit in INFO space to disable erasure.
+    //
+    ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR)  &
+                        ~AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M;
+
+    //
+    // Now write the word to the flash INFO space.
+    //
+    return g_am_hal_flash.flash_program_info(
+            AM_HAL_FLASH_PROGRAM_KEY,
+            0,                                  // instance
+            &ui32SecurityValue,                 // source data
+            AM_HAL_FLASH_INFO_SECURITY_O / 4,   // word offset
+            1 );                                // number of words
+}
+
+//*****************************************************************************
+//
+//! @brief Check for Disabled FLASH INFO space.
+//!
+//! Use this function to determine whether FLASH INFO erasure is disabled.
+//!
+//! @return true if FLASH INFO erase is disabled, otherwise false.
+//
+//*****************************************************************************
+bool
+am_hal_flash_info_erase_disable_check(void)
+{
+    //
+    // If they are erased at this point then SRAM wipe can't be enabled.
+    //
+    if ( customer_info_signature_erased() )
+    {
+        return false;
+    }
+
+    //
+    // If they are not valid at this point then SRAM wipe can't be enabled.
+    //
+    if ( !am_hal_flash_customer_info_signature_check() )
+    {
+        return false;
+    }
+
+    //
+    // Looking good so far, now check the SRAM WIPE bit.
+    //
+    return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR)   &
+                     AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M  ? false : true;
+}
+
+//*****************************************************************************
+//
+//! @brief Mask off 1 to 4 quadrants of FLASH INFO space for programming.
+//!
+//! Use this function to set the state of the 128 valid bits at the beginning
+//! of customer info space, if needed. Then and the mask bits with the INFO
+//! space programming disable bits.
+//!
+//! @param ui32Mask - A mask of the 4 quadrants of info space where
+//!                   bit0 = First quadrant (first 2KB).
+//!                   bit1 = Second quadrant (second 2KB).
+//!                   bit2 = Third quadrant (third 2KB).
+//!                   bit3 = Fourth quadrant (fourth 2KB).
+//!
+//! @note This function disables only, any quadrant already disabled is not
+//! reenabled.  That is, any ui32Mask bits specified as 0 are essentially nops.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return Zero for success. Non-Zero for errors.
+//
+//*****************************************************************************
+int32_t
+am_hal_flash_info_program_disable(uint32_t ui32Mask)
+{
+    int iRC;
+    uint32_t ui32SecurityValue;
+
+    //
+    // Security protection only works if the signature data is correct.
+    //
+    iRC = customer_info_signature_set();
+    if ( iRC )
+    {
+        return iRC;
+    }
+
+    //
+    // Make sure we have a valid mask and get the mask into the correct position.
+    //
+    ui32Mask <<= AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S;
+    ui32Mask &= AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M;
+
+    //
+    // The security bit set to 1 enables programming, 0 disables programming.
+    //
+    ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & ~ui32Mask;
+
+    //
+    // Now write the word to the flash INFO space.
+    //
+    return g_am_hal_flash.flash_program_info(
+            AM_HAL_FLASH_PROGRAM_KEY,
+            0,                                  // instance
+            &ui32SecurityValue,                 // source data
+            AM_HAL_FLASH_INFO_SECURITY_O / 4,   // word offset
+            1 );                                // number of words
+}
+
+//*****************************************************************************
+//
+//! @brief Return a mask specifying which quadrants of customer INFO space have
+//! been disabled for programming.
+//!
+//! Use this function to determine whether programming of customer INFO space
+//! has been disabled.
+//!
+//! @return A 4-bit mask of the disabled quadrants.
+//! 0xFFFFFFFF indicates an error.
+//! 0x0  indicates all customer INFO space programming is enabled.
+//! 0xF  indicates all customer INFO space programming is disabled.
+//! bit0 indicates the first customer INFO space is disabled for programming.
+//! bit1 indicates the second customer INFO space is disabled for programming.
+//! bit2 indicates the third customer INFO space is disabled for programming.
+//! bit3 indicates the fourth customer INFO space is disabled for programming.
+//
+//*****************************************************************************
+uint32_t
+am_hal_flash_info_program_disable_get(void)
+{
+    //
+    // If they are erased at this point then SRAM wipe can't be enabled.
+    //
+    if ( customer_info_signature_erased() )
+    {
+        return 0xFFFFFFFF;
+    }
+
+    //
+    // If not valid at this point, then INFO programming can't be enabled.
+    //
+    if ( !am_hal_flash_customer_info_signature_check() )
+    {
+        return 0xFFFFFFFF;
+    }
+
+    //
+    // Looking good so far, now return a mask of the disabled bits.
+    //
+    return  ((AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+                AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M) ^
+                AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M) >>
+                AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable FLASH debugger protection (FLASH gets wiped if a debugger is
+//! connected).
+//!
+//! Use this function to set the state of the 128 valid bits at the beginning
+//! of customer info space, if needed. Then set the FLASH wipe bit to zero.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return Zero for success. Non-Zero for errors.
+//
+//*****************************************************************************
+int32_t
+am_hal_flash_wipe_flash_enable(void)
+{
+    int iRC;
+    uint32_t ui32SecurityValue;
+
+    //
+    // Security protection only works if the signature data is correct.
+    //
+    iRC = customer_info_signature_set();
+    if ( iRC )
+    {
+        return iRC;
+    }
+
+    //
+    // Clear the FLASH Wipe bit.
+    //
+    ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+                        ~AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M;
+
+    //
+    // Now write the word to the flash INFO space.
+    //
+    return g_am_hal_flash.flash_program_info(
+            AM_HAL_FLASH_PROGRAM_KEY,
+            0,                                  // instance
+            &ui32SecurityValue,                 // source data
+            AM_HAL_FLASH_INFO_SECURITY_O / 4,   // word offset
+            1 );                                // number of words
+}
+
+//*****************************************************************************
+//
+//! @brief check for FLASH wipe protection enabled.
+//!
+//! Use this function to determine if FLASH wipe protection is enabled.
+//!
+//! @return true if FLASH wipe protection is enabled, otherwise false.
+//
+//*****************************************************************************
+bool
+am_hal_flash_wipe_flash_enable_check(void)
+{
+    //
+    // If they are erased at this point then flash wipe can't be enabled.
+    //
+    if ( customer_info_signature_erased() )
+    {
+        return false;
+    }
+
+    //
+    // If they are not valid at this point then flash wipe can't be enabled.
+    //
+    if ( !am_hal_flash_customer_info_signature_check() )
+    {
+        return false;
+    }
+
+    //
+    // Looking good so far, now check the Flash WIPE bit.
+    //
+    return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+            AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M ? false : true;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable SRAM protection so SRAM gets wiped if a debgger is connected.
+//!
+//! Use this function to set the state of the 128 valid bits at the beginning
+//! of customer info space, if needed. Then set the SRAM wipe bit to zero.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return Zero for success. Non-Zero for errors.
+//
+//*****************************************************************************
+int32_t
+am_hal_flash_wipe_sram_enable(void)
+{
+    int iRC;
+    uint32_t ui32SecurityValue;
+
+    //
+    // Security protection only works if the signature data is correct.
+    //
+    iRC = customer_info_signature_set();
+    if ( iRC )
+    {
+        return iRC;
+    }
+
+    //
+    // Clear the SRAM Wipe bit.
+    //
+    ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+                        ~AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M;
+
+    //
+    // Now write the word to the flash INFO space.
+    //
+    return g_am_hal_flash.flash_program_info(
+            AM_HAL_FLASH_PROGRAM_KEY,
+            0,                                  // instance
+            &ui32SecurityValue,                 // source data
+            AM_HAL_FLASH_INFO_SECURITY_O / 4,   // word offset
+            1 );                                // number of words
+}
+
+//*****************************************************************************
+//
+//! @brief check for SRAM protection enabled.
+//!
+//! Use this function to determine if SRAM protection is enabled.
+//!
+//! @return true if SRAM wipe protection is enabled, otherwise false.
+//
+//*****************************************************************************
+bool
+am_hal_flash_wipe_sram_enable_check(void)
+{
+    //
+    // If they are erased at this point then SRAM wipe can't be enabled.
+    //
+    if ( customer_info_signature_erased() )
+    {
+        return false;
+    }
+
+    //
+    // If they are not vale at this point then SRAM wipe can't be enabled.
+    //
+    if ( !am_hal_flash_customer_info_signature_check() )
+    {
+        return false;
+    }
+
+    //
+    // Looking good so far, now check the SRAM WIPE bit.
+    //
+    return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+            AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M ? false : true;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable Output from ITM/SWO.
+//!
+//! Use this function to set the state of the 128 valid bits at the beginning
+//! of customer info space, if needed. Set the SWO disable bit to zero.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return Zero for success. Non-Zero for errors.
+//
+//*****************************************************************************
+int32_t
+am_hal_flash_swo_disable(void)
+{
+    int iRC;
+    uint32_t ui32SecurityValue;
+
+    //
+    // Security protection only works if the signature data is correct.
+    //
+    iRC = customer_info_signature_set();
+    if ( iRC )
+    {
+        return iRC;
+    }
+
+    //
+    // Clear the SWO bit.
+    //
+    ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+                        ~AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M;
+
+    //
+    // Now write the word to the flash INFO space.
+    //
+    return g_am_hal_flash.flash_program_info(
+            AM_HAL_FLASH_PROGRAM_KEY,
+            0,                                  // instance
+            &ui32SecurityValue,                 // source data
+            AM_HAL_FLASH_INFO_SECURITY_O / 4,   // word offset
+            1 );                                // number of words
+}
+
+//*****************************************************************************
+//
+//! @brief check for SWO disabled.
+//!
+//! Use this function to determine if the SWO is disabled.
+//!
+//! @return true if the ITM/SWO is disabled, otherwise false.
+//
+//*****************************************************************************
+bool
+am_hal_flash_swo_disable_check(void)
+{
+    //
+    // If they are erased at this point then SRAM wipe can't be enabled.
+    //
+    if ( customer_info_signature_erased() )
+    {
+        return false;
+    }
+
+    //
+    // If they are not vale at this point then SRAM wipe can't be enabled.
+    //
+    if ( !am_hal_flash_customer_info_signature_check() )
+    {
+        return false;
+    }
+
+    //
+    // Looking good so far, now check the SWO bit.
+    //
+    return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+            AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M ? false : true;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable Connections from a debugger on the SWD interface.
+//!
+//! Use this function to set the state of the 128 valid bits at the beginning
+//! of customer info space, if needed. Set the debugger disable bit to zero.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return Zero for success. Non-Zero for errors.
+//
+//*****************************************************************************
+int32_t
+am_hal_flash_debugger_disable(void)
+{
+    int iRC;
+    uint32_t ui32SecurityValue;
+
+    //
+    // Security protection only works if the signature data is correct.
+    //
+    iRC = customer_info_signature_set();
+    if ( iRC )
+    {
+        return iRC;
+    }
+
+    //
+    // Clear the DEBUGGER bit.
+    //
+    ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+                        ~AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M;
+
+    //
+    // Now write the word to the flash INFO space.
+    //
+    return g_am_hal_flash.flash_program_info(
+            AM_HAL_FLASH_PROGRAM_KEY,
+            0,                                  // instance
+            &ui32SecurityValue,                 // source data
+            AM_HAL_FLASH_INFO_SECURITY_O / 4,   // word offset
+            1 );                                // number of words
+}
+
+//*****************************************************************************
+//
+//! @brief check for debugger disabled.
+//!
+//! Use this function to determine if the debugger is disabled.
+//!
+//! @return true if the debugger is disabled, otherwise false.
+//
+//*****************************************************************************
+bool
+am_hal_flash_debugger_disable_check(void)
+{
+    //
+    // If they are erased at this point then SRAM wipe can't be enabled.
+    //
+    if ( customer_info_signature_erased() )
+    {
+        return false;
+    }
+
+    //
+    // If they are not vale at this point then SRAM wipe can't be enabled.
+    //
+    if ( !am_hal_flash_customer_info_signature_check() )
+    {
+        return false;
+    }
+
+    //
+    // Looking good so far, now check the debugger disable bit.
+    //
+    return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) &
+            AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M ? false : true;
+}
+
+//*****************************************************************************
+//
+//! @brief This static helper function generates a 64-bit protection mask.
+//!
+//! @param pui32StartAddress - Starting address in flash to begin protection.
+//! @param pui32StopAddress  - Ending address in flash to stop protection.
+//!
+//! This function computes a chunk map for the protection range.
+//!
+//! @return Inverse of the actual chunk mask.  That is, chunks to be protected
+//! are represented as 0 in the returned mask, while chunks to be left alone
+//! are represented as 1.  This value can therefore be directly ANDed with the
+//! existing bits in INFO space.
+//! Note that -1 is returned if input parameters are invalid - this return
+//! value would indicate that no chunks are to be protected.
+//!
+//
+//*****************************************************************************
+static uint64_t
+generate_chunk_mask(uint32_t *pui32StartAddress, uint32_t *pui32StopAddress)
+{
+    uint32_t ui32ChunkStart, ui32ChunkStop;
+    uint32_t ui32Width;
+    uint64_t ui64Mask;
+
+    //
+    // Validate the address input parameters
+    //
+    if ( (pui32StartAddress > pui32StopAddress)  ||
+         (pui32StopAddress > (uint32_t*)AM_HAL_FLASH_LARGEST_VALID_ADDR) )
+    {
+        //
+        // Argument error, return value to leave all chunks unprotected.
+        //
+        return 0xFFFFFFFFFFFFFFFF;
+    }
+
+    //
+    // Extract chunk related information
+    //
+    ui32ChunkStart = AM_HAL_FLASH_INFO_ADDR2CHUNK((uint32_t)pui32StartAddress);
+    ui32ChunkStop  = AM_HAL_FLASH_INFO_ADDR2CHUNK((uint32_t)pui32StopAddress);
+    ui32Width = ui32ChunkStop - ui32ChunkStart + 1;
+
+    if ( ui32Width == 64 )
+    {
+        ui64Mask = (uint64_t)0xFFFFFFFFFFFFFFFFLLU;
+    }
+    else
+    {
+        ui64Mask = ( ((uint64_t)0x0000000000000001) << ui32Width) - 1;
+        ui64Mask <<= ui32ChunkStart;
+    }
+
+    //
+    // OK now return the chunk mask (inverted).
+    //
+    return ~ui64Mask;
+}
+
+//*****************************************************************************
+//
+//! @brief This function sets copy protection for a range of flash chunks.
+//!
+//! @param pui32StartAddress - Starting address in flash to begin protection.
+//! @param pui32StopAddress - Ending address in flash to stop protection.
+//!
+//! This function will set copy protection bits for a range of flash chunks
+//!
+//! @note Each flash chunk contains 16KBytes and corresponds to one bit in
+//! the protection register. Set the bit to zero to enable protection.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return
+//!     0 for success.
+//!     0x400000 if the protection bits were already programmed (mask the return
+//!              value with 0x3FFFFF to ignore this case and treat as success).
+//!     Otherwise, non-zero for failure.
+//
+//*****************************************************************************
+int32_t
+am_hal_flash_copy_protect_set(uint32_t *pui32StartAddress,
+                              uint32_t *pui32StopAddress)
+{
+    int iRC;
+    bool bModified = false;
+    uint64_t ui64Mask;
+    uint32_t ui32Work;
+    uint32_t ui32Protection[2];
+    uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_COPYPROT_ADDR;
+
+    //
+    // Extract chunk mask from parameters.
+    // Also checks parameter validity (returns -1 if bad parameters).
+    //
+    ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress);
+    if ( ~ui64Mask == 0x0 )
+    {
+        return 0x100000;
+    }
+
+    //
+    // Go get the current settings for copy protection.
+    //
+    ui32Protection[0] = pui32Protection[0];
+    ui32Protection[1] = pui32Protection[1];
+
+    //
+    // AND mask off the necessary protection bits in the lower word.
+    //
+    ui32Work = (uint32_t)ui64Mask;
+    if ( ( ~ui32Work )  &&  ( ui32Work != ui32Protection[0] ) )
+    {
+        bModified = true;
+        ui32Protection[0] &= ui32Work;
+        iRC = g_am_hal_flash.flash_program_info(
+                AM_HAL_FLASH_PROGRAM_KEY,
+                0,                                      // instance
+                &ui32Protection[0],                     // source data
+                (AM_HAL_FLASH_INFO_COPYPROT_O / 4) + 0, // word offset
+                1 );                                    // number of words
+
+        if ( iRC )
+        {
+            return iRC | 0x10000;
+        }
+    }
+
+    //
+    // AND mask off the necessary protection bits in the upper word.
+    //
+    ui32Work = (uint32_t)(ui64Mask >> 32);
+    if ( ( ~ui32Work )  &&  ( ui32Work != ui32Protection[1] ) )
+    {
+        bModified = true;
+        ui32Protection[1] &= ui32Work;
+        iRC = g_am_hal_flash.flash_program_info(
+                AM_HAL_FLASH_PROGRAM_KEY,
+                0,                                      // instance
+                &ui32Protection[1],                     // source data
+                (AM_HAL_FLASH_INFO_COPYPROT_O / 4) + 1, // word offset
+                1 );                                    // number of words
+
+        if ( iRC )
+        {
+            return iRC | 0x20000;
+        }
+    }
+
+    if ( bModified )
+    {
+        return 0;
+    }
+    else
+    {
+        return 0x400000;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief This function checks copy protection for a range of flash chunks.
+//!
+//! @param pui32StartAddress - Starting address in flash.
+//! @param pui32StopAddress - Ending address in flash.
+//!
+//! This function will check copy protection bits for a range of flash chunks
+//! it expects all chunks in the range to be protected.
+//!
+//! @note Each flash chunk contains 16KBytes and corresponds to one bit in
+//! the protection register. Set the bit to zero to enable protection.
+//!
+//! @return false for at least one chunk in the covered range is not protected,
+//!         and true if all chunks in the covered range are protected.
+//!
+//
+//*****************************************************************************
+bool
+am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress,
+                                uint32_t *pui32StopAddress)
+{
+    uint64_t ui64Mask;
+    uint32_t ui32Work;
+    uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_COPYPROT_ADDR;
+
+    //
+    // Extract chunk mask from parameters.
+    // Also checks parameter validity (returns -1 if bad parameters).
+    //
+    ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress);
+    if ( ~ui64Mask == 0x0 )
+    {
+        return false;
+    }
+
+    //
+    // Now check the lower word of protection bits.
+    //
+    ui32Work = (uint32_t)ui64Mask;
+    if ( ~ui32Work  &  pui32Protection[0] )
+    {
+        return false;
+    }
+
+    //
+    // Now check the lower word of protection bits.
+    //
+    ui32Work = (uint32_t)(ui64Mask >> 32);
+    if ( ~ui32Work & pui32Protection[1] )
+    {
+        return false;
+    }
+
+    //
+    // If we get here, there are no unprotected chunks within specified range.
+    //
+    return true;
+}
+
+//*****************************************************************************
+//
+//! @brief This function sets write protection for a range of flash chunks.
+//!
+//! @param pui32StartAddress - Starting address in flash to begin protection.
+//! @param pui32StopAddress - Ending address in flash to stop protection.
+//!
+//! This function will set write protection bits for a range of flash chunks
+//!
+//! @note Each flash chunk contains 16KBytes and corresponds to one bit in
+//! the protection register. Set the bit to zero to enable protection.
+//!
+//! @note Interrupts are active during execution of this function. Any interrupt
+//! taken could cause execution errors. Please see the IMPORTANT note under
+//! Detailed Description above for more details.
+//!
+//! @return
+//!     0 for success.
+//!     0x400000 if the protection bits were already programmed (mask the return
+//!              value with 0x3FFFFF to ignore this case and treat as success).
+//!     Otherwise, non-zero for failure.
+//
+//*****************************************************************************
+int32_t
+am_hal_flash_write_protect_set(uint32_t *pui32StartAddress,
+                               uint32_t *pui32StopAddress)
+{
+    int iRC;
+    bool bModified = false;
+    uint64_t ui64Mask;
+    uint32_t ui32Work;
+    uint32_t ui32Protection[2];
+    uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_WRITPROT_ADDR;
+
+    //
+    // Extract chunk mask from parameters.
+    // Also checks parameter validity (returns -1 if bad parameters).
+    //
+    ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress);
+    if ( ~ui64Mask == 0x0 )
+    {
+        return 0x100000;
+    }
+
+    //
+    // Go get the current settings for copy protection.
+    //
+    ui32Protection[0] = pui32Protection[0];
+    ui32Protection[1] = pui32Protection[1];
+
+    //
+    // AND mask off the necessary protection bits in the lower word.
+    //
+    ui32Work = (uint32_t)ui64Mask;
+    if ( ( ~ui32Work )  &&  ( ui32Work != ui32Protection[0] ) )
+    {
+        bModified = true;
+        ui32Protection[0] &= ui32Work;
+        iRC = g_am_hal_flash.flash_program_info(
+                AM_HAL_FLASH_PROGRAM_KEY,
+                0,                                      // instance
+                &ui32Protection[0],                     // source data
+                (AM_HAL_FLASH_INFO_WRITPROT_O / 4) + 0, // word offset
+                1 );                                    // number of words
+
+        if ( iRC )
+        {
+            return iRC | 0x10000;
+        }
+    }
+
+    //
+    // AND mask off the necessary protection bits in the upper word.
+    //
+    ui32Work = (uint32_t)(ui64Mask >> 32);
+    if ( ( ~ui32Work )  &&  ( ui32Work != ui32Protection[1] ) )
+    {
+        bModified = true;
+        ui32Protection[1] &= ui32Work;
+        iRC = g_am_hal_flash.flash_program_info(
+                AM_HAL_FLASH_PROGRAM_KEY,
+                0,                                      // instance
+                &ui32Protection[1],                     // source data
+                (AM_HAL_FLASH_INFO_WRITPROT_O / 4) + 1, // word offset
+                1 );                                    // number of words
+
+        if ( iRC )
+        {
+            return iRC | 0x20000;
+        }
+    }
+
+    if ( bModified )
+    {
+        return 0;
+    }
+    else
+    {
+        return 0x400000;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief This function checks write protection for a range of flash chunks.
+//!
+//! @param pui32StartAddress - Starting address in flash.
+//! @param pui32StopAddress - Ending address in flash.
+//!
+//! This function will check write protection bits for a range of flash chunks
+//! it expects all chunks in the range to be protected.
+//!
+//! @note Each flash chunk contains 16KBytes and corresponds to one bit in
+//! the protection register. Set the bit to zero to enable protection.
+//!
+//! @return false for at least one chunk in the covered range is not protected,
+//!         and true if all chunks in the covered range are protected.
+//!
+//
+//*****************************************************************************
+bool
+am_hal_flash_write_protect_check(uint32_t *pui32StartAddress,
+                                 uint32_t *pui32StopAddress)
+{
+    uint64_t ui64Mask;
+    uint32_t ui32Work;
+    uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_WRITPROT_ADDR;
+
+    //
+    // Extract chunk mask from parameters.
+    // Also checks parameter validity (returns -1 if bad parameters).
+    //
+    ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress);
+    if ( ~ui64Mask == 0x0 )
+    {
+        return false;
+    }
+
+    //
+    // Now check the lower word of protection bits.
+    //
+    ui32Work = (uint32_t)ui64Mask;
+    if ( ~ui32Work & pui32Protection[0] )
+    {
+        return false;
+    }
+
+    //
+    // Now check the lower word of protection bits.
+    //
+    ui32Work = (uint32_t)(ui64Mask >> 32);
+    if ( ~ui32Work & pui32Protection[1] )
+    {
+        return false;
+    }
+
+    //
+    // If we get here, there are no unprotected chunks within specified range.
+    //
+    return true;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h
new file mode 100644
index 0000000000..66d6f5059c
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h
@@ -0,0 +1,297 @@
+//*****************************************************************************
+//
+//  am_hal_flash.h
+//! @file
+//!
+//! @brief Functions for performing Flash operations.
+//!
+//! @addtogroup flash2 Flash
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_FLASH_H
+#define AM_HAL_FLASH_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Flash Program keys.
+//
+//*****************************************************************************
+#define AM_HAL_FLASH_PROGRAM_KEY            0x12344321
+#define AM_HAL_FLASH_RECOVERY_KEY           0xA35C9B6D
+#define AM_HAL_FLASH_INFO_KEY               0x12344321
+#define AM_HAL_FLASH_OTP_KEY                (AM_HAL_FLASH_INFO_KEY)
+
+//*****************************************************************************
+//
+// Some helpful flash values and macros.
+//
+//*****************************************************************************
+#define AM_HAL_FLASH_ADDR                   0x00000000
+#define AM_HAL_FLASH_PAGE_SIZE              ( 8 * 1024 )
+#define AM_HAL_FLASH_INFO_SIZE              AM_HAL_FLASH_PAGE_SIZE
+#define AM_HAL_FLASH_INSTANCE_SIZE          ( 512 * 1024 )
+#define AM_HAL_FLASH_INSTANCE_PAGES         ( AM_HAL_FLASH_INSTANCE_SIZE / AM_HAL_FLASH_PAGE_SIZE )
+#define AM_HAL_FLASH_TOTAL_SIZE             ( AM_HAL_FLASH_INSTANCE_SIZE * 2 )
+#define AM_HAL_FLASH_LARGEST_VALID_ADDR     ( AM_HAL_FLASH_ADDR + AM_HAL_FLASH_TOTAL_SIZE - 1 )
+
+//
+// Convert an absolute flash address to a instance
+//
+#define AM_HAL_FLASH_ADDR2INST(addr)        ( ( addr >> 19 ) & 1 )
+
+//
+// Convert an absolute flash address to a page number relative to the instance
+//
+#define AM_HAL_FLASH_ADDR2PAGE(addr)        ( ( addr >> 13 ) & 0x3F )
+
+//
+// Convert an absolute flash address to an absolute page number
+//
+#define AM_HAL_FLASH_ADDR2ABSPAGE(addr)     ( addr >> 13 )
+
+//
+// Given a number of microseconds, convert to a value representing the number of
+// cycles that will give that delay. This macro is basically taking into account
+// some of the call overhead.
+// e.g. To provide a 2us delay:
+//  am_hal_flash_delay( FLASH_CYCLES_US(2) );
+//
+#define FLASH_CYCLES_US(n)      ((n * (AM_HAL_CLKGEN_FREQ_MAX_MHZ / 3)) - 4)
+
+//
+// Backward compatibility
+//
+#define am_hal_flash_program_otp        am_hal_flash_program_info
+#define am_hal_flash_program_otp_sram   am_hal_flash_program_info_sram
+
+//*****************************************************************************
+//
+// Structure of function pointers to helper functions for invoking various
+// flash operations. The functions we are pointing to here are in the Apollo 2
+// integrated BOOTROM.
+//
+//*****************************************************************************
+typedef struct am_hal_flash_helper_struct
+{
+    //
+    // The basics.
+    //
+    int      (*flash_mass_erase)(uint32_t, uint32_t);
+    int      (*flash_page_erase)(uint32_t, uint32_t, uint32_t);
+    int      (*flash_program_main)(uint32_t,  uint32_t *,
+                                          uint32_t*, uint32_t);
+    int      (*flash_program_info)(uint32_t,   uint32_t,
+                                         uint32_t*,  uint32_t, uint32_t);
+
+    //
+    // Non-blocking variants, but be careful these are not interrupt safe so
+    // mask interrupts while these very long operations proceed.
+    //
+    int      (*flash_mass_erase_nb)(uint32_t, uint32_t);
+    int      (*flash_page_erase_nb)(uint32_t, uint32_t, uint32_t);
+    bool     (*flash_nb_operation_complete)(void);
+
+    //
+    // Essentially these are recovery options.
+    //
+    int      (*flash_erase_info)(uint32_t, uint32_t);
+    int      (*flash_erase_main_plus_info)(uint32_t, uint32_t);
+    int      (*flash_erase_main_plus_info_both_instances)(uint32_t);
+    void     (*flash_recovery)(uint32_t);
+
+    //
+    // Useful utilities.
+    //
+    uint32_t (*flash_util_read_word)(uint32_t*);
+    void     (*flash_util_write_word)(uint32_t*, uint32_t);
+    void     (*delay_cycles)(uint32_t);
+
+    //
+    // The following functions pointers will generally never be called from
+    // user programs. They are here primarily to document these entry points
+    // which are usable from a debugger or debugger script.
+    //
+    void     (*flash_program_main_sram)(void);
+    void     (*flash_program_info_sram)(void);
+    void     (*flash_erase_main_pages_sram)(void);
+    void     (*flash_mass_erase_sram)(void);
+    void     (*flash_erase_info_sram)(void);
+    void     (*flash_erase_main_plus_info_sram)(void);
+} g_am_hal_flash_t;
+extern g_am_hal_flash_t g_am_hal_flash;
+
+
+//*****************************************************************************
+//
+// Define some FLASH INFO SPACE values and macros.
+//
+//*****************************************************************************
+#define AM_HAL_FLASH_INFO_ADDR              0x50020000
+#define AM_HAL_FLASH_INFO_SECURITY_O        0x10
+#define AM_HAL_FLASH_INFO_WRITPROT_O        0x20
+#define AM_HAL_FLASH_INFO_COPYPROT_O        0x30
+
+#define AM_HAL_FLASH_INFO_SECURITY_ADDR     (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_SECURITY_O)
+#define AM_HAL_FLASH_INFO_WRITPROT_ADDR     (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_WRITPROT_O)
+#define AM_HAL_FLASH_INFO_COPYPROT_ADDR     (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_COPYPROT_O)
+
+//
+// Define the customer info signature data (at AM_HAL_FLASH_INFO_ADDR).
+// These bits must exist in the customer info space in order for many of the
+// security and protection functions to work.
+//
+#define AM_HAL_FLASH_INFO_SIGNATURE0        0x48EAAD88
+#define AM_HAL_FLASH_INFO_SIGNATURE1        0xC9705737
+#define AM_HAL_FLASH_INFO_SIGNATURE2        0x0A6B8458
+#define AM_HAL_FLASH_INFO_SIGNATURE3        0xE41A9D74
+
+//
+// Define the customer security bits (at AM_HAL_FLASH_INFO_SECURITY_ADDR)
+//
+#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S       0
+#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S            1
+#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S           2
+#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S          3
+#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S         4
+#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S        8
+#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S     9
+
+#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M       ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S))
+#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M            ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S))
+#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M           ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S))
+#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M          ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S))
+#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M         ((uint32_t)(0xF << AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S))
+#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M        ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S))
+#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_M     ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S))
+#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP_M          ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S))
+#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP            ((uint32_t)(0x0 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S))
+
+//
+// Protection chunk macros
+// AM_HAL_FLASH_INFO_CHUNK2ADDR: Convert a chunk number to an address
+// AM_HAL_FLASH_INFO_CHUNK2INST: Convert a chunk number to an instance number
+// AM_HAL_FLASH_INFO_ADDR2CHUNK: Convert an address to a chunk number
+//
+#define AM_HAL_FLASH_INFO_CHUNKSIZE         (16*1024)
+
+#define AM_HAL_FLASH_INFO_CHUNK2ADDR(n)     (AM_HAL_FLASH_ADDR + (n << 14))
+#define AM_HAL_FLASH_INFO_CHUNK2INST(n)     ((n >> 5) & 1
+#define AM_HAL_FLASH_INFO_ADDR2CHUNK(n)     ((n) >> 14)
+
+//*****************************************************************************
+//
+// Function prototypes for the helper functions
+//
+//*****************************************************************************
+extern int am_hal_flash_mass_erase(uint32_t ui32Value, uint32_t ui32FlashInst);
+extern int am_hal_flash_page_erase(uint32_t ui32Value, uint32_t ui32FlashInst,
+                                   uint32_t ui32PageNum);
+extern int am_hal_flash_program_main(uint32_t value, uint32_t *pSrc,
+                                     uint32_t *pDst, uint32_t  NumberOfWords);
+extern int am_hal_flash_program_info(uint32_t ui32Value, uint32_t ui32InfoInst,
+                                     uint32_t *pui32Src, uint32_t ui32Offset,
+                                     uint32_t ui32NumWords);
+
+//
+// Recovery type functions for Customer INFO space.
+//
+extern int      am_hal_flash_erase_info(uint32_t ui32ProgramKey,
+                                        uint32_t ui32Instance);
+extern int      am_hal_flash_erase_main_plus_info(uint32_t ui32ProgramKey,
+                                                  uint32_t ui32Instance);
+extern int      am_hal_flash_erase_main_plus_info_both_instances(
+                                                  uint32_t ui32ProgramKey);
+extern void     am_hal_flash_recovery(uint32_t ui32RecoveryKey);
+
+//
+// BOOTROM resident reader, writer and delay utility functions.
+//
+extern uint32_t am_hal_flash_load_ui32(uint32_t ui32Address);
+extern void     am_hal_flash_store_ui32(uint32_t ui32Address, uint32_t ui32Data);
+extern void     am_hal_flash_delay(uint32_t ui32Iterations);
+
+//
+// These functions update security/protection bits in the customer INFO blOCK.
+//
+extern bool     am_hal_flash_customer_info_signature_check(void);
+extern bool     am_hal_flash_info_signature_set(void);
+extern int32_t  am_hal_flash_info_erase_disable(void);
+extern bool     am_hal_flash_info_erase_disable_check(void);
+extern int32_t  am_hal_flash_info_program_disable(uint32_t ui32Mask);
+extern uint32_t am_hal_flash_info_program_disable_get(void);
+extern int32_t  am_hal_flash_wipe_flash_enable(void);
+extern bool     am_hal_flash_wipe_flash_enable_check(void);
+extern int32_t  am_hal_flash_wipe_sram_enable(void);
+extern bool     am_hal_flash_wipe_sram_enable_check(void);
+extern int32_t  am_hal_flash_swo_disable(void);
+extern bool     am_hal_flash_swo_disable_check(void);
+extern int32_t  am_hal_flash_debugger_disable(void);
+extern bool     am_hal_flash_debugger_disable_check(void);
+
+extern int32_t  am_hal_flash_copy_protect_set(uint32_t *pui32StartAddress,
+                                              uint32_t *pui32StopAddress);
+extern bool     am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress,
+                                                uint32_t *pui32StopAddress);
+extern int32_t  am_hal_flash_write_protect_set(uint32_t *pui32StartAddress,
+                                               uint32_t *pui32StopAddress);
+extern bool     am_hal_flash_write_protect_check(uint32_t *pui32StartAddress,
+                                                 uint32_t *pui32StopAddress);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_FLASH_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_global.c b/bsp/apollo2/libraries/drivers/hal/am_hal_global.c
new file mode 100644
index 0000000000..498eb1627a
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_global.c
@@ -0,0 +1,59 @@
+//*****************************************************************************
+//
+//  am_hal_global.c
+//! @file
+//!
+//! @brief Locate global variables here.
+//!
+//! This module contains global variables that are used throughout the HAL.
+//!
+//! One use in particular is that it uses a global HAL flags variable that
+//! contains flags used in various parts of the HAL.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Global Variables
+//
+//*****************************************************************************
+uint32_t volatile g_ui32HALflags = 0x00000000;
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_global.h b/bsp/apollo2/libraries/drivers/hal/am_hal_global.h
new file mode 100644
index 0000000000..bb437b198a
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_global.h
@@ -0,0 +1,114 @@
+//*****************************************************************************
+//
+//  am_hal_global.h
+//! @file
+//!
+//! @brief Locate all HAL global variables here.
+//!
+//! This module contains global variables that are used throughout the HAL,
+//! but not necessarily those designated as const (which typically end up in
+//! flash). Consolidating globals here will make it easier to manage them.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_GLOBAL_H
+#define AM_HAL_GLOBAL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macro definitions
+//
+//*****************************************************************************
+
+//******************************************************************************
+//
+// Macros used to access the bit fields in the flags variable.
+//
+//******************************************************************************
+#define AM_HAL_FLAGS_BFR(flagnm)                                            \
+    ((g_ui32HALflags & AM_HAL_FLAGS_##flagnm##_M) >> AM_HAL_FLAGS_##flagnm##_S)
+
+#define AM_HAL_FLAGS_BFW(flagnm, value)                                     \
+    g_ui32HALflags = ((g_ui32HALflags & (~(AM_HAL_FLAGS_##flagnm##_M)))  |    \
+     ((value << AM_HAL_FLAGS_##flagnm##_S) & (AM_HAL_FLAGS_##flagnm##_M)) )
+
+//******************************************************************************
+//
+// ITMSKIPENABLEDISABLE - Set when the ITM is not to be disabled.  This is
+//                        typically needed by Keil debug.ini.
+//
+//******************************************************************************
+#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S         0
+#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M         (1 << AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S)
+#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE(n)        (((n) << AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S) & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M)
+
+//******************************************************************************
+//
+// ITMBKPT - Breakpoint at the end of itm_enable(), which is needed by
+//           Keil debug.ini.
+//
+//******************************************************************************
+#define AM_HAL_FLAGS_ITMBKPT_S                      1
+#define AM_HAL_FLAGS_ITMBKPT_M                      (1 << AM_HAL_FLAGS_ITMBKPT_S)
+#define AM_HAL_FLAGS_ITMBKPT(n)                     (((n) << AM_HAL_FLAGS_ITMBKPT_S) & AM_HAL_FLAGS_ITMBKPT_M)
+
+//******************************************************************************
+//
+// Next available flag or bit field.
+//
+//******************************************************************************
+#define AM_HAL_FLAGS_NEXTBITFIELD_S                 2
+#define AM_HAL_FLAGS_NEXTBITFIELD_M                 (1 << AM_HAL_FLAGS_NEXTBITFIELD_S)
+#define AM_HAL_FLAGS_NEXTBITFIELD(n)                (((n) << AM_HAL_FLAGS_NEXTBITFIELD_S) & AM_HAL_FLAGS_NEXTBITFIELD_M)
+
+//*****************************************************************************
+//
+// Global Variables extern declarations.
+//
+//*****************************************************************************
+extern volatile uint32_t g_ui32HALflags;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_GLOBAL_H
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c
new file mode 100644
index 0000000000..480118da6b
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c
@@ -0,0 +1,503 @@
+//*****************************************************************************
+//
+//  am_hal_gpio.c
+//! @file
+//!
+//! @brief Functions for interfacing with the GPIO module
+//!
+//! @addtogroup gpio2 GPIO
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Array of function pointers for handling GPIO interrupts.
+//
+//*****************************************************************************
+am_hal_gpio_handler_t am_hal_gpio_ppfnHandlers[64];
+
+//*****************************************************************************
+//
+//! @brief Read the configuration information for the given pin..
+//!
+//! @param ui32GPIONum is the GPIO number whose configuration we want to read.
+//!
+//! This function reads the PADREG, GPIO CFG, and ALTPAD registers for the
+//! given GPIO and returns them in the following format:
+//!
+//! ( (ALTPAD << 16) | (CFG << 8) | PADREG)
+//!
+//! This is the same format used by the \e am_hal_gpio_pin_config()
+//! function-like macro.
+//!
+//! @return Pin configuration information.
+//
+//*****************************************************************************
+uint32_t
+am_hal_gpio_pin_config_read(uint32_t ui32PinNumber)
+{
+    uint32_t ui32CfgVal, ui32PadregVal, ui32AltPadVal;
+
+    am_hal_debug_assert_msg(ui32PinNumber <= 63, "Invalid GPIO number.");
+
+    ui32CfgVal    = AM_HAL_GPIO_CFG_R(ui32PinNumber);
+    ui32PadregVal = AM_HAL_GPIO_PADREG_R(ui32PinNumber);
+    ui32AltPadVal = AM_HAL_GPIO_ALTPADREG_R(ui32PinNumber);
+
+    return ( (ui32CfgVal    << CFGVAL_GPIOCFG_S)    |
+             (ui32PadregVal << CFGVAL_PADREG_S)     |
+             (ui32AltPadVal << CFGVAL_ALTPAD_S) );
+}
+
+//*****************************************************************************
+//
+//! @brief Get the state of ALL GPIOs from the INPUT READ REGISTER.
+//!
+//! This function retrieves the state of ALL GPIOs from the INPUT READ
+//! REGISTER.
+//!
+//! @return the state for the requested GPIO or -1 for error.
+//
+//*****************************************************************************
+uint64_t
+am_hal_gpio_input_read(void)
+{
+    //
+    // Combine upper or lower GPIO words into one 64 bit return value.
+    //
+    uint64_t ui64RetVal;
+
+    ui64RetVal  = ((uint64_t) AM_REGn(GPIO, 0, RDB)) << 32;
+    ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, RDA)) << 0;
+
+    return ui64RetVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Get the state of ALL GPIOs from the DATA OUTPUT REGISTER.
+//!
+//! This function retrieves the state of ALL GPIOs from the DATA OUTPUT
+//! REGISTER.
+//!
+//! @return the state for the requested GPIO or -1 for error.
+//
+//*****************************************************************************
+uint64_t
+am_hal_gpio_out_read(void)
+{
+    //
+    // Combine upper or lower GPIO words into one 64 bit return value.
+    //
+    uint64_t ui64RetVal;
+
+    ui64RetVal  = ((uint64_t) AM_REGn(GPIO, 0, WTB)) << 32;
+    ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, WTA)) << 0;
+
+    return ui64RetVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Gets the state of one GPIO from the DATA ENABLE REGISTER.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function gets the state of one GPIO from the DATA ENABLE REGISTER.
+//!
+//! @return the current state for the requested GPIO.
+//
+//*****************************************************************************
+uint32_t
+am_hal_gpio_out_enable_bit_get(uint32_t ui32BitNum)
+{
+    //
+    // Return 0 or 1.
+    //
+
+    return (AM_HAL_GPIO_EN(ui32BitNum) & AM_HAL_GPIO_EN_M(ui32BitNum)) ? 1 : 0;
+}
+
+//*****************************************************************************
+//
+//! @brief Gets the state of ALL GPIOs from the DATA ENABLE REGISTER.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function gets the state of all GPIOs from the DATA ENABLE REGISTER.
+//!
+//! @return the current state for the ALL GPIOs.
+//
+//*****************************************************************************
+uint64_t
+am_hal_gpio_out_enable_get(void)
+{
+    //
+    // Combine upper or lower GPIO words into one 64 bit return value.
+    //
+    uint64_t ui64RetVal;
+
+    ui64RetVal  = ((uint64_t) AM_REGn(GPIO, 0, ENB)) << 32;
+    ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, ENA)) << 0;
+
+    return ui64RetVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable selected GPIO Interrupts.
+//!
+//! @param ui64InterruptMask - GPIOs to enable interrupts on.
+//!
+//! Use this function to enable the GPIO interrupts.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_gpio_int_enable(uint64_t ui64InterruptMask)
+{
+    //
+    // Enable the interrupts.
+    //
+    AM_REG(GPIO, INT1EN) |= (ui64InterruptMask >> 32);
+    AM_REG(GPIO, INT0EN) |= (ui64InterruptMask & 0xFFFFFFFF);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable selected GPIO Interrupts.
+//!
+//! Use this function to enable the GPIO interrupts.
+//!
+//! @return logical or of all enabled interrupts. Use AM_HAL_GPIO_BITx to mask
+//! interrupts of interest.
+//
+//*****************************************************************************
+uint64_t
+am_hal_gpio_int_enable_get(void)
+{
+    //
+    // Return enabled interrupts.
+    //
+    uint64_t ui64RetVal;
+
+    ui64RetVal  = ((uint64_t) AM_REGn(GPIO, 0, INT1EN)) << 32;
+    ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, INT0EN)) << 0;
+
+    return ui64RetVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable selected GPIO Interrupts.
+//!
+//! @param ui64InterruptMask - GPIOs to disable interrupts on.
+//!
+//! Use this function to disable the GPIO interrupts.
+//!
+//! ui64InterruptMask should be a logical or of AM_HAL_GPIO_BITx defines.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_gpio_int_disable(uint64_t ui64InterruptMask)
+{
+    //
+    // Disable the interrupts.
+    //
+    AM_CRITICAL_BEGIN_ASM
+    AM_REG(GPIO, INT1EN) &= ~(ui64InterruptMask >> 32);
+    AM_REG(GPIO, INT0EN) &= ~(ui64InterruptMask & 0xFFFFFFFF);
+    AM_CRITICAL_END_ASM
+}
+
+//*****************************************************************************
+//
+//! @brief Clear selected GPIO Interrupts.
+//!
+//! @param ui64InterruptMask - GPIOs to clear interrupts on.
+//!
+//! Use this function to clear the GPIO interrupts.
+//!
+//! ui64InterruptMask should be a logical or of AM_HAL_GPIO_BITx defines.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_gpio_int_clear(uint64_t ui64InterruptMask)
+{
+    //
+    // Clear the interrupts.
+    //
+    AM_CRITICAL_BEGIN_ASM
+    AM_REG(GPIO, INT1CLR) = (ui64InterruptMask >> 32);
+    AM_REG(GPIO, INT0CLR) = (ui64InterruptMask & 0xFFFFFFFF);
+    AM_CRITICAL_END_ASM
+}
+
+//*****************************************************************************
+//
+//! @brief Set selected GPIO Interrupts.
+//!
+//! @param ui64InterruptMask - GPIOs to set interrupts on.
+//!
+//! Use this function to set the GPIO interrupts.
+//!
+//! ui64InterruptMask should be a logical or of AM_HAL_GPIO_BITx defines.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_gpio_int_set(uint64_t ui64InterruptMask)
+{
+    //
+    // Set the interrupts.
+    //
+    AM_REG(GPIO, INT1SET) = (ui64InterruptMask >> 32);
+    AM_REG(GPIO, INT0SET) = (ui64InterruptMask & 0xFFFFFFFF);
+}
+
+//*****************************************************************************
+//
+//! @brief Set selected GPIO Interrupts.
+//!
+//! @param bEnabledOnly - return the status of only the enabled interrupts.
+//!
+//! Use this function to set the GPIO interrupts.
+//!
+//! @return None
+//
+//*****************************************************************************
+uint64_t
+am_hal_gpio_int_status_get(bool bEnabledOnly)
+{
+    uint64_t ui64RetVal, ui64Mask;
+
+    //
+    // Combine upper or lower GPIO words into one 64 bit return value.
+    //
+    ui64Mask   = 0xFFFFFFFFFFFFFFFF;
+
+    AM_CRITICAL_BEGIN_ASM
+    ui64RetVal  = ((uint64_t) AM_REGn(GPIO, 0, INT1STAT)) << 32;
+    ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, INT0STAT)) << 0;
+
+    if ( bEnabledOnly )
+    {
+        ui64Mask    = ((uint64_t) AM_REGn(GPIO, 0, INT1EN)) << 32;
+        ui64Mask   |= ((uint64_t) AM_REGn(GPIO, 0, INT0EN)) << 0;
+    }
+
+    ui64RetVal &= ui64Mask;
+    AM_CRITICAL_END_ASM
+
+    return ui64RetVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Convenience function for responding to pin interrupts.
+//!
+//! @param ui64Status is the interrupt status as returned by
+//! am_hal_gpio_int_status_get()
+//!
+//! This function may be called from am_hal_gpio_isr() to read the status of
+//! the GPIO interrupts, determine which pin(s) caused the most recent
+//! interrupt, and call an interrupt handler function to respond. The interrupt
+//! handler to be called must be first registered with the
+//! am_hal_gpio_int_register() function.
+//!
+//! In the event that multiple GPIO interrupts are active, the corresponding
+//! interrupt handlers will be called in numerical order by GPIO number
+//! starting with the lowest GPIO number.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_gpio_int_service(uint64_t ui64Status)
+{
+    uint32_t ui32Status;
+    uint32_t ui32Clz;
+
+    am_hal_gpio_handler_t pfnHandler;
+
+    //
+    // Handle any active interrupts in the lower 32 bits
+    //
+    ui32Status = (uint32_t) ui64Status;
+    while ( ui32Status )
+    {
+        //
+        // Pick one of any remaining active interrupt bits
+        //
+#ifdef __IAR_SYSTEMS_ICC__
+        ui32Clz = __CLZ(ui32Status);
+#else
+        ui32Clz = __builtin_clz(ui32Status);
+#endif
+
+        //
+        // Turn off the bit we picked in the working copy
+        //
+        ui32Status &= ~(0x80000000 >> ui32Clz);
+
+        //
+        // Check the bit handler table to see if there is an interrupt handler
+        // registered for this particular bit.
+        //
+        pfnHandler = am_hal_gpio_ppfnHandlers[31 - ui32Clz];
+        if ( pfnHandler )
+        {
+            //
+            // If we found an interrupt handler routine, call it now.
+            //
+            pfnHandler();
+        }
+    }
+
+    //
+    // Handle any active interrupts in the upper 32 bits
+    //
+    ui32Status = (uint32_t) (ui64Status >> 32);
+    while ( ui32Status )
+    {
+        //
+        // Pick one of any remaining active interrupt bits
+        //
+#ifdef __IAR_SYSTEMS_ICC__
+        ui32Clz = __CLZ(ui32Status);
+#else
+        ui32Clz = __builtin_clz(ui32Status);
+#endif
+
+        //
+        // Turn off the bit we picked in the working copy
+        //
+        ui32Status &= ~(0x80000000 >> ui32Clz);
+
+        //
+        // Check the bit handler table to see if there is an interrupt handler
+        // registered for this particular bit.
+        //
+        pfnHandler = am_hal_gpio_ppfnHandlers[63 - ui32Clz];
+        if ( pfnHandler )
+        {
+            //
+            // If we found an interrupt handler routine, call it now.
+            //
+            pfnHandler();
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Register an interrupt handler for an individual GPIO pin.
+//!
+//! @param ui32GPIONumber - GPIO number to assign this interrupt handler to.
+//! @param pfnHandler - Function to call when this GPIO interrupt is received.
+//!
+//! This function allows the caller to specify a function that should be called
+//! any time a GPIO interrupt is received on a particular pin. Registering an
+//! interrupt handler using this function adds the function pointer to an array
+//! in SRAM. This interrupt handler will be called by am_hal_gpio_int_service()
+//! whenever the ui64Status parameter indicates that the corresponding pin is
+//! asserting it's interrupt.
+//!
+//! To remove an interrupt handler that has already been registered, the
+//! pfnHandler parameter may be set to zero.
+//!
+//! @note This function will not have any effect unless the
+//! am_hal_gpio_int_service() function is being used.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_gpio_int_register(uint32_t ui32GPIONumber,
+                         am_hal_gpio_handler_t pfnHandler)
+{
+    //
+    // Check to make sure the GPIO number is valid. (Debug builds only)
+    //
+    am_hal_debug_assert_msg(ui32GPIONumber < 64, "GPIO number out of range.");
+
+    am_hal_gpio_ppfnHandlers[ui32GPIONumber] = pfnHandler;
+}
+
+//*****************************************************************************
+//
+//! @brief Get the state of one GPIO polarity bit.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function gets the state of one GPIO polarity bit.
+//!
+//! @note When the bit is a one the interrupt polarity is rising edge.
+//!
+//! @return the current polarity.
+//
+//*****************************************************************************
+bool
+am_hal_gpio_int_polarity_bit_get(uint32_t ui32BitNum)
+{
+    //
+    // Check the GPIO_CFGx register's interrupt polarity bit corresponding to
+    // this pin number.
+    //
+    return (AM_REGVAL(AM_HAL_GPIO_CFG(ui32BitNum)) &
+            AM_HAL_GPIO_POL_M(ui32BitNum));
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h
new file mode 100644
index 0000000000..60e5cf36d6
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h
@@ -0,0 +1,684 @@
+//*****************************************************************************
+//
+//  am_hal_gpio.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the GPIO module.
+//!
+//! @addtogroup gpio2 GPIO
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_HAL_GPIO_H
+#define AM_HAL_GPIO_H
+
+// DEVICE ADDRESS IS 8-bits
+#define AM_HAL_GPIO_DEV_ADDR_8      (0)
+
+// DEVICE ADDRESS IS 16-bits
+#define AM_HAL_GPIO_DEV_ADDR_16     (1)
+
+// DEVICE OFFSET IS 8-bits
+#define AM_HAL_GPIO_DEV_OFFSET_8    (0x00000000)
+
+// DEVICE OFFSET IS 16-bits
+#define AM_HAL_GPIO_DEV_OFFSET_16   (0x00010000)
+
+// Maximum number of GPIOs on this device
+#define AM_HAL_GPIO_MAX_PADS        (50)
+
+//*****************************************************************************
+//
+//! @name GPIO Pin defines
+//! @brief GPIO Pin defines for use with interrupt functions
+//!
+//! These macros may be used to with \e am_hal_gpio_int_x().
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_BIT(n)          (((uint64_t) 0x1) << n)
+//! @}
+
+//
+// Helper macros used for unraveling the GPIO configuration value (configval).
+//
+// Note that the configval, which is passed into functions such as
+//  am_hal_gpio_pin_config() as well as various helper macros, is a concatenated
+//  value that contains values used in multiple configuration registers.
+//
+// The GPIO configuration value fields are arranged as follows:
+// [ 7: 0] PADREG configuration.
+// [11: 8] GPIOCFG
+// [15:12] Unused.
+// [23:16] ALTPADREG configuration.
+//
+// Define macros describing these configval fields.
+//
+#define CFGVAL_PADREG_S             0
+#define CFGVAL_PADREG_M             (0xFF << CFGVAL_PADREG_S)
+#define CFGVAL_GPIOCFG_S            8
+#define CFGVAL_GPIOCFG_M            (0x0F << CFGVAL_GPIOCFG_S)
+#define CFGVAL_ALTPAD_S             16
+#define CFGVAL_ALTPAD_M             (0xFF << CFGVAL_ALTPAD_S)
+
+//
+// Extraction macros
+//
+#define CFGVAL_PADREG_X(x)          (((uint32_t)(x) & CFGVAL_PADREG_M)  >>  \
+                                     CFGVAL_PADREG_S)
+#define CFGVAL_GPIOCFG_X(x)         (((uint32_t)(x) & CFGVAL_GPIOCFG_M) >>  \
+                                     CFGVAL_GPIOCFG_S)
+#define CFGVAL_ALTPAD_X(x)          (((uint32_t)(x) & CFGVAL_ALTPAD_M)  >>  \
+                                     CFGVAL_ALTPAD_S)
+
+//*****************************************************************************
+//
+// Input options.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_INPEN           (0x02 << CFGVAL_PADREG_S)   // Enable input transistors.
+#define AM_HAL_GPIO_INCFG_RDZERO    (0x01 << CFGVAL_GPIOCFG_S)  // Disable input read registers.
+
+//*****************************************************************************
+//
+// Output options
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_OUT_DISABLE     ((0x0 << 1) << CFGVAL_GPIOCFG_S)
+#define AM_HAL_GPIO_OUT_PUSHPULL    ((0x1 << 1) << CFGVAL_GPIOCFG_S)
+#define AM_HAL_GPIO_OUT_OPENDRAIN   ((0x2 << 1) << CFGVAL_GPIOCFG_S)
+#define AM_HAL_GPIO_OUT_3STATE      ((0x3 << 1) << CFGVAL_GPIOCFG_S)
+
+//*****************************************************************************
+//
+// Pad configuration options.
+// (Configuration value bits 7:0.)
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_HIGH_DRIVE      (0x04 << CFGVAL_PADREG_S)
+#define AM_HAL_GPIO_LOW_DRIVE       (0x00 << CFGVAL_PADREG_S)
+#define AM_HAL_GPIO_PULLUP          (0x01 << CFGVAL_PADREG_S)
+#define AM_HAL_GPIO_PULL1_5K        ( (0x01 << CFGVAL_PADREG_S) |   \
+                                      AM_HAL_GPIO_PULLUP )
+#define AM_HAL_GPIO_PULL6K          ( (0x40 << CFGVAL_PADREG_S) |   \
+                                      AM_HAL_GPIO_PULLUP )
+#define AM_HAL_GPIO_PULL12K         ( (0x80 << CFGVAL_PADREG_S) |   \
+                                      AM_HAL_GPIO_PULLUP )
+#define AM_HAL_GPIO_PULL24K         ( (0xC0 << CFGVAL_PADREG_S) |   \
+                                      AM_HAL_GPIO_PULLUP )
+
+// POWER SWITCH is available on selected pins
+#define AM_HAL_GPIO_POWER           (0x80 << CFGVAL_PADREG_S)
+
+//*****************************************************************************
+//
+//! ALTPADREG configuration options.
+//! (Configuration value bits 23:16.)
+//!
+//! All Apollo2 GPIO pins can be configured for 2mA or 4mA.
+//!     AM_HAL_GPIO_DRIVE_2MA  =  2mA configuration.
+//!     AM_HAL_GPIO_DRIVE_4MA  =  4mA configuration.
+//!
+//! Certain Apollo2 GPIO pins can be configured to drive up to 12mA.
+//!     AM_HAL_GPIO_DRIVE_8MA  =  8mA configuration.
+//!     AM_HAL_GPIO_DRIVE_12MA = 12mA configuration.
+//!
+//! Notes:
+//! - Always consult the Apollo2 data sheet for the latest details.
+//! - The higher drive GPIOxx pads generally include:
+//!   0-2,5,7-8,10,12-13,22-23,26-29,38-39,42,44-48.
+//! - GPIOxx pads that do not support the higher drive:
+//!   3-4,6,9,11,14-21,24-25,30-37,40-41,43,49.
+//! - User is responsible for ensuring that the selected pin actually supports
+//!   the higher drive (8mA or 12mA) capabilities. See the Apollo2 data sheet.
+//! - Attempting to set the higher drive (8mA or 12mA) configuration on a
+//!   non-supporting pad will actually set the pad for 4mA drive strength,
+//!   regardless of the lower bit setting.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_DRIVE_2MA       ( 0 )
+#define AM_HAL_GPIO_DRIVE_4MA       AM_HAL_GPIO_HIGH_DRIVE
+#define AM_HAL_GPIO_DRIVE_8MA       ( 0x01 << CFGVAL_ALTPAD_S )
+#define AM_HAL_GPIO_DRIVE_12MA      ( (0x01 << CFGVAL_ALTPAD_S)  |  \
+                                      AM_HAL_GPIO_HIGH_DRIVE )
+
+#define AM_HAL_GPIO_SLEWRATE        ( 0x10 << CFGVAL_ALTPAD_S )
+
+//*****************************************************************************
+//
+// Interrupt polarity
+// These values can be used directly in the configval.
+//
+//*****************************************************************************
+#define AM_HAL_GPIOCFGVAL_FALLING   ((1 << 2) << CFGVAL_GPIOCFG_S)
+#define AM_HAL_GPIOCFGVAL_RISING    ((0 << 2) << CFGVAL_GPIOCFG_S)
+
+//*****************************************************************************
+//
+// Pad function select
+// This macro represents the 3 bit function select field in the PADREG byte.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_FUNC(x)         ((x & 0x7) << 3)
+
+//*****************************************************************************
+//
+//! Interrupt polarity
+//!
+//! Important:
+//!  These values are to be used with am_hal_gpio_int_polarity_bit_set().
+//   They are not intended to be used as part of the GPIO configval.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_FALLING         0x00000001
+#define AM_HAL_GPIO_RISING          0x00000000
+
+//*****************************************************************************
+//
+// A few common pin configurations.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_DISABLE                                                   \
+    (AM_HAL_GPIO_FUNC(3))
+
+#define AM_HAL_GPIO_INPUT                                                     \
+    (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_INPEN)
+
+#define AM_HAL_GPIO_OUTPUT                                                    \
+    (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_PUSHPULL)
+
+#define AM_HAL_GPIO_OPENDRAIN                                                 \
+    (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_OPENDRAIN | AM_HAL_GPIO_INPEN)
+
+#define AM_HAL_GPIO_3STATE                                                    \
+    (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_3STATE)
+
+//*****************************************************************************
+//
+// PADREG helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_PADREG(n)                                                 \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_PADREGA_O + (n & 0xFC))
+
+#define AM_HAL_GPIO_PADREG_S(n)                                               \
+    (((uint32_t)(n) % 4) << 3)
+
+#define AM_HAL_GPIO_PADREG_M(n)                                               \
+    ((uint32_t) 0xFF << AM_HAL_GPIO_PADREG_S(n))
+
+#define AM_HAL_GPIO_PADREG_FIELD(n, configval)                                \
+    (((uint32_t)(configval) & CFGVAL_PADREG_M) << AM_HAL_GPIO_PADREG_S(n))
+
+#define AM_HAL_GPIO_PADREG_W(n, configval)                                    \
+    AM_REGVAL(AM_HAL_GPIO_PADREG(n)) =                                        \
+        (AM_HAL_GPIO_PADREG_FIELD(n, configval) |                             \
+         (AM_REGVAL(AM_HAL_GPIO_PADREG(n)) & ~AM_HAL_GPIO_PADREG_M(n)))
+
+#define AM_HAL_GPIO_PADREG_R(n)                                               \
+    ((AM_REGVAL(AM_HAL_GPIO_PADREG(n)) & AM_HAL_GPIO_PADREG_M(n)) >>          \
+     AM_HAL_GPIO_PADREG_S(n))
+
+
+//*****************************************************************************
+//
+// ALTPADCFG helper macros.
+// The ALTPADCFG bits are located in [23:16] of the configval.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_ALTPADREG(n)                                              \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_ALTPADCFGA_O + (n & 0xFC))
+
+#define AM_HAL_GPIO_ALTPADREG_S(n)                                            \
+    (((uint32_t)(n) % 4) << 3)
+
+#define AM_HAL_GPIO_ALTPADREG_M(n)                                            \
+    ((uint32_t) 0xFF << AM_HAL_GPIO_ALTPADREG_S(n))
+
+#define AM_HAL_GPIO_ALTPADREG_FIELD(n, configval)                             \
+        (CFGVAL_ALTPAD_X(configval) << AM_HAL_GPIO_ALTPADREG_S(n))
+
+#define AM_HAL_GPIO_ALTPADREG_W(n, configval)                                 \
+    AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) =                                     \
+        (AM_HAL_GPIO_ALTPADREG_FIELD(n, configval) |                          \
+         (AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) & ~AM_HAL_GPIO_ALTPADREG_M(n)))
+
+#define AM_HAL_GPIO_ALTPADREG_R(n)                                            \
+    ((AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) & AM_HAL_GPIO_ALTPADREG_M(n)) >>    \
+     AM_HAL_GPIO_ALTPADREG_S(n))
+
+//*****************************************************************************
+//
+// CFG helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_CFG(n)                                                    \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_CFGA_O + ((n & 0xF8) >> 1))
+
+#define AM_HAL_GPIO_CFG_S(n)                                                  \
+    (((uint32_t)(n) % 8) << 2)
+
+#define AM_HAL_GPIO_CFG_M(n)                                                  \
+    ((uint32_t) 0x7 << AM_HAL_GPIO_CFG_S(n))
+
+#define AM_HAL_GPIO_CFG_FIELD(n, configval)                                   \
+    ((((uint32_t)(configval) & 0x700) >> 8) << AM_HAL_GPIO_CFG_S(n))
+
+#define AM_HAL_GPIO_CFG_W(n, configval)                                       \
+    AM_REGVAL(AM_HAL_GPIO_CFG(n)) =                                           \
+        (AM_HAL_GPIO_CFG_FIELD(n, configval) |                                \
+         (AM_REGVAL(AM_HAL_GPIO_CFG(n)) & ~AM_HAL_GPIO_CFG_M(n)))
+
+#define AM_HAL_GPIO_CFG_R(n)                                                  \
+    ((AM_REGVAL(AM_HAL_GPIO_CFG(n)) & AM_HAL_GPIO_CFG_M(n)) >>                \
+     AM_HAL_GPIO_CFG_S(n))
+
+//*****************************************************************************
+//
+// Polarity helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_POL_S(n)                                                  \
+    ((((uint32_t)(n) % 8) << 2) + 3)
+
+#define AM_HAL_GPIO_POL_M(n)                                                  \
+    ((uint32_t) 0x1 << AM_HAL_GPIO_POL_S(n))
+
+#define AM_HAL_GPIO_POL_FIELD(n, polarity)                                    \
+    (((uint32_t)(polarity) & 0x1) << AM_HAL_GPIO_POL_S(n))
+
+#define AM_HAL_GPIO_POL_W(n, polarity)                                        \
+    AM_REGVAL(AM_HAL_GPIO_CFG(n)) =                                           \
+        (AM_HAL_GPIO_POL_FIELD(n, polarity) |                                 \
+         (AM_REGVAL(AM_HAL_GPIO_CFG(n)) & ~AM_HAL_GPIO_POL_M(n)))
+
+//*****************************************************************************
+//
+// RD helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_RD_REG(n)                                                 \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_RDA_O + (((uint32_t)(n) & 0x20) >> 3))
+
+#define AM_HAL_GPIO_RD_S(n)                                                   \
+    ((uint32_t)(n) % 32)
+
+#define AM_HAL_GPIO_RD_M(n)                                                   \
+    ((uint32_t) 0x1 << AM_HAL_GPIO_RD_S(n))
+
+#define AM_HAL_GPIO_RD(n)                                                     \
+    AM_REGVAL(AM_HAL_GPIO_RD_REG(n))
+
+//*****************************************************************************
+//
+// WT helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_WT_REG(n)                                                 \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_WTA_O + (((uint32_t)(n) & 0x20) >> 3))
+
+#define AM_HAL_GPIO_WT_S(n)                                                   \
+    ((uint32_t)(n) % 32)
+
+#define AM_HAL_GPIO_WT_M(n)                                                   \
+    ((uint32_t) 0x1 << AM_HAL_GPIO_WT_S(n))
+
+#define AM_HAL_GPIO_WT(n)                                                     \
+    AM_REGVAL(AM_HAL_GPIO_WT_REG(n))
+
+//*****************************************************************************
+//
+// WTS helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_WTS_REG(n)                                                \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_WTSA_O + (((uint32_t)(n) & 0x20) >> 3))
+
+#define AM_HAL_GPIO_WTS_S(n)                                                  \
+    ((uint32_t)(n) % 32)
+
+#define AM_HAL_GPIO_WTS_M(n)                                                  \
+    ((uint32_t) 0x1 << AM_HAL_GPIO_WTS_S(n))
+
+#define AM_HAL_GPIO_WTS(n)                                                    \
+    AM_REGVAL(AM_HAL_GPIO_WTS_REG(n))
+
+//*****************************************************************************
+//
+// WTC helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_WTC_REG(n)                                                \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_WTCA_O + (((uint32_t)(n) & 0x20) >> 3))
+
+#define AM_HAL_GPIO_WTC_S(n)                                                  \
+    ((uint32_t)(n) % 32)
+
+#define AM_HAL_GPIO_WTC_M(n)                                                  \
+    ((uint32_t) 0x1 << AM_HAL_GPIO_WTC_S(n))
+
+#define AM_HAL_GPIO_WTC(n)                                                    \
+    AM_REGVAL(AM_HAL_GPIO_WTC_REG(n))
+
+//*****************************************************************************
+//
+// EN helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_EN_REG(n)                                                 \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_ENA_O + (((uint32_t)(n) & 0x20) >> 3))
+
+#define AM_HAL_GPIO_EN_S(n)                                                   \
+    ((uint32_t)(n) % 32)
+
+#define AM_HAL_GPIO_EN_M(n)                                                   \
+    ((uint32_t) 0x1 << AM_HAL_GPIO_EN_S(n))
+
+#define AM_HAL_GPIO_EN(n)                                                     \
+    AM_REGVAL(AM_HAL_GPIO_EN_REG(n))
+
+//*****************************************************************************
+//
+// ENS helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_ENS_REG(n)                                                \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_ENSA_O + (((uint32_t)(n) & 0x20) >> 3))
+
+#define AM_HAL_GPIO_ENS_S(n)                                                  \
+    ((uint32_t)(n) % 32)
+
+#define AM_HAL_GPIO_ENS_M(n)                                                  \
+    ((uint32_t) 0x1 << AM_HAL_GPIO_ENS_S(n))
+
+#define AM_HAL_GPIO_ENS(n)                                                    \
+    AM_REGVAL(AM_HAL_GPIO_ENS_REG(n))
+
+//*****************************************************************************
+//
+// ENC helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_GPIO_ENC_REG(n)                                                \
+    (AM_REG_GPIOn(0) + AM_REG_GPIO_ENCA_O + (((uint32_t)(n) & 0x20) >> 3))
+
+#define AM_HAL_GPIO_ENC_S(n)                                                  \
+    ((uint32_t)(n) % 32)
+
+#define AM_HAL_GPIO_ENC_M(n)                                                  \
+    ((uint32_t) 0x1 << AM_HAL_GPIO_ENC_S(n))
+
+#define AM_HAL_GPIO_ENC(n)                                                    \
+    AM_REGVAL(AM_HAL_GPIO_ENC_REG(n))
+
+//*****************************************************************************
+//
+//! @brief Configure the GPIO PAD MUX & GPIO PIN Configurations
+//!
+//! @param ui32PinNumber - GPIO pin number.
+//! @param ui32Config - Configuration options.
+//!
+//! This function applies the settings for a single GPIO. For a list of valid
+//! options please see the top of this file (am_hal_gpio.h) and am_hal_pin.h.
+//!
+//! Usage examples:
+//! am_hal_gpio_pin_config(11, AM_HAL_GPIO_INPUT);
+//! am_hal_gpio_pin_config(10, AM_HAL_GPIO_OUTPUT);
+//! am_hal_gpio_pin_config(14, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_SLEWRATE);
+//! am_hal_gpio_pin_config(15, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_HIGHDRIVESTR);
+//
+//*****************************************************************************
+#define am_hal_gpio_pin_config(ui32PinNumber, ui32Config)                     \
+    if ( (uint32_t)(ui32PinNumber) < AM_HAL_GPIO_MAX_PADS )                   \
+    {                                                                         \
+        AM_CRITICAL_BEGIN_ASM                                                 \
+                                                                              \
+        AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL;                 \
+                                                                              \
+        AM_HAL_GPIO_CFG_W(ui32PinNumber, ui32Config);                         \
+        AM_HAL_GPIO_PADREG_W(ui32PinNumber, ui32Config);                      \
+        AM_HAL_GPIO_ALTPADREG_W(ui32PinNumber, ui32Config);                   \
+                                                                              \
+        AM_REGn(GPIO, 0, PADKEY) = 0;                                         \
+                                                                              \
+        AM_CRITICAL_END_ASM                                                   \
+    }
+
+//*****************************************************************************
+//
+//! @brief Set the state of one GPIO polarity bit.
+//!
+//! @param ui32BitNum - GPIO number.
+//! @param ui32Polarity - Desired state.
+//!
+//! This function sets the state of one GPIO polarity bit to a supplied value.
+//! The ui32Polarity parameter should be one of the following values:
+//!
+//!     AM_HAL_GPIO_FALLING
+//!     AM_HAL_GPIO_RISING
+//!
+//! @return None.
+//
+//*****************************************************************************
+#define am_hal_gpio_int_polarity_bit_set(ui32PinNumber, ui32Polarity)         \
+    if ( (uint32_t)(ui32PinNumber) < AM_HAL_GPIO_MAX_PADS )                   \
+    {                                                                         \
+        AM_CRITICAL_BEGIN_ASM                                                 \
+                                                                              \
+        AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL;                 \
+        AM_HAL_GPIO_POL_W(ui32PinNumber, ui32Polarity);                       \
+        AM_REGn(GPIO, 0, PADKEY) = 0;                                         \
+                                                                              \
+        AM_CRITICAL_END_ASM                                                   \
+    }
+
+//*****************************************************************************
+//
+//! @brief Get the state of one GPIO from the INPUT READ REGISTER.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function retrieves the state of one GPIO from the INPUT READ
+//! REGISTER.
+//!
+//! @return the state for the requested GPIO.
+//
+//*****************************************************************************
+#define am_hal_gpio_input_bit_read(ui32BitNum)                                \
+    ((AM_HAL_GPIO_RD(ui32BitNum) & AM_HAL_GPIO_RD_M(ui32BitNum)) != 0)
+
+//*****************************************************************************
+//
+//! @brief Get the state of one GPIO in the DATA OUTPUT REGISTER
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function retrieves the state of one GPIO in the DATA OUTPUT REGISTER.
+//!
+//! @return the state for the requested GPIO or -1 for error.
+//
+//*****************************************************************************
+#define am_hal_gpio_out_bit_read(ui32BitNum)                                  \
+    ((AM_HAL_GPIO_WT(ui32BitNum) & AM_HAL_GPIO_WT_M(ui32BitNum)) != 0)
+
+//*****************************************************************************
+//
+//! @brief Set the output state high for one GPIO.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function sets the output state to high for one GPIO.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#define am_hal_gpio_out_bit_set(ui32BitNum)                                   \
+    AM_HAL_GPIO_WTS(ui32BitNum) = AM_HAL_GPIO_WTS_M(ui32BitNum)
+
+//*****************************************************************************
+//
+//! @brief Sets the output state to low for one GPIO.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function sets the output state to low for one GPIO.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#define am_hal_gpio_out_bit_clear(ui32BitNum)                                 \
+    AM_HAL_GPIO_WTC(ui32BitNum) = AM_HAL_GPIO_WTC_M(ui32BitNum)
+
+//*****************************************************************************
+//
+//! @brief Sets the output state to ui32Value for one GPIO.
+//!
+//! @param ui32BitNum - GPIO number.
+//! @param ui32Value - Desired output state.
+//!
+//! This function sets the output state to ui32Value for one GPIO.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#define am_hal_gpio_out_bit_replace(ui32BitNum, ui32Value)                    \
+    if ( ui32Value )                                                          \
+    {                                                                         \
+        AM_HAL_GPIO_WTS(ui32BitNum) = AM_HAL_GPIO_WTS_M(ui32BitNum);          \
+    }                                                                         \
+    else                                                                      \
+    {                                                                         \
+        AM_HAL_GPIO_WTC(ui32BitNum) = AM_HAL_GPIO_WTC_M(ui32BitNum);          \
+    }
+
+//*****************************************************************************
+//
+//! @brief Toggle the output state of one GPIO.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function toggles the output state of one GPIO.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#define am_hal_gpio_out_bit_toggle(ui32BitNum)                                \
+    if ( 1 )                                                                  \
+    {                                                                         \
+        AM_CRITICAL_BEGIN_ASM                                                 \
+        AM_HAL_GPIO_WT(ui32BitNum) ^= AM_HAL_GPIO_WT_M(ui32BitNum);           \
+        AM_CRITICAL_END_ASM                                                   \
+    }
+
+//*****************************************************************************
+//
+//! @brief Sets the output enable for one GPIO.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function sets the output enable for one GPIO.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#define am_hal_gpio_out_enable_bit_set(ui32BitNum)                            \
+    AM_HAL_GPIO_ENS(ui32BitNum) = AM_HAL_GPIO_ENS_M(ui32BitNum)
+
+//*****************************************************************************
+//
+//! @brief Clears the output enable for one GPIO.
+//!
+//! @param ui32BitNum - GPIO number.
+//!
+//! This function clears the output enable for one GPIO.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#define am_hal_gpio_out_enable_bit_clear(ui32BitNum)                          \
+    AM_HAL_GPIO_ENC(ui32BitNum) = AM_HAL_GPIO_ENC_M(ui32BitNum)
+
+//*****************************************************************************
+//
+// Function pointer type for GPIO interrupt handlers.
+//
+//*****************************************************************************
+typedef void (*am_hal_gpio_handler_t)(void);
+
+//*****************************************************************************
+//
+// External function prototypes
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+extern uint32_t am_hal_gpio_pin_config_read(uint32_t ui32PinNumber);
+extern uint64_t am_hal_gpio_input_read(void);
+extern uint64_t am_hal_gpio_out_read(void);
+extern uint32_t am_hal_gpio_out_enable_bit_get(uint32_t ui32BitNum);
+extern uint64_t am_hal_gpio_out_enable_get(void);
+extern void am_hal_gpio_int_enable(uint64_t ui64InterruptMask);
+extern uint64_t am_hal_gpio_int_enable_get(void);
+extern void am_hal_gpio_int_disable(uint64_t ui64InterruptMask);
+extern void am_hal_gpio_int_clear(uint64_t ui64InterruptMask);
+extern void am_hal_gpio_int_set(uint64_t ui64InterruptMask);
+extern uint64_t am_hal_gpio_int_status_get(bool bEnabledOnly);
+extern void am_hal_gpio_int_service(uint64_t ui64Status);
+extern void am_hal_gpio_int_register(uint32_t ui32GPIONumber,
+                                     am_hal_gpio_handler_t pfnHandler);
+
+extern bool am_hal_gpio_int_polarity_bit_get(uint32_t ui32BitNum);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // AM_HAL_GPIO_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c
new file mode 100644
index 0000000000..603dd8c4ec
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c
@@ -0,0 +1,757 @@
+//*****************************************************************************
+//
+//  am_hal_i2c_bit_bang.c
+//! @file
+//!
+//! @brief I2C bit bang module.
+//!
+//! These functions implement the I2C bit bang utility
+//! It implements an I2C interface at close to 400 kHz
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "am_mcu_apollo.h"
+#include "am_util.h"
+#include "am_hal_i2c_bit_bang.h"
+
+// Max number of clock cycles to wait for clock stretch
+#define I2C_BB_MAX_CLOCK_STRETCH_WAIT               100
+
+#define I2C_BB_DESIRED_FREQ_HZ                      400000
+
+#define I2C_BB_CYCLES_PER_DELAY_COUNT               3
+#define I2C_BB_ONE_BIT_TIME_IN_CYCLES               (AM_HAL_CLKGEN_FREQ_MAX_HZ/I2C_BB_DESIRED_FREQ_HZ)
+#define I2C_BB_ONE_BIT_TIME_IN_DELAY_COUNT          (I2C_BB_ONE_BIT_TIME_IN_CYCLES/I2C_BB_CYCLES_PER_DELAY_COUNT)
+
+// Number of loops (each worth 3 cycles) needed to delay for defined time
+// This is imprecise, as there is a setup time as well which is not accounted
+// for
+// One Bit time = 120 Cycles (400 kHz @ 48 MHz)
+#define HALF_BIT_TIME    (I2C_BB_ONE_BIT_TIME_IN_DELAY_COUNT/2)
+#define QUARTER_BIT_TIME (I2C_BB_ONE_BIT_TIME_IN_DELAY_COUNT/4)
+#define ASM_DELAY        am_hal_flash_delay
+
+// Empirically determined adjustments to account for the fact that there is a
+// variable time spent in actual processing as well, and hence we need not delay
+// for the full time. This processing time is variable based on exact processing
+// needed at various times, and will also vary based on compiler type and
+// optimization levels
+#define I2C_BB_TIMER_ADJUST     6 // Can not be more than QUARTER_BIT_TIME - 1
+#define I2C_BB_TIMER_HI_ADJUST  15 // Can not be more than HALF_BIT_TIME - 1
+#define I2C_BB_TIMER_LO_ADJUST  13 // Can not be more than HALF_BIT_TIME - 1
+
+// Wait till it is time to end the SCL Hi Period
+#define WAIT_I2C_CLOCK_HI_PERIOD()     ASM_DELAY(HALF_BIT_TIME - I2C_BB_TIMER_HI_ADJUST)
+// Wait till it is time to end the SCL Lo Period
+#define WAIT_I2C_CLOCK_LOW_PERIOD()    ASM_DELAY(HALF_BIT_TIME - I2C_BB_TIMER_LO_ADJUST)
+// Delay for Quarter Clock
+#define WAIT_FOR_QUARTER_I2C_CLOCK()   ASM_DELAY(QUARTER_BIT_TIME - I2C_BB_TIMER_ADJUST)
+#define WRITE_SCL_LO()    \
+    do { \
+        AM_REGVAL(am_hal_i2c_bit_bang_priv.sck_reg_clr_addr) = (am_hal_i2c_bit_bang_priv.sck_reg_val); \
+    } while(0)
+
+#define PULL_SCL_HI()    \
+    do { \
+        AM_REGVAL(am_hal_i2c_bit_bang_priv.sck_reg_set_addr) = (am_hal_i2c_bit_bang_priv.sck_reg_val); \
+    } while(0)
+
+#define GET_SCL()   (AM_REGVAL(am_hal_i2c_bit_bang_priv.sck_reg_read_addr) & (am_hal_i2c_bit_bang_priv.sck_reg_val))
+#define GET_SDA()   (AM_REGVAL(am_hal_i2c_bit_bang_priv.sda_reg_read_addr) & (am_hal_i2c_bit_bang_priv.sda_reg_val))
+
+#define WRITE_SDA_LO()    \
+    do { \
+        AM_REGVAL(am_hal_i2c_bit_bang_priv.sda_reg_clr_addr) = (am_hal_i2c_bit_bang_priv.sda_reg_val); \
+    } while(0)
+
+#define PULL_SDA_HI()    \
+    do { \
+        AM_REGVAL(am_hal_i2c_bit_bang_priv.sda_reg_set_addr) = (am_hal_i2c_bit_bang_priv.sda_reg_val); \
+    } while(0)
+
+
+//*****************************************************************************
+//
+// I2C Bit Bang Private Data Structure
+//
+//*****************************************************************************
+typedef struct am_util_bit_bang_priv
+{
+    bool  start_flag;
+    uint32_t sck_gpio_number;
+    uint32_t sda_gpio_number;
+    uint32_t sck_reg_set_addr;
+    uint32_t sck_reg_clr_addr;
+    uint32_t sck_reg_read_addr;
+    uint32_t sck_reg_val;
+    uint32_t sda_reg_set_addr;
+    uint32_t sda_reg_clr_addr;
+    uint32_t sda_reg_read_addr;
+    uint32_t sda_reg_val;
+} am_hal_i2c_bit_bang_priv_t;
+static am_hal_i2c_bit_bang_priv_t am_hal_i2c_bit_bang_priv;
+
+//
+// Wait for any stretched clock to go high
+// If it times out - return failure
+//
+static inline bool
+i2c_pull_and_wait_scl_hi(void)
+{
+    // Maximum time to wait for clock stretching
+    uint32_t maxLoop = 4*I2C_BB_MAX_CLOCK_STRETCH_WAIT + 1;
+    // Pull SCL High
+    PULL_SCL_HI();
+    // Poll for SCL to check for clock stretching
+    while (!GET_SCL())
+    {
+        if (--maxLoop == 0)
+        {
+            // timeout!
+            return true;
+        }
+        WAIT_FOR_QUARTER_I2C_CLOCK();
+    }
+    return false;
+}
+
+//*****************************************************************************
+//
+//! @brief Initialize i2c bit bang private data structure
+//!
+//! @param sck_gpio_number is the GPIO # for the I2C SCK clock pin
+//! @param sda_gpio_number is the GPIO # for the I2C SDA data pin
+//!
+//! This function initializes the I2C bit bang utility's internal data struct.
+//!
+//! returns None.
+//
+//*****************************************************************************
+am_hal_i2c_bit_bang_enum_t
+am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
+                         uint32_t sda_gpio_number)
+{
+    int i;
+    //
+    // remember GPIO pin assignments for I2C bus signals
+    //
+    am_hal_i2c_bit_bang_priv.sck_gpio_number = sck_gpio_number;
+    am_hal_i2c_bit_bang_priv.sda_gpio_number = sda_gpio_number;
+
+    am_hal_i2c_bit_bang_priv.sck_reg_set_addr = AM_HAL_GPIO_WTS_REG(sck_gpio_number);
+    am_hal_i2c_bit_bang_priv.sck_reg_clr_addr = AM_HAL_GPIO_WTC_REG(sck_gpio_number);
+    am_hal_i2c_bit_bang_priv.sck_reg_read_addr = AM_HAL_GPIO_RD_REG(sck_gpio_number);
+    am_hal_i2c_bit_bang_priv.sck_reg_val = AM_HAL_GPIO_WTC_M(sck_gpio_number);
+    am_hal_i2c_bit_bang_priv.sda_reg_set_addr = AM_HAL_GPIO_WTS_REG(sda_gpio_number);
+    am_hal_i2c_bit_bang_priv.sda_reg_clr_addr = AM_HAL_GPIO_WTC_REG(sda_gpio_number);
+    am_hal_i2c_bit_bang_priv.sda_reg_read_addr = AM_HAL_GPIO_RD_REG(sda_gpio_number);
+    am_hal_i2c_bit_bang_priv.sda_reg_val =  AM_HAL_GPIO_WTC_M(sda_gpio_number);
+
+    //
+    // Set SCK GPIO data bit high so we aren't pulling down the clock
+    //
+    am_hal_gpio_out_bit_set(sck_gpio_number);
+    //
+    // Set up SCK GPIO configuration bi-direction, input
+    //
+    am_hal_gpio_pin_config(sck_gpio_number, AM_HAL_PIN_OPENDRAIN);
+
+    //
+    // Set SDA GPIO data bit high so we aren't pulling down the data line
+    //
+    am_hal_gpio_out_bit_set(sda_gpio_number);
+    //
+    // Set up SDA GPIO configuration bi-direction, input
+    //
+    am_hal_gpio_pin_config(sda_gpio_number, AM_HAL_PIN_OPENDRAIN);
+
+    // Now make sure we have control of the clock line
+    //
+    // Wait for any stretched clock to go high. Return if still not high
+    //
+    if (i2c_pull_and_wait_scl_hi())
+    {
+        return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+    }
+    if (!GET_SDA())
+    {
+        // If previous transaction did not finish - SDA may be pulled low for a Read.
+        // If so - need to flush out the data (max 8 bits) & NACK
+        for (i = 0; i < 9; i++)
+        {
+            //
+            // Pull down on clock line
+            //
+            WRITE_SCL_LO();
+            //
+            // Delay for 1/2 bit cell time to start the clock and let peer write on SDA
+            //
+            WAIT_I2C_CLOCK_LOW_PERIOD();
+            if (i2c_pull_and_wait_scl_hi())
+            {
+                return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+            }
+            if (GET_SDA())
+            {
+                // Send START/STOP to clear the bus
+                //
+                // Delay for 1/4 bit cell time
+                //
+                WAIT_FOR_QUARTER_I2C_CLOCK();
+                WRITE_SDA_LO();
+                //
+                // Delay for 1/4 bit cell time
+                //
+                WAIT_FOR_QUARTER_I2C_CLOCK();
+                //
+                // Pull down on clock line
+                //
+                WRITE_SCL_LO();
+                //
+                // Delay for 1/2 bit cell time to start the clock and let peer write on SDA
+                //
+                WAIT_I2C_CLOCK_LOW_PERIOD();
+                //
+                // Release the clock line
+                //
+                PULL_SCL_HI();
+                //
+                // Delay for 1/4 bit cell time
+                //
+                WAIT_FOR_QUARTER_I2C_CLOCK();
+                PULL_SDA_HI();
+                //
+                // Delay for 1/4 bit cell time
+                //
+                WAIT_FOR_QUARTER_I2C_CLOCK();
+                break;
+            }
+        }
+        if (i == 9)
+        {
+            // It is it still stuck after 9 clocks - something is wrong. Need to bail out
+            return AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT;
+        }
+    }
+    return AM_HAL_I2C_BIT_BANG_SUCCESS;
+}
+
+//*****************************************************************************
+//
+//! @brief Receive one data byte from an I2C device
+//!
+//! This function handles sending one byte to a slave device
+//! bNack defines if we should send an ACK or NACK
+//!
+//! returns the byte received
+//
+//*****************************************************************************
+static inline am_hal_i2c_bit_bang_enum_t
+i2c_receive_byte(uint8_t *pRxByte, bool bNack)
+{
+    int i;
+    uint8_t data_byte = 0;
+
+    //
+    // Loop through receiving 8 bits
+    //
+    for (i = 0; i < 8; i++)
+    {
+        //
+        // Pull down on clock line
+        //
+        WRITE_SCL_LO();
+
+        //
+        // release the data line from from the previous ACK
+        //
+        PULL_SDA_HI();
+
+        //
+        // Delay for 1/2 bit cell time to start the clock and let peer write on SDA
+        //
+        WAIT_I2C_CLOCK_LOW_PERIOD();
+
+        if (i2c_pull_and_wait_scl_hi())
+        {
+            return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+        }
+        //
+        // grab the data bit here
+        //
+        if ( GET_SDA() )
+        {
+            //
+            // set the bit in the data byte to be returned
+            //
+            data_byte |=  (0x80 >> i);
+        }
+
+        //
+        // Delay for 1/2 bit cell time while clock is high
+        //
+        WAIT_I2C_CLOCK_HI_PERIOD();
+    }
+
+    *pRxByte = data_byte;
+    //
+    // Pull down on clock line
+    //
+    WRITE_SCL_LO();
+
+    //
+    // pull the data line down so we can ACK/NAK the byte we just received
+    //
+    if (bNack)
+    {
+        //
+        // Pull up on data line with clock low to indicate NAK
+        //
+        PULL_SDA_HI();
+    }
+    else
+    {
+        //
+        // Pull down on data line with clock low to indicate ACK
+        //
+        WRITE_SDA_LO();
+    }
+    //
+    // Delay for 1/2 bit cell time before sending ACK to device
+    //
+    WAIT_I2C_CLOCK_LOW_PERIOD();
+
+    if (i2c_pull_and_wait_scl_hi())
+    {
+        return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+    }
+    //
+    // Delay for 1/2 bit cell time while clock is high to le peer sample the ACK/NAK
+    //
+    WAIT_I2C_CLOCK_HI_PERIOD();
+    //
+    // Give the received data byte back to them
+    //
+    return AM_HAL_I2C_BIT_BANG_SUCCESS;
+}
+
+//*****************************************************************************
+//
+//! @brief Send one data bytes to an I2C device
+//!
+//! @param one_byte the byte to send, could be address could be data
+//!
+//! This function handles sending one byte to a slave device
+//! Starts with 0 clock and runs till full cycle
+//!
+//! returns I2C BB ENUM
+//!     {
+//!     AM_HAL_I2C_BIT_BANG_SUCCESS,
+//!     AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED
+//!     }
+//
+//*****************************************************************************
+static inline am_hal_i2c_bit_bang_enum_t
+i2c_send_byte(uint8_t one_byte)
+{
+    int i;
+    bool data_naked = false;
+
+    //
+    // Loop through sending 8 bits
+    //
+    for (i = 0; i < 8; i++)
+    {
+        //
+        // Pull down on clock line
+        //
+        WRITE_SCL_LO();
+
+        //
+        // output the next data bit
+        //
+        if ( one_byte & (0x80 >> i) )
+        {
+            PULL_SDA_HI();
+        }
+        else
+        {
+            WRITE_SDA_LO();
+        }
+
+        //
+        // Delay for 1/2 bit cell time to start the clock
+        //
+        WAIT_I2C_CLOCK_LOW_PERIOD();
+
+        if (i2c_pull_and_wait_scl_hi())
+        {
+            return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+        }
+        //
+        // Delay for 1/2 bit cell time while clock is high
+        //
+        WAIT_I2C_CLOCK_HI_PERIOD();
+    }
+
+    //
+    // Pull down on clock line
+    //
+    WRITE_SCL_LO();
+
+    //
+    // Delay for 1/2 bit cell time to start the clock
+    //
+    WAIT_I2C_CLOCK_LOW_PERIOD();
+
+    if (i2c_pull_and_wait_scl_hi())
+    {
+        return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+    }
+    //
+    // Grab the state of the ACK bit and return it
+    //
+    data_naked = GET_SDA();
+    //
+    // Delay for 1/2 bit cell time to complete the high period
+    //
+    WAIT_I2C_CLOCK_HI_PERIOD();
+    if ( data_naked )
+    {
+        return AM_HAL_I2C_BIT_BANG_DATA_NAKED;
+    }
+    else
+    {
+        return AM_HAL_I2C_BIT_BANG_SUCCESS;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Receive a string of data bytes from an I2C device
+//!
+//! @param address (only 8 bit I2C addresses are supported)
+//!        LSB is I2C R/W
+//! @param number_of_bytes to transfer (# payload bytes)
+//! @param pData pointer to data buffer to receive payload
+//!
+//! This function handles receiving a payload from a slave device
+//!
+//! returns ENUM{AM_HAL_I2C_BIT_BANG_SUCCESS,AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED}
+//
+//*****************************************************************************
+am_hal_i2c_bit_bang_enum_t
+am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes,
+                            uint8_t *pData, uint8_t ui8Offset,
+                            bool bUseOffset, bool bNoStop)
+{
+    uint32_t ui32I;
+    am_hal_i2c_bit_bang_enum_t status = AM_HAL_I2C_BIT_BANG_SUCCESS;
+
+
+    if (i2c_pull_and_wait_scl_hi())
+    {
+        return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+    }
+    //
+    // Pull down on data line with clock high --> START CONDITION
+    //
+    WRITE_SDA_LO();
+
+    //
+    // Delay for 1/2 bit cell time to start the clock
+    //
+    WAIT_I2C_CLOCK_HI_PERIOD();
+
+    //
+    // send the address byte and wait for the ACK/NAK
+    //
+    status = i2c_send_byte(address);
+    if ( status != AM_HAL_I2C_BIT_BANG_SUCCESS )
+    {
+        if ( status == AM_HAL_I2C_BIT_BANG_DATA_NAKED)
+        {
+            return AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED;
+        }
+        return status;
+    }
+
+    if ( bUseOffset )
+    {
+        status = i2c_send_byte(ui8Offset);
+        if ( status != AM_HAL_I2C_BIT_BANG_SUCCESS )
+        {
+            return status;
+        }
+    }
+
+    //
+    // receive the requested number of data bytes
+    //
+    for (ui32I = 0; ui32I < number_of_bytes - 1; ui32I++)
+    {
+        //
+        // receive the data bytes and send ACK for each one
+        //
+        status = i2c_receive_byte(pData, false);
+        if (status != AM_HAL_I2C_BIT_BANG_SUCCESS)
+        {
+            return status;
+        }
+        pData++;
+    }
+    // Send NAK for the last byte
+    status = i2c_receive_byte(pData, true);
+    if (status != AM_HAL_I2C_BIT_BANG_SUCCESS)
+    {
+        return status;
+    }
+
+    //********************
+    // Send stop condition
+    //********************
+    //
+    // Pull down on clock line
+    //
+    WRITE_SCL_LO();
+
+    //
+    // Delay for 1/4 bit cell time
+    //
+    WAIT_FOR_QUARTER_I2C_CLOCK();
+
+
+    if (!bNoStop)
+    {
+        //
+        // Pull down on data line with clock low
+        //
+        WRITE_SDA_LO();
+    }
+    else
+    {
+        //
+        // Release data line with clock low itself, as we are not sending STOP
+        //
+        PULL_SDA_HI();
+    }
+    //
+    //
+    // Delay for 1/4 bit cell time
+    //
+    WAIT_FOR_QUARTER_I2C_CLOCK();
+
+    if (i2c_pull_and_wait_scl_hi())
+    {
+        return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+    }
+    //
+    // Delay for 1/2 bit cell time while clock is high
+    //
+    WAIT_I2C_CLOCK_HI_PERIOD();
+
+    if (!bNoStop)
+    {
+        //
+        // release data line with clock high --> STOP CONDITION
+        //
+        PULL_SDA_HI();
+    }
+
+    //
+    // message successfully received (how could we fail???)
+    //
+    return AM_HAL_I2C_BIT_BANG_SUCCESS;
+}
+
+//*****************************************************************************
+//
+//! @brief Send a string of data bytes to an I2C device
+//!
+//! @param address (only 8 bit I2C addresses are supported)
+//!        LSB is I2C R/W
+//! @param number_of_bytes to transfer (# payload bytes)
+//! @param pData pointer to data buffer containing payload
+//!
+//! This function handles sending a payload to a slave device
+//!
+//! returns ENUM {AM_HAL_I2C_BIT_BANG_SUCCESS, AM_HAL_I2C_BIT_BANG_DATA_NAKED,
+//!               AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED}
+//
+//*****************************************************************************
+am_hal_i2c_bit_bang_enum_t
+am_hal_i2c_bit_bang_send(uint8_t address, uint32_t number_of_bytes,
+                         uint8_t *pData, uint8_t ui8Offset,
+                         bool bUseOffset, bool bNoStop)
+{
+    uint32_t ui32I;
+    am_hal_i2c_bit_bang_enum_t status;
+    bool data_naked = false;
+
+    if (i2c_pull_and_wait_scl_hi())
+    {
+        return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+    }
+    //
+    // Pull down on data line with clock high --> START CONDITION
+    //
+    WRITE_SDA_LO();
+
+    //
+    // Delay for 1/2 bit cell time to start the clock
+    //
+    WAIT_I2C_CLOCK_HI_PERIOD();
+
+    //
+    // send the address byte and wait for the ACK/NAK
+    //
+    status = i2c_send_byte(address);
+    if ( status != AM_HAL_I2C_BIT_BANG_SUCCESS )
+    {
+        if ( status == AM_HAL_I2C_BIT_BANG_DATA_NAKED)
+        {
+            return AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED;
+        }
+        return status;
+    }
+
+    if ( bUseOffset )
+    {
+        status = i2c_send_byte(ui8Offset);
+        if ( status != AM_HAL_I2C_BIT_BANG_SUCCESS )
+        {
+            return status;
+        }
+    }
+
+    //
+    // send the requested number of data bytes
+    //
+    for (ui32I = 0; ui32I < number_of_bytes; ui32I++)
+    {
+        //
+        // send out the data bytes while watching for premature NAK
+        //
+        status =  i2c_send_byte(*pData++);
+        if (status != AM_HAL_I2C_BIT_BANG_SUCCESS)
+        {
+            if (status == AM_HAL_I2C_BIT_BANG_DATA_NAKED)
+            {
+                if (ui32I != (number_of_bytes-1))
+                {
+                    data_naked = true;
+                    // TODO - should we be sending the STOP bit in this case regardless of bNoStop?
+                    break;
+                }
+                else
+                {
+                    status = AM_HAL_I2C_BIT_BANG_SUCCESS;
+                }
+            }
+            else
+            {
+                return status;
+            }
+        }
+    }
+
+    //********************
+    // Send stop condition
+    //********************
+
+    //
+    // Pull down on clock line
+    //
+    WRITE_SCL_LO();
+
+    //
+    // Delay for 1/4 bit cell time
+    //
+    WAIT_FOR_QUARTER_I2C_CLOCK();
+
+
+    if (!bNoStop)
+    {
+        //
+        // Pull down on data line with clock low
+        //
+        WRITE_SDA_LO();
+    }
+    else
+    {
+        //
+        // Release data line with clock low itself, as we are not sending STOP
+        //
+        PULL_SDA_HI();
+    }
+
+    //
+    // Delay for 1/4 bit cell time
+    //
+    WAIT_FOR_QUARTER_I2C_CLOCK();
+
+    if (i2c_pull_and_wait_scl_hi())
+    {
+        return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT;
+    }
+    if (!bNoStop)
+    {
+        //
+        // release data line with clock high --> STOP CONDITION
+        //
+        PULL_SDA_HI();
+    }
+
+    //
+    // Delay for 1/2 bit cell time while clock is high
+    //
+    WAIT_I2C_CLOCK_HI_PERIOD();
+
+    if ( data_naked )
+    {
+        return AM_HAL_I2C_BIT_BANG_DATA_NAKED;  // if it happens early
+    }
+
+    //
+    // message successfully sent
+    //
+    return AM_HAL_I2C_BIT_BANG_SUCCESS;
+}
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h
new file mode 100644
index 0000000000..a9571edbe5
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h
@@ -0,0 +1,100 @@
+//*****************************************************************************
+//
+//  am_hal_i2c_bit_bang.h
+//! @file
+//!
+//! @brief I2C bit bang module.
+//!
+//! These functions implement the I2C bit bang utility
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_I2C_BIT_BANG_H
+#define AM_HAL_I2C_BIT_BANG_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Enumerated return constants
+//
+//*****************************************************************************
+typedef enum
+{
+    AM_HAL_I2C_BIT_BANG_SUCCESS = 0,
+    AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED,
+    AM_HAL_I2C_BIT_BANG_DATA_NAKED,
+    AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT,
+    AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT,
+}am_hal_i2c_bit_bang_enum_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
+                                     uint32_t sda_gpio_number);
+
+extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_send(uint8_t address,
+                                                    uint32_t number_of_bytes,
+                                                    uint8_t *pData,
+                                                    uint8_t ui8Offset,
+                                                    bool bUseOffset,
+                                                    bool bNoStop);
+
+extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_receive(uint8_t address,
+                                                    uint32_t number_of_bytes,
+                                                    uint8_t *pData,
+                                                    uint8_t ui8Offset,
+                                                    bool bUseOffset,
+                                                    bool bNoStop);
+#ifdef __cplusplus
+}
+#endif
+
+#endif //AM_HAL_I2C_BIT_BANG_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c
new file mode 100644
index 0000000000..2f93b09cfc
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c
@@ -0,0 +1,407 @@
+//*****************************************************************************
+//
+//  am_hal_interrupt.c
+//! @file
+//!
+//! @brief Helper functions supporting interrupts and NVIC operation.
+//!
+//! These functions may be used for NVIC-level interrupt configuration.
+//!
+//! @addtogroup interrupt2 Interrupt (ARM NVIC support functions)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Enable an interrupt.
+//!
+//! @param ui32Interrupt The ISR number of the interrupt to be enabled.
+//!
+//! This function enables an interrupt signal to the NVIC based on the provided
+//! ISR number.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_interrupt_enable(uint32_t ui32Interrupt)
+{
+    //
+    // Check to see what type of interrupt this is.
+    //
+    if ( ui32Interrupt > 15 )
+    {
+        //
+        // If this ISR number corresponds to a "normal" peripheral interrupt,
+        // enable it using the NVIC register.
+        //
+        AM_REG(NVIC, ISER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
+    }
+    else
+    {
+        //
+        // If this is an ARM internal interrupt number, route it to the
+        // appropriate enable register.
+        //
+        switch(ui32Interrupt)
+        {
+            case AM_HAL_INTERRUPT_BUSFAULT:
+                AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 1);
+            break;
+
+            case AM_HAL_INTERRUPT_USAGEFAULT:
+                AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 1);
+            break;
+
+            case AM_HAL_INTERRUPT_MPUFAULT:
+                AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 1);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Disable an interrupt.
+//!
+//! @param ui32Interrupt The ISR number of the interrupt to be disabled.
+//!
+//! This function disables an interrupt signal to the NVIC based on the
+//! provided ISR number.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_interrupt_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Check to see what type of interrupt this is.
+    //
+    if ( ui32Interrupt > 15 )
+    {
+        //
+        // If this ISR number corresponds to a "normal" peripheral interrupt,
+        // disable it using the NVIC register.
+        //
+        AM_REG(NVIC, ICER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
+    }
+    else
+    {
+        //
+        // If this is an ARM internal interrupt number, route it to the
+        // appropriate enable register.
+        //
+        switch(ui32Interrupt)
+        {
+            case AM_HAL_INTERRUPT_BUSFAULT:
+                AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 0);
+            break;
+
+            case AM_HAL_INTERRUPT_USAGEFAULT:
+                AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 0);
+            break;
+
+            case AM_HAL_INTERRUPT_MPUFAULT:
+                AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Set the priority of an interrupt vector.
+//!
+//! @param ui32Interrupt is the ISR number of the interrupt to change.
+//! @param ui32Priority is the new ISR priority value.
+//!
+//! This function changes the priority value in the NVIC for the given
+//! interrupt vector number.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_interrupt_priority_set(uint32_t ui32Interrupt, uint32_t ui32Priority)
+{
+    volatile uint32_t *pui32PriorityReg;
+    volatile uint32_t ui32OldPriority;
+    uint32_t ui32Shift;
+
+    //
+    // Find the correct priority register.
+    //
+    pui32PriorityReg = (volatile uint32_t *) AM_REG_NVIC_IPR0_O;
+    pui32PriorityReg += ((ui32Interrupt - 16) >> 2);
+
+    //
+    // Find the correct shift value.
+    //
+    ui32Shift = (((ui32Interrupt - 16) & 0x3) * 8);
+
+    //
+    // Mask out the old priority.
+    //
+    ui32OldPriority = *pui32PriorityReg;
+    ui32OldPriority &= ~(0xFF << ui32Shift);
+
+    //
+    // OR in the new priority.
+    //
+    *pui32PriorityReg |= (ui32Priority << ui32Shift);
+}
+
+//*****************************************************************************
+//
+//! @brief Set a pending interrupt bit in the NVIC (Software Interrupt)
+//!
+//! @param ui32Interrupt is the ISR number of the interrupt to change.
+//!
+//! This function sets the specified bit in the Interrupt Set Pending (ISPR0)
+//! register. For future MCUs there may be more than one ISPR.
+//!
+//! @return None
+//
+//*****************************************************************************
+void am_hal_interrupt_pend_set(uint32_t ui32Interrupt)
+{
+    //
+    // Check to see if the specified interrupt is valid for this MCU
+    //
+    if ( ui32Interrupt > 47 )
+    {
+        return;
+    }
+
+    //
+    // Check to see what type of interrupt this is.
+    //
+    if ( ui32Interrupt > 15 )
+    {
+        //
+        // If this ISR number corresponds to a "normal" peripheral interrupt,
+        // disable it using the NVIC register.
+        //
+        AM_REG(NVIC, ISPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Clear a pending interrupt bit in the NVIC without servicing it
+//!
+//! @param ui32Interrupt is the ISR number of the interrupt to change.
+//!
+//! This function clears the specified bit in the Interrupt Clear Pending
+//! (ICPR0) register. For future MCUs there may be more than one ICPR. This
+//! function is useful immediately following a WFI before interrupts are
+//! re-enabled.
+//!
+//! @return None
+//
+//*****************************************************************************
+void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Check to see if the specified interrupt is valid for this MCU
+    //
+    if ( ui32Interrupt > 47 )
+    {
+        return;
+    }
+
+    //
+    // Check to see what type of interrupt this is.
+    //
+    if ( ui32Interrupt > 15 )
+    {
+        //
+        // If this ISR number corresponds to a "normal" peripheral interrupt,
+        // disable it using the NVIC register.
+        //
+        AM_REG(NVIC, ICPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Globally enable interrupt service routines
+//!
+//! This function allows interrupt signals from the NVIC to trigger ISR entry
+//! in the CPU. This function must be called if interrupts are to be serviced
+//! in software.
+//!
+//! @return 1 if interrupts were previously disabled, 0 otherwise.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+uint32_t __attribute__((naked))
+am_hal_interrupt_master_enable(void)
+{
+    __asm("    mrs     r0, PRIMASK");
+    __asm("    cpsie i");
+    __asm("    bx lr");
+}
+#elif defined(__ARMCC_VERSION)
+__asm uint32_t
+am_hal_interrupt_master_enable(void)
+{
+    mrs     r0, PRIMASK
+    cpsie   i
+    bx      lr
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma diag_suppress = Pe940   // Suppress IAR compiler warning about missing
+                                // return statement on a non-void function
+__stackless uint32_t
+am_hal_interrupt_master_enable(void)
+{
+    __asm("    mrs     r0, PRIMASK");
+    __asm("    cpsie i");
+    __asm("    bx lr");
+}
+#pragma diag_default = Pe940    // Restore IAR compiler warning
+#endif
+
+//*****************************************************************************
+//
+//! @brief Globally disable interrupt service routines
+//!
+//! This function prevents interrupt signals from the NVIC from triggering ISR
+//! entry in the CPU. This will effectively stop incoming interrupt sources
+//! from triggering their corresponding ISRs.
+//!
+//! @note Any external interrupt signal that occurs while the master interrupt
+//! disable is active will still reach the "pending" state in the NVIC, but it
+//! will not be allowed to reach the "active" state or trigger the
+//! corresponding ISR. Instead, these interrupts are essentially "queued" until
+//! the next time the master interrupt enable instruction is executed. At that
+//! time, the interrupt handlers will be executed in order of decreasing
+//! priority.
+//!
+//! @return 1 if interrupts were previously disabled, 0 otherwise.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+uint32_t __attribute__((naked))
+am_hal_interrupt_master_disable(void)
+{
+    __asm("    mrs     r0, PRIMASK");
+    __asm("    cpsid i");
+    __asm("    bx lr");
+}
+#elif defined(__ARMCC_VERSION)
+__asm uint32_t
+am_hal_interrupt_master_disable(void)
+{
+    mrs     r0, PRIMASK
+    cpsid   i
+    bx      lr
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma diag_suppress = Pe940   // Suppress IAR compiler warning about missing
+                                // return statement on a non-void function
+__stackless uint32_t
+am_hal_interrupt_master_disable(void)
+{
+    __asm("    mrs     r0, PRIMASK");
+    __asm("    cpsid i");
+    __asm("    bx lr");
+}
+#pragma diag_default = Pe940    // Restore IAR compiler warning
+#endif
+
+//*****************************************************************************
+//
+//! @brief Sets the master interrupt state based on the input.
+//!
+//! @param ui32InterruptState - Desired PRIMASK value.
+//!
+//! This function directly writes the PRIMASK register in the ARM core. A value
+//! of 1 will disable interrupts, while a value of zero will enable them.
+//!
+//! This function may be used along with am_hal_interrupt_master_disable() to
+//! implement a nesting critical section. To do this, call
+//! am_hal_interrupt_master_disable() to start the critical section, and save
+//! its return value. To complete the critical section, call
+//! am_hal_interrupt_master_set() using the saved return value as \e
+//! ui32InterruptState. This will safely restore PRIMASK to the value it
+//! contained just before the start of the critical section.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+void __attribute__((naked))
+am_hal_interrupt_master_set(uint32_t ui32InterruptState)
+{
+    __asm("    msr     PRIMASK, r0");
+    __asm("    bx lr");
+}
+#elif defined(__ARMCC_VERSION)
+__asm void
+am_hal_interrupt_master_set(uint32_t ui32InterruptState)
+{
+    msr     PRIMASK, r0
+    bx      lr
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma diag_suppress = Pe940   // Suppress IAR compiler warning about missing
+                                // return statement on a non-void function
+__stackless void
+am_hal_interrupt_master_set(uint32_t ui32InterruptState)
+{
+    __asm("    msr     PRIMASK, r0");
+    __asm("    bx lr");
+}
+#pragma diag_default = Pe940    // Restore IAR compiler warning
+#endif
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h
new file mode 100644
index 0000000000..a8523371eb
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h
@@ -0,0 +1,159 @@
+//*****************************************************************************
+//
+//  am_hal_interrupt.h
+//! @file
+//!
+//! @brief Helper functions supporting interrupts and NVIC operation.
+//!
+//! These functions may be used for NVIC-level interrupt configuration.
+//!
+//! @addtogroup interrupt2 Interrupt (ARM NVIC support functions)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_INTERRUPT_H
+#define AM_HAL_INTERRUPT_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+//*****************************************************************************
+//
+//! @name ISR number macros.
+//! @brief ISR macros.
+//!
+//! These macros are used for all ui32Interrupt arguments in this module.
+//! @{
+//
+//*****************************************************************************
+//
+// Hardware interrupts
+//
+#define AM_HAL_INTERRUPT_RESET              1
+#define AM_HAL_INTERRUPT_NMI                2
+#define AM_HAL_INTERRUPT_HARDFAULT          3
+#define AM_HAL_INTERRUPT_MPUFAULT           4
+#define AM_HAL_INTERRUPT_BUSFAULT           5
+#define AM_HAL_INTERRUPT_USAGEFAULT         6
+
+#define AM_HAL_INTERRUPT_SVCALL             11
+#define AM_HAL_INTERRUPT_DEBUGMON           12
+#define AM_HAL_INTERRUPT_PENDSV             14
+#define AM_HAL_INTERRUPT_SYSTICK            15
+
+//
+// Begin IRQs
+//
+#define AM_HAL_INTERRUPT_BROWNOUT           16
+#define AM_HAL_INTERRUPT_WATCHDOG           17
+#define AM_HAL_INTERRUPT_CLKGEN             18
+#define AM_HAL_INTERRUPT_VCOMP              19
+#define AM_HAL_INTERRUPT_IOSLAVE            20
+#define AM_HAL_INTERRUPT_IOSACC             21
+#define AM_HAL_INTERRUPT_IOMASTER0          22
+#define AM_HAL_INTERRUPT_IOMASTER1          23
+#define AM_HAL_INTERRUPT_IOMASTER2          24
+#define AM_HAL_INTERRUPT_IOMASTER3          25
+#define AM_HAL_INTERRUPT_IOMASTER4          26
+#define AM_HAL_INTERRUPT_IOMASTER5          27
+#define AM_HAL_INTERRUPT_GPIO               28
+#define AM_HAL_INTERRUPT_CTIMER             29
+#define AM_HAL_INTERRUPT_UART0              30
+#define AM_HAL_INTERRUPT_UART1              31
+#define AM_HAL_INTERRUPT_UART               (AM_HAL_INTERRUPT_UART0)
+#define AM_HAL_INTERRUPT_ADC                32
+#define AM_HAL_INTERRUPT_PDM                33
+#define AM_HAL_INTERRUPT_STIMER             34
+#define AM_HAL_INTERRUPT_STIMER_CMPR0       35
+#define AM_HAL_INTERRUPT_STIMER_CMPR1       36
+#define AM_HAL_INTERRUPT_STIMER_CMPR2       37
+#define AM_HAL_INTERRUPT_STIMER_CMPR3       38
+#define AM_HAL_INTERRUPT_STIMER_CMPR4       39
+#define AM_HAL_INTERRUPT_STIMER_CMPR5       40
+#define AM_HAL_INTERRUPT_STIMER_CMPR6       41
+#define AM_HAL_INTERRUPT_STIMER_CMPR7       42
+#define AM_HAL_INTERRUPT_FLASH              43
+
+#define AM_HAL_INTERRUPT_SOFTWARE0          44
+#define AM_HAL_INTERRUPT_SOFTWARE1          45
+#define AM_HAL_INTERRUPT_SOFTWARE2          46
+#define AM_HAL_INTERRUPT_SOFTWARE3          47
+//! @}
+
+//*****************************************************************************
+//
+//! @brief Interrupt priority
+//!
+//! This macro is made to be used with the \e am_hal_interrupt_priority_set()
+//! function. It converts a priority number to the format used by the ARM
+//! standard priority register, where only the top 3 bits are used.
+//!
+//! For example, AM_HAL_INTERRUPT_PRIORITY(1) yields a value of 0x20.
+//
+//*****************************************************************************
+#define AM_HAL_INTERRUPT_PRIORITY(n)        (((uint32_t)(n) & 0x7) << 5)
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_interrupt_enable(uint32_t ui32Interrupt);
+extern void am_hal_interrupt_disable(uint32_t ui32Interrupt);
+extern void am_hal_interrupt_pend_set(uint32_t ui32Interrupt);
+extern void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt);
+extern void am_hal_interrupt_priority_set(uint32_t ui32Interrupt,
+                                          uint32_t ui32Priority);
+extern uint32_t am_hal_interrupt_master_disable(void);
+extern uint32_t am_hal_interrupt_master_enable(void);
+extern void am_hal_interrupt_master_set(uint32_t ui32InterruptState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_INTERRUPT_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c
new file mode 100644
index 0000000000..8b85c32b6a
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c
@@ -0,0 +1,4426 @@
+//*****************************************************************************
+//
+//  am_hal_iom.c
+//! @file
+//!
+//! @brief Functions for interfacing with the IO Master module
+//!
+//! @addtogroup iom2 IO Master (SPI/I2C)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+#include "am_util_delay.h"
+
+#ifdef __IAR_SYSTEMS_ICC__
+#define AM_INSTR_CLZ(n)                     __CLZ(n)
+#else
+#define AM_INSTR_CLZ(n)                     __builtin_clz(n)
+#endif
+
+//! ASSERT(1) or Correct(0) invalid IOM R/W Thresholds.
+#ifndef AM_ASSERT_INVALID_THRESHOLD
+#define AM_ASSERT_INVALID_THRESHOLD    (1)
+#endif
+
+//*****************************************************************************
+//
+// Forcing optimizations
+//
+// These pragmas must be enabled if we intend to use the IOM4 workaround with a
+// delay higher than 18-bits in the first word.
+//
+//*****************************************************************************
+//#ifdef __IAR_SYSTEMS_ICC__
+//#pragma optimize=3 s
+//#endif
+//
+//#ifdef __ARMCC_VERSION
+//#pragma O3
+//#endif
+//
+//#ifdef __GNUC__
+//#pragma GCC optimize ("O3")
+//#endif
+
+//*****************************************************************************
+//
+// Forward declarations.
+//
+//*****************************************************************************
+static void iom_workaround_loop(uint32_t ui32PadRegVal,
+                                volatile uint32_t *pui32PadReg,
+                                bool bRising);
+static uint32_t
+internal_am_hal_iom_spi_cmd_construct(uint32_t ui32Operation,
+                                      uint32_t ui32ChipSelect,
+                                      uint32_t ui32NumBytes,
+                                      uint32_t ui32Options);
+
+//*****************************************************************************
+//
+// IOM Buffer states.
+//
+//*****************************************************************************
+#define BUFFER_IDLE                         0x0
+#define BUFFER_SENDING                      0x1
+#define BUFFER_RECEIVING                    0x2
+
+//*****************************************************************************
+//
+// Global state variables
+//
+//*****************************************************************************
+//
+// Save error status from ISR, particularly for use in I2C queue mode.
+//
+uint32_t g_iom_error_status = 0;
+
+//
+// Define a structure to map CE for IOM4 only.
+//
+typedef struct
+{
+  uint8_t       channel;        // CE channel for SPI
+  uint8_t       pad;            // GPIO Pad
+  uint8_t       funcsel;        // FNCSEL value
+} IOMPad_t;
+
+// Define the mapping between SPI CEn, Pads, and FNCSEL values for all IOMs.
+const IOMPad_t g_IOMPads[] =
+{
+    {0, 29, 6}, {0, 34, 6}, {1, 18, 4}, {1, 37, 5}, {2, 41, 6},
+    {3, 17, 4}, {3, 45, 4}, {4, 10, 6}, {4, 46, 6}, {5,  9, 4},
+    {5, 47, 6}, {6, 35, 4}, {7, 38, 6}
+};
+
+#define WORKAROUND_IOM          4
+#define WORKAROUND_IOM_MOSI_PIN 44
+#define WORKAROUND_IOM_MOSI_CFG AM_HAL_PIN_44_M4MOSI
+
+#define MAX_IOM_BITS            9
+#define IOM_OVERHEAD_FACTOR     2
+
+//*****************************************************************************
+//
+// Non-blocking buffer and buffer-management variables.
+//
+//*****************************************************************************
+typedef struct
+{
+    uint32_t ui32State;
+    uint32_t *pui32Data;
+    uint32_t ui32BytesLeft;
+    uint32_t ui32Options;
+    void (*pfnCallback)(void);
+}
+am_hal_iom_nb_buffer;
+
+//
+// Global State to keep track if there is an ongoing transaction
+//
+volatile bool g_bIomBusy[AM_REG_IOMSTR_NUM_MODULES] = {0};
+
+am_hal_iom_nb_buffer g_psIOMBuffers[AM_REG_IOMSTR_NUM_MODULES];
+
+//*****************************************************************************
+//
+// Computed timeout.
+//
+// The IOM may not always respond to events (e.g., CMDCMP).  This is a
+// timeout value in cycles to be used when waiting on status changes.
+//*****************************************************************************
+uint32_t ui32StatusTimeout[AM_REG_IOMSTR_NUM_MODULES];
+
+//*****************************************************************************
+//
+// Queue management variables.
+//
+//*****************************************************************************
+am_hal_queue_t g_psIOMQueue[AM_REG_IOMSTR_NUM_MODULES];
+
+//*****************************************************************************
+//
+// Default queue flush function
+//
+//*****************************************************************************
+am_hal_iom_queue_flush_t am_hal_iom_queue_flush = am_hal_iom_sleeping_queue_flush;
+
+//*****************************************************************************
+//
+// Power management structure.
+//
+//*****************************************************************************
+am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES];
+
+
+//*****************************************************************************
+//
+// Static helper functions
+//
+//*****************************************************************************
+
+//*****************************************************************************
+// onebit()
+//*****************************************************************************
+//
+// A power of 2?
+// Return true if ui32Value has exactly 1 bit set, otherwise false.
+//
+static bool onebit(uint32_t ui32Value)
+{
+    return ui32Value  &&  !(ui32Value & (ui32Value - 1));
+}
+
+//*****************************************************************************
+// compute_freq()
+//*****************************************************************************
+//
+// Compute the interface frequency based on the given parameters
+//
+static uint32_t compute_freq(uint32_t ui32HFRCfreqHz,
+                             uint32_t ui32Fsel, uint32_t ui32Div3,
+                             uint32_t ui32DivEn, uint32_t ui32TotPer)
+{
+    uint32_t ui32Denomfinal, ui32ClkFreq;
+
+    ui32Denomfinal = ((1 << (ui32Fsel - 1)) * (1 + ui32Div3 * 2) * (1 + ui32DivEn * (ui32TotPer)));
+    ui32ClkFreq = (ui32HFRCfreqHz) / ui32Denomfinal;                           // Compute the set frequency value
+    ui32ClkFreq +=  (((ui32HFRCfreqHz) % ui32Denomfinal) > (ui32Denomfinal / 2)) ? 1 : 0;
+
+    return ui32ClkFreq;
+}
+
+//*****************************************************************************
+// iom_calc_gpio()
+//
+// Calculate the IOM4 GPIO to assert.
+//
+//*****************************************************************************
+static uint32_t iom_calc_gpio(uint32_t ui32ChipSelect)
+{
+    uint32_t      index;
+    uint8_t       ui8PadRegVal, ui8FncSelVal;
+
+    //
+    // Figure out which GPIO we are using for the IOM
+    //
+    for ( index = 0; index < (sizeof(g_IOMPads) / sizeof(IOMPad_t)); index++ )
+    {
+        //
+        //  Is this one of the CEn that we are using?
+        //
+        if ( g_IOMPads[index].channel == ui32ChipSelect )
+        {
+            //
+            // Get the PAD register value
+            //
+            ui8PadRegVal = ((AM_REGVAL(AM_HAL_GPIO_PADREG(g_IOMPads[index].pad))) &
+                             AM_HAL_GPIO_PADREG_M(g_IOMPads[index].pad)) >>
+                             AM_HAL_GPIO_PADREG_S(g_IOMPads[index].pad);
+
+            //
+            // Get the FNCSEL field value
+            //
+            ui8FncSelVal = (ui8PadRegVal & 0x38) >> 3;
+
+            //
+            // Is the FNCSEL filed for this pad set to the expected value?
+            //
+            if ( ui8FncSelVal == g_IOMPads[index].funcsel )
+            {
+                // This is the GPIO we need to use.
+                return g_IOMPads[index].pad;
+            }
+        }
+    }
+    return 0xDEADBEEF;
+}
+
+//*****************************************************************************
+//
+// Checks to see if this processor is a Rev B0 device.
+//
+// This is needed for the B0 IOM workaround.
+//
+//*****************************************************************************
+bool
+isRevB0(void)
+{
+    //
+    // Check to make sure the major rev is B and the minor rev is zero.
+    //
+    if ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B )
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Returns the proper settings for the CLKCFG register.
+//!
+//! @param ui32FreqHz - The desired interface frequency in Hz.
+//!        ui32Phase  - SPI phase (0 or 1).  Can affect duty cycle.
+//!
+//! Given a desired serial interface clock frequency, this function computes
+//! the appropriate settings for the various fields in the CLKCFG register
+//! and returns the 32-bit value that should be written to that register.
+//! The actual interface frequency may be slightly lower than the specified
+//! frequency, but the actual frequency is also returned.
+//!
+//! @note A couple of criteria that this algorithm follow are:
+//!  1. For power savings, choose the highest FSEL possible.
+//!  2. For best duty cycle, use DIV3 when possible rather than DIVEN.
+//!
+//! An example of #1 is that both of the following CLKCFGs would result
+//! in a frequency of 428,571 Hz:  0x0E071400 and 0x1C0E1300.
+//! The former is chosen by the algorithm because it results in FSEL=4
+//! while the latter is FSEL=3.
+//!
+//! An example of #2 is that both of the following CLKCFGs would result
+//! in a frequency of 2,000,000 Hz:  0x02011400 and 0x00000C00.
+//! The latter is chosen by the algorithm because it results in use of DIV3
+//! rather than DIVEN.
+//!
+//! @return An unsigned 64-bit value.
+//! The lower 32-bits represent the value to use to set CLKCFG.
+//! The upper 32-bits represent the actual frequency (in Hz) that will result
+//! from setting CLKCFG with the lower 32-bits.
+//!
+//! 0 (64 bits) = error. Note that the caller must check the entire 64 bits.
+//! It is not an error if only the low 32-bits are 0 (this is a valid value).
+//! But the entire 64 bits returning 0 is an error.
+//!
+//*****************************************************************************
+
+static
+uint64_t iom_get_interface_clock_cfg(uint32_t ui32FreqHz, uint32_t ui32Phase )
+{
+    uint32_t ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer, ui32LowPer;
+    uint32_t ui32Denom, ui32v1, ui32Denomfinal, ui32ClkFreq, ui32ClkCfg;
+    uint32_t ui32HFRCfreqHz;
+    int32_t i32Div, i32N;
+
+    if ( ui32FreqHz == 0 )
+    {
+        return 0;
+    }
+
+    //
+    // Set the HFRC clock frequency.
+    //
+    ui32HFRCfreqHz = AM_HAL_CLKGEN_FREQ_MAX_HZ;
+
+    //
+    // Compute various parameters used for computing the optimal CLKCFG setting.
+    //
+    i32Div = (ui32HFRCfreqHz / ui32FreqHz) + ((ui32HFRCfreqHz % ui32FreqHz) ? 1 : 0);    // Round up (ceiling)
+
+    //
+    // Compute N (count the number of LS zeros of Div) = ctz(Div) = log2(Div & (-Div))
+    //
+    i32N = 31 - AM_INSTR_CLZ((i32Div & (-i32Div)));
+
+    if ( i32N > 6 )
+    {
+        i32N = 6;
+    }
+
+    ui32Div3 = ( (ui32FreqHz < (ui32HFRCfreqHz / 16384))            ||
+                 ( ((ui32FreqHz >= (ui32HFRCfreqHz / 3))    &&
+                    (ui32FreqHz <= ((ui32HFRCfreqHz / 2) - 1)) ) ) ) ? 1 : 0;
+    ui32Denom = ( 1 << i32N ) * ( 1 + (ui32Div3 * 2) );
+    ui32TotPer = i32Div / ui32Denom;
+    ui32TotPer += (i32Div % ui32Denom) ? 1 : 0;
+    ui32v1 = 31 - AM_INSTR_CLZ(ui32TotPer);     // v1 = log2(TotPer)
+    ui32Fsel = (ui32v1 > 7) ? ui32v1 + i32N - 7 : i32N;
+    ui32Fsel++;
+
+    if ( ui32Fsel > 7 )
+    {
+        //
+        // This is an error, can't go that low.
+        //
+        return 0;
+    }
+
+    if ( ui32v1 > 7 )
+    {
+        ui32DivEn = ui32TotPer;     // Save TotPer for the round up calculation
+        ui32TotPer = ui32TotPer>>(ui32v1-7);
+        ui32TotPer += ((ui32DivEn) % (1 << (ui32v1 - 7))) ? 1 : 0;
+    }
+
+    ui32DivEn = ( (ui32FreqHz >= (ui32HFRCfreqHz / 4)) ||
+                  ((1 << (ui32Fsel - 1)) == i32Div) ) ? 0 : 1;
+
+    if (ui32Phase == 1)
+    {
+        ui32LowPer = (ui32TotPer - 2) / 2;          // Longer high phase
+    }
+    else
+    {
+        ui32LowPer = (ui32TotPer - 1) / 2;          // Longer low phase
+    }
+
+    ui32ClkCfg = AM_REG_IOMSTR_CLKCFG_FSEL(ui32Fsel)                |
+                 AM_REG_IOMSTR_CLKCFG_DIV3(ui32Div3)                |
+                 AM_REG_IOMSTR_CLKCFG_DIVEN(ui32DivEn)              |
+                 AM_REG_IOMSTR_CLKCFG_LOWPER(ui32LowPer)            |
+                 AM_REG_IOMSTR_CLKCFG_TOTPER(ui32TotPer - 1);
+
+
+    //
+    // Now, compute the actual frequency, which will be returned.
+    //
+    ui32ClkFreq = compute_freq(ui32HFRCfreqHz, ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer - 1);
+
+    //
+    // Determine if the actual frequency is a power of 2 (MHz).
+    //
+    if ( (ui32ClkFreq % 250000) == 0 )
+    {
+        //
+        // If the actual clock frequency is a power of 2 ranging from 250KHz up,
+        // we can simplify the CLKCFG value using DIV3 (which also results in a
+        // better duty cycle).
+        //
+        ui32Denomfinal = ui32ClkFreq / (uint32_t)250000;
+
+        if ( onebit(ui32Denomfinal) )
+        {
+            //
+            // These configurations can be simplified by using DIV3.  Configs
+            // using DIV3 have a 50% duty cycle, while those from DIVEN will
+            // have a 66/33 duty cycle.
+            //
+            ui32TotPer = ui32LowPer = ui32DivEn = 0;
+            ui32Div3 = 1;
+
+            //
+            // Now, compute the return values.
+            //
+            ui32ClkFreq = compute_freq(ui32HFRCfreqHz, ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer);
+
+            ui32ClkCfg = AM_REG_IOMSTR_CLKCFG_FSEL(ui32Fsel)    |
+                         AM_REG_IOMSTR_CLKCFG_DIV3(1)           |
+                         AM_REG_IOMSTR_CLKCFG_DIVEN(0)          |
+                         AM_REG_IOMSTR_CLKCFG_LOWPER(0)         |
+                         AM_REG_IOMSTR_CLKCFG_TOTPER(0);
+        }
+    }
+
+    return ( ((uint64_t)ui32ClkFreq) << 32) | (uint64_t)ui32ClkCfg;
+
+} //iom_get_interface_clock_cfg()
+
+
+//*****************************************************************************
+//
+//! @brief Enable the IOM in the power control block.
+//!
+//! This function enables the desigated IOM module in the power control block.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_pwrctrl_enable(uint32_t ui32Module)
+{
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to enable an IOM module that doesn't exist.");
+
+    am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_IOM0 << ui32Module);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the IOM in the power control block.
+//!
+//! This function disables the desigated IOM module in the power control block.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_pwrctrl_disable(uint32_t ui32Module)
+{
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to disable an IOM module that doesn't exist.");
+
+    am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_IOM0 << ui32Module);
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the IOM module
+//!
+//! @param ui32Module - The number of the IOM module to be enabled.
+//!
+//! This function enables the IOM module using the IFCEN bitfield in the
+//! IOMSTR_CFG register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_enable(uint32_t ui32Module)
+{
+    if ( ui32Module < AM_REG_IOMSTR_NUM_MODULES )
+    {
+        AM_REGn(IOMSTR, ui32Module, CFG) |= AM_REG_IOMSTR_CFG_IFCEN(1);
+        g_bIomBusy[ui32Module] = false;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the IOM module.
+//!
+//! @param ui32Module - The number of the IOM module to be disabled.
+//!
+//! This function disables the IOM module using the IFCEN bitfield in the
+//! IOMSTR_CFG register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_disable(uint32_t ui32Module)
+{
+    if ( ui32Module < AM_REG_IOMSTR_NUM_MODULES )
+    {
+        //
+        // Wait until the bus is idle.
+        //
+        am_hal_iom_poll_complete(ui32Module);
+
+        //
+        // Disable the interface.
+        //
+        AM_REGn(IOMSTR, ui32Module, CFG) &= ~(AM_REG_IOMSTR_CFG_IFCEN(1));
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Enable power to the selected IOM module.
+//!
+//! @param ui32Module - Module number for the IOM to be turned on.
+//!
+//! This function enables the power gate to the selected IOM module. It is
+//! intended to be used along with am_hal_iom_power_off_save(). Used together,
+//! these functions allow the caller to power IOM modules off to save
+//! additional power without losing important configuration information.
+//!
+//! The am_hal_iom_power_off_save() function will save IOM configuration
+//! register information to SRAM before powering off the selected IOM module.
+//! This function will re-enable the IOM module, and restore those
+//! configuration settings from SRAM.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_power_on_restore(uint32_t ui32Module)
+{
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to enable an IOM module that doesn't exist.");
+
+    //
+    // Make sure this restore is a companion to a previous save call.
+    //
+    if ( am_hal_iom_pwrsave[ui32Module].bValid == 0 )
+    {
+        return;
+    }
+
+    //
+    // Enable power to the selected IOM.
+    //
+    am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_IOM0 << ui32Module);
+
+    //
+    // Restore the IOM configuration registers from the structure in SRAM.
+    //
+    AM_REGn(IOMSTR, ui32Module, FIFOTHR) = am_hal_iom_pwrsave[ui32Module].FIFOTHR;
+    AM_REGn(IOMSTR, ui32Module, CLKCFG) = am_hal_iom_pwrsave[ui32Module].CLKCFG;
+    AM_REGn(IOMSTR, ui32Module, CFG) = am_hal_iom_pwrsave[ui32Module].CFG;
+    AM_REGn(IOMSTR, ui32Module, INTEN) = am_hal_iom_pwrsave[ui32Module].INTEN;
+
+    //
+    // Indicates we have restored the configuration.
+    //
+    am_hal_iom_pwrsave[ui32Module].bValid = 0;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable power to the selected IOM module.
+//!
+//! @param ui32Module - Module number for the IOM to be turned off.
+//!
+//! This function disables the power gate to the selected IOM module. It is
+//! intended to be used along with am_hal_iom_power_on_restore(). Used together,
+//! these functions allow the caller to power IOM modules off to save
+//! additional power without losing important configuration information.
+//!
+//! The am_hal_iom_power_off_save() function will save IOM configuration
+//! register information to SRAM before powering off the selected IOM module.
+//! The am_hal_iom_power_on_restore() function will re-enable the IOM module
+//! and restore those configuration settings from SRAM.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_power_off_save(uint32_t ui32Module)
+{
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to disable an IOM module that doesn't exist.");
+
+    //
+    // Save the IOM configuration registers to the structure in SRAM.
+    //
+    am_hal_iom_pwrsave[ui32Module].FIFOTHR = AM_REGn(IOMSTR, ui32Module, FIFOTHR);
+    am_hal_iom_pwrsave[ui32Module].CLKCFG = AM_REGn(IOMSTR, ui32Module, CLKCFG);
+    am_hal_iom_pwrsave[ui32Module].CFG = AM_REGn(IOMSTR, ui32Module, CFG);
+    am_hal_iom_pwrsave[ui32Module].INTEN = AM_REGn(IOMSTR, ui32Module, INTEN);
+
+    //
+    // Indicates we have a valid saved configuration.
+    //
+    am_hal_iom_pwrsave[ui32Module].bValid = 1;
+
+    //
+    // Disable power to the selected IOM.
+    //
+    am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_IOM0 << ui32Module);
+}
+
+//
+//! Check and correct the IOM FIFO threshold.
+//
+#define MAX_RW_THRESHOLD    (AM_HAL_IOM_MAX_FIFO_SIZE - 4)
+#define MIN_RW_THRESHOLD    (4)
+#if (AM_ASSERT_INVALID_THRESHOLD == 0)
+static uint8_t check_iom_threshold(const uint8_t iom_threshold)
+{
+    uint8_t corrected_threshold = iom_threshold;
+
+    if ( corrected_threshold < MIN_RW_THRESHOLD )
+    {
+        corrected_threshold = MIN_RW_THRESHOLD;
+    }
+
+    if ( corrected_threshold > MAX_RW_THRESHOLD )
+    {
+        corrected_threshold = MAX_RW_THRESHOLD;
+    }
+
+    return corrected_threshold;
+}
+#endif
+
+//*****************************************************************************
+//
+//! @brief Sets module-wide configuration options for the IOM module.
+//!
+//! @param ui32Module - The instance number for the module to be configured
+//! (zero or one)
+//!
+//! @param psConfig - Pointer to an IOM configuration structure.
+//!
+//! This function is used to set the interface mode (SPI or I2C), clock
+//! frequency, SPI format (when relevant), and FIFO read/write interrupt
+//! thresholds for the IO master. For more information on specific
+//! configuration options, please see the documentation for the configuration
+//! structure.
+//!
+//! @note The IOM module should be disabled before configuring or
+//! re-configuring. This function will not re-enable the module when it
+//! completes. Call the am_hal_iom_enable function when the module is
+//! configured and ready to use.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_config(uint32_t ui32Module, const am_hal_iom_config_t *psConfig)
+{
+    uint32_t ui32Config, ui32ClkCfg;
+
+    //
+    // Start by checking the interface mode (I2C or SPI), and writing it to the
+    // configuration word.
+    //
+    ui32Config = psConfig->ui32InterfaceMode;
+
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    //
+    // Check the SPI format, and OR in the bits for SPHA (clock phase) and SPOL
+    // (polarity). These shouldn't have any effect in I2C mode, so it should be
+    // ok to write them without checking exactly which mode we're in.
+    //
+    if ( psConfig->bSPHA )
+    {
+        ui32Config |= AM_REG_IOMSTR_CFG_SPHA(1);
+    }
+
+    if ( psConfig->bSPOL )
+    {
+        ui32Config |= AM_REG_IOMSTR_CFG_SPOL(1);
+    }
+
+    // Set the STARTRD based on the interface speed
+    // For all I2C frequencies and SPI frequencies below 16 MHz, the STARTRD
+    // field should be set to 0 to minimize the potential of the IO transfer
+    // holding off a bus access to the FIFO. For SPI frequencies of 16 MHz
+    // or 24 MHz, the STARTRD field must be set to a value of 2 to insure
+    // enough time for the IO preread.
+    if ( psConfig->ui32ClockFrequency >= 16000000UL)
+    {
+        ui32Config |= AM_REG_IOMSTR_CFG_STARTRD(2);
+    }
+
+    //
+    // Write the resulting configuration word to the IO master CFG register for
+    // the module number we were provided.
+    //
+    AM_REGn(IOMSTR, ui32Module, CFG) = ui32Config;
+
+    //
+    // Write the FIFO write and read thresholds to the appropriate registers.
+    //
+#if     (AM_ASSERT_INVALID_THRESHOLD == 1)
+    am_hal_debug_assert_msg(
+        (psConfig->ui8WriteThreshold <= MAX_RW_THRESHOLD), "IOM write threshold too big.");
+    am_hal_debug_assert_msg(
+        (psConfig->ui8ReadThreshold <= MAX_RW_THRESHOLD), "IOM read threshold too big.");
+    am_hal_debug_assert_msg(
+        (psConfig->ui8WriteThreshold >= MIN_RW_THRESHOLD), "IOM write threshold too small.");
+    am_hal_debug_assert_msg(
+        (psConfig->ui8ReadThreshold >= MIN_RW_THRESHOLD), "IOM read threshold too small.");
+
+    AM_REGn(IOMSTR, ui32Module, FIFOTHR) =
+        (AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(psConfig->ui8WriteThreshold) |
+         AM_REG_IOMSTR_FIFOTHR_FIFORTHR(psConfig->ui8ReadThreshold));
+#elif   (AM_ASSERT_INVALID_THRESHOLD == 0)
+    AM_REGn(IOMSTR, ui32Module, FIFOTHR) =
+        (AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(check_iom_threshold(psConfig->ui8WriteThreshold)) |
+         AM_REG_IOMSTR_FIFOTHR_FIFORTHR(check_iom_threshold(psConfig->ui8ReadThreshold)));
+#else
+#error AM_ASSERT_INVALID_THRESHOLD must be 0 or 1.
+#endif
+
+    //
+    // An exception occurs in the LOWPER computation when setting an interface
+    //  frequency (such as a divide by 5 frequency) which results in a 60/40
+    //  duty cycle.  The 60% cycle must occur in the appropriate half-period,
+    //  as only one of the half-periods is active, depending on which phase
+    //  is being selected.
+    // If SPHA=0 the low period must be 60%. If SPHA=1 high period must be 60%.
+    // Note that the predetermined frequency parameters use the formula
+    //  lowper = (totper-1)/2, which results in a 60% low period.
+    //
+    ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFrequency,
+                                             psConfig->bSPHA );
+    if ( ui32ClkCfg )
+    {
+        AM_REGn(IOMSTR, ui32Module, CLKCFG) = (uint32_t)ui32ClkCfg;
+    }
+    
+    //
+    // Compute the status timeout value.
+    //
+    ui32StatusTimeout[ui32Module] = MAX_IOM_BITS * AM_HAL_IOM_MAX_FIFO_SIZE * 
+      IOM_OVERHEAD_FACTOR * (am_hal_clkgen_sysclk_get() / psConfig->ui32ClockFrequency);
+}
+
+//*****************************************************************************
+//
+//! @brief Returns the actual currently configured interface frequency in Hz.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_frequency_get(uint32_t ui32ClkCfg)
+{
+    uint32_t ui32Freq;
+
+    ui32Freq = compute_freq(AM_HAL_CLKGEN_FREQ_MAX_HZ,
+    (ui32ClkCfg & AM_REG_IOMSTR_CLKCFG_FSEL_M)  >> AM_REG_IOMSTR_CLKCFG_FSEL_S,
+    (ui32ClkCfg & AM_REG_IOMSTR_CLKCFG_DIV3_M)  >> AM_REG_IOMSTR_CLKCFG_DIV3_S,
+    (ui32ClkCfg & AM_REG_IOMSTR_CLKCFG_DIVEN_M) >> AM_REG_IOMSTR_CLKCFG_DIVEN_S,
+    (ui32ClkCfg & AM_REG_IOMSTR_CLKCFG_TOTPER_M)>> AM_REG_IOMSTR_CLKCFG_TOTPER_S);
+
+    return ui32Freq;
+}
+
+//*****************************************************************************
+//
+// Helper function for the B0 workaround.
+//
+//*****************************************************************************
+static uint32_t
+iom_get_workaround_fsel(uint32_t maxFreq)
+{
+    uint32_t ui32Freq, ui32Fsel;
+    uint32_t ui32ClkCfg = AM_REGn(IOMSTR, 4, CLKCFG);
+
+    //
+    // Starting with the current clock configuration parameters, find a value
+    // of FSEL that will bring our total frequency down to or below maxFreq.
+    //
+    for ( ui32Fsel = 1; ui32Fsel < 8; ui32Fsel++ )
+    {
+        ui32Freq = compute_freq(AM_HAL_CLKGEN_FREQ_MAX_HZ, ui32Fsel,
+                                AM_BFX(IOMSTR, CLKCFG, DIV3, ui32ClkCfg),
+                                AM_BFX(IOMSTR, CLKCFG, DIVEN, ui32ClkCfg),
+                                AM_BFX(IOMSTR, CLKCFG, TOTPER, ui32ClkCfg));
+
+        if ( ui32Freq <= maxFreq && ui32Freq != 0 )
+        {
+            //
+            // Return the new FSEL
+            //
+            return ui32Fsel;
+        }
+    }
+
+    //
+    // Couldn't find an appropriate frequency. This should be impossible
+    // because there should always be a value of FSEL that brings the final IOM
+    // frequency below 500 KHz.
+    //
+    am_hal_debug_assert_msg(false, "Could find a valid frequency.  Should never get here.");
+    return maxFreq;
+}
+
+// Separating this piece of code in separate function to keep the impact of
+// rest of the code to mimimal because of stack usage
+static void
+internal_iom_workaround_critical(uint32_t ui32Command,
+                                 volatile uint32_t *pui32CSPadreg,
+                                 uint32_t ui32CSPadregVal,
+                                 uint32_t ui32DelayTime,
+                                 uint32_t ui32ClkCfg,
+                                 uint32_t ui32LowClkCfg,
+                                 bool bRising)
+{
+    uint32_t ui32Critical = 0;
+    //
+    // Start a critical section.
+    //
+    ui32Critical = am_hal_interrupt_master_disable();
+
+    //
+    // Start the write on the bus.
+    //
+    AM_REGn(IOMSTR, WORKAROUND_IOM, CMD) = ui32Command;
+
+    //
+    // Slow down the clock, and run the workaround loop. The workaround
+    // loop runs an edge-detector on MOSI, and triggers a falling edge on
+    // chip-enable on the first bit of our real data.
+    //
+    ((void (*)(uint32_t)) 0x0800009d)(ui32DelayTime);
+    // Switch to Low Freq
+    AM_REGn(IOMSTR, WORKAROUND_IOM, CLKCFG) = ui32LowClkCfg;
+    iom_workaround_loop(ui32CSPadregVal, pui32CSPadreg, bRising);
+    //
+    // Restore the clock frequency and the normal MOSI pin function.
+    //
+    AM_REGn(IOMSTR, WORKAROUND_IOM, CLKCFG) = ui32ClkCfg;
+    am_hal_gpio_pin_config(WORKAROUND_IOM_MOSI_PIN, WORKAROUND_IOM_MOSI_CFG);
+
+    //
+    // End the critical section.
+    //
+    am_hal_interrupt_master_set(ui32Critical);
+}
+
+
+//*****************************************************************************
+//
+//! @brief Workaround for an Apollo2 Rev B0 issue.
+//!
+//! @param ui32ChipSelect - Chip-select number for this transaction.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional SPI transfer options.
+//!
+//! Some Apollo2 Rev B0 devices have an issue where the first byte of a SPI
+//! write transaction can have some of its bits changed from ones to zeroes. In
+//! order to get around this issue, we artificially pad the SPI write data with
+//! additional bytes, and manually control the CS pin for the beginning of the
+//! SPI frame so that the receiving device will ignore the bytes of padding
+//! that we added.
+//!
+//! This function acts as a helper function to higher-level spi APIs. It
+//! performs the functions of am_hal_iom_fifo_write() and
+//! am_hal_iom_spi_cmd_run() to get a SPI write started on the bus, including
+//! all of the necessary workaround behavior.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_workaround_word_write(uint32_t ui32ChipSelect,
+                                 uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                 uint32_t ui32Options)
+{
+    uint32_t ui32TransferSize;
+    uint32_t ui32IOMGPIO = 0xDEADBEEF;
+    volatile uint32_t *pui32CSPadreg = 0;
+    uint32_t ui32CSPadregVal = 0;
+    uint32_t ui32ClkCfg = 0;
+    uint32_t ui32HiClkCfg, ui32LowClkCfg;
+    bool bRising = 0;
+    uint32_t ui32HiFreq = 0, ui32NormalFreq = 0;
+    uint32_t ui32DelayTime = 0;
+    uint32_t ui32LowFsel = 0;
+    uint32_t ui32HiFsel = 0;
+    uint32_t ui32FirstWord = 0;
+    uint32_t ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, WORKAROUND_IOM, CFG, FULLDUP)) ?
+                               AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2);
+    uint32_t ui32Command;
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    // Note: This is a little shorter than usual, since the workaround
+    // consumes an extra byte at the beginning of the transfer.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes <= 4091, "SPI transfer too big.");
+
+    //
+    // Create a "dummy" word to add on to the beginning of the transfer
+    // that will guarantee a transition between the first word and the
+    // second on the bus.
+    //
+    // For raw transactions, this is straightforward. For transactions
+    // preceded by an offset, we'll add the offset in to the "dummy" word
+    // to preserve data alignment later.
+    //
+    // The workaround uses a critical section for precision
+    // To minimize the time in critical section, we raise the SPI frequency
+    // to the max possible for the initial preamble to be clocked out
+    // then we switch to a 'reasonably' slow frequency to be able to reliably
+    // catch the rising or falling edge by polling. Then we switch back to
+    // configured frequency
+    //
+
+    // We want to slow down the clock to help us count edges more
+    // accurately. Save it first, then slow it down. Also, we will
+    // pre-calculate a delay for when we need to restore the SPI settings.
+    //
+    ui32ClkCfg = AM_REGn(IOMSTR, WORKAROUND_IOM, CLKCFG);
+    // Get the largest speed we can configure within our rated speed of 16MHz
+    ui32HiFsel = iom_get_workaround_fsel(16000000);
+    ui32HiClkCfg = ((ui32ClkCfg & (~AM_REG_IOMSTR_CLKCFG_FSEL_M)) |
+                     AM_BFV(IOMSTR, CLKCFG, FSEL, ui32HiFsel));
+    // Switch to Hi Freq
+    // Need to make sure we wait long enough for the hi clock to be effective
+    // Delay 2 cycles based on previous frequency
+    ui32NormalFreq = am_hal_iom_frequency_get(ui32ClkCfg);
+    AM_REGn(IOMSTR, WORKAROUND_IOM, CLKCFG) = ui32HiClkCfg;
+    ui32DelayTime = ((2 * AM_HAL_CLKGEN_FREQ_MAX_HZ) / (ui32NormalFreq * 3));
+    ((void (*)(uint32_t)) 0x0800009d)(ui32DelayTime);
+    //
+    // Remember what frequency we'll be running at.during Hi Phase
+    //
+    ui32HiFreq = am_hal_iom_frequency_get(ui32HiClkCfg);
+
+    //
+    // Validate return value to prevent DIVBY0 errors.
+    //
+    am_hal_debug_assert_msg(ui32HiFreq > 0, "Invalid Hi Frequency for IOM.");
+
+    // Get a reasonably slow speed (~1MHz) we can safely poll for the transition
+    ui32LowFsel = iom_get_workaround_fsel(1000000);
+    ui32LowClkCfg = ((ui32ClkCfg & (~AM_REG_IOMSTR_CLKCFG_FSEL_M)) |
+                     AM_BFV(IOMSTR, CLKCFG, FSEL, ui32LowFsel));
+
+    if ( ui32Options & AM_HAL_IOM_RAW )
+    {
+        //
+        // The transition we care for is on 33rd bit.
+        // Prepare to delay 27 bits past the start of the transaction
+        // before getting into polling - to leave some
+        // margin for compiler related variations
+        //
+        ui32DelayTime = ((27 * AM_HAL_CLKGEN_FREQ_MAX_HZ) / (ui32HiFreq * 3));
+
+        if ( pui32Data[0] & 0x80 )
+        {
+            ui32FirstWord = 0x00000000;
+            bRising = true;
+        }
+        else
+        {
+            ui32FirstWord = 0xFFFFFF00;
+            bRising = false;
+        }
+    }
+    else
+    {
+        //
+        // The transition we care for is on 25th bit.
+        // Prepare to delay 19 bits past the start of the transaction
+        // before getting into polling - to leave some
+        // margin for compiler related variations
+        //
+        ui32DelayTime = ((19 * AM_HAL_CLKGEN_FREQ_MAX_HZ) / (ui32HiFreq * 3));
+        ui32FirstWord = ((ui32Options & 0xFF00) << 16);
+        if ( ui32FirstWord & 0x80000000 )
+        {
+            bRising = true;
+        }
+        else
+        {
+            ui32FirstWord |= 0x00FFFF00;
+            bRising = false;
+        }
+    }
+
+    //
+    // Now that weve taken care of the offset byte, we can run the
+    // transaction in RAW mode.
+    //
+    ui32Options |= AM_HAL_IOM_RAW;
+
+    ui32NumBytes += 4;
+
+    //
+    // Figure out how many bytes we can write to the FIFO immediately.
+    //
+    ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes :
+                        ui32MaxFifoSize);
+
+    am_hal_iom_fifo_write(WORKAROUND_IOM, &ui32FirstWord, 4);
+
+    am_hal_iom_fifo_write(WORKAROUND_IOM, pui32Data, ui32TransferSize - 4);
+
+    //
+    // Calculate the GPIO to be controlled until the initial shift is
+    // complete. Make sure we get a valid value.
+    //
+    ui32IOMGPIO = iom_calc_gpio(ui32ChipSelect);
+    am_hal_debug_assert(0xDEADBEEF != ui32IOMGPIO);
+
+    //
+    // Save the locations and values of the CS pin configuration
+    // information.
+    //
+    pui32CSPadreg = (volatile uint32_t *)AM_HAL_GPIO_PADREG(ui32IOMGPIO);
+    ui32CSPadregVal = *pui32CSPadreg;
+
+    //
+    // Switch CS to a GPIO.
+    //
+    am_hal_gpio_out_bit_set(ui32IOMGPIO);
+    am_hal_gpio_pin_config(ui32IOMGPIO, AM_HAL_GPIO_OUTPUT);
+
+    //
+    // Enable the input buffer on MOSI.
+    //
+    am_hal_gpio_pin_config(WORKAROUND_IOM_MOSI_PIN, WORKAROUND_IOM_MOSI_CFG | AM_HAL_PIN_DIR_INPUT);
+
+    //
+    // Write the GPIO PADKEY register to allow the workaround loop to
+    // reconfigure chip enable.
+    //
+    AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL;
+    // Preconstruct the command - to save on calculations inside critical section
+    ui32Command = internal_am_hal_iom_spi_cmd_construct(AM_HAL_IOM_WRITE,
+                        ui32ChipSelect, ui32NumBytes, ui32Options);
+    internal_iom_workaround_critical(ui32Command,
+            pui32CSPadreg, ui32CSPadregVal,
+            ui32DelayTime, ui32ClkCfg,
+            ui32LowClkCfg, bRising);
+
+    //
+    // Update the pointer and data counter.
+    //
+    ui32NumBytes -= ui32TransferSize;
+    pui32Data += (ui32TransferSize - 4) >> 2;
+}
+
+//*****************************************************************************
+//
+//! @brief Implement an iterative spin loop.
+//!
+//! @param ui32Iterations - Number of iterations to delay.
+//!
+//! Use this function to implement a CPU busy waiting spin.  For Apollo, this
+//! delay can be used for timing purposes since for Apollo, each iteration will
+//! take 3 cycles.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+static void __attribute__((naked))
+iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg,
+                    bool bRising)
+{
+    //
+    // Check to see if this is a "rising edge" or "falling edge" detector.
+    //
+    __asm("    cbz      r2, falling_edge");
+
+    //
+    // Read GPIO pin 44, and loop until it's HIGH.
+    //
+    __asm("rising_edge:");
+    __asm("    ldr      r2, =0x40010084");
+    __asm("rising_check_mosi:");
+    __asm("    ldr      r3, [r2]");
+    __asm("    ands     r3, r3, #0x1000");
+    __asm("    beq      rising_check_mosi");
+
+    //
+    // Write the PADREG Value to the PADREG register.
+    //
+    __asm("    str     r0, [r1]");
+    __asm("    bx      lr");
+
+    //
+    // Read GPIO pin 44, and loop until it's LOW.
+    //
+    __asm("falling_edge:");
+    __asm("    ldr      r2, =0x40010084");
+    __asm("falling_check_mosi:");
+    __asm("    ldr      r3, [r2]");
+    __asm("    ands     r3, r3, #0x1000");
+    __asm("    bne      falling_check_mosi");
+
+    //
+    // Write the PADREG Value to the PADREG register.
+    //
+    __asm("    str     r0, [r1]");
+    __asm("    bx      lr");
+}
+#endif
+#ifdef keil
+__asm static void
+iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg,
+                    bool bRising)
+{
+    //
+    // Check to see if this is a "rising edge" or "falling edge" detector.
+    //
+    cbz      r2, falling_edge
+
+    //
+    // Read GPIO pin 44, and loop until it's HIGH.
+    //
+rising_edge
+    ldr      r2, =0x40010084
+rising_check_mosi
+    ldr      r3, [r2]
+    ands     r3, r3, #0x1000
+    beq      rising_check_mosi
+
+    //
+    // Write the PADREG Value to the PADREG register.
+    //
+    str     r0, [r1]
+    bx      lr
+
+    //
+    // Read GPIO pin 44, and loop until it's LOW.
+    //
+falling_edge
+    ldr      r2, =0x40010084
+falling_check_mosi
+    ldr      r3, [r2]
+    ands     r3, r3, #0x1000
+    bne      falling_check_mosi
+
+    //
+    // Write the PADREG Value to the PADREG register.
+    //
+    str     r0, [r1]
+    bx      lr
+    nop
+}
+#endif
+#ifdef iar
+static void
+iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg,
+                    bool bRising)
+{
+    //
+    // Check to see if this is a "rising edge" or "falling edge" detector.
+    //
+    asm(
+    "    cbz      r2, falling_edge\n"
+
+    //
+    // Read GPIO pin 44, and loop until it's HIGH.
+    //
+    "rising_edge:\n"
+    "    mov32    r2, #0x40010084\n"
+    "rising_check_mosi:\n"
+    "    ldr      r3, [r2]\n"
+    "    ands     r3, r3, #0x1000\n"
+    "    beq      rising_check_mosi\n"
+
+    //
+    // Write the PADREG Value to the PADREG register.
+    //
+    "    str     r0, [r1]\n"
+    "    bx      lr\n"
+
+    //
+    // Read GPIO pin 44, and loop until it's LOW.
+    //
+    "falling_edge:\n"
+    "    mov32    r2, #0x40010084\n"
+    "falling_check_mosi:\n"
+    "    ldr      r3, [r2]\n"
+    "    ands     r3, r3, #0x1000\n"
+    "    bne      falling_check_mosi\n"
+
+    //
+    // Write the PADREG Value to the PADREG register.
+    //
+    "    str     r0, [r1]\n"
+    "    bx      lr"
+    );
+}
+#endif
+
+//*****************************************************************************
+//
+//! @brief Perform a simple write to the SPI interface.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32ChipSelect - Chip-select number for this transaction.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional SPI transfer options.
+//!
+//! This function performs SPI writes to a selected SPI device.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui8Data array.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                     uint32_t *pui32Data, uint32_t ui32NumBytes,
+                     uint32_t ui32Options)
+{
+    //
+    // Validate parameters
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to use an IOM module that doesn't exist.");
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Check to see if queues have been enabled. If they are, we'll actually
+    // switch to the queued interface.
+    //
+    if ( g_psIOMQueue[ui32Module].pui8Data != NULL )
+    {
+        //
+        // If the queue is on, go ahead and add this transaction to the queue.
+        //
+        am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data,
+                                   ui32NumBytes, ui32Options, 0);
+
+        //
+        // Wait until the transaction actually clears.
+        //
+        am_hal_iom_queue_flush(ui32Module);
+
+        //
+        // At this point, we've completed the transaction, and we can return.
+        //
+        return;
+    }
+    else
+    {
+        //
+        // Otherwise, we'll just do a polled transaction.
+        //
+        am_hal_iom_spi_write_nq(ui32Module, ui32ChipSelect, pui32Data,
+                                ui32NumBytes, ui32Options);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Perform simple SPI read operations.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32ChipSelect - Chip-select number for this transaction.
+//! @param pui32Data - Pointer to the array where received bytes should go.
+//! @param ui32NumBytes - Number of bytes to read.
+//! @param ui32Options - Additional SPI transfer options.
+//!
+//! This function performs simple SPI read operations. The caller is
+//! responsible for ensuring that the receive buffer is large enough to hold
+//! the requested amount of data.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This function will pack the individual bytes from the physical interface
+//! into 32-bit words, which are then placed into the \e pui32Data array. Only
+//! the first \e ui32NumBytes bytes in this array will contain valid data.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                    uint32_t *pui32Data, uint32_t ui32NumBytes,
+                    uint32_t ui32Options)
+{
+    //
+    // Validate parameters
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to use an IOM module that doesn't exist.");
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big.");
+
+    //
+    // Check to see if queues have been enabled. If they are, we'll actually
+    // switch to the queued interface.
+    //
+    if ( g_psIOMQueue[ui32Module].pui8Data != NULL )
+    {
+        //
+        // If the queue is on, go ahead and add this transaction to the queue.
+        //
+        am_hal_iom_queue_spi_read(ui32Module, ui32ChipSelect, pui32Data,
+                                  ui32NumBytes, ui32Options, 0);
+
+        //
+        // Wait until the transaction actually clears.
+        //
+        am_hal_iom_queue_flush(ui32Module);
+
+        //
+        // At this point, we've completed the transaction, and we can return.
+        //
+        return;
+    }
+    else
+    {
+        //
+        // Otherwise, just perform a polled transaction.
+        //
+        am_hal_iom_spi_read_nq(ui32Module, ui32ChipSelect, pui32Data,
+                               ui32NumBytes, ui32Options);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Perform a simple write to the SPI interface (without queuing)
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32ChipSelect - Chip-select number for this transaction.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional SPI transfer options.
+//!
+//! This function performs SPI writes to a selected SPI device.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui8Data array.
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                        uint32_t *pui32Data, uint32_t ui32NumBytes,
+                        uint32_t ui32Options)
+{
+    uint32_t ui32TransferSize;
+    uint32_t ui32SpaceInFifo;
+    uint32_t ui32IntConfig;
+    uint32_t ui32MaxFifoSize;
+    uint32_t ui32Status = 1;
+
+    //
+    // Validate parameters
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to use an IOM module that doesn't exist.");
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big.");
+
+    ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ?
+                       AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2);
+    //
+    // Wait until any earlier transactions have completed.
+    //
+    am_hal_iom_poll_complete(ui32Module);
+    //
+    // Disable interrupts so that we don't get any undesired interrupts.
+    //
+    ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN);
+    AM_REGn(IOMSTR, ui32Module, INTEN) = 0;
+    // Clear CMDCMP status
+    AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+
+    //
+    // If we're on a B0 part, and we're using IOM4, our first byte coule be
+    // corrupted, so we need to send a dummy word with chip-select held high to
+    // get that first byte out of the way.
+    //
+    // That operation is tricky and detailed, so we'll call a function to do it
+    // for us.
+    //
+    if ( WORKAROUND_IOM == ui32Module && isRevB0() )
+    {
+        am_hal_iom_workaround_word_write(ui32ChipSelect, pui32Data,
+                                         ui32NumBytes, ui32Options);
+        //
+        // The workaround function is going to a partial transfer for us, but
+        // we have to keep our own data-tracking variables updated. Here, we're
+        // subtracting 4 bytes from the effective transfer size to account for
+        // the 4 bytes of "dummy" word that we sent instead of the actual data.
+        //
+        ui32TransferSize = (ui32NumBytes <= (ui32MaxFifoSize - 4) ? ui32NumBytes :
+                            (ui32MaxFifoSize - 4));
+    }
+    else
+    {
+        //
+        // Figure out how many bytes we can write to the FIFO immediately.
+        //
+        ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes :
+                            ui32MaxFifoSize);
+        //
+        // write our first word to the fifo.
+        //
+
+        am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize);
+
+        //
+        // Start the write on the bus.
+        //
+        am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32ChipSelect,
+                               ui32NumBytes, ui32Options);
+    }
+
+    //
+    // Update the pointer and data counter.
+    //
+    ui32NumBytes -= ui32TransferSize;
+    pui32Data += ui32TransferSize >> 2;
+
+    //
+    // Keep looping until we're out of bytes to send or command complete (error).
+    //
+    while ( ui32NumBytes && !AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP) )
+    {
+        //
+        // This will always return a multiple of four.
+        //
+        ui32SpaceInFifo =  am_hal_iom_fifo_empty_slots(ui32Module);
+
+        if ( ui32NumBytes <= ui32SpaceInFifo )
+        {
+            //
+            // If the entire message will fit in the fifo, prepare to copy
+            // everything.
+            //
+            ui32TransferSize = ui32NumBytes;
+        }
+        else
+        {
+            //
+            // If only a portion of the message will fit in the fifo, prepare
+            // to copy the largest number of 4-byte blocks possible.
+            //
+            ui32TransferSize = ui32SpaceInFifo & ~(0x3);
+        }
+
+        //
+        // Write this chunk to the fifo.
+        //
+        am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize);
+
+        //
+        // Update the data pointer and bytes-left count.
+        //
+        ui32NumBytes -= ui32TransferSize;
+        pui32Data += ui32TransferSize >> 2;
+    }
+
+    //
+    // Make sure CMDCMP was raised with standard timeout
+    //
+    ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module],
+    		AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O,
+    		AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M);
+
+    //
+    // Re-enable IOM interrupts. Make sure CMDCMP is cleared
+    //
+    AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M);
+    AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig;
+
+    am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen");
+    
+    //
+    // Return the status (0 = timeout; 1 = success)
+    //
+    return ui32Status;
+
+}
+
+//*****************************************************************************
+//
+//! @brief Perform simple SPI read operations (without queuing).
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32ChipSelect - Chip-select number for this transaction.
+//! @param pui32Data - Pointer to the array where received bytes should go.
+//! @param ui32NumBytes - Number of bytes to read.
+//! @param ui32Options - Additional SPI transfer options.
+//!
+//! This function performs simple SPI read operations. The caller is
+//! responsible for ensuring that the receive buffer is large enough to hold
+//! the requested amount of data.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This function will pack the individual bytes from the physical interface
+//! into 32-bit words, which are then placed into the \e pui32Data array. Only
+//! the first \e ui32NumBytes bytes in this array will contain valid data.
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                       uint32_t *pui32Data, uint32_t ui32NumBytes,
+                       uint32_t ui32Options)
+{
+    uint32_t ui32BytesInFifo;
+    uint32_t ui32IntConfig;
+    uint32_t bCmdCmp = false;
+    uint32_t ui32Status = 1;
+
+    //
+    // Validate parameters
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to use an IOM module that doesn't exist.");
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big.");
+
+    //
+    // Wait until the bus is idle, then start the requested READ transfer on
+    // the physical interface.
+    //
+    am_hal_iom_poll_complete(ui32Module);
+
+    //
+    // Disable interrupts so that we don't get any undesired interrupts.
+    //
+    ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN);
+
+    //
+    // Disable IOM interrupts as we'll be polling
+    //
+    AM_REGn(IOMSTR, ui32Module, INTEN) = 0;
+
+    //
+    // Clear CMDCMP status
+    //
+    AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+
+    //
+    // If we're on a B0 part, and we're using IOM4, our first byte coule be
+    // corrupted, so we need to send a dummy word with chip-select held high to
+    // get that first byte out of the way. This is only true for spi reads with
+    // OFFSET values.
+    //
+    // That operation is tricky and detailed, so we'll call a function to do it
+    // for us.
+    //
+    if ( (WORKAROUND_IOM == ui32Module) && !(ui32Options & AM_HAL_IOM_RAW) &&
+        isRevB0() )
+    {
+        am_hal_iom_workaround_word_write(ui32ChipSelect, pui32Data, 0,
+                                         ui32Options | AM_HAL_IOM_CS_LOW);
+
+        //
+        // The workaround will send our offset for us, so we can run a RAW
+        // command after.
+        //
+        ui32Options |= AM_HAL_IOM_RAW;
+        //
+        // Wait for the dummy word to go out over the bus.
+        //
+        // Make sure the command complete has also been raised
+        ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module],
+    		AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O,
+    		AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M);
+        
+        
+        // Clear CMDCMP status
+        AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+    }
+
+    am_hal_iom_spi_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32ChipSelect,
+                           ui32NumBytes, ui32Options);
+
+    //
+    // Start a loop to catch the Rx data.
+    //
+    while ( ui32NumBytes )
+    {
+        ui32BytesInFifo =  am_hal_iom_fifo_full_slots(ui32Module);
+
+        if ( ui32BytesInFifo >= ui32NumBytes )
+        {
+            //
+            // If the fifo contains our entire message, just copy the whole
+            // thing out.
+            //
+            am_hal_iom_fifo_read(ui32Module, pui32Data, ui32NumBytes);
+            ui32NumBytes = 0;
+        }
+        else if ( ui32BytesInFifo >= 4 )
+        {
+            //
+            // If the fifo has at least one 32-bit word in it, copy whole
+            // words out.
+            //
+            am_hal_iom_fifo_read(ui32Module, pui32Data, ui32BytesInFifo & ~0x3);
+            ui32NumBytes -= ui32BytesInFifo & ~0x3;
+            pui32Data += ui32BytesInFifo >> 2;
+        }
+        if ( bCmdCmp == true )
+        {
+            //
+            // No more data expected. Get out of the loop
+            //
+            break;
+        }
+
+        bCmdCmp = AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP);
+    }
+
+    //
+    // Make sure CMDCMP was raised,
+    //
+    ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module],
+    		AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O,
+    		AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M);
+
+    //
+    // Re-enable IOM interrupts. Make sure CMDCMP is cleared
+    //
+    AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M);
+    AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig;
+
+    am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen");
+    
+    //
+    // Return the status (0 = timeout; 1 = success)
+    //
+    return ui32Status;
+}
+
+//*****************************************************************************
+//
+//! @brief Perform a non-blocking write to the SPI interface.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32ChipSelect - Chip-select number for this transaction.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional SPI transfer options.
+//! @param pfnCallback - Function to call when the transaction completes.
+//!
+//! This function performs SPI writes to the selected SPI device.
+//!
+//! This function call is a non-blocking implementation. It will write as much
+//! data to the FIFO as possible immediately, store a pointer to the remaining
+//! data, start the transfer on the bus, and then immediately return. The
+//! caller will need to make sure that \e am_hal_iom_int_service() is called
+//! for IOM FIFO interrupt events and "command complete" interrupt events. The
+//! \e am_hal_iom_int_service() function will refill the FIFO as necessary and
+//! call the \e pfnCallback function when the transaction is finished.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui8Data array.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                        uint32_t *pui32Data, uint32_t ui32NumBytes,
+                        uint32_t ui32Options,
+                        am_hal_iom_callback_t pfnCallback)
+{
+    uint32_t ui32TransferSize;
+    uint32_t ui32MaxFifoSize;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big.");
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ?
+                      AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2);
+
+    //
+    // Wait until the bus is idle
+    //
+    am_hal_iom_poll_complete(ui32Module);
+
+    //
+    // Need to mark IOM busy to avoid another transaction to be scheduled.
+    // This is to take care of a race condition in Queue mode, where the IDLE
+    // set is not a guarantee that the CMDCMP has been received
+    //
+    g_bIomBusy[ui32Module] = true;
+
+    //
+    // Clear CMDCMP status
+    //
+    AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+
+    //
+    // Check to see if we need to do the workaround.
+    //
+    if ( WORKAROUND_IOM == ui32Module && isRevB0() )
+    {
+        //
+        // Figure out how many bytes we can write to the FIFO immediately,
+        // accounting for the extra word from the workaround.
+        //
+        ui32TransferSize = (ui32NumBytes <= (ui32MaxFifoSize - 4) ?  ui32NumBytes :
+                            (ui32MaxFifoSize - 4));
+
+        //
+        // Prepare the global IOM buffer structure.
+        //
+        g_psIOMBuffers[ui32Module].ui32State = BUFFER_SENDING;
+        g_psIOMBuffers[ui32Module].pui32Data = pui32Data + (ui32TransferSize / 4);
+        g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes - ui32TransferSize;
+        g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback;
+        g_psIOMBuffers[ui32Module].ui32Options = ui32Options;
+
+        //
+        // Start the write on the bus using the workaround. This includes both
+        // the command write and the first fifo write, so we won't need to do
+        // either of those things manually.
+        //
+        am_hal_iom_workaround_word_write(ui32ChipSelect, pui32Data,
+                                         ui32NumBytes, ui32Options);
+    }
+    else
+    {
+        //
+        // Figure out how many bytes we can write to the FIFO immediately.
+        //
+        ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes :
+                            ui32MaxFifoSize);
+
+        if ( am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize) > 0 )
+        {
+            //
+            // Prepare the global IOM buffer structure.
+            //
+            g_psIOMBuffers[ui32Module].ui32State = BUFFER_SENDING;
+            g_psIOMBuffers[ui32Module].pui32Data = pui32Data;
+            g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes;
+            g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback;
+            g_psIOMBuffers[ui32Module].ui32Options = ui32Options;
+
+            //
+            // Update the pointer and the byte counter based on the portion of
+            // the transfer we just sent to the fifo.
+            //
+            g_psIOMBuffers[ui32Module].ui32BytesLeft -= ui32TransferSize;
+            g_psIOMBuffers[ui32Module].pui32Data += (ui32TransferSize / 4);
+
+            //
+            // Start the write on the bus.
+            //
+            am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32ChipSelect,
+                                   ui32NumBytes, ui32Options);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Perform a non-blocking SPI read.
+//!
+//! @param ui32Module - Module number for the IOM.
+//! @param ui32ChipSelect - Chip select number of the target device.
+//! @param pui32Data - Pointer to the array where received bytes should go.
+//! @param ui32NumBytes - Number of bytes to read.
+//! @param ui32Options - Additional SPI transfer options.
+//! @param pfnCallback - Function to call when the transaction completes.
+//!
+//! This function performs SPI reads to a selected SPI device.
+//!
+//! This function call is a non-blocking implementation. It will start the SPI
+//! transaction on the bus and store a pointer for the destination for the read
+//! data, but it will not wait for the SPI transaction to finish.  The caller
+//! will need to make sure that \e am_hal_iom_int_service() is called for IOM
+//! FIFO interrupt events and "command complete" interrupt events. The \e
+//! am_hal_iom_int_service() function will empty the FIFO as necessary,
+//! transfer the data to the \e pui32Data buffer, and call the \e pfnCallback
+//! function when the transaction is finished.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This function will pack the individual bytes from the physical interface
+//! into 32-bit words, which are then placed into the \e pui32Data array. Only
+//! the first \e ui32NumBytes bytes in this array will contain valid data.
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                       uint32_t *pui32Data, uint32_t ui32NumBytes,
+                       uint32_t ui32Options,
+                       am_hal_iom_callback_t pfnCallback)
+{
+    uint32_t ui32IntConfig;
+    uint32_t ui32Status = 1;
+    
+    //
+    // Validate parameters
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES,
+                            "Trying to use an IOM module that doesn't exist.");
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big.");
+
+    //
+    // Wait until the bus is idle
+    //
+    am_hal_iom_poll_complete(ui32Module);
+
+    //
+    // Need to mark IOM busy to avoid another transaction to be scheduled.
+    // This is to take care of a race condition in Queue mode, where the IDLE
+    // set is not a guarantee that the CMDCMP has been received
+    //
+
+    g_bIomBusy[ui32Module] = true;
+
+    //
+    // Clear CMDCMP status
+    //
+    AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+
+    //
+    // If we're on a B0 part, and we're using IOM4, our first byte coule be
+    // corrupted, so we need to send a dummy word with chip-select held high to
+    // get that first byte out of the way. This is only true for spi reads with
+    // OFFSET values.
+    //
+    // That operation is tricky and detailed, so we'll call a function to do it
+    // for us.
+    //
+    if ( (WORKAROUND_IOM == ui32Module) && !(ui32Options & AM_HAL_IOM_RAW) &&
+        isRevB0() )
+    {
+        //
+        // We might mess up the interrupt handler behavior if we allow this
+        // polled transaction to complete with interrupts enabled. We'll
+        // briefly turn them off here.
+        //
+        ui32IntConfig = AM_REGn(IOMSTR, 4, INTEN);
+        AM_REGn(IOMSTR, 4, INTEN) = 0;
+
+        am_hal_iom_workaround_word_write(ui32ChipSelect, pui32Data,
+                                         0, ui32Options | AM_HAL_IOM_CS_LOW);
+
+        //
+        // The workaround will send our offset for us, so we can run a RAW
+        // command after.
+        //
+        ui32Options |= AM_HAL_IOM_RAW;
+
+        //
+        // Wait for the dummy word to go out over the bus.
+        //
+        // Make sure the command complete has also been raised
+        ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module],
+    		AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O,
+    		AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M);
+
+        //
+        // Re-mark IOM as busy
+        //
+
+        g_bIomBusy[ui32Module] = true;
+
+        //
+        // Re-enable IOM interrupts. Make sure CMDCMP is cleared
+        //
+        AM_REGn(IOMSTR, 4, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M);
+        AM_REGn(IOMSTR, 4, INTEN) = ui32IntConfig;
+    }
+
+    //
+    // Prepare the global IOM buffer structure.
+    //
+    g_psIOMBuffers[ui32Module].ui32State = BUFFER_RECEIVING;
+    g_psIOMBuffers[ui32Module].pui32Data = pui32Data;
+    g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes;
+    g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback;
+    g_psIOMBuffers[ui32Module].ui32Options = ui32Options;
+
+    //
+    // Start the read transaction on the bus.
+    //
+    am_hal_iom_spi_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32ChipSelect,
+                           ui32NumBytes, ui32Options);
+    
+    am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen");
+    
+    return ui32Status;
+}
+
+static uint32_t
+internal_am_hal_iom_spi_cmd_construct(uint32_t ui32Operation,
+                                      uint32_t ui32ChipSelect,
+                                      uint32_t ui32NumBytes,
+                                      uint32_t ui32Options)
+{
+    uint32_t ui32Command;
+    //
+    // Start building the command from the operation parameter.
+    //
+    ui32Command = ui32Operation;
+
+    //
+    // Set the transfer length (the length field is split, so this requires
+    // some swizzling).
+    //
+    ui32Command |= ((ui32NumBytes & 0xF00) << 15);
+    ui32Command |= (ui32NumBytes & 0xFF);
+
+    //
+    // Set the chip select number.
+    //
+    ui32Command |= ((ui32ChipSelect << 16) & 0x00070000);
+
+    //
+    // Finally, OR in the rest of the options. This mask should make sure that
+    // erroneous option values won't interfere with the other transfer
+    // parameters.
+    //
+    ui32Command |= ui32Options & 0x5C00FF00;
+    return ui32Command;
+}
+//*****************************************************************************
+//
+//! @brief Runs a SPI "command" through the IO master.
+//!
+//! @param ui32Operation - SPI action to be performed.
+//!
+//! @param psDevice - Structure containing information about the slave device.
+//!
+//! @param ui32NumBytes - Number of bytes to move (transmit or receive) with
+//! this command.
+//!
+//! @param ui32Options - Additional SPI options to apply to this command.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_spi_cmd_run(uint32_t ui32Operation, uint32_t ui32Module,
+                       uint32_t ui32ChipSelect, uint32_t ui32NumBytes,
+                       uint32_t ui32Options)
+{
+    uint32_t ui32Command;
+
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+    ui32Command = internal_am_hal_iom_spi_cmd_construct(ui32Operation,
+                        ui32ChipSelect, ui32NumBytes, ui32Options);
+
+
+    //
+    // Write the complete command word to the IOM command register.
+    //
+    AM_REGn(IOMSTR, ui32Module, CMD) = ui32Command;
+}
+
+//*****************************************************************************
+//
+//! @brief Perform a simple write to the I2C interface (without queuing)
+//!
+//! @param ui32Module - Module number for the IOM.
+//! @param ui32BusAddress - I2C address of the target device.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional I2C transfer options.
+//!
+//! This function performs I2C writes to a selected I2C device.
+//!
+//! This function call is a blocking implementation. It will write as much
+//! data to the FIFO as possible immediately, and then refill the FIFO as data
+//! is transmiitted.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui32Data array.
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress,
+                        uint32_t *pui32Data, uint32_t ui32NumBytes,
+                        uint32_t ui32Options)
+{
+    uint32_t ui32TransferSize;
+    uint32_t ui32SpaceInFifo;
+    uint32_t ui32IntConfig;
+    uint32_t ui32MaxFifoSize;
+    uint32_t ui32Status = 1;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Redirect to the bit-bang interface if the module number matches the
+    // software I2C module.
+    //
+    if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE )
+    {
+        if ( ui32Options & AM_HAL_IOM_RAW )
+        {
+            am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes,
+                                     (uint8_t *)pui32Data, 0, false,
+                                     (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+        else
+        {
+            am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes,
+                                     (uint8_t *)pui32Data,
+                                     ((ui32Options & 0xFF00) >> 8),
+                                     true,
+                                     (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+
+        //
+        // Return.
+        //
+        return 0;
+    }
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big.");
+
+    ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ?
+                      AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2);
+
+    //
+    // Wait until any earlier transactions have completed.
+    //
+    am_hal_iom_poll_complete(ui32Module);
+
+    //
+    // Disable interrupts so that we don't get any undesired interrupts.
+    //
+    ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN);
+    AM_REGn(IOMSTR, ui32Module, INTEN) = 0;
+
+    //
+    // Clear CMDCMP status
+    //
+    AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+
+    //
+    // Figure out how many bytes we can write to the FIFO immediately.
+    //
+    ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes :
+                        ui32MaxFifoSize);
+
+    am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize);
+
+    //
+    // Start the write on the bus.
+    //
+    am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress,
+                           ui32NumBytes, ui32Options);
+
+    //
+    // Update the pointer and data counter.
+    //
+    ui32NumBytes -= ui32TransferSize;
+    pui32Data += ui32TransferSize >> 2;
+
+    //
+    // Keep looping until we're out of bytes to send or command complete (error).
+    //
+    while ( ui32NumBytes && !AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP) )
+    {
+        //
+        // This will always return a multiple of four.
+        //
+        ui32SpaceInFifo =  am_hal_iom_fifo_empty_slots(ui32Module);
+
+        if ( ui32NumBytes <= ui32SpaceInFifo )
+        {
+            //
+            // If the entire message will fit in the fifo, prepare to copy
+            // everything.
+            //
+            ui32TransferSize = ui32NumBytes;
+        }
+        else
+        {
+            //
+            // If only a portion of the message will fit in the fifo, prepare
+            // to copy the largest number of 4-byte blocks possible.
+            //
+            ui32TransferSize = ui32SpaceInFifo;
+        }
+
+        //
+        // Write this chunk to the fifo.
+        //
+        am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize);
+
+        //
+        // Update the data pointer and bytes-left count.
+        //
+        ui32NumBytes -= ui32TransferSize;
+        pui32Data += ui32TransferSize >> 2;
+    }
+
+    //
+    // Make sure CMDCMP was raised,
+    //
+    ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module],
+    		AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O,
+    		AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M);
+
+    //
+    // Re-enable IOM interrupts. Make sure CMDCMP is cleared
+    //
+    AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M);
+    AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig;
+    
+    am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen");
+    
+    //
+    // Return the status (0 = timeout; 1 = success)
+    //
+    return ui32Status;
+}
+
+//*****************************************************************************
+//
+//! @brief Perform simple I2C read operations (without queuing).
+//!
+//! @param ui32Module - Module number for the IOM.
+//! @param ui32BusAddress - I2C address of the target device.
+//! @param pui32Data - Pointer to the array where received bytes should go.
+//! @param ui32NumBytes - Number of bytes to read.
+//! @param ui32Options - Additional I2C transfer options.
+//!
+//! This function performs an I2C read to a selected I2C device.
+//!
+//! This function call is a blocking implementation. It will read as much
+//! data from the FIFO as possible immediately, and then re-read the FIFO as more
+//! data is available.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This function will pack the individual bytes from the physical interface
+//! into 32-bit words, which are then placed into the \e pui32Data array. Only
+//! the first \e ui32NumBytes bytes in this array will contain valid data.
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress,
+                       uint32_t *pui32Data, uint32_t ui32NumBytes,
+                       uint32_t ui32Options)
+{
+    uint32_t ui32BytesInFifo;
+    uint32_t ui32IntConfig;
+    uint32_t bCmdCmp = false;
+    uint32_t ui32Status = 1;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Redirect to the bit-bang interface if the module number matches the
+    // software I2C module.
+    //
+    if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE )
+    {
+        if ( ui32Options & AM_HAL_IOM_RAW )
+        {
+            am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes,
+                                        (uint8_t *)pui32Data, 0, false,
+                                        (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+        else
+        {
+            am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes,
+                                        (uint8_t *)pui32Data,
+                                        ((ui32Options & 0xFF00) >> 8),
+                                        true,
+                                        (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+
+        //
+        // Return.
+        //
+        return 0;
+    }
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big.");
+
+    //
+    // Wait until the bus is idle
+    //
+    am_hal_iom_poll_complete(ui32Module);
+
+    //
+    // Disable interrupts so that we don't get any undesired interrupts.
+    //
+    ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN);
+    AM_REGn(IOMSTR, ui32Module, INTEN) = 0;
+
+    //
+    // Clear CMDCMP status
+    //
+    AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+
+    am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress,
+                           ui32NumBytes, ui32Options);
+
+    //
+    // Start a loop to catch the Rx data.
+    //
+    while ( ui32NumBytes )
+    {
+        ui32BytesInFifo =  am_hal_iom_fifo_full_slots(ui32Module);
+
+        if ( ui32BytesInFifo >= ui32NumBytes )
+        {
+            //
+            // If the fifo contains our entire message, just copy the whole
+            // thing out.
+            //
+            am_hal_iom_fifo_read(ui32Module, pui32Data, ui32NumBytes);
+            ui32NumBytes = 0;
+        }
+        else if ( ui32BytesInFifo >= 4 )
+        {
+            //
+            // If the fifo has at least one 32-bit word in it, copy whole
+            // words out.
+            //
+            am_hal_iom_fifo_read(ui32Module, pui32Data, ui32BytesInFifo & ~0x3);
+
+            ui32NumBytes -= ui32BytesInFifo & ~0x3;
+            pui32Data += ui32BytesInFifo >> 2;
+        }
+
+        if ( bCmdCmp == true )
+        {
+            // No more data expected - exit out of loop
+            break;
+        }
+
+        bCmdCmp = AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP);
+    }
+
+    //
+    // Make sure CMDCMP was raised,
+    //
+    ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module],
+    		AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O,
+    		AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M);
+
+    //
+    // Re-enable IOM interrupts. Make sure CMDCMP is cleared
+    //
+    AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M);
+    AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig;
+    
+    am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen");
+    
+    //
+    // Return the status (0 = timeout; 1 = success)
+    //
+    return ui32Status;
+}
+
+//*****************************************************************************
+//
+//! @brief Perform a simple write to the I2C interface.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32BusAddress - I2C bus address for this transaction.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional options
+//!
+//! Performs a write to the I2C interface using the provided parameters.
+//!
+//! See the "Command Options" section for parameters that may be ORed together
+//! and used in the \b ui32Options parameter.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress,
+                     uint32_t *pui32Data, uint32_t ui32NumBytes,
+                     uint32_t ui32Options)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Redirect to the bit-bang interface if the module number matches the
+    // software I2C module.
+    //
+    if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE )
+    {
+        if ( ui32Options & AM_HAL_IOM_RAW )
+        {
+            am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes,
+                                     (uint8_t *)pui32Data, 0, false,
+                                     (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+        else
+        {
+            am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes,
+                                     (uint8_t *)pui32Data,
+                                     ((ui32Options & 0xFF00) >> 8),
+                                     true,
+                                     (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+
+        //
+        // Return.
+        //
+        return;
+    }
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big.");
+
+    //
+    // Check to see if queues have been enabled. If they are, we'll actually
+    // switch to the queued interface.
+    //
+    if ( g_psIOMQueue[ui32Module].pui8Data != NULL )
+    {
+        //
+        // If the queue is on, go ahead and add this transaction to the queue.
+        //
+        am_hal_iom_queue_i2c_write(ui32Module, ui32BusAddress, pui32Data,
+                                   ui32NumBytes, ui32Options, 0);
+
+        //
+        // Wait until the transaction actually clears.
+        //
+        am_hal_iom_queue_flush(ui32Module);
+
+        //
+        // At this point, we've completed the transaction, and we can return.
+        //
+        return;
+    }
+    else
+    {
+        //
+        // Otherwise, we'll just do a polled transaction.
+        //
+        am_hal_iom_i2c_write_nq(ui32Module, ui32BusAddress, pui32Data,
+                                ui32NumBytes, ui32Options);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Perform simple I2C read operations.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32BusAddress - I2C bus address for this transaction.
+//! @param pui32Data - Pointer to the array where received bytes should go.
+//! @param ui32NumBytes - Number of bytes to read.
+//! @param ui32Options - Additional I2C transfer options.
+//!
+//! This function performs simple I2C read operations. The caller is
+//! responsible for ensuring that the receive buffer is large enough to hold
+//! the requested amount of data. If \e bPolled is true, this function will
+//! block until all of the requested data has been received and placed in the
+//! user-supplied buffer. Otherwise, the function will execute the I2C read
+//! command and return immediately. The user-supplied buffer will be filled
+//! with the received I2C data as it comes in over the physical interface, and
+//! the "command complete" interrupt bit will become active once the entire
+//! message is available.
+//!
+//! See the "Command Options" section for parameters that may be ORed together
+//! and used in the \b ui32Options parameter.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This function will pack the individual bytes from the physical interface
+//! into 32-bit words, which are then placed into the \e pui32Data array. Only
+//! the first \e ui32NumBytes bytes in this array will contain valid data.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress,
+                    uint32_t *pui32Data, uint32_t ui32NumBytes,
+                    uint32_t ui32Options)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Redirect to the bit-bang interface if the module number matches the
+    // software I2C module.
+    //
+    if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE )
+    {
+        if ( ui32Options & AM_HAL_IOM_RAW )
+        {
+            am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes,
+                                        (uint8_t *)pui32Data, 0, false,
+                                        (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+        else
+        {
+            am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes,
+                                        (uint8_t *)pui32Data,
+                                        ((ui32Options & 0xFF00) >> 8),
+                                        true,
+                                        (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+
+        //
+        // Return.
+        //
+        return;
+    }
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big.");
+
+    //
+    // Check to see if queues have been enabled. If they are, we'll actually
+    // switch to the queued interface.
+    //
+    if ( g_psIOMQueue[ui32Module].pui8Data != NULL )
+    {
+        //
+        // If the queue is on, go ahead and add this transaction to the queue.
+        //
+        am_hal_iom_queue_i2c_read(ui32Module, ui32BusAddress, pui32Data,
+                                  ui32NumBytes, ui32Options, 0);
+
+        //
+        // Wait until the transaction actually clears.
+        //
+        am_hal_iom_queue_flush(ui32Module);
+
+        //
+        // At this point, we've completed the transaction, and we can return.
+        //
+        return;
+    }
+    else
+    {
+        //
+        // Otherwise, just perform a polled transaction.
+        //
+        am_hal_iom_i2c_read_nq(ui32Module, ui32BusAddress, pui32Data,
+                               ui32NumBytes, ui32Options);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Perform a non-blocking write to the I2C interface.
+//!
+//! @param ui32Module - Module number for the IOM.
+//! @param ui32BusAddress - I2C address of the target device.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional I2C transfer options.
+//! @param pfnCallback - Function to call when the transaction completes.
+//!
+//! This function performs I2C writes to a selected I2C device.
+//!
+//! This function call is a non-blocking implementation. It will write as much
+//! data to the FIFO as possible immediately, store a pointer to the remaining
+//! data, start the transfer on the bus, and then immediately return. The
+//! caller will need to make sure that \e am_hal_iom_int_service() is called
+//! for IOM FIFO interrupt events and "command complete" interrupt events. The
+//! \e am_hal_iom_int_service() function will refill the FIFO as necessary and
+//! call the \e pfnCallback function when the transaction is finished.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui32Data array.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress,
+                        uint32_t *pui32Data, uint32_t ui32NumBytes,
+                        uint32_t ui32Options,
+                        am_hal_iom_callback_t pfnCallback)
+{
+    uint32_t ui32TransferSize;
+    uint32_t ui32MaxFifoSize;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Redirect to the bit-bang interface if the module number matches the
+    // software I2C module.
+    //
+    if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE )
+    {
+        if ( ui32Options & AM_HAL_IOM_RAW )
+        {
+            am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes,
+                                     (uint8_t *)pui32Data, 0, false,
+                                     (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+        else
+        {
+            am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes,
+                                     (uint8_t *)pui32Data,
+                                     ((ui32Options & 0xFF00) >> 8),
+                                     true,
+                                     (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+
+        //
+        // The I2C bit-bang interface is actually a blocking transfer, and it
+        // doesn't trigger the interrupt handler, so we have to call the
+        // callback function manually.
+        //
+        if ( pfnCallback )
+        {
+            pfnCallback();
+        }
+        //
+        // Return.
+        //
+        return;
+    }
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big.");
+
+    ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ?
+                       AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2);
+
+    //
+    // Figure out how many bytes we can write to the FIFO immediately.
+    //
+    ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes :
+                        ui32MaxFifoSize);
+
+    //
+    // Wait until any earlier transactions have completed, and then write our
+    // first word to the fifo.
+    //
+    am_hal_iom_poll_complete(ui32Module);
+
+    // Need to mark IOM busy to avoid another transaction to be scheduled.
+    // This is to take care of a race condition in Queue mode, where the IDLE
+    // set is not a guarantee that the CMDCMP has been received
+    g_bIomBusy[ui32Module] = true;
+
+    //
+    // Clear CMDCMP status
+    //
+    AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+
+    if ( am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize) > 0 )
+    {
+        //
+        // Prepare the global IOM buffer structure.
+        //
+        g_psIOMBuffers[ui32Module].ui32State = BUFFER_SENDING;
+        g_psIOMBuffers[ui32Module].pui32Data = pui32Data;
+        g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes;
+        g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback;
+
+        //
+        // Update the pointer and the byte counter based on the portion of the
+        // transfer we just sent to the fifo.
+        //
+        g_psIOMBuffers[ui32Module].ui32BytesLeft -= ui32TransferSize;
+        g_psIOMBuffers[ui32Module].pui32Data += (ui32TransferSize / 4);
+
+        //
+        // Start the write on the bus.
+        //
+        am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress,
+                               ui32NumBytes, ui32Options);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Perform a non-blocking I2C read.
+//!
+//! @param ui32Module - Module number for the IOM.
+//! @param ui32ChipSelect - I2C address of the target device.
+//! @param pui32Data - Pointer to the array where received bytes should go.
+//! @param ui32NumBytes - Number of bytes to read.
+//! @param ui32Options - Additional I2C transfer options.
+//! @param pfnCallback - Function to call when the transaction completes.
+//!
+//! This function performs an I2C read to a selected I2C device.
+//!
+//! This function call is a non-blocking implementation. It will start the I2C
+//! transaction on the bus and store a pointer for the destination for the read
+//! data, but it will not wait for the I2C transaction to finish.  The caller
+//! will need to make sure that \e am_hal_iom_int_service() is called for IOM
+//! FIFO interrupt events and "command complete" interrupt events. The \e
+//! am_hal_iom_int_service() function will empty the FIFO as necessary,
+//! transfer the data to the \e pui32Data buffer, and call the \e pfnCallback
+//! function when the transaction is finished.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This function will pack the individual bytes from the physical interface
+//! into 32-bit words, which are then placed into the \e pui32Data array. Only
+//! the first \e ui32NumBytes bytes in this array will contain valid data.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress,
+                       uint32_t *pui32Data, uint32_t ui32NumBytes,
+                       uint32_t ui32Options,
+                       am_hal_iom_callback_t pfnCallback)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Redirect to the bit-bang interface if the module number matches the
+    // software I2C module.
+    //
+    if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE )
+    {
+        if ( ui32Options & AM_HAL_IOM_RAW )
+        {
+            am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes,
+                                        (uint8_t *)pui32Data, 0, false,
+                                        (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+        else
+        {
+            am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes,
+                                        (uint8_t *)pui32Data,
+                                        ((ui32Options & 0xFF00) >> 8),
+                                        true,
+                                        (ui32Options & AM_HAL_IOM_NO_STOP));
+        }
+
+        //
+        // The I2C bit-bang interface is actually a blocking transfer, and it
+        // doesn't trigger the interrupt handler, so we have to call the
+        // callback function manually.
+        //
+        if ( pfnCallback )
+        {
+            pfnCallback();
+        }
+
+        //
+        // Return.
+        //
+        return;
+    }
+
+    //
+    // Make sure the transfer isn't too long for the hardware to support.
+    //
+    am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big.");
+
+    //
+    // Wait until the bus is idle
+    //
+    am_hal_iom_poll_complete(ui32Module);
+
+    //
+    // Need to mark IOM busy to avoid another transaction to be scheduled.
+    // This is to take care of a race condition in Queue mode, where the IDLE
+    // set is not a guarantee that the CMDCMP has been received
+    //
+    g_bIomBusy[ui32Module] = true;
+
+    //
+    // Clear CMDCMP status
+    //
+    AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1);
+
+    //
+    // Prepare the global IOM buffer structure.
+    //
+    g_psIOMBuffers[ui32Module].ui32State = BUFFER_RECEIVING;
+    g_psIOMBuffers[ui32Module].pui32Data = pui32Data;
+    g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes;
+    g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback;
+
+    //
+    // Start the read transaction on the bus.
+    //
+    am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress,
+                           ui32NumBytes, ui32Options);
+}
+
+//*****************************************************************************
+//
+//! @brief Runs a I2C "command" through the IO master.
+//!
+//! @param ui32Operation - I2C action to be performed. This should either be
+//! AM_HAL_IOM_WRITE or AM_HAL_IOM_READ.
+//! @param psDevice - Structure containing information about the slave device.
+//! @param ui32NumBytes - Number of bytes to move (transmit or receive) with
+//! this command.
+//! @param ui32Options - Additional I2C options to apply to this command.
+//!
+//! This function may be used along with am_hal_iom_fifo_write and
+//! am_hal_iom_fifo_read to perform more complex I2C reads and writes. This
+//! function
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, uint32_t ui32Module,
+                       uint32_t ui32BusAddress, uint32_t ui32NumBytes,
+                       uint32_t ui32Options)
+{
+    uint32_t ui32Command;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Start building the command from the operation parameter.
+    //
+    ui32Command = ui32Operation;
+
+    //
+    // Set the transfer length.
+    //
+    ui32Command |= (ui32NumBytes & 0xFF);
+
+    //
+    // Set the chip select number.
+    //
+    ui32Command |= ((ui32BusAddress << 16) & 0x03FF0000);
+
+    //
+    // Finally, OR in the rest of the options. This mask should make sure that
+    // erroneous option values won't interfere with the other transfer
+    // parameters.
+    //
+    ui32Command |= (ui32Options & 0x5C00FF00);
+
+    //
+    // Write the complete command word to the IOM command register.
+    //
+    AM_REGn(IOMSTR, ui32Module, CMD) = ui32Command;
+}
+
+//*****************************************************************************
+//
+//! @brief Sets the repeat count for the next IOM command.
+//!
+//! @param ui32Module is the IOM module number.
+//! @param ui32CmdCount is the number of times the next command should be
+//! executed.
+//!
+//! @note This function is not compatible with the am_hal_iom_spi_read/write()
+//! or am_hal_iom_i2c_read/write() functions. Instead, you will need to use the
+//! am_hal_iom_fifo_read/write() functions and the am_hal_iom_spi/i2c_cmd_run()
+//! functions.
+//!
+//! Example usage:
+//! @code
+//!
+//! //
+//! // Create a buffer and add 3 bytes of data to it.
+//! //
+//! am_hal_iom_buffer(3) psBuffer;
+//! psBuffer.bytes[0] = 's';
+//! psBuffer.bytes[1] = 'p';
+//! psBuffer.bytes[2] = 'i';
+//!
+//! //
+//! // Send three different bytes to the same SPI register on a remote device.
+//! //
+//! am_hal_iom_fifo_write(ui32Module, psBuffer.words, 3);
+//!
+//! am_hal_command_repeat_set(ui32Module, 3);
+//!
+//! am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, psDevice, 1,
+//!                        AM_HAL_IOM_OFFSET(0x5));
+//!
+//! //
+//! // The sequence "0x5, 's', 0x5, 'p', 0x5, 'i'" should be written to the SPI
+//! // bus.
+//! //
+//!
+//! @endcode
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_command_repeat_set(uint32_t ui32Module, uint32_t ui32CmdCount)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    AM_REGn(IOMSTR, ui32Module, CMDRPT) = ui32CmdCount;
+}
+
+//*****************************************************************************
+//
+//! @brief Writes data to the IOM FIFO.
+//!
+//! @param ui32Module - Selects the IOM module to use (zero or one).
+//! @param pui32Data - Pointer to an array of the data to be written.
+//! @param ui32NumBytes - Number of BYTES to copy into the FIFO.
+//!
+//! This function copies data from the array \e pui32Data into the IOM FIFO.
+//! This prepares the data to eventually be sent as SPI or I2C data by an IOM
+//! "command".
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui8Data array.
+//!
+//! @note This function may be used to write partial or complete SPI or I2C
+//! messages into the IOM FIFO. When writing partial messages to the FIFO, make
+//! sure that the number of bytes written is a multiple of four. Only the last
+//! 'part' of a message may consist of a number of bytes that is not a multiple
+//! of four. If this rule is not followed, the IOM will not be able to send
+//! these bytes correctly.
+//!
+//! @return Number of bytes actually written to the FIFO.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data,
+                      uint32_t ui32NumBytes)
+{
+    uint32_t ui32Index;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+
+    //
+    // Make sure we check the number of bytes we're writing to the FIFO.
+    //
+    am_hal_debug_assert_msg((am_hal_iom_fifo_empty_slots(ui32Module) >= ui32NumBytes),
+                            "The fifo couldn't fit the requested number of bytes");
+
+    //
+    // Loop over the words in the array until we have the correct number of
+    // bytes.
+    //
+    for ( ui32Index = 0; (4 * ui32Index) < ui32NumBytes; ui32Index++ )
+    {
+        //
+        // Write the word to the FIFO.
+        //
+        AM_REGn(IOMSTR, ui32Module, FIFO) = pui32Data[ui32Index];
+    }
+
+    return ui32NumBytes;
+}
+
+//*****************************************************************************
+//
+//! @brief Reads data from the IOM FIFO.
+//!
+//! @param ui32Module - Selects the IOM module to use (zero or one).
+//! @param pui32Data - Pointer to an array where the FIFO data will be copied.
+//! @param ui32NumBytes - Number of bytes to copy into array.
+//!
+//! This function copies data from the IOM FIFO into the array \e pui32Data.
+//! This is how input data from SPI or I2C transactions may be retrieved.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This function will pack the individual bytes from the physical interface
+//! into 32-bit words, which are then placed into the \e pui32Data array. Only
+//! the first \e ui32NumBytes bytes in this array will contain valid data.
+//!
+//! @return Number of bytes read from the fifo.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data,
+                     uint32_t ui32NumBytes)
+{
+    am_hal_iom_buffer(4) sTempBuffer;
+    uint32_t i, j, ui32NumWords, ui32Leftovers;
+    uint8_t *pui8Data;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+
+    //
+    // Make sure we check the number of bytes we're reading from the FIFO.
+    //
+    am_hal_debug_assert_msg((am_hal_iom_fifo_full_slots(ui32Module) >= ui32NumBytes),
+                            "The fifo doesn't contain the requested number of bytes.");
+
+    //
+    // Figure out how many whole words we're reading from the fifo, and how
+    // many bytes will be left over when we're done.
+    //
+    ui32NumWords = ui32NumBytes / 4;
+    ui32Leftovers = ui32NumBytes - (ui32NumWords * 4);
+
+    //
+    // Copy out as many full words as we can.
+    //
+    for ( i = 0; i < ui32NumWords; i++ )
+    {
+        //
+        // Copy data out of the FIFO, one word at a time.
+        //
+        pui32Data[i] = AM_REGn(IOMSTR, ui32Module, FIFO);
+    }
+
+    //
+    // If there were leftovers, we'll copy them carefully. Pull the last word
+    // from the fifo (there should only be one) into a temporary buffer. Also,
+    // create an 8-bit pointer to help us copy the remaining bytes one at a
+    // time.
+    //
+    // Note: If the data buffer we were given was truly a word pointer like the
+    // definition requests, we wouldn't need to do this. It's possible to call
+    // this function with a re-cast or packed pointer instead though. If that
+    // happens, we want to be careful not to overwrite any data that might be
+    // sitting just past the end of the destination array.
+    //
+    if ( ui32Leftovers )
+    {
+        sTempBuffer.words[0] = AM_REGn(IOMSTR, ui32Module, FIFO);
+        pui8Data = (uint8_t *) (&pui32Data[i]);
+
+        //
+        // If we had leftover bytes, copy them out one byte at a time.
+        //
+        for ( j = 0; j < ui32Leftovers; j++ )
+        {
+            pui8Data[j] = sTempBuffer.bytes[j];
+        }
+    }
+
+    return ui32NumBytes;
+}
+
+//*****************************************************************************
+//
+//! @brief Check amount of empty space in the IOM fifo.
+//!
+//! @param ui32Module - Module number of the IOM whose fifo should be checked.
+//!
+//! Returns the number of bytes that could be written to the IOM fifo without
+//! causing an overflow.
+//!
+//! @return Amount of space available in the fifo (in bytes).
+//
+//*****************************************************************************
+uint8_t
+am_hal_iom_fifo_empty_slots(uint32_t ui32Module)
+{
+    uint32_t ui32MaxFifoSize;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+
+    ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2);
+
+    //
+    // Calculate the FIFO Remaining from the FIFO size. This will be different
+    // depending on whether the IOM is configured for half-duplex or
+    // full-duplex.
+    //
+    return (ui32MaxFifoSize - AM_BFRn(IOMSTR, ui32Module, FIFOPTR, FIFOSIZ)) & (~0x3);
+}
+
+//*****************************************************************************
+//
+//! @brief Check to see how much data is in the IOM fifo.
+//!
+//! @param ui32Module - Module number of the IOM whose fifo should be checked.
+//!
+//! Returns the number of bytes of data that are currently in the IOM fifo.
+//!
+//! @return Number of bytes in the fifo.
+//
+//*****************************************************************************
+uint8_t
+am_hal_iom_fifo_full_slots(uint32_t ui32Module)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+
+    return AM_BFRn(IOMSTR, ui32Module, FIFOPTR, FIFOSIZ);
+}
+
+//*****************************************************************************
+//
+//! @brief Wait for the current IOM command to complete.
+//!
+//! @param ui32Module - The module number of the IOM to use.
+//!
+//! This function polls until the IOM bus becomes idle.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_poll_complete(uint32_t ui32Module)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    //
+    // Poll on the IDLE bit in the status register.
+    //
+    while ( g_bIomBusy[ui32Module] );
+}
+
+//*****************************************************************************
+//
+//! @brief Returns the contents of the IOM status register.
+//!
+//! @param ui32Module IOM instance to check the status of.
+//!
+//! This function is just a wrapper around the IOM status register.
+//!
+//! @return 32-bit contents of IOM status register.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_status_get(uint32_t ui32Module)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+
+    return AM_REGn(IOMSTR, ui32Module, STATUS);
+}
+
+//*****************************************************************************
+//
+//! @brief Returns current error state of the IOM.
+//!
+//! @param ui32Module IOM instance to check the status of.
+//!
+//! This function returns status indicating whether the IOM has incurred any
+//! errors or not.
+//!
+//! @return 0 if all is well.
+//!         Otherwise error status as a bitmask of:
+//!             AM_HAL_IOM_ERR_INVALID_MODULE
+//!             AM_HAL_IOM_INT_ARB      Another master initiated an operation
+//!                                     simultaenously and the IOM lost.  Or
+//!                                     the IOM started an operation but found
+//!                                     SDA already low.
+//!             AM_HAL_IOM_INT_START    A START from another master detected.
+//!                                     SW must wait for STOP before continuing.
+//!             AM_HAL_IOM_INT_ICMD     Attempt to issue a CMD while another
+//!                                     CMD was already in progress, or issue a
+//!                                     non-zero-len write CMD with empty FIFO.
+//!             AM_HAL_IOM_INT_IACC     Attempt to read the FIFO on a write. Or
+//!                                     an attempt to write the FIFO on a read.
+//!             AM_HAL_IOM_INT_NAK      Expected ACK from slave not received.
+//!             AM_HAL_IOM_INT_FOVFL    Attempt to write the FIFO while full
+//!                                     (FIFOSIZ > 124).
+//!             AM_HAL_IOM_INT_FUNDFL   Attempt to read FIFO when empty (that is
+//!                                     FIFOSIZ < 4).
+//!         Note - see the datasheet text for full explanations of the INT errs.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_error_status_get(uint32_t ui32Module)
+{
+    uint32_t ui32intstat = 0;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        //
+        // AM_HAL_IOM_ERR_INVALID_MODULE is defined as an unused interrupt bit.
+        //
+        return AM_HAL_IOM_ERR_INVALID_MODULE;
+    }
+
+    if ( AM_REGn(IOMSTR, ui32Module, STATUS) & AM_REG_IOMSTR_STATUS_ERR_ERROR )
+    {
+        //
+        // The IOM is currently indicating an error condition.
+        // Let's figure out what is going on.
+        //
+        ui32intstat = AM_REGn(IOMSTR, ui32Module, INTSTAT);
+
+        //
+        // Filter out non-error bits.
+        //
+        ui32intstat &=  AM_REG_IOMSTR_INTSTAT_ARB_M     |
+                        AM_REG_IOMSTR_INTSTAT_START_M   |
+                        AM_REG_IOMSTR_INTSTAT_ICMD_M    |
+                        AM_REG_IOMSTR_INTSTAT_IACC_M    |
+                        AM_REG_IOMSTR_INTSTAT_NAK_M     |
+                        AM_REG_IOMSTR_INTSTAT_FOVFL_M   |
+                        AM_REG_IOMSTR_INTSTAT_FUNDFL_M;
+    }
+
+    return ui32intstat;
+}
+
+//*****************************************************************************
+//
+//! @brief Service interrupts from the IOM.
+//!
+//! @param ui32Status is the IOM interrupt status as returned from
+//! am_hal_iom_int_status_get()
+//!
+//! This function performs the necessary operations to facilitate non-blocking
+//! IOM writes and reads.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status)
+{
+    am_hal_iom_nb_buffer *psBuffer;
+    uint32_t ui32NumBytes;
+    uint32_t ui32SpaceInFifo;
+    uint32_t thresh;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    //
+    // Find the buffer information for the chosen IOM module.
+    //
+    psBuffer = &g_psIOMBuffers[ui32Module];
+
+    //
+    // Figure out what type of interrupt this was.
+    //
+    if ( ui32Status & AM_HAL_IOM_INT_CMDCMP )
+    {
+        //
+        // Need to mark IOM Free
+        //
+        g_bIomBusy[ui32Module] = false;
+
+        //
+        // If we're not in the middle of a non-blocking call right now, there's
+        // nothing for this routine to do.
+        //
+        if ( psBuffer->ui32State == BUFFER_IDLE )
+        {
+            return;
+        }
+
+        //
+        // If a command just completed, we need to transfer all available data.
+        //
+        if ( psBuffer->ui32State == BUFFER_RECEIVING )
+        {
+            //
+            // If we were receiving, we need to copy any remaining data out of
+            // the IOM FIFO before calling the callback.
+            //
+            ui32NumBytes = am_hal_iom_fifo_full_slots(ui32Module);
+            am_hal_iom_fifo_read(ui32Module, psBuffer->pui32Data, ui32NumBytes);
+        }
+
+        //
+        // A command complete event also means that we've already transferred
+        // all of the data we need, so we can mark the data buffer as IDLE.
+        //
+        psBuffer->ui32State = BUFFER_IDLE;
+
+        //
+        // If we have a callback, call it now.
+        //
+        if ( psBuffer->pfnCallback )
+        {
+            psBuffer->pfnCallback();
+        }
+    }
+    else if ( ui32Status & AM_HAL_IOM_INT_THR )
+    {
+        //
+        // If we're not in the middle of a non-blocking call right now, there's
+        // nothing for this routine to do.
+        //
+        if ( psBuffer->ui32State == BUFFER_IDLE )
+        {
+            return;
+        }
+        //
+        // If we received a threshold event in the middle of a command, we need
+        // to transfer data.
+        //
+        if ( psBuffer->ui32State == BUFFER_SENDING )
+        {
+            thresh = AM_BFRn(IOMSTR, ui32Module, FIFOTHR, FIFOWTHR);
+            do
+            {
+                ui32SpaceInFifo = am_hal_iom_fifo_empty_slots(ui32Module);
+
+                //
+                // Figure out how much data we can send.
+                //
+                if ( psBuffer->ui32BytesLeft <= ui32SpaceInFifo )
+                {
+                    //
+                    // If the whole transfer will fit in the fifo, send it all.
+                    //
+                    ui32NumBytes = psBuffer->ui32BytesLeft;
+                }
+                else
+                {
+                    //
+                    // If the transfer won't fit in the fifo completely, send as
+                    // much as we can (rounded down to a multiple of four bytes).
+                    //
+                    ui32NumBytes = ui32SpaceInFifo;
+                }
+
+                //
+                // Perform the transfer.
+                //
+                am_hal_iom_fifo_write(ui32Module, psBuffer->pui32Data, ui32NumBytes);
+
+                // Clear any spurious THR interrupt that might have got raised
+                // while we were adding data to FIFO
+                AM_BFWn(IOMSTR, ui32Module, INTCLR, THR, 1);
+                //
+                // Update the pointer and the byte counter.
+                //
+                psBuffer->ui32BytesLeft -= ui32NumBytes;
+                psBuffer->pui32Data += (ui32NumBytes / 4);
+
+                if ( 0 == psBuffer->ui32BytesLeft )
+                {
+                    //
+                    // Done with this transaction
+                    //
+                    break;
+                }
+            } while ( am_hal_iom_fifo_full_slots(ui32Module) <= thresh );
+        }
+        else
+        {
+            thresh = AM_BFRn(IOMSTR, ui32Module, FIFOTHR, FIFORTHR);
+            while ( (ui32NumBytes = am_hal_iom_fifo_full_slots(ui32Module)) >= thresh )
+            {
+                //
+                // If we get here, we're in the middle of a read. Transfer as much
+                // data as possible out of the FIFO and into our buffer.
+                //
+                if ( ui32NumBytes == psBuffer->ui32BytesLeft )
+                {
+                    //
+                    // If the fifo contains our entire message, just copy the whole
+                    // thing out.
+                    //
+                    am_hal_iom_fifo_read(ui32Module, psBuffer->pui32Data,
+                                         psBuffer->ui32BytesLeft);
+
+                    break;
+                }
+                else if ( ui32NumBytes >= 4 )
+                {
+                    //
+                    // If the fifo has at least one 32-bit word in it, copy out the
+                    // biggest block we can.
+                    //
+                    ui32NumBytes = (ui32NumBytes & (~0x3));
+
+                    am_hal_iom_fifo_read(ui32Module, psBuffer->pui32Data, ui32NumBytes);
+
+                    //
+                    // Update the pointer and the byte counter.
+                    //
+                    psBuffer->ui32BytesLeft -= ui32NumBytes;
+                    psBuffer->pui32Data += (ui32NumBytes / 4);
+
+                    // Clear any spurious THR interrupt that might have got raised
+                    // while we were reading the data from FIFO
+                    AM_BFWn(IOMSTR, ui32Module, INTCLR, THR, 1);
+                }
+            }
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Initialize the IOM queue system.
+//!
+//! @param ui32Module - IOM module to be initialized for queue transfers.
+//! @param psQueueMemory - Memory to be used for queueing IOM transfers.
+//! @param ui32QueueMemSize - Size of the queue memory.
+//!
+//! This function prepares the selected IOM interface for use with the IOM
+//! queue system. The IOM queue system allows the caller to start multiple IOM
+//! transfers in a non-blocking way. In order to do this, the HAL requires some
+//! amount of memory dedicated to keeping track of IOM transactions before they
+//! can be sent to the hardware registers. This function tells the HAL what
+//! memory it should use for this purpose. For more information on the IOM
+//! queue interface, please see the documentation for
+//! am_hal_iom_queue_spi_write().
+//!
+//! @note This function only needs to be called once (per module), but it must
+//! be called before any other am_hal_iom_queue function.
+//!
+//! @note Each IOM module will need its own working space. If you intend to use
+//! the queueing mechanism with more than one IOM module, you will need to
+//! provide separate queue memory for each module.
+//!
+//! Example usage:
+//!
+//! @code
+//!
+//! //
+//! // Declare an array to be used for IOM queue transactions. This array will
+//! // be big enough to handle 32 IOM transactions.
+//! //
+//! am_hal_iom_queue_entry_t g_psQueueMemory[32];
+//!
+//! //
+//! // Attach the IOM0 queue system to the memory we just allocated.
+//! //
+//! am_hal_iom_queue_init(0, g_psQueueMemory, sizeof(g_psQueueMemory));
+//!
+//! @endcode
+//
+//*****************************************************************************
+void
+am_hal_iom_queue_init(uint32_t ui32Module, am_hal_iom_queue_entry_t *psQueueMemory,
+                      uint32_t ui32QueueMemSize)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    am_hal_queue_init(&g_psIOMQueue[ui32Module], psQueueMemory,
+                      sizeof(am_hal_iom_queue_entry_t), ui32QueueMemSize);
+}
+
+//*****************************************************************************
+//
+//! @brief Check to see how many transactions are in the queue.
+//!
+//! @param ui32Module Module number for the queue to check
+//!
+//! This function will check to see how many transactions are in the IOM queue
+//! for the selected IOM module.
+//!
+//! @return Number of transactions in the queue.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_queue_length_get(uint32_t ui32Module)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+
+    return am_hal_queue_data_left(&g_psIOMQueue[ui32Module]);
+}
+
+//*****************************************************************************
+//
+//! @brief Executes the next operation in the IOM queue.
+//!
+//! @param ui32ModuleNum - Module number for the IOM to use.
+//!
+//! This function checks the IOM queue to see if there are any remaining
+//! transactions. If so, it will start the next available transaction in a
+//! non-blocking way.
+//!
+//! @note This function is called automatically by am_hal_iom_queue_service().
+//! You should not call this function standalone in a normal application.
+//
+//*****************************************************************************
+void
+am_hal_iom_queue_start_next_msg(uint32_t ui32Module)
+{
+  am_hal_iom_queue_entry_t sIOMTransaction = {0};
+
+    uint32_t ui32ChipSelect;
+    uint32_t *pui32Data;
+    uint32_t ui32NumBytes;
+    uint32_t ui32Options;
+    am_hal_iom_callback_t pfnCallback;
+
+    uint32_t ui32Critical;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    //
+    // Start a critical section.
+    //
+    ui32Critical = am_hal_interrupt_master_disable();
+
+    //
+    // Try to get the next IOM operation from the queue.
+    //
+    if ( am_hal_queue_item_get(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) )
+    {
+        //
+        // Read the operation parameters
+        //
+        ui32ChipSelect = sIOMTransaction.ui32ChipSelect;
+        pui32Data = sIOMTransaction.pui32Data;
+        ui32NumBytes = sIOMTransaction.ui32NumBytes;
+        ui32Options = sIOMTransaction.ui32Options;
+        pfnCallback = sIOMTransaction.pfnCallback;
+
+        //
+        // Figure out if this was a SPI or I2C write or read, and call the
+        // appropriate non-blocking function.
+        //
+        switch ( sIOMTransaction.ui32Operation )
+        {
+            case AM_HAL_IOM_QUEUE_SPI_WRITE:
+                am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data,
+                                        ui32NumBytes, ui32Options, pfnCallback);
+                break;
+
+            case AM_HAL_IOM_QUEUE_SPI_READ:
+                am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data,
+                                       ui32NumBytes, ui32Options, pfnCallback);
+                break;
+
+            case AM_HAL_IOM_QUEUE_I2C_WRITE:
+                am_hal_iom_i2c_write_nb(ui32Module, ui32ChipSelect, pui32Data,
+                                        ui32NumBytes, ui32Options, pfnCallback);
+                break;
+
+            case AM_HAL_IOM_QUEUE_I2C_READ:
+                am_hal_iom_i2c_read_nb(ui32Module, ui32ChipSelect, pui32Data,
+                                       ui32NumBytes, ui32Options, pfnCallback);
+                break;
+        }
+    }
+
+    //
+    // Exit the critical section.
+    //
+    am_hal_interrupt_master_set(ui32Critical);
+}
+
+//*****************************************************************************
+//
+//! @brief Send a SPI frame using the IOM queue.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32ChipSelect - Chip-select number for this transaction.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional SPI transfer options.
+//!
+//! This function performs SPI writes to a selected SPI device.
+//!
+//! This function call is a queued implementation. It will write as much
+//! data to the FIFO as possible immediately, store a pointer to the remaining
+//! data, start the transfer on the bus, and then immediately return. If the
+//! FIFO is already in use, this function will save its arguments to the IOM
+//! queue and execute the transaction when the FIFO becomes available.
+//!
+//! The caller will need to make sure that \e am_hal_iom_queue_service() is
+//! called for IOM FIFO interrupt events and "command complete" interrupt
+//! events. The \e am_hal_iom_queue_service() function will refill the FIFO as
+//! necessary and call the \e pfnCallback function when the transaction is
+//! finished.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui8Data array.
+//
+//*****************************************************************************
+void
+am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                           uint32_t *pui32Data, uint32_t ui32NumBytes,
+                           uint32_t ui32Options, am_hal_iom_callback_t pfnCallback)
+{
+    uint32_t ui32Critical;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Start a critical section.
+    //
+    ui32Critical = am_hal_interrupt_master_disable();
+
+    //
+    // Check to see if we need to use the queue. If the IOM is idle, and
+    // there's nothing in the queue already, we can go ahead and start the
+    // transaction in the physical IOM. Need to check for the g_bIomBusy to
+    // avoid a race condition where IDLE is set - but the command complete
+    // for previous transaction has not been processed yet
+    //
+    if ( (g_bIomBusy[ui32Module] == false) &&
+        am_hal_queue_empty(&g_psIOMQueue[ui32Module]) )
+    {
+        //
+        // Send the packet.
+        //
+        am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data,
+                                ui32NumBytes, ui32Options, pfnCallback);
+    }
+    else
+    {
+        //
+        // Otherwise, we'll build a transaction structure and add it to the queue.
+        //
+        am_hal_iom_queue_entry_t sIOMTransaction;
+
+        sIOMTransaction.ui32Operation = AM_HAL_IOM_QUEUE_SPI_WRITE;
+        sIOMTransaction.ui32Module = ui32Module;
+        sIOMTransaction.ui32ChipSelect = ui32ChipSelect;
+        sIOMTransaction.pui32Data = pui32Data;
+        sIOMTransaction.ui32NumBytes = ui32NumBytes;
+        sIOMTransaction.ui32Options = ui32Options;
+        sIOMTransaction.pfnCallback = pfnCallback;
+
+        //
+        // Make sure the item actually makes it into the queue
+        //
+        if ( am_hal_queue_item_add(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) == false )
+        {
+            //
+            // Didn't have enough memory.
+            //
+            am_hal_debug_assert_msg(0,
+                                    "The IOM queue is full. Allocate more"
+                                    "memory to the IOM queue, or allow it more"
+                                    "time to empty between transactions.");
+        }
+    }
+
+    //
+    // Exit the critical section.
+    //
+    am_hal_interrupt_master_set(ui32Critical);
+}
+
+//*****************************************************************************
+//
+//! @brief Read a SPI frame using the IOM queue.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32ChipSelect - Chip select number for this transaction.
+//! @param pui32Data - Pointer to the array where received bytes should go.
+//! @param ui32NumBytes - Number of bytes to read.
+//! @param ui32Options - Additional SPI transfer options.
+//!
+//! This function performs SPI reads to a selected SPI device.
+//!
+//! This function call is a queued implementation. It will write as much
+//! data to the FIFO as possible immediately, store a pointer to the remaining
+//! data, start the transfer on the bus, and then immediately return. If the
+//! FIFO is already in use, this function will save its arguments to the IOM
+//! queue and execute the transaction when the FIFO becomes available.
+//!
+//! The caller will need to make sure that \e am_hal_iom_queue_service() is
+//! called for IOM FIFO interrupt events and "command complete" interrupt
+//! events. The \e am_hal_iom_queue_service() function will empty the FIFO as
+//! necessary and call the \e pfnCallback function when the transaction is
+//! finished.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui8Data array.
+//
+//*****************************************************************************
+void
+am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                          uint32_t *pui32Data, uint32_t ui32NumBytes,
+                          uint32_t ui32Options, am_hal_iom_callback_t pfnCallback)
+{
+    uint32_t ui32Critical;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    // Start a critical section.
+    //
+    ui32Critical = am_hal_interrupt_master_disable();
+
+    //
+    // Check to see if we need to use the queue. If the IOM is idle, and
+    // there's nothing in the queue already, we can go ahead and start the
+    // transaction in the physical IOM. Need to check for the g_bIomBusy to
+    // avoid a race condition where IDLE is set - but the command complete
+    // for previous transaction has not been processed yet
+    //
+    if ( (g_bIomBusy[ui32Module] == false) &&
+        am_hal_queue_empty(&g_psIOMQueue[ui32Module]) )
+    {
+        //
+        // Send the packet.
+        //
+        am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data,
+                               ui32NumBytes, ui32Options, pfnCallback);
+    }
+    else
+    {
+        //
+        // Otherwise, we'll build a transaction structure and add it to the queue.
+        //
+        am_hal_iom_queue_entry_t sIOMTransaction;
+
+        sIOMTransaction.ui32Operation = AM_HAL_IOM_QUEUE_SPI_READ;
+        sIOMTransaction.ui32Module = ui32Module;
+        sIOMTransaction.ui32ChipSelect = ui32ChipSelect;
+        sIOMTransaction.pui32Data = pui32Data;
+        sIOMTransaction.ui32NumBytes = ui32NumBytes;
+        sIOMTransaction.ui32Options = ui32Options;
+        sIOMTransaction.pfnCallback = pfnCallback;
+
+        //
+        // Make sure the item actually makes it into the queue
+        //
+        if ( am_hal_queue_item_add(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) == false )
+        {
+            //
+            // Didn't have enough memory.
+            //
+            am_hal_debug_assert_msg(0,
+                                    "The IOM queue is full. Allocate more"
+                                    "memory to the IOM queue, or allow it more"
+                                    "time to empty between transactions.");
+        }
+    }
+
+    //
+    // Exit the critical section.
+    //
+    am_hal_interrupt_master_set(ui32Critical);
+}
+
+//*****************************************************************************
+//
+//! @brief Send an I2C frame using the IOM queue.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32BusAddress - I2C address of the target device.
+//! @param pui32Data - Pointer to the bytes that will be sent.
+//! @param ui32NumBytes - Number of bytes to send.
+//! @param ui32Options - Additional I2C transfer options.
+//!
+//! This function performs I2C writes to a selected I2C device.
+//!
+//! This function call is a queued implementation. It will write as much
+//! data to the FIFO as possible immediately, store a pointer to the remaining
+//! data, start the transfer on the bus, and then immediately return. If the
+//! FIFO is already in use, this function will save its arguments to the IOM
+//! queue and execute the transaction when the FIFO becomes available.
+//!
+//! The caller will need to make sure that \e am_hal_iom_queue_service() is
+//! called for IOM FIFO interrupt events and "command complete" interrupt
+//! events. The \e am_hal_iom_queue_service() function will refill the FIFO as
+//! necessary and call the \e pfnCallback function when the transaction is
+//! finished.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui8Data array.
+//
+//*****************************************************************************
+void
+am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress,
+                           uint32_t *pui32Data, uint32_t ui32NumBytes,
+                           uint32_t ui32Options, am_hal_iom_callback_t pfnCallback)
+{
+    uint32_t ui32Critical;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Start a critical section.
+    //
+    ui32Critical = am_hal_interrupt_master_disable();
+
+    //
+    // Check to see if we need to use the queue. If the IOM is idle, and
+    // there's nothing in the queue already, we can go ahead and start the
+    // transaction in the physical IOM. Need to check for the g_bIomBusy to
+    // avoid a race condition where IDLE is set - but the command complete
+    // for previous transaction has not been processed yet
+    //
+    if ( (g_bIomBusy[ui32Module] == false) &&
+        am_hal_queue_empty(&g_psIOMQueue[ui32Module]) )
+    {
+        //
+        // Send the packet.
+        //
+        am_hal_iom_i2c_write_nb(ui32Module, ui32BusAddress, pui32Data,
+                                ui32NumBytes, ui32Options, pfnCallback);
+    }
+    else
+    {
+        //
+        // Otherwise, we'll build a transaction structure and add it to the queue.
+        //
+        am_hal_iom_queue_entry_t sIOMTransaction;
+
+        sIOMTransaction.ui32Operation = AM_HAL_IOM_QUEUE_I2C_WRITE;
+        sIOMTransaction.ui32Module = ui32Module;
+        sIOMTransaction.ui32ChipSelect = ui32BusAddress;
+        sIOMTransaction.pui32Data = pui32Data;
+        sIOMTransaction.ui32NumBytes = ui32NumBytes;
+        sIOMTransaction.ui32Options = ui32Options;
+        sIOMTransaction.pfnCallback = pfnCallback;
+
+        //
+        // Make sure the item actually makes it into the queue
+        //
+        if ( am_hal_queue_item_add(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) == false )
+        {
+            //
+            // Didn't have enough memory.
+            //
+            am_hal_debug_assert_msg(0,
+                                    "The IOM queue is full. Allocate more"
+                                    "memory to the IOM queue, or allow it more"
+                                    "time to empty between transactions.");
+        }
+    }
+
+    //
+    // Exit the critical section.
+    //
+    am_hal_interrupt_master_set(ui32Critical);
+}
+
+//*****************************************************************************
+//
+//! @brief Read a I2C frame using the IOM queue.
+//!
+//! @param ui32Module - Module number for the IOM
+//! @param ui32BusAddress - I2C address of the target device.
+//! @param pui32Data - Pointer to the array where received bytes should go.
+//! @param ui32NumBytes - Number of bytes to read.
+//! @param ui32Options - Additional I2C transfer options.
+//!
+//! This function performs I2C reads to a selected I2C device.
+//!
+//! This function call is a queued implementation. It will write as much
+//! data to the FIFO as possible immediately, store a pointer to the remaining
+//! data, start the transfer on the bus, and then immediately return. If the
+//! FIFO is already in use, this function will save its arguments to the IOM
+//! queue and execute the transaction when the FIFO becomes available.
+//!
+//! The caller will need to make sure that \e am_hal_iom_queue_service() is
+//! called for IOM FIFO interrupt events and "command complete" interrupt
+//! events. The \e am_hal_iom_queue_service() function will empty the FIFO as
+//! necessary and call the \e pfnCallback function when the transaction is
+//! finished.
+//!
+//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words.
+//! This means that you will need to byte-pack the \e pui32Data array with the
+//! data you intend to send over the interface. One easy way to do this is to
+//! declare the array as a 32-bit integer array, but use an 8-bit pointer to
+//! put your actual data into the array. If there are not enough bytes in your
+//! desired message to completely fill the last 32-bit word, you may pad that
+//! last word with bytes of any value. The IOM hardware will only read the
+//! first \e ui32NumBytes in the \e pui8Data array.
+//
+//*****************************************************************************
+void
+am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress,
+                          uint32_t *pui32Data, uint32_t ui32NumBytes,
+                          uint32_t ui32Options, am_hal_iom_callback_t pfnCallback)
+{
+    uint32_t ui32Critical;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+    am_hal_debug_assert_msg(ui32NumBytes > 0,
+                            "Trying to do a 0 byte transaction");
+
+    //
+    // Start a critical section.
+    //
+    ui32Critical = am_hal_interrupt_master_disable();
+
+    //
+    // Check to see if we need to use the queue. If the IOM is idle, and
+    // there's nothing in the queue already, we can go ahead and start the
+    // transaction in the physical IOM. Need to check for the g_bIomBusy to
+    // avoid a race condition where IDLE is set - but the command complete
+    // for previous transaction has not been processed yet
+    //
+    if ( (g_bIomBusy[ui32Module] == false) &&
+        am_hal_queue_empty(&g_psIOMQueue[ui32Module]) )
+    {
+        //
+        // Send the packet.
+        //
+        am_hal_iom_i2c_read_nb(ui32Module, ui32BusAddress, pui32Data,
+                               ui32NumBytes, ui32Options, pfnCallback);
+    }
+    else
+    {
+        //
+        // Otherwise, we'll build a transaction structure and add it to the queue.
+        //
+        am_hal_iom_queue_entry_t sIOMTransaction;
+
+        sIOMTransaction.ui32Operation = AM_HAL_IOM_QUEUE_I2C_READ;
+        sIOMTransaction.ui32Module = ui32Module;
+        sIOMTransaction.ui32ChipSelect = ui32BusAddress;
+        sIOMTransaction.pui32Data = pui32Data;
+        sIOMTransaction.ui32NumBytes = ui32NumBytes;
+        sIOMTransaction.ui32Options = ui32Options;
+        sIOMTransaction.pfnCallback = pfnCallback;
+
+        //
+        // Make sure the item actually makes it into the queue
+        //
+        if ( am_hal_queue_item_add(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) == false )
+        {
+            //
+            // Didn't have enough memory.
+            //
+            am_hal_debug_assert_msg(0, "The IOM queue is full. Allocate more"
+                                       "memory to the IOM queue, or allow it more"
+                                       "time to empty between transactions.");
+        }
+    }
+
+    //
+    // Exit the critical section.
+    //
+    am_hal_interrupt_master_set(ui32Critical);
+}
+
+//*****************************************************************************
+//
+//! @brief "Block" until the queue of IOM transactions is over.
+//!
+//! @param ui32Module - Module number for the IOM.
+//!
+//! This function will sleep the core block until the queue for the selected
+//! IOM is empty. This is mainly useful for non-RTOS applications where the
+//! caller needs to know that a certain IOM transaction is complete before
+//! continuing with the main program flow.
+//!
+//! @note This function will put the core to sleep while it waits for the
+//! queued IOM transactions to complete. This will save power, in most
+//! situations, but it may not be the best option in all cases. \e Do \e not
+//! call this function from interrupt context (the core may not wake up again).
+//! \e Be \e careful using this function from an RTOS task (many RTOS
+//! implementations use hardware interrupts to switch contexts, and most RTOS
+//! implementations expect to control sleep behavior).
+//
+//*****************************************************************************
+void
+am_hal_iom_sleeping_queue_flush(uint32_t ui32Module)
+{
+    bool bWaiting = true;
+    uint32_t ui32Critical;
+
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    //
+    // Loop forever waiting for the IOM to be idle and the queue to be empty.
+    //
+    while ( bWaiting )
+    {
+        //
+        // Start a critical section.
+        //
+        ui32Critical = am_hal_interrupt_master_disable();
+
+        //
+        // Check the queue and the IOM itself.
+        //
+        if ( (g_bIomBusy[ui32Module] == false) &&
+            am_hal_queue_empty(&g_psIOMQueue[ui32Module]) )
+        {
+            //
+            // If the queue is empty and the IOM is idle, we can go ahead and
+            // return.
+            //
+            bWaiting = false;
+        }
+        else
+        {
+            //
+            // Otherwise, we should sleep until the interface is actually free.
+            //
+            am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_NORMAL);
+        }
+
+        //
+        // End the critical section.
+        //
+        am_hal_interrupt_master_set(ui32Critical);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Service IOM transaction queue.
+//!
+//! @param ui32Module - Module number for the IOM to be used.
+//! @param ui32Status - Interrupt status bits for the IOM module being used.
+//!
+//! This function handles the operation of FIFOs and the IOM queue during
+//! queued IOM transactions. If you are using \e am_hal_iom_queue_spi_write()
+//! or similar functions, you will need to call this function in your interrupt
+//! handler.
+//!
+//! @note This interrupt service routine relies on the user to enable the IOM
+//! interrupts for FIFO threshold and CMD complete.
+//!
+//! Example:
+//!
+//! @code
+//! void
+//! am_iomaster0_isr(void)
+//! {
+//!     uint32_t ui32Status;
+//!
+//!     //
+//!     // Check to see which interrupt caused us to enter the ISR.
+//!     //
+//!     ui32Status = am_hal_iom_int_status(0, true);
+//!
+//!     //
+//!     // Fill or empty the FIFO, and either continue the current operation or
+//!     // start the next one in the queue. If there was a callback, it will be
+//!     // called here.
+//!     //
+//!     am_hal_iom_queue_service(0, ui32Status);
+//!
+//!     //
+//!     // Clear the interrupts before leaving the ISR.
+//!     //
+//!     am_hal_iom_int_clear(ui32Status);
+//! }
+//! @endcode
+//!
+//! @return
+//
+//*****************************************************************************
+void
+am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Status)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    //
+    // Service the FIFOs in case this was a threshold interrupt.
+    //
+    am_hal_iom_int_service(ui32Module, ui32Status);
+
+    //
+    // If the last interrupt was a "command complete", then the IOM should be
+    // idle already or very soon. Make absolutely sure that the IOM is not in
+    // use, and then start the next transaction in the queue.
+    //
+    if ( ui32Status & AM_HAL_IOM_INT_CMDCMP )
+    {
+        if ( g_psIOMQueue[ui32Module].pui8Data != NULL )
+        {
+            am_hal_iom_queue_start_next_msg(ui32Module);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Enable selected IOM Interrupts.
+//!
+//! @param ui32Module - Module number.
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_iom.h
+//!
+//! Use this function to enable the IOM interrupts.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_iom_int_enable(uint32_t ui32Module, uint32_t ui32Interrupt)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    AM_REGn(IOMSTR, ui32Module, INTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return the enabled IOM Interrupts.
+//!
+//! @param ui32Module - Module number.
+//!
+//! Use this function to return all enabled IOM interrupts.
+//!
+//! @return all enabled IOM interrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_int_enable_get(uint32_t ui32Module)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+
+    return AM_REGn(IOMSTR, ui32Module, INTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable selected IOM Interrupts.
+//!
+//! @param ui32Module - Module number.
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_iom.h
+//!
+//! Use this function to disable the IOM interrupts.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_iom_int_disable(uint32_t ui32Module, uint32_t ui32Interrupt)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    AM_REGn(IOMSTR, ui32Module, INTEN) &= ~ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Clear selected IOM Interrupts.
+//!
+//! @param ui32Module - Module number.
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_iom.h
+//!
+//! Use this function to clear the IOM interrupts.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_iom_int_clear(uint32_t ui32Module, uint32_t ui32Interrupt)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    AM_REGn(IOMSTR, ui32Module, INTCLR) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Set selected IOM Interrupts.
+//!
+//! @param ui32Module - Module number.
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_iom.h
+//!
+//! Use this function to set the IOM interrupts.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_iom_int_set(uint32_t ui32Module, uint32_t ui32Interrupt)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return;
+    }
+
+    AM_REGn(IOMSTR, ui32Module, INTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return the IOM Interrupt status.
+//!
+//! @param ui32Module - Module number.
+//! @param bEnabledOnly - return only the enabled interrupts.
+//!
+//! Use this function to get the IOM interrupt status.
+//!
+//! @return interrupt status
+//
+//*****************************************************************************
+uint32_t
+am_hal_iom_int_status_get(uint32_t ui32Module, bool bEnabledOnly)
+{
+    //
+    // Validate parameters
+    //
+    if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES )
+    {
+        return 0;
+    }
+
+    if ( bEnabledOnly )
+    {
+        uint32_t u32RetVal = AM_REGn(IOMSTR, ui32Module, INTSTAT);
+        return u32RetVal & AM_REGn(IOMSTR, ui32Module, INTEN);
+    }
+    else
+    {
+        return AM_REGn(IOMSTR, ui32Module, INTSTAT);
+    }
+}
+
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h
new file mode 100644
index 0000000000..e5a450f15c
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h
@@ -0,0 +1,559 @@
+//*****************************************************************************
+//
+//  am_hal_iom.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the IO Master module
+//!
+//! @addtogroup iom2 IO Master (SPI/I2C)
+//! @ingroup apollo2hal
+//! @{
+
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_HAL_IOM_H
+#define AM_HAL_IOM_H
+
+//*****************************************************************************
+//
+// Macro definitions
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! @name IOM Clock Frequencies
+//! @brief Macro definitions for common SPI and I2C clock frequencies.
+//!
+//! These macros may be used with the ui32ClockFrequency member of the
+//! am_hal_iom_config_t structure to set the clock frequency of the serial
+//! interfaces.
+//!
+//! This list of frequencies is not exhaustive by any means. If your desired
+//! frequency is not in this list, simply set ui32ClockFrequency to the
+//! desired frequency (in Hz) when calling am_hal_iom_config().
+//
+//*****************************************************************************
+#define AM_HAL_IOM_24MHZ    24000000
+#define AM_HAL_IOM_16MHZ    16000000
+#define AM_HAL_IOM_12MHZ    12000000
+#define AM_HAL_IOM_8MHZ      8000000
+#define AM_HAL_IOM_6MHZ      6000000
+#define AM_HAL_IOM_4MHZ      4000000
+#define AM_HAL_IOM_3MHZ      3000000
+#define AM_HAL_IOM_2MHZ      2000000
+#define AM_HAL_IOM_1_5MHZ    1500000
+#define AM_HAL_IOM_1MHZ      1000000
+#define AM_HAL_IOM_750KHZ     750000
+#define AM_HAL_IOM_500KHZ     500000
+#define AM_HAL_IOM_400KHZ     400000
+#define AM_HAL_IOM_375KHZ     375000
+#define AM_HAL_IOM_250KHZ     250000
+#define AM_HAL_IOM_125KHZ     125000
+#define AM_HAL_IOM_100KHZ     100000
+#define AM_HAL_IOM_50KHZ       50000
+#define AM_HAL_IOM_10KHZ       10000
+
+// Hardware FIFO Size
+#define AM_HAL_IOM_MAX_FIFO_SIZE    128
+
+//*****************************************************************************
+//
+//! @name IOM Physical Protocols
+//! @brief Macro Definitions for general IOM configuration.
+//!
+//! These macros may be used with the am_hal_iom_config_t structure to set the
+//! operating parameters of each serial IO master module. Choose SPIMODE to
+//! select the SPI interface, or I2CMODE to select the I2C interface.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOM_SPIMODE                  AM_REG_IOMSTR_CFG_IFCSEL(1)
+#define AM_HAL_IOM_I2CMODE                  AM_REG_IOMSTR_CFG_IFCSEL(0)
+//! @}
+
+//*****************************************************************************
+//
+//! @name IOM Operations
+//! @brief Macro definitions used for ui32Operation parameters.
+//!
+//! These macros may be used to specify which action an IOM command will
+//! execute. The 'OFFSET' operations will cause the IOM hardware to transmit the
+//! provided 1-byte 'offset' before executing the rest of the command.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOM_WRITE                    0x00000000
+#define AM_HAL_IOM_READ                     0x80000000
+//! @}
+
+//*****************************************************************************
+//
+//! @name Command Options
+//! @brief Macro definitions used for ui32Options parameters.
+//!
+//! These macros are all related to SPI or I2C command words. They can be used
+//! to set specific options on a per-transaction basis.
+//!
+//! - CS_LOW - Do not raise the CS signal at the end of this SPI command.
+//! - NO_STOP - Do not release the I2C bus with a STOP bit after this command.
+//! - LSB_FIRST - Reverse the payload bits of this command.
+//! - 10BIT_ADDRESS - (I2C only) use a 10-bit I2C address protocol.
+//! - RAW - Don't use an offset byte.
+//! - OFFSET() - Send this 1-byte offset as the first byte of the transaction.
+//!   This can be used to access "registers" in external I2C devices, or add a
+//!   1-byte write to the beginning of a SPI write or read command. See
+//!   "normal mode" operation in the I2C/SPI Master section of the datasheet
+//!   for more information on this parameter.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOM_CS_LOW                   0x10000000
+#define AM_HAL_IOM_NO_STOP                  0x10000000
+#define AM_HAL_IOM_LSB_FIRST                0x08000000
+#define AM_HAL_IOM_10BIT_ADDRESS            0x04000000
+#define AM_HAL_IOM_RAW                      0x40000000
+#define AM_HAL_IOM_OFFSET(n)                (((n) << 8) & 0x0000FF00)
+//! @}
+
+//*****************************************************************************
+//
+//! @name IOM Interrupts
+//! @brief Macro definitions for IOM interrupt status bits.
+//!
+//! These macros correspond to the bits in the IOM interrupt status register.
+//! They may be used with any of the \e am_hal_iom_int_x() functions.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOM_INT_ARB                  AM_REG_IOMSTR_INTEN_ARB_M
+#define AM_HAL_IOM_INT_STOP                 AM_REG_IOMSTR_INTEN_STOP_M
+#define AM_HAL_IOM_INT_START                AM_REG_IOMSTR_INTEN_START_M
+#define AM_HAL_IOM_INT_ICMD                 AM_REG_IOMSTR_INTEN_ICMD_M
+#define AM_HAL_IOM_INT_IACC                 AM_REG_IOMSTR_INTEN_IACC_M
+#define AM_HAL_IOM_INT_WTLEN                AM_REG_IOMSTR_INTEN_WTLEN_M
+#define AM_HAL_IOM_INT_NAK                  AM_REG_IOMSTR_INTEN_NAK_M
+#define AM_HAL_IOM_INT_FOVFL                AM_REG_IOMSTR_INTEN_FOVFL_M
+#define AM_HAL_IOM_INT_FUNDFL               AM_REG_IOMSTR_INTEN_FUNDFL_M
+#define AM_HAL_IOM_INT_THR                  AM_REG_IOMSTR_INTEN_THR_M
+#define AM_HAL_IOM_INT_CMDCMP               AM_REG_IOMSTR_INTEN_CMDCMP_M
+//! @}
+
+//*****************************************************************************
+//
+//! @name IOM function errors
+//! @brief Return values for IOM HAL function errors, such as with the function
+//!        am_hal_iom_error_status_get().
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOM_ERR_INVALID_MODULE       (1 << 30)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Software IOM modules
+//! @brief Macro definitions for using the software I2C interface.
+//!
+//! Use this macro as the module number for standard IOM functions to emulate
+//! them using the bit-banged i2c interface.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOM_I2CBB_MODULE             AM_REG_IOMSTR_NUM_MODULES
+//! @}
+
+//*****************************************************************************
+//
+//! @brief Union type for a word-aligned, byte-addressable array.
+//!
+//! This is a convenience macro that may be used to define byte-addressable
+//! arrays with 32-bit alignment. This allows the programmer to define SPI or
+//! I2C transactions as a series of 8-bit values, but also write them to the
+//! IOM FIFO efficiently as a series of 32-bit values.
+//!
+//! Example usage:
+//!
+//! @code
+//!     //
+//!     // Declare a buffer array with at least 3-bytes worth of space.
+//!     //
+//!     am_hal_iom_buffer(3) sBuffer;
+//!
+//!     //
+//!     // Populate the buffer with a 3-byte command.
+//!     //
+//!     sBuffer.bytes[0] = 's';
+//!     sBuffer.bytes[1] = 'p';
+//!     sBuffer.bytes[2] = 'i';
+//!
+//!     //
+//!     // Send the buffer over the spi interface.
+//!     //
+//!     am_hal_iom_spi_write(psDevice, sBuffer.words, 3, 0);
+//!
+//! @endcode
+//
+//*****************************************************************************
+#define am_hal_iom_buffer(A)                                                  \
+    union                                                                     \
+    {                                                                         \
+        uint32_t words[(A + 3) >> 2];                                         \
+        uint8_t bytes[A];                                                     \
+    }
+
+//*****************************************************************************
+//
+//! @brief Configuration structure for the IO master module.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! @brief Selects the physical protocol for the IO master module. Choose
+    //! either AM_HAL_IOM_SPIMODE or AM_HAL_IOM_I2CMODE.
+    //
+    uint32_t ui32InterfaceMode;
+
+    //
+    //! @brief Selects the output clock frequency for SPI or I2C mode. Choose
+    //! one of the AM_HAL_IOM_nMHZ or AM_HAL_IOM_nKHZ macros.
+    //
+    uint32_t ui32ClockFrequency;
+
+    //
+    //! Select the SPI clock phase (unused in I2C mode).
+    //
+    bool bSPHA;
+
+    //
+    //! Select the SPI clock polarity (unused in I2C mode).
+    //
+    bool bSPOL;
+
+    //
+    //! @brief Select the FIFO write threshold.
+    //!
+    //! The IOM controller will generate a processor interrupt when the number
+    //! of entries in the FIFO goes *below* this number.
+    //
+    uint8_t ui8WriteThreshold;
+
+    //
+    //! @brief Select the FIFO read threshold.
+    //!
+    //! The IOM controller will generate a processor interrupt when the number
+    //! of entries in the FIFO grows *larger* than this number.
+    //
+    uint8_t ui8ReadThreshold;
+    
+}
+am_hal_iom_config_t;
+
+//*****************************************************************************
+//
+//! Configuration structure for an individual SPI device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! IOM module to use for communicating with this device.
+    //
+    uint32_t ui32Module;
+
+    //
+    //! Chip select signal that should be used for this device.
+    //
+    uint32_t ui32ChipSelect;
+
+    //
+    //! Additional options that will ALWAYS be ORed into the command word.
+    //
+    uint32_t ui32Options;
+}
+am_hal_iom_spi_device_t;
+
+//*****************************************************************************
+//
+//! Configuration structure for an individual I2C device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! IOM module to use for communicating with this device.
+    //
+    uint32_t ui32Module;
+
+    //
+    //! I2C address associated with this device.
+    //
+    uint32_t ui32BusAddress;
+
+    //
+    //! Additional options that will ALWAYS be ORed into the command word.
+    //
+    uint32_t ui32Options;
+}
+am_hal_iom_i2c_device_t;
+
+//*****************************************************************************
+//
+// Typedef for non-blocking function callbacks.
+//
+//*****************************************************************************
+typedef void (*am_hal_iom_callback_t)(void);
+
+//*****************************************************************************
+//
+// Typedef for a function that waits until the IOM queue is empty.
+//
+//*****************************************************************************
+typedef void (*am_hal_iom_queue_flush_t)(uint32_t);
+
+extern am_hal_iom_queue_flush_t am_hal_iom_queue_flush;
+
+
+//*****************************************************************************
+//
+// Operations
+//
+//*****************************************************************************
+#define AM_HAL_IOM_QUEUE_SPI_WRITE                 0
+#define AM_HAL_IOM_QUEUE_SPI_READ                  1
+#define AM_HAL_IOM_QUEUE_I2C_WRITE                 2
+#define AM_HAL_IOM_QUEUE_I2C_READ                  3
+
+//*****************************************************************************
+//
+// Structure to hold IOM operations.
+//
+//*****************************************************************************
+typedef struct
+{
+    uint32_t ui32Operation;
+    uint32_t ui32Module;
+    uint32_t ui32ChipSelect;
+    uint32_t *pui32Data;
+    uint32_t ui32NumBytes;
+    uint32_t ui32Options;
+    am_hal_iom_callback_t pfnCallback;
+}
+am_hal_iom_queue_entry_t;
+
+//*****************************************************************************
+//
+// Structure to hold IOM configuration during module power-down.
+//
+//*****************************************************************************
+typedef struct
+{
+    uint32_t FIFOTHR;
+    uint32_t CLKCFG;
+    uint32_t CFG;
+    uint32_t INTEN;
+    uint32_t bValid;
+}
+am_hal_iom_pwrsave_t;
+
+//*****************************************************************************
+//
+// Global variables
+//
+//*****************************************************************************
+extern am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES];
+extern uint32_t g_iom_error_status;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void     am_hal_iom_pwrctrl_enable(uint32_t ui32Module);
+extern void     am_hal_iom_pwrctrl_disable(uint32_t ui32Module);
+extern void     am_hal_iom_power_on_restore(uint32_t ui32Module);
+extern void     am_hal_iom_power_off_save(uint32_t ui32Module);
+extern void     am_hal_iom_config(uint32_t ui32Module,
+                                  const am_hal_iom_config_t *psConfig);
+extern uint32_t am_hal_iom_frequency_get(uint32_t ui32Module);
+extern void     am_hal_iom_enable(uint32_t ui32Module);
+extern void     am_hal_iom_disable(uint32_t ui32Module);
+extern void     am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                                     uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                     uint32_t ui32Options);
+extern void     am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                                    uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                    uint32_t ui32Options);
+extern uint32_t am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                                        uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                        uint32_t ui32Options);
+extern uint32_t am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                                       uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                       uint32_t ui32Options);
+extern void     am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                                        uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                        uint32_t ui32Options,
+                                        am_hal_iom_callback_t pfnCallback);
+extern uint32_t am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                                       uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                       uint32_t ui32Options,
+                                       am_hal_iom_callback_t pfnCallback);
+extern void     am_hal_iom_spi_cmd_run(uint32_t ui32Operation,
+                                       uint32_t ui32Module,
+                                       uint32_t ui32ChipSelect,
+                                       uint32_t ui32NumBytes,
+                                       uint32_t ui32Options);
+extern void     am_hal_iom_i2c_write(uint32_t ui32Module,
+                                     uint32_t ui32BusAddress,
+                                     uint32_t *pui32Data,
+                                     uint32_t ui32NumBytes,
+                                     uint32_t ui32Options);
+extern void     am_hal_iom_i2c_read(uint32_t ui32Module,
+                                    uint32_t ui32BusAddress,
+                                    uint32_t *pui32Data,
+                                    uint32_t ui32NumBytes,
+                                    uint32_t ui32Options);
+extern uint32_t am_hal_iom_i2c_write_nq(uint32_t ui32Module,
+                                        uint32_t ui32BusAddress,
+                                        uint32_t *pui32Data,
+                                        uint32_t ui32NumBytes,
+                                        uint32_t ui32Options);
+extern uint32_t am_hal_iom_i2c_read_nq(uint32_t ui32Module,
+                                       uint32_t ui32BusAddress,
+                                       uint32_t *pui32Data,
+                                       uint32_t ui32NumBytes,
+                                       uint32_t ui32Options);
+extern void     am_hal_iom_i2c_write_nb(uint32_t ui32Module,
+                                        uint32_t ui32BusAddress,
+                                        uint32_t *pui32Data,
+                                        uint32_t ui32NumBytes,
+                                        uint32_t ui32Options,
+                                        am_hal_iom_callback_t pfnCallback);
+extern void     am_hal_iom_i2c_read_nb(uint32_t ui32Module,
+                                       uint32_t ui32BusAddress,
+                                       uint32_t *pui32Data,
+                                       uint32_t ui32NumBytes,
+                                       uint32_t ui32Options,
+                                       am_hal_iom_callback_t pfnCallback);
+extern void     am_hal_iom_i2c_cmd_run(uint32_t ui32Operation,
+                                       uint32_t ui32Module,
+                                       uint32_t ui32BusAddress,
+                                       uint32_t ui32NumBytes,
+                                       uint32_t ui32Options);
+extern void     am_hal_iom_command_repeat_set(uint32_t ui32Module,
+                                              uint32_t ui32CmdCount);
+extern uint32_t am_hal_iom_status_get(uint32_t ui32Module);
+extern uint32_t am_hal_iom_error_status_get(uint32_t ui32Module);
+extern uint32_t am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data,
+                                      uint32_t ui32NumBytes);
+extern uint32_t am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data,
+                                     uint32_t ui32NumBytes);
+extern uint8_t  am_hal_iom_fifo_empty_slots(uint32_t ui32Module);
+extern uint8_t  am_hal_iom_fifo_full_slots(uint32_t ui32Module);
+extern void     am_hal_iom_poll_complete(uint32_t ui32Module);
+extern void     am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status);
+extern void     am_hal_iom_int_enable(uint32_t ui32Module, uint32_t ui32Interrupt);
+extern uint32_t am_hal_iom_int_enable_get(uint32_t ui32Module);
+extern void     am_hal_iom_int_disable(uint32_t ui32Module, uint32_t ui32Interrupt);
+extern void     am_hal_iom_int_clear(uint32_t ui32Module, uint32_t ui32Interrupt);
+extern void     am_hal_iom_int_set(uint32_t ui32Module, uint32_t ui32Interrupt);
+extern uint32_t am_hal_iom_int_status_get(uint32_t ui32Module, bool bEnabledOnly);
+extern void     am_hal_iom_queue_init(uint32_t ui32ModuleNum,
+                                      am_hal_iom_queue_entry_t *psQueueMemory,
+                                      uint32_t ui32QueueMemSize);
+extern uint32_t am_hal_iom_queue_length_get(uint32_t ui32Module);
+extern void     am_hal_iom_sleeping_queue_flush(uint32_t ui32Module);
+extern void     am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                                           uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                           uint32_t ui32Options,
+                                           am_hal_iom_callback_t pfnCallback);
+extern void     am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
+                                          uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                          uint32_t ui32Options,
+                                          am_hal_iom_callback_t pfnCallback);
+extern void     am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress,
+                                           uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                           uint32_t ui32Options,
+                                           am_hal_iom_callback_t pfnCallback);
+extern void     am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress,
+                                          uint32_t *pui32Data, uint32_t ui32NumBytes,
+                                          uint32_t ui32Options,
+                                          am_hal_iom_callback_t pfnCallback);
+extern void     am_hal_iom_queue_start_next_msg(uint32_t ui32Module);
+extern void     am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Status);
+
+//*****************************************************************************
+//
+// Helper functions.
+//
+//*****************************************************************************
+#define AM_IOMASTER_ISR_QUEUE(x)                            \
+void am_iomaster##x##_isr(void)                             \
+{                                                           \
+    uint32_t ui32IntStatus;                                 \
+    g_iom_error_status = am_hal_iom_error_status_get(x);    \
+    ui32IntStatus = am_hal_iom_int_status_get(x, false);    \
+    am_hal_iom_int_clear(x, ui32IntStatus);                 \
+    am_hal_iom_queue_service(x, ui32IntStatus);             \
+}
+
+#define AM_IOMASTER_ISR_NB(x)                               \
+void am_iomaster##x##_isr(void)                             \
+{                                                           \
+    uint32_t ui32IntStatus;                                 \
+    g_iom_error_status = am_hal_iom_error_status_get(x);    \
+    ui32IntStatus = am_hal_iom_int_status_get(x, false);    \
+    am_hal_iom_int_clear(x, ui32IntStatus);                 \
+    am_hal_iom_int_service(x, ui32IntStatus);               \
+}
+
+#endif // AM_HAL_IOM_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c
new file mode 100644
index 0000000000..0f34aa6efb
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c
@@ -0,0 +1,1303 @@
+//*****************************************************************************
+//
+//  am_hal_ios.c
+//! @file
+//!
+//! @brief Functions for interfacing with the IO Slave module
+//!
+//! @addtogroup ios2 IO Slave (SPI/I2C)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// SRAM Buffer structure
+//
+//*****************************************************************************
+typedef struct
+{
+    uint8_t           *pui8Data;
+    volatile uint32_t ui32WriteIndex;
+    volatile uint32_t ui32ReadIndex;
+    volatile uint32_t ui32Length;
+    uint32_t          ui32Capacity;
+}
+am_hal_ios_buffer_t;
+
+am_hal_ios_buffer_t g_sSRAMBuffer;
+
+//*****************************************************************************
+//
+// Forward declarations of static funcitons.
+//
+//*****************************************************************************
+static void am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer,
+                                   void *pvArray, uint32_t ui32Bytes);
+
+static void fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes);
+
+//*****************************************************************************
+//
+// Function-like macros.
+//
+//*****************************************************************************
+#define am_hal_ios_buffer_empty(psBuffer)                                   \
+    ((psBuffer)->ui32Length == 0)
+
+#define am_hal_ios_buffer_full(psBuffer)                                    \
+    ((psBuffer)->ui32Length == (psBuffer)->ui32Capacity)
+
+#define am_hal_ios_buffer_data_left(psBuffer)                               \
+    ((psBuffer)->ui32Length)
+
+//*****************************************************************************
+//
+// Global Variables
+//
+//*****************************************************************************
+volatile uint8_t * const am_hal_ios_pui8LRAM = (uint8_t *)REG_IOSLAVE_BASEADDR;
+uint8_t *g_pui8FIFOBase = (uint8_t *) REG_IOSLAVE_BASEADDR;
+uint8_t *g_pui8FIFOEnd = (uint8_t *) REG_IOSLAVE_BASEADDR;
+uint8_t *g_pui8FIFOPtr = (uint8_t *) REG_IOSLAVE_BASEADDR;
+uint8_t g_ui32HwFifoSize = 0;
+uint32_t g_ui32FifoBaseOffset = 0;
+
+//*****************************************************************************
+//
+//! @brief Enable the IOS in the power control block.
+//!
+//! This function enables the IOS module in the power control block.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_pwrctrl_enable(void)
+{
+    am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_IOS);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the IOS in the power control block.
+//!
+//! This function disables the IOS module in the power control block.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_pwrctrl_disable(void)
+{
+    am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_IOS);
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the IOS module
+//!
+//! This function enables the IOSLAVE module using the IFCEN bitfield in the
+//! IOSLAVE_CFG register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_enable(uint32_t ui32Module)
+{
+    AM_REGn(IOSLAVE, ui32Module, CFG) |= AM_REG_IOSLAVE_CFG_IFCEN(1);
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the IOSLAVE module.
+//!
+//! This function disables the IOSLAVE module using the IFCEN bitfield in the
+//! IOSLAVE_CFG register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_disable(uint32_t ui32Module)
+{
+    AM_REGn(IOSLAVE, ui32Module, CFG) &= ~(AM_REG_IOSLAVE_CFG_IFCEN(1));
+}
+
+//*****************************************************************************
+//
+//! @brief Configure the IOS module.
+//!
+//! This function reads the an \e am_hal_ios_config_t structure and uses it to
+//! set up the IO Slave module. Please see the information on the configuration
+//! structure for more information on the parameters that may be set by this
+//! function.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_config(am_hal_ios_config_t *psConfig)
+{
+    uint32_t ui32LRAMConfig;
+
+    am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_IOS);
+
+    //
+    // Record the FIFO parameters for later use.
+    //
+    g_pui8FIFOBase = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32FIFOBase);
+    g_pui8FIFOEnd = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32RAMBase);
+    g_ui32HwFifoSize = g_pui8FIFOEnd - g_pui8FIFOBase;
+    g_ui32FifoBaseOffset = psConfig->ui32FIFOBase;
+
+    //
+    // Caluclate the value for the IO Slave FIFO configuration register.
+    //
+    ui32LRAMConfig = AM_REG_IOSLAVE_FIFOCFG_ROBASE(psConfig->ui32ROBase >> 3);
+    ui32LRAMConfig |= AM_REG_IOSLAVE_FIFOCFG_FIFOBASE(psConfig->ui32FIFOBase >> 3);
+    ui32LRAMConfig |= AM_REG_IOSLAVE_FIFOCFG_FIFOMAX(psConfig->ui32RAMBase >> 3);
+
+    //
+    // Just in case, disable the IOS
+    //
+    am_hal_ios_disable(0);
+
+    //
+    // Write the configuration register with the user's selected interface
+    // characteristics.
+    //
+    AM_REG(IOSLAVE, CFG) = psConfig->ui32InterfaceSelect;
+
+    //
+    // Write the FIFO configuration register to set the memory map for the LRAM.
+    //
+    AM_REG(IOSLAVE, FIFOCFG) = ui32LRAMConfig;
+
+    //
+    // Enable the IOS. The following configuration options can't be set while
+    // the IOS is disabled.
+    //
+    am_hal_ios_enable(0);
+
+    //
+    // Initialize the FIFO pointer to the beginning of the FIFO section.
+    //
+    am_hal_ios_fifo_ptr_set(psConfig->ui32FIFOBase);
+
+    //
+    // Write the FIFO threshold register.
+    //
+    AM_REG(IOSLAVE, FIFOTHR) = psConfig->ui32FIFOThreshold;
+}
+
+//*****************************************************************************
+//
+//! @brief Set bits in the HOST side IOINTCTL register.
+//!
+//! This function may be used to set an interrupt bit to the host.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_host_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Set a bit that will cause an interrupt to the host.
+    //
+    AM_REG(IOSLAVE, IOINTCTL) = AM_REG_IOSLAVE_IOINTCTL_IOINTSET(ui32Interrupt);
+}
+
+//*****************************************************************************
+//
+//! @brief Clear bits in the HOST side IOINTCTL register.
+//!
+//! This function may be used to clear an interrupt bit to the host.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_host_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Clear bits that will cause an interrupt to the host.
+    //
+    AM_REG(IOSLAVE, IOINTCTL) = AM_REG_IOSLAVE_IOINTCTL_IOINTCLR(ui32Interrupt);
+}
+
+//*****************************************************************************
+//
+//! @brief Get the bits in the HOST side IOINTCTL register.
+//!
+//! This function may be used to read the host side interrupt bits.
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_host_int_get(void)
+{
+    //
+    // return the value of the bits that will cause an interrupt to the host.
+    //
+    return AM_BFR(IOSLAVE, IOINTCTL, IOINT);
+}
+
+//*****************************************************************************
+//
+//! @brief Get the enable bits in the HOST side IOINTCTL register.
+//!
+//! This function may be used to read the host side interrupt bits.
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_host_int_enable_get(void)
+{
+    //
+    // return the value of the bits that will cause an interrupt to the host.
+    //
+    return AM_BFR(IOSLAVE, IOINTCTL, IOINTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable an IOS Access Interrupt.
+//!
+//! This function may be used to enable an interrupt to the NVIC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_access_int_enable(uint32_t ui32Interrupt)
+{
+    //
+    // OR the desired interrupt into the enable register.
+    //
+    AM_REG(IOSLAVE, REGACCINTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return all enabled IOS Access Interrupts.
+//!
+//! This function may be used to return all enabled IOS Access interrupts.
+//!
+//! @return the enabled interrrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_access_int_enable_get(void)
+{
+    //
+    // Return the enabled interrupts.
+    //
+    return AM_REG(IOSLAVE, REGACCINTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable an IOS Access Interrupt.
+//!
+//! This function may be used to disable an interrupt to the NVIC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_access_int_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Clear the desired bit from the interrupt enable register.
+    //
+    AM_REG(IOSLAVE, REGACCINTEN) &= ~(ui32Interrupt);
+}
+
+//*****************************************************************************
+//
+//! @brief Clear an IOS Access Interrupt.
+//!
+//! This function may be used to clear an interrupt to the NVIC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_access_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Use the interrupt clear register to deactivate the chosen interrupt.
+    //
+    AM_REG(IOSLAVE, REGACCINTCLR) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Set an IOS Access Interrupt.
+//!
+//! This function may be used to set an interrupt to the NVIC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_access_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Use the interrupt set register to activate the chosen interrupt.
+    //
+    AM_REG(IOSLAVE, REGACCINTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Check the status of an IOS Access Interrupt.
+//!
+//! @param bEnabledOnly - return only the enabled interrupt status.
+//!
+//! This function may be used to return the enabled interrupt status.
+//!
+//! @return the enabled interrupt status.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_access_int_status_get(bool bEnabledOnly)
+{
+    if ( bEnabledOnly )
+    {
+        uint32_t u32RetVal = AM_REG(IOSLAVE, REGACCINTSTAT);
+        return u32RetVal & AM_REG(IOSLAVE, REGACCINTEN);
+
+    }
+    else
+    {
+        return AM_REG(IOSLAVE, REGACCINTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Enable an IOS Interrupt.
+//!
+//! @param ui32Interrupt - desired interrupts.
+//!
+//! This function may be used to enable an interrupt to the NVIC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_int_enable(uint32_t ui32Interrupt)
+{
+    //
+    // OR the desired interrupt into the enable register.
+    //
+    AM_REG(IOSLAVE, INTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return all enabled IOS Interrupts.
+//!
+//! This function may be used to return all enabled IOS interrupts.
+//!
+//! @return the enabled interrrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_int_enable_get(void)
+{
+    //
+    // Return the enabled interrupts.
+    //
+    return AM_REG(IOSLAVE, INTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable an IOS Interrupt.
+//!
+//! @param ui32Interrupt - desired interrupts.
+//!
+//! This function may be used to disable an interrupt to the NVIC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_int_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Clear the desired bit from the interrupt enable register.
+    //
+    AM_REG(IOSLAVE, INTEN) &= ~(ui32Interrupt);
+}
+
+//*****************************************************************************
+//
+//! @brief Clear an IOS Interrupt.
+//!
+//! @param ui32Interrupt - desired interrupts.
+//!
+//! This function may be used to clear an interrupt to the NVIC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Use the interrupt clear register to deactivate the chosen interrupt.
+    //
+    AM_REG(IOSLAVE, INTCLR) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Set an IOS Interrupt.
+//!
+//! @param ui32Interrupt - desired interrupts.
+//!
+//! This function may be used to set an interrupt to the NVIC.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Use the interrupt clear register to deactivate the chosen interrupt.
+    //
+    AM_REG(IOSLAVE, INTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Write to the LRAM.
+//!
+//! @param ui32Offset - offset into the LRAM to write.
+//! @param ui8Value - value to be written.
+//!
+//! This function writes ui8Value to offset ui32Offset inside the LRAM.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_lram_write(uint32_t ui32Offset, uint8_t ui8Value)
+{
+    //
+    // Write the LRAM.
+    //
+    am_hal_ios_pui8LRAM[ui32Offset] = ui8Value;
+}
+
+//*****************************************************************************
+//
+//! @brief Read from the LRAM.
+//!
+//! @param ui32Offset - offset into the LRAM to read.
+//!
+//! This function read from offset ui32Offset inside the LRAM.
+//!
+//! @return the value at ui32Offset.
+//
+//*****************************************************************************
+uint8_t
+am_hal_ios_lram_read(uint32_t ui32Offset)
+{
+    //
+    // Read the LRAM.
+    //
+    return am_hal_ios_pui8LRAM[ui32Offset];
+}
+
+//*****************************************************************************
+//
+//! @brief Check the status of an IOS Interrupt.
+//!
+//! @param bEnabledOnly - return only the enabled interrupt status.
+//!
+//! This function may be used to return the enabled interrupt status.
+//!
+//! @return the enabled interrupt status.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_int_status_get(bool bEnabledOnly)
+{
+    if ( bEnabledOnly )
+    {
+        uint32_t u32RetVal = AM_REG(IOSLAVE, INTSTAT);
+        return u32RetVal & AM_REG(IOSLAVE, INTEN);
+
+    }
+    else
+    {
+        return AM_REG(IOSLAVE, INTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Check the amount of space used in the FIFO
+//!
+//! This function returns the available data in the overall FIFO yet to be
+//! read by the host. This takes into account the SRAM buffer and hardware FIFO
+//!
+//! @return Bytes used in the Overall FIFO.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_fifo_space_used(void)
+{
+    uint32_t ui32Val;
+    uint32_t ui32Primask;
+    //
+    // Start a critical section for thread safety.
+    //
+    ui32Primask = am_hal_interrupt_master_disable();
+    ui32Val = g_sSRAMBuffer.ui32Length;
+    ui32Val += AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ);
+    //
+    // End the critical section
+    //
+    am_hal_interrupt_master_set(ui32Primask);
+    return ui32Val;
+}
+
+
+
+//*****************************************************************************
+//
+//! @brief Check the amount of space left in the FIFO
+//!
+//! This function returns the available space in the overall FIFO to accept
+//! new data. This takes into account the SRAM buffer and hardware FIFO
+//!
+//! @return Bytes left in the Overall FIFO.
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_fifo_space_left(void)
+{
+    uint32_t ui32Val;
+    uint32_t ui32Primask;
+    //
+    // Start a critical section for thread safety.
+    //
+    ui32Primask = am_hal_interrupt_master_disable();
+    //
+    // We waste one byte in HW FIFO
+    //
+    ui32Val = g_sSRAMBuffer.ui32Capacity + g_ui32HwFifoSize - 1;
+    ui32Val -= g_sSRAMBuffer.ui32Length;
+    ui32Val -= AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ);
+    //
+    // End the critical section
+    //
+    am_hal_interrupt_master_set(ui32Primask);
+    return ui32Val;
+}
+
+//*****************************************************************************
+//
+//! @brief Check the amount of space left in the hardware FIFO
+//!
+//! This function reads the IOSLAVE FIFOPTR register and determines the amount
+//! of space left in the IOS LRAM FIFO.
+//!
+//! @return Bytes left in the IOS FIFO.
+//
+//*****************************************************************************
+static uint32_t
+fifo_space_left(void)
+{
+    //
+    // We waste one byte in HW FIFO
+    //
+    return ((uint32_t)g_ui32HwFifoSize- AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ) - 1);
+}
+
+//*****************************************************************************
+//
+// Helper function for managing IOS FIFO writes.
+//
+//*****************************************************************************
+static void
+fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes)
+{
+    uint8_t *pFifoPtr = g_pui8FIFOPtr;
+    uint8_t *pFifoBase = g_pui8FIFOBase;
+    uint8_t *pFifoEnd = g_pui8FIFOEnd;
+    while ( ui32NumBytes )
+    {
+        //
+        // Write the data to the FIFO
+        //
+        *pFifoPtr++ = *pui8Data++;
+        ui32NumBytes--;
+
+        //
+        // Make sure to wrap the FIFO pointer if necessary.
+        //
+        if ( pFifoPtr == pFifoEnd )
+        {
+            pFifoPtr = pFifoBase;
+        }
+    }
+    g_pui8FIFOPtr = pFifoPtr;
+}
+
+//
+// Assembly code below assumes 8bit FIFOSIZ field aligned at a byte boundary
+//
+#if (((AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M >> AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S) != 0xFF) \
+        || (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S & 0x3))
+#error "FIFOSIZ not 8bit value aligned at byte offset"
+#endif
+
+//
+// Byte offset of FIFOSIZ field in FIFOPTR register
+//
+#define BYTEOFFSET_FIFOSIZE             (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S >> 3)
+
+//*****************************************************************************
+//
+// Helper function in assembly for implementing the ReSync
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+#if (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S != 8)
+#error "AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S not 8"
+#endif
+__attribute__((naked))
+static void
+internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr)
+{
+    __asm
+    (
+        "   push    {r3,r4}\n\t"                  // Save r3, r4 - used by this function
+        "__internal_resync_fifoSize_loop:\n\t"
+        "   ldr     r4, [r2]\n\t"                 // Load FIFOPTR register in r4
+        "   ubfx    r3, r4, #8, #8\n\t"           // Extract hwFifoSize to r3
+        "   uxtb    r4, r4\n\t"                   // Extract rdOffset in r4
+        "   subs    r4, r0, r4\n\t"               // fifoSize in r4 = wrOffset - rdOffset
+        "   it      cc\n\t"                       // if (wrOffset < rdOffset)
+        "   addcc   r4, r4, r1\n\t"               //     fifoSize = maxFifoSize - (rdOffset - wrOffset)
+        "   cmp     r3, r4\n\t"                   // (hwFifoSize != fifoSize)
+        "   beq     __internal_resync_fifosize_done\n\t"
+        "   strb    r4, [r2, #1]\n\t"             // Overwrite FIFOSIZ value with fifoSize
+        "   b       __internal_resync_fifoSize_loop\n\t" // Repeat the check
+        "__internal_resync_fifosize_done:\n\t"
+        "   pop     {r3,r4}\n\t"                  // Restore registers
+        "   bx      lr\n\t"
+    );
+}
+
+#elif defined(__ARMCC_VERSION)
+__asm static void
+internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr)
+{
+    push    {r3, r4}                 // Save r3, r4 - used by this function
+internal_resync_fifoSize_loop
+    ldr     r4, [r2]                 // Load FIFOPTR register in r4
+    ubfx    r3, r4, #AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S, #8 // Extract hwFifoSize to r3
+    uxtb    r4, r4                   // Extract rdOffset in r4
+    subs    r4, r0, r4               // fifoSize in r4 = wrOffset - rdOffset
+    it      cc                       // if (wrOffset < rdOffset),
+    addcc   r4, r4, r1               //     fifoSize = maxFifoSize - (rdOffset - wrOffset)
+    cmp     r3, r4                   // (hwFifoSize != fifoSize)
+    beq     internal_resync_fifosize_done
+    strb    r4, [r2, #1]             // Overwrite FIFOSIZ value with fifoSize
+    b       internal_resync_fifoSize_loop // Repeat the check
+internal_resync_fifosize_done
+    pop     {r3, r4}                 // Restore registers
+    bx      lr
+}
+
+#elif defined(__IAR_SYSTEMS_ICC__)
+#if (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S != 8)
+#error "AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S not 8"
+#endif
+__stackless static void
+internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr)
+{
+    __asm volatile (
+          "    push    {r3,r4}\n"                  // Save r3, r4 - used by this function
+          "__internal_resync_fifoSize_loop:\n"
+          "    ldr     r4, [r2]\n"                 // Load FIFOPTR register in r4
+          "    ubfx    r3, r4, #8, #8\n"           // Extract hwFifoSize to r3
+          "    uxtb    r4, r4\n"                   // Extract rdOffset in r4
+          "    subs    r4, r0, r4\n"               // fifoSize in r4 = wrOffset - rdOffset
+          "    it      cc\n"
+          "    addcc   r4, r4, r1\n"               //     fifoSize = maxFifoSize - (rdOffset - wrOffset)
+          "    cmp     r3, r4\n"                   // (fifoSize != hwFifoSize)
+          "    beq     __internal_resync_fifosize_done\n"
+          "    strb    r4, [r2, #1]\n"             // Overwrite FIFOSIZ value with fifoSize
+          "    b       __internal_resync_fifoSize_loop\n" // Repeat the check
+          "__internal_resync_fifosize_done:\n"
+          "    pop     {r3,r4}\n"                  // Restore registers
+          "    bx      lr\n"
+          );
+}
+
+#else
+static void
+internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr)
+{
+    uint32_t fifoSize;
+    uint32_t hwFifoPtrReg;
+    uint32_t rdOffset;
+    uint32_t hwFifoSize;
+
+    hwFifoPtrReg = AM_REGVAL(hwFifoPtrRegAddr);
+    rdOffset = ((hwFifoPtrReg & AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_M) >> AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_S);
+    hwFifoSize = (hwFifoPtrReg & AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M) >> AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S;
+    // By wasting one byte in hardware FIFO, we're guaranteed that fifoSize does not need special handling for FULL FIFO case
+    fifoSize = ((wrOffset >= rdOffset) ? (wrOffset - rdOffset) : (maxFifoSize - (rdOffset - wrOffset)));
+    while ( fifoSize != hwFifoSize )
+    {
+        // Overwite correct FIFOSIZ
+        // Need to do a Byte Write to make sure the FIFOPTR is not overwritten
+        *((uint8_t *)(hwFifoPtrRegAddr + BYTEOFFSET_FIFOSIZE)) = fifoSize;
+        // Read back the register and check for consistency
+        hwFifoPtrReg = AM_REGVAL(hwFifoPtrRegAddr);
+        rdOffset = ((hwFifoPtrReg & AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_M) >> AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_S);
+        hwFifoSize = (hwFifoPtrReg & AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M) >> AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S;
+        // By wasting one byte in hardware FIFO, we're guaranteed that fifoSize does not need special handling for FULL FIFO case
+        fifoSize = ((wrOffset >= rdOffset) ? (wrOffset - rdOffset) : (hwFifoSize - (rdOffset - wrOffset)));
+    }
+}
+#endif
+
+//
+// Address of the FIFOPTR register
+//
+#define AM_REG_IOS_FIFOPTR      (REG_IOSLAVE_BASEADDR + AM_REG_IOSLAVE_FIFOPTR_O)
+
+// When the FIFO is being replenished by the SW, at the same time as host is
+// reading from it, there is a possible race condition, where the hardware decrement
+// of FIFOSIZ as a result of read gets overwritten by hardware increment due to
+// write.
+// This function re-sync's the FIFOSIZ to ensure such errors do not accumulate
+void
+resync_fifoSize(void)
+{
+    uint32_t ui32Primask;
+    uint32_t wrOffset = (uint32_t)g_pui8FIFOPtr - (uint32_t)am_hal_ios_pui8LRAM;
+    //
+    // Start a critical section for thread safety.
+    //
+    ui32Primask = am_hal_interrupt_master_disable();
+    internal_resync_fifoSize(wrOffset, g_ui32HwFifoSize, AM_REG_IOS_FIFOPTR);
+    // Clear interrupts for IOS which could be spuriously triggered
+    AM_REG(IOSLAVE, REGACCINTCLR) = (AM_HAL_IOS_INT_FSIZE | AM_HAL_IOS_INT_FOVFL | AM_HAL_IOS_INT_FUNDFL);
+    //
+    // End the critical section
+    //
+    am_hal_interrupt_master_set(ui32Primask);
+    return;
+}
+
+//*****************************************************************************
+//
+//! @brief Transfer any available data from the IOS SRAM buffer to the FIFO.
+//!
+//! This function is meant to be called from an interrupt handler for the
+//! ioslave module. It checks the IOS FIFO interrupt status for a threshold
+//! event, and transfers data from an SRAM buffer into the IOS FIFO.
+//!
+//! @param ui32Status should be set to the ios interrupt status at the time of
+//! ISR entry.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_fifo_service(uint32_t ui32Status)
+{
+    uint32_t thresh;
+    uint32_t freeSpace, usedSpace, chunk1, chunk2, ui32WriteIndex;
+
+    //
+    // Check for FIFO size interrupts.
+    //
+    if ( ui32Status & AM_HAL_IOS_INT_FSIZE )
+    {
+        thresh = AM_BFR(IOSLAVE, FIFOTHR, FIFOTHR);
+
+        //
+        // While the FIFO is at or below threshold Add more data
+        // If Fifo level is above threshold, we're guaranteed an FSIZ interrupt
+        //
+        while ( g_sSRAMBuffer.ui32Length &&
+                ((usedSpace = AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ)) <= thresh) )
+        {
+            //
+            // So, we do have some data in SRAM which needs to be moved to FIFO.
+            // A chunk of data is a continguous set of bytes in SRAM that can be
+            //  written to FIFO. Determine the chunks of data from SRAM that can
+            //  be written. Up to two chunks possible
+            //
+            ui32WriteIndex = g_sSRAMBuffer.ui32WriteIndex;
+            chunk1 = ((ui32WriteIndex > (uint32_t)g_sSRAMBuffer.ui32ReadIndex) ?   \
+                        (ui32WriteIndex - (uint32_t)g_sSRAMBuffer.ui32ReadIndex) : \
+                        (g_sSRAMBuffer.ui32Capacity - (uint32_t)g_sSRAMBuffer.ui32ReadIndex));
+            chunk2 = g_sSRAMBuffer.ui32Length - chunk1;
+            // We waste one byte in HW FIFO
+            freeSpace = g_ui32HwFifoSize - usedSpace - 1;
+            // Write data in chunks
+            // Determine the chunks of data from SRAM that can be written
+            if ( chunk1 > freeSpace )
+            {
+                fifo_write((uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), freeSpace);
+                //
+                // Advance the read index, wrapping if needed.
+                //
+                g_sSRAMBuffer.ui32ReadIndex += freeSpace;
+                // No need to check for wrap as we wrote less than chunk1
+                //
+                // Adjust the length value to reflect the change.
+                //
+                g_sSRAMBuffer.ui32Length -= freeSpace;
+            }
+            else
+            {
+                fifo_write((uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), chunk1);
+
+                //
+                // Update the read index - wrapping as needed
+                //
+                g_sSRAMBuffer.ui32ReadIndex += chunk1;
+                g_sSRAMBuffer.ui32ReadIndex %= g_sSRAMBuffer.ui32Capacity;
+                //
+                // Adjust the length value to reflect the change.
+                //
+                g_sSRAMBuffer.ui32Length -= chunk1;
+                freeSpace -= chunk1;
+
+                if ( freeSpace && chunk2 )
+                {
+                    if ( chunk2 > freeSpace )
+                    {
+                        fifo_write((uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), freeSpace);
+
+                        //
+                        // Advance the read index, wrapping if needed.
+                        //
+                        g_sSRAMBuffer.ui32ReadIndex += freeSpace;
+
+                        // No need to check for wrap in chunk2
+                        //
+                        // Adjust the length value to reflect the change.
+                        //
+                        g_sSRAMBuffer.ui32Length -= freeSpace;
+                    }
+                    else
+                    {
+                        fifo_write((uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), chunk2);
+                        //
+                        // Advance the read index, wrapping if needed.
+                        //
+                        g_sSRAMBuffer.ui32ReadIndex += chunk2;
+
+                        // No need to check for wrap in chunk2
+                        //
+                        // Adjust the length value to reflect the change.
+                        //
+                        g_sSRAMBuffer.ui32Length -= chunk2;
+                    }
+                }
+            }
+            resync_fifoSize();
+
+            //
+            // Need to retake the FIFO space, after Threshold interrupt has been reenabled
+            // Clear any spurious FSIZE interrupt that might have got raised
+            //
+            AM_BFW(IOSLAVE, INTCLR, FSIZE, 1);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Writes the specified number of bytes to the IOS fifo.
+//!
+//! @param pui8Data is a pointer to the data to be written to the fifo.
+//! @param ui32NumBytes is the number of bytes to send.
+//!
+//! This function will write data from the caller-provided array to the IOS
+//! LRAM FIFO. If there is no space in the LRAM FIFO, the data will be copied
+//! to a temporary SRAM buffer instead.
+//!
+//! The maximum message size for the IO Slave is 1023 bytes.
+//!
+//! @note In order for SRAM copy operations in the function to work correctly,
+//! the \e am_hal_ios_buffer_service() function must be called in the ISR for
+//! the ioslave module.
+//!
+//! @return Number of bytes written (could be less than ui32NumBytes, if not enough space)
+//
+//*****************************************************************************
+uint32_t
+am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes)
+{
+    uint32_t ui32FIFOSpace;
+    uint32_t ui32SRAMSpace;
+    uint32_t ui32SRAMLength;
+    uint32_t ui32Primask;
+    uint32_t totalBytes = ui32NumBytes;
+
+    //
+    // This operation will only work properly if an SRAM buffer has been
+    // allocated. Make sure that am_hal_ios_fifo_buffer_init() has been called,
+    // and the buffer pointer looks valid.
+    //
+    am_hal_debug_assert(g_sSRAMBuffer.pui8Data != 0);
+
+    if ( ui32NumBytes == 0 )
+    {
+        return 0;
+    }
+
+    //
+    // Start a critical section for thread safety.
+    //
+    ui32Primask = am_hal_interrupt_master_disable();
+
+    ui32SRAMLength = g_sSRAMBuffer.ui32Length;
+    //
+    // End the critical section
+    //
+    am_hal_interrupt_master_set(ui32Primask);
+
+    //
+    // If the SRAM buffer is empty, we should just write directly to the FIFO.
+    //
+    if ( ui32SRAMLength == 0 )
+    {
+        ui32FIFOSpace = fifo_space_left();
+
+        //
+        // If the whole message fits, send it now.
+        //
+        if ( ui32NumBytes <= ui32FIFOSpace )
+        {
+            fifo_write(pui8Data, ui32NumBytes);
+            ui32NumBytes = 0;
+        }
+        else
+        {
+            fifo_write(pui8Data, ui32FIFOSpace);
+            ui32NumBytes -= ui32FIFOSpace;
+            pui8Data += ui32FIFOSpace;
+        };
+        resync_fifoSize();
+    }
+
+    //
+    // If there's still data, write it to the SRAM buffer.
+    //
+    if ( ui32NumBytes )
+    {
+        uint32_t idx, writeIdx, capacity, fifoSize;
+        ui32SRAMSpace = g_sSRAMBuffer.ui32Capacity - ui32SRAMLength;
+
+        writeIdx = g_sSRAMBuffer.ui32WriteIndex;
+        capacity = g_sSRAMBuffer.ui32Capacity;
+        //
+        // Make sure that the data will fit inside the SRAM buffer.
+        //
+        if ( ui32SRAMSpace > ui32NumBytes )
+        {
+            ui32SRAMSpace = ui32NumBytes;
+        }
+
+        //
+        // If the data will fit, write it to the SRAM buffer.
+        //
+        for ( idx = 0; idx < ui32SRAMSpace; idx++ )
+        {
+            g_sSRAMBuffer.pui8Data[(idx + writeIdx) % capacity] = pui8Data[idx];
+        }
+
+        ui32NumBytes -= idx;
+        //
+        // Start a critical section for thread safety before updating length & wrIdx.
+        //
+        ui32Primask = am_hal_interrupt_master_disable();
+        //
+        // Advance the write index, making sure to wrap if necessary.
+        //
+        g_sSRAMBuffer.ui32WriteIndex = (idx + writeIdx) % capacity;
+
+        //
+        // Update the length value appropriately.
+        //
+        g_sSRAMBuffer.ui32Length += idx;
+        //
+        // End the critical section
+        //
+        am_hal_interrupt_master_set(ui32Primask);
+
+        // It is possible that there is a race condition that the FIFO level has
+        // gone below the threshold by the time we set the wrIdx above, and hence
+        // we may never get the threshold interrupt to serve the SRAM data we
+        // just wrote
+
+        // If that is the case, explicitly generate the FSIZE interrupt from here
+        fifoSize = AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ);
+        if ( fifoSize <= AM_BFR(IOSLAVE, FIFOTHR, FIFOTHR) )
+        {
+            AM_BFW(IOSLAVE, INTSET, FSIZE, 1);
+        }
+    }
+
+    return (totalBytes - ui32NumBytes);
+}
+
+//*****************************************************************************
+//
+//! @brief Writes the specified number of bytes to the IOS fifo simply.
+//!
+//! @param pui8Data is a pointer to the data to be written to the fifo.
+//! @param ui32NumBytes is the number of bytes to send.
+//!
+//! This function will write data from the caller-provided array to the IOS
+//! LRAM FIFO. This simple routine does not use SRAM buffering for large
+//! messages.
+//!
+//! The maximum message size for the IO Slave is 128 bytes.
+//!
+//! @note Do note call the \e am_hal_ios_buffer_service() function in the ISR for
+//! the ioslave module.
+//!
+//! @return
+//
+//*****************************************************************************
+void
+am_hal_ios_fifo_write_simple(uint8_t *pui8Data, uint32_t ui32NumBytes)
+{
+    uint32_t ui32FIFOSpace;
+
+    //
+    // Check the FIFO and the SRAM buffer to see where we have space.
+    //
+    ui32FIFOSpace = fifo_space_left();
+
+    //
+    // If the whole message fits, send it now.
+    //
+    if ( ui32NumBytes <= ui32FIFOSpace )
+    {
+        fifo_write(pui8Data, ui32NumBytes);
+    }
+    else
+    {
+        //
+        // The message didn't fit. Try using am_hal_ios_fifo_write() instead.
+        //
+        am_hal_debug_assert_msg(0, "The requested IOS transfer didn't fit in"
+                                   "the LRAM FIFO. Try using am_hal_ios_fifo_write().");
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Sets the IOS FIFO pointer to the specified LRAM offset.
+//!
+//! @param ui32Offset is LRAM offset to set the FIFO pointer to.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_fifo_ptr_set(uint32_t ui32Offset)
+{
+    uint32_t ui32Primask;
+
+    //
+    // Start a critical section for thread safety.
+    //
+    ui32Primask = am_hal_interrupt_master_disable();
+
+    //
+    // Set the FIFO Update bit.
+    //
+    AM_REG(IOSLAVE, FUPD) = 0x1;
+
+    //
+    // Change the FIFO offset.
+    //
+    AM_REG(IOSLAVE, FIFOPTR) = ui32Offset;
+
+    //
+    // Clear the FIFO update bit.
+    //
+    AM_REG(IOSLAVE, FUPD) = 0x0;
+
+    //
+    // Set the global FIFO-pointer tracking variable.
+    //
+    g_pui8FIFOPtr = (uint8_t *) (REG_IOSLAVE_BASEADDR + ui32Offset);
+
+    //
+    // End the critical section.
+    //
+    am_hal_interrupt_master_set(ui32Primask);
+}
+
+//*****************************************************************************
+//
+// Initialize an SRAM buffer for use with the IO Slave.
+//
+//*****************************************************************************
+static void
+am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, void *pvArray,
+                       uint32_t ui32Bytes)
+{
+    psBuffer->ui32WriteIndex = 0;
+    psBuffer->ui32ReadIndex = 0;
+    psBuffer->ui32Length = 0;
+    psBuffer->ui32Capacity = ui32Bytes;
+    psBuffer->pui8Data = (uint8_t *)pvArray;
+}
+
+//*****************************************************************************
+//
+//! @brief Poll for all host side read activity to complete.
+//!
+//! Poll for all host side read activity to complete. Use this before
+//! calling am_hal_ios_fifo_write_simple().
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_read_poll_complete(void)
+{
+    while ( AM_REG(IOSLAVE, FUPD) & AM_REG_IOSLAVE_FUPD_IOREAD_M );
+}
+
+//*****************************************************************************
+//
+//! @brief Initializes an SRAM buffer for the IOS FIFO.
+//!
+//! @param pui8Buffer is the SRAM buffer that will be used for IOS fifo data.
+//! @param ui32BufferSize is the size of the SRAM buffer.
+//!
+//! This function provides the IOS HAL functions with working memory for
+//! managing outgoing IOS FIFO transactions. It needs to be called at least
+//! once before am_hal_ios_fifo_write() may be used.
+//!
+//! The recommended buffer size for the IOS FIFO is 1024 bytes.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes)
+{
+    //
+    // Initialize the global SRAM buffer
+    // Total size, which is SRAM Buffer plus the hardware FIFO needs to be
+    // limited to 1023
+    //
+    if ( ui32NumBytes > (1023 - g_ui32HwFifoSize + 1) )
+    {
+        ui32NumBytes = (1023 - g_ui32HwFifoSize + 1);
+    }
+
+    am_hal_ios_buffer_init(&g_sSRAMBuffer, pui8Buffer, ui32NumBytes);
+
+    //
+    // Clear the FIFO State
+    //
+    AM_BFW(IOSLAVE, FIFOCTR, FIFOCTR, 0x0);
+    AM_BFW(IOSLAVE, FIFOPTR, FIFOSIZ, 0x0);
+
+    am_hal_ios_fifo_ptr_set(g_ui32FifoBaseOffset);
+}
+
+//*****************************************************************************
+//
+//! @brief Update the FIFOCTR to inform host of available data to read.
+//!
+//! This function allows the application to indicate to HAL when it is safe to
+//! update the FIFOCTR.
+//!
+//! Application needs to implement some sort of
+//! synchronization with the host to make sure host is not reading FIFOCTR while
+//! it is being updated by the MCU, since the FIFOCTR read over
+//! IO is not an atomic operation.
+//!
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_ios_update_fifoctr(void)
+{
+    uint32_t ui32Val;
+    // Determine the available data
+    ui32Val = am_hal_ios_fifo_space_used();
+    // Update FIFOCTR
+    AM_BFW(IOSLAVE, FIFOCTR, FIFOCTR, ui32Val);
+    return;
+}
+
+//*****************************************************************************
+//
+//  End the doxygen group
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h
new file mode 100644
index 0000000000..b166c9c6e5
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h
@@ -0,0 +1,362 @@
+//*****************************************************************************
+//
+//  am_hal_ios.h
+//! @file
+//!
+//! @brief Functions for interfacing with the IO Slave module
+//!
+//! @addtogroup ios2 IO Slave (SPI/I2C)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_IOS_H
+#define AM_HAL_IOS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name Interface Configuration
+//! @brief Macro definitions for configuring the physical interface of the IO
+//! Slave
+//!
+//! These macros may be used with the am_hal_ios_config_t structure to set the
+//! physical parameters of the SPI/I2C slave module.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOS_USE_SPI           AM_REG_IOSLAVE_CFG_IFCSEL_SPI
+#define AM_HAL_IOS_SPIMODE_0         AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3
+#define AM_HAL_IOS_SPIMODE_1         AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2
+#define AM_HAL_IOS_SPIMODE_2         AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2
+#define AM_HAL_IOS_SPIMODE_3         AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3
+
+#define AM_HAL_IOS_USE_I2C           AM_REG_IOSLAVE_CFG_IFCSEL_I2C
+#define AM_HAL_IOS_I2C_ADDRESS(n)    AM_REG_IOSLAVE_CFG_I2CADDR(n)
+
+#define AM_HAL_IOS_LSB_FIRST         AM_REG_IOSLAVE_CFG_LSB(1)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Register Access Interrupts
+//! @brief Macro definitions for register access interrupts.
+//!
+//! These macros may be used with any of the
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOS_ACCESS_INT_00     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 31)
+#define AM_HAL_IOS_ACCESS_INT_01     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 30)
+#define AM_HAL_IOS_ACCESS_INT_02     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 29)
+#define AM_HAL_IOS_ACCESS_INT_03     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 28)
+#define AM_HAL_IOS_ACCESS_INT_04     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 27)
+#define AM_HAL_IOS_ACCESS_INT_05     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 26)
+#define AM_HAL_IOS_ACCESS_INT_06     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 25)
+#define AM_HAL_IOS_ACCESS_INT_07     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 24)
+#define AM_HAL_IOS_ACCESS_INT_08     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 23)
+#define AM_HAL_IOS_ACCESS_INT_09     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 22)
+#define AM_HAL_IOS_ACCESS_INT_0A     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 21)
+#define AM_HAL_IOS_ACCESS_INT_0B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 20)
+#define AM_HAL_IOS_ACCESS_INT_0C     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 19)
+#define AM_HAL_IOS_ACCESS_INT_0D     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 18)
+#define AM_HAL_IOS_ACCESS_INT_0E     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 17)
+#define AM_HAL_IOS_ACCESS_INT_0F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 16)
+#define AM_HAL_IOS_ACCESS_INT_13     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 15)
+#define AM_HAL_IOS_ACCESS_INT_17     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 14)
+#define AM_HAL_IOS_ACCESS_INT_1B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 13)
+#define AM_HAL_IOS_ACCESS_INT_1F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 12)
+#define AM_HAL_IOS_ACCESS_INT_23     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 11)
+#define AM_HAL_IOS_ACCESS_INT_27     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 10)
+#define AM_HAL_IOS_ACCESS_INT_2B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 9)
+#define AM_HAL_IOS_ACCESS_INT_2F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 8)
+#define AM_HAL_IOS_ACCESS_INT_33     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 7)
+#define AM_HAL_IOS_ACCESS_INT_37     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 6)
+#define AM_HAL_IOS_ACCESS_INT_3B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 5)
+#define AM_HAL_IOS_ACCESS_INT_3F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 4)
+#define AM_HAL_IOS_ACCESS_INT_43     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 3)
+#define AM_HAL_IOS_ACCESS_INT_47     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 2)
+#define AM_HAL_IOS_ACCESS_INT_4B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 1)
+#define AM_HAL_IOS_ACCESS_INT_4F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 0)
+#define AM_HAL_IOS_ACCESS_INT_ALL    0xFFFFFFFF
+//! @}
+
+//*****************************************************************************
+//
+//! @name I/O Slave Interrupts
+//! @brief Macro definitions for I/O slave (IOS) interrupts.
+//!
+//! These macros may be used with any of the
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOS_INT_FSIZE            AM_REG_IOSLAVE_INTEN_FSIZE_M
+#define AM_HAL_IOS_INT_FOVFL            AM_REG_IOSLAVE_INTEN_FOVFL_M
+#define AM_HAL_IOS_INT_FUNDFL           AM_REG_IOSLAVE_INTEN_FUNDFL_M
+#define AM_HAL_IOS_INT_FRDERR           AM_REG_IOSLAVE_INTEN_FRDERR_M
+#define AM_HAL_IOS_INT_GENAD            AM_REG_IOSLAVE_INTEN_GENAD_M
+#define AM_HAL_IOS_INT_IOINTW           AM_REG_IOSLAVE_INTEN_IOINTW_M
+#define AM_HAL_IOS_INT_XCMPWR           AM_REG_IOSLAVE_INTEN_XCMPWR_M
+#define AM_HAL_IOS_INT_XCMPWF           AM_REG_IOSLAVE_INTEN_XCMPWF_M
+#define AM_HAL_IOS_INT_XCMPRR           AM_REG_IOSLAVE_INTEN_XCMPRR_M
+#define AM_HAL_IOS_INT_XCMPRF           AM_REG_IOSLAVE_INTEN_XCMPRF_M
+#define AM_HAL_IOS_INT_ALL              0xFFFFFFFF
+//! @}
+
+//*****************************************************************************
+//
+//! @name I/O Slave Interrupts triggers
+//! @brief Macro definitions for I/O slave (IOS) interrupts.
+//!
+//! These macros may be used with am_hal_ios_int_set and am_hal_ios_int_clear
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOS_IOINTCTL_INT0    (0x01)
+#define AM_HAL_IOS_IOINTCTL_INT1    (0x02)
+#define AM_HAL_IOS_IOINTCTL_INT2    (0x04)
+#define AM_HAL_IOS_IOINTCTL_INT3    (0x08)
+#define AM_HAL_IOS_IOINTCTL_INT4    (0x10)
+#define AM_HAL_IOS_IOINTCTL_INT5    (0x20)
+//! @}
+
+//*****************************************************************************
+//
+// External variable definitions
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! @brief LRAM pointer
+//!
+//! Pointer to the base of the IO Slave LRAM.
+//
+//*****************************************************************************
+extern volatile uint8_t * const am_hal_ios_pui8LRAM;
+
+//*****************************************************************************
+//
+//! @brief Configuration structure for the IO slave module.
+//!
+//! This structure may be used along with the am_hal_ios_config() function to
+//! select key parameters of the IO Slave module. See the descriptions of each
+//! parameter within this structure for more information on what they control.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Interface Selection
+    //!
+    //! This word selects the physical behavior of the IO Slave port. For SPI
+    //! mode, this word should be the logical OR of one or more of the
+    //! following:
+    //!
+    //!     AM_HAL_IOS_USE_SPI
+    //!     AM_HAL_IOS_SPIMODE_0
+    //!     AM_HAL_IOS_SPIMODE_1
+    //!     AM_HAL_IOS_SPIMODE_2
+    //!     AM_HAL_IOS_SPIMODE_3
+    //!
+    //! For I2C mode, use the logical OR of one or more of these values instead
+    //! (where n is the 7 or 10-bit I2C address to use):
+    //!
+    //!     AM_HAL_IOS_USE_I2C
+    //!     AM_HAL_IOS_I2C_ADDRESS(n)
+    //!
+    //! Also, in any mode, you may OR in this value to reverse the order of
+    //! incoming data bits.
+    //!
+    //!     AM_HAL_IOS_LSB_FIRST
+    //
+    uint32_t ui32InterfaceSelect;
+
+    //
+    //! Read-Only section
+    //!
+    //! The IO Slave LRAM is split into three main sections. The first section
+    //! is a "Direct Write" section, which may be accessed for reads or write
+    //! either directly through the Apollo CPU, or over the SPI/I2C bus. The
+    //! "Direct Write" section always begins at LRAM offset 0x0. At the end of
+    //! the normal "Direct Write" space, there is a "Read Only" space, which is
+    //! read/write accessible to the Apollo CPU, but read-only over the I2C/SPI
+    //! Bus. This word selects the base address of this "Read Only" space.
+    //!
+    //! This value may be set to any multiple of 8 between 0x0 and 0x78,
+    //! inclusive. For the configuration to be valid, \e ui32ROBase must also
+    //! be less than or equal to \e ui32FIFOBase
+    //!
+    //! @note The address given here is in units of BYTES. Since the location
+    //! of the "Read Only" space may only be set in 8-byte increments, this
+    //! value must be a multiple of 8.
+    //!
+    //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
+    //! will shift right by 8 internally.
+    //
+    uint32_t ui32ROBase;
+
+    //
+    //! FIFO section
+    //!
+    //! After the "Direct Access" and "Read Only" sections is a section of LRAM
+    //! allocated to a FIFO. This section is accessible by the Apollo CPU
+    //! through the FIFO control registers, and accessible on the SPI/I2C bus
+    //! through the 0x7F address. This word selects the base address of the
+    //! FIFO space. The FIFO will extend from the address specified here to the
+    //! address specified in \e ui32RAMBase.
+    //!
+    //! This value may be set to any multiple of 8 between 0x0 and 0x78,
+    //! inclusive. For the configuration to be valid, \e ui32FIFOBase must also
+    //! be greater than or equal to \e ui32ROBase.
+    //!
+    //! @note The address given here is in units of BYTES. Since the location
+    //! of the "FIFO" space may only be set in 8-byte increments, this value
+    //! must be a multiple of 8.
+    //!
+    //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
+    //! will shift right by 8 internally.
+    //
+    uint32_t ui32FIFOBase;
+
+    //
+    //! RAM section
+    //!
+    //! At the end of the IOS LRAM, the user may allocate a "RAM" space that
+    //! can only be accessed by the Apollo CPU. This space will not interact
+    //! with the SPI/I2C bus at all, and may be used as general-purpose memory.
+    //! Unlike normal SRAM, this section of LRAM will retain its state through
+    //! Deep Sleep, so it may be used as a data retention space for
+    //! ultra-low-power applications.
+    //!
+    //! This value may be set to any multiple of 8 between 0x0 and 0x100,
+    //! inclusive. For the configuration to be valid, \e ui32RAMBase must also
+    //! be greater than or equal to \e ui32FIFOBase.
+    //!
+    //! @note The address given here is in units of BYTES. Since the location
+    //! of the "FIFO" space may only be set in 8-byte increments, this value
+    //! must be a multiple of 8.
+    //!
+    //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
+    //! will shift right by 8 internally.
+    //
+    uint32_t ui32RAMBase;
+
+    //
+    //! FIFO threshold
+    //!
+    //! The IO Slave module will trigger an interrupt when the number of
+    //! entries in the FIFO drops below this number of bytes.
+    //
+    uint32_t ui32FIFOThreshold;
+
+    //
+    // Pointer to an SRAM
+    //
+    uint8_t *pui8SRAMBuffer;
+}
+am_hal_ios_config_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_ios_enable(uint32_t ui32Module);
+extern void am_hal_ios_disable(uint32_t ui32Module);
+
+// these interrupts drive the HOST side IOS interrupt pins
+extern void am_hal_ios_host_int_set(uint32_t ui32Interrupt);
+extern void am_hal_ios_host_int_clear(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_host_int_get(void);
+extern uint32_t am_hal_ios_host_int_enable_get(void);
+
+extern void am_hal_ios_lram_write(uint32_t ui32Offset, uint8_t ui8Value);
+extern uint8_t am_hal_ios_lram_read(uint32_t ui32Offset);
+
+// the following interrupts go back to the NVIC
+extern void am_hal_ios_config(am_hal_ios_config_t *psConfig);
+extern void am_hal_ios_access_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_access_int_enable_get(void);
+extern void am_hal_ios_access_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_ios_access_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_ios_access_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_access_int_status_get(bool bEnabledOnly);
+extern void am_hal_ios_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_int_enable_get(void);
+extern void am_hal_ios_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_ios_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_ios_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_int_status_get(bool bEnabledOnly);
+
+extern void am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes);
+extern uint32_t am_hal_ios_fifo_space_left(void);
+extern uint32_t am_hal_ios_fifo_space_used(void);
+extern void am_hal_ios_fifo_service(uint32_t ui32Status);
+// Returns the number of bytes actually written
+extern uint32_t am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes);
+extern void am_hal_ios_fifo_write_simple(uint8_t *pui8Data,
+                                         uint32_t ui32NumBytes);
+extern void am_hal_ios_fifo_ptr_set(uint32_t ui32Offset);
+extern void am_hal_ios_update_fifoctr(void);
+
+extern void am_hal_ios_read_poll_complete(void);
+extern void am_hal_ios_pwrctrl_enable(void);
+extern void am_hal_ios_pwrctrl_disable(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_IOS_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c
new file mode 100644
index 0000000000..0f57c0d417
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c
@@ -0,0 +1,453 @@
+//*****************************************************************************
+//
+//  am_hal_itm.c
+//! @file
+//!
+//! @brief Functions for operating the instrumentation trace macrocell
+//!
+//! @addtogroup itm2 Instrumentation Trace Macrocell (ITM)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Global Variables
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! @brief Delays for a desired amount of microseconds.
+//!
+//! @note - This function is based on the similar function in am_util_delay.c,
+//! please see that module for implementation details. It was necessary to
+//! duplicate it here to avoid having to update every example to include the
+//! am_util_delay.c module in its build.
+//!
+//! @returns None
+//
+//*****************************************************************************
+void
+am_hal_itm_delay_us(uint32_t ui32MicroSeconds)
+{
+    uint32_t ui32Iterations = ui32MicroSeconds *
+                              (am_hal_clkgen_sysclk_get() / 3000000);
+
+    //
+    // Call the BOOTROM cycle delay function
+    //
+    am_hal_flash_delay(ui32Iterations);
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the ITM
+//!
+//! This function enables the ARM ITM by setting the TRCENA bit in the DEMCR
+//! register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_enable(void)
+{
+    if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M)
+    {
+        return;
+    }
+
+    //
+    // To be able to access ITM registers, set the Trace Enable bit
+    // in the Debug Exception and Monitor Control Register (DEMCR).
+    //
+    AM_REG(SYSCTRL, DEMCR) |= AM_REG_SYSCTRL_DEMCR_TRCENA(1);
+    while ( !(AM_REG(SYSCTRL, DEMCR) & AM_REG_SYSCTRL_DEMCR_TRCENA(1)) );
+
+    //
+    // Write the key to the ITM Lock Access register to unlock the ITM_TCR.
+    //
+    AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL;
+
+    //
+    // Set the enable bits in the ITM trace enable register, and the ITM
+    // control registers to enable trace data output.
+    //
+    AM_REGVAL(AM_REG_ITM_TPR_O) = 0x0000000f;
+    AM_REGVAL(AM_REG_ITM_TER_O) = 0xffffffff;
+
+    //
+    // Write to the ITM control and status register (don't enable yet).
+    //
+    AM_REGVAL(AM_REG_ITM_TCR_O) =
+        AM_WRITE_SM(AM_REG_ITM_TCR_ATB_ID, 0x15)      |
+        AM_WRITE_SM(AM_REG_ITM_TCR_TS_FREQ, 1)        |
+        AM_WRITE_SM(AM_REG_ITM_TCR_TS_PRESCALE, 1)    |
+        AM_WRITE_SM(AM_REG_ITM_TCR_SWV_ENABLE, 1)     |
+        AM_WRITE_SM(AM_REG_ITM_TCR_DWT_ENABLE, 0)     |
+        AM_WRITE_SM(AM_REG_ITM_TCR_SYNC_ENABLE, 0)    |
+        AM_WRITE_SM(AM_REG_ITM_TCR_TS_ENABLE, 0)      |
+        AM_WRITE_SM(AM_REG_ITM_TCR_ITM_ENABLE, 1);
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the ITM
+//!
+//! This function completely disables the ARM ITM by resetting the TRCENA bit
+//! in the DEMCR register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_disable(void)
+{
+
+    if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M)
+    {
+        return;
+    }
+
+    //
+    // Make sure the ITM_TCR is unlocked.
+    //
+    AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL;
+
+    //
+    // Make sure the ITM/TPIU is not busy.
+    //
+    while ( AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1) );
+
+    //
+    // Disable the ITM.
+    //
+    for (int ix = 0; ix < 100; ix++)
+    {
+        AM_REG(ITM, TCR) &= ~AM_REG_ITM_TCR_ITM_ENABLE(1);
+        while ( AM_REG(ITM, TCR) & (AM_REG_ITM_TCR_ITM_ENABLE(1) | AM_REG_ITM_TCR_BUSY(1)) );
+    }
+
+    //
+    // Reset the TRCENA bit in the DEMCR register, which should disable the ITM
+    // for operation.
+    //
+    AM_REG(SYSCTRL, DEMCR) &= ~AM_REG_SYSCTRL_DEMCR_TRCENA(1);
+
+    //
+    // Disable the TPIU clock source in MCU control.
+    //
+    AM_REG(MCUCTRL, TPIUCTRL) = AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz |
+                                AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS;
+}
+
+//*****************************************************************************
+//
+//! @brief Checks if itm is busy and provides a delay to flush the fifo
+//!
+//! This function disables the ARM ITM by resetting the TRCENA bit in the DEMCR
+//! register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_not_busy(void)
+{
+    //
+    // Make sure the ITM/TPIU is not busy.
+    //
+    while (AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1));
+
+    //
+    // wait for 50us for the data to flush out
+    //
+    am_hal_itm_delay_us(50);
+}
+
+//*****************************************************************************
+//
+//! @brief Enables tracing on a given set of ITM ports
+//!
+//! @param ui8portNum - Set ports to be enabled
+//!
+//! Enables tracing on the ports referred to by \e ui8portNum by writing the
+//! associated bit in the Trace Privilege Register in the ITM. The value for
+//! ui8portNum should be the logical OR one or more of the following values:
+//!
+//! \e ITM_PRIVMASK_0_7 - enable ports 0 through 7
+//! \e ITM_PRIVMASK_8_15 - enable ports 8 through 15
+//! \e ITM_PRIVMASK_16_23 - enable ports 16 through 23
+//! \e ITM_PRIVMASK_24_31 - enable ports 24 through 31
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_trace_port_enable(uint8_t ui8portNum)
+{
+    AM_REGVAL(AM_REG_ITM_TPR_O) |= (0x00000001 << (ui8portNum>>3));
+}
+
+//*****************************************************************************
+//
+//! @brief Disable tracing on the given ITM stimulus port.
+//!
+//! @param ui8portNum
+//!
+//! Disables tracing on the ports referred to by \e ui8portNum by writing the
+//! associated bit in the Trace Privilege Register in the ITM. The value for
+//! ui8portNum should be the logical OR one or more of the following values:
+//!
+//! \e ITM_PRIVMASK_0_7 - disable ports 0 through 7
+//! \e ITM_PRIVMASK_8_15 - disable ports 8 through 15
+//! \e ITM_PRIVMASK_16_23 - disable ports 16 through 23
+//! \e ITM_PRIVMASK_24_31 - disable ports 24 through 31
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_trace_port_disable(uint8_t ui8portNum)
+{
+    AM_REGVAL(AM_REG_ITM_TPR_O) &= ~(0x00000001 << (ui8portNum >> 3));
+}
+
+//*****************************************************************************
+//
+//! @brief Poll the given ITM stimulus register until not busy.
+//!
+//! @param ui32StimReg - stimulus register
+//!
+//! @return true if not busy, false if busy (timed out or other error).
+//
+//*****************************************************************************
+bool
+am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg)
+{
+    uint32_t ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg));
+
+    //
+    // Busy waiting until it is available, non-zero means ready.
+    //
+    while (!AM_REGVAL(ui32StimAddr));
+
+    return true;
+}
+
+//*****************************************************************************
+//
+//! @brief Writes a 32-bit value to the given ITM stimulus register.
+//!
+//! @param ui32StimReg - stimulus register
+//! @param ui32Value - value to be written.
+//!
+//! Write a word to the desired stimulus register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg, uint32_t ui32Value)
+{
+    uint32_t ui32StimAddr;
+
+    ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg));
+
+    //
+    // Busy waiting until it is available, non-zero means ready
+    //
+    while (!AM_REGVAL(ui32StimAddr));
+
+    //
+    // Write the register.
+    //
+    AM_REGVAL(ui32StimAddr) = ui32Value;
+}
+
+//*****************************************************************************
+//
+//! @brief Writes a short to the given ITM stimulus register.
+//!
+//! @param ui32StimReg - stimulus register
+//! @param ui16Value - short to be written.
+//!
+//! Write a short to the desired stimulus register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg, uint16_t ui16Value)
+{
+    uint32_t ui32StimAddr;
+
+    ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg));
+
+    //
+    // Busy waiting until it is available non-zero means ready
+    //
+    while (!AM_REGVAL(ui32StimAddr));
+
+    //
+    // Write the register.
+    //
+    *((volatile uint16_t *) ui32StimAddr) = ui16Value;
+}
+
+//*****************************************************************************
+//
+//! @brief Writes a byte to the given ITM stimulus register.
+//!
+//! @param ui32StimReg - stimulus register
+//! @param ui8Value - byte to be written.
+//!
+//! Write a byte to the desired stimulus register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg, uint8_t ui8Value)
+{
+    uint32_t ui32StimAddr;
+
+    ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg));
+
+    //
+    // Busy waiting until it is available (non-zero means ready)
+    //
+    while (!AM_REGVAL(ui32StimAddr));
+
+    //
+    // Write the register.
+    //
+    *((volatile uint8_t *) ui32StimAddr) = ui8Value;
+}
+
+//*****************************************************************************
+//
+//! @brief Sends a Sync Packet.
+//!
+//! Sends a sync packet. This can be useful for external software should it
+//! become out of sync with the ITM stream.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_sync_send(void)
+{
+    //
+    // Write the register.
+    //
+    am_hal_itm_stimulus_reg_word_write(AM_HAL_ITM_SYNC_REG,
+                                       AM_HAL_ITM_SYNC_VAL);
+}
+
+//*****************************************************************************
+//
+//! @brief Poll the print stimulus registers until not busy.
+//!
+//! @return true if not busy, false if busy (timed out or other error).
+//
+//*****************************************************************************
+bool
+am_hal_itm_print_not_busy(void)
+{
+    //
+    // Poll stimulus register allocated for printing.
+    //
+    am_hal_itm_stimulus_not_busy(0);
+
+
+    return true;
+}
+
+//*****************************************************************************
+//
+//! @brief Prints a char string out of the ITM.
+//!
+//! @param pcString pointer to the character sting
+//!
+//! This function prints a sting out of the ITM.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_print(char *pcString)
+{
+    uint32_t ui32Length = 0;
+
+    //
+    // Determine the length of the string.
+    //
+    while (*(pcString + ui32Length))
+    {
+        ui32Length++;
+    }
+
+    //
+    // If there is no longer a word left, empty out the remaining characters.
+    //
+    while (ui32Length)
+    {
+            //
+            // Print string out the ITM.
+            //
+            am_hal_itm_stimulus_reg_byte_write(0, (uint8_t)*pcString++);
+
+            //
+            // Subtract from length.
+            //
+            ui32Length--;
+    }
+}
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h
new file mode 100644
index 0000000000..e747b0ab65
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h
@@ -0,0 +1,107 @@
+//*****************************************************************************
+//
+//  am_hal_itm.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the ARM ITM.
+//!
+//! @addtogroup itm2 Instrumentation Trace Macrocell (ITM)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_HAL_ITM_H
+#define AM_HAL_ITM_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Sync Packet Defines
+//
+//*****************************************************************************
+#define AM_HAL_ITM_SYNC_REG             23
+#define AM_HAL_ITM_SYNC_VAL             0xF8F8F8F8
+
+//*****************************************************************************
+//
+// PrintF Setup
+//
+//*****************************************************************************
+#define AM_HAL_ITM_PRINT_NUM_BYTES      1
+#define AM_HAL_ITM_PRINT_NUM_REGS       1
+extern uint32_t am_hal_itm_print_registers[AM_HAL_ITM_PRINT_NUM_REGS];
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_itm_delay_us(uint32_t ui32MicroSeconds);
+extern void am_hal_itm_enable(void);
+extern void am_hal_itm_disable(void);
+extern void am_hal_itm_not_busy(void);
+extern void am_hal_itm_sync_send(void);
+extern void am_hal_itm_trace_port_enable(uint8_t ui8portNum);
+extern void am_hal_itm_trace_port_disable(uint8_t ui8portNum);
+extern bool am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg);
+extern void am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg,
+                                                uint32_t ui32Value);
+extern void am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg,
+                                                uint16_t ui16Value);
+extern void am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg,
+                                                uint8_t ui8Value);
+extern bool am_hal_itm_print_not_busy(void);
+extern void am_hal_itm_print(char *pcString);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_ITM_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c
new file mode 100644
index 0000000000..f7b60e3c1a
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c
@@ -0,0 +1,292 @@
+//*****************************************************************************
+//
+//  am_hal_mcuctrl.c
+//! @file
+//!
+//! @brief Functions for interfacing with the MCUCTRL.
+//!
+//! @addtogroup mcuctrl2 MCU Control (MCUCTRL)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+#define LDO_TRIM_REG_ADDR   (0x50023004)
+#define BUCK_TRIM_REG_ADDR  (0x50023000)
+
+//*****************************************************************************
+//
+// Global Variables.
+//
+//*****************************************************************************
+//
+// Define the flash sizes from CHIP_INFO.
+//
+const uint32_t g_am_hal_mcuctrl_flash_size[16] =
+{
+     16 * 1024,             /* 0x0 0x00004000   16 KB */
+     32 * 1024,             /* 0x1 0x00008000   32 KB */
+     64 * 1024,             /* 0x2 0x00010000   64 KB */
+    128 * 1024,             /* 0x3 0x00020000  128 KB */
+    256 * 1024,             /* 0x4 0x00040000  256 KB */
+    512 * 1024,             /* 0x5 0x00080000  512 KB */
+      1 * 1024 * 1024,      /* 0x6 0x00100000    1 MB */
+      2 * 1024 * 1024,      /* 0x7 0x00200000    2 MB */
+      4 * 1024 * 1024,      /* 0x8 0x00400000    4 MB */
+      8 * 1024 * 1024,      /* 0x9 0x00800000    8 MB */
+     16 * 1024 * 1024,      /* 0xA 0x01000000    16 MB */
+     32 * 1024 * 1024,      /* 0xB 0x02000000    32 MB */
+     64 * 1024 * 1024,      /* 0xC 0x04000000    64 MB */
+    128 * 1024 * 1024,      /* 0xD 0x08000000   128 MB */
+    256 * 1024 * 1024,      /* 0xE 0x10000000   256 MB */
+    512 * 1024 * 1024       /* 0xF 0x20000000   512 MB */
+};
+
+//
+// Define the SRAM sizes from CHIP_INFO.
+// For Apollo2, the SRAM sizes are defined exactly the same as the flash sizes.
+//
+#define g_am_hal_mcuctrl_sram_size  g_am_hal_mcuctrl_flash_size
+
+//*****************************************************************************
+//
+//! @brief Gets all relevant device information.
+//!
+//! @param psDevice is a pointer to a structure that will be used to store all
+//! device info.
+//!
+//! This function gets the device part number, chip IDs, and revision and
+//! stores them in the passed structure.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_mcuctrl_device_info_get(am_hal_mcuctrl_device_t *psDevice)
+{
+    //
+    // Read the Part Number.
+    //
+    psDevice->ui32ChipPN = AM_REG(MCUCTRL, CHIP_INFO);
+
+    //
+    // Read the Chip ID0.
+    //
+    psDevice->ui32ChipID0 = AM_REG(MCUCTRL, CHIPID0);
+
+    //
+    // Read the Chip ID1.
+    //
+    psDevice->ui32ChipID1 = AM_REG(MCUCTRL, CHIPID1);
+
+    //
+    // Read the Chip Revision.
+    //
+    psDevice->ui32ChipRev = AM_REG(MCUCTRL, CHIPREV);
+
+    //
+    // Read the Part Number.
+    //
+    psDevice->ui32ChipPN = AM_REG(MCUCTRL, CHIP_INFO);
+
+    //
+    // Read the Chip ID0.
+    //
+    psDevice->ui32ChipID0 = AM_REG(MCUCTRL, CHIPID0);
+
+    //
+    // Read the Chip ID1.
+    //
+    psDevice->ui32ChipID1 = AM_REG(MCUCTRL, CHIPID1);
+
+    //
+    // Read the Chip Revision.
+    //
+    psDevice->ui32ChipRev = AM_REG(MCUCTRL, CHIPREV);
+
+    //
+    // Read the Chip VENDOR ID.
+    //
+    psDevice->ui32VendorID = AM_REG(MCUCTRL, VENDORID);
+
+    //
+    // Qualified from Part Number.
+    //
+    psDevice->ui32Qualified =
+            (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_QUAL_M) >>
+             AM_HAL_MCUCTRL_CHIP_INFO_QUAL_S;
+
+    //
+    // Flash size from Part Number.
+    //
+    psDevice->ui32FlashSize =
+        g_am_hal_mcuctrl_flash_size[
+            (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_M) >>
+            AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_S];
+
+    //
+    // SRAM size from Part Number.
+    //
+    psDevice->ui32SRAMSize =
+        g_am_hal_mcuctrl_flash_size[
+            (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_M) >>
+            AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_S];
+
+    //
+    // Now, let's look at the JEDEC info.
+    // The full partnumber is 12 bits total, but is scattered across 2 registers.
+    // Bits [11:8] are 0xE.
+    // Bits [7:4] are 0xE for Apollo, 0xD for Apollo2.
+    // Bits [3:0] are defined differently for Apollo and Apollo2.
+    //   For Apollo, the low nibble is 0x0.
+    //   For Apollo2, the low nibble indicates flash and SRAM size.
+    //
+    psDevice->ui32JedecPN  = (AM_BFR(JEDEC, PID0, PNL8) << 0);
+    psDevice->ui32JedecPN |= (AM_BFR(JEDEC, PID1, PNH4) << 8);
+
+    //
+    // JEPID is the JEP-106 Manufacturer ID Code, which is assigned to Ambiq as
+    //  0x1B, with parity bit is 0x9B.  It is 8 bits located across 2 registers.
+    //
+    psDevice->ui32JedecJEPID  = (AM_BFR(JEDEC, PID1, JEPIDL) << 0);
+    psDevice->ui32JedecJEPID |= (AM_BFR(JEDEC, PID2, JEPIDH) << 4);
+
+    //
+    // CHIPREV is 8 bits located across 2 registers.
+    //
+    psDevice->ui32JedecCHIPREV  = (AM_BFR(JEDEC, PID2, CHIPREVH4) << 4);
+    psDevice->ui32JedecCHIPREV |= (AM_BFR(JEDEC, PID3, CHIPREVL4) << 0);
+
+    //
+    // Let's get the Coresight ID (32-bits across 4 registers)
+    // For Apollo and Apollo2, it's expected to be 0xB105100D.
+    //
+    psDevice->ui32JedecCID  = (AM_BFR(JEDEC, CID3, CID) << 24);
+    psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID2, CID) << 16);
+    psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID1, CID) <<  8);
+    psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID0, CID) <<  0);
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the fault capture registers.
+//!
+//! This function enables the DCODEFAULTADDR and ICODEFAULTADDR registers.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_mcuctrl_fault_capture_enable(void)
+{
+    //
+    // Enable the Fault Capture registers.
+    //
+    AM_BFW(MCUCTRL, FAULTCAPTUREEN, ENABLE, 1);
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the fault capture registers.
+//!
+//! This function disables the DCODEFAULTADDR and ICODEFAULTADDR registers.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_mcuctrl_fault_capture_disable(void)
+{
+    //
+    // Disable the Fault Capture registers.
+    //
+    AM_BFW(MCUCTRL, FAULTCAPTUREEN, ENABLE, 0);
+}
+
+//*****************************************************************************
+//
+//! @brief Gets the fault status and capture registers.
+//!
+//! @param psFault is a pointer to a structure that will be used to store all
+//! fault info.
+//!
+//! This function gets the status of the ICODE, DCODE, and SYS bus faults and
+//! the addresses associated with the fault.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault)
+{
+    uint32_t ui32FaultStat;
+
+    //
+    // Read the Fault Status Register.
+    //
+    ui32FaultStat = AM_REG(MCUCTRL, FAULTSTATUS);
+    psFault->bICODE = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_ICODE_M);
+    psFault->bDCODE = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_DCODE_M);
+    psFault->bSYS = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_SYS_M);
+
+    //
+    // Read the DCODE fault capture address register.
+    //
+    psFault->ui32DCODE = AM_REG(MCUCTRL, DCODEFAULTADDR);
+
+    //
+    // Read the ICODE fault capture address register.
+    //
+    psFault->ui32ICODE |= AM_REG(MCUCTRL, ICODEFAULTADDR);
+
+    //
+    // Read the ICODE fault capture address register.
+    //
+    psFault->ui32SYS |= AM_REG(MCUCTRL, SYSFAULTADDR);
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h
new file mode 100644
index 0000000000..6811006fd6
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h
@@ -0,0 +1,212 @@
+//*****************************************************************************
+//
+//  am_hal_mcuctrl.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the MCUCTRL.
+//!
+//! @addtogroup mcuctrl2 MCU Control (MCUCTRL)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_MCUCTRL_H
+#define AM_HAL_MCUCTRL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//
+// Deprecate the am_hal_mcuctrl_bucks_enable() and disable() functions.
+// This functionality is now handled in pwrctrl.
+//
+#define am_hal_mcuctrl_bucks_enable     am_hal_pwrctrl_bucks_enable
+#define am_hal_mcuctrl_bucks_disable    am_hal_pwrctrl_bucks_disable
+
+
+//*****************************************************************************
+//
+// Define CHIP_INFO fields, which for Apollo2 are not defined in the register
+// definitions.
+//
+//*****************************************************************************
+#define AM_HAL_MCUCTRL_CHIP_INFO_CLASS_M        0xFF000000
+#define AM_HAL_MCUCTRL_CHIP_INFO_CLASS_S        24
+#define AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_M   0x00F00000
+#define AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_S   20
+#define AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_M    0x000F0000
+#define AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_S    16
+#define AM_HAL_MCUCTRL_CHIP_INFO_REV_M          0x0000FF00
+#define AM_HAL_MCUCTRL_CHIP_INFO_REV_S          8
+#define AM_HAL_MCUCTRL_CHIP_INFO_PKG_M          0x000000C0
+#define AM_HAL_MCUCTRL_CHIP_INFO_PKG_S          6
+#define AM_HAL_MCUCTRL_CHIP_INFO_PINS_M         0x00000038
+#define AM_HAL_MCUCTRL_CHIP_INFO_PINS_S         3
+#define AM_HAL_MCUCTRL_CHIP_INFO_TEMP_M         0x00000006
+#define AM_HAL_MCUCTRL_CHIP_INFO_TEMP_S         1
+#define AM_HAL_MCUCTRL_CHIP_INFO_QUAL_M         0x00000001
+#define AM_HAL_MCUCTRL_CHIP_INFO_QUAL_S         0
+
+//*****************************************************************************
+//
+// Apollo Number Decode.
+//
+//*****************************************************************************
+extern const uint32_t g_am_hal_mcuctrl_flash_size[];
+extern const uint32_t g_am_hal_mcuctrl_sram_size[];
+
+//*****************************************************************************
+//
+//! MCUCTRL device structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Device part number. (BCD format)
+    //
+    uint32_t ui32ChipPN;
+
+    //
+    //! Unique Chip ID 0.
+    //
+    uint32_t ui32ChipID0;
+
+    //
+    //! Unique Chip ID 1.
+    //
+    uint32_t ui32ChipID1;
+
+    //
+    //! Chip Revision.
+    //
+    uint32_t ui32ChipRev;
+
+    //
+    //! Vendor ID.
+    //
+    uint32_t ui32VendorID;
+
+    //
+    //! Qualified chip.
+    //
+    uint32_t ui32Qualified;
+
+    //
+    //! Flash Size.
+    //
+    uint32_t ui32FlashSize;
+
+    //
+    //! SRAM Size.
+    //
+    uint32_t ui32SRAMSize;
+
+    //
+    // JEDEC chip info
+    //
+    uint32_t ui32JedecPN;
+    uint32_t ui32JedecJEPID;
+    uint32_t ui32JedecCHIPREV;
+    uint32_t ui32JedecCID;
+}
+am_hal_mcuctrl_device_t;
+
+//*****************************************************************************
+//
+//! MCUCTRL fault structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! ICODE bus fault occurred.
+    //
+    bool bICODE;
+
+    //
+    //! ICODE bus fault address.
+    //
+    uint32_t ui32ICODE;
+
+    //
+    //! DCODE bus fault occurred.
+    //
+    bool bDCODE;
+
+    //
+    //! DCODE bus fault address.
+    //
+    uint32_t ui32DCODE;
+
+    //
+    //! SYS bus fault occurred.
+    //
+    bool bSYS;
+
+    //
+    //! SYS bus fault address.
+    //
+    uint32_t ui32SYS;
+}
+am_hal_mcuctrl_fault_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_mcuctrl_device_info_get(am_hal_mcuctrl_device_t *psDevice);
+extern void am_hal_mcuctrl_fault_capture_enable(void);
+extern void am_hal_mcuctrl_fault_capture_disable(void);
+extern void am_hal_mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_MCUCTRL_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c
new file mode 100644
index 0000000000..67d08448da
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c
@@ -0,0 +1,173 @@
+//*****************************************************************************
+//
+//  am_hal_otp.c
+//! @file
+//!
+//! @brief Functions for handling the OTP interface.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#include "am_mcu_apollo.h"
+#include "am_hal_flash.h"
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Check if debugger is currently locked out.
+//
+// @param None.
+//
+// Determine if the debugger is already locked out.
+//
+// @return non-zero if debugger is currently locked out.
+//     Specifically:
+//     0 = debugger is not locked out.
+//     1 = debugger is locked out.
+//
+//*****************************************************************************
+int
+am_hal_otp_is_debugger_lockedout(void)
+{
+    return am_hal_flash_debugger_disable_check();
+}
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Lock out debugger access.
+//
+// @param None.
+//
+// This function locks out access by a debugger.
+//
+// @return 0 if lockout was successful or if lockout was already enabled.
+//
+//*****************************************************************************
+int
+am_hal_otp_debugger_lockout(void)
+{
+    return am_hal_flash_debugger_disable();
+}
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Lock out SRAM access.
+//
+// @param None.
+//
+// This function locks out access by a debugger to SRAM.
+//
+// @return 0 if lockout was successful or if lockout was already enabled.
+//         Low byte=0xff, byte 1 contains current value of lockout.
+//         Else, return value from HAL programming function.
+//
+//*****************************************************************************
+int
+am_hal_otp_sram_lockout(void)
+{
+    return am_hal_flash_wipe_sram_enable();
+}
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Set copy (read) protection.
+//
+// @param @u32BegAddr The beginning address to be copy protected.
+//        @u32EndAddr The ending address to be copy protected.
+//
+// @note For Apollo, the u32BegAddr parameter should be on a 16KB boundary, and
+//       the u32EndAddr parameter should be on a (16KB-1) boundary. Otherwise
+//       both parameters will be truncated/expanded to do so.
+//       For example, if u32BegAddr=0x1000 and u32EndAddr=0xC200, the actual
+//       range that protected is: 0x0 - 0xFFFF.
+//
+// This function enables copy protection on a given flash address range.
+//
+// @return 0 if copy protection was successfully enabled.
+//
+//*****************************************************************************
+int
+am_hal_otp_set_copy_protection(uint32_t u32BegAddr, uint32_t u32EndAddr)
+{
+    return am_hal_flash_copy_protect_set((uint32_t*)u32BegAddr,
+                                         (uint32_t*)u32EndAddr);
+}
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Set write protection.
+//
+// @param @u32BegAddr The beginning address to be write protected.
+//        @u32EndAddr The ending address to be write protected.
+//
+// @note For Apollo, the u32BegAddr parameter should be on a 16KB boundary, and
+//       the u32EndAddr parameter should be on a (16KB-1) boundary. Otherwise
+//       both parameters will be truncated/expanded to do so.
+//       For example, if u32BegAddr=0x1000 and u32EndAddr=0xC200, the actual
+//       range that protected is: 0x0 - 0xFFFF.
+//
+// This function enables write protection on a given flash address range.
+//
+// @return 0 if write protection was successfully enabled.
+//
+//*****************************************************************************
+int
+am_hal_otp_set_write_protection(uint32_t u32BegAddr, uint32_t u32EndAddr)
+{
+    return am_hal_flash_write_protect_set((uint32_t*)u32BegAddr,
+                                          (uint32_t*)u32EndAddr);
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h
new file mode 100644
index 0000000000..d938e916fb
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h
@@ -0,0 +1,108 @@
+//*****************************************************************************
+//
+//  am_hal_otp.h
+//! @file
+//!
+//! @brief Functions for handling the OTP interface.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_OTP_H
+#define AM_HAL_OTP_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Define some OTP values and macros.
+//
+//*****************************************************************************
+#define AM_HAL_OTP_SIG0             0x00
+#define AM_HAL_OTP_SIG1             0x04
+#define AM_HAL_OTP_SIG2             0x08
+#define AM_HAL_OTP_SIG3             0x0C
+
+#define AM_HAL_OTP_DBGR_O           0x10
+#define AM_HAL_OTP_WRITPROT0_O      0x20
+#define AM_HAL_OTP_WRITPROT1_O      0x24
+#define AM_HAL_OTP_COPYPROT0_O      0x30
+#define AM_HAL_OTP_COPYPROT1_O      0x34
+
+#define AM_HAL_OTP_ADDR             0x50020000
+#define AM_HAL_OTP_DBGRPROT_ADDR    (AM_HAL_OTP_ADDR + AM_HAL_OTP_DBGR_O)
+#define AM_HAL_OTP_WRITPROT_ADDR    (AM_HAL_OTP_ADDR + AM_HAL_OTP_WRITPROT0_O)
+#define AM_HAL_OTP_COPYPROT_ADDR    (AM_HAL_OTP_ADDR + AM_HAL_OTP_COPYPROT0_O)
+
+#define AM_HAL_OTP_CHUNKSIZE        (16*1024)
+
+//
+// Debugger port lockout macros.
+//
+#define AM_OTP_DBGR_LOCKOUT_S       (0)
+#define AM_OTP_DBGR_LOCKOUT_M       (0x1 << AM_OTP_DBGR_LOCKOUT_S)
+#define AM_OTP_STRM_LOCKOUT_S       (1)
+#define AM_OTP_STRM_LOCKOUT_M       (0x1 << AM_OTP_STRM_LOCKOUT_S)
+#define AM_OTP_SRAM_LOCKOUT_S       (2)
+#define AM_OTP_SRAM_LOCKOUT_M       (0x1 << AM_OTP_SRAM_LOCKOUT_S)
+
+//*****************************************************************************
+//
+// Function prototypes
+//
+//*****************************************************************************
+extern int am_hal_otp_is_debugger_lockedout(void);
+extern int am_hal_otp_debugger_lockout(void);
+extern int am_hal_otp_sram_lockout(void);
+extern int am_hal_otp_set_copy_protection(uint32_t u32BegAddr, uint32_t u32EndAddr);
+extern int am_hal_otp_set_write_protection(uint32_t u32BegAddr, uint32_t u32EndAddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_OTP_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c
new file mode 100644
index 0000000000..45acfab995
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c
@@ -0,0 +1,158 @@
+//*****************************************************************************
+//
+//  am_hal_pdm.c
+//! @file
+//!
+//! @brief Functions for interfacing with Pulse Density Modulation (PDM).
+//!
+//! @addtogroup pdm2 DMEMS Microphon3 (PDM)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Configure the PDM module.
+//!
+//! This function reads the an \e am_hal_pdm_config_t structure and uses it to
+//! set up the PDM module.
+//!
+//! Please see the information on the am_hal_pdm_config_t configuration
+//! structure, found in am_hal_pdm.h, for more information on the parameters
+//! that may be set by this function.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_pdm_config(am_hal_pdm_config_t *psConfig)
+{
+    //
+    // setup the PDM PCFG register
+    //
+    AM_REG(PDM, PCFG) = psConfig->ui32PDMConfigReg;
+
+    //
+    // setup the PDM VCFG register
+    //
+    AM_REG(PDM, VCFG) = psConfig->ui32VoiceConfigReg;
+
+    //
+    // setup the PDM FIFO Threshold register
+    //
+    AM_REG(PDM, FTHR) = psConfig->ui32FIFOThreshold;
+
+    //
+    // Flush the FIFO for good measure.
+    //
+    am_hal_pdm_fifo_flush();
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the PDM module.
+//!
+//! This function enables the PDM module in the mode previously defined by
+//! am_hal_pdm_config().
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_pdm_enable(void)
+{
+    AM_REG(PDM, PCFG) |=  AM_REG_PDM_PCFG_PDMCORE_EN;
+    AM_REG(PDM, VCFG) |=  ( AM_REG_PDM_VCFG_IOCLKEN_EN      |
+                            AM_REG_PDM_VCFG_PDMCLK_EN       |
+                            AM_REG_PDM_VCFG_RSTB_NORM );
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the PDM module.
+//!
+//! This function disables the PDM module.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_pdm_disable(void)
+{
+    AM_REG(PDM, PCFG) &= ~ AM_REG_PDM_PCFG_PDMCORE_EN;
+    AM_REG(PDM, VCFG) &= ~ (  AM_REG_PDM_VCFG_IOCLKEN_EN    |
+                              AM_REG_PDM_VCFG_PDMCLK_EN     |
+                              AM_REG_PDM_VCFG_RSTB_NORM );
+}
+
+//*****************************************************************************
+//
+//! @brief Return the PDM Interrupt status.
+//!
+//! @param bEnabledOnly - return only the enabled interrupts.
+//!
+//! Use this function to get the PDM interrupt status.
+//!
+//! @return intrrupt status
+//
+//*****************************************************************************
+uint32_t
+am_hal_pdm_int_status_get(bool bEnabledOnly)
+{
+    if ( bEnabledOnly )
+    {
+        uint32_t u32RetVal = AM_REG(PDM, INTSTAT);
+        return u32RetVal & AM_REG(PDM, INTEN);
+    }
+    else
+    {
+        return AM_REG(PDM, INTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//  End the doxygen group
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h
new file mode 100644
index 0000000000..a6e23d2698
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h
@@ -0,0 +1,665 @@
+//*****************************************************************************
+//
+//  am_hal_pdm.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the PDM module
+//!
+//! @addtogroup pdm2 Pulse Density Modulation (PDM) Input Module.
+//! @ingroup apollo2hal
+//! @{
+
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_HAL_PDM_H
+#define AM_HAL_PDM_H
+
+//*****************************************************************************
+//
+// Macro definitions
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! @name PDM Left Right Swap Control
+//! @brief Macro definitions for the PDM LRSWAP bit field
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! left right swap bit.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_LRSWAP_ENABLE                                         \
+              AM_REG_PDM_PCFG_LRSWAP_EN
+#define AM_HAL_PDM_PCFG_LRSWAP_DISABLE                                        \
+              AM_REG_PDM_PCFG_LRSWAP_NOSWAP
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Right Gain Setting
+//! @brief Macro definitions for the PDM Right Gain Setting.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! right gain value.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_M15DB   AM_REG_PDM_PCFG_PGARIGHT_M15DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_M300DB  AM_REG_PDM_PCFG_PGARIGHT_M300DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_M45DB   AM_REG_PDM_PCFG_PGARIGHT_M45DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_M60DB   AM_REG_PDM_PCFG_PGARIGHT_M60DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_M75DB   AM_REG_PDM_PCFG_PGARIGHT_M75DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_M90DB   AM_REG_PDM_PCFG_PGARIGHT_M90DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_M105DB  AM_REG_PDM_PCFG_PGARIGHT_M105DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_M120DB  AM_REG_PDM_PCFG_PGARIGHT_M120DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_P105DB  AM_REG_PDM_PCFG_PGARIGHT_P105DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_P90DB   AM_REG_PDM_PCFG_PGARIGHT_P90DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_P75DB   AM_REG_PDM_PCFG_PGARIGHT_P75DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_P60DB   AM_REG_PDM_PCFG_PGARIGHT_P60DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_P45DB   AM_REG_PDM_PCFG_PGARIGHT_P45DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_P300DB  AM_REG_PDM_PCFG_PGARIGHT_P300DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_P15DB   AM_REG_PDM_PCFG_PGARIGHT_P15DB
+#define AM_HAL_PDM_PCFG_RIGHT_PGA_0DB     AM_REG_PDM_PCFG_PGARIGHT_0DB
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Left Gain Setting
+//! @brief Macro definitions for the PDM Left Gain Setting.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! left gain value.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_LEFT_PGA_M15DB   AM_REG_PDM_PCFG_PGALEFT_M15DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_M300DB  AM_REG_PDM_PCFG_PGALEFT_M300DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_M45DB   AM_REG_PDM_PCFG_PGALEFT_M45DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_M60DB   AM_REG_PDM_PCFG_PGALEFT_M60DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_M75DB   AM_REG_PDM_PCFG_PGALEFT_M75DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_M90DB   AM_REG_PDM_PCFG_PGALEFT_M90DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_M105DB  AM_REG_PDM_PCFG_PGALEFT_M105DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_M120DB  AM_REG_PDM_PCFG_PGALEFT_M120DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_P105DB  AM_REG_PDM_PCFG_PGALEFT_P105DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_P90DB   AM_REG_PDM_PCFG_PGALEFT_P90DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_P75DB   AM_REG_PDM_PCFG_PGALEFT_P75DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_P60DB   AM_REG_PDM_PCFG_PGALEFT_P60DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_P45DB   AM_REG_PDM_PCFG_PGALEFT_P45DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_P300DB  AM_REG_PDM_PCFG_PGALEFT_P300DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_P15DB   AM_REG_PDM_PCFG_PGALEFT_P15DB
+#define AM_HAL_PDM_PCFG_LEFT_PGA_0DB     AM_REG_PDM_PCFG_PGALEFT_0DB
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Configuration MCLK Divider
+//! @brief Macro definitions for the PDM MCLK Divider
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! sinc decimation rate relative to the PDM sample clock (OSR).
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_MCLKDIV_DIV1    AM_REG_PDM_PCFG_MCLKDIV_MCKDIV1
+#define AM_HAL_PDM_PCFG_MCLKDIV_DIV2    AM_REG_PDM_PCFG_MCLKDIV_MCKDIV2
+#define AM_HAL_PDM_PCFG_MCLKDIV_DIV3    AM_REG_PDM_PCFG_MCLKDIV_MCKDIV3
+#define AM_HAL_PDM_PCFG_MCLKDIV_DIV4    AM_REG_PDM_PCFG_MCLKDIV_MCKDIV4
+
+#define AM_HAL_PDM_PCFG_MCLKDIV(DIV)    AM_REG_PDM_PCFG_MCLKDIV(DIV)
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Configuration SINC Decimation Rate
+//! @brief Macro definitions for the PDM SINC decimation rate
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! sinc decimation rate relative to the PDM sample clock (OSR).
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_SINC_RATE(OSR)                                        \
+              AM_REG_PDM_PCFG_SINCRATE(OSR)
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Configuration High Pass Filter Enable
+//! @brief Macro definitions for the PDM ADCHPD
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to enable
+//! the high pass filter.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_ADCHPD_ENABLE  AM_REG_PDM_PCFG_ADCHPD_EN
+#define AM_HAL_PDM_PCFG_ADCHPD_DISABLE AM_REG_PDM_PCFG_ADCHPD_DIS
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Configuration HPCUTOFF
+//! @brief Macro definitions for the PDM High Pass Filter Cutoff Selector.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! high pass filter cutoff frequency. Valid range is 0 to 7.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_HPCUTOFF(HPSEL)                                       \
+              AM_REG_PDM_PCFG_HPCUTOFF(HPSEL)
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Configuration Gain Set Change Clock Delay
+//! @brief Macro definitions for the PDM clock delay for gain set changes.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! number of clocks for spreading gain setting changes. Valid range is 0 to 7.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_CYCLES(CLOCKS)                                        \
+              AM_REG_PDM_PCFG_CYCLES(CLOCKS)
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Configuration SOFTMUTE enable/disable.
+//! @brief Macro definitions for the PDM PCFG register mute controls.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to enable
+//! or disable the SOFTMUTE option.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_SOFTMUTE_ENABLE  AM_REG_PDM_PCFG_SOFTMUTE_EN
+#define AM_HAL_PDM_PCFG_SOFTMUTE_DISABLE AM_REG_PDM_PCFG_SOFTMUTE_DIS
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Configuration PDM Core enable/disable.
+//! @brief Macro definitions for the PDM PCFG register filter engine enable.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to enable
+//! or disable the PDM filter engine core.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_PCFG_PDMCORE_ENABLE  AM_REG_PDM_PCFG_PDMCORE_EN
+#define AM_HAL_PDM_PCFG_PDMCORE_DISABLE AM_REG_PDM_PCFG_PDMCORE_DIS
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Clock Frequencies
+//! @brief Macro definitions for the PDM clock (from clkgen) frequencies.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! source clock frequency of the PDM interface.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_IOCLK_12MHZ                                              \
+        (AM_REG_PDM_VCFG_PDMCLKSEL_12MHz | AM_REG_PDM_VCFG_IOCLKEN_EN)
+#define AM_HAL_PDM_IOCLK_6MHZ                                               \
+        (AM_REG_PDM_VCFG_PDMCLKSEL_6MHz | AM_REG_PDM_VCFG_IOCLKEN_EN)
+#define AM_HAL_PDM_IOCLK_3MHZ                                               \
+        (AM_REG_PDM_VCFG_PDMCLKSEL_3MHz | AM_REG_PDM_VCFG_IOCLKEN_EN)
+#define AM_HAL_PDM_IOCLK_1_5MHZ                                             \
+        (AM_REG_PDM_VCFG_PDMCLKSEL_1_5MHz | AM_REG_PDM_VCFG_IOCLKEN_EN)
+#define AM_HAL_PDM_IOCLK_750KHZ                                             \
+        (AM_REG_PDM_VCFG_PDMCLKSEL_750KHz | AM_REG_PDM_VCFG_IOCLKEN_EN)
+#define AM_HAL_PDM_IOCLK_375KHZ                                             \
+        (AM_REG_PDM_VCFG_PDMCLKSEL_375KHz | AM_REG_PDM_VCFG_IOCLKEN_EN)
+#define AM_HAL_PDM_IOCLK_187KHZ                                             \
+        (AM_REG_PDM_VCFG_PDMCLKSEL_187KHz | AM_REG_PDM_VCFG_IOCLKEN_EN)
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Voice Configuration RSTB
+//! @brief Reset the IP core.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_VCFG_RSTB_RESET      AM_REG_PDM_VCFG_RSTB_RESET
+#define AM_HAL_PDM_VCFG_RSTB_NORMAL     AM_REG_PDM_VCFG_RSTB_NORM
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Voice Configuration PDM Clock Enable/Disable
+//! @brief Macro definitions for the PDM VCFG register PDMCLKEN.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to enable
+//! or disable the PDM clock output to the pad mux and from there to the world.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_VCFG_PDMCLK_ENABLE  AM_REG_PDM_VCFG_PDMCLK_EN
+#define AM_HAL_PDM_VCFG_PDMCLK_DISABLE AM_REG_PDM_VCFG_PDMCLK_DIS
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Voice Configuration I2S Mode Enable/Disable
+//! @brief Macro definitions for the PDM VCFG register I2SMODE.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to enable
+//! or disable the PDM clock output to the pad mux and from there to the world.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_VCFG_I2SMODE_ENABLE  AM_REG_PDM_VCFG_I2SMODE_EN
+#define AM_HAL_PDM_VCFG_I2SMODE_DISABLE AM_REG_PDM_VCFG_I2SMODE_DIS
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Voice Configuration BCLK Inversion Enable/Disable
+//! @brief Macro definitions for the PDM VCFG register BCLKINV.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to enable
+//! or disable the PDM clock output to the pad mux and from there to the world.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_VCFG_BCLKINV_ENABLE  AM_REG_PDM_VCFG_BCLKINV_INV
+#define AM_HAL_PDM_VCFG_BCLKINV_DISABLE AM_REG_PDM_VCFG_BCLKINV_NORM
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Voice Configuration DMICDEL Enable/Disable
+//! @brief Macro definitions for the PDM VCFG register Digital Mic Delay.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to enable
+//! or disable the PDM digital microphone clock delay.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_VCFG_DMICDEL_1CYC    AM_REG_PDM_VCFG_DMICKDEL_1CYC
+#define AM_HAL_PDM_VCFG_DMICDEL_0CYC    AM_REG_PDM_VCFG_DMICKDEL_0CYC
+#define AM_HAL_PDM_VCFG_DMICDEL_ENABLE  AM_REG_PDM_VCFG_DMICKDEL_1CYC
+#define AM_HAL_PDM_VCFG_DMICDEL_DISABLE AM_REG_PDM_VCFG_DMICKDEL_0CYC
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Voice Configuration Select Apps Processor (AP) versus Internal
+//! @brief Macro definitions for the PDM VCFG register Digital Mic Delay.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to select
+//! the Application Processor (I2S slave) mode or the Internal FIFO interface
+//! to the Apollo Cortex M4.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_VCFG_SELAP_I2S       AM_REG_PDM_VCFG_SELAP_I2S
+#define AM_HAL_PDM_VCFG_SELAP_INTERNAL  AM_REG_PDM_VCFG_SELAP_INTERNAL
+#define AM_HAL_PDM_VCFG_SELAP_AP_I2S    AM_REG_PDM_VCFG_SELAP_I2S
+#define AM_HAL_PDM_VCFG_SELAP_CM4_FIFO  AM_REG_PDM_VCFG_SELAP_INTERNAL
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Voice Configuration PACK Enable/Disable
+//! @brief Macro definitions for the PDM VCFG register sample packing mode.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to enable
+//! or disable the PDM sample packing mode. This mode puts two 16-bit samples
+//! per 32-bit FIFO word. The following packed modes are available:
+//!
+//!   mono left:            LEFT_NEW, LEFT_OLD
+//!   mono right:           RIGHT_NEW,RIGHT_OLD
+//!   stereo right:         LEFT,     RIGHT
+//!   stereo right(LRSWAP): RIGHT,    LEFT
+//!
+//!
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_VCFG_PACK_ENABLE  AM_REG_PDM_VCFG_PCMPACK_EN
+#define AM_HAL_PDM_VCFG_PACK_DISABLE AM_REG_PDM_VCFG_PCMPACK_DIS
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Channel Selects
+//! @brief Macro definitions for the PDM Channel Selection.
+//!
+//! These macros may be used with the am_hal_pdm_config_t structure to set the
+//! channel selection for the PDM interface.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_VCFG_CHANNEL_LEFT   AM_REG_PDM_VCFG_CHSET_LEFT
+#define AM_HAL_PDM_VCFG_CHANNEL_RIGHT  AM_REG_PDM_VCFG_CHSET_RIGHT
+#define AM_HAL_PDM_VCFG_CHANNEL_STEREO AM_REG_PDM_VCFG_CHSET_STEREO
+//! @}
+
+//*****************************************************************************
+//
+//! @name PDM Interrupts
+//! @brief Macro definitions for the PDM interrupt status bits.
+//!
+//! These macros correspond to the bits in the PDM interrupt status register.
+//! They may be used for any of the am_hal_pdm_int_x() functions.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_PDM_INT_UNDFL AM_REG_PDM_INTEN_UNDFL_M
+#define AM_HAL_PDM_INT_OVF   AM_REG_PDM_INTEN_OVF_M
+#define AM_HAL_PDM_INT_FIFO  AM_REG_PDM_INTEN_THR_M
+//! @}
+
+//*****************************************************************************
+//
+//! @brief Configuration structure for the PDM module.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! @brief Set the PDM configuration reg with the values in this member.
+    //! Choose from AM_HAL_PDM_PCFG macros.
+    //!     AM_HAL_PDM_PCFG_LRSWAP_xxx
+    //!     AM_HAL_PDM_PCFG_RIGHT_PGA_xxx
+    //!     AM_HAL_PDM_PCFG_LEFT_PGA_xxx
+    //!     AM_HAL_PDM_PCFG_MCLKDIV_xxx
+    //!     AM_HAL_PDM_PCFG_SINC_RATE()
+    //!     AM_HAL_PDM_PCFG_ADCHPD_xxx
+    //!     AM_HAL_PDM_PCFG_HPCUTOFF()
+    //!     AM_HAL_PDM_PCFG_CYCLES()
+    //!     AM_HAL_PDM_PCFG_SOFTMUTE_xxx
+    //!   * AM_HAL_PDM_PCFG_PDMCORE_EN
+    //!     AM_HAL_PDM_PCFG_PDMCORE_DISABLE
+    //
+    uint32_t ui32PDMConfigReg;
+
+    //
+    //! @brief Set the Voice Configuration reg with the values in this member.
+    //! Choose from AM_HAL_PDM_VCFG macros.
+    //!     AM_HAL_PDM_IOCLK_xxx (also sets AM_REG_PDM_VCFG_IOCLKEN_EN)
+    //!   * AM_REG_PDM_VCFG_IOCLKEN_EN
+    //!   * AM_HAL_PDM_VCFG_RSTB_RESET
+    //!     AM_HAL_PDM_VCFG_RSTB_NORMAL
+    //!   * AM_HAL_PDM_VCFG_PDMCLK_EN
+    //!     AM_HAL_PDM_VCFG_PDMCLK_DIS
+    //!     AM_HAL_PDM_VCFG_I2SMODE_xxx
+    //!     AM_HAL_PDM_VCFG_BCLKINV_xxx
+    //!     AM_HAL_PDM_VCFG_DMICDEL_xxx
+    //!     AM_HAL_PDM_VCFG_SELAP_xxx
+    //!     AM_HAL_PDM_VCFG_PACK_xxx
+    //!     AM_HAL_PDM_VCFG_CHANNEL_xxx
+    //!
+    //! * = These bits are set or cleared by the HAL PDM functions
+    //!     am_hal_pdm_enable() or am_hal_pdm_disable().
+    //
+    uint32_t ui32VoiceConfigReg;
+
+    //
+    //! @brief Select the FIFO PCM sample threshold.
+    //!
+    //! The PDM controller will generate a processor interrupt when the number
+    //! of entries in the FIFO goes *above* this number.
+    //
+    uint32_t ui32FIFOThreshold;
+} am_hal_pdm_config_t;
+
+//*****************************************************************************
+//
+// Define function-like macros.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! @brief Read the FIFO depth information as an in-line macro
+//
+//*****************************************************************************
+#define am_hal_pdm_fifo_depth_read()    (AM_REG(PDM, FR))
+
+//*****************************************************************************
+//
+//! @brief Read the FIFO READ DATA as an in-line macro
+//
+//*****************************************************************************
+#define am_hal_pdm_fifo_data_read()     (AM_REG(PDM, FRD))
+
+//*****************************************************************************
+//
+//! @brief Flush the FIFO as an in-line macro
+//
+//*****************************************************************************
+#define am_hal_pdm_fifo_flush()         (AM_REG(PDM, FLUSH) = 0)
+
+//*****************************************************************************
+//
+//! @brief Set the PDM Configuration (PCFG) Register
+//!
+//! This function sets the PDM configuration register
+//
+//*****************************************************************************
+#define am_hal_pdm_pcfg_set(Value)      (AM_REG(PDM, PCFG) = Value)
+
+//*****************************************************************************
+//
+//! @brief Get the PCFG register value from PDM module.
+//
+//*****************************************************************************
+#define am_hal_pdm_pcfg_get()           (AM_REG(PDM, PCFG))
+
+//*****************************************************************************
+//
+//! @brief Set the Voice Configuration (VCFG) Register
+//
+//*****************************************************************************
+#define am_hal_pdm_vcfg_set(Value)      (AM_REG(PDM, VCFG) = Value)
+
+//*****************************************************************************
+//
+//! @brief Get the VCFG register value from PDM module.
+//
+//*****************************************************************************
+#define am_hal_pdm_vcfg_get()           (AM_REG(PDM, VCFG))
+
+//*****************************************************************************
+//
+//! @brief Set the FIFO Threshold
+//
+//*****************************************************************************
+#define am_hal_pdm_thresh_set(thresh)   (AM_REG(PDM, FTHR) = thresh)
+
+//*****************************************************************************
+//
+//! @brief Get the FIFO Threshold register value from PDM module.
+//
+//*****************************************************************************
+#define am_hal_pdm_thresh_get()         (AM_REG(PDM, FTHR))
+
+//*****************************************************************************
+//
+//! @brief Set the left microphone PGA gain.
+//!
+//*****************************************************************************
+#define am_hal_pdm_left_gain_set(gain)  (AM_BFW(PDM, PCFG, PGALEFT, gain))
+
+//*****************************************************************************
+//
+//! @brief Set the right microphone PGA gain.
+//
+//*****************************************************************************
+#define am_hal_pdm_right_gain_set(gain) (AM_BFW(PDM, PCFG, PGARIGHT, gain))
+
+//*****************************************************************************
+//
+//! @brief Get the left microphone PGA gain value.
+//
+//*****************************************************************************
+#define am_hal_pdm_left_gain_get()      (AM_BFR(PDM, PCFG, PGALEFT))
+
+//*****************************************************************************
+//
+//! @brief Get the right microphone PGA gain value.
+//
+//*****************************************************************************
+#define am_hal_pdm_right_gain_get()     (AM_BFR(PDM, PCFG, PGARIGHT))
+
+//*****************************************************************************
+//
+//! @brief Enable the Soft Mute functionality.
+//
+//*****************************************************************************
+#define am_hal_pdm_soft_mute_enable()   (AM_BFWe(PDM, PCFG, SOFTMUTE, EN))
+
+//*****************************************************************************
+//
+//! @brief Disable the Soft Mute functionality.
+//
+//*****************************************************************************
+#define am_hal_pdm_soft_mute_disable()  (AM_BFWe(PDM, PCFG, SOFTMUTE, DIS))
+
+//*****************************************************************************
+//
+//! @brief Enable selected PDM Interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_pdm.h\n
+//!     AM_HAL_PDM_INT_UNDFL\n
+//!     AM_HAL_PDM_INT_OVF\n
+//!     AM_HAL_PDM_INT_FIFO\n
+//
+//*****************************************************************************
+#define am_hal_pdm_int_enable(intrpt)   (AM_REG(PDM, INTEN) |= intrpt)
+
+//*****************************************************************************
+//
+//! @brief Return the enabled PDM Interrupts.
+//!
+//! Use this function to return all enabled PDM interrupts.
+//!
+//! @return all enabled PDM interrupts as a mask.\n
+//!     AM_HAL_PDM_INT_UNDFL\n
+//!     AM_HAL_PDM_INT_OVF\n
+//!     AM_HAL_PDM_INT_FIFO\n
+//
+//*****************************************************************************
+#define am_hal_pdm_int_enable_get()     (AM_REG(PDM, INTEN))
+
+//*****************************************************************************
+//
+//! @brief Disable selected PDM Interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_pdm.h\n
+//!     AM_HAL_PDM_INT_UNDFL\n
+//!     AM_HAL_PDM_INT_OVF\n
+//!     AM_HAL_PDM_INT_FIFO\n
+//
+//*****************************************************************************
+#define am_hal_pdm_int_disable(intrpt)  (AM_REG(PDM, INTEN) &= ~intrpt)
+
+//*****************************************************************************
+//
+//! @brief Clear selected PDM Interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_pdm.h\n
+//!     AM_HAL_PDM_INT_UNDFL\n
+//!     AM_HAL_PDM_INT_OVF\n
+//!     AM_HAL_PDM_INT_FIFO\n
+//
+//*****************************************************************************
+#define am_hal_pdm_int_clear(intrpt)    (AM_REG(PDM, INTCLR) = intrpt)
+
+//*****************************************************************************
+//
+//! @brief Set selected PDM Interrupts.
+//!
+//! Use this function to set the PDM interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_pdm.h\n
+//!     AM_HAL_PDM_INT_UNDFL\n
+//!     AM_HAL_PDM_INT_OVF\n
+//!     AM_HAL_PDM_INT_FIFO\n
+//
+//*****************************************************************************
+#define am_hal_pdm_int_set(intrpt)      (AM_REG(PDM, INTSET) = intrpt)
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_pdm_config(am_hal_pdm_config_t * cfg);
+extern void am_hal_pdm_enable(void);
+extern void am_hal_pdm_disable(void);
+
+extern uint32_t am_hal_pdm_int_status_get(bool bEnabledOnly);
+
+#endif // AM_HAL_PDM_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h
new file mode 100644
index 0000000000..8a1068f882
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h
@@ -0,0 +1,557 @@
+//*****************************************************************************
+//
+//  am_hal_pin.h
+//! @file
+//! @brief Macros for configuring specific pins.
+//!
+//! @addtogroup pin2 PIN definitions for Apollo2.
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_HAL_PIN_H
+#define AM_HAL_PIN_H
+
+//*****************************************************************************
+//
+// Pin definition helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_PIN_DIR_INPUT      (AM_HAL_GPIO_INPEN)
+#define AM_HAL_PIN_DIR_OUTPUT     (AM_HAL_GPIO_OUT_PUSHPULL)
+#define AM_HAL_PIN_DIR_OPENDRAIN  (AM_HAL_GPIO_OUT_OPENDRAIN | AM_HAL_GPIO_INPEN)
+#define AM_HAL_PIN_DIR_3STATE     (AM_HAL_GPIO_OUT_3STATE)
+
+//*****************************************************************************
+//
+// Pin definition helper macros.
+//
+//*****************************************************************************
+#define AM_HAL_PIN_DISABLE        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_INPUT          (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_OUTPUT         (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT)
+#define AM_HAL_PIN_OPENDRAIN      (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_3STATE         (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_3STATE)
+
+//*****************************************************************************
+//
+// Pin definition macros.
+//
+//*****************************************************************************
+#define AM_HAL_PIN_0_SLSCL        (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_0_SLSCK        (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_0_CLKOUT       (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_0_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_0_MxSCKLB      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_0_M2SCK        (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_0_MxSCLLB      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_0_M2SCL        (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN)
+
+#define AM_HAL_PIN_1_SLSDA        (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_1_SLMISO       (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_1_UART0TX      (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_1_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_1_MxMISOLB     (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_1_M2MISO       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_1_MxSDALB      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_1_M2SDA        (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN)
+
+#define AM_HAL_PIN_2_SLWIR3       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE)
+#define AM_HAL_PIN_2_SLMOSI       (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_2_UART0RX      (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_2_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_2_MxMOSILB     (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_2_M2MOSI       (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_2_MxWIR3LB     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_2_M2WIR3       (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_3STATE)
+
+#define AM_HAL_PIN_3_UART0RTS     (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_3_SLnCE        (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_3_M1nCE4       (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_3_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_3_MxnCELB      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_3_M2nCE0       (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_3_TRIG1        (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_3_I2S_WCLK     (AM_HAL_GPIO_FUNC(7))
+#define AM_HAL_PIN_3_PSOURCE      (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER)
+
+#define AM_HAL_PIN_4_UART0CTS     (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_4_SLINT        (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_4_M0nCE5       (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_4_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_4_SLINTGP      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_4_M2nCE5       (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_4_CLKOUT       (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_4_32KHZ_XT     (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_5_M0SCL        (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_5_M0SCK        (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_5_UART0RTS     (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_5_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_5_M0SCKLB      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_5_EXTHFA       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_5_M0SCLLB      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_5_M1nCE2       (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_6_M0SDA        (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_6_M0MISO       (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_6_UART0CTS     (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_6_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_6_SLMISOLB     (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_6_M1nCE0       (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_6_SLSDALB      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_6_I2S_DAT      (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_7_M0WIR3       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE)
+#define AM_HAL_PIN_7_M0MOSI       (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_7_CLKOUT       (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_7_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_7_TRIG0        (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_7_UART0TX      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_7_SLWIR3LB     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_7_M1nCE1       (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_8_M1SCL        (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_8_M1SCK        (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_8_M0nCE4       (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_8_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_8_M2nCE4       (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_8_M1SCKLB      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_8_UART1TX      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_8_M1SCLLB      (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_9_M1SDA        (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_9_M1MISO       (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_9_M0nCE5       (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_9_GPIO         (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_9_M4nCE5       (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_9_SLMISOLB     (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_9_UART1RX      (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_9_SLSDALB      (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_10_M1WIR3      (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE)
+#define AM_HAL_PIN_10_M1MOSI      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_10_M0nCE6      (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_10_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_10_M2nCE6      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_10_UART1RTS    (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_10_M4nCE4      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_10_SLWIR3LB    (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_11_ADCSE2      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_11_M0nCE0      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_11_CLKOUT      (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_11_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_11_M2nCE7      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_11_UART1CTS    (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_11_UART0RX     (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_11_PDM_DATA    (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_11_PSINK       (AM_HAL_GPIO_FUNC(3))
+
+#define AM_HAL_PIN_12_ADCD0NSE9   (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_12_M1nCE0      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_12_TCTA0       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_12_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_12_CLKOUT      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_12_PDM_CLK     (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_12_UART0CTS    (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_12_UART1TX     (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_13_ADCD0PSE8   (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_13_M1nCE1      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_13_TCTB0       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_13_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_13_M2nCE3      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_13_EXTHFB      (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_13_UART0RTS    (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_13_UART1RX     (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
+
+#define AM_HAL_PIN_14_ADCD1P      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_14_M1nCE2      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_14_UART1TX     (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_14_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_14_M2nCE1      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_14_EXTHFS      (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_14_SWDCK       (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_14_32KHZ_XT    (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_15_ADCD1N      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_15_M1nCE3      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_15_UART1RX     (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_15_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_15_M2nCE2      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_15_EXTXT       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_15_SWDIO       (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_15_SWO         (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_16_ADCSE0      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_16_M0nCE4      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_16_TRIG0       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_16_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_16_M2nCE3      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_16_CMPIN0      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_16_UART0TX     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_16_UART1RTS    (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_17_CMPRF1      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_17_M0nCE1      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_17_TRIG1       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_17_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_17_M4nCE3      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_17_EXTLF       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_17_UART0RX     (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_17_UART1CTS    (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
+
+#define AM_HAL_PIN_18_CMPIN1      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_18_M0nCE2      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_18_TCTA1       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_18_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_18_M4nCE1      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_18_ANATEST2    (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_18_UART1TX     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_18_32KHZ_XT    (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_19_CMPRF0      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_19_M0nCE3      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_19_TCTB1       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_19_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_19_TCTA1       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_19_ANATEST1    (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_19_UART1RX     (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_19_I2S_BCLK    (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_20_SWDCK       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_20_M1nCE5      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_20_TCTA2       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_20_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_20_UART0TX     (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_20_UART1TX     (AM_HAL_GPIO_FUNC(5))
+
+#define AM_HAL_PIN_21_SWDIO       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_21_M1nCE6      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_21_TCTB2       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_21_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_21_UART0RX     (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_21_UART1RX     (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+
+#define AM_HAL_PIN_22_UART0TX     (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_22_M1nCE7      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_22_TCTA3       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_22_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_22_PDM_CLK     (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_22_TCTB1       (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_22_SWO         (AM_HAL_GPIO_FUNC(7))
+#define AM_HAL_PIN_22_PSOURCE     (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER)
+
+#define AM_HAL_PIN_23_UART0RX     (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_23_M0nCE0      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_23_TCTB3       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_23_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_23_PDM_DATA    (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_23_CMPOUT      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_23_TCTB1       (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_24_M2nCE1      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_24_M0nCE1      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_24_CLKOUT      (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_24_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_24_M5nCE0      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_24_TCTA1       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_24_I2S_BCLK    (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_24_SWO         (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_25_EXTXT       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_25_M0nCE2      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_25_TCTA0       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_25_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_25_M2SDA       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_25_M2MISO      (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_25_SLMISOLB    (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_25_SLSDALB     (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#define AM_HAL_PIN_26_EXTLF       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_26_M0nCE3      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_26_TCTB0       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_26_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_26_M2nCE0      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_26_TCTA1       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_26_M5nCE1      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_26_M3nCE0      (AM_HAL_GPIO_FUNC(7))
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_27_EXTHF       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_27_M1nCE4      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_27_TCTA1       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_27_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_27_M2SCL       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_27_M2SCK       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_27_M2SCKLB     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_27_M2SCLLB     (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#define AM_HAL_PIN_28_I2S_WCLK    (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_28_M1nCE5      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_28_TCTB1       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_28_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_28_M2WIR3      (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE)
+#define AM_HAL_PIN_28_M2MOSI      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_28_M5nCE3      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_28_SLWIR3LB    (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_29_ADCSE1      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_29_M1nCE6      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_29_TCTA2       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_29_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_29_UART0CTS    (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_29_UART1CTS    (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_29_M4nCE0      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_29_PDM_DATA    (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_30_M1nCE7      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_30_TCTB2       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_30_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_30_UART0TX     (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_30_UART1RTS    (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_30_SWO         (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_30_I2S_DAT     (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_31_ADCSE3      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_31_M0nCE4      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_31_TCTA3       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_31_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_31_UART0RX     (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_31_TCTB1       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_32_ADCSE4      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_32_M0nCE5      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_32_TCTB3       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_32_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_32_TCTB1       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_33_ADCSE5      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_33_M0nCE6      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_33_32KHZ_XT    (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_33_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_33_M3nCE7      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_33_TCTB1       (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_33_SWO         (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_34_ADCSE6      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_34_M0nCE7      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_34_M2nCE3      (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_34_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_34_CMPRF2      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_34_M3nCE1      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_34_M4nCE0      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_34_M5nCE2      (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_35_ADCSE7      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_35_M1nCE0      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_35_UART1TX     (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_35_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_35_M4nCE6      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_35_TCTA1       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_35_UART0RTS    (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_35_M3nCE2      (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_36_TRIG1       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_36_M1nCE1      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_36_UART1RX     (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_36_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_36_32KHZ_XT    (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_36_M2nCE0      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_36_UART0CTS    (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_36_M3nCE3      (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_37_TRIG2       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_37_M1nCE2      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_37_UART0RTS    (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_37_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_37_M3nCE4      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_37_M4nCE1      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_37_PDM_CLK     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_37_TCTA1       (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_38_TRIG3       (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_38_M1nCE3      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_38_UART0CTS    (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_38_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_38_M3WIR3      (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE)
+#define AM_HAL_PIN_38_M3MOSI      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_38_M4nCE7      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_38_SLWIR3LB    (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#define AM_HAL_PIN_39_UART0TX     (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_39_UART1TX     (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_39_CLKOUT      (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_39_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_39_M4SCL       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_39_M4SCK       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_39_M4SCKLB     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_39_M4SCLLB     (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_40_UART0RX     (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_40_UART1RX     (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_40_TRIG0       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_40_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_40_M4SDA       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_40_M4MISO      (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_40_SLMISOLB    (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_40_SLSDALB     (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_41_M2nCE1      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_41_CLKOUT      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_41_SWO         (AM_HAL_GPIO_FUNC(2))
+#define AM_HAL_PIN_41_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_41_M3nCE5      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_41_M5nCE7      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_41_M4nCE2      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_41_UART0RTS    (AM_HAL_GPIO_FUNC(7))
+#define AM_HAL_PIN_41_PSOURCE     (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_42_M2nCE2      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_42_M0nCE0      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_42_TCTA0       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_42_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_42_M3SCL       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_42_M3SCK       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_42_M3SCKLB     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_42_M3SCLLB     (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_43_M2nCE4      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_43_M0nCE1      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_43_TCTB0       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_43_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_43_M3SDA       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_43_M3MISO      (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_43_SLMISOLB    (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_43_SLSDALB     (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#define AM_HAL_PIN_44_UART1RTS    (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_44_M0nCE2      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_44_TCTA1       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_44_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_44_M4WIR3      (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE)
+#define AM_HAL_PIN_44_M4MOSI      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_44_M5nCE6      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_44_SLWIR3LB    (AM_HAL_GPIO_FUNC(7))
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_45_UART1CTS    (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_45_M0nCE3      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_45_TCTB1       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_45_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_45_M4nCE3      (AM_HAL_GPIO_FUNC(4))
+#define AM_HAL_PIN_45_M3nCE6      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_45_M5nCE5      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_45_TCTA1       (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
+#endif // defined (AM_PACKAGE_BGA)
+
+#if defined (AM_PACKAGE_BGA)
+#define AM_HAL_PIN_46_32KHZ_XT    (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_46_M0nCE4      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_46_TCTA2       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_46_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_46_TCTA1       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_46_M5nCE4      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_46_M4nCE4      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_46_SWO         (AM_HAL_GPIO_FUNC(7))
+#endif // defined (AM_PACKAGE_BGA)
+
+#define AM_HAL_PIN_47_M2nCE5      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_47_M0nCE5      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_47_TCTB2       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_47_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_47_M5WIR3      (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE)
+#define AM_HAL_PIN_47_M5MOSI      (AM_HAL_GPIO_FUNC(5))
+#define AM_HAL_PIN_47_M4nCE5      (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_47_SLWIR3LB    (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_48_M2nCE6      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_48_M0nCE6      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_48_TCTA3       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_48_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_48_M5SCL       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_48_M5SCK       (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_48_M5SCKLB     (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_48_M5SCLLB     (AM_HAL_GPIO_FUNC(7))
+
+#define AM_HAL_PIN_49_M2nCE7      (AM_HAL_GPIO_FUNC(0))
+#define AM_HAL_PIN_49_M0nCE7      (AM_HAL_GPIO_FUNC(1))
+#define AM_HAL_PIN_49_TCTB3       (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_49_GPIO        (AM_HAL_GPIO_FUNC(3))
+#define AM_HAL_PIN_49_M5SDA       (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
+#define AM_HAL_PIN_49_M5MISO      (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
+#define AM_HAL_PIN_49_SLMISOLB    (AM_HAL_GPIO_FUNC(6))
+#define AM_HAL_PIN_49_SLSDALB     (AM_HAL_GPIO_FUNC(7))
+
+#endif  // AM_HAL_PIN_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c
new file mode 100644
index 0000000000..cc91eeb159
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c
@@ -0,0 +1,558 @@
+//*****************************************************************************
+//
+//  am_hal_pwrctrl.c
+//! @file
+//!
+//! @brief Functions for enabling and disabling power domains.
+//!
+//! @addtogroup pwrctrl2 Power Control
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//  ONE_BIT - true iff value has exactly 1 bit set.
+//
+//*****************************************************************************
+#define ONE_BIT(ui32Value)   (ui32Value  &&  !(ui32Value & (ui32Value - 1)))
+
+//*****************************************************************************
+//
+//  Determine if this is an Apollo2 revision that requires additional handling
+//  of the BUCK to LDO transition when only the ADC is in use and going to
+//  deepsleep.
+//
+//*****************************************************************************
+static bool
+isRev_ADC(void)
+{
+    return AM_BFM(MCUCTRL, CHIPREV, REVMAJ) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B ?
+            true : false;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable power for a peripheral.
+//!
+//! @param ui32Peripheral - The peripheral to enable
+//!
+//! This function directly enables or disables power for the chosen peripheral.
+//!
+//! @note Unpowered peripherals may lose their configuration information. This
+//! function does not save or restore peripheral configuration registers.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral)
+{
+
+    am_hal_debug_assert_msg(ONE_BIT(ui32Peripheral),
+                        "Cannot enable more than one peripheral at a time.");
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Enable power control for the given device.
+    //
+    AM_REG(PWRCTRL, DEVICEEN) |= ui32Peripheral;
+
+    //
+    // End Critical Section.
+    //
+    AM_CRITICAL_END_ASM
+
+    //
+    // Wait for the power to stablize.  Using a simple delay loop is more
+    // power efficient than a polling loop.
+    //
+    am_hal_flash_delay(AM_HAL_PWRCTRL_DEVICEEN_DELAYCYCLES / 3);
+
+    //
+    // Quick check to guarantee we're good (should never be more than 1 read).
+    //
+    POLL_PWRSTATUS(ui32Peripheral);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable power for a peripheral.
+//!
+//! @param ui32Peripheral - The peripheral to disable
+//!
+//! This function directly disables or disables power for the chosen peripheral.
+//!
+//! @note Unpowered peripherals may lose their configuration information. This
+//! function does not save or restore peripheral configuration registers.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral)
+{
+
+    am_hal_debug_assert_msg(ONE_BIT(ui32Peripheral),
+                        "Cannot enable more than one peripheral at a time.");
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Disable power control for the given device.
+    //
+    AM_REG(PWRCTRL, DEVICEEN) &= ~ui32Peripheral;
+
+    //
+    // End critical section.
+    //
+    AM_CRITICAL_END_ASM
+
+    //
+    // Wait for the power to stablize
+    //
+    am_hal_flash_delay(AM_HAL_PWRCTRL_DEVICEDIS_DELAYCYCLES / 3);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable and disable power for memory devices (SRAM, flash, cache).
+//!
+//! @param ui32MemEn - The memory and amount to be enabled.
+//!         Must be one of the following:
+//!         AM_HAL_PWRCTRL_MEMEN_CACHE
+//!         AM_HAL_PWRCTRL_MEMEN_CACHE_DIS
+//!         AM_HAL_PWRCTRL_MEMEN_FLASH512K
+//!         AM_HAL_PWRCTRL_MEMEN_FLASH1M
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM8K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM16K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM24K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM32K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM64K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM96K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM128K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM160K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM192K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM224K
+//!         AM_HAL_PWRCTRL_MEMEN_SRAM256K
+//!         AM_HAL_PWRCTRL_MEMEN_ALL (the default, power-up state)
+//!
+//! This function enables/disables power to provide only the given amount of
+//! the type of memory specified.
+//!
+//! Only the type of memory specified is affected. Therefore separate calls
+//! are required to affect power settings for FLASH, SRAM, or CACHE.
+//!
+//! Settings for zero SRAM or FLASH are not provided as device behavior under
+//! either of those conditions is undefined.
+//!
+//! @note Unpowered memory devices may lose their configuration information.
+//! This function does not save or restore peripheral configuration registers.
+//!
+//! @return None.
+//
+//*****************************************************************************
+bool
+am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn)
+{
+    uint32_t ui32MemEnMask, ui32MemDisMask;
+    uint32_t ui32PwrStatEnMask, ui32PwrStatDisMask;
+    int32_t i32TOcnt;
+
+    if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_FLASH512K )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_FLASH0_EN;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_FLASH1_EN;
+        ui32PwrStatEnMask  = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M;
+        ui32PwrStatDisMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_FLASH1M )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_FLASH0_EN |
+                         AM_REG_PWRCTRL_MEMEN_FLASH1_EN;
+        ui32MemDisMask = 0;
+        ui32PwrStatEnMask  = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M  |
+                             AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M;
+        ui32PwrStatDisMask = 0;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM8K )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM16K )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM24K )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0       |
+                         AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1       |
+                         AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~(AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0     |
+                           AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1     |
+                           AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2);
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM32K )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM64K )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM96K )
+    {
+        ui32MemEnMask  = AM_HAL_PWRCTRL_MEMEN_SRAM96K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_HAL_PWRCTRL_MEMEN_SRAM96K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM128K )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM160K )
+    {
+        ui32MemEnMask  = AM_HAL_PWRCTRL_MEMEN_SRAM160K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_HAL_PWRCTRL_MEMEN_SRAM160K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM192K )
+    {
+        ui32MemEnMask  = AM_HAL_PWRCTRL_MEMEN_SRAM192K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_HAL_PWRCTRL_MEMEN_SRAM192K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM224K )
+    {
+        ui32MemEnMask  = AM_HAL_PWRCTRL_MEMEN_SRAM224K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_HAL_PWRCTRL_MEMEN_SRAM224K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM256K )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K;
+        ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    &
+                         ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K;
+        ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL    &
+                             ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_CACHE )
+    {
+        ui32MemEnMask  = AM_REG_PWRCTRL_MEMEN_CACHEB0_EN    |
+                         AM_REG_PWRCTRL_MEMEN_CACHEB2_EN;
+        ui32MemDisMask = 0;
+        ui32PwrStatEnMask  = AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M    |
+                             AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M;
+        ui32PwrStatDisMask = 0;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_CACHE_DIS )
+    {
+        ui32MemEnMask = 0;
+        ui32MemDisMask  = AM_REG_PWRCTRL_MEMEN_CACHEB0_EN   |
+                          AM_REG_PWRCTRL_MEMEN_CACHEB2_EN;
+        ui32PwrStatEnMask  = 0;
+        ui32PwrStatDisMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M    |
+                             AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M;
+    }
+    else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_ALL )
+    {
+        ui32MemEnMask  = AM_HAL_PWRCTRL_MEMEN_ALL;
+        ui32MemDisMask = 0;
+        ui32PwrStatEnMask  = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL;
+        ui32PwrStatDisMask = 0;
+    }
+    else
+    {
+        return false;
+    }
+
+    //
+    // Disable unneeded memory. If nothing to be disabled, skip to save time.
+    //
+    // Note that a deliberate disable step using a disable mask is taken here
+    // for 2 reasons: 1) To only affect the specified type of memory, and 2)
+    // To avoid inadvertently disabling any memory currently being depended on.
+    //
+    if ( ui32MemDisMask != 0 )
+    {
+        AM_REG(PWRCTRL, MEMEN) &= ~ui32MemDisMask;
+    }
+
+    //
+    // Enable the required memory.
+    //
+    if ( ui32MemEnMask != 0 )
+    {
+        AM_REG(PWRCTRL, MEMEN) |= ui32MemEnMask;
+    }
+
+    //
+    // Wait for the power to be turned on.
+    // Apollo2 note - these loops typically end up taking 1 iteration.
+    //
+    i32TOcnt = 200;
+    if ( ui32PwrStatDisMask )
+    {
+        while ( --i32TOcnt              &&
+                ( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatDisMask ) );
+    }
+
+    if ( i32TOcnt <= 0 )
+    {
+        return false;
+    }
+
+    i32TOcnt = 200;
+    if ( ui32PwrStatEnMask )
+    {
+        while ( --i32TOcnt              &&
+            (( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatEnMask )
+                != ui32PwrStatEnMask) );
+    }
+    if ( i32TOcnt <= 0 )
+    {
+        return false;
+    }
+
+    return true;
+}
+
+//*****************************************************************************
+//
+//! @brief Initialize the core and memory buck converters.
+//!
+//! This function is intended to be used for first time core and memory buck
+//! converters initialization.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_pwrctrl_bucks_init(void)
+{
+    am_hal_pwrctrl_bucks_enable();
+
+    while ( ( AM_REG(PWRCTRL, POWERSTATUS) &
+              ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M |
+                AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) )  !=
+              ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M |
+                AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) );
+
+    //
+    // Additional delay to make sure BUCKs are initialized.
+    //
+    am_hal_flash_delay(200 / 3);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the core and memory buck converters.
+//!
+//! This function enables the core and memory buck converters.
+//!
+//! @return None
+//
+//*****************************************************************************
+#define LDO_TRIM_REG_ADDR   (0x50023004)
+#define BUCK_TRIM_REG_ADDR  (0x50023000)
+
+void
+am_hal_pwrctrl_bucks_enable(void)
+{
+    //
+    // Check to see if the bucks are already on. If so, we can just return.
+    //
+    if ( AM_BFR(PWRCTRL, POWERSTATUS, COREBUCKON)   &&
+         AM_BFR(PWRCTRL, POWERSTATUS, MEMBUCKON) )
+    {
+        return;
+    }
+
+    //
+    // Enable BUCK power up
+    //
+    AM_BFW(PWRCTRL, SUPPLYSRC, COREBUCKEN, 1);
+    AM_BFW(PWRCTRL, SUPPLYSRC, MEMBUCKEN, 1);
+
+    //
+    // Make sure bucks are ready.
+    //
+    while ( ( AM_REG(PWRCTRL, POWERSTATUS)                      &
+              ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M |
+                AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) )  !=
+              ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M |
+                AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) );
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the core and memory buck converters.
+//!
+//! This function disables the core and memory buck converters.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_pwrctrl_bucks_disable(void)
+{
+    //
+    // Check to see if the bucks are already off. If so, we can just return.
+    //
+    if ( AM_BFR(PWRCTRL, POWERSTATUS, COREBUCKON) == 0  &&
+         AM_BFR(PWRCTRL, POWERSTATUS, MEMBUCKON) == 0)
+    {
+        return;
+    }
+
+    //
+    // Handle the special case if only the ADC is powered.
+    //
+    if ( isRev_ADC()  &&
+         (AM_REG(PWRCTRL, DEVICEEN) == AM_REG_PWRCTRL_DEVICEEN_ADC_EN) )
+    {
+            //
+            // Set SUPPLYSRC to handle this case
+            //
+            AM_REG(PWRCTRL, SUPPLYSRC) &=
+                (AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_EN    |
+                 AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_EN);
+    }
+    else
+    {
+        //
+        // Power them down
+        //
+        AM_BFW(PWRCTRL, SUPPLYSRC, COREBUCKEN, 0);
+        AM_BFW(PWRCTRL, SUPPLYSRC, MEMBUCKEN, 0);
+    }
+
+    //
+    // Wait until BUCKs are disabled.
+    //
+    am_hal_flash_delay(AM_HAL_PWRCTRL_BUCKDIS_DELAYCYCLES / 3);
+}
+
+//*****************************************************************************
+//
+//! @brief Misc low power initializations.
+//!
+//! This function performs low power initializations that aren't specifically
+//! handled elsewhere.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_pwrctrl_low_power_init(void)
+{
+    //
+    // For lowest power, we enable clock gating for all SRAM configuration.
+    //
+    AM_REG(PWRCTRL, SRAMCTRL) |=
+        AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_EN  |
+        AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_EN         |
+        AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_DIS;
+
+    //
+    // For lowest deep sleep power, make sure we stay in BUCK mode.
+    //
+    AM_REG(PWRCTRL, SUPPLYSRC) &=
+        ~AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_M;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h
new file mode 100644
index 0000000000..bc9adabf84
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h
@@ -0,0 +1,342 @@
+//*****************************************************************************
+//
+//  am_hal_pwrctrl.h
+//! @file
+//!
+//! @brief Functions for enabling and disabling power domains.
+//!
+//! @addtogroup pwrctrl2 Power Control
+//! @ingroup apollo2hal
+//! @{
+
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_HAL_PWRCTRL_H
+#define AM_HAL_PWRCTRL_H
+
+//*****************************************************************************
+//
+// Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable()
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_ADC      AM_REG_PWRCTRL_DEVICEEN_ADC_EN
+#define AM_HAL_PWRCTRL_IOM0     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN
+#define AM_HAL_PWRCTRL_IOM1     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN
+#define AM_HAL_PWRCTRL_IOM2     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN
+#define AM_HAL_PWRCTRL_IOM3     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN
+#define AM_HAL_PWRCTRL_IOM4     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN
+#define AM_HAL_PWRCTRL_IOM5     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN
+#define AM_HAL_PWRCTRL_IOS      AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN
+#define AM_HAL_PWRCTRL_PDM      AM_REG_PWRCTRL_DEVICEEN_PDM_EN
+#define AM_HAL_PWRCTRL_UART0    AM_REG_PWRCTRL_DEVICEEN_UART0_EN
+#define AM_HAL_PWRCTRL_UART1    AM_REG_PWRCTRL_DEVICEEN_UART1_EN
+
+//*****************************************************************************
+//
+// Macro to set the appropriate IOM peripheral when using
+//  am_hal_pwrctrl_periph_enable()/disable().
+// For Apollo2, the module argument must resolve to be a value from 0-5.
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_IOM(module)                      \
+    (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN << module)
+
+//*****************************************************************************
+//
+// Macro to set the appropriate UART peripheral when using
+//  am_hal_pwrctrl_periph_enable()/disable().
+// For Apollo2, the module argument must resolve to be a value from 0-1.
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_UART(module)                     \
+    (AM_REG_PWRCTRL_DEVICEEN_UART0_EN << module)
+
+
+//*****************************************************************************
+//
+// Memory enable values for am_hal_pwrctrl_memory_enable()
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_MEMEN_SRAM8K     AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM16K    AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM24K   (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K | \
+                                        AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM32K    AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM64K    AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM96K                    \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K    |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM128K   AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM160K                   \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K   |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM192K                   \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K   |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4     |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM224K                   \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K   |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4     |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5     |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM256K   AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K
+
+#define AM_HAL_PWRCTRL_MEMEN_FLASH512K  AM_REG_PWRCTRL_MEMEN_FLASH0_EN
+#define AM_HAL_PWRCTRL_MEMEN_FLASH1M                \
+            (AM_REG_PWRCTRL_MEMEN_FLASH0_EN     |   \
+             AM_REG_PWRCTRL_MEMEN_FLASH1_EN)
+#define AM_HAL_PWRCTRL_MEMEN_CACHE                  \
+            (AM_REG_PWRCTRL_MEMEN_CACHEB0_EN    |   \
+             AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
+#define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS              \
+            ~(AM_REG_PWRCTRL_MEMEN_CACHEB0_EN   |   \
+              AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
+
+//
+// Power up all available memory devices (this is the default power up state)
+//
+#define AM_HAL_PWRCTRL_MEMEN_ALL                    \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    |   \
+             AM_REG_PWRCTRL_MEMEN_FLASH0_EN     |   \
+             AM_REG_PWRCTRL_MEMEN_FLASH1_EN     |   \
+             AM_REG_PWRCTRL_MEMEN_CACHEB0_EN    |   \
+             AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
+
+//*****************************************************************************
+//
+// Peripheral power enable and disable delays
+// The delay counts are based on an internal clock that runs at half of
+// HFRC. Therefore, we need to double the delay cycles.
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_DEVICEEN_DELAYCYCLES     (22 * 2)
+#define AM_HAL_PWRCTRL_DEVICEDIS_DELAYCYCLES    (22 * 2)
+
+//
+// Use the following only when enabling after sleep (not during initialization).
+//
+#define AM_HAL_PWRCTRL_BUCKEN_DELAYCYCLES       (0 * 2)
+#define AM_HAL_PWRCTRL_BUCKDIS_DELAYCYCLES      (15 * 2)
+
+//*****************************************************************************
+//
+// Peripheral PWRONSTATUS groupings.
+//
+//*****************************************************************************
+//
+// Group DEVICEEN bits (per PWRONSTATUS groupings).
+//
+#define AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2                     \
+            (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN      |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN      |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN )
+
+#define AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5                     \
+            (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN      |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN      |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN )
+
+#define AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS                   \
+            (AM_REG_PWRCTRL_DEVICEEN_UART0_EN           |   \
+             AM_REG_PWRCTRL_DEVICEEN_UART1_EN           |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN )
+
+#define AM_HAL_PWRCTRL_DEVICEEN_ADC             AM_REG_PWRCTRL_DEVICEEN_ADC_EN
+#define AM_HAL_PWRCTRL_DEVICEEN_PDM             AM_REG_PWRCTRL_DEVICEEN_PDM_EN
+
+//
+// Map PWRONSTATUS bits to peripheral groupings.
+//
+#define AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS    AM_REG_PWRCTRL_PWRONSTATUS_PDA_M
+#define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5      AM_REG_PWRCTRL_PWRONSTATUS_PDC_M
+#define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2      AM_REG_PWRCTRL_PWRONSTATUS_PDB_M
+#define AM_HAL_PWRCTRL_PWRONSTATUS_ADC          AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M
+#define AM_HAL_PWRCTRL_PWRONSTATUS_PDM          AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M
+
+#define POLL_PWRSTATUS(ui32Peripheral)                                  \
+    if ( 1 )                                                            \
+    {                                                                   \
+        uint32_t ui32PwrOnStat;                                         \
+        if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2 )         \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2;         \
+        }                                                               \
+        else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5 )    \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5;         \
+        }                                                               \
+        else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS )  \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS;       \
+        }                                                               \
+        else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_ADC )        \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_ADC;             \
+        }                                                               \
+        else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_PDM )        \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_PDM;             \
+        }                                                               \
+        else                                                            \
+        {                                                               \
+            ui32PwrOnStat = 0xFFFFFFFF;                                 \
+        }                                                               \
+                                                                        \
+        /* */                                                           \
+        /* Wait for the power control setting to take effect. */        \
+        /* */                                                           \
+        while ( !(AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrOnStat) );      \
+    }
+
+//*****************************************************************************
+//
+// Memory PWRONSTATUS enable values for am_hal_pwrctrl_memory_enable()
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K                  \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL                 \
+        AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K
+
+//*****************************************************************************
+//
+// Function prototypes
+//
+//*****************************************************************************
+extern void am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral);
+extern void am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral);
+extern bool am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn);
+extern void am_hal_pwrctrl_bucks_init(void);
+extern void am_hal_pwrctrl_bucks_enable(void);
+extern void am_hal_pwrctrl_bucks_disable(void);
+extern void am_hal_pwrctrl_low_power_init(void);
+
+#endif // AM_HAL_PWRCTRL_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c
new file mode 100644
index 0000000000..66a9846c29
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c
@@ -0,0 +1,286 @@
+//*****************************************************************************
+//
+//  am_hal_queue.c
+//! @file
+//!
+//! @brief Functions for implementing a queue system.
+//!
+//! @addtogroup Miscellaneous2 Software Features (MISC)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Initializes a queue.
+//!
+//! @param psQueue - Pointer to a queue structure.
+//! @param pvData - Pointer to a memory location to be used for data storage.
+//! @param ui32ItemSize - Number of bytes per item in the queue.
+//! @param ui32ArraySize - Number of bytes in the data array.
+//!
+//! This function initializes the members of a queue structure and attaches it
+//! to an array of memory that it can use for storage. This function should be
+//! called before the queue is used.
+//!
+//! In this example, we are creating a queue that can hold 1024 32-bit
+//! integers. The integers themselves will be stored in the array named
+//! pui32WorkingSpace, while information about the queue itself will be stored
+//! in sDataQueue.
+//!
+//! @note The caller should not modify any of the members of am_hal_queue_t
+//! structures. The queue API will handle these members in a thread-safe way.
+//!
+//! @note The queue will remember what size data is in it. Other queue API
+//! functions will perform transfers in units of "items" where one "item" is
+//! the number of bytes you specify in the \e ui32ItemSize argument upon
+//! initialization.
+//!
+//! Example usage:
+//!
+//! @code
+//!
+//! //
+//! // Declare a queue structure and an array of bytes we can use to store
+//! // data.
+//! //
+//! am_hal_queue_t sDataQueue;
+//! uint32_t pui32WorkingSpace[1024];
+//!
+//! //
+//! // Attach the queue structure to the working memory.
+//! //
+//! am_hal_queue_init(&sDataQueue, pui8WorkingSpace, sizeof(uint32_t)
+//!                   sizeof(pui32WorkingSpace));
+//!
+//! @endcode
+//!
+//! The am_hal_queue_from_array macro is a convenient shorthand for this
+//! operation. The code below does the same thing as the code above.
+//!
+//! @code
+//!
+//! //
+//! // Declare a queue structure and an array of bytes we can use to store
+//! // data.
+//! //
+//! am_hal_queue_t sDataQueue;
+//! uint32_t pui32WorkingSpace[1024];
+//!
+//! //
+//! // Attach the queue structure to the working memory.
+//! //
+//! am_hal_queue_from_array(&sDataQueue, pui8WorkingSpace);
+//!
+//! @endcode
+//
+//*****************************************************************************
+void
+am_hal_queue_init(am_hal_queue_t *psQueue, void *pvData, uint32_t ui32ItemSize,
+                  uint32_t ui32ArraySize)
+{
+    psQueue->ui32WriteIndex = 0;
+    psQueue->ui32ReadIndex = 0;
+    psQueue->ui32Length = 0;
+    psQueue->ui32Capacity = ui32ArraySize;
+    psQueue->ui32ItemSize = ui32ItemSize;
+    psQueue->pui8Data = (uint8_t *) pvData;
+}
+
+//*****************************************************************************
+//
+//! @brief Adds an item to the Queue
+//!
+//! @param psQueue - Pointer to a queue structure.
+//! @param pvSource - Pointer to the data to be added.
+//! @param ui32NumItems - Number of items to be added.
+//!
+//! This function will copy the data pointed to by pvSource into the queue. The
+//! \e ui32NumItems term specifies the number of items to be copied from \e
+//! pvSource. The size of an "item" depends on how the queue was initialized.
+//! Please see am_hal_queue_init() for more information on this.
+//!
+//! @return true if the add operation was successful, or false if the queue
+//! didn't have enough space.
+//
+//*****************************************************************************
+bool
+am_hal_queue_item_add(am_hal_queue_t *psQueue, const void *pvSource, uint32_t ui32NumItems)
+{
+    uint32_t i;
+    uint8_t *pui8Source;
+    uint32_t ui32Bytes = ui32NumItems * psQueue->ui32ItemSize;
+    bool bSuccess = false;
+    uint32_t ui32Primask;
+
+    pui8Source = (uint8_t *) pvSource;
+
+    ui32Primask = am_hal_interrupt_master_disable();
+
+    //
+    // Check to make sure that the buffer isn't already full
+    //
+    if ( am_hal_queue_space_left(psQueue) >= ui32Bytes )
+    {
+        //
+        // Loop over the bytes in the source array.
+        //
+        for ( i = 0; i < ui32Bytes; i++ )
+        {
+            //
+            // Write the value to the buffer.
+            //
+            psQueue->pui8Data[psQueue->ui32WriteIndex] = pui8Source[i];
+
+            //
+            // Advance the write index, making sure to wrap if necessary.
+            //
+            psQueue->ui32WriteIndex = ((psQueue->ui32WriteIndex + 1) %
+                                        psQueue->ui32Capacity);
+        }
+
+        //
+        // Update the length value appropriately.
+        //
+        psQueue->ui32Length += ui32Bytes;
+
+        //
+        // Report a success.
+        //
+        bSuccess = true;
+    }
+    else
+    {
+        //
+        // The buffer can't fit the amount of data requested. Return a
+        // failure.
+        //
+        bSuccess = false;
+    }
+
+    am_hal_interrupt_master_set(ui32Primask);
+
+    return bSuccess;
+}
+
+//*****************************************************************************
+//
+//! @brief Removes an item from the Queue
+//!
+//! @param psQueue - Pointer to a queue structure.
+//! @param pvDest - Pointer to the data to be added.
+//! @param ui32NumItems - Number of items to be added.
+//!
+//! This function will copy the data from the queue into the memory pointed to
+//! by pvDest. The \e ui32NumItems term specifies the number of items to be
+//! copied from the queue. The size of an "item" depends on how the queue was
+//! initialized.  Please see am_hal_queue_init() for more information on this.
+//!
+//! @return true if we were able to pull the requested number of items from the
+//! queue, or false if the queue didn't have that many items to pull.
+//
+//*****************************************************************************
+bool
+am_hal_queue_item_get(am_hal_queue_t *psQueue, void *pvDest, uint32_t ui32NumItems)
+{
+    uint32_t i;
+    uint8_t *pui8Dest;
+    uint32_t ui32Bytes = ui32NumItems * psQueue->ui32ItemSize;
+    bool bSuccess = false;
+    uint32_t ui32Primask;
+
+    pui8Dest = (uint8_t *) pvDest;
+
+    ui32Primask = am_hal_interrupt_master_disable();
+
+    //
+    // Check to make sure that the buffer isn't empty
+    //
+    if ( am_hal_queue_data_left(psQueue) >= ui32Bytes )
+    {
+        //
+        // Loop over the bytes in the destination array.
+        //
+        for ( i = 0; i < ui32Bytes; i++ )
+        {
+            //
+            // Grab the next value from the buffer.
+            //
+            pui8Dest[i] = psQueue->pui8Data[psQueue->ui32ReadIndex];
+
+            //
+            // Advance the read index, wrapping if needed.
+            //
+            psQueue->ui32ReadIndex = ((psQueue->ui32ReadIndex + 1) %
+                                       psQueue->ui32Capacity);
+        }
+
+        //
+        // Adjust the length value to reflect the change.
+        //
+        psQueue->ui32Length -= ui32Bytes;
+
+        //
+        // Report a success.
+        //
+        bSuccess = true;
+    }
+    else
+    {
+        //
+        // If the buffer didn't have enough data, just return false.
+        //
+        bSuccess = false;
+    }
+
+    am_hal_interrupt_master_set(ui32Primask);
+
+    return bSuccess;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h
new file mode 100644
index 0000000000..11e8ace90a
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h
@@ -0,0 +1,123 @@
+//*****************************************************************************
+//
+//  am_hal_queue.h
+//! @file
+//!
+//! @brief Functions for implementing a queue system.
+//!
+//! @addtogroup Miscellaneous2 Software Features (MISC)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_QUEUE_H
+#define AM_HAL_QUEUE_H
+
+//*****************************************************************************
+//
+//! @brief A data structure that will operate as a queue.
+//!
+//! This data structure holds information necessary for operating a thread-safe
+//! queue. When declaring a structure of type am_hal_queue_t, you will also need
+//! to provide some working memory for the queue to use. For more information on
+//! setting up and using the am_hal_queue_t structure, please see the
+//! documentation for am_hal_queue_init().
+//
+//*****************************************************************************
+typedef struct
+{
+    uint32_t ui32WriteIndex;
+    uint32_t ui32ReadIndex;
+    uint32_t ui32Length;
+    uint32_t ui32Capacity;
+    uint32_t ui32ItemSize;
+    uint8_t *pui8Data;
+}
+am_hal_queue_t;
+
+//*****************************************************************************
+//
+// Function-like macros.
+//
+//*****************************************************************************
+#define am_hal_queue_empty(psQueue)                                           \
+    ((psQueue)->ui32Length == 0)
+
+#define am_hal_queue_full(psQueue)                                            \
+    ((psQueue)->ui32Length == (psQueue)->ui32Capacity)
+
+#define am_hal_queue_space_left(psQueue)                                      \
+    ((psQueue)->ui32Capacity - (psQueue)->ui32Length)
+
+#define am_hal_queue_data_left(psQueue)                                       \
+    ((psQueue)->ui32Length)
+
+//*****************************************************************************
+//
+// Use this to make sure you get the size parameters right.
+//
+//*****************************************************************************
+#define am_hal_queue_from_array(queue, array)                                 \
+    am_hal_queue_init((queue), (array), sizeof((array)[0]), sizeof(array))
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// External function definitions.
+//
+//*****************************************************************************
+extern void am_hal_queue_init(am_hal_queue_t *psQueue, void *pvData, uint32_t ui32ItemSize, uint32_t ui32ArraySize);
+extern bool am_hal_queue_item_add(am_hal_queue_t *psQueue, const void *pvSource, uint32_t ui32NumItems);
+extern bool am_hal_queue_item_get(am_hal_queue_t *psQueue, void *pvDest, uint32_t ui32NumItems);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_QUEUE_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c
new file mode 100644
index 0000000000..86d5cf10b7
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c
@@ -0,0 +1,160 @@
+//*****************************************************************************
+//
+//  am_hal_reset.c
+//! @file
+//!
+//! @brief Hardware abstraction layer for the Reset Generator module.
+//!
+//! @addtogroup rstgen2 Reset Generator (RSTGEN)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Configure the Reset Generator.
+//!
+//! @param ui32Config - Or together the supplied macros to enable
+//! configurations to obtain the desired reset generator settings.
+//!
+//! This function will set the reset generator's configuration register based on
+//! the user's desired settings listed in the supplied arugment.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_reset_init(uint32_t ui32Config)
+{
+    //
+    // Write the configuration to the reset generator
+    //
+    AM_REG(RSTGEN, CFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! @brief Issue a POR (Apollo's last stage interrupt).
+//!
+//! This function will issue a POR reset.
+//! The Apollo chip has numerous stages of reset. POR is the last and is also
+//! the reset invoked by the chip's reset pin, the watchdog timer, the AIRCR
+//! reset, and the SWD debugger requested interrupt.
+//!
+//! The Debug Access Port in the M4 is not cleared by this reset.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void am_hal_reset_por(void)
+{
+    //
+    // Write the POR key to the software POR register.
+    //
+    AM_REG(RSTGEN, SWPOR) =
+           AM_REG_RSTGEN_SWPOR_SWPORKEY(AM_REG_RSTGEN_SWPOR_SWPORKEY_KEYVALUE);
+}
+
+//*****************************************************************************
+//
+//! @brief Issue a POI (Apollo's second stage interrupt).
+//!
+//! This function will issue a POI reset.
+//! The Apollo chip has numerous stages of reset. POI is the second stage.
+//! A few modules are reset by POI that are not reset by POR, notably POI
+//! causes the shadow registers to be reloaded from the OTP. A full power
+//! cycle or POI should be used after writing new flash, debug or SRAM
+//! protection bits into the OTP for these protections to take effect.
+//!
+//! The Debug Access Port in the M4 is not cleared by this reset.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void am_hal_reset_poi(void)
+{
+    //
+    // Write the POI key to the software POI register.
+    //
+    AM_REG(RSTGEN, SWPOI) =
+           AM_REG_RSTGEN_SWPOI_SWPOIKEY(AM_REG_RSTGEN_SWPOI_SWPOIKEY_KEYVALUE);
+}
+
+//*****************************************************************************
+//
+//! @brief Retrieve the status bits from the reset generator.
+//!
+//! This function will get the status bits from the reset generator.
+//! These bits are sticky and show the accumulation of reset types that the
+//! Apollo chip has experienced since power on. One should clear these out
+//! after reading them.
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t am_hal_reset_status_get(void)
+{
+    //
+    // Retrieve the reset generator status bits
+    //
+    return AM_REG(RSTGEN, STAT);
+}
+
+//*****************************************************************************
+//
+//! @brief Clear ALL of the status bits in the reset generator.
+//!
+//! This function will clear all status bits in the reset generator status.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void am_hal_reset_status_clear(void)
+{
+    AM_REG(RSTGEN, CLRSTAT) = AM_REG_RSTGEN_CLRSTAT_CLRSTAT(1);
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h
new file mode 100644
index 0000000000..a3273dad10
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h
@@ -0,0 +1,119 @@
+//*****************************************************************************
+//
+//  am_hal_reset.h
+//! @file
+//!
+//! @brief Hardware abstraction layer for the Reset Generator module.
+//!
+//! @addtogroup wdt2 Watchdog Timer (RSTGEN)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_RSTGEN_H
+#define AM_HAL_RSTGEN_H
+
+//*****************************************************************************
+//
+//! @name Reset Generator Configuration
+//! @brief These macros may be used to set the reset generator's configuration.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_RESET_CFG_WDT_RESET_ENABLE       (AM_REG_RSTGEN_CFG_WDREN(1))
+// Brown out high (2.1v) reset enable.
+#define AM_HAL_RESET_CFG_BOD_HIGH_RESET_ENABLE  (AM_REG_RSTGEN_CFG_BODHREN(1))
+//! @}
+
+//*****************************************************************************
+//
+//! @name Reset Generator Status Bit Masks
+//! @brief These macros may be used to determine which type(s) of resets have
+//!        been seen.
+//! @{
+//
+//*****************************************************************************
+// Reset was initiated by a Watchdog Timer Reset.
+#define AM_HAL_RESET_STAT_WDT (AM_REG_RSTGEN_STAT_WDRSTAT_M)
+
+// Reset was a initiated by Debugger Reset.
+#define AM_HAL_RESET_STAT_DEBUG (AM_REG_RSTGEN_STAT_DBGRSTAT_M)
+
+// Reset was a initiated by Software POI Reset.
+#define AM_HAL_RESET_STAT_POI (AM_REG_RSTGEN_STAT_POIRSTAT_M)
+
+// Reset was a initiated by Software POR or AIRCR Reset.
+#define AM_HAL_RESET_STAT_SOFTWARE (AM_REG_RSTGEN_STAT_SWRSTAT_M)
+
+// Reset was initiated by a Brown-Out Reset.
+#define AM_HAL_RESET_STAT_BOD (AM_REG_RSTGEN_STAT_BORSTAT_M)
+
+// Reset was initiated by a Power Cycle
+#define AM_HAL_RESET_STAT_POWER_CYCLE (AM_REG_RSTGEN_STAT_PORSTAT_M)
+
+// Reset was initiated by an External Reset.
+#define AM_HAL_RESET_STAT_EXTERNAL (AM_REG_RSTGEN_STAT_EXRSTAT_M)
+//! @}
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_reset_init(uint32_t ui32Config);
+extern void am_hal_reset_por(void);
+extern void am_hal_reset_poi(void);
+extern uint32_t am_hal_reset_status_get(void);
+extern void am_hal_reset_status_clear(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_RSTGEN_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c
new file mode 100644
index 0000000000..4630d5a117
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c
@@ -0,0 +1,678 @@
+//*****************************************************************************
+//
+//  am_hal_rtc.c
+//! @file
+//!
+//! @brief Functions for interfacing with the Real-Time Clock (RTC).
+//!
+//! @addtogroup rtc2 Real-Time Clock (RTC)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Converts a Binary Coded Decimal (BCD) byte to its Decimal form.
+//
+//*****************************************************************************
+static uint8_t
+bcd_to_dec(uint8_t ui8BCDByte)
+{
+  return (((ui8BCDByte & 0xF0) >> 4) * 10) + (ui8BCDByte & 0x0F);
+}
+
+//*****************************************************************************
+//
+// Converts a Decimal byte to its Binary Coded Decimal (BCD) form.
+//
+//*****************************************************************************
+static uint8_t
+dec_to_bcd(uint8_t ui8DecimalByte)
+{
+  return (((ui8DecimalByte / 10) << 4) | (ui8DecimalByte % 10));
+}
+
+//*****************************************************************************
+//
+//! @brief Selects the clock source for the RTC.
+//!
+//! @param ui32OSC the clock source for the RTC.
+//!
+//! This function selects the clock source for the RTC.
+//!
+//! Valid values for ui32OSC are:
+//!
+//!     AM_HAL_RTC_OSC_LFRC
+//!     AM_HAL_RTC_OSC_XT
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_rtc_osc_select(uint32_t ui32OSC)
+{
+    //
+    // Set XT if flag is set.
+    // Otherwise configure for LFRC.
+    //
+    if (ui32OSC)
+    {
+        AM_REG(CLKGEN, OCTRL) |= AM_REG_CLKGEN_OCTRL_OSEL_M;
+    }
+    else
+    {
+        AM_REG(CLKGEN, OCTRL) &= ~AM_REG_CLKGEN_OCTRL_OSEL_M;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Enable/Start the RTC oscillator.
+//!
+//! Starts the RTC oscillator.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_osc_enable(void)
+{
+    //
+    // Start the RTC Oscillator.
+    //
+    AM_REG(RTC, RTCCTL) &= ~AM_REG_RTC_RTCCTL_RSTOP(1);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable/Stop the RTC oscillator.
+//!
+//! Stops the RTC oscillator.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_osc_disable(void)
+{
+    //
+    // Stop the RTC Oscillator.
+    //
+    AM_REG(RTC, RTCCTL) |= AM_REG_RTC_RTCCTL_RSTOP(1);
+}
+
+//*****************************************************************************
+//
+//! @brief Configures the RTC for 12 or 24 hour time keeping.
+//!
+//! @param b12Hour - A 'true' configures the RTC for 12 hour time keeping.
+//!
+//! Configures the RTC for 12 (true) or 24 (false) hour time keeping.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_time_12hour(bool b12Hour)
+{
+    //
+    // Set the 12/24 hour bit.
+    //
+    AM_REG(RTC, RTCCTL) |= AM_REG_RTC_RTCCTL_HR1224(b12Hour);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable selected RTC interrupts.
+//!
+//! @param ui32Interrupt - desired interrupts
+//!
+//! Enables the RTC interrupts.
+//!
+//! ui32Interrupt should be an OR of the following:
+//!
+//!     AM_HAL_RTC_INT_ALM
+//!     AM_HAL_RTC_INT_OF
+//!     AM_HAL_RTC_INT_ACC
+//!     AM_HAL_RTC_INT_ACF
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_int_enable(uint32_t ui32Interrupt)
+{
+    //
+    // Enable the interrupts.
+    //
+    AM_REG(RTC, INTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return the enabled RTC interrupts.
+//!
+//! Returns the enabled RTC interrupts.
+//!
+//! @return enabled RTC interrupts. Return is a logical or of:
+//!
+//!     AM_HAL_RTC_INT_ALM
+//!     AM_HAL_RTC_INT_OF
+//!     AM_HAL_RTC_INT_ACC
+//!     AM_HAL_RTC_INT_ACF
+//
+//*****************************************************************************
+uint32_t
+am_hal_rtc_int_enable_get(void)
+{
+    //
+    // Read the RTC interrupt enable register, and return its contents.
+    //
+    return AM_REG(RTC, INTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable selected RTC interrupts.
+//!
+//! @param ui32Interrupt - desired interrupts
+//!
+//! Disables the RTC interrupts.
+//!
+//! ui32Interrupt should be an OR of the following:
+//!
+//!     AM_HAL_RTC_INT_ALM
+//!     AM_HAL_RTC_INT_OF
+//!     AM_HAL_RTC_INT_ACC
+//!     AM_HAL_RTC_INT_ACF
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_int_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Disable the interrupts.
+    //
+    AM_REG(RTC, INTEN) &= ~ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Sets the selected RTC interrupts.
+//!
+//! @param ui32Interrupt - desired interrupts
+//!
+//! Sets the RTC interrupts causing them to immediately trigger.
+//!
+//! ui32Interrupt should be an OR of the following:
+//!
+//!     AM_HAL_RTC_INT_ALM
+//!     AM_HAL_RTC_INT_OF
+//!     AM_HAL_RTC_INT_ACC
+//!     AM_HAL_RTC_INT_ACF
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Set the interrupts.
+    //
+    AM_REG(RTC, INTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Clear selected RTC interrupts.
+//!
+//! @param ui32Interrupt - desired interrupts
+//!
+//! Clears the RTC interrupts.
+//!
+//! ui32Interrupt should be an OR of the following:
+//!
+//!     AM_HAL_RTC_INT_ALM
+//!     AM_HAL_RTC_INT_OF
+//!     AM_HAL_RTC_INT_ACC
+//!     AM_HAL_RTC_INT_ACF
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Clear the interrupts.
+    //
+    AM_REG(RTC, INTCLR) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Returns the RTC interrupt status.
+//!
+//! @param bEnabledOnly - return the status of only the enabled interrupts.
+//!
+//! Returns the RTC interrupt status.
+//!
+//! @return Bitwise representation of the current interrupt status.
+//!
+//! The return value will be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_RTC_INT_ALM
+//!     AM_HAL_RTC_INT_OF
+//!     AM_HAL_RTC_INT_ACC
+//!     AM_HAL_RTC_INT_ACF
+//
+//*****************************************************************************
+uint32_t
+am_hal_rtc_int_status_get(bool bEnabledOnly)
+{
+    //
+    // Get the interrupt status.
+    //
+    if (bEnabledOnly)
+    {
+        uint32_t u32RetVal;
+        u32RetVal  = AM_REG(RTC, INTSTAT);
+        u32RetVal &= AM_REG(RTC, INTEN);
+        return u32RetVal &
+                (AM_HAL_RTC_INT_ALM | AM_HAL_RTC_INT_OF |
+                AM_HAL_RTC_INT_ACC | AM_HAL_RTC_INT_ACF);
+    }
+    else
+    {
+        return (AM_REG(RTC, INTSTAT) & (AM_HAL_RTC_INT_ALM |
+                                        AM_HAL_RTC_INT_OF |
+                                        AM_HAL_RTC_INT_ACC |
+                                        AM_HAL_RTC_INT_ACF));
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Set the Real Time Clock counter registers.
+//!
+//! @param *pTime - A pointer to the time structure.
+//!
+//! Sets the RTC counter registers to the supplied values.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_time_set(am_hal_rtc_time_t *pTime)
+{
+    //
+    // Enable writing to the counters.
+    //
+    AM_REG(RTC, RTCCTL) |= AM_REG_RTC_RTCCTL_WRTC(1);
+
+    //
+    // Write the RTCLOW register.
+    //
+    AM_REG(RTC, CTRLOW) =
+        AM_REG_RTC_CTRLOW_CTRHR(dec_to_bcd(pTime->ui32Hour))                |
+        AM_REG_RTC_CTRLOW_CTRMIN(dec_to_bcd(pTime->ui32Minute))             |
+        AM_REG_RTC_CTRLOW_CTRSEC(dec_to_bcd(pTime->ui32Second))             |
+        AM_REG_RTC_CTRLOW_CTR100(dec_to_bcd(pTime->ui32Hundredths));
+
+    //
+    // Write the RTCUP register.
+    //
+    AM_REG(RTC, CTRUP) =
+        AM_REG_RTC_CTRUP_CEB((pTime->ui32CenturyEnable))                   |
+        AM_REG_RTC_CTRUP_CB((pTime->ui32Century))                          |
+        AM_REG_RTC_CTRUP_CTRWKDY((pTime->ui32Weekday))                     |
+        AM_REG_RTC_CTRUP_CTRYR(dec_to_bcd((pTime->ui32Year)))              |
+        AM_REG_RTC_CTRUP_CTRMO(dec_to_bcd((pTime->ui32Month)))             |
+        AM_REG_RTC_CTRUP_CTRDATE(dec_to_bcd((pTime->ui32DayOfMonth)));
+
+    //
+    // Disable writing to the counters.
+    //
+    AM_REG(RTC, RTCCTL) |= AM_REG_RTC_RTCCTL_WRTC(0);
+}
+
+//*****************************************************************************
+//
+//! @brief Get the Real Time Clock current time.
+//!
+//! @param *pTime - A pointer to the time structure to store the current time.
+//!
+//! Gets the RTC's current time
+//!
+//! @return 0 for success and 1 for error.
+//
+//*****************************************************************************
+uint32_t
+am_hal_rtc_time_get(am_hal_rtc_time_t *pTime)
+{
+    uint32_t ui32RTCLow, ui32RTCUp, ui32Value;
+
+    //
+    // Read the upper and lower RTC registers.
+    //
+    ui32RTCLow = AM_REG(RTC, CTRLOW);
+    ui32RTCUp = AM_REG(RTC, CTRUP);
+
+    //
+    // Break out the lower word.
+    //
+    ui32Value =
+        ((ui32RTCLow & AM_REG_RTC_CTRLOW_CTRHR_M) >> AM_REG_RTC_CTRLOW_CTRHR_S);
+    pTime->ui32Hour = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32RTCLow & AM_REG_RTC_CTRLOW_CTRMIN_M) >> AM_REG_RTC_CTRLOW_CTRMIN_S);
+    pTime->ui32Minute = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32RTCLow & AM_REG_RTC_CTRLOW_CTRSEC_M) >> AM_REG_RTC_CTRLOW_CTRSEC_S);
+    pTime->ui32Second = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32RTCLow & AM_REG_RTC_CTRLOW_CTR100_M) >> AM_REG_RTC_CTRLOW_CTR100_S);
+    pTime->ui32Hundredths = bcd_to_dec(ui32Value);
+
+    //
+    // Break out the upper word.
+    //
+    pTime->ui32ReadError =
+        ((ui32RTCUp & AM_REG_RTC_CTRUP_CTERR_M) >> AM_REG_RTC_CTRUP_CTERR_S);
+
+    pTime->ui32CenturyEnable =
+        ((ui32RTCUp & AM_REG_RTC_CTRUP_CEB_M) >> AM_REG_RTC_CTRUP_CEB_S);
+
+    pTime->ui32Century =
+        ((ui32RTCUp & AM_REG_RTC_CTRUP_CB_M) >> AM_REG_RTC_CTRUP_CB_S);
+
+    ui32Value =
+        ((ui32RTCUp & AM_REG_RTC_CTRUP_CTRWKDY_M) >> AM_REG_RTC_CTRUP_CTRWKDY_S);
+    pTime->ui32Weekday = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32RTCUp & AM_REG_RTC_CTRUP_CTRYR_M) >> AM_REG_RTC_CTRUP_CTRYR_S);
+    pTime->ui32Year = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32RTCUp & AM_REG_RTC_CTRUP_CTRMO_M) >> AM_REG_RTC_CTRUP_CTRMO_S);
+    pTime->ui32Month = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32RTCUp & AM_REG_RTC_CTRUP_CTRDATE_M) >> AM_REG_RTC_CTRUP_CTRDATE_S);
+    pTime->ui32DayOfMonth = bcd_to_dec(ui32Value);
+
+    //
+    // Was there a read error?
+    //
+    if (pTime->ui32ReadError)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Sets the alarm repeat interval.
+//!
+//! @param ui32RepeatInterval the desired repeat interval.
+//!
+//! Sets the alarm repeat interval.
+//!
+//! Valid values for ui32RepeatInterval:
+//!
+//!     AM_HAL_RTC_ALM_RPT_DIS
+//!     AM_HAL_RTC_ALM_RPT_YR
+//!     AM_HAL_RTC_ALM_RPT_MTH
+//!     AM_HAL_RTC_ALM_RPT_WK
+//!     AM_HAL_RTC_ALM_RPT_DAY
+//!     AM_HAL_RTC_ALM_RPT_HR
+//!     AM_HAL_RTC_ALM_RPT_MIN
+//!     AM_HAL_RTC_ALM_RPT_SEC
+//!     AM_HAL_RTC_ALM_RPT_10TH
+//!     AM_HAL_RTC_ALM_RPT_100TH
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_alarm_interval_set(uint32_t ui32RepeatInterval)
+{
+    uint32_t ui32RptInt, ui32Alm100, ui32Value;
+
+    switch(ui32RepeatInterval)
+    {
+        //
+        // If repeat every 10th set RPT and ALM100 field accordinly
+        //
+        case AM_HAL_RTC_ALM_RPT_10TH:
+            ui32RptInt = AM_HAL_RTC_ALM_RPT_SEC;
+            ui32Alm100 = AM_HAL_RTC_ALM100_10TH;
+            break;
+        //
+        // If repeat every 100th set RPT and ALM100 field accordinly
+        //
+        case AM_HAL_RTC_ALM_RPT_100TH:
+            ui32RptInt = AM_HAL_RTC_ALM_RPT_SEC;
+            ui32Alm100 = AM_HAL_RTC_ALM100_100TH;
+            break;
+        //
+        // Otherwise set RPT as value passed.  ALM100 values need to be 0xnn
+        // in this setting where n = 0-9.
+        //
+        default:
+            //
+            // Get the current value of the ALM100 field.
+            //
+            ui32Value = AM_BFR(RTC, ALMLOW, ALM100);
+
+            //
+            // If ALM100 was previous EVERY_10TH or EVERY_100TH reset to zero
+            // otherwise keep previous setting.
+            //
+            ui32Alm100 = ui32Value >= 0xF0 ? 0 : ui32Value;
+
+            //
+            // Set RPT value to value passed.
+            //
+            ui32RptInt = ui32RepeatInterval;
+            break;
+    }
+
+    //
+    // Write the interval to the register.
+    //
+    AM_BFW(RTC, RTCCTL, RPT, ui32RptInt);
+
+    //
+    // Write the Alarm 100 bits in the ALM100 register.
+    //
+    AM_BFW(RTC, ALMLOW, ALM100, ui32Alm100);
+}
+
+//*****************************************************************************
+//
+//! @brief Sets the RTC's Alarm.
+//!
+//! @param *pTime - A pointer to the time structure.
+//! @param ui32RepeatInterval - the desired alarm repeat interval.
+//!
+//! Set the Real Time Clock Alarm Parameters.
+//!
+//! Valid values for ui32RepeatInterval:
+//!
+//!     AM_HAL_RTC_ALM_RPT_DIS
+//!     AM_HAL_RTC_ALM_RPT_YR
+//!     AM_HAL_RTC_ALM_RPT_MTH
+//!     AM_HAL_RTC_ALM_RPT_WK
+//!     AM_HAL_RTC_ALM_RPT_DAY
+//!     AM_HAL_RTC_ALM_RPT_HR
+//!     AM_HAL_RTC_ALM_RPT_MIN
+//!     AM_HAL_RTC_ALM_RPT_SEC
+//!     AM_HAL_RTC_ALM_RPT_10TH
+//!     AM_HAL_RTC_ALM_RPT_EVERY_100TH
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_alarm_set(am_hal_rtc_time_t *pTime, uint32_t ui32RepeatInterval)
+{
+    uint8_t ui8Value = 0;
+
+    //
+    // Write the interval to the register.
+    //
+    AM_REG(RTC, RTCCTL) |=
+        AM_REG_RTC_RTCCTL_RPT(ui32RepeatInterval > 0x7 ? 0x7 : ui32RepeatInterval);
+
+    //
+    // Check if the interval is 10th or every 100th and track it in ui8Value.
+    //
+    if (ui32RepeatInterval == AM_HAL_RTC_ALM_RPT_10TH)
+    {
+        ui8Value = 0xF0;
+    }
+    else if (ui32RepeatInterval == AM_HAL_RTC_ALM_RPT_100TH)
+    {
+        ui8Value = 0xFF;
+    }
+
+    //
+    // Write the ALMUP register.
+    //
+    AM_REG(RTC, ALMUP) =
+        AM_REG_RTC_ALMUP_ALMWKDY((pTime->ui32Weekday))                     |
+        AM_REG_RTC_ALMUP_ALMMO(dec_to_bcd((pTime->ui32Month)))             |
+        AM_REG_RTC_ALMUP_ALMDATE(dec_to_bcd((pTime->ui32DayOfMonth)));
+
+    //
+    // Write the ALMLOW register.
+    //
+    AM_REG(RTC, ALMLOW) =
+        AM_REG_RTC_ALMLOW_ALMHR(dec_to_bcd(pTime->ui32Hour))                |
+        AM_REG_RTC_ALMLOW_ALMMIN(dec_to_bcd(pTime->ui32Minute))             |
+        AM_REG_RTC_ALMLOW_ALMSEC(dec_to_bcd(pTime->ui32Second))             |
+        AM_REG_RTC_ALMLOW_ALM100(dec_to_bcd(pTime->ui32Hundredths) | ui8Value);
+}
+
+//*****************************************************************************
+//
+//! @brief Get the Real Time Clock Alarm Parameters
+//!
+//! @param *pTime - A pointer to the time structure to store the current alarm.
+//!
+//! Gets the RTC's Alarm time
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_rtc_alarm_get(am_hal_rtc_time_t *pTime)
+{
+    uint32_t ui32ALMLow, ui32ALMUp, ui32Value;
+
+    //
+    // Read the upper and lower RTC registers.
+    //
+    ui32ALMLow = AM_REG(RTC, ALMLOW);
+    ui32ALMUp = AM_REG(RTC, ALMUP);
+
+    //
+    // Break out the lower word.
+    //
+    ui32Value =
+        ((ui32ALMLow & AM_REG_RTC_ALMLOW_ALMHR_M) >> AM_REG_RTC_ALMLOW_ALMHR_S);
+    pTime->ui32Hour = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32ALMLow & AM_REG_RTC_ALMLOW_ALMMIN_M) >> AM_REG_RTC_ALMLOW_ALMMIN_S);
+    pTime->ui32Minute = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32ALMLow & AM_REG_RTC_ALMLOW_ALMSEC_M) >> AM_REG_RTC_ALMLOW_ALMSEC_S);
+    pTime->ui32Second = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32ALMLow & AM_REG_RTC_ALMLOW_ALM100_M) >> AM_REG_RTC_ALMLOW_ALM100_S);
+    pTime->ui32Hundredths = bcd_to_dec(ui32Value);
+
+    //
+    // Break out the upper word.
+    //
+    pTime->ui32ReadError = 0;
+    pTime->ui32CenturyEnable = 0;
+    pTime->ui32Century = 0;
+
+    ui32Value =
+        ((ui32ALMUp & AM_REG_RTC_ALMUP_ALMWKDY_M) >> AM_REG_RTC_ALMUP_ALMWKDY_S);
+    pTime->ui32Weekday = bcd_to_dec(ui32Value);
+
+    pTime->ui32Year = 0;
+
+    ui32Value =
+        ((ui32ALMUp & AM_REG_RTC_ALMUP_ALMMO_M) >> AM_REG_RTC_ALMUP_ALMMO_S);
+    pTime->ui32Month = bcd_to_dec(ui32Value);
+
+    ui32Value =
+        ((ui32ALMUp & AM_REG_RTC_ALMUP_ALMDATE_M) >> AM_REG_RTC_ALMUP_ALMDATE_S);
+    pTime->ui32DayOfMonth = bcd_to_dec(ui32Value);
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h
new file mode 100644
index 0000000000..9304a6c67f
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h
@@ -0,0 +1,185 @@
+//*****************************************************************************
+//
+//  am_hal_rtc.h
+//! @file
+//!
+//! @brief Functions for interfacing and accessing the Real-Time Clock (RTC).
+//!
+//! @addtogroup rtc2 Real-Time Clock (RTC)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_RTC_H
+#define AM_HAL_RTC_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name OSC Start and Stop
+//! @brief OSC Start and Stop defines.
+//!
+//! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x().
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_RTC_OSC_LFRC          0x1
+#define AM_HAL_RTC_OSC_XT            0x0
+//! @}
+
+//*****************************************************************************
+//
+//! @name RTC Interrupts
+//! @brief Macro definitions for RTC interrupt status bits.
+//!
+//! These macros correspond to the bits in the RTC interrupt status register.
+//! They may be used with any of the \e am_hal_rtc_int_x() functions.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_RTC_INT_ALM                  AM_REG_RTC_INTEN_ALM_M
+#define AM_HAL_RTC_INT_OF                   AM_REG_RTC_INTEN_OF_M
+#define AM_HAL_RTC_INT_ACC                  AM_REG_RTC_INTEN_ACC_M
+#define AM_HAL_RTC_INT_ACF                  AM_REG_RTC_INTEN_ACF_M
+//! @}
+
+//*****************************************************************************
+//
+//! @name RTC Alarm Repeat Interval.
+//! @brief Macro definitions for the RTC alarm repeat interval.
+//!
+//! These macros correspond to the RPT bits in the RTCCTL register.
+//! They may be used with the \e am_hal_rtc_alarm_interval_set() function.
+//!
+//! Note: AM_HAL_RTC_ALM_RPT_10TH and AM_HAL_RTC_ALM_RPT_100TH do not
+//! correspond to the RPT bits but are used in conjunction with setting the
+//! ALM100 bits in the ALMLOW register.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_RTC_ALM_RPT_DIS              0x0
+#define AM_HAL_RTC_ALM_RPT_YR               0x1
+#define AM_HAL_RTC_ALM_RPT_MTH              0x2
+#define AM_HAL_RTC_ALM_RPT_WK               0x3
+#define AM_HAL_RTC_ALM_RPT_DAY              0x4
+#define AM_HAL_RTC_ALM_RPT_HR               0x5
+#define AM_HAL_RTC_ALM_RPT_MIN              0x6
+#define AM_HAL_RTC_ALM_RPT_SEC              0x7
+#define AM_HAL_RTC_ALM_RPT_10TH             0x8
+#define AM_HAL_RTC_ALM_RPT_100TH            0x9
+//! @}
+
+//*****************************************************************************
+//
+//! @name RTC Alarm 100 Interval.
+//! @brief Macro definitions for the RTC alarm ms intervals.
+//!
+//! These macros are used inside the #am_hal_rtc_alarm_interval_set function
+//! when 10ms and 100ms repeated alarm intervals are desired.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_RTC_ALM100_DEFAULT           0x00
+#define AM_HAL_RTC_ALM100_10TH              0xF0
+#define AM_HAL_RTC_ALM100_100TH             0xFF
+//! @}
+
+//*****************************************************************************
+//
+//! @brief The basic time structure used by the HAL for RTC interaction.
+//!
+//! All values are positive whole numbers. The HAL routines convert back and
+//! forth to BCD.
+//
+//*****************************************************************************
+typedef struct am_hal_rtc_time_struct
+{
+    uint32_t ui32ReadError;
+    uint32_t ui32CenturyEnable;
+    uint32_t ui32Weekday;
+    uint32_t ui32Century;
+    uint32_t ui32Year;
+    uint32_t ui32Month;
+    uint32_t ui32DayOfMonth;
+    uint32_t ui32Hour;
+    uint32_t ui32Minute;
+    uint32_t ui32Second;
+    uint32_t ui32Hundredths;
+}am_hal_rtc_time_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_rtc_osc_select(uint32_t ui32OSC);
+extern void am_hal_rtc_osc_enable(void);
+extern void am_hal_rtc_osc_disable(void);
+extern void am_hal_rtc_time_12hour(bool b12Hour);
+extern void am_hal_rtc_time_set(am_hal_rtc_time_t *pTime);
+extern uint32_t am_hal_rtc_time_get(am_hal_rtc_time_t *pTime);
+extern void am_hal_rtc_alarm_interval_set(uint32_t ui32RepeatInterval);
+extern void am_hal_rtc_alarm_set(am_hal_rtc_time_t *pTime,
+                                 uint32_t ui32RepeatInterval);
+extern void am_hal_rtc_alarm_get(am_hal_rtc_time_t *pTime);
+extern void am_hal_rtc_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_rtc_int_enable_get(void);
+extern void am_hal_rtc_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_rtc_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_rtc_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_rtc_int_status_get(bool bEnabledOnly);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_RTC_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c
new file mode 100644
index 0000000000..0cdd706c9e
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c
@@ -0,0 +1,525 @@
+//*****************************************************************************
+//
+//  am_hal_stimer.c
+//! @file
+//!
+//! @brief Functions for interfacing with the system timer (STIMER).
+//!
+//! @addtogroup stimer2 System Timer (STIMER)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Set up the stimer.
+//!
+//! @param ui32STimerConfig is the value to load into the configuration reg.
+//!
+//! This function should be used to perform the initial set-up of the
+//! stimer.
+//!
+//! @return The 32-bit current config of the STimer Config register
+//
+//*****************************************************************************
+uint32_t
+am_hal_stimer_config(uint32_t ui32STimerConfig)
+{
+    uint32_t ui32CurrVal;
+
+    //
+    // Read the current config
+    //
+    ui32CurrVal = AM_REG(CTIMER, STCFG);
+
+    //
+    // Write our configuration value.
+    //
+    AM_REG(CTIMER, STCFG) = ui32STimerConfig;
+
+    //
+    // If all of the clock sources are not HFRC, disable LDO when sleeping if timers are enabled.
+    //
+    if ( (AM_BFR(CTIMER, STCFG, CLKSEL) == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16)   ||
+         (AM_BFR(CTIMER, STCFG, CLKSEL) == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256) )
+    {
+        AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 0);
+    }
+    else
+    {
+        AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 1);
+    }
+    return ui32CurrVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Get the current stimer value.
+//!
+//! This function can be used to read, uninvasively, the value in the stimer.
+//!
+//! @return The 32-bit value from the STimer counter register.
+//
+//*****************************************************************************
+uint32_t
+am_hal_stimer_counter_get(void)
+{
+    return AM_REG(CTIMER, STTMR);
+}
+
+//*****************************************************************************
+//
+//! @brief Clear the stimer counter.
+//!
+//! This function clears the STimer Counter and leaves the stimer running.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_stimer_counter_clear(void)
+{
+    //
+    // Set the clear bit
+    //
+    AM_REG(CTIMER, STCFG) |= AM_REG_CTIMER_STCFG_CLEAR_M;
+
+    //
+    // Reset the clear bit
+    //
+    AM_REG(CTIMER, STCFG) &= ~AM_REG_CTIMER_STCFG_CLEAR_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Set the compare value.
+//!
+//! @param ui32CmprInstance is the compare register instance number (0-7).
+//! @param ui32Delta is the value to add to the STimer counter and load into
+//!        the comparator register.
+//!
+//! NOTE: There is no way to set an absolute value into a comparator register.
+//!       Only deltas added to the STimer counter can be written to the compare
+//!       registers.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, uint32_t ui32Delta)
+{
+    if ( ui32CmprInstance > 7 )
+    {
+        return;
+    }
+
+    AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta;
+}
+
+//*****************************************************************************
+//
+//! @brief Get the current stimer compare register value.
+//!
+//! @param ui32CmprInstance is the compare register instance number (0-7).
+//!
+//! This function can be used to read the value in an stimer compare register.
+//!
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t
+am_hal_stimer_compare_get(uint32_t ui32CmprInstance)
+{
+    if ( ui32CmprInstance > 7 )
+    {
+        return 0;
+    }
+
+    return AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance));
+}
+
+//*****************************************************************************
+//
+//! @brief Start capturing data with the specified capture register.
+//!
+//! @param ui32CaptureNum is the Capture Register Number to read (0-3).
+//!        ui32GPIONumber is the pin number.
+//!        bPolarity: false (0) = Capture on low to high transition.
+//!                   true  (1) = Capture on high to low transition.
+//!
+//! Use this function to start capturing.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_stimer_capture_start(uint32_t ui32CaptureNum,
+                            uint32_t ui32GPIONumber,
+                            bool bPolarity)
+{
+    uint32_t ui32CapCtrl;
+
+    if ( ui32GPIONumber > (AM_HAL_GPIO_MAX_PADS-1) )
+    {
+        return;
+    }
+
+    //
+    // Set the polarity and pin selection in the GPIO block.
+    //
+    switch (ui32CaptureNum)
+    {
+         case 0:
+            AM_BFW(GPIO, STMRCAP, STPOL0, bPolarity);
+            AM_BFW(GPIO, STMRCAP, STSEL0, ui32GPIONumber);
+            ui32CapCtrl = AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_M;
+            break;
+         case 1:
+            AM_BFW(GPIO, STMRCAP, STPOL1, bPolarity);
+            AM_BFW(GPIO, STMRCAP, STSEL1, ui32GPIONumber);
+            ui32CapCtrl = AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_M;
+            break;
+         case 2:
+            AM_BFW(GPIO, STMRCAP, STPOL2, bPolarity);
+            AM_BFW(GPIO, STMRCAP, STSEL2, ui32GPIONumber);
+            ui32CapCtrl = AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_M;
+            break;
+         case 3:
+            AM_BFW(GPIO, STMRCAP, STPOL3, bPolarity);
+            AM_BFW(GPIO, STMRCAP, STSEL3, ui32GPIONumber);
+            ui32CapCtrl = AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_M;
+            break;
+         default:
+            return;     // error concealment.
+    }
+
+    //
+    // Enable it in the CTIMER Block
+    //
+    AM_REG(CTIMER, CAPTURE_CONTROL) |= ui32CapCtrl;
+}
+
+//*****************************************************************************
+//
+//! @brief Start capturing data with the specified capture register.
+//!
+//! @param ui32CaptureNum is the Capture Register Number to read.
+//!
+//! Use this function to start capturing.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void am_hal_stimer_capture_stop(uint32_t ui32CaptureNum)
+{
+    //
+    // Disable it in the CTIMER block.
+    //
+    AM_REG(CTIMER, CAPTURE_CONTROL) &=
+        ~(AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_M <<
+            ((AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_S -
+              AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_S) * ui32CaptureNum));
+}
+
+//*****************************************************************************
+//
+//! @brief Get the current stimer capture register value.
+//!
+//! @param ui32CaptureNum is the Capture Register Number to read.
+//!
+//! This function can be used to read the value in an stimer capture register.
+//!
+//!
+//! @return None.
+//
+//*****************************************************************************
+uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum)
+{
+    if ( ui32CaptureNum > 7 )
+    {
+        return 0;
+    }
+
+    return AM_REGVAL(AM_REG_STIMER_CAPTURE(0, ui32CaptureNum));
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the selected system timer interrupt.
+//!
+//! @param ui32Interrupt is the interrupt to be used.
+//!
+//! This function will enable the selected interrupts in the STIMER interrupt
+//! enable register. In order to receive an interrupt from an stimer component,
+//! you will need to enable the interrupt for that component in this main
+//! register, as well as in the stimer configuration register (accessible though
+//! am_hal_stimer_config()), and in the NVIC.
+//!
+//! ui32Interrupt should be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_STIMER_INT_COMPAREA
+//!     AM_HAL_STIMER_INT_COMPAREB
+//!     AM_HAL_STIMER_INT_COMPAREC
+//!     AM_HAL_STIMER_INT_COMPARED
+//!     AM_HAL_STIMER_INT_COMPAREE
+//!     AM_HAL_STIMER_INT_COMPAREF
+//!     AM_HAL_STIMER_INT_COMPAREG
+//!     AM_HAL_STIMER_INT_COMPAREH
+//!
+//!     AM_HAL_STIMER_INT_OVERFLOW
+//!
+//!     AM_HAL_STIMER_INT_CAPTUREA
+//!     AM_HAL_STIMER_INT_CAPTUREB
+//!     AM_HAL_STIMER_INT_CAPTUREC
+//!     AM_HAL_STIMER_INT_CAPTURED
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_stimer_int_enable(uint32_t ui32Interrupt)
+{
+    //
+    // Enable the interrupt at the module level.
+    //
+    AM_REGn(CTIMER, 0, STMINTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return the enabled stimer interrupts.
+//!
+//! This function will return all enabled interrupts in the STIMER
+//! interrupt enable register.
+//!
+//! @return return enabled interrupts. This will be a logical or of:
+//!
+//!     AM_HAL_STIMER_INT_COMPAREA
+//!     AM_HAL_STIMER_INT_COMPAREB
+//!     AM_HAL_STIMER_INT_COMPAREC
+//!     AM_HAL_STIMER_INT_COMPARED
+//!     AM_HAL_STIMER_INT_COMPAREE
+//!     AM_HAL_STIMER_INT_COMPAREF
+//!     AM_HAL_STIMER_INT_COMPAREG
+//!     AM_HAL_STIMER_INT_COMPAREH
+//!
+//!     AM_HAL_STIMER_INT_OVERFLOW
+//!
+//!     AM_HAL_STIMER_INT_CAPTUREA
+//!     AM_HAL_STIMER_INT_CAPTUREB
+//!     AM_HAL_STIMER_INT_CAPTUREC
+//!     AM_HAL_STIMER_INT_CAPTURED
+//!
+//! @return Return the enabled timer interrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_stimer_int_enable_get(void)
+{
+    //
+    // Return enabled interrupts.
+    //
+    return AM_REGn(CTIMER, 0, STMINTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the selected stimer interrupt.
+//!
+//! @param ui32Interrupt is the interrupt to be used.
+//!
+//! This function will disable the selected interrupts in the STIMER
+//! interrupt register.
+//!
+//! ui32Interrupt should be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_STIMER_INT_COMPAREA
+//!     AM_HAL_STIMER_INT_COMPAREB
+//!     AM_HAL_STIMER_INT_COMPAREC
+//!     AM_HAL_STIMER_INT_COMPARED
+//!     AM_HAL_STIMER_INT_COMPAREE
+//!     AM_HAL_STIMER_INT_COMPAREF
+//!     AM_HAL_STIMER_INT_COMPAREG
+//!     AM_HAL_STIMER_INT_COMPAREH
+//!
+//!     AM_HAL_STIMER_INT_OVERFLOW
+//!
+//!     AM_HAL_STIMER_INT_CAPTUREA
+//!     AM_HAL_STIMER_INT_CAPTUREB
+//!     AM_HAL_STIMER_INT_CAPTUREC
+//!     AM_HAL_STIMER_INT_CAPTURED
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_stimer_int_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Disable the interrupt at the module level.
+    //
+    AM_REGn(CTIMER, 0, STMINTEN) &= ~ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Sets the selected stimer interrupt.
+//!
+//! @param ui32Interrupt is the interrupt to be used.
+//!
+//! This function will set the selected interrupts in the STIMER
+//! interrupt register.
+//!
+//! ui32Interrupt should be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_STIMER_INT_COMPAREA
+//!     AM_HAL_STIMER_INT_COMPAREB
+//!     AM_HAL_STIMER_INT_COMPAREC
+//!     AM_HAL_STIMER_INT_COMPARED
+//!     AM_HAL_STIMER_INT_COMPAREE
+//!     AM_HAL_STIMER_INT_COMPAREF
+//!     AM_HAL_STIMER_INT_COMPAREG
+//!     AM_HAL_STIMER_INT_COMPAREH
+//!
+//!     AM_HAL_STIMER_INT_OVERFLOW
+//!
+//!     AM_HAL_STIMER_INT_CAPTUREA
+//!     AM_HAL_STIMER_INT_CAPTUREB
+//!     AM_HAL_STIMER_INT_CAPTUREC
+//!     AM_HAL_STIMER_INT_CAPTURED
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_stimer_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Set the interrupts.
+    //
+    AM_REGn(CTIMER, 0, STMINTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Clears the selected stimer interrupt.
+//!
+//! @param ui32Interrupt is the interrupt to be used.
+//!
+//! This function will clear the selected interrupts in the STIMER
+//! interrupt register.
+//!
+//! ui32Interrupt should be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_STIMER_INT_COMPAREA
+//!     AM_HAL_STIMER_INT_COMPAREB
+//!     AM_HAL_STIMER_INT_COMPAREC
+//!     AM_HAL_STIMER_INT_COMPARED
+//!     AM_HAL_STIMER_INT_COMPAREE
+//!     AM_HAL_STIMER_INT_COMPAREF
+//!     AM_HAL_STIMER_INT_COMPAREG
+//!     AM_HAL_STIMER_INT_COMPAREH
+//!
+//!     AM_HAL_STIMER_INT_OVERFLOW
+//!
+//!     AM_HAL_STIMER_INT_CAPTUREA
+//!     AM_HAL_STIMER_INT_CAPTUREB
+//!     AM_HAL_STIMER_INT_CAPTUREC
+//!     AM_HAL_STIMER_INT_CAPTURED
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_stimer_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Disable the interrupt at the module level.
+    //
+    AM_REGn(CTIMER, 0, STMINTCLR) = ui32Interrupt;
+}
+
+
+//*****************************************************************************
+//
+//! @brief Returns either the enabled or raw stimer interrupt status.
+//!
+//! This function will return the stimer interrupt status.
+//!
+//! @bEnabledOnly if true returns the status of the enabled interrupts
+//! only.
+//!
+//! The return value will be the logical OR of one or more of the following
+//! values:
+//!
+//!
+//! @return Returns the stimer interrupt status.
+//
+//*****************************************************************************
+uint32_t
+am_hal_stimer_int_status_get(bool bEnabledOnly)
+{
+    //
+    // Return the desired status.
+    //
+    uint32_t ui32RetVal = AM_REGn(CTIMER, 0, STMINTSTAT);
+
+    if ( bEnabledOnly )
+    {
+        ui32RetVal &= AM_REGn(CTIMER, 0, STMINTEN);
+    }
+
+    return ui32RetVal;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h
new file mode 100644
index 0000000000..bd4b09feae
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h
@@ -0,0 +1,242 @@
+//*****************************************************************************
+//
+//  am_hal_stimer.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the STIMER.
+//!
+//! @addtogroup stimer2 Counter/Timer (STIMER)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_STIMER_H
+#define AM_HAL_STIMER_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//
+// Compute address of a given COMPARE or CAPTURE register.
+// Note - For Apollo2, the parameter n should be 0 (as only 1 stimer module
+//        exists) and the parameter r should be 0-7 (compare) or 0-3 (capture).
+//
+#define AM_REG_STIMER_COMPARE(n, r) (AM_REG_CTIMERn(n) +                \
+                                     AM_REG_CTIMER_SCMPR0_O + (r * 4))
+
+#define AM_REG_STIMER_CAPTURE(n, r) (AM_REG_CTIMERn(n) +                \
+                                     AM_REG_CTIMER_SCAPT0_O + (r * 4))
+
+//*****************************************************************************
+//
+//! @name Interrupt Status Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to set and clear interrupt bits
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_STIMER_INT_COMPAREA         AM_REG_CTIMER_STMINTSTAT_COMPAREA_M
+#define AM_HAL_STIMER_INT_COMPAREB         AM_REG_CTIMER_STMINTSTAT_COMPAREB_M
+#define AM_HAL_STIMER_INT_COMPAREC         AM_REG_CTIMER_STMINTSTAT_COMPAREC_M
+#define AM_HAL_STIMER_INT_COMPARED         AM_REG_CTIMER_STMINTSTAT_COMPARED_M
+#define AM_HAL_STIMER_INT_COMPAREE         AM_REG_CTIMER_STMINTSTAT_COMPAREE_M
+#define AM_HAL_STIMER_INT_COMPAREF         AM_REG_CTIMER_STMINTSTAT_COMPAREF_M
+#define AM_HAL_STIMER_INT_COMPAREG         AM_REG_CTIMER_STMINTSTAT_COMPAREG_M
+#define AM_HAL_STIMER_INT_COMPAREH         AM_REG_CTIMER_STMINTSTAT_COMPAREH_M
+
+#define AM_HAL_STIMER_INT_OVERFLOW         AM_REG_CTIMER_STMINTSTAT_OVERFLOW_M
+
+#define AM_HAL_STIMER_INT_CAPTUREA         AM_REG_CTIMER_STMINTSTAT_CAPTUREA_M
+#define AM_HAL_STIMER_INT_CAPTUREB         AM_REG_CTIMER_STMINTSTAT_CAPTUREB_M
+#define AM_HAL_STIMER_INT_CAPTUREC         AM_REG_CTIMER_STMINTSTAT_CAPTUREC_M
+#define AM_HAL_STIMER_INT_CAPTURED         AM_REG_CTIMER_STMINTSTAT_CAPTURED_M
+
+//! @}
+
+
+
+//*****************************************************************************
+//
+//! @name STimer Configuration Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to set and clear interrupt bits
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_STIMER_CFG_THAW                                                \
+                                                AM_REG_CTIMER_STCFG_FREEZE_THAW
+#define AM_HAL_STIMER_CFG_FREEZE                                              \
+                                              AM_REG_CTIMER_STCFG_FREEZE_FREEZE
+#define AM_HAL_STIMER_CFG_RUN                                                 \
+                                                  AM_REG_CTIMER_STCFG_CLEAR_RUN
+#define AM_HAL_STIMER_CFG_CLEAR                                               \
+                                                AM_REG_CTIMER_STCFG_CLEAR_CLEAR
+#define AM_HAL_STIMER_CFG_COMPARE_A_ENABLE                                    \
+                                        AM_REG_CTIMER_STCFG_COMPARE_A_EN_ENABLE
+#define AM_HAL_STIMER_CFG_COMPARE_B_ENABLE                                    \
+                                        AM_REG_CTIMER_STCFG_COMPARE_B_EN_ENABLE
+#define AM_HAL_STIMER_CFG_COMPARE_C_ENABLE                                    \
+                                        AM_REG_CTIMER_STCFG_COMPARE_C_EN_ENABLE
+#define AM_HAL_STIMER_CFG_COMPARE_D_ENABLE                                    \
+                                        AM_REG_CTIMER_STCFG_COMPARE_D_EN_ENABLE
+#define AM_HAL_STIMER_CFG_COMPARE_E_ENABLE                                    \
+                                        AM_REG_CTIMER_STCFG_COMPARE_E_EN_ENABLE
+#define AM_HAL_STIMER_CFG_COMPARE_F_ENABLE                                    \
+                                        AM_REG_CTIMER_STCFG_COMPARE_F_EN_ENABLE
+#define AM_HAL_STIMER_CFG_COMPARE_G_ENABLE                                    \
+                                        AM_REG_CTIMER_STCFG_COMPARE_G_EN_ENABLE
+#define AM_HAL_STIMER_CFG_COMPARE_H_ENABLE                                    \
+                                        AM_REG_CTIMER_STCFG_COMPARE_H_EN_ENABLE
+
+//! @}
+
+//*****************************************************************************
+//
+//! @name Clock Configuration options
+//! @brief STimer Configuration register options.
+//!
+//! These options are to be used with the am_hal_stimer_config() function.
+//!  @{
+//
+//*****************************************************************************
+#define AM_HAL_STIMER_NO_CLK                                                  \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_NOCLK)
+#define AM_HAL_STIMER_HFRC_3MHZ                                               \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16)
+#define AM_HAL_STIMER_HFRC_187_5KHZ                                           \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256)
+#define AM_HAL_STIMER_XTAL_32KHZ                                              \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV1)
+#define AM_HAL_STIMER_XTAL_16KHZ                                              \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV2)
+#define AM_HAL_STIMER_XTAL_1KHZ                                               \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV32)
+#define AM_HAL_STIMER_LFRC_1KHZ                                               \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_LFRC_DIV1)
+#define AM_HAL_STIMER_HFRC_CTIMER0A                                           \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0A)
+#define AM_HAL_STIMER_HFRC_CTIMER0B                                           \
+              AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0B)
+//! @}
+
+
+
+//*****************************************************************************
+//
+//! @name Capture Control Register options.
+//! @brief Configuration options for capture control register.
+//!
+//! These options are to be used with the am_hal_stimer_capture_control_set
+//! function.
+//!  @{
+//
+//*****************************************************************************
+#define AM_HAL_STIMER_CAPTURE_A_ENABLE                                        \
+                                 AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_ENABLE
+#define AM_HAL_STIMER_CAPTURE_B_ENABLE                                        \
+                                 AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_ENABLE
+#define AM_HAL_STIMER_CAPTURE_C_ENABLE                                        \
+                                 AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_ENABLE
+#define AM_HAL_STIMER_CAPTURE_D_ENABLE                                        \
+                                 AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_ENABLE
+
+//! @}
+
+
+//*****************************************************************************
+//
+//
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Stimer configuration structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Configuration options for the STIMER
+    //
+    uint32_t ui32STimerConfig;
+}
+am_hal_stimer_config_t;
+
+
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern uint32_t am_hal_stimer_config(uint32_t ui32STimerConfig);
+extern uint32_t am_hal_stimer_counter_get(void);
+extern void     am_hal_stimer_counter_clear(void);
+extern void     am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance,
+                                                uint32_t ui32Delta);
+extern uint32_t am_hal_stimer_compare_get(uint32_t ui32CmprInstance);
+extern void     am_hal_stimer_capture_start(uint32_t ui32CaptureNum,
+                                            uint32_t ui32GPIONumber,
+                                            bool bPolarity);
+extern void     am_hal_stimer_capture_stop(uint32_t ui32CaptureNum);
+extern uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum);
+extern void     am_hal_stimer_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_stimer_int_enable_get(void);
+extern void     am_hal_stimer_int_disable(uint32_t ui32Interrupt);
+extern void     am_hal_stimer_int_set(uint32_t ui32Interrupt);
+extern void     am_hal_stimer_int_clear(uint32_t ui32Interrupt);
+extern uint32_t am_hal_stimer_int_status_get(bool bEnabledOnly);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_STIMER_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c
new file mode 100644
index 0000000000..50e0b67915
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c
@@ -0,0 +1,851 @@
+//*****************************************************************************
+//
+//  am_hal_sysctrl.c
+//! @file
+//!
+//! @brief Functions for interfacing with the M4F system control registers
+//!
+//! @addtogroup sysctrl2 System Control (SYSCTRL)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//  Local macro constants
+//
+//*****************************************************************************
+//
+// Define ZX workaround values.
+// These values are defined by the factory.
+//
+#define COREZXVALUE         0x07
+#define MEMZXVALUE          0x07
+
+//
+// Define values for g_ui32CoreBuck, which indicates which timer carries
+// the signal for the CORE Buck, and which also implies that the other timer
+// carries the signal for the MEM buck.
+//
+#define COREBUCK_TIMERA     1       // Core buck signal comes in on timer A
+#define COREBUCK_TIMERB     2       // Core buck signal comes in on timer B
+
+//
+// Define the bit values for static function g_buckZX_chk;
+//
+#define CHKBUCKZX_BUCKS     0x01    // The bucks are enabled
+#define CHKBUCKZX_REV       0x02    // This chip rev needs the workaround
+#define CHKBUCKZX_TIMER     0x04    // A valid timer has been allocated
+#define CHKBUCKZX_DEVEN     0x08    // Devices are powered up and enabled
+
+//*****************************************************************************
+//
+//  Prototypes
+//
+//*****************************************************************************
+static void am_hal_sysctrl_buckA_ctimer_isr(void);
+static void am_hal_sysctrl_buckB_ctimer_isr(void);
+
+//*****************************************************************************
+//
+//  Globals
+//
+//*****************************************************************************
+static volatile uint32_t g_ui32BuckTimer = 0;
+static volatile uint32_t g_ui32BuckInputs = 0;
+static volatile bool     g_bBuckRestoreComplete = false;
+static volatile bool     g_bBuckTimed = false;
+static          uint32_t g_ui32SaveCoreBuckZX, g_ui32SaveMemBuckZX;
+static          uint32_t g_buckZX_chk = 0;
+static volatile uint32_t g_ui32CoreBuck;
+
+//
+// Timer configuration for BUCK inputs.
+//
+static const am_hal_ctimer_config_t g_sBuckTimer =
+{
+    // Don't link timers.
+    0,
+
+    // Set up Timer0A.
+    (AM_HAL_CTIMER_FN_ONCE      |
+     AM_HAL_CTIMER_INT_ENABLE   |
+     AM_HAL_CTIMER_BUCK),
+
+    // Set up Timer0B.
+    (AM_HAL_CTIMER_FN_ONCE      |
+     AM_HAL_CTIMER_INT_ENABLE   |
+     AM_HAL_CTIMER_BUCK),
+};
+
+//*****************************************************************************
+//
+// Determine if we need to do the zero cross workaround on this device.
+// Three criteria are used.  All three must be true.
+//  1. Are the bucks enabled?
+//  2. Is the chip rev appropriate for the workaround?
+//  3. Has a timer been allocated to do the workaround?
+//  4. Are certain peripherals powered up?
+//
+// Saves the bitmask to the global g_buckZX_chk.
+// Bitmask bits are defined as: CHKBUCKZX_BUCKS, CHKBUCKZX_REV, CHKBUCKZX_TIMER.
+//
+// Returns true if all criteria are met, false otherwise.
+// g_buckZX_chk can be probed to determine which criteria passed or failed.
+//
+//*****************************************************************************
+static bool
+buckZX_chk(void)
+{
+    uint32_t ui32SupplySrc;
+
+    //
+    // Is this chip rev appropriate to do the workaround?
+    //
+    g_buckZX_chk = AM_BFM(MCUCTRL, CHIPREV, REVMAJ) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B ?
+                   CHKBUCKZX_REV : 0x0;
+
+    //
+    // Has a timer been configured to handle the workaround?
+    //
+    g_buckZX_chk |= ( g_ui32BuckTimer - 1 ) <= BUCK_TIMER_MAX ?
+                    CHKBUCKZX_TIMER : 0x0;
+
+    //
+    // Are either or both of the bucks actually enabled?
+    //
+    ui32SupplySrc = AM_REG(PWRCTRL, SUPPLYSRC);
+
+    g_buckZX_chk |= (ui32SupplySrc &
+                    (AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_M  |
+                     AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_M) ) ?
+                     CHKBUCKZX_BUCKS : 0x0;
+
+    //
+    // Finally, if any peripheral is already powered up, we don't need to do the
+    //  ZX workaround because in this case the bucks remain in active mode.
+    //
+    ui32SupplySrc = AM_REG(PWRCTRL, DEVICEEN);
+
+    g_buckZX_chk |= ( ui32SupplySrc &
+            (AM_REG_PWRCTRL_DEVICEEN_PDM_M          |
+             AM_REG_PWRCTRL_DEVICEEN_UART1_M        |
+             AM_REG_PWRCTRL_DEVICEEN_UART0_M        |
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_M   |
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_M   |
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_M   |
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_M   |
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_M   |
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_M   |
+             AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_M) )      ?
+                0x0 : CHKBUCKZX_DEVEN;
+
+    //
+    // If all 4 criteria were met, we're good to do the workaround.
+    //
+    return ( g_buckZX_chk ==
+             (CHKBUCKZX_BUCKS | CHKBUCKZX_REV |
+              CHKBUCKZX_TIMER | CHKBUCKZX_DEVEN) ) ? true : false;
+}
+
+//*****************************************************************************
+//
+// Set the buck zero cross settings to the values given.
+//
+// ui32Flags, one or more of the following:
+//  SETBUCKZX_USE_PROVIDED_SETTINGS - Use the values provided in the parameters
+//                                    to set the trim value(s).
+//  SETBUCKZX_USE_SAVED_SETTINGS    - Use the values that were previously saved
+//                                    to set the trim value(s).
+//  SETBUCKZX_SAVE_CURR_SETTINGS    - Save the current trim values before
+//                                    setting the new ones.
+//  SETBUCKZX_RESTORE_CORE_ONLY     - Restore the Core trim and save the current
+//                                    value of the core buck trim iff
+//                                    SETBUCKZX_SAVE_CURR_SETTINGS is set.
+//  SETBUCKZX_RESTORE_MEM_ONLY      - Restore the Mem trim and save the current
+//                                    value of the mem buck trim iff
+//                                    SETBUCKZX_SAVE_CURR_SETTINGS is set.
+//  SETBUCKZX_RESTORE_BOTH          - Restore both buck trims and save the
+//                                    current value of both iff
+//                                    SETBUCKZX_SAVE_CURR_SETTINGS is set.
+//
+//*****************************************************************************
+#define SETBUCKZX_USE_PROVIDED_SETTINGS 0x01
+#define SETBUCKZX_USE_SAVED_SETTINGS    0x02
+#define SETBUCKZX_SAVE_CURR_SETTINGS    0x04
+#define SETBUCKZX_RESTORE_CORE_ONLY     0x10
+#define SETBUCKZX_RESTORE_MEM_ONLY      0x20
+#define SETBUCKZX_RESTORE_BOTH          ( SETBUCKZX_RESTORE_CORE_ONLY |     \
+                                          SETBUCKZX_RESTORE_MEM_ONLY )
+static void
+setBuckZX(uint32_t ui32CoreBuckZX, uint32_t ui32MemBuckZX, uint32_t ui32Flags)
+{
+    uint32_t ui32SaveCore, ui32SaveMem, ui32NewCore, ui32NewMem;
+    bool bDoRestore = false;
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Get the current zero cross trim values.
+    //
+    ui32SaveCore = AM_BFR(MCUCTRL, BUCK3, COREBUCKZXTRIM);
+    ui32SaveMem  = AM_BFR(MCUCTRL, BUCK3, MEMBUCKZXTRIM);
+
+    //
+    // Determine which values will be restored.
+    //
+    if ( ui32Flags & SETBUCKZX_USE_SAVED_SETTINGS )
+    {
+        //
+        // Use saved settings
+        //
+        ui32NewCore = g_ui32SaveCoreBuckZX;
+        ui32NewMem  = g_ui32SaveMemBuckZX;
+        bDoRestore = true;
+    }
+    else if ( ui32Flags & SETBUCKZX_USE_PROVIDED_SETTINGS )
+    {
+        //
+        // Use settings provided in the call parameters
+        //
+        ui32NewCore = ui32CoreBuckZX;
+        ui32NewMem  = ui32MemBuckZX;
+        bDoRestore = true;
+    }
+
+    //
+    // Restore the buck Core and Mem trim registers.
+    //
+    if ( bDoRestore )
+    {
+        if ( ui32Flags & SETBUCKZX_RESTORE_CORE_ONLY )
+        {
+            AM_BFW(MCUCTRL, BUCK3, COREBUCKZXTRIM, ui32NewCore);
+        }
+
+        if ( ui32Flags & SETBUCKZX_RESTORE_MEM_ONLY )
+        {
+            AM_BFW(MCUCTRL, BUCK3, MEMBUCKZXTRIM,  ui32NewMem);
+        }
+    }
+
+    if ( ui32Flags & SETBUCKZX_SAVE_CURR_SETTINGS )
+    {
+        //
+        // Save off the zero cross values as read on entry to the function.
+        //
+        if ( ui32Flags & SETBUCKZX_RESTORE_CORE_ONLY )
+        {
+            g_ui32SaveCoreBuckZX = ui32SaveCore;
+        }
+
+        if ( ui32Flags & SETBUCKZX_RESTORE_MEM_ONLY )
+        {
+            g_ui32SaveMemBuckZX  = ui32SaveMem;
+        }
+    }
+
+    //
+    // Done with critical section.
+    //
+    AM_CRITICAL_END_ASM
+}
+
+//*****************************************************************************
+//
+//! @brief Place the core into sleep or deepsleep.
+//!
+//! @param bSleepDeep - False for Normal or True Deep sleep.
+//!
+//! This function puts the MCU to sleep or deepsleep depending on bSleepDeep.
+//!
+//! Valid values for bSleepDeep are:
+//!
+//!     AM_HAL_SYSCTRL_SLEEP_NORMAL
+//!     AM_HAL_SYSCTRL_SLEEP_DEEP
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_sysctrl_sleep(bool bSleepDeep)
+{
+    uint32_t ui32Critical;
+//  uint32_t ui32DebugGpioSleep = g_ui32DebugGpioSleep - 1;
+    bool bBuckZX_chk;
+    volatile uint32_t ui32BuckTimer;
+
+    //
+    // Disable interrupts and save the previous interrupt state.
+    //
+    ui32Critical = am_hal_interrupt_master_disable();
+
+    //
+    // If the user selected DEEPSLEEP and the TPIU is off, attempt to enter
+    // DEEP SLEEP.
+    //
+    if ((bSleepDeep == AM_HAL_SYSCTRL_SLEEP_DEEP) &&
+        (AM_BFM(MCUCTRL, TPIUCTRL, ENABLE) == AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS))
+    {
+        //
+        // Prepare the core for deepsleep (write 1 to the DEEPSLEEP bit).
+        //
+        AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 1);
+
+        //
+        // Check if special buck handling is needed
+        //
+        bBuckZX_chk = buckZX_chk();
+
+        if ( bBuckZX_chk )
+        {
+            ui32BuckTimer = g_ui32BuckTimer - 1;
+
+            //
+            // Before going to sleep, clear the buck timers.
+            // This will also handle the case where we're going back to
+            // sleep before the buck sequence has even completed.
+            //
+            am_hal_ctimer_clear(ui32BuckTimer, AM_HAL_CTIMER_BOTH);
+
+            //
+            // Set CMPR0 of both timerA and timerB to the period value
+            //
+            #define     TIMER_PERIOD_BUCKS  1
+            am_hal_ctimer_period_set(ui32BuckTimer,
+                                     AM_HAL_CTIMER_BOTH,
+                                     TIMER_PERIOD_BUCKS |
+                                     (TIMER_PERIOD_BUCKS << 16),
+                                     0);
+
+            //
+            // Disable bucks before going to sleep.
+            //
+            am_hal_pwrctrl_bucks_disable();
+        }
+
+        //
+        // Execute the sleep instruction.
+        //
+        AM_ASM_WFI;
+
+        //
+        // Return from sleep
+        //
+        if ( bBuckZX_chk )
+        {
+            //
+            // Adjust the core and mem trims
+            //
+            setBuckZX(COREZXVALUE, MEMZXVALUE,
+                      SETBUCKZX_USE_PROVIDED_SETTINGS   |
+                      SETBUCKZX_RESTORE_BOTH );
+
+            //
+            // Delay for 2us before enabling bucks.
+            //
+            am_hal_flash_delay( FLASH_CYCLES_US(2) );
+
+            //
+            // Turn on the bucks
+            //
+            am_hal_pwrctrl_bucks_enable();
+
+            //
+            // Get the actual timer number
+            //
+            ui32BuckTimer = g_ui32BuckTimer - 1;
+
+            //
+            // Initialize the complete flag
+            //
+            g_bBuckRestoreComplete = false;
+
+            //
+            // Initialize the input flags
+            //
+            g_ui32BuckInputs = 0;
+
+            //
+            // Delay for 5us to make sure we're receiving clean buck signals.
+            //
+            am_hal_flash_delay( FLASH_CYCLES_US(5) );
+
+            //
+            // Start timers (set the enable bit, clear the clear bit)
+            //
+            am_hal_ctimer_start(ui32BuckTimer, AM_HAL_CTIMER_BOTH);
+        }
+        else
+        {
+            //
+            // Since we're not doing anything, we're done, so set the done flag.
+            //
+            g_bBuckRestoreComplete = true;
+        }
+    }
+    else
+    {
+        //
+        // Prepare the core for normal sleep (write 0 to the DEEPSLEEP bit).
+        //
+        AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 0);
+
+        //
+        // Go to sleep.
+        //
+        AM_ASM_WFI;
+    }
+
+    //
+    // Restore the interrupt state.
+    //
+    am_hal_interrupt_master_set(ui32Critical);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the floating point module.
+//!
+//! Call this function to enable the ARM hardware floating point module.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_sysctrl_fpu_enable(void)
+{
+    //
+    // Enable access to the FPU in both privileged and user modes.
+    // NOTE: Write 0s to all reserved fields in this register.
+    //
+    AM_REG(SYSCTRL, CPACR) = (AM_REG_SYSCTRL_CPACR_CP11(0x3) |
+                             AM_REG_SYSCTRL_CPACR_CP10(0x3));
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the floating point module.
+//!
+//! Call this function to disable the ARM hardware floating point module.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_sysctrl_fpu_disable(void)
+{
+    //
+    // Disable access to the FPU in both privileged and user modes.
+    // NOTE: Write 0s to all reserved fields in this register.
+    //
+    AM_REG(SYSCTRL, CPACR) = 0x00000000                     &
+                          ~(AM_REG_SYSCTRL_CPACR_CP11(0x3) |
+                            AM_REG_SYSCTRL_CPACR_CP10(0x3));
+}
+
+//*****************************************************************************
+//
+//! @brief Enable stacking of FPU registers on exception entry.
+//!
+//! @param bLazy - Set to "true" to enable "lazy stacking".
+//!
+//! This function allows the core to save floating-point information to the
+//! stack on exception entry. Setting the bLazy option enables "lazy stacking"
+//! for interrupt handlers.  Normally, mixing floating-point code and interrupt
+//! driven routines causes increased interrupt latency, because the core must
+//! save extra information to the stack upon exception entry. With the lazy
+//! stacking option enabled, the core will skip the saving of floating-point
+//! registers when possible, reducing average interrupt latency.
+//!
+//! @note This function should be called before the floating-point module is
+//! used in interrupt-driven code. If it is not called, the core will not have
+//! any way to save context information for floating-point variables on
+//! exception entry.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_sysctrl_fpu_stacking_enable(bool bLazy)
+{
+    if ( bLazy )
+    {
+        //
+        // Enable automatic saving of FPU registers on exception entry, using lazy
+        // context saving.
+        //
+        AM_REG(SYSCTRL, FPCCR) |= (AM_REG_SYSCTRL_FPCCR_ASPEN(0x1) |
+                                   AM_REG_SYSCTRL_FPCCR_LSPEN(0x1));
+    }
+    else
+    {
+        //
+        // Enable automatic saving of FPU registers on exception entry.
+        //
+        AM_REG(SYSCTRL, FPCCR) |= AM_REG_SYSCTRL_FPCCR_ASPEN(0x1);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Disable FPU register stacking on exception entry.
+//!
+//! This function disables all stacking of floating point registers for
+//! interrupt handlers.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_sysctrl_fpu_stacking_disable(void)
+{
+    //
+    // Enable automatic saving of FPU registers on exception entry, using lazy
+    // context saving.
+    //
+    AM_REG(SYSCTRL, FPCCR) &= ~(AM_REG_SYSCTRL_FPCCR_ASPEN(0x1) |
+                                AM_REG_SYSCTRL_FPCCR_LSPEN(0x1));
+}
+
+//*****************************************************************************
+//
+//! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl.
+//!
+//! This function issues a system wide reset (Apollo POR level reset).
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_sysctrl_aircr_reset(void)
+{
+    //
+    // Set the system reset bit in the AIRCR register
+    //
+    AM_REG(SYSCTRL, AIRCR) = AM_REG_SYSCTRL_AIRCR_VECTKEY(0x5FA) |
+                             AM_REG_SYSCTRL_AIRCR_SYSRESETREQ(1);
+}
+
+//*****************************************************************************
+//
+//! @brief Buck CTimer ISR initializer.
+//!
+//! @param ui32BuckTimerNumber - Timer number to be used for handling the buck.
+//!                              Must be 0-3.
+//!
+//! If called with an invalid timer (that is, not 0 - 3, or greater than
+//! BUCK_TIMER_MAX), then the workaround will not be enabled.
+//!
+//! Instead, the bucks will be initialized with a value that will avoid the
+//! issues described in the Errata (ERR019).  However, this will cause a
+//! less efficient energy usage condtion.
+//!
+//! @return 0.
+//
+//*****************************************************************************
+uint32_t
+am_hal_sysctrl_buck_ctimer_isr_init(uint32_t ui32BuckTimerNumber)
+{
+    uint32_t ui32RetVal = 0;
+
+    //
+    // Initialize the input flags
+    //
+    g_ui32BuckInputs = 0;
+
+    //
+    // Initialize operation complete flag
+    //
+    g_bBuckRestoreComplete = false;
+
+    //
+    // Initialize to assume there is no valid timer.
+    //
+    g_ui32BuckTimer = 0;
+
+    if ( ui32BuckTimerNumber > BUCK_TIMER_MAX )
+    {
+        if ( ( ui32BuckTimerNumber & 0xFFFF0000 ) ==
+             AM_HAL_SYSCTRL_BUCK_CTIMER_ZX_CONSTANT )
+        {
+            //
+            // The caller is asking for the hard option, which changes the
+            //  settings to the more noise-immune, if less efficient, settings.
+            // While we're at it, go ahead and save off the current settings.
+            //
+            if ( (ui32BuckTimerNumber & 0x0000FFFF) == 0 )
+            {
+                setBuckZX(COREZXVALUE, MEMZXVALUE,
+                          SETBUCKZX_USE_PROVIDED_SETTINGS   |
+                          SETBUCKZX_SAVE_CURR_SETTINGS      |
+                          SETBUCKZX_RESTORE_BOTH );
+            }
+            else
+            {
+                uint32_t ui32Core, ui32Mem;
+
+                //
+                // Use the setting provided in the parameter.
+                //
+                ui32Core = (((ui32BuckTimerNumber & 0x001F) >> 0) - 1) & 0xF;
+                ui32Mem  = (((ui32BuckTimerNumber & 0x1F00) >> 8) - 1) & 0xF;
+
+                setBuckZX(ui32Core, ui32Mem,
+                          SETBUCKZX_USE_PROVIDED_SETTINGS   |
+                          SETBUCKZX_SAVE_CURR_SETTINGS      |
+                          SETBUCKZX_RESTORE_BOTH );
+            }
+        }
+    }
+    else
+    {
+        //
+        // Save off the current trim settings (but don't change any settings).
+        //
+        setBuckZX(0, 0, SETBUCKZX_SAVE_CURR_SETTINGS | SETBUCKZX_RESTORE_BOTH);
+
+        //
+        // The timer number will be maintained as (n + 1).  Therefore, a value
+        // of 0 saved in the global is an invalid timer.  1=timer0, 2=timer1...
+        //
+        g_ui32BuckTimer = ui32BuckTimerNumber + 1;
+
+        //
+        // Register the timer ISRs
+        //
+        am_hal_ctimer_int_register( AM_HAL_CTIMER_INT_TIMERA0C0 <<
+                                    (ui32BuckTimerNumber * 2),
+                                     am_hal_sysctrl_buckA_ctimer_isr );
+
+        am_hal_ctimer_int_register( AM_HAL_CTIMER_INT_TIMERB0C0 <<
+                                    (ui32BuckTimerNumber * 2),
+                                     am_hal_sysctrl_buckB_ctimer_isr );
+
+        //
+        // Determine which timer input (A or B) is core buck and which is mem
+        // buck based on the timer number.
+        //  For CTIMER 0 & 1: Timer A is mem  buck, Timer B is core buck
+        //  For CTIMER 2 & 3: Timer A is core buck, Timer B is mem  buck
+        //
+        if ( (ui32BuckTimerNumber == 0)  ||  (ui32BuckTimerNumber == 1) )
+        {
+            //
+            // Indicate that TimerB is core buck.
+            //
+            g_ui32CoreBuck = COREBUCK_TIMERB;
+        }
+        else
+        {
+            //
+            // Indicate that TimerA is core buck
+            //
+            g_ui32CoreBuck = COREBUCK_TIMERA;
+        }
+
+        //
+        // Clear and configure the timers
+        //
+        am_hal_ctimer_clear(ui32BuckTimerNumber, AM_HAL_CTIMER_BOTH);
+
+        am_hal_ctimer_config(ui32BuckTimerNumber,
+                             (am_hal_ctimer_config_t*)&g_sBuckTimer);
+
+        //
+        // Enable the interrupts for timers A and B
+        //
+        am_hal_ctimer_int_enable( (AM_HAL_CTIMER_INT_TIMERA0C0 |
+                                   AM_HAL_CTIMER_INT_TIMERB0C0 ) <<
+                                   (ui32BuckTimerNumber * 2) );
+
+        //
+        // Enable the timer interrupt in the NVIC.
+        //
+        am_hal_interrupt_enable(AM_HAL_INTERRUPT_CTIMER);
+    }
+
+    return ui32RetVal;
+}
+
+//*****************************************************************************
+//
+// Get buck update complete status.
+//
+//*****************************************************************************
+bool
+am_hal_sysctrl_buck_update_complete(void)
+{
+    return g_bBuckRestoreComplete;
+}
+
+//*****************************************************************************
+//
+// Buck CTIMER ISR (for handling buck switching via TimerA).
+//
+// Note: This handler assumes that the interrupt is cleared in am_ctimer_isr().
+//
+//*****************************************************************************
+static void
+am_hal_sysctrl_buckA_ctimer_isr(void)
+{
+    volatile uint32_t ui32BuckTimer = g_ui32BuckTimer - 1;
+
+    //
+    // Begin critical section.
+    // Although a relatively long time, the following 2us delay is critically
+    // timed for re-trimming the buck and thus cannot be extended.  Therefore,
+    // we must keep it inside the critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Delay for 2us.
+    //
+    am_hal_flash_delay( FLASH_CYCLES_US(2) );
+
+    //
+    // Determine which buck (core or mem) needs to be updated.
+    //
+    if ( g_ui32CoreBuck == COREBUCK_TIMERA )
+    {
+        //
+        // Timer A buck signal is the CORE buck.
+        // Restore the core buck.
+        //
+        setBuckZX(0, 0, SETBUCKZX_RESTORE_CORE_ONLY |
+                        SETBUCKZX_USE_SAVED_SETTINGS );
+    }
+    else
+    {
+        //
+        // Timer A buck signal is the MEM buck.
+        // Restore the mem buck.
+        //
+        setBuckZX(0, 0, SETBUCKZX_RESTORE_MEM_ONLY  |
+                        SETBUCKZX_USE_SAVED_SETTINGS );
+    }
+
+    g_ui32BuckInputs |= 0x1;
+
+    if ( g_ui32BuckInputs == 0x3 )
+    {
+        g_bBuckRestoreComplete = true;
+        g_ui32BuckInputs = 0;
+    }
+
+    //
+    // End critical section.
+    //
+    AM_CRITICAL_END_ASM
+}
+
+//*****************************************************************************
+//
+// Buck CTIMER ISR (for handling buck switching via TimerB).
+//
+// Note: This handler assumes that the interrupt is cleared in am_ctimer_isr().
+//
+//*****************************************************************************
+static void
+am_hal_sysctrl_buckB_ctimer_isr(void)
+{
+    volatile uint32_t ui32BuckTimer = g_ui32BuckTimer - 1;
+
+    //
+    // Begin critical section.
+    // Although a relatively long time, the following 2us delay is critically
+    // timed for re-trimming the buck and thus cannot be extended.  Therefore,
+    // we must keep it inside the critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Delay for 2us.
+    //
+    am_hal_flash_delay( FLASH_CYCLES_US(2) );
+
+    //
+    // Determine which buck (core or mem) needs to be updated.
+    //
+    if ( g_ui32CoreBuck == COREBUCK_TIMERB )
+    {
+        //
+        // Timer B buck signal is the CORE buck.
+        // Restore the core buck.
+        //
+        setBuckZX(0, 0, SETBUCKZX_RESTORE_CORE_ONLY |
+                        SETBUCKZX_USE_SAVED_SETTINGS );
+    }
+    else
+    {
+        //
+        // Timer B buck signal is the MEM buck.
+        // Restore the mem buck.
+        //
+        setBuckZX(0, 0, SETBUCKZX_RESTORE_MEM_ONLY  |
+                        SETBUCKZX_USE_SAVED_SETTINGS );
+    }
+
+    g_ui32BuckInputs |= 0x2;
+
+    if ( g_ui32BuckInputs == 0x3 )
+    {
+        g_bBuckRestoreComplete = true;
+        g_ui32BuckInputs = 0;
+    }
+
+    //
+    // End critical section.
+    //
+    AM_CRITICAL_END_ASM
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h
new file mode 100644
index 0000000000..34c72b4173
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h
@@ -0,0 +1,119 @@
+//*****************************************************************************
+//
+//! am_hal_sysctrl.h
+//! @file
+//!
+//! @brief Functions for interfacing with the M4F system control registers
+//!
+//! @addtogroup sysctrl2 System Control (SYSCTRL)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_SYSCTRL_H
+#define AM_HAL_SYSCTRL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Definitions for sleep mode parameter
+//
+//*****************************************************************************
+#define AM_HAL_SYSCTRL_SLEEP_DEEP       true
+#define AM_HAL_SYSCTRL_SLEEP_NORMAL     false
+
+//*****************************************************************************
+//
+// Parameters for am_hal_sysctrl_buck_ctimer_isr_init()
+//
+//*****************************************************************************
+//
+// Define the maximum valid timer number
+//
+#define BUCK_TIMER_MAX                  (AM_HAL_CTIMER_TIMERS_NUM - 1)
+
+//
+// Define the valid timer numbers
+//
+#define AM_HAL_SYSCTRL_BUCK_CTIMER_TIMER0   0
+#define AM_HAL_SYSCTRL_BUCK_CTIMER_TIMER1   1
+#define AM_HAL_SYSCTRL_BUCK_CTIMER_TIMER2   2
+#define AM_HAL_SYSCTRL_BUCK_CTIMER_TIMER3   3
+
+//
+// The following is an invalid timer number. If used, it is the caller telling
+// the HAL to use the "Hard Option", which applies a constant value to the zero
+// cross. The applied value is more noise immune, if less energy efficent.
+//
+#define AM_HAL_SYSCTRL_BUCK_CTIMER_ZX_CONSTANT      0x01000000  // No timer, apply a constant value
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void     am_hal_sysctrl_sleep(bool bSleepDeep);
+extern void     am_hal_sysctrl_fpu_enable(void);
+extern void     am_hal_sysctrl_fpu_disable(void);
+extern void     am_hal_sysctrl_fpu_stacking_enable(bool bLazy);
+extern void     am_hal_sysctrl_fpu_stacking_disable(void);
+extern void     am_hal_sysctrl_aircr_reset(void);
+
+//
+// Apollo2 zero-cross buck/ctimer related functions
+//
+extern uint32_t am_hal_sysctrl_buck_ctimer_isr_init(uint32_t ui32BuckTimerNumber);
+extern bool     am_hal_sysctrl_buck_update_complete(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_SYSCTRL_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c
new file mode 100644
index 0000000000..3654910495
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c
@@ -0,0 +1,453 @@
+//*****************************************************************************
+//
+//  am_hal_systick.c
+//! @file
+//!
+//! @brief Functions for interfacing with the SYSTICK
+//!
+//! @addtogroup systick2 System Timer (SYSTICK)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+
+//*****************************************************************************
+//
+// Macro definitions
+//
+//*****************************************************************************
+#define SYSTICK_MAX_TICKS   ((1 << 24)-1)
+#define MAX_U32             (0xffffffff)
+
+//*****************************************************************************
+//
+//! @brief Start the SYSTICK.
+//!
+//! This function starts the systick timer.
+//!
+//! @note This timer does not run in deep-sleep mode as it runs from the core
+//! clock, which is gated in deep-sleep. If a timer is needed in deep-sleep use
+//! one of the ctimers instead. Also to note is this timer will consume higher
+//! power than the ctimers.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_systick_start(void)
+{
+    //
+    // Start the systick timer.
+    //
+    AM_REG(SYSTICK, SYSTCSR) |= AM_REG_SYSTICK_SYSTCSR_ENABLE_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Stop the SYSTICK.
+//!
+//! This function stops the systick timer.
+//!
+//! @note This timer does not run in deep-sleep mode as it runs from the core
+//! clock, which is gated in deep-sleep. If a timer is needed in deep-sleep use
+//! one of the ctimers instead. Also to note is this timer will consume higher
+//! power than the ctimers.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_systick_stop(void)
+{
+    //
+    // Stop the systick timer.
+    //
+    AM_REG(SYSTICK, SYSTCSR) &= ~AM_REG_SYSTICK_SYSTCSR_ENABLE_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the interrupt in the SYSTICK.
+//!
+//! This function enables the interupt in the systick timer.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_systick_int_enable(void)
+{
+    //
+    // Enable the systick timer interrupt.
+    //
+    AM_REG(SYSTICK, SYSTCSR) |= AM_REG_SYSTICK_SYSTCSR_TICKINT_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the interrupt in the SYSTICK.
+//!
+//! This function disables the interupt in the systick timer.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_systick_int_disable(void)
+{
+    //
+    // Disable the systick timer interrupt.
+    //
+    AM_REG(SYSTICK, SYSTCSR) &= ~AM_REG_SYSTICK_SYSTCSR_TICKINT_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Reads the interrupt status.
+//!
+//! This function reads the interrupt status in the systick timer.
+//!
+//! @return the interrupt status.
+//
+//*****************************************************************************
+uint32_t
+am_hal_systick_int_status_get(void)
+{
+    //
+    // Return the systick timer interrupt status.
+    //
+    return AM_REG(SYSTICK, SYSTCSR) & AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Reset the interrupt in the SYSTICK.
+//!
+//! This function resets the systick timer by clearing out the configuration
+//! register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_systick_reset(void)
+{
+    //
+    // Reset the systick timer interrupt.
+    //
+    AM_REG(SYSTICK, SYSTCSR) = 0x0;
+}
+
+//*****************************************************************************
+//
+//! @brief Load the value into the SYSTICK.
+//!
+//! @param ui32LoadVal the desired load value for the systick. Maximum value is
+//! 0x00FF.FFFF.
+//!
+//! This function loads the desired value into the systick timer.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_systick_load(uint32_t ui32LoadVal)
+{
+    //
+    // Write the reload register.
+    //
+    AM_REG(SYSTICK, SYSTRVR) = ui32LoadVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Get the current count value in the SYSTICK.
+//!
+//! This function gets the current count value in the systick timer.
+//!
+//! @return Current count value.
+//
+//*****************************************************************************
+uint32_t
+am_hal_systick_count(void)
+{
+    //
+    // Return the current systick timer count value.
+    //
+    return AM_REG(SYSTICK, SYSTCVR);
+}
+
+//*****************************************************************************
+//
+//! @brief Wait the specified number of ticks.
+//!
+//! This function delays for the given number of SysTick ticks.
+//!
+//! @note If the SysTick timer is being used elsewhere, it will be corrupted
+//! by calling this function.
+//!
+//! @return 0 if successful.
+//
+//*****************************************************************************
+uint32_t
+am_hal_systick_wait_ticks(uint32_t u32Ticks)
+{
+
+    if ( u32Ticks == 0 )
+    {
+        u32Ticks++;                 // Make sure we get the COUNTFLAG
+    }
+
+    //
+    //  The proper SysTick initialization sequence is: (p 4-36 of the M4 UG).
+    //      1. Program reload value
+    //      2. Clear current value
+    //      3. Program CSR
+    //
+    // Set the reload value to the required number of ticks.
+    //
+    AM_REG(SYSTICK, SYSTRVR) = u32Ticks;
+
+    //
+    // Clear the current count.
+    //
+    AM_REG(SYSTICK, SYSTCVR) = 0x0;
+
+    //
+    // Set to use the processor clock, but don't cause an exception (we'll poll).
+    //
+    AM_REG(SYSTICK, SYSTCSR) = AM_REG_SYSTICK_SYSTCSR_ENABLE_M;
+
+    //
+    // Poll till done
+    //
+    while ( !(AM_REG(SYSTICK, SYSTCSR) & AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_M) );
+
+    //
+    // And disable systick before exiting.
+    //
+    AM_REG(SYSTICK, SYSTCSR) = 0;
+
+    return 0;
+}
+
+//*****************************************************************************
+//
+//! @brief Delay the specified number of microseconds.
+//!
+//! This function will use the SysTick timer to delay until the specified
+//!  number of microseconds have elapsed.  It uses the processor clocks and
+//!  takes into account the current CORESEL setting.
+//!
+//! @note If the SysTick timer is being used elsewhere, it will be corrupted
+//! by calling this function.
+//!
+//! @return Total number of SysTick ticks delayed.
+//
+//*****************************************************************************
+uint32_t
+am_hal_systick_delay_us(uint32_t u32NumUs)
+{
+    uint32_t u32ClkFreq, u32nLoops, u32Ticks, uRet;
+    uint32_t u32CoreSel = AM_BFR(CLKGEN, CCTRL, CORESEL);
+
+    u32nLoops = 1;
+    switch (u32CoreSel)
+    {
+        //
+        // We need to compute the required number of ticks.  To do so and to
+        //   minimize divide operations, we'll use the following equation:
+        // u32Ticks = (u32NumUs * HFCR_EXACT)/1000000
+        //          = (u32NumUs * (HFCR_EXACT * 1024)/1000000) / 1024
+        // The values for the variable u32ClkFreq are computed as follows:
+        //  u32ClkFreq = (24390200 * 1024) / ((clksel+1)*1000000);
+        //  (and we'll do the remaining divide by 1024, using a shift, later).
+        //
+        case 0:
+            u32ClkFreq = 24975;
+            if ( u32NumUs > ((SYSTICK_MAX_TICKS / 24975)*1024) )
+            {
+                u32nLoops = (u32NumUs / ((SYSTICK_MAX_TICKS / 24975)*1024)) + 1;
+                u32NumUs /= u32nLoops;
+            }
+            if ( u32NumUs > (MAX_U32 / 24975) )
+            {
+                u32Ticks = (u32NumUs >> 10) * u32ClkFreq;
+            }
+            else
+            {
+                u32Ticks = (u32NumUs * u32ClkFreq) >> 10;
+            }
+            break;
+        case 1:
+            u32ClkFreq = 12487;
+            if ( u32NumUs > ((SYSTICK_MAX_TICKS / 12487)*1024) )
+            {
+                u32nLoops = (u32NumUs / ((SYSTICK_MAX_TICKS / 12487)*1024)) + 1;
+                u32NumUs /= u32nLoops;
+            }
+            if ( u32NumUs > (MAX_U32 / 12487) )
+            {
+                u32Ticks = (u32NumUs >> 10) * u32ClkFreq;
+            }
+            else
+            {
+                u32Ticks = (u32NumUs * u32ClkFreq) >> 10;
+            }
+            break;
+        case 2:
+            u32ClkFreq = 8325;
+            if ( u32NumUs > ((SYSTICK_MAX_TICKS / 8325)*1024) )
+            {
+                u32nLoops = (u32NumUs / ((SYSTICK_MAX_TICKS / 8325)*1024)) + 1;
+                u32NumUs /= u32nLoops;
+            }
+            if ( u32NumUs > (MAX_U32 / 8325) )
+            {
+                u32Ticks = (u32NumUs >> 10) * u32ClkFreq;
+            }
+            else
+            {
+                u32Ticks = (u32NumUs * u32ClkFreq) >> 10;
+            }
+            break;
+        case 3:
+            u32ClkFreq = 6243;
+            if ( u32NumUs > ((SYSTICK_MAX_TICKS / 6243)*1024) )
+            {
+                u32nLoops = (u32NumUs / ((SYSTICK_MAX_TICKS / 6243)*1024)) + 1;
+                u32NumUs /= u32nLoops;
+            }
+            if ( u32NumUs > (MAX_U32 / 6243) )
+            {
+                u32Ticks = (u32NumUs >> 10) * u32ClkFreq;
+            }
+            else
+            {
+                u32Ticks = (u32NumUs * u32ClkFreq) >> 10;
+            }
+            break;
+        case 4:
+            u32ClkFreq = 4995;
+            if ( u32NumUs > ((SYSTICK_MAX_TICKS / 4995)*1024) )
+            {
+                u32nLoops = (u32NumUs / ((SYSTICK_MAX_TICKS / 4995)*1024)) + 1;
+                u32NumUs /= u32nLoops;
+            }
+            if ( u32NumUs > (MAX_U32 / 4995) )
+            {
+                u32Ticks = (u32NumUs >> 10) * u32ClkFreq;
+            }
+            else
+            {
+                u32Ticks = (u32NumUs * u32ClkFreq) >> 10;
+            }
+            break;
+        case 5:
+            u32ClkFreq = 4162;
+            if ( u32NumUs > ((SYSTICK_MAX_TICKS / 4162)*1024) )
+            {
+                u32nLoops = (u32NumUs / ((SYSTICK_MAX_TICKS / 4162)*1024)) + 1;
+                u32NumUs /= u32nLoops;
+            }
+            if ( u32NumUs > (MAX_U32 / 4162) )
+            {
+                u32Ticks = (u32NumUs >> 10) * u32ClkFreq;
+            }
+            else
+            {
+                u32Ticks = (u32NumUs * u32ClkFreq) >> 10;
+            }
+            break;
+        case 6:
+            u32ClkFreq = 3567;
+            if ( u32NumUs > ((SYSTICK_MAX_TICKS / 3567)*1024) )
+            {
+                u32nLoops = (u32NumUs / ((SYSTICK_MAX_TICKS / 3567)*1024)) + 1;
+                u32NumUs /= u32nLoops;
+            }
+            if ( u32NumUs > (MAX_U32 / 3567) )
+            {
+                u32Ticks = (u32NumUs >> 10) * u32ClkFreq;
+            }
+            else
+            {
+                u32Ticks = (u32NumUs * u32ClkFreq) >> 10;
+            }
+            break;
+        case 7:
+            u32ClkFreq = 3121;
+            if ( u32NumUs > ((SYSTICK_MAX_TICKS / 3121)*1024) )
+            {
+                u32nLoops = (u32NumUs / ((SYSTICK_MAX_TICKS / 3121)*1024)) + 1;
+                u32NumUs /= u32nLoops;
+            }
+            if ( u32NumUs > (MAX_U32 / 3121) )
+            {
+                u32Ticks = (u32NumUs >> 10) * u32ClkFreq;
+            }
+            else
+            {
+                u32Ticks = (u32NumUs * u32ClkFreq) >> 10;
+            }
+            break;
+        default:
+            u32Ticks = 1;
+            break;
+    } // switch()
+
+    uRet = u32Ticks * u32nLoops;
+    while ( u32nLoops-- )
+    {
+        am_hal_systick_wait_ticks(u32Ticks);
+    }
+
+    return uRet;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h
new file mode 100644
index 0000000000..bd5e576938
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h
@@ -0,0 +1,83 @@
+//*****************************************************************************
+//
+//  am_hal_systick.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the SYSTICK.
+//!
+//! @addtogroup systick2 System Timer (SYSTICK)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_SYSTICK_H
+#define AM_HAL_SYSTICK_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_systick_start(void);
+extern void am_hal_systick_stop(void);
+extern void am_hal_systick_int_enable(void);
+extern void am_hal_systick_int_disable(void);
+extern uint32_t am_hal_systick_int_status_get(void);
+extern void am_hal_systick_reset(void);
+extern void am_hal_systick_load(uint32_t ui32LoadVal);
+extern uint32_t am_hal_systick_count(void);
+extern uint32_t am_hal_systick_wait_ticks(uint32_t u32Ticks);
+extern uint32_t am_hal_systick_delay_us(uint32_t u32NumUs);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_SYSTICK_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c
new file mode 100644
index 0000000000..722f22fa13
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c
@@ -0,0 +1,381 @@
+//*****************************************************************************
+//
+//  am_hal_tpiu.c
+//! @file
+//!
+//! @brief Support functions for the ARM TPIU module
+//!
+//! Provides support functions for configuring the ARM TPIU module
+//!
+//! @addtogroup tpiu2 Trace Port Interface Unit (TPIU)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Enable the clock to the TPIU module.
+//!
+//! This function enables the clock to the TPIU module.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_tpiu_clock_enable(void)
+{
+    //
+    // Enable the TPIU clock
+    //
+    AM_REG(MCUCTRL, TPIUCTRL) |= AM_REG_MCUCTRL_TPIUCTRL_ENABLE_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the clock to the TPIU module.
+//!
+//! This function disables the clock to the TPIU module.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_tpiu_clock_disable(void)
+{
+    //
+    // Disable the TPIU clock
+    //
+    AM_REG(MCUCTRL, TPIUCTRL) &= ~AM_REG_MCUCTRL_TPIUCTRL_ENABLE_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Set the output port width of the TPIU
+//!
+//! @param ui32PortWidth - The desired port width (in bits)
+//!
+//! This function uses the TPIU_CSPSR register to set the desired output port
+//! width of the TPIU.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_tpiu_port_width_set(uint32_t ui32PortWidth)
+{
+   AM_REG(TPIU, CSPSR) = 1 << (ui32PortWidth - 1);
+}
+
+//*****************************************************************************
+//
+//! @brief Read the supported_output port width of the TPIU
+//!
+//! This function uses the \e TPIU_SSPSR register to set the supported output
+//! port widths of the TPIU.
+//!
+//! @return Current width of the TPIU output port
+//
+//*****************************************************************************
+uint32_t
+am_hal_tpiu_supported_port_width_get(void)
+{
+    uint32_t i, ui32WidthValue;
+
+    //
+    // Read the supported width register.
+    //
+    ui32WidthValue = AM_REG(TPIU, SSPSR);
+
+    //
+    // The register value is encoded in a one-hot format, so the position of
+    // the single set bit determines the actual width of the port.
+    //
+    for (i = 1; i < 32; i++)
+    {
+        //
+        // Check each bit for a '1'. When we find it, our current loop index
+        // will be equal to the port width.
+        //
+        if (ui32WidthValue == (0x1 << (i - 1)))
+        {
+            return i;
+        }
+    }
+
+    //
+    // We should never get here, but if we do, just return the smallest
+    // possible value for a supported trace port width.
+    //
+    return 1;
+}
+
+//*****************************************************************************
+//
+//! @brief Read the output port width of the TPIU
+//!
+//! This function uses the \e TPIU_CSPSR register to set the desired output
+//! port width of the TPIU.
+//!
+//! @return Current width of the TPIU output port
+//
+//*****************************************************************************
+uint32_t
+am_hal_tpiu_port_width_get(void)
+{
+    uint32_t ui32Temp;
+    uint32_t ui32Width;
+
+    ui32Width = 1;
+    ui32Temp = AM_REG(TPIU, CSPSR);
+
+    while ( !(ui32Temp & 1) )
+    {
+        ui32Temp = ui32Temp >> 1;
+        ui32Width++;
+
+        if (ui32Width > 32)
+        {
+            ui32Width = 0;
+            break;
+        }
+    }
+
+    //
+    // Current width of the TPIU output port.
+    //
+    return ui32Width;
+}
+
+//*****************************************************************************
+//
+//! @brief Configure the TPIU based on the values in the configuration struct.
+//!
+//! @param psConfig - pointer to an am_hal_tpiu_config_t structure containing
+//! the desired configuration information.
+//!
+//! This function reads the provided configuration structure, and sets the
+//! relevant TPIU registers to achieve the desired configuration.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig)
+{
+    //
+    // Set the clock freq in the MCUCTRL register.
+    //
+    AM_REG(MCUCTRL, TPIUCTRL) |= psConfig->ui32TraceClkIn;
+
+    //
+    // Set the desired protocol.
+    //
+    AM_REG(TPIU, SPPR) = psConfig->ui32PinProtocol;
+
+    //
+    // Set the parallel port width. This may be redundant if the user has
+    // selected a serial protocol, but we'll set it anyway.
+    //
+    AM_REG(TPIU, CSPSR) = (1 << (psConfig->ui32ParallelPortSize - 1));
+
+    //
+    // Set the clock prescaler.
+    //
+    AM_REG(TPIU, ACPR) = psConfig->ui32ClockPrescaler;
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the TPIU
+//!
+//! This function enables the ARM TPIU by setting the TPIU registers and then
+//! enabling the TPIU clock source in MCU control register.
+//!
+//! @param psConfig - structure for configuration.
+//!     If ui32SetItmBaud, the other structure members are used to set the
+//!      TPIU configuration.
+//!     But for simplicity, ui32SetItmBaud can be set to one of the
+//!      following, in which case all other structure members are ignored.
+//!      In this case, the given BAUD rate is based on a div-by-8 HFRC clock.
+//!         AM_HAL_TPIU_BAUD_57600
+//!         AM_HAL_TPIU_BAUD_115200
+//!         AM_HAL_TPIU_BAUD_230400
+//!         AM_HAL_TPIU_BAUD_460800
+//!         AM_HAL_TPIU_BAUD_500000
+//!         AM_HAL_TPIU_BAUD_1M
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig)
+{
+    uint32_t ui32HFRC, ui32SWOscaler, ui32ITMbitrate;
+
+    ui32ITMbitrate = psConfig->ui32SetItmBaud;
+
+    //
+    // TPIU formatter & flush control register.
+    //
+    AM_REG(TPIU, FFCR) = 0;
+
+    if ( ui32ITMbitrate )
+    {
+        //
+        // Set the Current Parallel Port Size (note - only 1 bit can be set).
+        //
+        AM_REG(TPIU, CSPSR) = AM_REG_TPIU_CSPSR_CWIDTH_1BIT;
+
+        //
+        // Use some default assumptions to set the ITM frequency.
+        //
+        if ( (ui32ITMbitrate < AM_HAL_TPIU_BAUD_57600 )  ||
+             (ui32ITMbitrate > AM_HAL_TPIU_BAUD_2M ) )
+        {
+            ui32ITMbitrate = AM_HAL_TPIU_BAUD_DEFAULT;
+        }
+
+        //
+        // Get the current HFRC frequency.
+        //
+        ui32HFRC = am_hal_clkgen_sysclk_get();
+
+        //
+        // Compute the SWO scaler value.
+        //
+        if ( ui32HFRC != 0xFFFFFFFF )
+        {
+            ui32SWOscaler = ((ui32HFRC / 8) / ui32ITMbitrate) - 1;
+        }
+        else
+        {
+            ui32SWOscaler = ( (AM_HAL_CLKGEN_FREQ_MAX_HZ / 8) /
+                              AM_HAL_TPIU_BAUD_DEFAULT ) - 1;
+        }
+
+        //
+        // Set the scaler value.
+        //
+        AM_REG(TPIU, ACPR) = AM_REG_TPIU_ACPR_SWOSCALER(ui32SWOscaler);
+
+        //
+        // Set for UART mode
+        //
+        AM_REG(TPIU, SPPR) = AM_REG_TPIU_SPPR_TXMODE_UART;
+
+        //
+        // Make sure we are not in test mode (important for proper deep sleep
+        // operation).
+        //
+        AM_REG(TPIU, ITCTRL) = AM_REG_TPIU_ITCTRL_MODE_NORMAL;
+
+        //
+        // Enable the TPIU clock source in MCU control.
+        // Set TPIU clock for HFRC/8 (6 or 3 MHz) operation.
+        //
+        AM_REGn(MCUCTRL, 0, TPIUCTRL) =
+                AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_8 |
+                AM_REG_MCUCTRL_TPIUCTRL_ENABLE_EN;
+    }
+    else
+    {
+        //
+        // Set the configuration according to the structure values.
+        //
+
+        //
+        // Set the Asynchronous Clock Prescaler Register.
+        //
+        AM_REG(TPIU, ACPR) = psConfig->ui32ClockPrescaler;
+
+        //
+        // Set the Selected Pin Protocol Register.
+        //  e.g. AM_REG_TPIU_SPPR_TXMODE_UART
+        //
+        AM_REG(TPIU, SPPR) = psConfig->ui32PinProtocol;
+
+        //
+        // Set the Current Parallel Port Size (note - only 1 bit can be set).
+        // This may be redundant if the user has selected a serial protocol,
+        // but we'll set it anyway.
+        //
+        AM_REG(TPIU, CSPSR) = (1 << (psConfig->ui32ParallelPortSize - 1));
+
+        //
+        // Set the clock freq in the MCUCTRL register.
+        //
+        AM_REG(MCUCTRL, TPIUCTRL) |= psConfig->ui32TraceClkIn;
+    }
+
+    //
+    // Wait for 50us for the data to flush out.
+    //
+    am_hal_itm_delay_us(50);
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the TPIU
+//!
+//! This function disables the ARM TPIU by disabling the TPIU clock source
+//! in MCU control register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_tpiu_disable(void)
+{
+    //
+    // Disable the TPIU clock source in MCU control.
+    //
+    AM_REG(MCUCTRL, TPIUCTRL) = AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz |
+                                AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h
new file mode 100644
index 0000000000..9739034a18
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h
@@ -0,0 +1,193 @@
+//*****************************************************************************
+//
+//  am_hal_tpiu.h
+//! @file
+//!
+//! @brief Definitions and structures for working with the TPIU.
+//!
+//! @addtogroup tpiu2 Trace Port Interface Unit (TPIU)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_TPIU_H
+#define AM_HAL_TPIU_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// TPIU bit rate defines.
+//
+//*****************************************************************************
+#define AM_HAL_TPIU_BAUD_57600      (115200 / 2)
+#define AM_HAL_TPIU_BAUD_115200     (115200 * 1)
+#define AM_HAL_TPIU_BAUD_230400     (115200 * 2)
+#define AM_HAL_TPIU_BAUD_460800     (115200 * 4)
+#define AM_HAL_TPIU_BAUD_500000     (1000000 / 2)
+#define AM_HAL_TPIU_BAUD_1M         (1000000 * 1)
+#define AM_HAL_TPIU_BAUD_2M         (1000000 * 2)
+#define AM_HAL_TPIU_BAUD_DEFAULT    (AM_HAL_TPIU_BAUD_1M)
+
+//*****************************************************************************
+//
+// TPIU register defines.
+//
+//*****************************************************************************
+#define AM_HAL_TPIU_SSPSR       0xE0040000  //! Supported Parallel Port Sizes
+#define AM_HAL_TPIU_CSPSR       0xE0040004  //! Current Parallel Port Size
+#define AM_HAL_TPIU_ACPR        0xE0040010  //! Asynchronous Clock Prescaler
+#define AM_HAL_TPIU_SPPR        0xE00400F0  //! Selected Pin Protocol
+#define AM_HAL_TPIU_TYPE        0xE0040FC8  //! TPIU Type
+
+//*****************************************************************************
+//
+// TPIU ACPR defines.
+//
+//*****************************************************************************
+#define AM_HAL_TPIU_ACPR_SWOSCALER_M    0x0000FFFF  //! SWO baud rate prescalar
+
+//*****************************************************************************
+//
+// TPIU_SPPR TXMODE defines.
+//
+//*****************************************************************************
+#define AM_HAL_TPIU_SPPR_PARALLEL       0x00000000
+#define AM_HAL_TPIU_SPPR_MANCHESTER     0x00000001
+#define AM_HAL_TPIU_SPPR_NRZ            0x00000002
+
+//*****************************************************************************
+//
+// TPIU Type defines
+//
+//*****************************************************************************
+#define AM_HAL_TPIU_TYPE_NRZVALID       0x00000800
+#define AM_HAL_TPIU_TYPE_MANCVALID      0x00000400
+#define AM_HAL_TPIU_TYPE_PTINVALID      0x00000200
+#define AM_HAL_TPIU_TYPE_FIFOSZ_M       0x000001C0
+
+//*****************************************************************************
+//
+// TPIU Clock defines
+//
+//*****************************************************************************
+#define AM_HAL_TPIU_TRACECLKIN_6MHZ     AM_REG_MCUCTRL_TPIUCTRL_TPIUCLKSEL(0)
+#define AM_HAL_TPIU_TRACECLKIN_3MHZ     AM_REG_MCUCTRL_TPIUCTRL_TPIUCLKSEL(1)
+#define AM_HAL_TPIU_TRACECLKIN_1_5MHZ   AM_REG_MCUCTRL_TPIUCTRL_TPIUCLKSEL(2)
+#define AM_HAL_TPIU_TRACECLKIN_750KHZ   AM_REG_MCUCTRL_TPIUCTRL_TPIUCLKSEL(3)
+
+//*****************************************************************************
+//
+//! @brief Structure used for configuring the TPIU
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // If ui32SetItmBaud is non-zero, the ITM frequency is set to the given
+    //  frequency, and is based on a divide-by-8 HFRC TPIU clock.
+    // If zero, other structure members are used to set the TPIU configuration.
+    //
+    uint32_t ui32SetItmBaud;
+
+    //
+    //! MCU Control TRACECLKIN clock freq.
+    //!
+    //! Valid values for ui32TraceClkIn are:
+    //!
+    //!     AM_HAL_TPIU_TRACECLKIN_6MHZ
+    //!     AM_HAL_TPIU_TRACECLKIN_3MHZ
+    //!     AM_HAL_TPIU_TRACECLKIN_1_5MHZ
+    //!     AM_HAL_TPIU_TRACECLKIN_750KHZ
+    //
+    uint32_t ui32TraceClkIn;
+
+    //
+    //! Protocol to use for the TPIU
+    //!
+    //! Valid values for ui32PinProtocol are:
+    //!
+    //!     AM_HAL_TPIU_SPPR_PARALLEL
+    //!     AM_HAL_TPIU_SPPR_MANCHESTER
+    //!     AM_HAL_TPIU_SPPR_NRZ
+    //
+    uint32_t ui32PinProtocol;
+
+    //
+    //! Desired width of the TPIU parallel port
+    //
+    uint32_t ui32ParallelPortSize;
+
+    //
+    //! Desired Clock prescaler value
+    //
+    uint32_t ui32ClockPrescaler;
+}
+am_hal_tpiu_config_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_tpiu_clock_enable(void);
+extern void am_hal_tpiu_clock_disable(void);
+extern void am_hal_tpiu_port_width_set(uint32_t ui32PortWidth);
+extern uint32_t am_hal_tpiu_supported_port_width_get(void);
+extern uint32_t am_hal_tpiu_port_width_get(void);
+extern void am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig);
+extern void am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig);
+extern void am_hal_tpiu_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_TPIU_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c
new file mode 100644
index 0000000000..77bde67b87
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c
@@ -0,0 +1,205 @@
+//*****************************************************************************
+//
+//  am_hal_ttp.c
+//! @file
+//!
+//! @brief Functions for handling the "two time program" interface.
+//!
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#include "am_mcu_apollo.h"
+#include "am_hal_ttp.h"
+
+//*****************************************************************************
+//
+// Local constants
+//
+//*****************************************************************************
+#define TTP_ADDR                0x50020000
+
+//*****************************************************************************
+//
+// Local prototypes
+//
+//*****************************************************************************
+#if !defined(__GNUC__)
+void __breakpoint(int val);
+#endif
+
+//*****************************************************************************
+//
+// A function to verify that the TTP was saved and/or restored properly.
+//
+//*****************************************************************************
+int
+verifyTTPSaved(uint32_t *pSaveArray, int iNumWords)
+{
+    int ix, iErrCnt = 0;
+    uint32_t *pDataSpace = (uint32_t*)TTP_ADDR;
+
+    for (ix = 0; ix<iNumWords; ix++)
+    {
+        if ( *pSaveArray != am_hal_flash_load_ui32((uint32_t)pDataSpace) )
+        {
+            iErrCnt++;
+        }
+        pSaveArray++;
+        pDataSpace++;
+    }
+
+    //
+    // Hopefully returning 0.
+    //
+    return iErrCnt;
+}
+
+//*****************************************************************************
+//
+//! @brief TTP unlock.
+//!
+//! @param ui32Keyval - The key value to unlock the interface.
+//! @param pui8_1024Bytes - A pointer to a 1024 bytes array, used for
+//!                         temporary data storage.
+//!                         WARNING This area must be 32-bit aligned and at
+//!                         least 1024 bytes long.
+//!
+//! This function is used to unlock the TTP ability.
+//!
+//! @return None.
+//
+//*****************************************************************************
+int
+am_hal_ttp_unlock(uint32_t ui32Keyval, uint8_t *pui8_1024Bytes)
+{
+    int iErrCnt = 0;
+    int ix, iRet;
+    int iNumWords = 1024 / 4;
+    uint32_t *pSaveArray, *pDataSpace;
+    int (*pTTPClear)(uint32_t, uint32_t) = (int (*)(uint32_t, uint32_t))0x080002EF;
+    int (*pTTPSet)(uint32_t, uint32_t, uint32_t*, uint32_t, uint32_t) =
+        (int (*)(uint32_t, uint32_t, uint32_t*, uint32_t, uint32_t))0x080006FF;
+
+    //
+    // Save off the data.
+    //
+    pSaveArray = (uint32_t*)pui8_1024Bytes;
+    pDataSpace = (uint32_t*)TTP_ADDR;
+    for (ix = 0; ix < iNumWords; ix++)
+    {
+        *pSaveArray = am_hal_flash_load_ui32((uint32_t)pDataSpace);
+        pSaveArray++;
+        pDataSpace++;
+    }
+
+    //
+    // Before proceeding, make sure that we captured the data correctly.
+    //
+    iErrCnt += verifyTTPSaved((uint32_t*)pui8_1024Bytes, iNumWords);
+    if ( iErrCnt )
+    {
+        return 0x10000001;
+    }
+
+    //
+    // Erase the TTP area.
+    //
+    iRet = (*pTTPClear)(0, ui32Keyval);
+    if ( iRet != 0 )
+    {
+        iErrCnt++;
+        return 0x10000002;
+    }
+
+    //
+    // The point of no return!  The TTP space is successfully erased.
+    // Let's make sure.
+    //
+    pDataSpace = (uint32_t*)TTP_ADDR;
+    for (ix = 0; ix < iNumWords; ix++)
+    {
+        if ( am_hal_flash_load_ui32((uint32_t)pDataSpace) != 0xffffffff )
+        {
+            iErrCnt++;
+        }
+        pDataSpace++;
+    }
+
+    if ( iErrCnt )
+    {
+        return 0x10000003;
+    }
+
+    //
+    // Restore the TTP block from the saved data.
+    //
+    iRet = (*pTTPSet)(ui32Keyval, 0, (uint32_t*)pui8_1024Bytes, 0, iNumWords);
+    if ( iRet != 0 )
+    {
+        iErrCnt++;
+        return 0x10000004;
+    }
+
+    //
+    // Now, check the restored INFO data.
+    //
+    iRet = verifyTTPSaved((uint32_t*)pui8_1024Bytes, iNumWords);
+    if ( iRet )
+    {
+        iErrCnt++;
+        return 0x10000005;
+    }
+    else
+    {
+        //
+        // All good.  The device was successfully recovered.
+        //
+    }
+
+
+    //
+    // Return with error count (hopefully 0).
+    //
+    return iErrCnt;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h
new file mode 100644
index 0000000000..b254c957a7
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h
@@ -0,0 +1,72 @@
+//*****************************************************************************
+//
+//  am_hal_ttp.h
+//! @file
+//!
+//! @brief Functions for handling the "two time program" interface.
+//!
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_TTP_H
+#define AM_HAL_TTP_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Function prototypes
+//
+//*****************************************************************************
+extern int am_hal_ttp_unlock(uint32_t ui32Keyval, uint8_t *pui8_1024Bytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_TTP_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c
new file mode 100644
index 0000000000..1a7e5aca31
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c
@@ -0,0 +1,1160 @@
+//*****************************************************************************
+//
+//  am_hal_uart.c
+//! @file
+//!
+//! @brief Functions for interfacing with the UART.
+//!
+//! @addtogroup uart2 UART
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Transmit and receive queue pointers for each UART module.
+//
+//*****************************************************************************
+am_hal_queue_t g_psTxQueue[AM_REG_UART_NUM_MODULES];
+am_hal_queue_t g_psRxQueue[AM_REG_UART_NUM_MODULES];
+
+//*****************************************************************************
+//
+// Power tracking structure
+//
+//*****************************************************************************
+am_hal_uart_pwrsave_t am_hal_uart_pwrsave[AM_REG_UART_NUM_MODULES];
+
+//*****************************************************************************
+//
+// Set Baud Rate based on the UART clock frequency.
+//
+//*****************************************************************************
+
+#define BAUDCLK     (32)
+
+static void
+config_baudrate(uint32_t ui32Module, uint32_t ui32Baudrate, uint32_t ui32UartClkFreq)
+{
+    uint64_t ui64FractionDivisorLong;
+    uint64_t ui64IntermediateLong;
+    uint32_t ui32IntegerDivisor;
+    uint32_t ui32FractionDivisor;
+    uint32_t ui32BaudClk;
+
+    //
+    // Calculate register values.
+    //
+    ui32BaudClk = BAUDCLK * ui32Baudrate;
+    ui32IntegerDivisor = (uint32_t)(ui32UartClkFreq / ui32BaudClk);
+    ui64IntermediateLong = (ui32UartClkFreq * 64) / ui32BaudClk;
+    ui64FractionDivisorLong = ui64IntermediateLong - (ui32IntegerDivisor * 64);
+    ui32FractionDivisor = (uint32_t)ui64FractionDivisorLong;
+
+    //
+    // Check the result.
+    //
+    am_hal_debug_assert_msg(ui32IntegerDivisor > 0, "Integer divisor MUST be greater than or equal to 1.");
+
+    //
+    // Write the UART regs.
+    //
+    AM_REGn(UART, ui32Module, IBRD) = ui32IntegerDivisor;
+    AM_REGn(UART, ui32Module, IBRD) = ui32IntegerDivisor;
+    AM_REGn(UART, ui32Module, FBRD) = ui32FractionDivisor;
+}
+
+//*****************************************************************************
+//
+//! @brief Set up the UART.
+//!
+//! @param psConfig pointer to a structure that holds the settings for the UART.
+//! @param ui32UartclkFreq is clock frequency that the UART is running at.
+//!
+//! This function should be used to perform the initial set-up of the UART.
+//!
+//! @return none.
+//
+//*****************************************************************************
+void
+am_hal_uart_config(uint32_t ui32Module, am_hal_uart_config_t *psConfig)
+
+{
+    uint32_t ui32ConfigVal = 0;
+
+    //
+    // Configure the Baudrate.
+    //
+    config_baudrate(ui32Module, psConfig->ui32BaudRate, am_hal_clkgen_sysclk_get());
+
+    //
+    // OR in the Data bits.
+    //
+    ui32ConfigVal |= psConfig->ui32DataBits;
+
+    //
+    // OR in the Two Stop bit if used.
+    //
+    ui32ConfigVal |= psConfig->bTwoStopBits ? AM_REG_UART_LCRH_STP2_M : 0;
+
+    //
+    // OR in the Parity.
+    //
+    ui32ConfigVal |= psConfig->ui32Parity;
+
+    //
+    // Write config to Line control register.
+    //
+    AM_REGn(UART, ui32Module, LCRH) |= ui32ConfigVal;
+
+    //
+    // Write the flow control settings to the control register.
+    //
+    AM_REGn(UART, ui32Module, CR) |= psConfig->ui32FlowCtrl;
+
+    //
+    // Set the clock select field for 24MHz from the HFRC
+    //
+    AM_REGn(UART, ui32Module, CR) |= AM_REG_UART_CR_CLKSEL_24MHZ;
+}
+
+//*****************************************************************************
+//
+//! @brief Gets the status.
+//!
+//! This function returns the current status.
+//!
+//! @return current status.
+//
+//*****************************************************************************
+uint32_t
+am_hal_uart_status_get(uint32_t ui32Module)
+{
+    //
+    // Read and return the Status.
+    //
+    return AM_REGn(UART, ui32Module, RSR);
+}
+
+//*****************************************************************************
+//
+//! @brief Gets the interrupt status.
+//!
+//! @param bEnabledOnly - If true returns the enabled interrupt status.
+//!
+//! This function returns the masked or raw interrupt status.
+//!
+//! @return Bitwise representation of the current interrupt status.
+//!
+//! The return value will be the logical OR of one or more of the following
+//! values:
+//!
+//!     AM_HAL_UART_INT_OVER_RUN
+//!     AM_HAL_UART_INT_BREAK_ERR
+//!     AM_HAL_UART_INT_PARITY_ERR
+//!     AM_HAL_UART_INT_FRAME_ERR
+//!     AM_HAL_UART_INT_RX_TMOUT
+//!     AM_HAL_UART_INT_TX
+//!     AM_REG_UART_IER_TXIM_M
+//!     AM_HAL_UART_INT_RX
+//!     AM_HAL_UART_INT_DSRM
+//!     AM_HAL_UART_INT_DCDM
+//!     AM_HAL_UART_INT_CTSM
+//!     AM_HAL_UART_INT_RIM
+//
+//*****************************************************************************
+uint32_t
+am_hal_uart_int_status_get(uint32_t ui32Module, bool bEnabledOnly)
+{
+    if (bEnabledOnly)
+    {
+        //
+        // Read and return the Masked Interrupt Status.
+        //
+        return AM_REGn(UART, ui32Module, MIS);
+    }
+    else
+    {
+        //
+        // Read and return the Raw Interrupt Status.
+        //
+        return AM_REGn(UART, ui32Module, IES);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Clears the desired interrupts.
+//!
+//! @param ui32Interrupt - Interrupt bits to clear.
+//!
+//! This function clears the desired interrupts.
+//!
+//! ui32Interrupt should be a logical or of the following:
+//!
+//!     AM_HAL_UART_INT_OVER_RUN
+//!     AM_HAL_UART_INT_BREAK_ERR
+//!     AM_HAL_UART_INT_PARITY_ERR
+//!     AM_HAL_UART_INT_FRAME_ERR
+//!     AM_HAL_UART_INT_RX_TMOUT
+//!     AM_HAL_UART_INT_TX
+//!     AM_REG_UART_IER_TXIM_M
+//!     AM_HAL_UART_INT_RX
+//!     AM_HAL_UART_INT_DSRM
+//!     AM_HAL_UART_INT_DCDM
+//!     AM_HAL_UART_INT_CTSM
+//!     AM_HAL_UART_INT_RIM
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_int_clear(uint32_t ui32Module, uint32_t ui32Interrupt)
+{
+    //
+    // Clear the bits.
+    //
+    AM_REGn(UART, ui32Module, IEC) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the desired interrupts.
+//!
+//! @param ui32Interrupt - Interrupt bits to disable.
+//!
+//! This function disables the desired interrupts.
+//!
+//! ui32Interrupt should be a logical or of the following:
+//!
+//!     AM_HAL_UART_INT_OVER_RUN
+//!     AM_HAL_UART_INT_BREAK_ERR
+//!     AM_HAL_UART_INT_PARITY_ERR
+//!     AM_HAL_UART_INT_FRAME_ERR
+//!     AM_HAL_UART_INT_RX_TMOUT
+//!     AM_HAL_UART_INT_TX
+//!     AM_REG_UART_IER_TXIM_M
+//!     AM_HAL_UART_INT_RX
+//!     AM_HAL_UART_INT_DSRM
+//!     AM_HAL_UART_INT_DCDM
+//!     AM_HAL_UART_INT_CTSM
+//!     AM_HAL_UART_INT_RIM
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_int_disable(uint32_t ui32Module, uint32_t ui32Interrupt)
+{
+    //
+    // Disable the bits.
+    //
+    AM_REGn(UART, ui32Module, IER) &= ~ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the desired interrupts.
+//!
+//! @param ui32Interrupt - Interrupt bits to enable.
+//!
+//! This function enables the desired interrupts.
+//!
+//! ui32Interrupt should be a logical or of the following:
+//!
+//!     AM_HAL_UART_INT_OVER_RUN
+//!     AM_HAL_UART_INT_BREAK_ERR
+//!     AM_HAL_UART_INT_PARITY_ERR
+//!     AM_HAL_UART_INT_FRAME_ERR
+//!     AM_HAL_UART_INT_RX_TMOUT
+//!     AM_HAL_UART_INT_TX
+//!     AM_REG_UART_IER_TXIM_M
+//!     AM_HAL_UART_INT_RX
+//!     AM_HAL_UART_INT_DSRM
+//!     AM_HAL_UART_INT_DCDM
+//!     AM_HAL_UART_INT_CTSM
+//!     AM_HAL_UART_INT_RIM
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_int_enable(uint32_t ui32Module, uint32_t ui32Interrupt)
+{
+    //
+    // Enable the interrupts.
+    //
+    AM_REGn(UART, ui32Module, IER) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Returns the enabled interrupts.
+//!
+//! This function return the enabled interrupts.
+//!
+//! @return the enabled interrupts. This will be a logical or of the following:
+//!
+//!     AM_HAL_UART_INT_OVER_RUN
+//!     AM_HAL_UART_INT_BREAK_ERR
+//!     AM_HAL_UART_INT_PARITY_ERR
+//!     AM_HAL_UART_INT_FRAME_ERR
+//!     AM_HAL_UART_INT_RX_TMOUT
+//!     AM_HAL_UART_INT_TX
+//!     AM_REG_UART_IER_TXIM_M
+//!     AM_HAL_UART_INT_RX
+//!     AM_HAL_UART_INT_DSRM
+//!     AM_HAL_UART_INT_DCDM
+//!     AM_HAL_UART_INT_CTSM
+//!     AM_HAL_UART_INT_RIM
+//!
+//! @return Returns the enabled interrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_uart_int_enable_get(uint32_t ui32Module)
+{
+    //
+    // Return the enabled interrupts.
+    //
+    return AM_REGn(UART, ui32Module, IER);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the UART, RX, and TX.
+//!
+//! This function enables the UART, RX, and TX.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_enable(uint32_t ui32Module)
+{
+    //
+    // Enable the UART, RX, and TX.
+    //
+    AM_REGan_SET(UART, ui32Module, CR, (AM_REG_UART_CR_UARTEN_M   |
+                                        AM_REG_UART_CR_RXE_M      |
+                                        AM_REG_UART_CR_TXE_M) );
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the UART, RX, and TX.
+//!
+//! This function disables the UART, RX, and TX.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_disable(uint32_t ui32Module)
+{
+    //
+    // Disable the UART.
+    //
+    AM_REGan_CLR(UART, ui32Module, CR, (AM_REG_UART_CR_UARTEN_M   |
+                                        AM_REG_UART_CR_RXE_M      |
+                                        AM_REG_UART_CR_TXE_M) );
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the UART in the power control block.
+//!
+//! This function enables the UART device in the power control block.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_pwrctrl_enable(uint32_t ui32Module)
+{
+    //
+    // Check to make sure we're acting on a real UART module.
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_UART_NUM_MODULES,
+                            "Trying to disable a UART module that doesn't exist");
+
+    am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_UART0 << ui32Module);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the UART in the power control block.
+//!
+//! This function disables the UART device in the power control block.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_pwrctrl_disable(uint32_t ui32Module)
+{
+    //
+    // Check to make sure we're acting on a real UART module.
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_UART_NUM_MODULES,
+                            "Trying to disable a UART module that doesn't exist");
+
+    am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_UART0 << ui32Module);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the UART in the power control block.
+//!
+//! This function enables the UART device in the power control block.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_power_on_restore(uint32_t ui32Module)
+{
+    //
+    // Check to make sure we're acting on a real UART module.
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_UART_NUM_MODULES,
+                            "Trying to enable a UART module that doesn't exist");
+
+    //
+    // Make sure this restore is a companion to a previous save call.
+    //
+    if ( am_hal_uart_pwrsave[ui32Module].bValid == 0 )
+    {
+        return;
+    }
+
+    //
+    // Enable power to the selected UART
+    //
+    am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_UART0 << ui32Module);
+
+    //
+    // Restore the clock settings
+    //
+    am_hal_clkgen_uarten_set(ui32Module, am_hal_uart_pwrsave[ui32Module].UARTEN);
+
+    //
+    // Restore the configuration registers from the global variable in SRAM.
+    //
+    AM_REGn(UART, ui32Module, ILPR) = am_hal_uart_pwrsave[ui32Module].ILPR;
+    AM_REGn(UART, ui32Module, IBRD) = am_hal_uart_pwrsave[ui32Module].IBRD;
+    AM_REGn(UART, ui32Module, FBRD) = am_hal_uart_pwrsave[ui32Module].FBRD;
+    AM_REGn(UART, ui32Module, LCRH) = am_hal_uart_pwrsave[ui32Module].LCRH;
+    AM_REGn(UART, ui32Module, CR)   = am_hal_uart_pwrsave[ui32Module].CR;
+    AM_REGn(UART, ui32Module, IFLS) = am_hal_uart_pwrsave[ui32Module].IFLS;
+    AM_REGn(UART, ui32Module, IER)  = am_hal_uart_pwrsave[ui32Module].IER;
+
+    //
+    // Indicates we have restored the configuration.
+    //
+    am_hal_uart_pwrsave[ui32Module].bValid = 0;
+
+    return;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the UART in the power control block.
+//!
+//! This function disables the UART device in the power control block.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_power_off_save(uint32_t ui32Module)
+{
+    //
+    // Check to make sure we're acting on a real UART module.
+    //
+    am_hal_debug_assert_msg(ui32Module < AM_REG_UART_NUM_MODULES,
+                            "Trying to disable a UART module that doesn't exist");
+
+    //
+    // Save all of the configuration register information for the selected
+    // UART.
+    //
+    am_hal_uart_pwrsave[ui32Module].ILPR = AM_REGn(UART, ui32Module, ILPR);
+    am_hal_uart_pwrsave[ui32Module].IBRD = AM_REGn(UART, ui32Module, IBRD);
+    am_hal_uart_pwrsave[ui32Module].FBRD = AM_REGn(UART, ui32Module, FBRD);
+    am_hal_uart_pwrsave[ui32Module].LCRH = AM_REGn(UART, ui32Module, LCRH);
+    am_hal_uart_pwrsave[ui32Module].CR = AM_REGn(UART, ui32Module, CR);
+    am_hal_uart_pwrsave[ui32Module].IFLS = AM_REGn(UART, ui32Module, IFLS);
+    am_hal_uart_pwrsave[ui32Module].IER = AM_REGn(UART, ui32Module, IER);
+
+    //
+    // Save the clock setting and disable power to the selected UART.
+    // Save the current enable value.
+    //
+    am_hal_uart_pwrsave[ui32Module].UARTEN =
+        (AM_REG(CLKGEN, UARTEN) & AM_HAL_CLKGEN_UARTEN_UARTENn_M(ui32Module)) >>
+         AM_HAL_CLKGEN_UARTEN_UARTENn_S(ui32Module);
+
+    //
+    // Disable the UART.
+    //
+    am_hal_clkgen_uarten_set(ui32Module, AM_HAL_CLKGEN_UARTEN_DIS);
+
+    //
+    // Indicates we have a valid saved configuration.
+    //
+    am_hal_uart_pwrsave[ui32Module].bValid = 1;
+
+    //
+    // Disable power to the selected UART.
+    //
+    am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_UART0 << ui32Module);
+
+    return;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the UART clock.
+//!
+//! This function enables the clock to the UART.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_clock_enable(uint32_t ui32Module)
+{
+    //
+    // Set CLKGEN.UARTEN, clear the field then write the desired enable value
+    // Valid enable values are DIS, EN, REDUCE_FREQ, EN_POWER_SAV.
+    //
+    am_hal_clkgen_uarten_set(ui32Module, AM_HAL_CLKGEN_UARTEN_EN);
+
+    //
+    // Enable the UART clock.
+    //
+    AM_REGn(UART, ui32Module, CR) |= AM_REG_UART_CR_CLKEN_M;
+
+    //
+    // Select default UART clock source
+    //
+    AM_REGn(UART, ui32Module, CR) |= AM_REG_UART_CR_CLKSEL_24MHZ;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the UART clock.
+//!
+//! This function disables the clock to the UART.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_clock_disable(uint32_t ui32Module)
+{
+    //
+    // Disable the UART clock.
+    //
+    AM_REGn(UART, ui32Module, CR) &= ~AM_REG_UART_CR_CLKEN_M;
+
+    //
+    // Disable the UART clock in the CLKGEN module.
+    //
+    am_hal_clkgen_uarten_set(ui32Module, AM_HAL_CLKGEN_UARTEN_DIS);
+}
+
+//*****************************************************************************
+//
+//! @brief Set and enable the desired interrupt levels for the RX/TX fifo.
+//!
+//! @param ui32LvlCfg - Desired FIFO RX/TX levels.
+//!
+//! This function sets the desired interrupt levels for the RX/TX fifo and
+//! enables the use of transmit and receive FIFO buffers.
+//!
+//! Valid values for ui32LvlCfg are:
+//!
+//!     AM_HAL_UART_TX_FIFO_1_8
+//!     AM_HAL_UART_TX_FIFO_1_4
+//!     AM_HAL_UART_TX_FIFO_1_2
+//!     AM_HAL_UART_TX_FIFO_3_4
+//!     AM_HAL_UART_TX_FIFO_7_8
+//!
+//!     AM_HAL_UART_RX_FIFO_1_8
+//!     AM_HAL_UART_RX_FIFO_1_4
+//!     AM_HAL_UART_RX_FIFO_1_2
+//!     AM_HAL_UART_RX_FIFO_3_4
+//!     AM_HAL_UART_RX_FIFO_7_8
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_fifo_config(uint32_t ui32Module, uint32_t ui32LvlCfg)
+{
+    //
+    // Enable the use of FIFOs.
+    //
+    AM_REGn(UART, ui32Module, LCRH) |= AM_REG_UART_LCRH_FEN_M;
+
+    //
+    // Write the FIFO level register.
+    //
+    AM_REGn(UART, ui32Module, IFLS) = ui32LvlCfg;
+}
+
+//*****************************************************************************
+//
+//! @brief Return the UART Flags.
+//!
+//! This function reads and returns the UART flags.
+//!
+//! @return Returns the Flags.
+//
+//*****************************************************************************
+uint32_t
+am_hal_uart_flags_get(uint32_t ui32Module)
+{
+    //
+    // Read and return the Flags.
+    //
+    return AM_REGn(UART, ui32Module, FR);
+}
+
+//*****************************************************************************
+//
+//! @brief Outputs a single character using polling.
+//!
+//! @param cChar - Character to send.
+//!
+//! This function outputs a single character using polling.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_char_transmit_polled(uint32_t ui32Module, char cChar)
+{
+    //
+    // Wait for space, i.e.  TX FIFO EMPTY
+    //
+    while (AM_BFRn(UART, ui32Module, FR, TXFF));
+
+    //
+    // Write the char.
+    //
+    AM_REGn(UART, ui32Module, DR) = cChar;
+}
+
+//*****************************************************************************
+//
+//! @brief Outputs a zero terminated string using polling.
+//!
+//! @param pcString - Pointer to character string to send.
+//!
+//! This function outputs a zero terminated string using polling.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_string_transmit_polled(uint32_t ui32Module, char *pcString)
+{
+    while (*pcString)
+    {
+        //
+        // Wait for space, i.e.  TX FIFO EMPTY.
+        //
+        while (AM_BFRn(UART, ui32Module, FR, TXFF));
+
+        //
+        // Write the char.
+        //
+        AM_REGn(UART, ui32Module, DR) = *pcString++;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Receives a character using polling.
+//!
+//! @param pcChar - Pointer to character to store received char.
+//!
+//! This function receives a character using polling.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_char_receive_polled(uint32_t ui32Module, char *pcChar)
+{
+    //
+    // Wait for data, i.e. RX FIFO NOT EMPTY.
+    //
+    while (AM_BFRn(UART, ui32Module, FR, RXFE));
+
+    //
+    // Save the char.
+    //
+    *pcChar = AM_REGn(UART, ui32Module, DR);
+}
+
+//*****************************************************************************
+//
+//! @brief Receives one line using polling.
+//!
+//! @param ui32MaxChars - Maximum number of characters to receive.
+//! @param pcChar - Pointer to character string to store received line.
+//!
+//! This function receives a line (delimited by '/n' or '/r') using polling.
+//! Line buffer is 0 (NULL) terminated.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_line_receive_polled(uint32_t ui32Module,
+                                uint32_t ui32MaxChars,
+                                char *pcChar)
+{
+    char cRecChar;
+    uint32_t i;
+
+    //
+    // Loop until we receive ui32MaxChars or receive a line ending.
+    //
+    for (i = 0; i < (ui32MaxChars - 1); i++)
+    {
+        //
+        // Get char.
+        //
+        am_hal_uart_char_receive_polled(ui32Module, &cRecChar);
+
+        if ((cRecChar == '\n') || (cRecChar == '\r'))
+        {
+            //
+            // Zero terminate the buffer.
+            //
+            *pcChar = 0;
+
+            return;
+        }
+
+        *pcChar++ = cRecChar;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Initialize the buffered UART.
+//!
+//! @param pui8RxArray - Pointer to the RX buffer to fill.
+//! @param ui32RxSize - size of RX buffer.
+//! @param pui8TxArray - Pointer to the TX buffer to fill.
+//! @param ui32TxSize - size of TX buffer.
+//!
+//! This function initializes the buffered UART.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_init_buffered(uint32_t ui32Module,
+                          uint8_t *pui8RxArray, uint32_t ui32RxSize,
+                          uint8_t *pui8TxArray, uint32_t ui32TxSize)
+{
+    //
+    // Enable the UART RX timeout interrupt.
+    //
+    AM_REGn(UART, ui32Module, IER) |= (AM_REG_UART_IES_RTRIS_M |
+                                       AM_REG_UART_IES_TXRIS_M);
+
+    //
+    // Initialize the ring buffers.
+    //
+    am_hal_queue_init(&g_psTxQueue[ui32Module], pui8TxArray, 1, ui32TxSize);
+    am_hal_queue_init(&g_psRxQueue[ui32Module], pui8RxArray, 1, ui32RxSize);
+}
+
+//*****************************************************************************
+//
+//! @brief Get the status of the buffered UART.
+//!
+//! @param pui32RxSize - Pointer to variable to return the Rx ring data size.
+//! @param pui32TxSize - Pointer to variable to return the Tx ring data size.
+//!
+//! This function gets the status of the buffered UART.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_get_status_buffered(uint32_t ui32Module,
+                                uint32_t *pui32RxSize,
+                                uint32_t *pui32TxSize)
+{
+    //
+    // Return the current size of ring buffers.
+    //
+    if ( pui32RxSize )
+    {
+        *pui32RxSize = am_hal_queue_data_left(&g_psRxQueue[ui32Module]);
+    }
+
+    if ( pui32TxSize )
+    {
+        *pui32TxSize = am_hal_queue_data_left(&g_psTxQueue[ui32Module]);
+    }
+}
+
+
+//*****************************************************************************
+//
+//! @brief Services the buffered UART.
+//!
+//! @param ui32Status is the contents of the UART interrupt status register.
+//!
+//! This function is responsible for servicing the buffered UART. Designed to
+//! be called from the UART interrupt handler.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_uart_service_buffered(uint32_t ui32Module, uint32_t ui32Status)
+{
+    uint8_t ui8Character = '\x00';
+    uint32_t ui32FifoEntry = 0;
+
+    //
+    // Check to see if we have filled the Rx FIFO past the configured limit, or
+    // if we have an 'old' character or two sitting in the FIFO.
+    //
+    if (ui32Status & (AM_REG_UART_IES_RXRIS_M | AM_REG_UART_IES_RTRIS_M))
+    {
+        //
+        // While there's stuff in the RX fifo....
+        //
+        while (!AM_BFRn(UART, ui32Module, FR, RXFE))
+        {
+            //
+            // Read each character out one by one, and add it to the ring
+            // buffer. This will start losing bytes if the fifo ever overflows.
+            //
+            ui32FifoEntry = AM_REGn(UART, ui32Module , DR);
+
+            //
+            // As long as no error bits were set, we should push this byte to
+            // the FIFO.
+            //
+            if ( (ui32FifoEntry & 0xF00) == 0 )
+            {
+                ui8Character = ui32FifoEntry & 0xFF;
+                am_hal_queue_item_add(&g_psRxQueue[ui32Module], &ui8Character, 1);
+            }
+        }
+    }
+
+    //
+    // Check to see if our TX buffer has been recently emptied. If so, we
+    // should refill it from the TX ring buffer.
+    //
+    if (ui32Status & AM_REG_UART_IES_TXRIS_M)
+    {
+        //
+        // Keep refilling until the fifo is full, or the ring buffer is empty,
+        // whichever happens first.
+        //
+        while (am_hal_queue_data_left(&g_psTxQueue[ui32Module]) &&
+               !AM_BFRn(UART, ui32Module, FR, TXFF))
+        {
+            am_hal_queue_item_get(&g_psTxQueue[ui32Module], &ui8Character, 1);
+            AM_REGn(UART, ui32Module , DR) = ui8Character;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Services the buffered UART.
+//!
+//! @param ui32Status is the contents of the UART interrupt status register.
+//!
+//! This function is responsible for servicing the buffered UART. Designed to
+//! be called from the UART interrupt handler.
+//!
+//! This function behaves exactly like am_hal_uart_service_buffered() \e except
+//! it does not completely empty the RX FIFO on every interrupt event. Instead,
+//! it will leave at least one byte behind until it receives a UART RX TIMEOUT
+//! interrupt. If you use this service routine, you can treat the RX TIMEOUT
+//! interrupt as a UART IDLE interrupt. Every time the UART RX line goes IDLE
+//! for 32 consecutive bit-times you WILL receive a UART RX TIMEOUT interrupt.
+//! This behavior is not guaranteed for am_hal_uart_service_buffered().
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_uart_service_buffered_timeout_save(uint32_t ui32Module, uint32_t ui32Status)
+{
+    uint8_t ui8Character = '\x00';
+    uint32_t ui32Count = 0;
+    uint32_t ui32FifoEntry = 0;
+
+    //
+    // Check to see if we have filled the Rx FIFO past the configured limit, or
+    // if we have an 'old' character or two sitting in the FIFO.
+    //
+    if (ui32Status & (AM_REG_UART_IES_RXRIS_M | AM_REG_UART_IES_RTRIS_M))
+    {
+        //
+        // Check to see what our FIFO configuration setting is.
+        //
+        uint32_t ui32FifoThreshold;
+        uint32_t ui32FifoCfg = AM_BFMn(UART, ui32Module, IFLS, RXIFLSEL);
+
+        //
+        // Compute the number of bytes for receive interrupt from the FIFO level
+        // register.
+        //
+        switch(ui32FifoCfg)
+        {
+            case AM_HAL_UART_RX_FIFO_1_8: ui32FifoThreshold = 4; break;
+            case AM_HAL_UART_RX_FIFO_1_4: ui32FifoThreshold = 8; break;
+            case AM_HAL_UART_RX_FIFO_1_2: ui32FifoThreshold = 16; break;
+            case AM_HAL_UART_RX_FIFO_3_4: ui32FifoThreshold = 24; break;
+            case AM_HAL_UART_RX_FIFO_7_8: ui32FifoThreshold = 28; break;
+            default:
+                ui32FifoThreshold = 32;
+        }
+
+        //
+        // While there's stuff in the RX fifo....
+        //
+        while (!AM_BFRn(UART, ui32Module, FR, RXFE))
+        {
+            //
+            // Read each character out one by one, and add it to the ring
+            // buffer. This will start losing bytes if the fifo ever overflows.
+            //
+            ui32FifoEntry = AM_REGn(UART, ui32Module, DR);
+
+            //
+            // As long as no error bits were set, we should push this byte to
+            // the FIFO.
+            //
+            if ( (ui32FifoEntry & 0xF00) == 0)
+            {
+                ui8Character = ui32FifoEntry & 0xFF;
+                am_hal_queue_item_add(&g_psRxQueue[ui32Module], &ui8Character, 1);
+            }
+
+            //
+            // Leave one byte to trigger the RX timeout interrupt.
+            //
+            if ( ++ui32Count >= (ui32FifoThreshold - 1) )
+            {
+                break;
+            }
+        }
+    }
+
+    //
+    // Check to see if our TX buffer has been recently emptied. If so, we
+    // should refill it from the TX ring buffer.
+    //
+    if (ui32Status & AM_REG_UART_IES_TXRIS_M)
+    {
+        //
+        // Keep refilling until the fifo is full, or the ring buffer is empty,
+        // whichever happens first.
+        //
+        while (am_hal_queue_data_left(&g_psTxQueue[ui32Module]) &&
+               !AM_BFRn(UART, ui32Module, FR, TXFF))
+        {
+            am_hal_queue_item_get(&g_psTxQueue[ui32Module], &ui8Character, 1);
+            AM_REGn(UART, ui32Module , DR) = ui8Character;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Puts a char in the buffer or directly to the fifo if available.
+//!
+//! @param cChar - Character to send.
+//!
+//! This function puts a character in the buffer or directly to the fifo.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_char_transmit_buffered(uint32_t ui32Module, char cChar)
+{
+    //
+    // Check the status of the Tx fifo and the Tx ring buffer.
+    //
+    if (am_hal_queue_empty(&g_psTxQueue[ui32Module]) &&
+        !AM_BFRn(UART, ui32Module, FR, TXFF))
+    {
+        //
+        // If the fifo isn't full yet, and the ring buffer isn't being used,
+        // just write the new character directly to the fifo.
+        //
+        AM_REGn(UART, ui32Module, DR) = cChar;
+    }
+    else
+    {
+        //
+        // If we get here, either the fifo is full, or the ring buffer is
+        // already in use. In either case, we need to use the ring buffer
+        // to make sure that the transmitted data gets sent in the right
+        // order. If the buffer is already full, we will simply lose this
+        // byte.
+        //
+        am_hal_queue_item_add(&g_psTxQueue[ui32Module], &cChar, 1);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Puts a null terminaled string in the buffer or directly to the fifo.
+//!
+//! @param pcString - Pointer to buffer used for sending.
+//!
+//! This function puts a string in the buffer or directly to the fifo if there
+//! is space available.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_uart_string_transmit_buffered(uint32_t ui32Module, char *pcString)
+{
+    //
+    // Check the status of the Tx fifo and the Tx ring buffer.
+    //
+    while (*pcString)
+    {
+        if (am_hal_queue_empty(&g_psTxQueue[ui32Module]) &&
+            !AM_BFRn(UART, ui32Module, FR, TXFF))
+        {
+            //
+            // If the fifo isn't full yet, and the ring buffer isn't being used,
+            // just write the new character directly to the fifo.
+            //
+            AM_REGn(UART, ui32Module, DR) = *pcString;
+        }
+        else
+        {
+            //
+            // If we get here, either the fifo is full, or the ring buffer is
+            // already in use. In either case, we need to use the ring buffer
+            // to make sure that the transmitted data gets sent in the right
+            // order. If the buffer is already full, we will simply lose this
+            // byte.
+            //
+            am_hal_queue_item_add(&g_psTxQueue[ui32Module], pcString, 1);
+        }
+
+        //
+        // Move the pointer to the next character.
+        //
+        pcString++;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Returns n number of characters from the ring buffer or until empty.
+//!
+//! @param pcString - Pointer to buffer for putting received characters.
+//! @param ui32MaxChars - Maximum number of characters to receive.
+//!
+//! This function puts a char string in the buffer.
+//!
+//! @return Returns the number of chars received.
+//
+//*****************************************************************************
+uint32_t
+am_hal_uart_char_receive_buffered(uint32_t ui32Module,
+                                  char *pcString,
+                                  uint32_t ui32MaxChars)
+{
+    uint32_t ui32NumChars = 0;
+
+    //
+    // Loop until ui32MaxChars or until empty.
+    //
+    while (am_hal_queue_data_left(&g_psRxQueue[ui32Module]) && ui32MaxChars)
+    {
+        //
+        // Pull a char out of the ring buffer.
+        //
+        am_hal_queue_item_get(&g_psRxQueue[ui32Module], pcString, 1);
+
+        //
+        // Subtract from ui32MaxChars.
+        // Add to ui32NumChars.
+        // Move pointer in buffer.
+        //
+        ui32MaxChars--;
+        ui32NumChars++;
+        pcString++;
+    }
+
+    //
+    // return the number of chars received.
+    //
+    return ui32NumChars;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h
new file mode 100644
index 0000000000..4aab828582
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h
@@ -0,0 +1,345 @@
+//*****************************************************************************
+//
+//  am_hal_uart.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the UART.
+//!
+//! @addtogroup uart2 UART
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_UART_H
+#define AM_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name UART Interrupts
+//! @brief Macro definitions for UART FIFO levels.
+//!
+//! They may be used with the \e am_hal_uart_fifo_config() function.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_UART_INT_OVER_RUN            AM_REG_UART_IER_OEIM_M
+#define AM_HAL_UART_INT_BREAK_ERR           AM_REG_UART_IER_BEIM_M
+#define AM_HAL_UART_INT_PARITY_ERR          AM_REG_UART_IER_PEIM_M
+#define AM_HAL_UART_INT_FRAME_ERR           AM_REG_UART_IER_FEIM_M
+#define AM_HAL_UART_INT_RX_TMOUT            AM_REG_UART_IER_RTIM_M
+#define AM_HAL_UART_INT_TX                  AM_REG_UART_IER_TXIM_M
+#define AM_HAL_UART_INT_RX                  AM_REG_UART_IER_RXIM_M
+#define AM_HAL_UART_INT_DSRM                AM_REG_UART_IER_DSRMIM_M
+#define AM_HAL_UART_INT_DCDM                AM_REG_UART_IER_DCDMIM_M
+#define AM_HAL_UART_INT_CTSM                AM_REG_UART_IER_CTSMIM_M
+#define AM_HAL_UART_INT_TXCMP               AM_REG_UART_IER_TXCMPMIM_M
+//! @}
+
+//*****************************************************************************
+//
+//! @name UART FIFO Levels
+//! @brief Macro definitions for RTV interrupt status bits.
+//!
+//! These macros correspond to the bits in the UART interrupt status register.
+//! They may be used with any of the \e am_hal_uart_int_x() functions.
+//!
+//! @{
+//
+//*****************************************************************************
+//TX
+#define AM_HAL_UART_TX_FIFO_1_8             AM_REG_UART_IFLS_TXIFLSEL(0)
+#define AM_HAL_UART_TX_FIFO_1_4             AM_REG_UART_IFLS_TXIFLSEL(1)
+#define AM_HAL_UART_TX_FIFO_1_2             AM_REG_UART_IFLS_TXIFLSEL(2)
+#define AM_HAL_UART_TX_FIFO_3_4             AM_REG_UART_IFLS_TXIFLSEL(3)
+#define AM_HAL_UART_TX_FIFO_7_8             AM_REG_UART_IFLS_TXIFLSEL(4)
+// RX
+#define AM_HAL_UART_RX_FIFO_1_8             AM_REG_UART_IFLS_RXIFLSEL(0)
+#define AM_HAL_UART_RX_FIFO_1_4             AM_REG_UART_IFLS_RXIFLSEL(1)
+#define AM_HAL_UART_RX_FIFO_1_2             AM_REG_UART_IFLS_RXIFLSEL(2)
+#define AM_HAL_UART_RX_FIFO_3_4             AM_REG_UART_IFLS_RXIFLSEL(3)
+#define AM_HAL_UART_RX_FIFO_7_8             AM_REG_UART_IFLS_RXIFLSEL(4)
+//! @}
+
+//*****************************************************************************
+//
+//! @name UART Status Register
+//! @brief Macro definitions for UART Status Register Bits.
+//!
+//! They may be used with the \e am_hal_uart_status_get() function.
+//!
+//! @{
+//
+//*****************************************************************************
+// This is the overrun error indicator.
+#define AM_HAL_UART_RSR_OVERRUN_NOERR       AM_REG_UART_RSR_OESTAT_NOERR
+#define AM_HAL_UART_RSR_OVERRUN_ERROR       AM_REG_UART_RSR_OESTAT_ERR
+
+// This is the break error indicator.
+#define AM_HAL_UART_RSR_BREAK_NOERR         AM_REG_UART_RSR_BESTAT_NOERR
+#define AM_HAL_UART_RSR_BREAK_ERROR         AM_REG_UART_RSR_BESTAT_ERR
+
+// This is the parity error indicator.
+#define AM_HAL_UART_RSR_PARITY_NOERR        AM_REG_UART_RSR_PESTAT_NOERR
+#define AM_HAL_UART_RSR_PARITY_ERROR        AM_REG_UART_RSR_PESTAT_ERR
+
+// This is the framing error indicator.
+#define AM_HAL_UART_RSR_FRAME_ERROR_NOERR   AM_REG_UART_RSR_FESTAT_NOERR
+#define AM_HAL_UART_RSR_FRAME_ERROR_ERROR   AM_REG_UART_RSR_FESTAT_ERR
+//! @}
+
+//*****************************************************************************
+//
+//! @name UART Flag Register
+//! @brief Macro definitions for UART Flag Register Bits.
+//!
+//! They may be used with the \e am_hal_uart_flags_get() function.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_UART_FR_RING                 AM_REG_UART_FR_RI_M
+#define AM_HAL_UART_FR_TX_EMPTY             AM_REG_UART_FR_TXFE_XMTFIFO_EMPTY
+#define AM_HAL_UART_FR_RX_FULL              AM_REG_UART_FR_RXFF_RCVFIFO_FULL
+#define AM_HAL_UART_FR_TX_FULL              AM_REG_UART_FR_TXFF_XMTFIFO_FULL
+#define AM_HAL_UART_FR_RX_EMPTY             AM_REG_UART_FR_RXFE_RCVFIFO_EMPTY
+#define AM_HAL_UART_FR_BUSY                 AM_REG_UART_FR_BUSY_BUSY
+#define AM_HAL_UART_FR_DCD_DETECTED         AM_REG_UART_FR_DCD_DETECTED
+#define AM_HAL_UART_FR_DSR_READY            AM_REG_UART_FR_DSR_READY
+#define AM_HAL_UART_FR_CTS                  AM_REG_UART_FR_CTS_M
+//! @}
+
+
+//*****************************************************************************
+//
+//! @name UART Config Macros
+//! @brief Macro definitions for available Data bits.
+//!
+//! They may be used with the \e am_hal_uart_config_t structure used by \e
+//! am_hal_uart_config().
+//!
+//! @{
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Data bits defines.
+//
+//*****************************************************************************
+#define AM_HAL_UART_DATA_BITS_8             AM_REG_UART_LCRH_WLEN(3)
+#define AM_HAL_UART_DATA_BITS_7             AM_REG_UART_LCRH_WLEN(2)
+#define AM_HAL_UART_DATA_BITS_6             AM_REG_UART_LCRH_WLEN(1)
+#define AM_HAL_UART_DATA_BITS_5             0
+
+//*****************************************************************************
+//
+// Parity defines.
+//
+//*****************************************************************************
+#define AM_HAL_UART_PARITY_NONE             0
+#define AM_HAL_UART_PARITY_ODD              AM_REG_UART_LCRH_PEN_M
+#define AM_HAL_UART_PARITY_EVEN             AM_REG_UART_LCRH_PEN_M |       \
+                                            AM_REG_UART_LCRH_EPS_M
+
+//*****************************************************************************
+//
+// Flow control defines.
+//
+//*****************************************************************************
+#define AM_HAL_UART_FLOW_CTRL_NONE          0
+#define AM_HAL_UART_FLOW_CTRL_RTS_CTS       AM_REG_UART_CR_CTSEN_M |       \
+                                            AM_REG_UART_CR_RTSEN_M
+//! @}
+
+//*****************************************************************************
+//
+//! UART configuration structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Desired Baudrate for the UART.
+    //
+    uint32_t ui32BaudRate;
+
+    //
+    //! Number of data bits.
+    //!
+    //! Valid values for ui32DataBits are:
+    //!
+    //!     AM_HAL_UART_DATA_BITS_8
+    //!     AM_HAL_UART_DATA_BITS_7
+    //!     AM_HAL_UART_DATA_BITS_6
+    //!     AM_HAL_UART_DATA_BITS_5
+    //
+    uint32_t ui32DataBits;
+
+    //
+    //! Use two stop bits.
+    //
+    bool bTwoStopBits;
+
+    //
+    //! Parity.
+    //!
+    //! Valid values for ui32Parity are:
+    //!
+    //!     AM_HAL_UART_PARITY_NONE
+    //!     AM_HAL_UART_PARITY_ODD
+    //!     AM_HAL_UART_PARITY_EVEN
+    //
+    uint32_t ui32Parity;
+
+    //
+    //! Flow control.
+    //!
+    //! Valid values for ui32FlowCtrl are:
+    //!
+    //!     AM_HAL_UART_FLOW_CTRL_NONE
+    //!     AM_HAL_UART_FLOW_CTRL_RTS_CTS
+    //
+    uint32_t ui32FlowCtrl;
+}
+am_hal_uart_config_t;
+
+//*****************************************************************************
+//
+// Structure for containing information about the UART's configuration while
+// it is powered down.
+//
+//*****************************************************************************
+typedef struct
+{
+    uint32_t ILPR;
+    uint32_t IBRD;
+    uint32_t FBRD;
+    uint32_t LCRH;
+    uint32_t CR;
+    uint32_t IFLS;
+    uint32_t IER;
+    uint32_t UARTEN;
+    uint32_t bValid;
+}
+am_hal_uart_pwrsave_t;
+
+//*****************************************************************************
+//
+// Global Variables
+//
+//*****************************************************************************
+extern am_hal_uart_pwrsave_t am_hal_uart_pwrsave[AM_REG_UART_NUM_MODULES];
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_uart_pwrctrl_enable(uint32_t ui32Module);
+extern void am_hal_uart_pwrctrl_disable(uint32_t ui32Module);
+extern void am_hal_uart_power_on_restore(uint32_t ui32Module);
+extern void am_hal_uart_power_off_save(uint32_t ui32Module);
+extern void am_hal_uart_config(uint32_t ui32Module,
+                               am_hal_uart_config_t *psConfig);
+extern uint32_t am_hal_uart_status_get(uint32_t ui32Module);
+extern uint32_t am_hal_uart_int_status_get(uint32_t ui32Module,
+                                           bool bEnabledOnly);
+extern void am_hal_uart_int_clear(uint32_t ui32Module,
+                                  uint32_t ui32Interrupt);
+extern void am_hal_uart_int_disable(uint32_t ui32Module,
+                                    uint32_t ui32Interrupt);
+extern void am_hal_uart_int_enable(uint32_t ui32Module,
+                                   uint32_t ui32Interrupt);
+extern uint32_t am_hal_uart_int_enable_get(uint32_t ui32Module);
+extern void am_hal_uart_enable(uint32_t ui32Module);
+extern void am_hal_uart_disable(uint32_t ui32Module);
+extern void am_hal_uart_clock_enable(uint32_t ui32Module);
+extern void am_hal_uart_clock_disable(uint32_t ui32Module);
+extern void am_hal_uart_fifo_config(uint32_t ui32Module, uint32_t ui32LvlCfg);
+extern uint32_t am_hal_uart_flags_get(uint32_t ui32Module);
+
+// rx/tx polled
+extern void am_hal_uart_char_transmit_polled(uint32_t ui32Module,
+                                             char cChar);
+extern void am_hal_uart_string_transmit_polled(uint32_t ui32Module,
+                                               char *pcString);
+extern void am_hal_uart_char_receive_polled(uint32_t ui32Module,
+                                            char *pcChar);
+extern void am_hal_uart_line_receive_polled(uint32_t ui32Module,
+                                            uint32_t ui32MaxChars,
+                                            char *pcChar);
+
+// rx/tx buffered
+extern void am_hal_uart_init_buffered(uint32_t ui32Module,
+                                      uint8_t *pui8RxArray,
+                                      uint32_t ui32RxSize,
+                                      uint8_t *pui8TxArray,
+                                      uint32_t ui32TxSize);
+extern void am_hal_uart_get_status_buffered(uint32_t ui32Module,
+                          uint32_t *pui32RxSize,
+                          uint32_t *pui32TxSize);
+extern void am_hal_uart_service_buffered(uint32_t ui32Module,
+                                         uint32_t ui32Status);
+
+extern void am_hal_uart_service_buffered_timeout_save(uint32_t ui32Module,
+                                                      uint32_t ui32Status);
+extern void am_hal_uart_char_transmit_buffered(uint32_t ui32Module,
+                                               char cChar);
+extern void am_hal_uart_string_transmit_buffered(uint32_t ui32Module,
+                                                 char *pcString);
+extern uint32_t am_hal_uart_char_receive_buffered(uint32_t ui32Module,
+                                                  char *pcString,
+                                                  uint32_t ui32MaxChars);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_UART_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c
new file mode 100644
index 0000000000..31e28855e4
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c
@@ -0,0 +1,287 @@
+//*****************************************************************************
+//
+//  am_hal_vcomp.c
+//! @file
+//!
+//! @brief Functions for operating the on-chip Voltage Comparator
+//!
+//! @addtogroup vcomp2 Voltage Comparator (VCOMP)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Configure the Voltage Comparator module.
+//!
+//! @param psConfig is a structure containing configuration information for the
+//! voltage comparator.
+//!
+//! This function configures the positive and negative input signals for the
+//! voltage comparator.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_vcomp_config(const am_hal_vcomp_config_t *psConfig)
+{
+    //
+    // The configuration word should be a simple OR of the components of the
+    // configuration structure.
+    //
+    AM_REG(VCOMP, CFG) = (psConfig->ui32LevelSelect |
+                          psConfig->ui32PosInput |
+                          psConfig->ui32NegInput);
+}
+
+//*****************************************************************************
+//
+//! @brief Set the Voltage Comparator DAC Level Select in Configuration Reg.
+//!
+//! @param ui32Level - DAC voltage selector (use macros enumerations)
+//!
+//! This function sets the DAC level select in the configuration register.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_vcomp_dac_level_set(uint32_t ui32Level)
+{
+    //
+    // Insert the supplied level into the vcomp configuration register
+    //
+    AM_BFW(VCOMP, CFG, LVLSEL, ui32Level >> AM_REG_VCOMP_CFG_LVLSEL_S);
+}
+
+//*****************************************************************************
+//
+//! @brief Read the state of the voltage comparator.
+//!
+//! This function extracts the comparator state from the status register.
+//!
+//! @return the voltage comparator state
+//
+//*****************************************************************************
+bool
+am_hal_vcomp_read(void)
+{
+    return (AM_BFR(VCOMP,  STAT, CMPOUT) == 1);
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the voltage comparator.
+//!
+//! This function powers up the voltage comparator.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_vcomp_enable(void)
+{
+    AM_REG(VCOMP, PWDKEY) = 0;
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the voltage comparator.
+//!
+//! This function powers down the voltage comparator.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_vcomp_disable(void)
+{
+    AM_REG(VCOMP, PWDKEY) = AM_REG_VCOMP_PWDKEY_KEYVAL;
+}
+
+//*****************************************************************************
+//
+//! @brief Read the state of the voltage comparator interrupt status bits.
+//!
+//! @param bEnabledOnly - return the status of only the enabled interrupts.
+//!
+//! This function extracts the interrupt status bits and returns the raw or
+//! only the enabled based on bEnabledOnly.
+//!
+//! @return Bitwise representation of the current interrupt status.
+//!
+//! The return value will be the logical OR of one or more of the following
+//! values:
+//!
+//! AM_HAL_VCOMP_INT_OUTHI
+//! AM_HAL_VCOMP_INT_OUTLO
+//
+//*****************************************************************************
+uint32_t
+am_hal_vcomp_int_status_get(bool bEnabledOnly)
+{
+    if (bEnabledOnly)
+    {
+        uint32_t u32RetVal = AM_REG(VCOMP, INTSTAT);
+        return u32RetVal & AM_REG(VCOMP, INTEN);
+    }
+    else
+    {
+        return AM_REG(VCOMP, INTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Set the state of the voltage comparator interrupt status bits.
+//!
+//! @param ui32Interrupt - interrupts to be set.
+//!
+//! This function sets the specified interrupt status bits.
+//!
+//! ui32Interrupt should be a logical or of:
+//!
+//! AM_HAL_VCOMP_INT_OUTHI
+//! AM_HAL_VCOMP_INT_OUTLO
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_vcomp_int_set(uint32_t ui32Interrupt)
+{
+    AM_REG(VCOMP, INTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Clear the state of the voltage comparator interrupt status bits.
+//!
+//! @param ui32Interrupt - interrupts to be cleared.
+//!
+//! This function clears the specified interrupt status bits.
+//!
+//! ui32Interrupt should be a logical or of:
+//!
+//! AM_HAL_VCOMP_INT_OUTHI
+//! AM_HAL_VCOMP_INT_OUTLO
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_vcomp_int_clear(uint32_t ui32Interrupt)
+{
+    AM_REG(VCOMP, INTCLR) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the voltage comparator interrupt status bits.
+//!
+//! @param ui32Interrupt - interrupts to be enabled.
+//!
+//! This function enables desired interrupt status bits.
+//!
+//! ui32Interrupt should be a logical or of:
+//!
+//! AM_HAL_VCOMP_INT_OUTHI
+//! AM_HAL_VCOMP_INT_OUTLO
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_vcomp_int_enable(uint32_t ui32Interrupt)
+{
+    AM_REG(VCOMP, INTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return the enabled, voltage comparator interrupt status bits.
+//!
+//! This function returns the enabled interrupt status bits
+//!
+//! @return returns the enabled interrupt status bits. The return is a logical
+//! or of:
+//!
+//! AM_HAL_VCOMP_INT_OUTHI
+//! AM_HAL_VCOMP_INT_OUTLO
+//
+//*****************************************************************************
+uint32_t
+am_hal_vcomp_int_enable_get(void)
+{
+    return AM_REG(VCOMP, INTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the voltage comparator interrupt status bits.
+//!
+//! @param ui32Interrupt - interrupts to be disabled.
+//!
+//! This function disables desired interrupt status bits.
+//!
+//! ui32Interrupt should be a logical or of:
+//!
+//! AM_HAL_VCOMP_INT_OUTHI
+//! AM_HAL_VCOMP_INT_OUTLO
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_vcomp_int_disable(uint32_t ui32Interrupt)
+{
+    AM_REG(VCOMP, INTEN) &= ~ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h
new file mode 100644
index 0000000000..a6ca991aae
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h
@@ -0,0 +1,176 @@
+//*****************************************************************************
+//
+//  am_hal_vcomp.h
+//! @file
+//!
+//! @brief Functions for operating the on-chip Voltage Comparator
+//!
+//! @addtogroup vcomp2 Voltage Comparator (VCOMP)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_VCOMP_H
+#define AM_HAL_VCOMP_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name Positive Input Selection
+//! @brief Use these macros to determine the positive input to the comparator.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_VCOMP_PSEL_VDDADJ            AM_REG_VCOMP_CFG_PSEL_VDDADJ
+#define AM_HAL_VCOMP_PSEL_VTEMP             AM_REG_VCOMP_CFG_PSEL_VTEMP
+#define AM_HAL_VCOMP_PSEL_VEXT1             AM_REG_VCOMP_CFG_PSEL_VEXT1
+#define AM_HAL_VCOMP_PSEL_VEXT2             AM_REG_VCOMP_CFG_PSEL_VEXT2
+//! @}
+
+//*****************************************************************************
+//
+//! @name Negative Input Selection
+//! @brief Use these macros to determine the negative input to the comparator.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_VCOMP_NSEL_VREFEXT1          AM_REG_VCOMP_CFG_NSEL_VREFEXT1
+#define AM_HAL_VCOMP_NSEL_VREFEXT2          AM_REG_VCOMP_CFG_NSEL_VREFEXT2
+#define AM_HAL_VCOMP_NSEL_VREFEXT3          AM_REG_VCOMP_CFG_NSEL_VREFEXT3
+#define AM_HAL_VCOMP_NSEL_DAC_LEVEL         AM_REG_VCOMP_CFG_NSEL_DAC
+//! @}
+
+//*****************************************************************************
+//
+//! @name Negative Input DAC Selectioin
+//! @brief Use these macros to determine the NSEL DAC voltage setting
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_VCOMP_DAC_LVLSEL_0_58V        AM_REG_VCOMP_CFG_LVLSEL_0P58V
+#define AM_HAL_VCOMP_DAC_LVLSEL_0_77V        AM_REG_VCOMP_CFG_LVLSEL_0P77V
+#define AM_HAL_VCOMP_DAC_LVLSEL_0_97V        AM_REG_VCOMP_CFG_LVLSEL_0P97V
+#define AM_HAL_VCOMP_DAC_LVLSEL_1_16V        AM_REG_VCOMP_CFG_LVLSEL_1P16V
+#define AM_HAL_VCOMP_DAC_LVLSEL_1_35V        AM_REG_VCOMP_CFG_LVLSEL_1P35V
+#define AM_HAL_VCOMP_DAC_LVLSEL_1_55V        AM_REG_VCOMP_CFG_LVLSEL_1P55V
+#define AM_HAL_VCOMP_DAC_LVLSEL_1_74V        AM_REG_VCOMP_CFG_LVLSEL_1P74V
+#define AM_HAL_VCOMP_DAC_LVLSEL_1_93V        AM_REG_VCOMP_CFG_LVLSEL_1P93V
+#define AM_HAL_VCOMP_DAC_LVLSEL_2_13V        AM_REG_VCOMP_CFG_LVLSEL_2P13V
+#define AM_HAL_VCOMP_DAC_LVLSEL_2_32V        AM_REG_VCOMP_CFG_LVLSEL_2P32V
+#define AM_HAL_VCOMP_DAC_LVLSEL_2_51V        AM_REG_VCOMP_CFG_LVLSEL_2P51V
+#define AM_HAL_VCOMP_DAC_LVLSEL_2_71V        AM_REG_VCOMP_CFG_LVLSEL_2P71V
+#define AM_HAL_VCOMP_DAC_LVLSEL_2_90V        AM_REG_VCOMP_CFG_LVLSEL_2P90V
+#define AM_HAL_VCOMP_DAC_LVLSEL_3_09V        AM_REG_VCOMP_CFG_LVLSEL_3P09V
+#define AM_HAL_VCOMP_DAC_LVLSEL_3_29V        AM_REG_VCOMP_CFG_LVLSEL_3P29V
+#define AM_HAL_VCOMP_DAC_LVLSEL_3_48V        AM_REG_VCOMP_CFG_LVLSEL_3P48V
+//! @}
+
+//*****************************************************************************
+//
+//! @name Interrupt Status Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to set and clear interrupt bits
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_VCOMP_INT_OUTHI            AM_REG_VCOMP_INTEN_OUTHI_M
+#define AM_HAL_VCOMP_INT_OUTLO            AM_REG_VCOMP_INTEN_OUTLOW_M
+//! @}
+
+//*****************************************************************************
+//
+//! @brief Configuration struct
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The DAC level setting
+    //
+    uint32_t ui32LevelSelect;
+
+    //
+    //! The "positive" comparator input channel
+    //!
+    //! This channel is usually used as the signal to be monitored.
+    //
+    uint32_t ui32PosInput;
+
+    //
+    //! The "negative" comparator input channel
+    //!
+    //! This channel is usually used as the reference signal.
+    //
+    uint32_t ui32NegInput;
+}
+am_hal_vcomp_config_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_vcomp_config(const am_hal_vcomp_config_t *psConfig);
+extern void am_hal_vcomp_dac_level_set(uint32_t ui3Level);
+extern bool am_hal_vcomp_read(void);
+extern void am_hal_vcomp_enable(void);
+extern void am_hal_vcomp_disable(void);
+extern void am_hal_vcomp_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_vcomp_int_enable_get(void);
+extern void am_hal_vcomp_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_vcomp_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_vcomp_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_vcomp_int_status_get(bool bEnabledOnly);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_VCOMP_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c
new file mode 100644
index 0000000000..4e80113fd1
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c
@@ -0,0 +1,454 @@
+//*****************************************************************************
+//
+//  am_hal_wdt.c
+//! @file
+//!
+//! @brief Hardware abstraction layer for the Watchdog Timer module.
+//!
+//! @addtogroup wdt2 Watchdog Timer (WDT)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Adjacency check
+//
+// This is related to the timer read workaround. This macro checks to see if
+// the two supplied count values are within one "tick" of eachother. It should
+// still pass in the event of a timer rollover. The "B" read is assumed to
+// follow the "A" read.  The macro returns "TRUE" when the adjacent timer reads
+// can be used.
+//
+//*****************************************************************************
+#define adjacent(A, B)      (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0))
+
+//*****************************************************************************
+//
+//! @brief Configure the watchdog timer.
+//!
+//! @param psConfig - pointer to a configuration structure containing the
+//! desired watchdog settings.
+//!
+//! This function will set the watchdog configuration register based on the
+//! user's desired settings listed in the structure referenced by psConfig. If
+//! the structure indicates that watchdog interrupts are desired, this function
+//! will also set the interrupt enable bit in the configuration register.
+//!
+//! @note In order to actually receive watchdog interrupt and/or watchdog reset
+//! events, the caller will also need to make sure that the watchdog interrupt
+//! vector is enabled in the ARM NVIC, and that watchdog resets are enabled in
+//! the reset generator module. Otherwise, the watchdog-generated interrupt and
+//! reset events will have no effect.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_wdt_init(const am_hal_wdt_config_t *psConfig)
+{
+    uint32_t ui32ConfigVal;
+    uint16_t ui16IntCount, ui16ResetCount;
+    bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET;
+    bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT;
+
+    //
+    // Read the desired settings from the psConfig structure.
+    //
+    ui16IntCount = psConfig->ui16InterruptCount;
+    ui16ResetCount = psConfig->ui16ResetCount;
+
+    //
+    // Write the interrupt and reset count values to a temporary variable.
+    //
+    // Accept the passed Config value, but clear the Counts that we are about to set.
+    ui32ConfigVal = psConfig->ui32Config & ~(AM_REG_WDT_CFG_INTVAL_M | AM_REG_WDT_CFG_RESVAL_M);
+    ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_INTVAL, ui16IntCount);
+    ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_RESVAL, ui16ResetCount);
+
+    //
+    // If interrupts should be enabled, set the appropriate bit in the
+    // temporary variable. Also, enable the interrupt in INTEN register in the
+    // watchdog module.
+    //
+    if ( bInterruptEnabled )
+    {
+        //
+        // Enable the watchdog interrupt if the configuration calls for them.
+        //
+        AM_REGn(WDT, 0, INTEN) |= AM_REG_WDT_INTEN_WDT_M;
+    }
+    else
+    {
+        //
+        // Disable the watchdog interrupt if the configuration doesn't call for
+        // watchdog interrupts.
+        //
+        AM_REGn(WDT, 0, INTEN) &= ~AM_REG_WDT_INTEN_WDT_M;
+    }
+
+    //
+    // If resets should be enabled, set the appropriate bit in the temporary
+    // variable.
+    //
+    if ( bResetEnabled )
+    {
+        //
+        // Also enable watchdog resets in the reset module.
+        //
+        AM_REG(RSTGEN, CFG) |= AM_REG_RSTGEN_CFG_WDREN_M;
+    }
+    else
+    {
+        //
+        // Disable watchdog resets in the reset module.
+        //
+        AM_REG(RSTGEN, CFG) &= ~AM_REG_RSTGEN_CFG_WDREN_M;
+    }
+
+    //
+    // Check for a user specified clock select. If none specified then
+    // set 128Hz.
+    //
+    if ( !(psConfig->ui32Config & AM_REG_WDT_CFG_CLKSEL_M) )
+    {
+        ui32ConfigVal |= AM_REG_WDT_CFG_CLKSEL_128HZ;
+    }
+
+    //
+    // Write the saved value to the watchdog configuration register.
+    //
+    AM_REGn(WDT, 0, CFG) = ui32ConfigVal;
+}
+
+//*****************************************************************************
+//
+//! @brief Starts the watchdog timer.
+//!
+//! Enables the watchdog timer tick using the 'enable' bit in the watchdog
+//! configuration register.  This function does not perform any locking of the
+//! watchdog timer, so it can be disabled or reconfigured later.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_wdt_start(void)
+{
+    //
+    // Make sure the watchdog timer is in the "reset" state, and then set the
+    // enable bit to start counting.
+    //
+    AM_REGn(WDT, 0, CFG) |= AM_REG_WDT_CFG_WDTEN_M;
+    AM_REGn(WDT, 0, RSTRT) |= AM_REG_WDT_RSTRT_RSTRT_KEYVALUE;
+
+}
+
+//*****************************************************************************
+//
+//! @brief Stops the watchdog timer.
+//!
+//! Disables the watchdog timer tick by clearing the 'enable' bit in the
+//! watchdog configuration register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_wdt_halt(void)
+{
+
+    //
+    // Clear the watchdog enable bit.
+    //
+    AM_REGn(WDT, 0, CFG) &= ~AM_REG_WDT_CFG_WDTEN_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Locks the watchdog configuration and starts the watchdog timer.
+//!
+//! This function sets the watchdog "lock" register, which prevents software
+//! from re-configuring the watchdog. This action will also set the enable bit
+//! for the watchdog timer, so it will start counting immediately.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_wdt_lock_and_start(void)
+{
+    //
+    // Write the 'key' value to the watchdog lock register.
+    //
+    AM_REGn(WDT, 0, LOCK) = AM_REG_WDT_LOCK_LOCK_KEYVALUE;
+}
+
+//*****************************************************************************
+//
+//! @brief Read the state of the wdt interrupt status.
+//!
+//! @param bEnabledOnly - return the status of only the enabled interrupts.
+//!
+//! This function extracts the interrupt status bits and returns the enabled or
+//! raw based on bEnabledOnly.
+//!
+//! @return WDT interrupt status.
+//
+//*****************************************************************************
+uint32_t
+am_hal_wdt_int_status_get(bool bEnabledOnly)
+{
+    if (bEnabledOnly)
+    {
+        uint32_t u32RetVal = AM_REG(WDT, INTSTAT);
+        return u32RetVal & AM_REG(WDT, INTEN);
+    }
+    else
+    {
+        return AM_REG(WDT, INTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Set the state of the wdt interrupt status bit.
+//!
+//! This function sets the interrupt bit.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_wdt_int_set(void)
+{
+    AM_REG(WDT, INTSET) = AM_REG_WDT_INTSET_WDT_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Clear the state of the wdt interrupt status bit.
+//!
+//! This function clear the interrupt bit.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_wdt_int_clear(void)
+{
+    AM_REGn(WDT, 0, INTCLR) = AM_REG_WDT_INTCLR_WDT_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the wdt interrupt.
+//!
+//! This function enable the interrupt.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_wdt_int_enable(void)
+{
+    AM_REG(WDT, INTEN) |= AM_REG_WDT_INTSET_WDT_M;
+}
+
+//*****************************************************************************
+//
+//! @brief Return the enabled WDT interrupts.
+//!
+//! This function returns the enabled WDT interrupts.
+//!
+//! @return enabled WDT interrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_wdt_int_enable_get(void)
+{
+    return AM_REG(WDT, INTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the wdt interrupt.
+//!
+//! This function disablee the interrupt.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_wdt_int_disable(void)
+{
+    AM_REG(WDT, INTEN) &= ~AM_REG_WDT_INTSET_WDT_M;
+}
+
+//*****************************************************************************
+//
+// Static function for reading the WDT counter value.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+__attribute__((naked))
+static
+void
+back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register)
+{
+    // pui32Array[] is a pointer to a 3 word data array provided by the caller.
+    // pui32Register = address of the timer to be read.
+    __asm
+    (
+        // Do 3 back-to-back reads of the register
+        "   ldr     r2, [r1, #0]\n"             // Get counter register value
+        "   ldr     r3, [r1, #0]\n"             // Get counter register value again
+        "   ldr     r1, [r1, #0]\n"             // Get counter register value for a third time
+        "   str     r2, [r0, #0]\n"             // Store register value to variable
+        "   str     r3, [r0, #4]\n"             // Store register value to variable
+        "   str     r1, [r0, #8]\n"             // Store register value to variable
+        "   bx      lr\n"
+    );
+}
+
+#elif defined(__ARMCC_VERSION)
+__asm static uint32_t
+back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register)
+{
+    ldr     r2, [r1, #0]             // Get TMRn register value
+    ldr     r3, [r1, #0]             // Get TMRn register value again
+    ldr     r1, [r1, #0]             // Get TMRn register value for a third time
+    str     r2, [r0, #0]             // Store register value to variable
+    str     r3, [r0, #4]             // Store register value to variable
+    str     r1, [r0, #8]             // Store register value to variable
+    bx      lr
+}
+
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma diag_suppress = Pe940   // Suppress IAR compiler warning about missing
+                                // return statement on a non-void function
+__stackless static uint32_t
+back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register)
+{
+    __asm("    ldr     r2, [r1, #0]");  // Get TMRn register value
+    __asm("    ldr     r3, [r1, #0]");  // Get TMRn register value again
+    __asm("    ldr     r1, [r1, #0]");  // Get TMRn register value for a third time
+    __asm("    str     r2, [r0, #0]");  // Store register value to variable
+    __asm("    str     r3, [r0, #4]");  // Store register value to variable
+    __asm("    str     r1, [r0, #8]");  // Store register value to variable
+    __asm("    bx      lr");
+}
+#pragma diag_default = Pe940    // Restore IAR compiler warning
+#endif
+
+
+//*****************************************************************************
+//
+//! @brief Get the wdt counter value.
+//!
+//! This function reads the current value of watch dog timer counter register.
+//!
+//! WARNING caller is responsible for masking interrutps before calling this
+//! function.
+//!
+//! @return None
+//
+//*****************************************************************************
+uint32_t
+am_hal_wdt_counter_get(void)
+{
+  uint32_t ui32Values[3] = {0};
+    uint32_t ui32Value;
+
+    //
+    // First, go read the value from the counter register 3 times
+    // back to back in assembly language.
+    //
+    back2back_read_asm(ui32Values, (uint32_t *)AM_REG_WDTn(0));
+
+    //
+    // Now, we'll figure out which of the three values is the correct time.
+    //
+    if (ui32Values[0] == ui32Values[1])
+    {
+        //
+        // If the first two values match, then neither one was a bad read.
+        // We'll take this as the current time.
+        //
+        ui32Value = ui32Values[1];
+    }
+    else
+    {
+        //
+        // If the first two values didn't match, then one of them might be bad.
+        // If one of the first two values is bad, then the third one should
+        // always be correct. We'll take the third value as the correct count.
+        //
+        ui32Value = ui32Values[2];
+
+        //
+        // If all of the statements about the architecture are true, the third
+        // value should be correct, and it should always be within one count of
+        // either the first or the second value.
+        //
+        // Just in case, we'll check against the previous two values to make
+        // sure that our final answer was reasonable. If it isn't, we will
+        // flag it as a "bad read", and fail this assert statement.
+        //
+        // This shouldn't ever happen, and it hasn't ever happened in any of
+        // our tests so far.
+        //
+        am_hal_debug_assert_msg((adjacent(ui32Values[1], ui32Values[2]) ||
+                                 adjacent(ui32Values[0], ui32Values[2])),
+                                "Bad CDT read");
+    }
+
+    return ui32Value;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h
new file mode 100644
index 0000000000..63766fa458
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h
@@ -0,0 +1,184 @@
+//*****************************************************************************
+//
+//  am_hal_wdt.h
+//! @file
+//!
+//! @brief Hardware abstraction layer for the Watchdog Timer module.
+//!
+//! @addtogroup wdt2 Watchdog Timer (WDT)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_WDT_H
+#define AM_HAL_WDT_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Macro definitions
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! @name WDT Clock Divider Selections.
+//! @brief Macro definitions for WDT clock frequencies.
+//!
+//! These macros may be used with the am_hal_wdt_config_t structure to set the
+//! clock frequency of the watch dog timer.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_WDT_LFRC_CLK_DEFAULT AM_REG_WDT_CFG_CLKSEL_128HZ
+#define AM_HAL_WDT_LFRC_CLK_128HZ   AM_REG_WDT_CFG_CLKSEL_128HZ
+#define AM_HAL_WDT_LFRC_CLK_16HZ    AM_REG_WDT_CFG_CLKSEL_16HZ
+#define AM_HAL_WDT_LFRC_CLK_1HZ     AM_REG_WDT_CFG_CLKSEL_1HZ
+#define AM_HAL_WDT_LFRC_CLK_1_16HZ  AM_REG_WDT_CFG_CLKSEL_1_16HZ
+#define AM_HAL_WDT_LFRC_CLK_OFF     AM_REG_WDT_CFG_CLKSEL_OFF
+//! @}
+
+//*****************************************************************************
+//
+//! @name WDT Enable Reset in the WDT Configuration.
+//! @brief Macro definitions for WDT Reset Enable.
+//!
+//! These macros may be used with the am_hal_wdt_config_t structure to enable
+//! the watch dog timer to generate resets to the chip.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_WDT_ENABLE_RESET      AM_REG_WDT_CFG_RESEN(1)
+#define AM_HAL_WDT_DISABLE_RESET     AM_REG_WDT_CFG_RESEN(0)
+//! @}
+
+//*****************************************************************************
+//
+//! @name WDT Enable Interrupt Generation from the WDT Configuration.
+//! @brief Macro definitions for WDT Interrupt Enable.
+//!
+//! These macros may be used with the am_hal_wdt_config_t structure to enable
+//! the watch dog timer to generate generate WDT interrupts.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_WDT_ENABLE_INTERRUPT      AM_REG_WDT_CFG_INTEN(1)
+#define AM_HAL_WDT_DISABLE_INTERRUPT     AM_REG_WDT_CFG_INTEN(0)
+//! @}
+
+//*****************************************************************************
+//
+//! @brief Watchdog timer configuration structure.
+//!
+//! This structure is made to be used with the am_hal_wdt_init() function. It
+//! describes the configuration of the watchdog timer.
+//
+//*****************************************************************************
+typedef struct
+{
+    //! Configuration Values for watchdog timer
+    //! event is generated.
+    uint32_t ui32Config;
+
+    //! Number of watchdog timer ticks allowed before a watchdog interrupt
+    //! event is generated.
+    uint16_t ui16InterruptCount;
+
+    //! Number of watchdog timer ticks allowed before the watchdog will issue a
+    //! system reset.
+    uint16_t ui16ResetCount;
+
+}
+am_hal_wdt_config_t;
+
+
+//*****************************************************************************
+//
+//! @brief Restarts the watchdog timer ("Pets" the dog)
+//!
+//! This function restarts the watchdog timer from the beginning, preventing
+//! any interrupt or reset even from occuring until the next time the watchdog
+//! timer expires.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#define am_hal_wdt_restart()                                                  \
+    do                                                                        \
+    {                                                                         \
+        AM_REGn(WDT, 0, RSTRT) = AM_REG_WDT_RSTRT_RSTRT_KEYVALUE;             \
+        (void)AM_REGn(WDT, 0, RSTRT);                                         \
+    }                                                                         \
+    while(0)
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_wdt_init(const am_hal_wdt_config_t *psConfig);
+extern void am_hal_wdt_start(void);
+extern void am_hal_wdt_halt(void);
+extern void am_hal_wdt_lock_and_start(void);
+extern void am_hal_wdt_int_enable(void);
+extern uint32_t am_hal_wdt_int_enable_get(void);
+extern void am_hal_wdt_int_disable(void);
+extern void am_hal_wdt_int_clear(void);
+extern void am_hal_wdt_int_set(void);
+extern uint32_t am_hal_wdt_int_status_get(bool bEnabledOnly);
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_WDT_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h b/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h
new file mode 100644
index 0000000000..54d2d8620f
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h
@@ -0,0 +1,864 @@
+//*****************************************************************************
+//
+//  am_reg_adc.h
+//! @file
+//!
+//! @brief Register macros for the ADC module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_ADC_H
+#define AM_REG_ADC_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_ADC_NUM_MODULES                       1
+#define AM_REG_ADCn(n) \
+    (REG_ADC_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_ADC_CFG_O                             0x00000000
+#define AM_REG_ADC_STAT_O                            0x00000004
+#define AM_REG_ADC_SWT_O                             0x00000008
+#define AM_REG_ADC_SL0CFG_O                          0x0000000C
+#define AM_REG_ADC_SL1CFG_O                          0x00000010
+#define AM_REG_ADC_SL2CFG_O                          0x00000014
+#define AM_REG_ADC_SL3CFG_O                          0x00000018
+#define AM_REG_ADC_SL4CFG_O                          0x0000001C
+#define AM_REG_ADC_SL5CFG_O                          0x00000020
+#define AM_REG_ADC_SL6CFG_O                          0x00000024
+#define AM_REG_ADC_SL7CFG_O                          0x00000028
+#define AM_REG_ADC_WULIM_O                           0x0000002C
+#define AM_REG_ADC_WLLIM_O                           0x00000030
+#define AM_REG_ADC_FIFO_O                            0x00000038
+#define AM_REG_ADC_INTEN_O                           0x00000200
+#define AM_REG_ADC_INTSTAT_O                         0x00000204
+#define AM_REG_ADC_INTCLR_O                          0x00000208
+#define AM_REG_ADC_INTSET_O                          0x0000020C
+
+//*****************************************************************************
+//
+// ADC_INTEN - ADC Interrupt registers: Enable
+//
+//*****************************************************************************
+// Window comparator voltage incursion interrupt.
+#define AM_REG_ADC_INTEN_WCINC_S                     5
+#define AM_REG_ADC_INTEN_WCINC_M                     0x00000020
+#define AM_REG_ADC_INTEN_WCINC(n)                    (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_ADC_INTEN_WCINC_WCINCINT              0x00000020
+
+// Window comparator voltage excursion interrupt.
+#define AM_REG_ADC_INTEN_WCEXC_S                     4
+#define AM_REG_ADC_INTEN_WCEXC_M                     0x00000010
+#define AM_REG_ADC_INTEN_WCEXC(n)                    (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_ADC_INTEN_WCEXC_WCEXCINT              0x00000010
+
+// FIFO 100 percent full interrupt.
+#define AM_REG_ADC_INTEN_FIFOOVR2_S                  3
+#define AM_REG_ADC_INTEN_FIFOOVR2_M                  0x00000008
+#define AM_REG_ADC_INTEN_FIFOOVR2(n)                 (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_ADC_INTEN_FIFOOVR2_FIFOFULLINT        0x00000008
+
+// FIFO 75 percent full interrupt.
+#define AM_REG_ADC_INTEN_FIFOOVR1_S                  2
+#define AM_REG_ADC_INTEN_FIFOOVR1_M                  0x00000004
+#define AM_REG_ADC_INTEN_FIFOOVR1(n)                 (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_ADC_INTEN_FIFOOVR1_FIFO75INT          0x00000004
+
+// ADC scan complete interrupt.
+#define AM_REG_ADC_INTEN_SCNCMP_S                    1
+#define AM_REG_ADC_INTEN_SCNCMP_M                    0x00000002
+#define AM_REG_ADC_INTEN_SCNCMP(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_INTEN_SCNCMP_SCNCMPINT            0x00000002
+
+// ADC conversion complete interrupt.
+#define AM_REG_ADC_INTEN_CNVCMP_S                    0
+#define AM_REG_ADC_INTEN_CNVCMP_M                    0x00000001
+#define AM_REG_ADC_INTEN_CNVCMP(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_INTEN_CNVCMP_CNVCMPINT            0x00000001
+
+//*****************************************************************************
+//
+// ADC_INTSTAT - ADC Interrupt registers: Status
+//
+//*****************************************************************************
+// Window comparator voltage incursion interrupt.
+#define AM_REG_ADC_INTSTAT_WCINC_S                   5
+#define AM_REG_ADC_INTSTAT_WCINC_M                   0x00000020
+#define AM_REG_ADC_INTSTAT_WCINC(n)                  (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_ADC_INTSTAT_WCINC_WCINCINT            0x00000020
+
+// Window comparator voltage excursion interrupt.
+#define AM_REG_ADC_INTSTAT_WCEXC_S                   4
+#define AM_REG_ADC_INTSTAT_WCEXC_M                   0x00000010
+#define AM_REG_ADC_INTSTAT_WCEXC(n)                  (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_ADC_INTSTAT_WCEXC_WCEXCINT            0x00000010
+
+// FIFO 100 percent full interrupt.
+#define AM_REG_ADC_INTSTAT_FIFOOVR2_S                3
+#define AM_REG_ADC_INTSTAT_FIFOOVR2_M                0x00000008
+#define AM_REG_ADC_INTSTAT_FIFOOVR2(n)               (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_ADC_INTSTAT_FIFOOVR2_FIFOFULLINT      0x00000008
+
+// FIFO 75 percent full interrupt.
+#define AM_REG_ADC_INTSTAT_FIFOOVR1_S                2
+#define AM_REG_ADC_INTSTAT_FIFOOVR1_M                0x00000004
+#define AM_REG_ADC_INTSTAT_FIFOOVR1(n)               (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_ADC_INTSTAT_FIFOOVR1_FIFO75INT        0x00000004
+
+// ADC scan complete interrupt.
+#define AM_REG_ADC_INTSTAT_SCNCMP_S                  1
+#define AM_REG_ADC_INTSTAT_SCNCMP_M                  0x00000002
+#define AM_REG_ADC_INTSTAT_SCNCMP(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_INTSTAT_SCNCMP_SCNCMPINT          0x00000002
+
+// ADC conversion complete interrupt.
+#define AM_REG_ADC_INTSTAT_CNVCMP_S                  0
+#define AM_REG_ADC_INTSTAT_CNVCMP_M                  0x00000001
+#define AM_REG_ADC_INTSTAT_CNVCMP(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_INTSTAT_CNVCMP_CNVCMPINT          0x00000001
+
+//*****************************************************************************
+//
+// ADC_INTCLR - ADC Interrupt registers: Clear
+//
+//*****************************************************************************
+// Window comparator voltage incursion interrupt.
+#define AM_REG_ADC_INTCLR_WCINC_S                    5
+#define AM_REG_ADC_INTCLR_WCINC_M                    0x00000020
+#define AM_REG_ADC_INTCLR_WCINC(n)                   (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_ADC_INTCLR_WCINC_WCINCINT             0x00000020
+
+// Window comparator voltage excursion interrupt.
+#define AM_REG_ADC_INTCLR_WCEXC_S                    4
+#define AM_REG_ADC_INTCLR_WCEXC_M                    0x00000010
+#define AM_REG_ADC_INTCLR_WCEXC(n)                   (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_ADC_INTCLR_WCEXC_WCEXCINT             0x00000010
+
+// FIFO 100 percent full interrupt.
+#define AM_REG_ADC_INTCLR_FIFOOVR2_S                 3
+#define AM_REG_ADC_INTCLR_FIFOOVR2_M                 0x00000008
+#define AM_REG_ADC_INTCLR_FIFOOVR2(n)                (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_ADC_INTCLR_FIFOOVR2_FIFOFULLINT       0x00000008
+
+// FIFO 75 percent full interrupt.
+#define AM_REG_ADC_INTCLR_FIFOOVR1_S                 2
+#define AM_REG_ADC_INTCLR_FIFOOVR1_M                 0x00000004
+#define AM_REG_ADC_INTCLR_FIFOOVR1(n)                (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_ADC_INTCLR_FIFOOVR1_FIFO75INT         0x00000004
+
+// ADC scan complete interrupt.
+#define AM_REG_ADC_INTCLR_SCNCMP_S                   1
+#define AM_REG_ADC_INTCLR_SCNCMP_M                   0x00000002
+#define AM_REG_ADC_INTCLR_SCNCMP(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_INTCLR_SCNCMP_SCNCMPINT           0x00000002
+
+// ADC conversion complete interrupt.
+#define AM_REG_ADC_INTCLR_CNVCMP_S                   0
+#define AM_REG_ADC_INTCLR_CNVCMP_M                   0x00000001
+#define AM_REG_ADC_INTCLR_CNVCMP(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_INTCLR_CNVCMP_CNVCMPINT           0x00000001
+
+//*****************************************************************************
+//
+// ADC_INTSET - ADC Interrupt registers: Set
+//
+//*****************************************************************************
+// Window comparator voltage incursion interrupt.
+#define AM_REG_ADC_INTSET_WCINC_S                    5
+#define AM_REG_ADC_INTSET_WCINC_M                    0x00000020
+#define AM_REG_ADC_INTSET_WCINC(n)                   (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_ADC_INTSET_WCINC_WCINCINT             0x00000020
+
+// Window comparator voltage excursion interrupt.
+#define AM_REG_ADC_INTSET_WCEXC_S                    4
+#define AM_REG_ADC_INTSET_WCEXC_M                    0x00000010
+#define AM_REG_ADC_INTSET_WCEXC(n)                   (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_ADC_INTSET_WCEXC_WCEXCINT             0x00000010
+
+// FIFO 100 percent full interrupt.
+#define AM_REG_ADC_INTSET_FIFOOVR2_S                 3
+#define AM_REG_ADC_INTSET_FIFOOVR2_M                 0x00000008
+#define AM_REG_ADC_INTSET_FIFOOVR2(n)                (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_ADC_INTSET_FIFOOVR2_FIFOFULLINT       0x00000008
+
+// FIFO 75 percent full interrupt.
+#define AM_REG_ADC_INTSET_FIFOOVR1_S                 2
+#define AM_REG_ADC_INTSET_FIFOOVR1_M                 0x00000004
+#define AM_REG_ADC_INTSET_FIFOOVR1(n)                (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_ADC_INTSET_FIFOOVR1_FIFO75INT         0x00000004
+
+// ADC scan complete interrupt.
+#define AM_REG_ADC_INTSET_SCNCMP_S                   1
+#define AM_REG_ADC_INTSET_SCNCMP_M                   0x00000002
+#define AM_REG_ADC_INTSET_SCNCMP(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_INTSET_SCNCMP_SCNCMPINT           0x00000002
+
+// ADC conversion complete interrupt.
+#define AM_REG_ADC_INTSET_CNVCMP_S                   0
+#define AM_REG_ADC_INTSET_CNVCMP_M                   0x00000001
+#define AM_REG_ADC_INTSET_CNVCMP(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_INTSET_CNVCMP_CNVCMPINT           0x00000001
+
+//*****************************************************************************
+//
+// ADC_CFG - Configuration Register
+//
+//*****************************************************************************
+// Select the source and frequency for the ADC clock.  All values not enumerated
+// below are undefined.
+#define AM_REG_ADC_CFG_CLKSEL_S                      24
+#define AM_REG_ADC_CFG_CLKSEL_M                      0x03000000
+#define AM_REG_ADC_CFG_CLKSEL(n)                     (((uint32_t)(n) << 24) & 0x03000000)
+#define AM_REG_ADC_CFG_CLKSEL_OFF                    0x00000000
+#define AM_REG_ADC_CFG_CLKSEL_HFRC                   0x01000000
+#define AM_REG_ADC_CFG_CLKSEL_HFRC_DIV2              0x02000000
+
+// This bit selects the ADC trigger polarity for external off chip triggers.
+#define AM_REG_ADC_CFG_TRIGPOL_S                     19
+#define AM_REG_ADC_CFG_TRIGPOL_M                     0x00080000
+#define AM_REG_ADC_CFG_TRIGPOL(n)                    (((uint32_t)(n) << 19) & 0x00080000)
+#define AM_REG_ADC_CFG_TRIGPOL_RISING_EDGE           0x00000000
+#define AM_REG_ADC_CFG_TRIGPOL_FALLING_EDGE          0x00080000
+
+// Select the ADC trigger source.
+#define AM_REG_ADC_CFG_TRIGSEL_S                     16
+#define AM_REG_ADC_CFG_TRIGSEL_M                     0x00070000
+#define AM_REG_ADC_CFG_TRIGSEL(n)                    (((uint32_t)(n) << 16) & 0x00070000)
+#define AM_REG_ADC_CFG_TRIGSEL_EXT0                  0x00000000
+#define AM_REG_ADC_CFG_TRIGSEL_EXT1                  0x00010000
+#define AM_REG_ADC_CFG_TRIGSEL_EXT2                  0x00020000
+#define AM_REG_ADC_CFG_TRIGSEL_EXT3                  0x00030000
+#define AM_REG_ADC_CFG_TRIGSEL_VCOMP                 0x00040000
+#define AM_REG_ADC_CFG_TRIGSEL_SWT                   0x00070000
+
+// Select the ADC reference voltage.
+#define AM_REG_ADC_CFG_REFSEL_S                      8
+#define AM_REG_ADC_CFG_REFSEL_M                      0x00000300
+#define AM_REG_ADC_CFG_REFSEL(n)                     (((uint32_t)(n) << 8) & 0x00000300)
+#define AM_REG_ADC_CFG_REFSEL_INT2P0                 0x00000000
+#define AM_REG_ADC_CFG_REFSEL_INT1P5                 0x00000100
+#define AM_REG_ADC_CFG_REFSEL_EXT2P0                 0x00000200
+#define AM_REG_ADC_CFG_REFSEL_EXT1P5                 0x00000300
+
+// Clock mode register
+#define AM_REG_ADC_CFG_CKMODE_S                      4
+#define AM_REG_ADC_CFG_CKMODE_M                      0x00000010
+#define AM_REG_ADC_CFG_CKMODE(n)                     (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_ADC_CFG_CKMODE_LPCKMODE               0x00000000
+#define AM_REG_ADC_CFG_CKMODE_LLCKMODE               0x00000010
+
+// Select power mode to enter between active scans.
+#define AM_REG_ADC_CFG_LPMODE_S                      3
+#define AM_REG_ADC_CFG_LPMODE_M                      0x00000008
+#define AM_REG_ADC_CFG_LPMODE(n)                     (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_ADC_CFG_LPMODE_MODE0                  0x00000000
+#define AM_REG_ADC_CFG_LPMODE_MODE1                  0x00000008
+
+// This bit enables Repeating Scan Mode.
+#define AM_REG_ADC_CFG_RPTEN_S                       2
+#define AM_REG_ADC_CFG_RPTEN_M                       0x00000004
+#define AM_REG_ADC_CFG_RPTEN(n)                      (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_ADC_CFG_RPTEN_SINGLE_SCAN             0x00000000
+#define AM_REG_ADC_CFG_RPTEN_REPEATING_SCAN          0x00000004
+
+// This bit enables the ADC module. While the ADC is enabled, the ADCCFG and
+// SLOT Configuration regsiter settings must remain stable and unchanged. All
+// configuration register settings, slot configuration settings and window
+// comparison settings should be written prior to setting the ADCEN bit to '1'.
+#define AM_REG_ADC_CFG_ADCEN_S                       0
+#define AM_REG_ADC_CFG_ADCEN_M                       0x00000001
+#define AM_REG_ADC_CFG_ADCEN(n)                      (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_CFG_ADCEN_DIS                     0x00000000
+#define AM_REG_ADC_CFG_ADCEN_EN                      0x00000001
+
+//*****************************************************************************
+//
+// ADC_STAT - ADC Power Status
+//
+//*****************************************************************************
+// Indicates the power-status of the ADC.
+#define AM_REG_ADC_STAT_PWDSTAT_S                    0
+#define AM_REG_ADC_STAT_PWDSTAT_M                    0x00000001
+#define AM_REG_ADC_STAT_PWDSTAT(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_STAT_PWDSTAT_ON                   0x00000000
+#define AM_REG_ADC_STAT_PWDSTAT_POWERED_DOWN         0x00000001
+
+//*****************************************************************************
+//
+// ADC_SWT - Software trigger
+//
+//*****************************************************************************
+// Writing 0x37 to this register generates a software trigger.
+#define AM_REG_ADC_SWT_SWT_S                         0
+#define AM_REG_ADC_SWT_SWT_M                         0x000000FF
+#define AM_REG_ADC_SWT_SWT(n)                        (((uint32_t)(n) << 0) & 0x000000FF)
+#define AM_REG_ADC_SWT_SWT_GEN_SW_TRIGGER            0x00000037
+
+//*****************************************************************************
+//
+// ADC_SL0CFG - Slot 0 Configuration Register
+//
+//*****************************************************************************
+// Select the number of measurements to average in the accumulate divide module
+// for this slot.
+#define AM_REG_ADC_SL0CFG_ADSEL0_S                   24
+#define AM_REG_ADC_SL0CFG_ADSEL0_M                   0x07000000
+#define AM_REG_ADC_SL0CFG_ADSEL0(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_1_MSRMT         0x00000000
+#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS        0x01000000
+#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS        0x02000000
+#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_8_MSRMT         0x03000000
+#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS       0x04000000
+#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS       0x05000000
+#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS       0x06000000
+#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS      0x07000000
+
+// Set the Precision Mode For Slot.
+#define AM_REG_ADC_SL0CFG_PRMODE0_S                  16
+#define AM_REG_ADC_SL0CFG_PRMODE0_M                  0x00030000
+#define AM_REG_ADC_SL0CFG_PRMODE0(n)                 (((uint32_t)(n) << 16) & 0x00030000)
+#define AM_REG_ADC_SL0CFG_PRMODE0_P14B               0x00000000
+#define AM_REG_ADC_SL0CFG_PRMODE0_P12B               0x00010000
+#define AM_REG_ADC_SL0CFG_PRMODE0_P10B               0x00020000
+#define AM_REG_ADC_SL0CFG_PRMODE0_P8B                0x00030000
+
+// Select one of the 14 channel inputs for this slot.
+#define AM_REG_ADC_SL0CFG_CHSEL0_S                   8
+#define AM_REG_ADC_SL0CFG_CHSEL0_M                   0x00000F00
+#define AM_REG_ADC_SL0CFG_CHSEL0(n)                  (((uint32_t)(n) << 8) & 0x00000F00)
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE0                 0x00000000
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE1                 0x00000100
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE2                 0x00000200
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE3                 0x00000300
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE4                 0x00000400
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE5                 0x00000500
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE6                 0x00000600
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE7                 0x00000700
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE8                 0x00000800
+#define AM_REG_ADC_SL0CFG_CHSEL0_SE9                 0x00000900
+#define AM_REG_ADC_SL0CFG_CHSEL0_DF0                 0x00000A00
+#define AM_REG_ADC_SL0CFG_CHSEL0_DF1                 0x00000B00
+#define AM_REG_ADC_SL0CFG_CHSEL0_TEMP                0x00000C00
+#define AM_REG_ADC_SL0CFG_CHSEL0_BATT                0x00000D00
+#define AM_REG_ADC_SL0CFG_CHSEL0_VSS                 0x00000E00
+
+// This bit enables the window compare function for slot 0.
+#define AM_REG_ADC_SL0CFG_WCEN0_S                    1
+#define AM_REG_ADC_SL0CFG_WCEN0_M                    0x00000002
+#define AM_REG_ADC_SL0CFG_WCEN0(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_SL0CFG_WCEN0_WCEN                 0x00000002
+
+// This bit enables slot 0 for ADC conversions.
+#define AM_REG_ADC_SL0CFG_SLEN0_S                    0
+#define AM_REG_ADC_SL0CFG_SLEN0_M                    0x00000001
+#define AM_REG_ADC_SL0CFG_SLEN0(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_SL0CFG_SLEN0_SLEN                 0x00000001
+
+//*****************************************************************************
+//
+// ADC_SL1CFG - Slot 1 Configuration Register
+//
+//*****************************************************************************
+// Select the number of measurements to average in the accumulate divide module
+// for this slot.
+#define AM_REG_ADC_SL1CFG_ADSEL1_S                   24
+#define AM_REG_ADC_SL1CFG_ADSEL1_M                   0x07000000
+#define AM_REG_ADC_SL1CFG_ADSEL1(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_1_MSRMT         0x00000000
+#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS        0x01000000
+#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS        0x02000000
+#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_8_MSRMT         0x03000000
+#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS       0x04000000
+#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS       0x05000000
+#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS       0x06000000
+#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS      0x07000000
+
+// Set the Precision Mode For Slot.
+#define AM_REG_ADC_SL1CFG_PRMODE1_S                  16
+#define AM_REG_ADC_SL1CFG_PRMODE1_M                  0x00030000
+#define AM_REG_ADC_SL1CFG_PRMODE1(n)                 (((uint32_t)(n) << 16) & 0x00030000)
+#define AM_REG_ADC_SL1CFG_PRMODE1_P14B               0x00000000
+#define AM_REG_ADC_SL1CFG_PRMODE1_P12B               0x00010000
+#define AM_REG_ADC_SL1CFG_PRMODE1_P10B               0x00020000
+#define AM_REG_ADC_SL1CFG_PRMODE1_P8B                0x00030000
+
+// Select one of the 14 channel inputs for this slot.
+#define AM_REG_ADC_SL1CFG_CHSEL1_S                   8
+#define AM_REG_ADC_SL1CFG_CHSEL1_M                   0x00000F00
+#define AM_REG_ADC_SL1CFG_CHSEL1(n)                  (((uint32_t)(n) << 8) & 0x00000F00)
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE0                 0x00000000
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE1                 0x00000100
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE2                 0x00000200
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE3                 0x00000300
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE4                 0x00000400
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE5                 0x00000500
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE6                 0x00000600
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE7                 0x00000700
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE8                 0x00000800
+#define AM_REG_ADC_SL1CFG_CHSEL1_SE9                 0x00000900
+#define AM_REG_ADC_SL1CFG_CHSEL1_DF0                 0x00000A00
+#define AM_REG_ADC_SL1CFG_CHSEL1_DF1                 0x00000B00
+#define AM_REG_ADC_SL1CFG_CHSEL1_TEMP                0x00000C00
+#define AM_REG_ADC_SL1CFG_CHSEL1_BATT                0x00000D00
+#define AM_REG_ADC_SL1CFG_CHSEL1_VSS                 0x00000E00
+
+// This bit enables the window compare function for slot 1.
+#define AM_REG_ADC_SL1CFG_WCEN1_S                    1
+#define AM_REG_ADC_SL1CFG_WCEN1_M                    0x00000002
+#define AM_REG_ADC_SL1CFG_WCEN1(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_SL1CFG_WCEN1_WCEN                 0x00000002
+
+// This bit enables slot 1 for ADC conversions.
+#define AM_REG_ADC_SL1CFG_SLEN1_S                    0
+#define AM_REG_ADC_SL1CFG_SLEN1_M                    0x00000001
+#define AM_REG_ADC_SL1CFG_SLEN1(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_SL1CFG_SLEN1_SLEN                 0x00000001
+
+//*****************************************************************************
+//
+// ADC_SL2CFG - Slot 2 Configuration Register
+//
+//*****************************************************************************
+// Select the number of measurements to average in the accumulate divide module
+// for this slot.
+#define AM_REG_ADC_SL2CFG_ADSEL2_S                   24
+#define AM_REG_ADC_SL2CFG_ADSEL2_M                   0x07000000
+#define AM_REG_ADC_SL2CFG_ADSEL2(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_1_MSRMT         0x00000000
+#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS        0x01000000
+#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS        0x02000000
+#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_8_MSRMT         0x03000000
+#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS       0x04000000
+#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS       0x05000000
+#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS       0x06000000
+#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS      0x07000000
+
+// Set the Precision Mode For Slot.
+#define AM_REG_ADC_SL2CFG_PRMODE2_S                  16
+#define AM_REG_ADC_SL2CFG_PRMODE2_M                  0x00030000
+#define AM_REG_ADC_SL2CFG_PRMODE2(n)                 (((uint32_t)(n) << 16) & 0x00030000)
+#define AM_REG_ADC_SL2CFG_PRMODE2_P14B               0x00000000
+#define AM_REG_ADC_SL2CFG_PRMODE2_P12B               0x00010000
+#define AM_REG_ADC_SL2CFG_PRMODE2_P10B               0x00020000
+#define AM_REG_ADC_SL2CFG_PRMODE2_P8B                0x00030000
+
+// Select one of the 14 channel inputs for this slot.
+#define AM_REG_ADC_SL2CFG_CHSEL2_S                   8
+#define AM_REG_ADC_SL2CFG_CHSEL2_M                   0x00000F00
+#define AM_REG_ADC_SL2CFG_CHSEL2(n)                  (((uint32_t)(n) << 8) & 0x00000F00)
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE0                 0x00000000
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE1                 0x00000100
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE2                 0x00000200
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE3                 0x00000300
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE4                 0x00000400
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE5                 0x00000500
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE6                 0x00000600
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE7                 0x00000700
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE8                 0x00000800
+#define AM_REG_ADC_SL2CFG_CHSEL2_SE9                 0x00000900
+#define AM_REG_ADC_SL2CFG_CHSEL2_DF0                 0x00000A00
+#define AM_REG_ADC_SL2CFG_CHSEL2_DF1                 0x00000B00
+#define AM_REG_ADC_SL2CFG_CHSEL2_TEMP                0x00000C00
+#define AM_REG_ADC_SL2CFG_CHSEL2_BATT                0x00000D00
+#define AM_REG_ADC_SL2CFG_CHSEL2_VSS                 0x00000E00
+
+// This bit enables the window compare function for slot 2.
+#define AM_REG_ADC_SL2CFG_WCEN2_S                    1
+#define AM_REG_ADC_SL2CFG_WCEN2_M                    0x00000002
+#define AM_REG_ADC_SL2CFG_WCEN2(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_SL2CFG_WCEN2_WCEN                 0x00000002
+
+// This bit enables slot 2 for ADC conversions.
+#define AM_REG_ADC_SL2CFG_SLEN2_S                    0
+#define AM_REG_ADC_SL2CFG_SLEN2_M                    0x00000001
+#define AM_REG_ADC_SL2CFG_SLEN2(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_SL2CFG_SLEN2_SLEN                 0x00000001
+
+//*****************************************************************************
+//
+// ADC_SL3CFG - Slot 3 Configuration Register
+//
+//*****************************************************************************
+// Select the number of measurements to average in the accumulate divide module
+// for this slot.
+#define AM_REG_ADC_SL3CFG_ADSEL3_S                   24
+#define AM_REG_ADC_SL3CFG_ADSEL3_M                   0x07000000
+#define AM_REG_ADC_SL3CFG_ADSEL3(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_1_MSRMT         0x00000000
+#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS        0x01000000
+#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS        0x02000000
+#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_8_MSRMT         0x03000000
+#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS       0x04000000
+#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS       0x05000000
+#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS       0x06000000
+#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS      0x07000000
+
+// Set the Precision Mode For Slot.
+#define AM_REG_ADC_SL3CFG_PRMODE3_S                  16
+#define AM_REG_ADC_SL3CFG_PRMODE3_M                  0x00030000
+#define AM_REG_ADC_SL3CFG_PRMODE3(n)                 (((uint32_t)(n) << 16) & 0x00030000)
+#define AM_REG_ADC_SL3CFG_PRMODE3_P14B               0x00000000
+#define AM_REG_ADC_SL3CFG_PRMODE3_P12B               0x00010000
+#define AM_REG_ADC_SL3CFG_PRMODE3_P10B               0x00020000
+#define AM_REG_ADC_SL3CFG_PRMODE3_P8B                0x00030000
+
+// Select one of the 14 channel inputs for this slot.
+#define AM_REG_ADC_SL3CFG_CHSEL3_S                   8
+#define AM_REG_ADC_SL3CFG_CHSEL3_M                   0x00000F00
+#define AM_REG_ADC_SL3CFG_CHSEL3(n)                  (((uint32_t)(n) << 8) & 0x00000F00)
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE0                 0x00000000
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE1                 0x00000100
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE2                 0x00000200
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE3                 0x00000300
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE4                 0x00000400
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE5                 0x00000500
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE6                 0x00000600
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE7                 0x00000700
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE8                 0x00000800
+#define AM_REG_ADC_SL3CFG_CHSEL3_SE9                 0x00000900
+#define AM_REG_ADC_SL3CFG_CHSEL3_DF0                 0x00000A00
+#define AM_REG_ADC_SL3CFG_CHSEL3_DF1                 0x00000B00
+#define AM_REG_ADC_SL3CFG_CHSEL3_TEMP                0x00000C00
+#define AM_REG_ADC_SL3CFG_CHSEL3_BATT                0x00000D00
+#define AM_REG_ADC_SL3CFG_CHSEL3_VSS                 0x00000E00
+
+// This bit enables the window compare function for slot 3.
+#define AM_REG_ADC_SL3CFG_WCEN3_S                    1
+#define AM_REG_ADC_SL3CFG_WCEN3_M                    0x00000002
+#define AM_REG_ADC_SL3CFG_WCEN3(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_SL3CFG_WCEN3_WCEN                 0x00000002
+
+// This bit enables slot 3 for ADC conversions.
+#define AM_REG_ADC_SL3CFG_SLEN3_S                    0
+#define AM_REG_ADC_SL3CFG_SLEN3_M                    0x00000001
+#define AM_REG_ADC_SL3CFG_SLEN3(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_SL3CFG_SLEN3_SLEN                 0x00000001
+
+//*****************************************************************************
+//
+// ADC_SL4CFG - Slot 4 Configuration Register
+//
+//*****************************************************************************
+// Select the number of measurements to average in the accumulate divide module
+// for this slot.
+#define AM_REG_ADC_SL4CFG_ADSEL4_S                   24
+#define AM_REG_ADC_SL4CFG_ADSEL4_M                   0x07000000
+#define AM_REG_ADC_SL4CFG_ADSEL4(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_1_MSRMT         0x00000000
+#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS        0x01000000
+#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS        0x02000000
+#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_8_MSRMT         0x03000000
+#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS       0x04000000
+#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS       0x05000000
+#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS       0x06000000
+#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS      0x07000000
+
+// Set the Precision Mode For Slot.
+#define AM_REG_ADC_SL4CFG_PRMODE4_S                  16
+#define AM_REG_ADC_SL4CFG_PRMODE4_M                  0x00030000
+#define AM_REG_ADC_SL4CFG_PRMODE4(n)                 (((uint32_t)(n) << 16) & 0x00030000)
+#define AM_REG_ADC_SL4CFG_PRMODE4_P14B               0x00000000
+#define AM_REG_ADC_SL4CFG_PRMODE4_P12B               0x00010000
+#define AM_REG_ADC_SL4CFG_PRMODE4_P10B               0x00020000
+#define AM_REG_ADC_SL4CFG_PRMODE4_P8B                0x00030000
+
+// Select one of the 14 channel inputs for this slot.
+#define AM_REG_ADC_SL4CFG_CHSEL4_S                   8
+#define AM_REG_ADC_SL4CFG_CHSEL4_M                   0x00000F00
+#define AM_REG_ADC_SL4CFG_CHSEL4(n)                  (((uint32_t)(n) << 8) & 0x00000F00)
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE0                 0x00000000
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE1                 0x00000100
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE2                 0x00000200
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE3                 0x00000300
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE4                 0x00000400
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE5                 0x00000500
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE6                 0x00000600
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE7                 0x00000700
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE8                 0x00000800
+#define AM_REG_ADC_SL4CFG_CHSEL4_SE9                 0x00000900
+#define AM_REG_ADC_SL4CFG_CHSEL4_DF0                 0x00000A00
+#define AM_REG_ADC_SL4CFG_CHSEL4_DF1                 0x00000B00
+#define AM_REG_ADC_SL4CFG_CHSEL4_TEMP                0x00000C00
+#define AM_REG_ADC_SL4CFG_CHSEL4_BATT                0x00000D00
+#define AM_REG_ADC_SL4CFG_CHSEL4_VSS                 0x00000E00
+
+// This bit enables the window compare function for slot 4.
+#define AM_REG_ADC_SL4CFG_WCEN4_S                    1
+#define AM_REG_ADC_SL4CFG_WCEN4_M                    0x00000002
+#define AM_REG_ADC_SL4CFG_WCEN4(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_SL4CFG_WCEN4_WCEN                 0x00000002
+
+// This bit enables slot 4 for ADC conversions.
+#define AM_REG_ADC_SL4CFG_SLEN4_S                    0
+#define AM_REG_ADC_SL4CFG_SLEN4_M                    0x00000001
+#define AM_REG_ADC_SL4CFG_SLEN4(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_SL4CFG_SLEN4_SLEN                 0x00000001
+
+//*****************************************************************************
+//
+// ADC_SL5CFG - Slot 5 Configuration Register
+//
+//*****************************************************************************
+// Select number of measurements to average in the accumulate divide module for
+// this slot.
+#define AM_REG_ADC_SL5CFG_ADSEL5_S                   24
+#define AM_REG_ADC_SL5CFG_ADSEL5_M                   0x07000000
+#define AM_REG_ADC_SL5CFG_ADSEL5(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_1_MSRMT         0x00000000
+#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS        0x01000000
+#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS        0x02000000
+#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_8_MSRMT         0x03000000
+#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS       0x04000000
+#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS       0x05000000
+#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS       0x06000000
+#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS      0x07000000
+
+// Set the Precision Mode For Slot.
+#define AM_REG_ADC_SL5CFG_PRMODE5_S                  16
+#define AM_REG_ADC_SL5CFG_PRMODE5_M                  0x00030000
+#define AM_REG_ADC_SL5CFG_PRMODE5(n)                 (((uint32_t)(n) << 16) & 0x00030000)
+#define AM_REG_ADC_SL5CFG_PRMODE5_P14B               0x00000000
+#define AM_REG_ADC_SL5CFG_PRMODE5_P12B               0x00010000
+#define AM_REG_ADC_SL5CFG_PRMODE5_P10B               0x00020000
+#define AM_REG_ADC_SL5CFG_PRMODE5_P8B                0x00030000
+
+// Select one of the 14 channel inputs for this slot.
+#define AM_REG_ADC_SL5CFG_CHSEL5_S                   8
+#define AM_REG_ADC_SL5CFG_CHSEL5_M                   0x00000F00
+#define AM_REG_ADC_SL5CFG_CHSEL5(n)                  (((uint32_t)(n) << 8) & 0x00000F00)
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE0                 0x00000000
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE1                 0x00000100
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE2                 0x00000200
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE3                 0x00000300
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE4                 0x00000400
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE5                 0x00000500
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE6                 0x00000600
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE7                 0x00000700
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE8                 0x00000800
+#define AM_REG_ADC_SL5CFG_CHSEL5_SE9                 0x00000900
+#define AM_REG_ADC_SL5CFG_CHSEL5_DF0                 0x00000A00
+#define AM_REG_ADC_SL5CFG_CHSEL5_DF1                 0x00000B00
+#define AM_REG_ADC_SL5CFG_CHSEL5_TEMP                0x00000C00
+#define AM_REG_ADC_SL5CFG_CHSEL5_BATT                0x00000D00
+#define AM_REG_ADC_SL5CFG_CHSEL5_VSS                 0x00000E00
+
+// This bit enables the window compare function for slot 5.
+#define AM_REG_ADC_SL5CFG_WCEN5_S                    1
+#define AM_REG_ADC_SL5CFG_WCEN5_M                    0x00000002
+#define AM_REG_ADC_SL5CFG_WCEN5(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_SL5CFG_WCEN5_WCEN                 0x00000002
+
+// This bit enables slot 5 for ADC conversions.
+#define AM_REG_ADC_SL5CFG_SLEN5_S                    0
+#define AM_REG_ADC_SL5CFG_SLEN5_M                    0x00000001
+#define AM_REG_ADC_SL5CFG_SLEN5(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_SL5CFG_SLEN5_SLEN                 0x00000001
+
+//*****************************************************************************
+//
+// ADC_SL6CFG - Slot 6 Configuration Register
+//
+//*****************************************************************************
+// Select the number of measurements to average in the accumulate divide module
+// for this slot.
+#define AM_REG_ADC_SL6CFG_ADSEL6_S                   24
+#define AM_REG_ADC_SL6CFG_ADSEL6_M                   0x07000000
+#define AM_REG_ADC_SL6CFG_ADSEL6(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_1_MSRMT         0x00000000
+#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS        0x01000000
+#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS        0x02000000
+#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_8_MSRMT         0x03000000
+#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS       0x04000000
+#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS       0x05000000
+#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS       0x06000000
+#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS      0x07000000
+
+// Set the Precision Mode For Slot.
+#define AM_REG_ADC_SL6CFG_PRMODE6_S                  16
+#define AM_REG_ADC_SL6CFG_PRMODE6_M                  0x00030000
+#define AM_REG_ADC_SL6CFG_PRMODE6(n)                 (((uint32_t)(n) << 16) & 0x00030000)
+#define AM_REG_ADC_SL6CFG_PRMODE6_P14B               0x00000000
+#define AM_REG_ADC_SL6CFG_PRMODE6_P12B               0x00010000
+#define AM_REG_ADC_SL6CFG_PRMODE6_P10B               0x00020000
+#define AM_REG_ADC_SL6CFG_PRMODE6_P8B                0x00030000
+
+// Select one of the 14 channel inputs for this slot.
+#define AM_REG_ADC_SL6CFG_CHSEL6_S                   8
+#define AM_REG_ADC_SL6CFG_CHSEL6_M                   0x00000F00
+#define AM_REG_ADC_SL6CFG_CHSEL6(n)                  (((uint32_t)(n) << 8) & 0x00000F00)
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE0                 0x00000000
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE1                 0x00000100
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE2                 0x00000200
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE3                 0x00000300
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE4                 0x00000400
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE5                 0x00000500
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE6                 0x00000600
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE7                 0x00000700
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE8                 0x00000800
+#define AM_REG_ADC_SL6CFG_CHSEL6_SE9                 0x00000900
+#define AM_REG_ADC_SL6CFG_CHSEL6_DF0                 0x00000A00
+#define AM_REG_ADC_SL6CFG_CHSEL6_DF1                 0x00000B00
+#define AM_REG_ADC_SL6CFG_CHSEL6_TEMP                0x00000C00
+#define AM_REG_ADC_SL6CFG_CHSEL6_BATT                0x00000D00
+#define AM_REG_ADC_SL6CFG_CHSEL6_VSS                 0x00000E00
+
+// This bit enables the window compare function for slot 6.
+#define AM_REG_ADC_SL6CFG_WCEN6_S                    1
+#define AM_REG_ADC_SL6CFG_WCEN6_M                    0x00000002
+#define AM_REG_ADC_SL6CFG_WCEN6(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_SL6CFG_WCEN6_WCEN                 0x00000002
+
+// This bit enables slot 6 for ADC conversions.
+#define AM_REG_ADC_SL6CFG_SLEN6_S                    0
+#define AM_REG_ADC_SL6CFG_SLEN6_M                    0x00000001
+#define AM_REG_ADC_SL6CFG_SLEN6(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_SL6CFG_SLEN6_SLEN                 0x00000001
+
+//*****************************************************************************
+//
+// ADC_SL7CFG - Slot 7 Configuration Register
+//
+//*****************************************************************************
+// Select the number of measurements to average in the accumulate divide module
+// for this slot.
+#define AM_REG_ADC_SL7CFG_ADSEL7_S                   24
+#define AM_REG_ADC_SL7CFG_ADSEL7_M                   0x07000000
+#define AM_REG_ADC_SL7CFG_ADSEL7(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_1_MSRMT         0x00000000
+#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS        0x01000000
+#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS        0x02000000
+#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_8_MSRMT         0x03000000
+#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS       0x04000000
+#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS       0x05000000
+#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS       0x06000000
+#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS      0x07000000
+
+// Set the Precision Mode For Slot.
+#define AM_REG_ADC_SL7CFG_PRMODE7_S                  16
+#define AM_REG_ADC_SL7CFG_PRMODE7_M                  0x00030000
+#define AM_REG_ADC_SL7CFG_PRMODE7(n)                 (((uint32_t)(n) << 16) & 0x00030000)
+#define AM_REG_ADC_SL7CFG_PRMODE7_P14B               0x00000000
+#define AM_REG_ADC_SL7CFG_PRMODE7_P12B               0x00010000
+#define AM_REG_ADC_SL7CFG_PRMODE7_P10B               0x00020000
+#define AM_REG_ADC_SL7CFG_PRMODE7_P8B                0x00030000
+
+// Select one of the 14 channel inputs for this slot.
+#define AM_REG_ADC_SL7CFG_CHSEL7_S                   8
+#define AM_REG_ADC_SL7CFG_CHSEL7_M                   0x00000F00
+#define AM_REG_ADC_SL7CFG_CHSEL7(n)                  (((uint32_t)(n) << 8) & 0x00000F00)
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE0                 0x00000000
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE1                 0x00000100
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE2                 0x00000200
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE3                 0x00000300
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE4                 0x00000400
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE5                 0x00000500
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE6                 0x00000600
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE7                 0x00000700
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE8                 0x00000800
+#define AM_REG_ADC_SL7CFG_CHSEL7_SE9                 0x00000900
+#define AM_REG_ADC_SL7CFG_CHSEL7_DF0                 0x00000A00
+#define AM_REG_ADC_SL7CFG_CHSEL7_DF1                 0x00000B00
+#define AM_REG_ADC_SL7CFG_CHSEL7_TEMP                0x00000C00
+#define AM_REG_ADC_SL7CFG_CHSEL7_BATT                0x00000D00
+#define AM_REG_ADC_SL7CFG_CHSEL7_VSS                 0x00000E00
+
+// This bit enables the window compare function for slot 7.
+#define AM_REG_ADC_SL7CFG_WCEN7_S                    1
+#define AM_REG_ADC_SL7CFG_WCEN7_M                    0x00000002
+#define AM_REG_ADC_SL7CFG_WCEN7(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_ADC_SL7CFG_WCEN7_WCEN                 0x00000002
+
+// This bit enables slot 7 for ADC conversions.
+#define AM_REG_ADC_SL7CFG_SLEN7_S                    0
+#define AM_REG_ADC_SL7CFG_SLEN7_M                    0x00000001
+#define AM_REG_ADC_SL7CFG_SLEN7(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_ADC_SL7CFG_SLEN7_SLEN                 0x00000001
+
+//*****************************************************************************
+//
+// ADC_WULIM - Window Comparator Upper Limits Register
+//
+//*****************************************************************************
+// Sets the upper limit for the wondow comparator.
+#define AM_REG_ADC_WULIM_ULIM_S                      0
+#define AM_REG_ADC_WULIM_ULIM_M                      0x000FFFFF
+#define AM_REG_ADC_WULIM_ULIM(n)                     (((uint32_t)(n) << 0) & 0x000FFFFF)
+
+//*****************************************************************************
+//
+// ADC_WLLIM - Window Comparator Lower Limits Register
+//
+//*****************************************************************************
+// Sets the lower limit for the wondow comparator.
+#define AM_REG_ADC_WLLIM_LLIM_S                      0
+#define AM_REG_ADC_WLLIM_LLIM_M                      0x000FFFFF
+#define AM_REG_ADC_WLLIM_LLIM(n)                     (((uint32_t)(n) << 0) & 0x000FFFFF)
+
+//*****************************************************************************
+//
+// ADC_FIFO - FIFO Data and Valid Count Register
+//
+//*****************************************************************************
+// RESERVED.
+#define AM_REG_ADC_FIFO_RSVD_S                       31
+#define AM_REG_ADC_FIFO_RSVD_M                       0x80000000
+#define AM_REG_ADC_FIFO_RSVD(n)                      (((uint32_t)(n) << 31) & 0x80000000)
+
+// Slot number associated with this FIFO data.
+#define AM_REG_ADC_FIFO_SLOTNUM_S                    28
+#define AM_REG_ADC_FIFO_SLOTNUM_M                    0x70000000
+#define AM_REG_ADC_FIFO_SLOTNUM(n)                   (((uint32_t)(n) << 28) & 0x70000000)
+
+// Number of valid entries in the ADC FIFO.
+#define AM_REG_ADC_FIFO_COUNT_S                      20
+#define AM_REG_ADC_FIFO_COUNT_M                      0x0FF00000
+#define AM_REG_ADC_FIFO_COUNT(n)                     (((uint32_t)(n) << 20) & 0x0FF00000)
+
+// Oldest data in the FIFO.
+#define AM_REG_ADC_FIFO_DATA_S                       0
+#define AM_REG_ADC_FIFO_DATA_M                       0x000FFFFF
+#define AM_REG_ADC_FIFO_DATA(n)                      (((uint32_t)(n) << 0) & 0x000FFFFF)
+
+#endif // AM_REG_ADC_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h b/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h
new file mode 100644
index 0000000000..13a850d1c4
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h
@@ -0,0 +1,77 @@
+//*****************************************************************************
+//
+//! @file am_reg_base_addresses.h
+//!
+//! @brief Register defines for all module base addresses
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_BASE_ADDRESSES_H
+#define AM_REG_BASE_ADDRESSES_H
+
+#include "stdint.h"
+
+// ARM standard register space (needed for macros)
+#define REG_ITM_BASEADDR                         (0x00000000UL)
+#define REG_JEDEC_BASEADDR                       (0x00000000UL)
+#define REG_NVIC_BASEADDR                        (0x00000000UL)
+#define REG_SYSCTRL_BASEADDR                     (0x00000000UL)
+#define REG_SYSTICK_BASEADDR                     (0x00000000UL)
+#define REG_TPIU_BASEADDR                        (0x00000000UL)
+
+// Peripheral register space
+#define REG_ADC_BASEADDR                         (0x50010000UL)
+#define REG_CACHECTRL_BASEADDR                   (0x40018000UL)
+#define REG_CLKGEN_BASEADDR                      (0x40004000UL)
+#define REG_CTIMER_BASEADDR                      (0x40008000UL)
+#define REG_GPIO_BASEADDR                        (0x40010000UL)
+#define REG_IOMSTR_BASEADDR                      (0x50004000UL)
+#define REG_IOSLAVE_BASEADDR                     (0x50000000UL)
+#define REG_MCUCTRL_BASEADDR                     (0x40020000UL)
+#define REG_PDM_BASEADDR                         (0x50011000UL)
+#define REG_PWRCTRL_BASEADDR                     (0x40021000UL)
+#define REG_RSTGEN_BASEADDR                      (0x40000000UL)
+#define REG_RTC_BASEADDR                         (0x40004000UL)
+#define REG_UART_BASEADDR                        (0x4001C000UL)
+#define REG_VCOMP_BASEADDR                       (0x4000C000UL)
+#define REG_WDT_BASEADDR                         (0x40024000UL)
+
+// SRAM address space
+#define SRAM_BASEADDR                            (0x10000000UL)
+
+#endif // AM_REG_BASE_ADDRESSES_H
+
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h
new file mode 100644
index 0000000000..b933a08874
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h
@@ -0,0 +1,415 @@
+//*****************************************************************************
+//
+//  am_reg_cachectrl.h
+//! @file
+//!
+//! @brief Register macros for the CACHECTRL module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_CACHECTRL_H
+#define AM_REG_CACHECTRL_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_CACHECTRL_NUM_MODULES                 1
+#define AM_REG_CACHECTRLn(n) \
+    (REG_CACHECTRL_BASEADDR + 0x00001000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_CACHECTRL_CACHECFG_O                  0x00000000
+#define AM_REG_CACHECTRL_FLASHCFG_O                  0x00000004
+#define AM_REG_CACHECTRL_CACHECTRL_O                 0x00000008
+#define AM_REG_CACHECTRL_NCR0START_O                 0x00000010
+#define AM_REG_CACHECTRL_NCR0END_O                   0x00000014
+#define AM_REG_CACHECTRL_NCR1START_O                 0x00000018
+#define AM_REG_CACHECTRL_NCR1END_O                   0x0000001C
+#define AM_REG_CACHECTRL_CACHEMODE_O                 0x00000030
+#define AM_REG_CACHECTRL_DMON0_O                     0x00000040
+#define AM_REG_CACHECTRL_DMON1_O                     0x00000044
+#define AM_REG_CACHECTRL_DMON2_O                     0x00000048
+#define AM_REG_CACHECTRL_DMON3_O                     0x0000004C
+#define AM_REG_CACHECTRL_IMON0_O                     0x00000050
+#define AM_REG_CACHECTRL_IMON1_O                     0x00000054
+#define AM_REG_CACHECTRL_IMON2_O                     0x00000058
+#define AM_REG_CACHECTRL_IMON3_O                     0x0000005C
+
+//*****************************************************************************
+//
+// CACHECTRL_CACHECFG - Flash Cache Control Register
+//
+//*****************************************************************************
+// Enable Cache Monitoring Stats.  Only enable this for debug/performance
+// analysis since it will consume additional power.  See IMON/DMON registers for
+// data.
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_S   24
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M   0x01000000
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(n)  (((uint32_t)(n) << 24) & 0x01000000)
+
+// Enable clock gating of entire cache data array subsystem.  This should be
+// enabled for normal operation.
+#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_S     20
+#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M     0x00100000
+#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(n)    (((uint32_t)(n) << 20) & 0x00100000)
+
+// Unused.  Should be left at default value.
+#define AM_REG_CACHECTRL_CACHECFG_SMDLY_S            16
+#define AM_REG_CACHECTRL_CACHECFG_SMDLY_M            0x000F0000
+#define AM_REG_CACHECTRL_CACHECFG_SMDLY(n)           (((uint32_t)(n) << 16) & 0x000F0000)
+
+// Unused.  Should be left at default value.
+#define AM_REG_CACHECTRL_CACHECFG_DLY_S              12
+#define AM_REG_CACHECTRL_CACHECFG_DLY_M              0x0000F000
+#define AM_REG_CACHECTRL_CACHECFG_DLY(n)             (((uint32_t)(n) << 12) & 0x0000F000)
+
+// Enable LS (light sleep) of cache RAMs.  This should not be enabled for normal
+// operation.  When this bit is set, the cache's RAMS will be put into light
+// sleep mode while inactive.  NOTE:  if the cache is actively used, this may
+// have an adverse affect on power since entering/exiting LS mode may consume
+// more power than would be saved.
+#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_S         11
+#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M         0x00000800
+#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS(n)        (((uint32_t)(n) << 11) & 0x00000800)
+
+// Enable clock gating of individual cache RAMs.  This bit should be enabled for
+// normal operation for lowest power consumption.
+#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_S    10
+#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M    0x00000400
+#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE(n)   (((uint32_t)(n) << 10) & 0x00000400)
+
+// Enable Flash Data Caching.  When set to 1, all instruction accesses to flash
+// will be cached.
+#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_S    9
+#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M    0x00000200
+#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(n)   (((uint32_t)(n) << 9) & 0x00000200)
+
+// Enable Flash Instruction Caching.  When set to 1, all instruction accesses to
+// flash will be cached.
+#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_S    8
+#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M    0x00000100
+#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(n)   (((uint32_t)(n) << 8) & 0x00000100)
+
+// Bitfield should always be programmed to 0.
+#define AM_REG_CACHECTRL_CACHECFG_SERIAL_S           7
+#define AM_REG_CACHECTRL_CACHECFG_SERIAL_M           0x00000080
+#define AM_REG_CACHECTRL_CACHECFG_SERIAL(n)          (((uint32_t)(n) << 7) & 0x00000080)
+
+// Sets the cache configuration.  Only a single configuration of 0x5 is valid.
+#define AM_REG_CACHECTRL_CACHECFG_CONFIG_S           4
+#define AM_REG_CACHECTRL_CACHECFG_CONFIG_M           0x00000070
+#define AM_REG_CACHECTRL_CACHECFG_CONFIG(n)          (((uint32_t)(n) << 4) & 0x00000070)
+#define AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E 0x00000050
+
+// Enable Non-cacheable region 1.  See the NCR1 registers to set the region
+// boundaries and size.
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_S       3
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M       0x00000008
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1(n)      (((uint32_t)(n) << 3) & 0x00000008)
+
+// Enable Non-cacheable region 0.  See the NCR0 registers to set the region
+// boundaries and size.
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_S       2
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M       0x00000004
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0(n)      (((uint32_t)(n) << 2) & 0x00000004)
+
+// Sets the cache replacement policy.  0=LRR (least recently replaced), 1=LRU
+// (least recently used).  LRR minimizes writes to the TAG SRAM and is
+// recommended.
+#define AM_REG_CACHECTRL_CACHECFG_LRU_S              1
+#define AM_REG_CACHECTRL_CACHECFG_LRU_M              0x00000002
+#define AM_REG_CACHECTRL_CACHECFG_LRU(n)             (((uint32_t)(n) << 1) & 0x00000002)
+
+// Enables the main flash cache controller logic and enables power to the cache
+// RAMs.  Instruction and Data caching need to be enabled independently using
+// the ICACHE_ENABLE and DCACHE_ENABLE bits.
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_S           0
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE_M           0x00000001
+#define AM_REG_CACHECTRL_CACHECFG_ENABLE(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CACHECTRL_FLASHCFG - Flash Control Register
+//
+//*****************************************************************************
+// Sets read waitstates for flash accesses (in clock cycles).  This should be
+// left at the default value for normal flash operation.
+#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_S          0
+#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_M          0x00000007
+#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT(n)         (((uint32_t)(n) << 0) & 0x00000007)
+
+//*****************************************************************************
+//
+// CACHECTRL_CACHECTRL - Cache Control
+//
+//*****************************************************************************
+// Enable Flash Sleep Mode.  After writing this bit, the flash instance 1 will
+// enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash
+// access occurs.  Wake from SLM requires ~5us, so this should only be set if
+// the flash will not be accessed for reasonably long time.
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE_S 10
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE_M 0x00000400
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE(n) (((uint32_t)(n) << 10) & 0x00000400)
+
+// Disable Flash Sleep Mode.  Allows CPU to manually disable SLM mode.
+// Performing a flash read will also wake the array.
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE_S 9
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE_M 0x00000200
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE(n) (((uint32_t)(n) << 9) & 0x00000200)
+
+// Flash Sleep Mode Status.  When 1, flash instance 1 is asleep.
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_S 8
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_M 0x00000100
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS(n) (((uint32_t)(n) << 8) & 0x00000100)
+
+// Enable Flash Sleep Mode.  After writing this bit, the flash instance 0 will
+// enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash
+// access occurs.  Wake from SLM requires ~5us, so this should only be set if
+// the flash will not be accessed for reasonably long time.
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE_S 6
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE_M 0x00000040
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE(n) (((uint32_t)(n) << 6) & 0x00000040)
+
+// Disable Flash Sleep Mode.  Allows CPU to manually disable SLM mode.
+// Performing a flash read will also wake the array.
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE_S 5
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE_M 0x00000020
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE(n) (((uint32_t)(n) << 5) & 0x00000020)
+
+// Flash Sleep Mode Status.  When 1, flash instance 0 is asleep.
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_S 4
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_M 0x00000010
+#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS(n) (((uint32_t)(n) << 4) & 0x00000010)
+
+// Cache Ready Status.  A value of 1 indicates the cache is enabled and not
+// processing an invalidate operation.
+#define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY_S     2
+#define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY_M     0x00000004
+#define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY(n)    (((uint32_t)(n) << 2) & 0x00000004)
+
+// Writing a 1 to this bitfield will reset the cache monitor statistics
+// (DMON0-3, IMON0-3).  Statistic gathering can be paused/stopped by disabling
+// the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values
+// until the stats are reset by writing this bitfield.
+#define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_S      1
+#define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_M      0x00000002
+#define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT(n)     (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_CLEAR  0x00000002
+
+// Writing a 1 to this bitfield invalidates the flash cache contents.
+#define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_S      0
+#define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_M      0x00000001
+#define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE(n)     (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_GO     0x00000001
+
+//*****************************************************************************
+//
+// CACHECTRL_NCR0START - Flash Cache Noncachable Region 0 Start Address.
+//
+//*****************************************************************************
+// Start address for non-cacheable region 0.  The physical address of the start
+// of this region should be programmed to this register and must be aligned to a
+// 16-byte boundary (thus the lower 4 address bits are unused).
+#define AM_REG_CACHECTRL_NCR0START_ADDR_S            4
+#define AM_REG_CACHECTRL_NCR0START_ADDR_M            0x000FFFF0
+#define AM_REG_CACHECTRL_NCR0START_ADDR(n)           (((uint32_t)(n) << 4) & 0x000FFFF0)
+
+//*****************************************************************************
+//
+// CACHECTRL_NCR0END - Flash Cache Noncachable Region 0 End
+//
+//*****************************************************************************
+// End address for non-cacheable region 0.  The physical address of the end of
+// this region should be programmed to this register and must be aligned to a
+// 16-byte boundary (thus the lower 4 address bits are unused).
+#define AM_REG_CACHECTRL_NCR0END_ADDR_S              4
+#define AM_REG_CACHECTRL_NCR0END_ADDR_M              0x000FFFF0
+#define AM_REG_CACHECTRL_NCR0END_ADDR(n)             (((uint32_t)(n) << 4) & 0x000FFFF0)
+
+//*****************************************************************************
+//
+// CACHECTRL_NCR1START - Flash Cache Noncachable Region 1 Start
+//
+//*****************************************************************************
+// Start address for non-cacheable region 1.  The physical address of the start
+// of this region should be programmed to this register and must be aligned to a
+// 16-byte boundary (thus the lower 4 address bits are unused).
+#define AM_REG_CACHECTRL_NCR1START_ADDR_S            4
+#define AM_REG_CACHECTRL_NCR1START_ADDR_M            0x000FFFF0
+#define AM_REG_CACHECTRL_NCR1START_ADDR(n)           (((uint32_t)(n) << 4) & 0x000FFFF0)
+
+//*****************************************************************************
+//
+// CACHECTRL_NCR1END - Flash Cache Noncachable Region 1 End
+//
+//*****************************************************************************
+// End address for non-cacheable region 1.  The physical address of the end of
+// this region should be programmed to this register and must be aligned to a
+// 16-byte boundary (thus the lower 4 address bits are unused).
+#define AM_REG_CACHECTRL_NCR1END_ADDR_S              4
+#define AM_REG_CACHECTRL_NCR1END_ADDR_M              0x000FFFF0
+#define AM_REG_CACHECTRL_NCR1END_ADDR(n)             (((uint32_t)(n) << 4) & 0x000FFFF0)
+
+//*****************************************************************************
+//
+// CACHECTRL_CACHEMODE - Flash Cache Mode Register.  Used to trim
+// performance/power.
+//
+//*****************************************************************************
+// Disallow Simultaneous Data RAM reads (from 2 line hits on each bus).  Value
+// should be left at zero for optimal performance.
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_S       5
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_M       0x00000020
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6(n)      (((uint32_t)(n) << 5) & 0x00000020)
+
+// Disallow Data RAM reads (from line hits) during lookup read ops.  Value
+// should be left at zero for optimal performance.
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_S       4
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_M       0x00000010
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5(n)      (((uint32_t)(n) << 4) & 0x00000010)
+
+// Disallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should
+// be left at zero for optimal performance.
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_S       3
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_M       0x00000008
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4(n)      (((uint32_t)(n) << 3) & 0x00000008)
+
+// Disallow cache data RAM writes on data RAM read cycles. Value should be left
+// at zero for optimal performance.
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_S       2
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_M       0x00000004
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3(n)      (((uint32_t)(n) << 2) & 0x00000004)
+
+// Disallow cache data RAM writes on tag RAM read cycles. Value should be left
+// at zero for optimal performance.
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_S       1
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_M       0x00000002
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2(n)      (((uint32_t)(n) << 1) & 0x00000002)
+
+// Disallow cache data RAM writes on tag RAM fill cycles. Value should be left
+// at zero for optimal performance.
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_S       0
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_M       0x00000001
+#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1(n)      (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CACHECTRL_DMON0 - Data Cache Total Accesses
+//
+//*****************************************************************************
+// Total accesses to data cache
+#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_S       0
+#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_M       0xFFFFFFFF
+#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT(n)      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CACHECTRL_DMON1 - Data Cache Tag Lookups
+//
+//*****************************************************************************
+// Total tag lookups from data cache
+#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_S       0
+#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_M       0xFFFFFFFF
+#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT(n)      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CACHECTRL_DMON2 - Data Cache Hits
+//
+//*****************************************************************************
+// Cache hits from lookup operations
+#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_S          0
+#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_M          0xFFFFFFFF
+#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT(n)         (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CACHECTRL_DMON3 - Data Cache Line Hits
+//
+//*****************************************************************************
+// Cache hits from line cache
+#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_S         0
+#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_M         0xFFFFFFFF
+#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT(n)        (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CACHECTRL_IMON0 - Instruction Cache Total Accesses
+//
+//*****************************************************************************
+// Total accesses to Instruction cache
+#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_S       0
+#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_M       0xFFFFFFFF
+#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT(n)      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CACHECTRL_IMON1 - Instruction Cache Tag Lookups
+//
+//*****************************************************************************
+// Total tag lookups from Instruction cache
+#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_S       0
+#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_M       0xFFFFFFFF
+#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT(n)      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CACHECTRL_IMON2 - Instruction Cache Hits
+//
+//*****************************************************************************
+// Cache hits from lookup operations
+#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_S          0
+#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_M          0xFFFFFFFF
+#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT(n)         (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CACHECTRL_IMON3 - Instruction Cache Line Hits
+//
+//*****************************************************************************
+// Cache hits from line cache
+#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_S         0
+#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_M         0xFFFFFFFF
+#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT(n)        (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+#endif // AM_REG_CACHECTRL_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h b/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h
new file mode 100644
index 0000000000..c769673d65
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h
@@ -0,0 +1,501 @@
+//*****************************************************************************
+//
+//  am_reg_clkgen.h
+//! @file
+//!
+//! @brief Register macros for the CLKGEN module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_CLKGEN_H
+#define AM_REG_CLKGEN_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_CLKGEN_NUM_MODULES                    1
+#define AM_REG_CLKGENn(n) \
+    (REG_CLKGEN_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_CLKGEN_CALXT_O                        0x00000000
+#define AM_REG_CLKGEN_CALRC_O                        0x00000004
+#define AM_REG_CLKGEN_ACALCTR_O                      0x00000008
+#define AM_REG_CLKGEN_OCTRL_O                        0x0000000C
+#define AM_REG_CLKGEN_CLKOUT_O                       0x00000010
+#define AM_REG_CLKGEN_CCTRL_O                        0x00000018
+#define AM_REG_CLKGEN_STATUS_O                       0x0000001C
+#define AM_REG_CLKGEN_HFADJ_O                        0x00000020
+#define AM_REG_CLKGEN_HFVAL_O                        0x00000024
+#define AM_REG_CLKGEN_CLOCKEN_O                      0x00000028
+#define AM_REG_CLKGEN_CLOCKEN2_O                     0x0000002C
+#define AM_REG_CLKGEN_CLOCKEN3_O                     0x00000030
+#define AM_REG_CLKGEN_UARTEN_O                       0x00000034
+#define AM_REG_CLKGEN_CLKKEY_O                       0x00000014
+#define AM_REG_CLKGEN_INTEN_O                        0x00000100
+#define AM_REG_CLKGEN_INTSTAT_O                      0x00000104
+#define AM_REG_CLKGEN_INTCLR_O                       0x00000108
+#define AM_REG_CLKGEN_INTSET_O                       0x0000010C
+
+//*****************************************************************************
+//
+// Key values.
+//
+//*****************************************************************************
+#define AM_REG_CLKGEN_CLKKEY_KEYVAL                  0x00000047
+
+//*****************************************************************************
+//
+// CLKGEN_INTEN - CLKGEN Interrupt Register: Enable
+//
+//*****************************************************************************
+// RTC Alarm interrupt
+#define AM_REG_CLKGEN_INTEN_ALM_S                    3
+#define AM_REG_CLKGEN_INTEN_ALM_M                    0x00000008
+#define AM_REG_CLKGEN_INTEN_ALM(n)                   (((uint32_t)(n) << 3) & 0x00000008)
+
+// XT Oscillator Fail interrupt
+#define AM_REG_CLKGEN_INTEN_OF_S                     2
+#define AM_REG_CLKGEN_INTEN_OF_M                     0x00000004
+#define AM_REG_CLKGEN_INTEN_OF(n)                    (((uint32_t)(n) << 2) & 0x00000004)
+
+// Autocalibration Complete interrupt
+#define AM_REG_CLKGEN_INTEN_ACC_S                    1
+#define AM_REG_CLKGEN_INTEN_ACC_M                    0x00000002
+#define AM_REG_CLKGEN_INTEN_ACC(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+
+// Autocalibration Fail interrupt
+#define AM_REG_CLKGEN_INTEN_ACF_S                    0
+#define AM_REG_CLKGEN_INTEN_ACF_M                    0x00000001
+#define AM_REG_CLKGEN_INTEN_ACF(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CLKGEN_INTSTAT - CLKGEN Interrupt Register: Status
+//
+//*****************************************************************************
+// RTC Alarm interrupt
+#define AM_REG_CLKGEN_INTSTAT_ALM_S                  3
+#define AM_REG_CLKGEN_INTSTAT_ALM_M                  0x00000008
+#define AM_REG_CLKGEN_INTSTAT_ALM(n)                 (((uint32_t)(n) << 3) & 0x00000008)
+
+// XT Oscillator Fail interrupt
+#define AM_REG_CLKGEN_INTSTAT_OF_S                   2
+#define AM_REG_CLKGEN_INTSTAT_OF_M                   0x00000004
+#define AM_REG_CLKGEN_INTSTAT_OF(n)                  (((uint32_t)(n) << 2) & 0x00000004)
+
+// Autocalibration Complete interrupt
+#define AM_REG_CLKGEN_INTSTAT_ACC_S                  1
+#define AM_REG_CLKGEN_INTSTAT_ACC_M                  0x00000002
+#define AM_REG_CLKGEN_INTSTAT_ACC(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// Autocalibration Fail interrupt
+#define AM_REG_CLKGEN_INTSTAT_ACF_S                  0
+#define AM_REG_CLKGEN_INTSTAT_ACF_M                  0x00000001
+#define AM_REG_CLKGEN_INTSTAT_ACF(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CLKGEN_INTCLR - CLKGEN Interrupt Register: Clear
+//
+//*****************************************************************************
+// RTC Alarm interrupt
+#define AM_REG_CLKGEN_INTCLR_ALM_S                   3
+#define AM_REG_CLKGEN_INTCLR_ALM_M                   0x00000008
+#define AM_REG_CLKGEN_INTCLR_ALM(n)                  (((uint32_t)(n) << 3) & 0x00000008)
+
+// XT Oscillator Fail interrupt
+#define AM_REG_CLKGEN_INTCLR_OF_S                    2
+#define AM_REG_CLKGEN_INTCLR_OF_M                    0x00000004
+#define AM_REG_CLKGEN_INTCLR_OF(n)                   (((uint32_t)(n) << 2) & 0x00000004)
+
+// Autocalibration Complete interrupt
+#define AM_REG_CLKGEN_INTCLR_ACC_S                   1
+#define AM_REG_CLKGEN_INTCLR_ACC_M                   0x00000002
+#define AM_REG_CLKGEN_INTCLR_ACC(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+
+// Autocalibration Fail interrupt
+#define AM_REG_CLKGEN_INTCLR_ACF_S                   0
+#define AM_REG_CLKGEN_INTCLR_ACF_M                   0x00000001
+#define AM_REG_CLKGEN_INTCLR_ACF(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CLKGEN_INTSET - CLKGEN Interrupt Register: Set
+//
+//*****************************************************************************
+// RTC Alarm interrupt
+#define AM_REG_CLKGEN_INTSET_ALM_S                   3
+#define AM_REG_CLKGEN_INTSET_ALM_M                   0x00000008
+#define AM_REG_CLKGEN_INTSET_ALM(n)                  (((uint32_t)(n) << 3) & 0x00000008)
+
+// XT Oscillator Fail interrupt
+#define AM_REG_CLKGEN_INTSET_OF_S                    2
+#define AM_REG_CLKGEN_INTSET_OF_M                    0x00000004
+#define AM_REG_CLKGEN_INTSET_OF(n)                   (((uint32_t)(n) << 2) & 0x00000004)
+
+// Autocalibration Complete interrupt
+#define AM_REG_CLKGEN_INTSET_ACC_S                   1
+#define AM_REG_CLKGEN_INTSET_ACC_M                   0x00000002
+#define AM_REG_CLKGEN_INTSET_ACC(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+
+// Autocalibration Fail interrupt
+#define AM_REG_CLKGEN_INTSET_ACF_S                   0
+#define AM_REG_CLKGEN_INTSET_ACF_M                   0x00000001
+#define AM_REG_CLKGEN_INTSET_ACF(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CLKGEN_CALXT - XT Oscillator Control
+//
+//*****************************************************************************
+// XT Oscillator calibration value
+#define AM_REG_CLKGEN_CALXT_CALXT_S                  0
+#define AM_REG_CLKGEN_CALXT_CALXT_M                  0x000007FF
+#define AM_REG_CLKGEN_CALXT_CALXT(n)                 (((uint32_t)(n) << 0) & 0x000007FF)
+
+//*****************************************************************************
+//
+// CLKGEN_CALRC - RC Oscillator Control
+//
+//*****************************************************************************
+// LFRC Oscillator calibration value
+#define AM_REG_CLKGEN_CALRC_CALRC_S                  0
+#define AM_REG_CLKGEN_CALRC_CALRC_M                  0x0003FFFF
+#define AM_REG_CLKGEN_CALRC_CALRC(n)                 (((uint32_t)(n) << 0) & 0x0003FFFF)
+
+//*****************************************************************************
+//
+// CLKGEN_ACALCTR - Autocalibration Counter
+//
+//*****************************************************************************
+// Autocalibration Counter result.
+#define AM_REG_CLKGEN_ACALCTR_ACALCTR_S              0
+#define AM_REG_CLKGEN_ACALCTR_ACALCTR_M              0x00FFFFFF
+#define AM_REG_CLKGEN_ACALCTR_ACALCTR(n)             (((uint32_t)(n) << 0) & 0x00FFFFFF)
+
+//*****************************************************************************
+//
+// CLKGEN_OCTRL - Oscillator Control
+//
+//*****************************************************************************
+// Autocalibration control
+#define AM_REG_CLKGEN_OCTRL_ACAL_S                   8
+#define AM_REG_CLKGEN_OCTRL_ACAL_M                   0x00000700
+#define AM_REG_CLKGEN_OCTRL_ACAL(n)                  (((uint32_t)(n) << 8) & 0x00000700)
+#define AM_REG_CLKGEN_OCTRL_ACAL_DIS                 0x00000000
+#define AM_REG_CLKGEN_OCTRL_ACAL_1024SEC             0x00000200
+#define AM_REG_CLKGEN_OCTRL_ACAL_512SEC              0x00000300
+#define AM_REG_CLKGEN_OCTRL_ACAL_XTFREQ              0x00000600
+#define AM_REG_CLKGEN_OCTRL_ACAL_EXTFREQ             0x00000700
+
+// Selects the RTC oscillator (1 => LFRC, 0 => XT)
+#define AM_REG_CLKGEN_OCTRL_OSEL_S                   7
+#define AM_REG_CLKGEN_OCTRL_OSEL_M                   0x00000080
+#define AM_REG_CLKGEN_OCTRL_OSEL(n)                  (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_CLKGEN_OCTRL_OSEL_RTC_XT              0x00000000
+#define AM_REG_CLKGEN_OCTRL_OSEL_RTC_LFRC            0x00000080
+
+// Oscillator switch on failure function
+#define AM_REG_CLKGEN_OCTRL_FOS_S                    6
+#define AM_REG_CLKGEN_OCTRL_FOS_M                    0x00000040
+#define AM_REG_CLKGEN_OCTRL_FOS(n)                   (((uint32_t)(n) << 6) & 0x00000040)
+#define AM_REG_CLKGEN_OCTRL_FOS_DIS                  0x00000000
+#define AM_REG_CLKGEN_OCTRL_FOS_EN                   0x00000040
+
+// Stop the LFRC Oscillator to the RTC
+#define AM_REG_CLKGEN_OCTRL_STOPRC_S                 1
+#define AM_REG_CLKGEN_OCTRL_STOPRC_M                 0x00000002
+#define AM_REG_CLKGEN_OCTRL_STOPRC(n)                (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_CLKGEN_OCTRL_STOPRC_EN                0x00000000
+#define AM_REG_CLKGEN_OCTRL_STOPRC_STOP              0x00000002
+
+// Stop the XT Oscillator to the RTC
+#define AM_REG_CLKGEN_OCTRL_STOPXT_S                 0
+#define AM_REG_CLKGEN_OCTRL_STOPXT_M                 0x00000001
+#define AM_REG_CLKGEN_OCTRL_STOPXT(n)                (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CLKGEN_OCTRL_STOPXT_EN                0x00000000
+#define AM_REG_CLKGEN_OCTRL_STOPXT_STOP              0x00000001
+
+//*****************************************************************************
+//
+// CLKGEN_CLKOUT - CLKOUT Frequency Select
+//
+//*****************************************************************************
+// Enable the CLKOUT signal
+#define AM_REG_CLKGEN_CLKOUT_CKEN_S                  7
+#define AM_REG_CLKGEN_CLKOUT_CKEN_M                  0x00000080
+#define AM_REG_CLKGEN_CLKOUT_CKEN(n)                 (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_CLKGEN_CLKOUT_CKEN_DIS                0x00000000
+#define AM_REG_CLKGEN_CLKOUT_CKEN_EN                 0x00000080
+
+// CLKOUT signal select.  Note that HIGH_DRIVE should be selected if any high
+// frequencies (such as from HFRC) are selected for CLKOUT.
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_S                 0
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_M                 0x0000003F
+#define AM_REG_CLKGEN_CLKOUT_CKSEL(n)                (((uint32_t)(n) << 0) & 0x0000003F)
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC              0x00000000
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2           0x00000001
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4           0x00000002
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8           0x00000003
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16          0x00000004
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32          0x00000005
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_1Hz           0x00000010
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M          0x00000016
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT                0x00000017
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz          0x00000018
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC              0x00000019
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4         0x0000001A
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8         0x0000001B
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16        0x0000001C
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64        0x0000001D
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128       0x0000001E
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256       0x0000001F
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV512       0x00000020
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK         0x00000022
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2         0x00000023
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32        0x00000024
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512       0x00000025
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K       0x00000026
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256         0x00000027
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K          0x00000028
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K         0x00000029
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16       0x0000002A
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128      0x0000002B
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz         0x0000002C
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K       0x0000002D
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M       0x0000002E
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K       0x0000002F
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M       0x00000030
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M        0x00000031
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE            0x00000032
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8       0x00000033
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE              0x00000035
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16        0x00000036
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32      0x00000037
+#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE            0x00000039
+
+//*****************************************************************************
+//
+// CLKGEN_CCTRL - HFRC Clock Control
+//
+//*****************************************************************************
+// Core Clock divisor
+#define AM_REG_CLKGEN_CCTRL_CORESEL_S                0
+#define AM_REG_CLKGEN_CCTRL_CORESEL_M                0x00000001
+#define AM_REG_CLKGEN_CCTRL_CORESEL(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC             0x00000000
+#define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2        0x00000001
+
+//*****************************************************************************
+//
+// CLKGEN_STATUS - Clock Generator Status
+//
+//*****************************************************************************
+// XT Oscillator is enabled but not oscillating
+#define AM_REG_CLKGEN_STATUS_OSCF_S                  1
+#define AM_REG_CLKGEN_STATUS_OSCF_M                  0x00000002
+#define AM_REG_CLKGEN_STATUS_OSCF(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// Current RTC oscillator (1 => LFRC, 0 => XT)
+#define AM_REG_CLKGEN_STATUS_OMODE_S                 0
+#define AM_REG_CLKGEN_STATUS_OMODE_M                 0x00000001
+#define AM_REG_CLKGEN_STATUS_OMODE(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CLKGEN_HFADJ - HFRC Adjustment
+//
+//*****************************************************************************
+// Gain control for HFRC adjustment
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_S             21
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_M             0x00E00000
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN(n)            (((uint32_t)(n) << 21) & 0x00E00000)
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1     0x00000000
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2 0x00200000
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_4 0x00400000
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_8 0x00600000
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_16 0x00800000
+#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_32 0x00A00000
+
+// XT warmup period for HFRC adjustment
+#define AM_REG_CLKGEN_HFADJ_HFWARMUP_S               20
+#define AM_REG_CLKGEN_HFADJ_HFWARMUP_M               0x00100000
+#define AM_REG_CLKGEN_HFADJ_HFWARMUP(n)              (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC            0x00000000
+#define AM_REG_CLKGEN_HFADJ_HFWARMUP_2SEC            0x00100000
+
+// Target HFRC adjustment value.
+#define AM_REG_CLKGEN_HFADJ_HFXTADJ_S                8
+#define AM_REG_CLKGEN_HFADJ_HFXTADJ_M                0x000FFF00
+#define AM_REG_CLKGEN_HFADJ_HFXTADJ(n)               (((uint32_t)(n) << 8) & 0x000FFF00)
+
+// Repeat period for HFRC adjustment
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_S                1
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_M                0x0000000E
+#define AM_REG_CLKGEN_HFADJ_HFADJCK(n)               (((uint32_t)(n) << 1) & 0x0000000E)
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC             0x00000000
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_16SEC            0x00000002
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_32SEC            0x00000004
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_64SEC            0x00000006
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_128SEC           0x00000008
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_256SEC           0x0000000A
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_512SEC           0x0000000C
+#define AM_REG_CLKGEN_HFADJ_HFADJCK_1024SEC          0x0000000E
+
+// HFRC adjustment control
+#define AM_REG_CLKGEN_HFADJ_HFADJEN_S                0
+#define AM_REG_CLKGEN_HFADJ_HFADJEN_M                0x00000001
+#define AM_REG_CLKGEN_HFADJ_HFADJEN(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CLKGEN_HFADJ_HFADJEN_DIS              0x00000000
+#define AM_REG_CLKGEN_HFADJ_HFADJEN_EN               0x00000001
+
+//*****************************************************************************
+//
+// CLKGEN_HFVAL - HFADJ readback
+//
+//*****************************************************************************
+// Current HFTUNE value
+#define AM_REG_CLKGEN_HFVAL_HFTUNERB_S               0
+#define AM_REG_CLKGEN_HFVAL_HFTUNERB_M               0x000007FF
+#define AM_REG_CLKGEN_HFVAL_HFTUNERB(n)              (((uint32_t)(n) << 0) & 0x000007FF)
+
+//*****************************************************************************
+//
+// CLKGEN_CLOCKEN - Clock Enable Status
+//
+//*****************************************************************************
+// Clock enable status
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_S              0
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_M              0xFFFFFFFF
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN(n)             (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_ADC_CLKEN      0x00000001
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER_CLKEN   0x00000002
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0A_CLKEN 0x00000004
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0B_CLKEN 0x00000008
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1A_CLKEN 0x00000010
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1B_CLKEN 0x00000020
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2A_CLKEN 0x00000040
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2B_CLKEN 0x00000080
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3A_CLKEN 0x00000100
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3B_CLKEN 0x00000200
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR0_CLKEN  0x00000400
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR1_CLKEN  0x00000800
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR2_CLKEN  0x00001000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR3_CLKEN  0x00002000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR4_CLKEN  0x00004000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR5_CLKEN  0x00008000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC0_CLKEN 0x00010000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC1_CLKEN 0x00020000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC2_CLKEN 0x00040000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC3_CLKEN 0x00080000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC4_CLKEN 0x00100000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC5_CLKEN 0x00200000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOSLAVE_CLKEN  0x00400000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDM_CLKEN      0x00800000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDMIFC_CLKEN   0x01000000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_RSTGEN_CLKEN   0x02000000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_SRAM_WIPE_CLKEN 0x04000000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CLKEN   0x08000000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CNT_CLKEN 0x10000000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_TPIU_CLKEN     0x20000000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0_HCLK_CLKEN 0x40000000
+#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0HF_CLKEN  0x80000000
+
+//*****************************************************************************
+//
+// CLKGEN_CLOCKEN2 - Clock Enable Status
+//
+//*****************************************************************************
+// Clock enable status 2
+#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_S            0
+#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_M            0xFFFFFFFF
+#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2(n)           (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1_HCLK_CLKEN 0x00000001
+#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1HF_CLKEN 0x00000002
+#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_WDT_CLKEN    0x00000004
+#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_XT_32KHz_EN  0x40000000
+#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_FRCHFRC      0x80000000
+
+//*****************************************************************************
+//
+// CLKGEN_CLOCKEN3 - Clock Enable Status
+//
+//*****************************************************************************
+// Clock enable status 3
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_S            0
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_M            0xFFFFFFFF
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3(n)           (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_xtal_en 0x01000000
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_hfrc_en 0x02000000
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFADJEN      0x04000000
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_en_out  0x08000000
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_RTC_SOURCE   0x10000000
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_XTAL_EN      0x20000000
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_EN      0x40000000
+#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_FLASHCLK_EN  0x80000000
+
+//*****************************************************************************
+//
+// CLKGEN_UARTEN - UART Enable
+//
+//*****************************************************************************
+// UART1 system clock control
+#define AM_REG_CLKGEN_UARTEN_UART1EN_S               8
+#define AM_REG_CLKGEN_UARTEN_UART1EN_M               0x00000300
+#define AM_REG_CLKGEN_UARTEN_UART1EN(n)              (((uint32_t)(n) << 8) & 0x00000300)
+#define AM_REG_CLKGEN_UARTEN_UART1EN_DIS             0x00000000
+#define AM_REG_CLKGEN_UARTEN_UART1EN_EN              0x00000100
+#define AM_REG_CLKGEN_UARTEN_UART1EN_REDUCE_FREQ     0x00000200
+#define AM_REG_CLKGEN_UARTEN_UART1EN_EN_POWER_SAV    0x00000300
+
+// UART0 system clock control
+#define AM_REG_CLKGEN_UARTEN_UART0EN_S               0
+#define AM_REG_CLKGEN_UARTEN_UART0EN_M               0x00000003
+#define AM_REG_CLKGEN_UARTEN_UART0EN(n)              (((uint32_t)(n) << 0) & 0x00000003)
+#define AM_REG_CLKGEN_UARTEN_UART0EN_DIS             0x00000000
+#define AM_REG_CLKGEN_UARTEN_UART0EN_EN              0x00000001
+#define AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ     0x00000002
+#define AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV    0x00000003
+
+#endif // AM_REG_CLKGEN_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h b/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h
new file mode 100644
index 0000000000..278849a74d
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h
@@ -0,0 +1,1915 @@
+//*****************************************************************************
+//
+//  am_reg_ctimer.h
+//! @file
+//!
+//! @brief Register macros for the CTIMER module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_CTIMER_H
+#define AM_REG_CTIMER_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_CTIMER_NUM_MODULES                    1
+#define AM_REG_CTIMERn(n) \
+    (REG_CTIMER_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_CTIMER_TMR0_O                         0x00000000
+#define AM_REG_CTIMER_CMPRA0_O                       0x00000004
+#define AM_REG_CTIMER_CMPRB0_O                       0x00000008
+#define AM_REG_CTIMER_CTRL0_O                        0x0000000C
+#define AM_REG_CTIMER_TMR1_O                         0x00000010
+#define AM_REG_CTIMER_CMPRA1_O                       0x00000014
+#define AM_REG_CTIMER_CMPRB1_O                       0x00000018
+#define AM_REG_CTIMER_CTRL1_O                        0x0000001C
+#define AM_REG_CTIMER_TMR2_O                         0x00000020
+#define AM_REG_CTIMER_CMPRA2_O                       0x00000024
+#define AM_REG_CTIMER_CMPRB2_O                       0x00000028
+#define AM_REG_CTIMER_CTRL2_O                        0x0000002C
+#define AM_REG_CTIMER_TMR3_O                         0x00000030
+#define AM_REG_CTIMER_CMPRA3_O                       0x00000034
+#define AM_REG_CTIMER_CMPRB3_O                       0x00000038
+#define AM_REG_CTIMER_CTRL3_O                        0x0000003C
+#define AM_REG_CTIMER_STCFG_O                        0x00000100
+#define AM_REG_CTIMER_STTMR_O                        0x00000104
+#define AM_REG_CTIMER_CAPTURE_CONTROL_O              0x00000108
+#define AM_REG_CTIMER_SCMPR0_O                       0x00000110
+#define AM_REG_CTIMER_SCMPR1_O                       0x00000114
+#define AM_REG_CTIMER_SCMPR2_O                       0x00000118
+#define AM_REG_CTIMER_SCMPR3_O                       0x0000011C
+#define AM_REG_CTIMER_SCMPR4_O                       0x00000120
+#define AM_REG_CTIMER_SCMPR5_O                       0x00000124
+#define AM_REG_CTIMER_SCMPR6_O                       0x00000128
+#define AM_REG_CTIMER_SCMPR7_O                       0x0000012C
+#define AM_REG_CTIMER_SCAPT0_O                       0x000001E0
+#define AM_REG_CTIMER_SCAPT1_O                       0x000001E4
+#define AM_REG_CTIMER_SCAPT2_O                       0x000001E8
+#define AM_REG_CTIMER_SCAPT3_O                       0x000001EC
+#define AM_REG_CTIMER_SNVR0_O                        0x000001F0
+#define AM_REG_CTIMER_SNVR1_O                        0x000001F4
+#define AM_REG_CTIMER_SNVR2_O                        0x000001F8
+#define AM_REG_CTIMER_INTEN_O                        0x00000200
+#define AM_REG_CTIMER_INTSTAT_O                      0x00000204
+#define AM_REG_CTIMER_INTCLR_O                       0x00000208
+#define AM_REG_CTIMER_INTSET_O                       0x0000020C
+#define AM_REG_CTIMER_STMINTEN_O                     0x00000300
+#define AM_REG_CTIMER_STMINTSTAT_O                   0x00000304
+#define AM_REG_CTIMER_STMINTCLR_O                    0x00000308
+#define AM_REG_CTIMER_STMINTSET_O                    0x0000030C
+
+//*****************************************************************************
+//
+// CTIMER_INTEN - Counter/Timer Interrupts: Enable
+//
+//*****************************************************************************
+// Counter/Timer B3 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTEN_CTMRB3C1INT_S            15
+#define AM_REG_CTIMER_INTEN_CTMRB3C1INT_M            0x00008000
+#define AM_REG_CTIMER_INTEN_CTMRB3C1INT(n)           (((uint32_t)(n) << 15) & 0x00008000)
+
+// Counter/Timer A3 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTEN_CTMRA3C1INT_S            14
+#define AM_REG_CTIMER_INTEN_CTMRA3C1INT_M            0x00004000
+#define AM_REG_CTIMER_INTEN_CTMRA3C1INT(n)           (((uint32_t)(n) << 14) & 0x00004000)
+
+// Counter/Timer B2 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTEN_CTMRB2C1INT_S            13
+#define AM_REG_CTIMER_INTEN_CTMRB2C1INT_M            0x00002000
+#define AM_REG_CTIMER_INTEN_CTMRB2C1INT(n)           (((uint32_t)(n) << 13) & 0x00002000)
+
+// Counter/Timer A2 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTEN_CTMRA2C1INT_S            12
+#define AM_REG_CTIMER_INTEN_CTMRA2C1INT_M            0x00001000
+#define AM_REG_CTIMER_INTEN_CTMRA2C1INT(n)           (((uint32_t)(n) << 12) & 0x00001000)
+
+// Counter/Timer B1 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTEN_CTMRB1C1INT_S            11
+#define AM_REG_CTIMER_INTEN_CTMRB1C1INT_M            0x00000800
+#define AM_REG_CTIMER_INTEN_CTMRB1C1INT(n)           (((uint32_t)(n) << 11) & 0x00000800)
+
+// Counter/Timer A1 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTEN_CTMRA1C1INT_S            10
+#define AM_REG_CTIMER_INTEN_CTMRA1C1INT_M            0x00000400
+#define AM_REG_CTIMER_INTEN_CTMRA1C1INT(n)           (((uint32_t)(n) << 10) & 0x00000400)
+
+// Counter/Timer B0 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTEN_CTMRB0C1INT_S            9
+#define AM_REG_CTIMER_INTEN_CTMRB0C1INT_M            0x00000200
+#define AM_REG_CTIMER_INTEN_CTMRB0C1INT(n)           (((uint32_t)(n) << 9) & 0x00000200)
+
+// Counter/Timer A0 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTEN_CTMRA0C1INT_S            8
+#define AM_REG_CTIMER_INTEN_CTMRA0C1INT_M            0x00000100
+#define AM_REG_CTIMER_INTEN_CTMRA0C1INT(n)           (((uint32_t)(n) << 8) & 0x00000100)
+
+// Counter/Timer B3 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTEN_CTMRB3C0INT_S            7
+#define AM_REG_CTIMER_INTEN_CTMRB3C0INT_M            0x00000080
+#define AM_REG_CTIMER_INTEN_CTMRB3C0INT(n)           (((uint32_t)(n) << 7) & 0x00000080)
+
+// Counter/Timer A3 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTEN_CTMRA3C0INT_S            6
+#define AM_REG_CTIMER_INTEN_CTMRA3C0INT_M            0x00000040
+#define AM_REG_CTIMER_INTEN_CTMRA3C0INT(n)           (((uint32_t)(n) << 6) & 0x00000040)
+
+// Counter/Timer B2 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTEN_CTMRB2C0INT_S            5
+#define AM_REG_CTIMER_INTEN_CTMRB2C0INT_M            0x00000020
+#define AM_REG_CTIMER_INTEN_CTMRB2C0INT(n)           (((uint32_t)(n) << 5) & 0x00000020)
+
+// Counter/Timer A2 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTEN_CTMRA2C0INT_S            4
+#define AM_REG_CTIMER_INTEN_CTMRA2C0INT_M            0x00000010
+#define AM_REG_CTIMER_INTEN_CTMRA2C0INT(n)           (((uint32_t)(n) << 4) & 0x00000010)
+
+// Counter/Timer B1 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTEN_CTMRB1C0INT_S            3
+#define AM_REG_CTIMER_INTEN_CTMRB1C0INT_M            0x00000008
+#define AM_REG_CTIMER_INTEN_CTMRB1C0INT(n)           (((uint32_t)(n) << 3) & 0x00000008)
+
+// Counter/Timer A1 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTEN_CTMRA1C0INT_S            2
+#define AM_REG_CTIMER_INTEN_CTMRA1C0INT_M            0x00000004
+#define AM_REG_CTIMER_INTEN_CTMRA1C0INT(n)           (((uint32_t)(n) << 2) & 0x00000004)
+
+// Counter/Timer B0 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTEN_CTMRB0C0INT_S            1
+#define AM_REG_CTIMER_INTEN_CTMRB0C0INT_M            0x00000002
+#define AM_REG_CTIMER_INTEN_CTMRB0C0INT(n)           (((uint32_t)(n) << 1) & 0x00000002)
+
+// Counter/Timer A0 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTEN_CTMRA0C0INT_S            0
+#define AM_REG_CTIMER_INTEN_CTMRA0C0INT_M            0x00000001
+#define AM_REG_CTIMER_INTEN_CTMRA0C0INT(n)           (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CTIMER_INTSTAT - Counter/Timer Interrupts: Status
+//
+//*****************************************************************************
+// Counter/Timer B3 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT_S          15
+#define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT_M          0x00008000
+#define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT(n)         (((uint32_t)(n) << 15) & 0x00008000)
+
+// Counter/Timer A3 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT_S          14
+#define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT_M          0x00004000
+#define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT(n)         (((uint32_t)(n) << 14) & 0x00004000)
+
+// Counter/Timer B2 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT_S          13
+#define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT_M          0x00002000
+#define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT(n)         (((uint32_t)(n) << 13) & 0x00002000)
+
+// Counter/Timer A2 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT_S          12
+#define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT_M          0x00001000
+#define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT(n)         (((uint32_t)(n) << 12) & 0x00001000)
+
+// Counter/Timer B1 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT_S          11
+#define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT_M          0x00000800
+#define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT(n)         (((uint32_t)(n) << 11) & 0x00000800)
+
+// Counter/Timer A1 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT_S          10
+#define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT_M          0x00000400
+#define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT(n)         (((uint32_t)(n) << 10) & 0x00000400)
+
+// Counter/Timer B0 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT_S          9
+#define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT_M          0x00000200
+#define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT(n)         (((uint32_t)(n) << 9) & 0x00000200)
+
+// Counter/Timer A0 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT_S          8
+#define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT_M          0x00000100
+#define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT(n)         (((uint32_t)(n) << 8) & 0x00000100)
+
+// Counter/Timer B3 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT_S          7
+#define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT_M          0x00000080
+#define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT(n)         (((uint32_t)(n) << 7) & 0x00000080)
+
+// Counter/Timer A3 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT_S          6
+#define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT_M          0x00000040
+#define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT(n)         (((uint32_t)(n) << 6) & 0x00000040)
+
+// Counter/Timer B2 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT_S          5
+#define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT_M          0x00000020
+#define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT(n)         (((uint32_t)(n) << 5) & 0x00000020)
+
+// Counter/Timer A2 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT_S          4
+#define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT_M          0x00000010
+#define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT(n)         (((uint32_t)(n) << 4) & 0x00000010)
+
+// Counter/Timer B1 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT_S          3
+#define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT_M          0x00000008
+#define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT(n)         (((uint32_t)(n) << 3) & 0x00000008)
+
+// Counter/Timer A1 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT_S          2
+#define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT_M          0x00000004
+#define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT(n)         (((uint32_t)(n) << 2) & 0x00000004)
+
+// Counter/Timer B0 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT_S          1
+#define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT_M          0x00000002
+#define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT(n)         (((uint32_t)(n) << 1) & 0x00000002)
+
+// Counter/Timer A0 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT_S          0
+#define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT_M          0x00000001
+#define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT(n)         (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CTIMER_INTCLR - Counter/Timer Interrupts: Clear
+//
+//*****************************************************************************
+// Counter/Timer B3 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTCLR_CTMRB3C1INT_S           15
+#define AM_REG_CTIMER_INTCLR_CTMRB3C1INT_M           0x00008000
+#define AM_REG_CTIMER_INTCLR_CTMRB3C1INT(n)          (((uint32_t)(n) << 15) & 0x00008000)
+
+// Counter/Timer A3 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTCLR_CTMRA3C1INT_S           14
+#define AM_REG_CTIMER_INTCLR_CTMRA3C1INT_M           0x00004000
+#define AM_REG_CTIMER_INTCLR_CTMRA3C1INT(n)          (((uint32_t)(n) << 14) & 0x00004000)
+
+// Counter/Timer B2 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTCLR_CTMRB2C1INT_S           13
+#define AM_REG_CTIMER_INTCLR_CTMRB2C1INT_M           0x00002000
+#define AM_REG_CTIMER_INTCLR_CTMRB2C1INT(n)          (((uint32_t)(n) << 13) & 0x00002000)
+
+// Counter/Timer A2 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTCLR_CTMRA2C1INT_S           12
+#define AM_REG_CTIMER_INTCLR_CTMRA2C1INT_M           0x00001000
+#define AM_REG_CTIMER_INTCLR_CTMRA2C1INT(n)          (((uint32_t)(n) << 12) & 0x00001000)
+
+// Counter/Timer B1 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTCLR_CTMRB1C1INT_S           11
+#define AM_REG_CTIMER_INTCLR_CTMRB1C1INT_M           0x00000800
+#define AM_REG_CTIMER_INTCLR_CTMRB1C1INT(n)          (((uint32_t)(n) << 11) & 0x00000800)
+
+// Counter/Timer A1 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTCLR_CTMRA1C1INT_S           10
+#define AM_REG_CTIMER_INTCLR_CTMRA1C1INT_M           0x00000400
+#define AM_REG_CTIMER_INTCLR_CTMRA1C1INT(n)          (((uint32_t)(n) << 10) & 0x00000400)
+
+// Counter/Timer B0 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTCLR_CTMRB0C1INT_S           9
+#define AM_REG_CTIMER_INTCLR_CTMRB0C1INT_M           0x00000200
+#define AM_REG_CTIMER_INTCLR_CTMRB0C1INT(n)          (((uint32_t)(n) << 9) & 0x00000200)
+
+// Counter/Timer A0 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTCLR_CTMRA0C1INT_S           8
+#define AM_REG_CTIMER_INTCLR_CTMRA0C1INT_M           0x00000100
+#define AM_REG_CTIMER_INTCLR_CTMRA0C1INT(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Counter/Timer B3 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTCLR_CTMRB3C0INT_S           7
+#define AM_REG_CTIMER_INTCLR_CTMRB3C0INT_M           0x00000080
+#define AM_REG_CTIMER_INTCLR_CTMRB3C0INT(n)          (((uint32_t)(n) << 7) & 0x00000080)
+
+// Counter/Timer A3 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTCLR_CTMRA3C0INT_S           6
+#define AM_REG_CTIMER_INTCLR_CTMRA3C0INT_M           0x00000040
+#define AM_REG_CTIMER_INTCLR_CTMRA3C0INT(n)          (((uint32_t)(n) << 6) & 0x00000040)
+
+// Counter/Timer B2 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTCLR_CTMRB2C0INT_S           5
+#define AM_REG_CTIMER_INTCLR_CTMRB2C0INT_M           0x00000020
+#define AM_REG_CTIMER_INTCLR_CTMRB2C0INT(n)          (((uint32_t)(n) << 5) & 0x00000020)
+
+// Counter/Timer A2 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTCLR_CTMRA2C0INT_S           4
+#define AM_REG_CTIMER_INTCLR_CTMRA2C0INT_M           0x00000010
+#define AM_REG_CTIMER_INTCLR_CTMRA2C0INT(n)          (((uint32_t)(n) << 4) & 0x00000010)
+
+// Counter/Timer B1 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTCLR_CTMRB1C0INT_S           3
+#define AM_REG_CTIMER_INTCLR_CTMRB1C0INT_M           0x00000008
+#define AM_REG_CTIMER_INTCLR_CTMRB1C0INT(n)          (((uint32_t)(n) << 3) & 0x00000008)
+
+// Counter/Timer A1 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTCLR_CTMRA1C0INT_S           2
+#define AM_REG_CTIMER_INTCLR_CTMRA1C0INT_M           0x00000004
+#define AM_REG_CTIMER_INTCLR_CTMRA1C0INT(n)          (((uint32_t)(n) << 2) & 0x00000004)
+
+// Counter/Timer B0 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTCLR_CTMRB0C0INT_S           1
+#define AM_REG_CTIMER_INTCLR_CTMRB0C0INT_M           0x00000002
+#define AM_REG_CTIMER_INTCLR_CTMRB0C0INT(n)          (((uint32_t)(n) << 1) & 0x00000002)
+
+// Counter/Timer A0 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTCLR_CTMRA0C0INT_S           0
+#define AM_REG_CTIMER_INTCLR_CTMRA0C0INT_M           0x00000001
+#define AM_REG_CTIMER_INTCLR_CTMRA0C0INT(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CTIMER_INTSET - Counter/Timer Interrupts: Set
+//
+//*****************************************************************************
+// Counter/Timer B3 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSET_CTMRB3C1INT_S           15
+#define AM_REG_CTIMER_INTSET_CTMRB3C1INT_M           0x00008000
+#define AM_REG_CTIMER_INTSET_CTMRB3C1INT(n)          (((uint32_t)(n) << 15) & 0x00008000)
+
+// Counter/Timer A3 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSET_CTMRA3C1INT_S           14
+#define AM_REG_CTIMER_INTSET_CTMRA3C1INT_M           0x00004000
+#define AM_REG_CTIMER_INTSET_CTMRA3C1INT(n)          (((uint32_t)(n) << 14) & 0x00004000)
+
+// Counter/Timer B2 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSET_CTMRB2C1INT_S           13
+#define AM_REG_CTIMER_INTSET_CTMRB2C1INT_M           0x00002000
+#define AM_REG_CTIMER_INTSET_CTMRB2C1INT(n)          (((uint32_t)(n) << 13) & 0x00002000)
+
+// Counter/Timer A2 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSET_CTMRA2C1INT_S           12
+#define AM_REG_CTIMER_INTSET_CTMRA2C1INT_M           0x00001000
+#define AM_REG_CTIMER_INTSET_CTMRA2C1INT(n)          (((uint32_t)(n) << 12) & 0x00001000)
+
+// Counter/Timer B1 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSET_CTMRB1C1INT_S           11
+#define AM_REG_CTIMER_INTSET_CTMRB1C1INT_M           0x00000800
+#define AM_REG_CTIMER_INTSET_CTMRB1C1INT(n)          (((uint32_t)(n) << 11) & 0x00000800)
+
+// Counter/Timer A1 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSET_CTMRA1C1INT_S           10
+#define AM_REG_CTIMER_INTSET_CTMRA1C1INT_M           0x00000400
+#define AM_REG_CTIMER_INTSET_CTMRA1C1INT(n)          (((uint32_t)(n) << 10) & 0x00000400)
+
+// Counter/Timer B0 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSET_CTMRB0C1INT_S           9
+#define AM_REG_CTIMER_INTSET_CTMRB0C1INT_M           0x00000200
+#define AM_REG_CTIMER_INTSET_CTMRB0C1INT(n)          (((uint32_t)(n) << 9) & 0x00000200)
+
+// Counter/Timer A0 interrupt based on COMPR1.
+#define AM_REG_CTIMER_INTSET_CTMRA0C1INT_S           8
+#define AM_REG_CTIMER_INTSET_CTMRA0C1INT_M           0x00000100
+#define AM_REG_CTIMER_INTSET_CTMRA0C1INT(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Counter/Timer B3 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSET_CTMRB3C0INT_S           7
+#define AM_REG_CTIMER_INTSET_CTMRB3C0INT_M           0x00000080
+#define AM_REG_CTIMER_INTSET_CTMRB3C0INT(n)          (((uint32_t)(n) << 7) & 0x00000080)
+
+// Counter/Timer A3 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSET_CTMRA3C0INT_S           6
+#define AM_REG_CTIMER_INTSET_CTMRA3C0INT_M           0x00000040
+#define AM_REG_CTIMER_INTSET_CTMRA3C0INT(n)          (((uint32_t)(n) << 6) & 0x00000040)
+
+// Counter/Timer B2 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSET_CTMRB2C0INT_S           5
+#define AM_REG_CTIMER_INTSET_CTMRB2C0INT_M           0x00000020
+#define AM_REG_CTIMER_INTSET_CTMRB2C0INT(n)          (((uint32_t)(n) << 5) & 0x00000020)
+
+// Counter/Timer A2 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSET_CTMRA2C0INT_S           4
+#define AM_REG_CTIMER_INTSET_CTMRA2C0INT_M           0x00000010
+#define AM_REG_CTIMER_INTSET_CTMRA2C0INT(n)          (((uint32_t)(n) << 4) & 0x00000010)
+
+// Counter/Timer B1 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSET_CTMRB1C0INT_S           3
+#define AM_REG_CTIMER_INTSET_CTMRB1C0INT_M           0x00000008
+#define AM_REG_CTIMER_INTSET_CTMRB1C0INT(n)          (((uint32_t)(n) << 3) & 0x00000008)
+
+// Counter/Timer A1 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSET_CTMRA1C0INT_S           2
+#define AM_REG_CTIMER_INTSET_CTMRA1C0INT_M           0x00000004
+#define AM_REG_CTIMER_INTSET_CTMRA1C0INT(n)          (((uint32_t)(n) << 2) & 0x00000004)
+
+// Counter/Timer B0 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSET_CTMRB0C0INT_S           1
+#define AM_REG_CTIMER_INTSET_CTMRB0C0INT_M           0x00000002
+#define AM_REG_CTIMER_INTSET_CTMRB0C0INT(n)          (((uint32_t)(n) << 1) & 0x00000002)
+
+// Counter/Timer A0 interrupt based on COMPR0.
+#define AM_REG_CTIMER_INTSET_CTMRA0C0INT_S           0
+#define AM_REG_CTIMER_INTSET_CTMRA0C0INT_M           0x00000001
+#define AM_REG_CTIMER_INTSET_CTMRA0C0INT(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// CTIMER_STMINTEN - STIMER Interrupt registers: Enable
+//
+//*****************************************************************************
+// CAPTURE register D has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTEN_CAPTURED_S            12
+#define AM_REG_CTIMER_STMINTEN_CAPTURED_M            0x00001000
+#define AM_REG_CTIMER_STMINTEN_CAPTURED(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_STMINTEN_CAPTURED_CAPD_INT     0x00001000
+
+// CAPTURE register C has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTEN_CAPTUREC_S            11
+#define AM_REG_CTIMER_STMINTEN_CAPTUREC_M            0x00000800
+#define AM_REG_CTIMER_STMINTEN_CAPTUREC(n)           (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_STMINTEN_CAPTUREC_CAPC_INT     0x00000800
+
+// CAPTURE register B has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTEN_CAPTUREB_S            10
+#define AM_REG_CTIMER_STMINTEN_CAPTUREB_M            0x00000400
+#define AM_REG_CTIMER_STMINTEN_CAPTUREB(n)           (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_STMINTEN_CAPTUREB_CAPB_INT     0x00000400
+
+// CAPTURE register A has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTEN_CAPTUREA_S            9
+#define AM_REG_CTIMER_STMINTEN_CAPTUREA_M            0x00000200
+#define AM_REG_CTIMER_STMINTEN_CAPTUREA(n)           (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_STMINTEN_CAPTUREA_CAPA_INT     0x00000200
+
+// COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
+#define AM_REG_CTIMER_STMINTEN_OVERFLOW_S            8
+#define AM_REG_CTIMER_STMINTEN_OVERFLOW_M            0x00000100
+#define AM_REG_CTIMER_STMINTEN_OVERFLOW(n)           (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_CTIMER_STMINTEN_OVERFLOW_OFLOW_INT    0x00000100
+
+// COUNTER is greater than or equal to COMPARE register H.
+#define AM_REG_CTIMER_STMINTEN_COMPAREH_S            7
+#define AM_REG_CTIMER_STMINTEN_COMPAREH_M            0x00000080
+#define AM_REG_CTIMER_STMINTEN_COMPAREH(n)           (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_CTIMER_STMINTEN_COMPAREH_COMPARED     0x00000080
+
+// COUNTER is greater than or equal to COMPARE register G.
+#define AM_REG_CTIMER_STMINTEN_COMPAREG_S            6
+#define AM_REG_CTIMER_STMINTEN_COMPAREG_M            0x00000040
+#define AM_REG_CTIMER_STMINTEN_COMPAREG(n)           (((uint32_t)(n) << 6) & 0x00000040)
+#define AM_REG_CTIMER_STMINTEN_COMPAREG_COMPARED     0x00000040
+
+// COUNTER is greater than or equal to COMPARE register F.
+#define AM_REG_CTIMER_STMINTEN_COMPAREF_S            5
+#define AM_REG_CTIMER_STMINTEN_COMPAREF_M            0x00000020
+#define AM_REG_CTIMER_STMINTEN_COMPAREF(n)           (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_CTIMER_STMINTEN_COMPAREF_COMPARED     0x00000020
+
+// COUNTER is greater than or equal to COMPARE register E.
+#define AM_REG_CTIMER_STMINTEN_COMPAREE_S            4
+#define AM_REG_CTIMER_STMINTEN_COMPAREE_M            0x00000010
+#define AM_REG_CTIMER_STMINTEN_COMPAREE(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_CTIMER_STMINTEN_COMPAREE_COMPARED     0x00000010
+
+// COUNTER is greater than or equal to COMPARE register D.
+#define AM_REG_CTIMER_STMINTEN_COMPARED_S            3
+#define AM_REG_CTIMER_STMINTEN_COMPARED_M            0x00000008
+#define AM_REG_CTIMER_STMINTEN_COMPARED(n)           (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_CTIMER_STMINTEN_COMPARED_COMPARED     0x00000008
+
+// COUNTER is greater than or equal to COMPARE register C.
+#define AM_REG_CTIMER_STMINTEN_COMPAREC_S            2
+#define AM_REG_CTIMER_STMINTEN_COMPAREC_M            0x00000004
+#define AM_REG_CTIMER_STMINTEN_COMPAREC(n)           (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_CTIMER_STMINTEN_COMPAREC_COMPARED     0x00000004
+
+// COUNTER is greater than or equal to COMPARE register B.
+#define AM_REG_CTIMER_STMINTEN_COMPAREB_S            1
+#define AM_REG_CTIMER_STMINTEN_COMPAREB_M            0x00000002
+#define AM_REG_CTIMER_STMINTEN_COMPAREB(n)           (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_CTIMER_STMINTEN_COMPAREB_COMPARED     0x00000002
+
+// COUNTER is greater than or equal to COMPARE register A.
+#define AM_REG_CTIMER_STMINTEN_COMPAREA_S            0
+#define AM_REG_CTIMER_STMINTEN_COMPAREA_M            0x00000001
+#define AM_REG_CTIMER_STMINTEN_COMPAREA(n)           (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_STMINTEN_COMPAREA_COMPARED     0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_STMINTSTAT - STIMER Interrupt registers: Status
+//
+//*****************************************************************************
+// CAPTURE register D has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTSTAT_CAPTURED_S          12
+#define AM_REG_CTIMER_STMINTSTAT_CAPTURED_M          0x00001000
+#define AM_REG_CTIMER_STMINTSTAT_CAPTURED(n)         (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_STMINTSTAT_CAPTURED_CAPD_INT   0x00001000
+
+// CAPTURE register C has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_S          11
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_M          0x00000800
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREC(n)         (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT   0x00000800
+
+// CAPTURE register B has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_S          10
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_M          0x00000400
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREB(n)         (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT   0x00000400
+
+// CAPTURE register A has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_S          9
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_M          0x00000200
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREA(n)         (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT   0x00000200
+
+// COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
+#define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_S          8
+#define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_M          0x00000100
+#define AM_REG_CTIMER_STMINTSTAT_OVERFLOW(n)         (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT  0x00000100
+
+// COUNTER is greater than or equal to COMPARE register H.
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREH_S          7
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREH_M          0x00000080
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREH(n)         (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREH_COMPARED   0x00000080
+
+// COUNTER is greater than or equal to COMPARE register G.
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREG_S          6
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREG_M          0x00000040
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREG(n)         (((uint32_t)(n) << 6) & 0x00000040)
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREG_COMPARED   0x00000040
+
+// COUNTER is greater than or equal to COMPARE register F.
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREF_S          5
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREF_M          0x00000020
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREF(n)         (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREF_COMPARED   0x00000020
+
+// COUNTER is greater than or equal to COMPARE register E.
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREE_S          4
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREE_M          0x00000010
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREE(n)         (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREE_COMPARED   0x00000010
+
+// COUNTER is greater than or equal to COMPARE register D.
+#define AM_REG_CTIMER_STMINTSTAT_COMPARED_S          3
+#define AM_REG_CTIMER_STMINTSTAT_COMPARED_M          0x00000008
+#define AM_REG_CTIMER_STMINTSTAT_COMPARED(n)         (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_CTIMER_STMINTSTAT_COMPARED_COMPARED   0x00000008
+
+// COUNTER is greater than or equal to COMPARE register C.
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREC_S          2
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREC_M          0x00000004
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREC(n)         (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREC_COMPARED   0x00000004
+
+// COUNTER is greater than or equal to COMPARE register B.
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREB_S          1
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREB_M          0x00000002
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREB(n)         (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREB_COMPARED   0x00000002
+
+// COUNTER is greater than or equal to COMPARE register A.
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREA_S          0
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREA_M          0x00000001
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREA(n)         (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_STMINTSTAT_COMPAREA_COMPARED   0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_STMINTCLR - STIMER Interrupt registers: Clear
+//
+//*****************************************************************************
+// CAPTURE register D has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTCLR_CAPTURED_S           12
+#define AM_REG_CTIMER_STMINTCLR_CAPTURED_M           0x00001000
+#define AM_REG_CTIMER_STMINTCLR_CAPTURED(n)          (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_STMINTCLR_CAPTURED_CAPD_INT    0x00001000
+
+// CAPTURE register C has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREC_S           11
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREC_M           0x00000800
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREC(n)          (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREC_CAPC_INT    0x00000800
+
+// CAPTURE register B has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREB_S           10
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREB_M           0x00000400
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREB(n)          (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREB_CAPB_INT    0x00000400
+
+// CAPTURE register A has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREA_S           9
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREA_M           0x00000200
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREA(n)          (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_STMINTCLR_CAPTUREA_CAPA_INT    0x00000200
+
+// COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
+#define AM_REG_CTIMER_STMINTCLR_OVERFLOW_S           8
+#define AM_REG_CTIMER_STMINTCLR_OVERFLOW_M           0x00000100
+#define AM_REG_CTIMER_STMINTCLR_OVERFLOW(n)          (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT   0x00000100
+
+// COUNTER is greater than or equal to COMPARE register H.
+#define AM_REG_CTIMER_STMINTCLR_COMPAREH_S           7
+#define AM_REG_CTIMER_STMINTCLR_COMPAREH_M           0x00000080
+#define AM_REG_CTIMER_STMINTCLR_COMPAREH(n)          (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_CTIMER_STMINTCLR_COMPAREH_COMPARED    0x00000080
+
+// COUNTER is greater than or equal to COMPARE register G.
+#define AM_REG_CTIMER_STMINTCLR_COMPAREG_S           6
+#define AM_REG_CTIMER_STMINTCLR_COMPAREG_M           0x00000040
+#define AM_REG_CTIMER_STMINTCLR_COMPAREG(n)          (((uint32_t)(n) << 6) & 0x00000040)
+#define AM_REG_CTIMER_STMINTCLR_COMPAREG_COMPARED    0x00000040
+
+// COUNTER is greater than or equal to COMPARE register F.
+#define AM_REG_CTIMER_STMINTCLR_COMPAREF_S           5
+#define AM_REG_CTIMER_STMINTCLR_COMPAREF_M           0x00000020
+#define AM_REG_CTIMER_STMINTCLR_COMPAREF(n)          (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_CTIMER_STMINTCLR_COMPAREF_COMPARED    0x00000020
+
+// COUNTER is greater than or equal to COMPARE register E.
+#define AM_REG_CTIMER_STMINTCLR_COMPAREE_S           4
+#define AM_REG_CTIMER_STMINTCLR_COMPAREE_M           0x00000010
+#define AM_REG_CTIMER_STMINTCLR_COMPAREE(n)          (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_CTIMER_STMINTCLR_COMPAREE_COMPARED    0x00000010
+
+// COUNTER is greater than or equal to COMPARE register D.
+#define AM_REG_CTIMER_STMINTCLR_COMPARED_S           3
+#define AM_REG_CTIMER_STMINTCLR_COMPARED_M           0x00000008
+#define AM_REG_CTIMER_STMINTCLR_COMPARED(n)          (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_CTIMER_STMINTCLR_COMPARED_COMPARED    0x00000008
+
+// COUNTER is greater than or equal to COMPARE register C.
+#define AM_REG_CTIMER_STMINTCLR_COMPAREC_S           2
+#define AM_REG_CTIMER_STMINTCLR_COMPAREC_M           0x00000004
+#define AM_REG_CTIMER_STMINTCLR_COMPAREC(n)          (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_CTIMER_STMINTCLR_COMPAREC_COMPARED    0x00000004
+
+// COUNTER is greater than or equal to COMPARE register B.
+#define AM_REG_CTIMER_STMINTCLR_COMPAREB_S           1
+#define AM_REG_CTIMER_STMINTCLR_COMPAREB_M           0x00000002
+#define AM_REG_CTIMER_STMINTCLR_COMPAREB(n)          (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_CTIMER_STMINTCLR_COMPAREB_COMPARED    0x00000002
+
+// COUNTER is greater than or equal to COMPARE register A.
+#define AM_REG_CTIMER_STMINTCLR_COMPAREA_S           0
+#define AM_REG_CTIMER_STMINTCLR_COMPAREA_M           0x00000001
+#define AM_REG_CTIMER_STMINTCLR_COMPAREA(n)          (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_STMINTCLR_COMPAREA_COMPARED    0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_STMINTSET - STIMER Interrupt registers: Set
+//
+//*****************************************************************************
+// CAPTURE register D has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTSET_CAPTURED_S           12
+#define AM_REG_CTIMER_STMINTSET_CAPTURED_M           0x00001000
+#define AM_REG_CTIMER_STMINTSET_CAPTURED(n)          (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_STMINTSET_CAPTURED_CAPD_INT    0x00001000
+
+// CAPTURE register C has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTSET_CAPTUREC_S           11
+#define AM_REG_CTIMER_STMINTSET_CAPTUREC_M           0x00000800
+#define AM_REG_CTIMER_STMINTSET_CAPTUREC(n)          (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_STMINTSET_CAPTUREC_CAPC_INT    0x00000800
+
+// CAPTURE register B has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTSET_CAPTUREB_S           10
+#define AM_REG_CTIMER_STMINTSET_CAPTUREB_M           0x00000400
+#define AM_REG_CTIMER_STMINTSET_CAPTUREB(n)          (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_STMINTSET_CAPTUREB_CAPB_INT    0x00000400
+
+// CAPTURE register A has grabbed the value in the counter
+#define AM_REG_CTIMER_STMINTSET_CAPTUREA_S           9
+#define AM_REG_CTIMER_STMINTSET_CAPTUREA_M           0x00000200
+#define AM_REG_CTIMER_STMINTSET_CAPTUREA(n)          (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_STMINTSET_CAPTUREA_CAPA_INT    0x00000200
+
+// COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
+#define AM_REG_CTIMER_STMINTSET_OVERFLOW_S           8
+#define AM_REG_CTIMER_STMINTSET_OVERFLOW_M           0x00000100
+#define AM_REG_CTIMER_STMINTSET_OVERFLOW(n)          (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_CTIMER_STMINTSET_OVERFLOW_OFLOW_INT   0x00000100
+
+// COUNTER is greater than or equal to COMPARE register H.
+#define AM_REG_CTIMER_STMINTSET_COMPAREH_S           7
+#define AM_REG_CTIMER_STMINTSET_COMPAREH_M           0x00000080
+#define AM_REG_CTIMER_STMINTSET_COMPAREH(n)          (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_CTIMER_STMINTSET_COMPAREH_COMPARED    0x00000080
+
+// COUNTER is greater than or equal to COMPARE register G.
+#define AM_REG_CTIMER_STMINTSET_COMPAREG_S           6
+#define AM_REG_CTIMER_STMINTSET_COMPAREG_M           0x00000040
+#define AM_REG_CTIMER_STMINTSET_COMPAREG(n)          (((uint32_t)(n) << 6) & 0x00000040)
+#define AM_REG_CTIMER_STMINTSET_COMPAREG_COMPARED    0x00000040
+
+// COUNTER is greater than or equal to COMPARE register F.
+#define AM_REG_CTIMER_STMINTSET_COMPAREF_S           5
+#define AM_REG_CTIMER_STMINTSET_COMPAREF_M           0x00000020
+#define AM_REG_CTIMER_STMINTSET_COMPAREF(n)          (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_CTIMER_STMINTSET_COMPAREF_COMPARED    0x00000020
+
+// COUNTER is greater than or equal to COMPARE register E.
+#define AM_REG_CTIMER_STMINTSET_COMPAREE_S           4
+#define AM_REG_CTIMER_STMINTSET_COMPAREE_M           0x00000010
+#define AM_REG_CTIMER_STMINTSET_COMPAREE(n)          (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_CTIMER_STMINTSET_COMPAREE_COMPARED    0x00000010
+
+// COUNTER is greater than or equal to COMPARE register D.
+#define AM_REG_CTIMER_STMINTSET_COMPARED_S           3
+#define AM_REG_CTIMER_STMINTSET_COMPARED_M           0x00000008
+#define AM_REG_CTIMER_STMINTSET_COMPARED(n)          (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_CTIMER_STMINTSET_COMPARED_COMPARED    0x00000008
+
+// COUNTER is greater than or equal to COMPARE register C.
+#define AM_REG_CTIMER_STMINTSET_COMPAREC_S           2
+#define AM_REG_CTIMER_STMINTSET_COMPAREC_M           0x00000004
+#define AM_REG_CTIMER_STMINTSET_COMPAREC(n)          (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_CTIMER_STMINTSET_COMPAREC_COMPARED    0x00000004
+
+// COUNTER is greater than or equal to COMPARE register B.
+#define AM_REG_CTIMER_STMINTSET_COMPAREB_S           1
+#define AM_REG_CTIMER_STMINTSET_COMPAREB_M           0x00000002
+#define AM_REG_CTIMER_STMINTSET_COMPAREB(n)          (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_CTIMER_STMINTSET_COMPAREB_COMPARED    0x00000002
+
+// COUNTER is greater than or equal to COMPARE register A.
+#define AM_REG_CTIMER_STMINTSET_COMPAREA_S           0
+#define AM_REG_CTIMER_STMINTSET_COMPAREA_M           0x00000001
+#define AM_REG_CTIMER_STMINTSET_COMPAREA(n)          (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_STMINTSET_COMPAREA_COMPARED    0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_TMR0 - Counter/Timer Register
+//
+//*****************************************************************************
+// Counter/Timer B0.
+#define AM_REG_CTIMER_TMR0_CTTMRB0_S                 16
+#define AM_REG_CTIMER_TMR0_CTTMRB0_M                 0xFFFF0000
+#define AM_REG_CTIMER_TMR0_CTTMRB0(n)                (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer A0.
+#define AM_REG_CTIMER_TMR0_CTTMRA0_S                 0
+#define AM_REG_CTIMER_TMR0_CTTMRA0_M                 0x0000FFFF
+#define AM_REG_CTIMER_TMR0_CTTMRA0(n)                (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CMPRA0 - Counter/Timer A0 Compare Registers
+//
+//*****************************************************************************
+// Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.
+#define AM_REG_CTIMER_CMPRA0_CMPR1A0_S               16
+#define AM_REG_CTIMER_CMPRA0_CMPR1A0_M               0xFFFF0000
+#define AM_REG_CTIMER_CMPRA0_CMPR1A0(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.
+#define AM_REG_CTIMER_CMPRA0_CMPR0A0_S               0
+#define AM_REG_CTIMER_CMPRA0_CMPR0A0_M               0x0000FFFF
+#define AM_REG_CTIMER_CMPRA0_CMPR0A0(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CMPRB0 - Counter/Timer B0 Compare Registers
+//
+//*****************************************************************************
+// Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.
+#define AM_REG_CTIMER_CMPRB0_CMPR1B0_S               16
+#define AM_REG_CTIMER_CMPRB0_CMPR1B0_M               0xFFFF0000
+#define AM_REG_CTIMER_CMPRB0_CMPR1B0(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.
+#define AM_REG_CTIMER_CMPRB0_CMPR0B0_S               0
+#define AM_REG_CTIMER_CMPRB0_CMPR0B0_M               0x0000FFFF
+#define AM_REG_CTIMER_CMPRB0_CMPR0B0(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CTRL0 - Counter/Timer Control
+//
+//*****************************************************************************
+// Counter/Timer A0/B0 Link bit.
+#define AM_REG_CTIMER_CTRL0_CTLINK0_S                31
+#define AM_REG_CTIMER_CTRL0_CTLINK0_M                0x80000000
+#define AM_REG_CTIMER_CTRL0_CTLINK0(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS 0x00000000
+#define AM_REG_CTIMER_CTRL0_CTLINK0_32BIT_TIMER      0x80000000
+
+// Counter/Timer B0 Output Enable bit.
+#define AM_REG_CTIMER_CTRL0_TMRB0PE_S                29
+#define AM_REG_CTIMER_CTRL0_TMRB0PE_M                0x20000000
+#define AM_REG_CTIMER_CTRL0_TMRB0PE(n)               (((uint32_t)(n) << 29) & 0x20000000)
+#define AM_REG_CTIMER_CTRL0_TMRB0PE_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRB0PE_EN               0x20000000
+
+// Counter/Timer B0 output polarity.
+#define AM_REG_CTIMER_CTRL0_TMRB0POL_S               28
+#define AM_REG_CTIMER_CTRL0_TMRB0POL_M               0x10000000
+#define AM_REG_CTIMER_CTRL0_TMRB0POL(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_CTIMER_CTRL0_TMRB0POL_NORMAL          0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRB0POL_INVERTED        0x10000000
+
+// Counter/Timer B0 Clear bit.
+#define AM_REG_CTIMER_CTRL0_TMRB0CLR_S               27
+#define AM_REG_CTIMER_CTRL0_TMRB0CLR_M               0x08000000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLR(n)              (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_CTIMER_CTRL0_TMRB0CLR_RUN             0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLR_CLEAR           0x08000000
+
+// Counter/Timer B0 Interrupt Enable bit for COMPR1.
+#define AM_REG_CTIMER_CTRL0_TMRB0IE1_S               26
+#define AM_REG_CTIMER_CTRL0_TMRB0IE1_M               0x04000000
+#define AM_REG_CTIMER_CTRL0_TMRB0IE1(n)              (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_CTIMER_CTRL0_TMRB0IE1_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRB0IE1_EN              0x04000000
+
+// Counter/Timer B0 Interrupt Enable bit for COMPR0.
+#define AM_REG_CTIMER_CTRL0_TMRB0IE0_S               25
+#define AM_REG_CTIMER_CTRL0_TMRB0IE0_M               0x02000000
+#define AM_REG_CTIMER_CTRL0_TMRB0IE0(n)              (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_CTIMER_CTRL0_TMRB0IE0_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRB0IE0_EN              0x02000000
+
+// Counter/Timer B0 Function Select.
+#define AM_REG_CTIMER_CTRL0_TMRB0FN_S                22
+#define AM_REG_CTIMER_CTRL0_TMRB0FN_M                0x01C00000
+#define AM_REG_CTIMER_CTRL0_TMRB0FN(n)               (((uint32_t)(n) << 22) & 0x01C00000)
+#define AM_REG_CTIMER_CTRL0_TMRB0FN_SINGLECOUNT      0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT    0x00400000
+#define AM_REG_CTIMER_CTRL0_TMRB0FN_PULSE_ONCE       0x00800000
+#define AM_REG_CTIMER_CTRL0_TMRB0FN_PULSE_CONT       0x00C00000
+#define AM_REG_CTIMER_CTRL0_TMRB0FN_CONTINUOUS       0x01000000
+
+// Counter/Timer B0 Clock Select.
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_S               17
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_M               0x003E0000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK(n)              (((uint32_t)(n) << 17) & 0x003E0000)
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_TMRPIN          0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4       0x00020000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16      0x00040000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256     0x00060000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024    0x00080000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K      0x000A0000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT              0x000C0000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV2         0x000E0000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV16        0x00100000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV256       0x00120000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2       0x00140000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32      0x00160000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K      0x00180000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC            0x001A0000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_RTC_100HZ       0x001C0000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HCLK            0x001E0000
+#define AM_REG_CTIMER_CTRL0_TMRB0CLK_BUCKB           0x00200000
+
+// Counter/Timer B0 Enable bit.
+#define AM_REG_CTIMER_CTRL0_TMRB0EN_S                16
+#define AM_REG_CTIMER_CTRL0_TMRB0EN_M                0x00010000
+#define AM_REG_CTIMER_CTRL0_TMRB0EN(n)               (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_CTIMER_CTRL0_TMRB0EN_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRB0EN_EN               0x00010000
+
+// Counter/Timer A0 Output Enable bit.
+#define AM_REG_CTIMER_CTRL0_TMRA0PE_S                13
+#define AM_REG_CTIMER_CTRL0_TMRA0PE_M                0x00002000
+#define AM_REG_CTIMER_CTRL0_TMRA0PE(n)               (((uint32_t)(n) << 13) & 0x00002000)
+#define AM_REG_CTIMER_CTRL0_TMRA0PE_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRA0PE_EN               0x00002000
+
+// Counter/Timer A0 output polarity.
+#define AM_REG_CTIMER_CTRL0_TMRA0POL_S               12
+#define AM_REG_CTIMER_CTRL0_TMRA0POL_M               0x00001000
+#define AM_REG_CTIMER_CTRL0_TMRA0POL(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_CTRL0_TMRA0POL_NORMAL          0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRA0POL_INVERTED        0x00001000
+
+// Counter/Timer A0 Clear bit.
+#define AM_REG_CTIMER_CTRL0_TMRA0CLR_S               11
+#define AM_REG_CTIMER_CTRL0_TMRA0CLR_M               0x00000800
+#define AM_REG_CTIMER_CTRL0_TMRA0CLR(n)              (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_CTRL0_TMRA0CLR_RUN             0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRA0CLR_CLEAR           0x00000800
+
+// Counter/Timer A0 Interrupt Enable bit based on COMPR1.
+#define AM_REG_CTIMER_CTRL0_TMRA0IE1_S               10
+#define AM_REG_CTIMER_CTRL0_TMRA0IE1_M               0x00000400
+#define AM_REG_CTIMER_CTRL0_TMRA0IE1(n)              (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_CTRL0_TMRA0IE1_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRA0IE1_EN              0x00000400
+
+// Counter/Timer A0 Interrupt Enable bit based on COMPR0.
+#define AM_REG_CTIMER_CTRL0_TMRA0IE0_S               9
+#define AM_REG_CTIMER_CTRL0_TMRA0IE0_M               0x00000200
+#define AM_REG_CTIMER_CTRL0_TMRA0IE0(n)              (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_CTRL0_TMRA0IE0_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRA0IE0_EN              0x00000200
+
+// Counter/Timer A0 Function Select.
+#define AM_REG_CTIMER_CTRL0_TMRA0FN_S                6
+#define AM_REG_CTIMER_CTRL0_TMRA0FN_M                0x000001C0
+#define AM_REG_CTIMER_CTRL0_TMRA0FN(n)               (((uint32_t)(n) << 6) & 0x000001C0)
+#define AM_REG_CTIMER_CTRL0_TMRA0FN_SINGLECOUNT      0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT    0x00000040
+#define AM_REG_CTIMER_CTRL0_TMRA0FN_PULSE_ONCE       0x00000080
+#define AM_REG_CTIMER_CTRL0_TMRA0FN_PULSE_CONT       0x000000C0
+#define AM_REG_CTIMER_CTRL0_TMRA0FN_CONTINUOUS       0x00000100
+
+// Counter/Timer A0 Clock Select.
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_S               1
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_M               0x0000003E
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK(n)              (((uint32_t)(n) << 1) & 0x0000003E)
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_TMRPIN          0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4       0x00000002
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16      0x00000004
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256     0x00000006
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024    0x00000008
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K      0x0000000A
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT              0x0000000C
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV2         0x0000000E
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV16        0x00000010
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV256       0x00000012
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2       0x00000014
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32      0x00000016
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K      0x00000018
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC            0x0000001A
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_RTC_100HZ       0x0000001C
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4       0x0000001E
+#define AM_REG_CTIMER_CTRL0_TMRA0CLK_BUCKA           0x00000020
+
+// Counter/Timer A0 Enable bit.
+#define AM_REG_CTIMER_CTRL0_TMRA0EN_S                0
+#define AM_REG_CTIMER_CTRL0_TMRA0EN_M                0x00000001
+#define AM_REG_CTIMER_CTRL0_TMRA0EN(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_CTRL0_TMRA0EN_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL0_TMRA0EN_EN               0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_TMR1 - Counter/Timer Register
+//
+//*****************************************************************************
+// Counter/Timer B1.
+#define AM_REG_CTIMER_TMR1_CTTMRB1_S                 16
+#define AM_REG_CTIMER_TMR1_CTTMRB1_M                 0xFFFF0000
+#define AM_REG_CTIMER_TMR1_CTTMRB1(n)                (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer A1.
+#define AM_REG_CTIMER_TMR1_CTTMRA1_S                 0
+#define AM_REG_CTIMER_TMR1_CTTMRA1_M                 0x0000FFFF
+#define AM_REG_CTIMER_TMR1_CTTMRA1(n)                (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CMPRA1 - Counter/Timer A1 Compare Registers
+//
+//*****************************************************************************
+// Counter/Timer A1 Compare Register 1.
+#define AM_REG_CTIMER_CMPRA1_CMPR1A1_S               16
+#define AM_REG_CTIMER_CMPRA1_CMPR1A1_M               0xFFFF0000
+#define AM_REG_CTIMER_CMPRA1_CMPR1A1(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer A1 Compare Register 0.
+#define AM_REG_CTIMER_CMPRA1_CMPR0A1_S               0
+#define AM_REG_CTIMER_CMPRA1_CMPR0A1_M               0x0000FFFF
+#define AM_REG_CTIMER_CMPRA1_CMPR0A1(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CMPRB1 - Counter/Timer B1 Compare Registers
+//
+//*****************************************************************************
+// Counter/Timer B1 Compare Register 1.
+#define AM_REG_CTIMER_CMPRB1_CMPR1B1_S               16
+#define AM_REG_CTIMER_CMPRB1_CMPR1B1_M               0xFFFF0000
+#define AM_REG_CTIMER_CMPRB1_CMPR1B1(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer B1 Compare Register 0.
+#define AM_REG_CTIMER_CMPRB1_CMPR0B1_S               0
+#define AM_REG_CTIMER_CMPRB1_CMPR0B1_M               0x0000FFFF
+#define AM_REG_CTIMER_CMPRB1_CMPR0B1(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CTRL1 - Counter/Timer Control
+//
+//*****************************************************************************
+// Counter/Timer A1/B1 Link bit.
+#define AM_REG_CTIMER_CTRL1_CTLINK1_S                31
+#define AM_REG_CTIMER_CTRL1_CTLINK1_M                0x80000000
+#define AM_REG_CTIMER_CTRL1_CTLINK1(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS 0x00000000
+#define AM_REG_CTIMER_CTRL1_CTLINK1_32BIT_TIMER      0x80000000
+
+// Counter/Timer B1 Output Enable bit.
+#define AM_REG_CTIMER_CTRL1_TMRB1PE_S                29
+#define AM_REG_CTIMER_CTRL1_TMRB1PE_M                0x20000000
+#define AM_REG_CTIMER_CTRL1_TMRB1PE(n)               (((uint32_t)(n) << 29) & 0x20000000)
+#define AM_REG_CTIMER_CTRL1_TMRB1PE_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRB1PE_EN               0x20000000
+
+// Counter/Timer B1 output polarity.
+#define AM_REG_CTIMER_CTRL1_TMRB1POL_S               28
+#define AM_REG_CTIMER_CTRL1_TMRB1POL_M               0x10000000
+#define AM_REG_CTIMER_CTRL1_TMRB1POL(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_CTIMER_CTRL1_TMRB1POL_NORMAL          0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRB1POL_INVERTED        0x10000000
+
+// Counter/Timer B1 Clear bit.
+#define AM_REG_CTIMER_CTRL1_TMRB1CLR_S               27
+#define AM_REG_CTIMER_CTRL1_TMRB1CLR_M               0x08000000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLR(n)              (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_CTIMER_CTRL1_TMRB1CLR_RUN             0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLR_CLEAR           0x08000000
+
+// Counter/Timer B1 Interrupt Enable bit for COMPR1.
+#define AM_REG_CTIMER_CTRL1_TMRB1IE1_S               26
+#define AM_REG_CTIMER_CTRL1_TMRB1IE1_M               0x04000000
+#define AM_REG_CTIMER_CTRL1_TMRB1IE1(n)              (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_CTIMER_CTRL1_TMRB1IE1_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRB1IE1_EN              0x04000000
+
+// Counter/Timer B1 Interrupt Enable bit for COMPR0.
+#define AM_REG_CTIMER_CTRL1_TMRB1IE0_S               25
+#define AM_REG_CTIMER_CTRL1_TMRB1IE0_M               0x02000000
+#define AM_REG_CTIMER_CTRL1_TMRB1IE0(n)              (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_CTIMER_CTRL1_TMRB1IE0_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRB1IE0_EN              0x02000000
+
+// Counter/Timer B1 Function Select.
+#define AM_REG_CTIMER_CTRL1_TMRB1FN_S                22
+#define AM_REG_CTIMER_CTRL1_TMRB1FN_M                0x01C00000
+#define AM_REG_CTIMER_CTRL1_TMRB1FN(n)               (((uint32_t)(n) << 22) & 0x01C00000)
+#define AM_REG_CTIMER_CTRL1_TMRB1FN_SINGLECOUNT      0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT    0x00400000
+#define AM_REG_CTIMER_CTRL1_TMRB1FN_PULSE_ONCE       0x00800000
+#define AM_REG_CTIMER_CTRL1_TMRB1FN_PULSE_CONT       0x00C00000
+#define AM_REG_CTIMER_CTRL1_TMRB1FN_CONTINUOUS       0x01000000
+
+// Counter/Timer B1 Clock Select.
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_S               17
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_M               0x003E0000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK(n)              (((uint32_t)(n) << 17) & 0x003E0000)
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_TMRPIN          0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4       0x00020000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16      0x00040000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256     0x00060000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024    0x00080000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K      0x000A0000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT              0x000C0000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV2         0x000E0000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV16        0x00100000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV256       0x00120000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2       0x00140000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32      0x00160000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K      0x00180000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC            0x001A0000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_RTC_100HZ       0x001C0000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HCLK            0x001E0000
+#define AM_REG_CTIMER_CTRL1_TMRB1CLK_BUCKB           0x00200000
+
+// Counter/Timer B1 Enable bit.
+#define AM_REG_CTIMER_CTRL1_TMRB1EN_S                16
+#define AM_REG_CTIMER_CTRL1_TMRB1EN_M                0x00010000
+#define AM_REG_CTIMER_CTRL1_TMRB1EN(n)               (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_CTIMER_CTRL1_TMRB1EN_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRB1EN_EN               0x00010000
+
+// Counter/Timer A1 Output Enable bit.
+#define AM_REG_CTIMER_CTRL1_TMRA1PE_S                13
+#define AM_REG_CTIMER_CTRL1_TMRA1PE_M                0x00002000
+#define AM_REG_CTIMER_CTRL1_TMRA1PE(n)               (((uint32_t)(n) << 13) & 0x00002000)
+#define AM_REG_CTIMER_CTRL1_TMRA1PE_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRA1PE_EN               0x00002000
+
+// Counter/Timer A1 output polarity.
+#define AM_REG_CTIMER_CTRL1_TMRA1POL_S               12
+#define AM_REG_CTIMER_CTRL1_TMRA1POL_M               0x00001000
+#define AM_REG_CTIMER_CTRL1_TMRA1POL(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_CTRL1_TMRA1POL_NORMAL          0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRA1POL_INVERTED        0x00001000
+
+// Counter/Timer A1 Clear bit.
+#define AM_REG_CTIMER_CTRL1_TMRA1CLR_S               11
+#define AM_REG_CTIMER_CTRL1_TMRA1CLR_M               0x00000800
+#define AM_REG_CTIMER_CTRL1_TMRA1CLR(n)              (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_CTRL1_TMRA1CLR_RUN             0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRA1CLR_CLEAR           0x00000800
+
+// Counter/Timer A1 Interrupt Enable bit based on COMPR1.
+#define AM_REG_CTIMER_CTRL1_TMRA1IE1_S               10
+#define AM_REG_CTIMER_CTRL1_TMRA1IE1_M               0x00000400
+#define AM_REG_CTIMER_CTRL1_TMRA1IE1(n)              (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_CTRL1_TMRA1IE1_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRA1IE1_EN              0x00000400
+
+// Counter/Timer A1 Interrupt Enable bit based on COMPR0.
+#define AM_REG_CTIMER_CTRL1_TMRA1IE0_S               9
+#define AM_REG_CTIMER_CTRL1_TMRA1IE0_M               0x00000200
+#define AM_REG_CTIMER_CTRL1_TMRA1IE0(n)              (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_CTRL1_TMRA1IE0_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRA1IE0_EN              0x00000200
+
+// Counter/Timer A1 Function Select.
+#define AM_REG_CTIMER_CTRL1_TMRA1FN_S                6
+#define AM_REG_CTIMER_CTRL1_TMRA1FN_M                0x000001C0
+#define AM_REG_CTIMER_CTRL1_TMRA1FN(n)               (((uint32_t)(n) << 6) & 0x000001C0)
+#define AM_REG_CTIMER_CTRL1_TMRA1FN_SINGLECOUNT      0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT    0x00000040
+#define AM_REG_CTIMER_CTRL1_TMRA1FN_PULSE_ONCE       0x00000080
+#define AM_REG_CTIMER_CTRL1_TMRA1FN_PULSE_CONT       0x000000C0
+#define AM_REG_CTIMER_CTRL1_TMRA1FN_CONTINUOUS       0x00000100
+
+// Counter/Timer A1 Clock Select.
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_S               1
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_M               0x0000003E
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK(n)              (((uint32_t)(n) << 1) & 0x0000003E)
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_TMRPIN          0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4       0x00000002
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16      0x00000004
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256     0x00000006
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024    0x00000008
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K      0x0000000A
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT              0x0000000C
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV2         0x0000000E
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV16        0x00000010
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV256       0x00000012
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2       0x00000014
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32      0x00000016
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K      0x00000018
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC            0x0000001A
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_RTC_100HZ       0x0000001C
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HCLK            0x0000001E
+#define AM_REG_CTIMER_CTRL1_TMRA1CLK_BUCKA           0x00000020
+
+// Counter/Timer A1 Enable bit.
+#define AM_REG_CTIMER_CTRL1_TMRA1EN_S                0
+#define AM_REG_CTIMER_CTRL1_TMRA1EN_M                0x00000001
+#define AM_REG_CTIMER_CTRL1_TMRA1EN(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_CTRL1_TMRA1EN_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL1_TMRA1EN_EN               0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_TMR2 - Counter/Timer Register
+//
+//*****************************************************************************
+// Counter/Timer B2.
+#define AM_REG_CTIMER_TMR2_CTTMRB2_S                 16
+#define AM_REG_CTIMER_TMR2_CTTMRB2_M                 0xFFFF0000
+#define AM_REG_CTIMER_TMR2_CTTMRB2(n)                (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer A2.
+#define AM_REG_CTIMER_TMR2_CTTMRA2_S                 0
+#define AM_REG_CTIMER_TMR2_CTTMRA2_M                 0x0000FFFF
+#define AM_REG_CTIMER_TMR2_CTTMRA2(n)                (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CMPRA2 - Counter/Timer A2 Compare Registers
+//
+//*****************************************************************************
+// Counter/Timer A2 Compare Register 1.
+#define AM_REG_CTIMER_CMPRA2_CMPR1A2_S               16
+#define AM_REG_CTIMER_CMPRA2_CMPR1A2_M               0xFFFF0000
+#define AM_REG_CTIMER_CMPRA2_CMPR1A2(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer A2 Compare Register 0.
+#define AM_REG_CTIMER_CMPRA2_CMPR0A2_S               0
+#define AM_REG_CTIMER_CMPRA2_CMPR0A2_M               0x0000FFFF
+#define AM_REG_CTIMER_CMPRA2_CMPR0A2(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CMPRB2 - Counter/Timer B2 Compare Registers
+//
+//*****************************************************************************
+// Counter/Timer B2 Compare Register 1.
+#define AM_REG_CTIMER_CMPRB2_CMPR1B2_S               16
+#define AM_REG_CTIMER_CMPRB2_CMPR1B2_M               0xFFFF0000
+#define AM_REG_CTIMER_CMPRB2_CMPR1B2(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer B2 Compare Register 0.
+#define AM_REG_CTIMER_CMPRB2_CMPR0B2_S               0
+#define AM_REG_CTIMER_CMPRB2_CMPR0B2_M               0x0000FFFF
+#define AM_REG_CTIMER_CMPRB2_CMPR0B2(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CTRL2 - Counter/Timer Control
+//
+//*****************************************************************************
+// Counter/Timer A2/B2 Link bit.
+#define AM_REG_CTIMER_CTRL2_CTLINK2_S                31
+#define AM_REG_CTIMER_CTRL2_CTLINK2_M                0x80000000
+#define AM_REG_CTIMER_CTRL2_CTLINK2(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS 0x00000000
+#define AM_REG_CTIMER_CTRL2_CTLINK2_32BIT_TIMER      0x80000000
+
+// Counter/Timer B2 Output Enable bit.
+#define AM_REG_CTIMER_CTRL2_TMRB2PE_S                29
+#define AM_REG_CTIMER_CTRL2_TMRB2PE_M                0x20000000
+#define AM_REG_CTIMER_CTRL2_TMRB2PE(n)               (((uint32_t)(n) << 29) & 0x20000000)
+#define AM_REG_CTIMER_CTRL2_TMRB2PE_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRB2PE_EN               0x20000000
+
+// Counter/Timer B2 output polarity.
+#define AM_REG_CTIMER_CTRL2_TMRB2POL_S               28
+#define AM_REG_CTIMER_CTRL2_TMRB2POL_M               0x10000000
+#define AM_REG_CTIMER_CTRL2_TMRB2POL(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_CTIMER_CTRL2_TMRB2POL_NORMAL          0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRB2POL_INVERTED        0x10000000
+
+// Counter/Timer B2 Clear bit.
+#define AM_REG_CTIMER_CTRL2_TMRB2CLR_S               27
+#define AM_REG_CTIMER_CTRL2_TMRB2CLR_M               0x08000000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLR(n)              (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_CTIMER_CTRL2_TMRB2CLR_RUN             0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLR_CLEAR           0x08000000
+
+// Counter/Timer B2 Interrupt Enable bit for COMPR1.
+#define AM_REG_CTIMER_CTRL2_TMRB2IE1_S               26
+#define AM_REG_CTIMER_CTRL2_TMRB2IE1_M               0x04000000
+#define AM_REG_CTIMER_CTRL2_TMRB2IE1(n)              (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_CTIMER_CTRL2_TMRB2IE1_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRB2IE1_EN              0x04000000
+
+// Counter/Timer B2 Interrupt Enable bit for COMPR0.
+#define AM_REG_CTIMER_CTRL2_TMRB2IE0_S               25
+#define AM_REG_CTIMER_CTRL2_TMRB2IE0_M               0x02000000
+#define AM_REG_CTIMER_CTRL2_TMRB2IE0(n)              (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_CTIMER_CTRL2_TMRB2IE0_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRB2IE0_EN              0x02000000
+
+// Counter/Timer B2 Function Select.
+#define AM_REG_CTIMER_CTRL2_TMRB2FN_S                22
+#define AM_REG_CTIMER_CTRL2_TMRB2FN_M                0x01C00000
+#define AM_REG_CTIMER_CTRL2_TMRB2FN(n)               (((uint32_t)(n) << 22) & 0x01C00000)
+#define AM_REG_CTIMER_CTRL2_TMRB2FN_SINGLECOUNT      0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT    0x00400000
+#define AM_REG_CTIMER_CTRL2_TMRB2FN_PULSE_ONCE       0x00800000
+#define AM_REG_CTIMER_CTRL2_TMRB2FN_PULSE_CONT       0x00C00000
+#define AM_REG_CTIMER_CTRL2_TMRB2FN_CONTINUOUS       0x01000000
+
+// Counter/Timer B2 Clock Select.
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_S               17
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_M               0x003E0000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK(n)              (((uint32_t)(n) << 17) & 0x003E0000)
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_TMRPIN          0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4       0x00020000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16      0x00040000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256     0x00060000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024    0x00080000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K      0x000A0000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT              0x000C0000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV2         0x000E0000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV16        0x00100000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV256       0x00120000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2       0x00140000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32      0x00160000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K      0x00180000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC            0x001A0000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_RTC_100HZ       0x001C0000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HCLK            0x001E0000
+#define AM_REG_CTIMER_CTRL2_TMRB2CLK_BUCKA           0x00200000
+
+// Counter/Timer B2 Enable bit.
+#define AM_REG_CTIMER_CTRL2_TMRB2EN_S                16
+#define AM_REG_CTIMER_CTRL2_TMRB2EN_M                0x00010000
+#define AM_REG_CTIMER_CTRL2_TMRB2EN(n)               (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_CTIMER_CTRL2_TMRB2EN_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRB2EN_EN               0x00010000
+
+// Counter/Timer A2 Output Enable bit.
+#define AM_REG_CTIMER_CTRL2_TMRA2PE_S                13
+#define AM_REG_CTIMER_CTRL2_TMRA2PE_M                0x00002000
+#define AM_REG_CTIMER_CTRL2_TMRA2PE(n)               (((uint32_t)(n) << 13) & 0x00002000)
+#define AM_REG_CTIMER_CTRL2_TMRA2PE_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRA2PE_EN               0x00002000
+
+// Counter/Timer A2 output polarity.
+#define AM_REG_CTIMER_CTRL2_TMRA2POL_S               12
+#define AM_REG_CTIMER_CTRL2_TMRA2POL_M               0x00001000
+#define AM_REG_CTIMER_CTRL2_TMRA2POL(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_CTRL2_TMRA2POL_NORMAL          0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRA2POL_INVERTED        0x00001000
+
+// Counter/Timer A2 Clear bit.
+#define AM_REG_CTIMER_CTRL2_TMRA2CLR_S               11
+#define AM_REG_CTIMER_CTRL2_TMRA2CLR_M               0x00000800
+#define AM_REG_CTIMER_CTRL2_TMRA2CLR(n)              (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_CTRL2_TMRA2CLR_RUN             0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRA2CLR_CLEAR           0x00000800
+
+// Counter/Timer A2 Interrupt Enable bit based on COMPR1.
+#define AM_REG_CTIMER_CTRL2_TMRA2IE1_S               10
+#define AM_REG_CTIMER_CTRL2_TMRA2IE1_M               0x00000400
+#define AM_REG_CTIMER_CTRL2_TMRA2IE1(n)              (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_CTRL2_TMRA2IE1_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRA2IE1_EN              0x00000400
+
+// Counter/Timer A2 Interrupt Enable bit based on COMPR0.
+#define AM_REG_CTIMER_CTRL2_TMRA2IE0_S               9
+#define AM_REG_CTIMER_CTRL2_TMRA2IE0_M               0x00000200
+#define AM_REG_CTIMER_CTRL2_TMRA2IE0(n)              (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_CTRL2_TMRA2IE0_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRA2IE0_EN              0x00000200
+
+// Counter/Timer A2 Function Select.
+#define AM_REG_CTIMER_CTRL2_TMRA2FN_S                6
+#define AM_REG_CTIMER_CTRL2_TMRA2FN_M                0x000001C0
+#define AM_REG_CTIMER_CTRL2_TMRA2FN(n)               (((uint32_t)(n) << 6) & 0x000001C0)
+#define AM_REG_CTIMER_CTRL2_TMRA2FN_SINGLECOUNT      0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT    0x00000040
+#define AM_REG_CTIMER_CTRL2_TMRA2FN_PULSE_ONCE       0x00000080
+#define AM_REG_CTIMER_CTRL2_TMRA2FN_PULSE_CONT       0x000000C0
+#define AM_REG_CTIMER_CTRL2_TMRA2FN_CONTINUOUS       0x00000100
+
+// Counter/Timer A2 Clock Select.
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_S               1
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_M               0x0000003E
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK(n)              (((uint32_t)(n) << 1) & 0x0000003E)
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_TMRPIN          0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4       0x00000002
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16      0x00000004
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256     0x00000006
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024    0x00000008
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K      0x0000000A
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT              0x0000000C
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV2         0x0000000E
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV16        0x00000010
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV256       0x00000012
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2       0x00000014
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32      0x00000016
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K      0x00000018
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC            0x0000001A
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_RTC_100HZ       0x0000001C
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HCLK            0x0000001E
+#define AM_REG_CTIMER_CTRL2_TMRA2CLK_BUCKB           0x00000020
+
+// Counter/Timer A2 Enable bit.
+#define AM_REG_CTIMER_CTRL2_TMRA2EN_S                0
+#define AM_REG_CTIMER_CTRL2_TMRA2EN_M                0x00000001
+#define AM_REG_CTIMER_CTRL2_TMRA2EN(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_CTRL2_TMRA2EN_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL2_TMRA2EN_EN               0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_TMR3 - Counter/Timer Register
+//
+//*****************************************************************************
+// Counter/Timer B3.
+#define AM_REG_CTIMER_TMR3_CTTMRB3_S                 16
+#define AM_REG_CTIMER_TMR3_CTTMRB3_M                 0xFFFF0000
+#define AM_REG_CTIMER_TMR3_CTTMRB3(n)                (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer A3.
+#define AM_REG_CTIMER_TMR3_CTTMRA3_S                 0
+#define AM_REG_CTIMER_TMR3_CTTMRA3_M                 0x0000FFFF
+#define AM_REG_CTIMER_TMR3_CTTMRA3(n)                (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CMPRA3 - Counter/Timer A3 Compare Registers
+//
+//*****************************************************************************
+// Counter/Timer A3 Compare Register 1.
+#define AM_REG_CTIMER_CMPRA3_CMPR1A3_S               16
+#define AM_REG_CTIMER_CMPRA3_CMPR1A3_M               0xFFFF0000
+#define AM_REG_CTIMER_CMPRA3_CMPR1A3(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer A3 Compare Register 0.
+#define AM_REG_CTIMER_CMPRA3_CMPR0A3_S               0
+#define AM_REG_CTIMER_CMPRA3_CMPR0A3_M               0x0000FFFF
+#define AM_REG_CTIMER_CMPRA3_CMPR0A3(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CMPRB3 - Counter/Timer B3 Compare Registers
+//
+//*****************************************************************************
+// Counter/Timer B3 Compare Register 1.
+#define AM_REG_CTIMER_CMPRB3_CMPR1B3_S               16
+#define AM_REG_CTIMER_CMPRB3_CMPR1B3_M               0xFFFF0000
+#define AM_REG_CTIMER_CMPRB3_CMPR1B3(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Counter/Timer B3 Compare Register 0.
+#define AM_REG_CTIMER_CMPRB3_CMPR0B3_S               0
+#define AM_REG_CTIMER_CMPRB3_CMPR0B3_M               0x0000FFFF
+#define AM_REG_CTIMER_CMPRB3_CMPR0B3(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CTRL3 - Counter/Timer Control
+//
+//*****************************************************************************
+// Counter/Timer A3/B3 Link bit.
+#define AM_REG_CTIMER_CTRL3_CTLINK3_S                31
+#define AM_REG_CTIMER_CTRL3_CTLINK3_M                0x80000000
+#define AM_REG_CTIMER_CTRL3_CTLINK3(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS 0x00000000
+#define AM_REG_CTIMER_CTRL3_CTLINK3_32BIT_TIMER      0x80000000
+
+// Counter/Timer B3 Output Enable bit.
+#define AM_REG_CTIMER_CTRL3_TMRB3PE_S                29
+#define AM_REG_CTIMER_CTRL3_TMRB3PE_M                0x20000000
+#define AM_REG_CTIMER_CTRL3_TMRB3PE(n)               (((uint32_t)(n) << 29) & 0x20000000)
+#define AM_REG_CTIMER_CTRL3_TMRB3PE_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRB3PE_EN               0x20000000
+
+// Counter/Timer B3 output polarity.
+#define AM_REG_CTIMER_CTRL3_TMRB3POL_S               28
+#define AM_REG_CTIMER_CTRL3_TMRB3POL_M               0x10000000
+#define AM_REG_CTIMER_CTRL3_TMRB3POL(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_CTIMER_CTRL3_TMRB3POL_NORMAL          0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRB3POL_INVERTED        0x10000000
+
+// Counter/Timer B3 Clear bit.
+#define AM_REG_CTIMER_CTRL3_TMRB3CLR_S               27
+#define AM_REG_CTIMER_CTRL3_TMRB3CLR_M               0x08000000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLR(n)              (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_CTIMER_CTRL3_TMRB3CLR_RUN             0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLR_CLEAR           0x08000000
+
+// Counter/Timer B3 Interrupt Enable bit for COMPR1.
+#define AM_REG_CTIMER_CTRL3_TMRB3IE1_S               26
+#define AM_REG_CTIMER_CTRL3_TMRB3IE1_M               0x04000000
+#define AM_REG_CTIMER_CTRL3_TMRB3IE1(n)              (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_CTIMER_CTRL3_TMRB3IE1_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRB3IE1_EN              0x04000000
+
+// Counter/Timer B3 Interrupt Enable bit for COMPR0.
+#define AM_REG_CTIMER_CTRL3_TMRB3IE0_S               25
+#define AM_REG_CTIMER_CTRL3_TMRB3IE0_M               0x02000000
+#define AM_REG_CTIMER_CTRL3_TMRB3IE0(n)              (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_CTIMER_CTRL3_TMRB3IE0_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRB3IE0_EN              0x02000000
+
+// Counter/Timer B3 Function Select.
+#define AM_REG_CTIMER_CTRL3_TMRB3FN_S                22
+#define AM_REG_CTIMER_CTRL3_TMRB3FN_M                0x01C00000
+#define AM_REG_CTIMER_CTRL3_TMRB3FN(n)               (((uint32_t)(n) << 22) & 0x01C00000)
+#define AM_REG_CTIMER_CTRL3_TMRB3FN_SINGLECOUNT      0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT    0x00400000
+#define AM_REG_CTIMER_CTRL3_TMRB3FN_PULSE_ONCE       0x00800000
+#define AM_REG_CTIMER_CTRL3_TMRB3FN_PULSE_CONT       0x00C00000
+#define AM_REG_CTIMER_CTRL3_TMRB3FN_CONTINUOUS       0x01000000
+
+// Counter/Timer B3 Clock Select.
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_S               17
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_M               0x003E0000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK(n)              (((uint32_t)(n) << 17) & 0x003E0000)
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_TMRPIN          0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4       0x00020000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16      0x00040000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256     0x00060000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024    0x00080000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K      0x000A0000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT              0x000C0000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV2         0x000E0000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV16        0x00100000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV256       0x00120000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2       0x00140000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32      0x00160000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K      0x00180000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC            0x001A0000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_RTC_100HZ       0x001C0000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HCLK            0x001E0000
+#define AM_REG_CTIMER_CTRL3_TMRB3CLK_BUCKA           0x00200000
+
+// Counter/Timer B3 Enable bit.
+#define AM_REG_CTIMER_CTRL3_TMRB3EN_S                16
+#define AM_REG_CTIMER_CTRL3_TMRB3EN_M                0x00010000
+#define AM_REG_CTIMER_CTRL3_TMRB3EN(n)               (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_CTIMER_CTRL3_TMRB3EN_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRB3EN_EN               0x00010000
+
+// Special Timer A3 enable for ADC function.
+#define AM_REG_CTIMER_CTRL3_ADCEN_S                  15
+#define AM_REG_CTIMER_CTRL3_ADCEN_M                  0x00008000
+#define AM_REG_CTIMER_CTRL3_ADCEN(n)                 (((uint32_t)(n) << 15) & 0x00008000)
+
+// Counter/Timer A3 Output Enable bit.
+#define AM_REG_CTIMER_CTRL3_TMRA3PE_S                13
+#define AM_REG_CTIMER_CTRL3_TMRA3PE_M                0x00002000
+#define AM_REG_CTIMER_CTRL3_TMRA3PE(n)               (((uint32_t)(n) << 13) & 0x00002000)
+#define AM_REG_CTIMER_CTRL3_TMRA3PE_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRA3PE_EN               0x00002000
+
+// Counter/Timer A3 output polarity.
+#define AM_REG_CTIMER_CTRL3_TMRA3POL_S               12
+#define AM_REG_CTIMER_CTRL3_TMRA3POL_M               0x00001000
+#define AM_REG_CTIMER_CTRL3_TMRA3POL(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_CTRL3_TMRA3POL_NORMAL          0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRA3POL_INVERTED        0x00001000
+
+// Counter/Timer A3 Clear bit.
+#define AM_REG_CTIMER_CTRL3_TMRA3CLR_S               11
+#define AM_REG_CTIMER_CTRL3_TMRA3CLR_M               0x00000800
+#define AM_REG_CTIMER_CTRL3_TMRA3CLR(n)              (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_CTRL3_TMRA3CLR_RUN             0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRA3CLR_CLEAR           0x00000800
+
+// Counter/Timer A3 Interrupt Enable bit based on COMPR1.
+#define AM_REG_CTIMER_CTRL3_TMRA3IE1_S               10
+#define AM_REG_CTIMER_CTRL3_TMRA3IE1_M               0x00000400
+#define AM_REG_CTIMER_CTRL3_TMRA3IE1(n)              (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_CTRL3_TMRA3IE1_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRA3IE1_EN              0x00000400
+
+// Counter/Timer A3 Interrupt Enable bit based on COMPR0.
+#define AM_REG_CTIMER_CTRL3_TMRA3IE0_S               9
+#define AM_REG_CTIMER_CTRL3_TMRA3IE0_M               0x00000200
+#define AM_REG_CTIMER_CTRL3_TMRA3IE0(n)              (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_CTRL3_TMRA3IE0_DIS             0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRA3IE0_EN              0x00000200
+
+// Counter/Timer A3 Function Select.
+#define AM_REG_CTIMER_CTRL3_TMRA3FN_S                6
+#define AM_REG_CTIMER_CTRL3_TMRA3FN_M                0x000001C0
+#define AM_REG_CTIMER_CTRL3_TMRA3FN(n)               (((uint32_t)(n) << 6) & 0x000001C0)
+#define AM_REG_CTIMER_CTRL3_TMRA3FN_SINGLECOUNT      0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT    0x00000040
+#define AM_REG_CTIMER_CTRL3_TMRA3FN_PULSE_ONCE       0x00000080
+#define AM_REG_CTIMER_CTRL3_TMRA3FN_PULSE_CONT       0x000000C0
+#define AM_REG_CTIMER_CTRL3_TMRA3FN_CONTINUOUS       0x00000100
+
+// Counter/Timer A3 Clock Select.
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_S               1
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_M               0x0000003E
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK(n)              (((uint32_t)(n) << 1) & 0x0000003E)
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_TMRPIN          0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4       0x00000002
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16      0x00000004
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256     0x00000006
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024    0x00000008
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K      0x0000000A
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT              0x0000000C
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV2         0x0000000E
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV16        0x00000010
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV256       0x00000012
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2       0x00000014
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32      0x00000016
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K      0x00000018
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC            0x0000001A
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_RTC_100HZ       0x0000001C
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HCLK            0x0000001E
+#define AM_REG_CTIMER_CTRL3_TMRA3CLK_BUCKB           0x00000020
+
+// Counter/Timer A3 Enable bit.
+#define AM_REG_CTIMER_CTRL3_TMRA3EN_S                0
+#define AM_REG_CTIMER_CTRL3_TMRA3EN_M                0x00000001
+#define AM_REG_CTIMER_CTRL3_TMRA3EN(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_CTRL3_TMRA3EN_DIS              0x00000000
+#define AM_REG_CTIMER_CTRL3_TMRA3EN_EN               0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_STCFG - Configuration Register
+//
+//*****************************************************************************
+// Set this bit to one to freeze the clock input to the COUNTER register. Once
+// frozen, the value can be safely written from the MCU.  Unfreeze to resume.
+#define AM_REG_CTIMER_STCFG_FREEZE_S                 31
+#define AM_REG_CTIMER_STCFG_FREEZE_M                 0x80000000
+#define AM_REG_CTIMER_STCFG_FREEZE(n)                (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_CTIMER_STCFG_FREEZE_THAW              0x00000000
+#define AM_REG_CTIMER_STCFG_FREEZE_FREEZE            0x80000000
+
+// Set this bit to one to clear the System Timer register.  If this bit is set
+// to '1', the system timer register will stay cleared.  It needs to be set to
+// '0' for the system timer to start running.
+#define AM_REG_CTIMER_STCFG_CLEAR_S                  30
+#define AM_REG_CTIMER_STCFG_CLEAR_M                  0x40000000
+#define AM_REG_CTIMER_STCFG_CLEAR(n)                 (((uint32_t)(n) << 30) & 0x40000000)
+#define AM_REG_CTIMER_STCFG_CLEAR_RUN                0x00000000
+#define AM_REG_CTIMER_STCFG_CLEAR_CLEAR              0x40000000
+
+// Selects whether compare is enabled for the corresponding SCMPR register. If
+// compare is enabled, the interrupt status is set once the comparision is met.
+#define AM_REG_CTIMER_STCFG_COMPARE_H_EN_S           15
+#define AM_REG_CTIMER_STCFG_COMPARE_H_EN_M           0x00008000
+#define AM_REG_CTIMER_STCFG_COMPARE_H_EN(n)          (((uint32_t)(n) << 15) & 0x00008000)
+#define AM_REG_CTIMER_STCFG_COMPARE_H_EN_DISABLE     0x00000000
+#define AM_REG_CTIMER_STCFG_COMPARE_H_EN_ENABLE      0x00008000
+
+// Selects whether compare is enabled for the corresponding SCMPR register. If
+// compare is enabled, the interrupt status is set once the comparision is met.
+#define AM_REG_CTIMER_STCFG_COMPARE_G_EN_S           14
+#define AM_REG_CTIMER_STCFG_COMPARE_G_EN_M           0x00004000
+#define AM_REG_CTIMER_STCFG_COMPARE_G_EN(n)          (((uint32_t)(n) << 14) & 0x00004000)
+#define AM_REG_CTIMER_STCFG_COMPARE_G_EN_DISABLE     0x00000000
+#define AM_REG_CTIMER_STCFG_COMPARE_G_EN_ENABLE      0x00004000
+
+// Selects whether compare is enabled for the corresponding SCMPR register. If
+// compare is enabled, the interrupt status is set once the comparision is met.
+#define AM_REG_CTIMER_STCFG_COMPARE_F_EN_S           13
+#define AM_REG_CTIMER_STCFG_COMPARE_F_EN_M           0x00002000
+#define AM_REG_CTIMER_STCFG_COMPARE_F_EN(n)          (((uint32_t)(n) << 13) & 0x00002000)
+#define AM_REG_CTIMER_STCFG_COMPARE_F_EN_DISABLE     0x00000000
+#define AM_REG_CTIMER_STCFG_COMPARE_F_EN_ENABLE      0x00002000
+
+// Selects whether compare is enabled for the corresponding SCMPR register. If
+// compare is enabled, the interrupt status is set once the comparision is met.
+#define AM_REG_CTIMER_STCFG_COMPARE_E_EN_S           12
+#define AM_REG_CTIMER_STCFG_COMPARE_E_EN_M           0x00001000
+#define AM_REG_CTIMER_STCFG_COMPARE_E_EN(n)          (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_CTIMER_STCFG_COMPARE_E_EN_DISABLE     0x00000000
+#define AM_REG_CTIMER_STCFG_COMPARE_E_EN_ENABLE      0x00001000
+
+// Selects whether compare is enabled for the corresponding SCMPR register. If
+// compare is enabled, the interrupt status is set once the comparision is met.
+#define AM_REG_CTIMER_STCFG_COMPARE_D_EN_S           11
+#define AM_REG_CTIMER_STCFG_COMPARE_D_EN_M           0x00000800
+#define AM_REG_CTIMER_STCFG_COMPARE_D_EN(n)          (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_CTIMER_STCFG_COMPARE_D_EN_DISABLE     0x00000000
+#define AM_REG_CTIMER_STCFG_COMPARE_D_EN_ENABLE      0x00000800
+
+// Selects whether compare is enabled for the corresponding SCMPR register. If
+// compare is enabled, the interrupt status is set once the comparision is met.
+#define AM_REG_CTIMER_STCFG_COMPARE_C_EN_S           10
+#define AM_REG_CTIMER_STCFG_COMPARE_C_EN_M           0x00000400
+#define AM_REG_CTIMER_STCFG_COMPARE_C_EN(n)          (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_CTIMER_STCFG_COMPARE_C_EN_DISABLE     0x00000000
+#define AM_REG_CTIMER_STCFG_COMPARE_C_EN_ENABLE      0x00000400
+
+// Selects whether compare is enabled for the corresponding SCMPR register. If
+// compare is enabled, the interrupt status is set once the comparision is met.
+#define AM_REG_CTIMER_STCFG_COMPARE_B_EN_S           9
+#define AM_REG_CTIMER_STCFG_COMPARE_B_EN_M           0x00000200
+#define AM_REG_CTIMER_STCFG_COMPARE_B_EN(n)          (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_CTIMER_STCFG_COMPARE_B_EN_DISABLE     0x00000000
+#define AM_REG_CTIMER_STCFG_COMPARE_B_EN_ENABLE      0x00000200
+
+// Selects whether compare is enabled for the corresponding SCMPR register. If
+// compare is enabled, the interrupt status is set once the comparision is met.
+#define AM_REG_CTIMER_STCFG_COMPARE_A_EN_S           8
+#define AM_REG_CTIMER_STCFG_COMPARE_A_EN_M           0x00000100
+#define AM_REG_CTIMER_STCFG_COMPARE_A_EN(n)          (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_CTIMER_STCFG_COMPARE_A_EN_DISABLE     0x00000000
+#define AM_REG_CTIMER_STCFG_COMPARE_A_EN_ENABLE      0x00000100
+
+// Selects an appropriate clock source and divider to use for the System Timer
+// clock.
+#define AM_REG_CTIMER_STCFG_CLKSEL_S                 0
+#define AM_REG_CTIMER_STCFG_CLKSEL_M                 0x0000000F
+#define AM_REG_CTIMER_STCFG_CLKSEL(n)                (((uint32_t)(n) << 0) & 0x0000000F)
+#define AM_REG_CTIMER_STCFG_CLKSEL_NOCLK             0x00000000
+#define AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16        0x00000001
+#define AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256       0x00000002
+#define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV1         0x00000003
+#define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV2         0x00000004
+#define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV32        0x00000005
+#define AM_REG_CTIMER_STCFG_CLKSEL_LFRC_DIV1         0x00000006
+#define AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0A          0x00000007
+#define AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0B          0x00000008
+
+//*****************************************************************************
+//
+// CTIMER_STTMR - System Timer Count Register (Real Time Counter)
+//
+//*****************************************************************************
+// Value of the 32-bit counter as it ticks over.
+#define AM_REG_CTIMER_STTMR_VALUE_S                  0
+#define AM_REG_CTIMER_STTMR_VALUE_M                  0xFFFFFFFF
+#define AM_REG_CTIMER_STTMR_VALUE(n)                 (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_CAPTURE_CONTROL - Capture Control Register
+//
+//*****************************************************************************
+// Selects whether capture is enabled for the specified capture register.
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_S    3
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_M    0x00000008
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D(n)   (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_DISABLE 0x00000000
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_ENABLE 0x00000008
+
+// Selects whether capture is enabled for the specified capture register.
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_S    2
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_M    0x00000004
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C(n)   (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_DISABLE 0x00000000
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_ENABLE 0x00000004
+
+// Selects whether capture is enabled for the specified capture register.
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_S    1
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_M    0x00000002
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B(n)   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_DISABLE 0x00000000
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_ENABLE 0x00000002
+
+// Selects whether capture is enabled for the specified capture register.
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_S    0
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_M    0x00000001
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A(n)   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_DISABLE 0x00000000
+#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_ENABLE 0x00000001
+
+//*****************************************************************************
+//
+// CTIMER_SCMPR0 - Compare Register A
+//
+//*****************************************************************************
+// Compare this value to the value in the COUNTER register according to the
+// match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF
+// register.
+#define AM_REG_CTIMER_SCMPR0_VALUE_S                 0
+#define AM_REG_CTIMER_SCMPR0_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCMPR0_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCMPR1 - Compare Register B
+//
+//*****************************************************************************
+// Compare this value to the value in the COUNTER register according to the
+// match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF
+// register.
+#define AM_REG_CTIMER_SCMPR1_VALUE_S                 0
+#define AM_REG_CTIMER_SCMPR1_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCMPR1_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCMPR2 - Compare Register C
+//
+//*****************************************************************************
+// Compare this value to the value in the COUNTER register according to the
+// match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF
+// register.
+#define AM_REG_CTIMER_SCMPR2_VALUE_S                 0
+#define AM_REG_CTIMER_SCMPR2_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCMPR2_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCMPR3 - Compare Register D
+//
+//*****************************************************************************
+// Compare this value to the value in the COUNTER register according to the
+// match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF
+// register.
+#define AM_REG_CTIMER_SCMPR3_VALUE_S                 0
+#define AM_REG_CTIMER_SCMPR3_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCMPR3_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCMPR4 - Compare Register E
+//
+//*****************************************************************************
+// Compare this value to the value in the COUNTER register according to the
+// match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF
+// register.
+#define AM_REG_CTIMER_SCMPR4_VALUE_S                 0
+#define AM_REG_CTIMER_SCMPR4_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCMPR4_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCMPR5 - Compare Register F
+//
+//*****************************************************************************
+// Compare this value to the value in the COUNTER register according to the
+// match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF
+// register.
+#define AM_REG_CTIMER_SCMPR5_VALUE_S                 0
+#define AM_REG_CTIMER_SCMPR5_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCMPR5_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCMPR6 - Compare Register G
+//
+//*****************************************************************************
+// Compare this value to the value in the COUNTER register according to the
+// match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF
+// register.
+#define AM_REG_CTIMER_SCMPR6_VALUE_S                 0
+#define AM_REG_CTIMER_SCMPR6_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCMPR6_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCMPR7 - Compare Register H
+//
+//*****************************************************************************
+// Compare this value to the value in the COUNTER register according to the
+// match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF
+// register.
+#define AM_REG_CTIMER_SCMPR7_VALUE_S                 0
+#define AM_REG_CTIMER_SCMPR7_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCMPR7_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCAPT0 - Capture Register A
+//
+//*****************************************************************************
+// Whenever the event is detected, the value in the COUNTER is copied into this
+// register and the corresponding interrupt status bit is set.
+#define AM_REG_CTIMER_SCAPT0_VALUE_S                 0
+#define AM_REG_CTIMER_SCAPT0_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCAPT0_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCAPT1 - Capture Register B
+//
+//*****************************************************************************
+// Whenever the event is detected, the value in the COUNTER is copied into this
+// register and the corresponding interrupt status bit is set.
+#define AM_REG_CTIMER_SCAPT1_VALUE_S                 0
+#define AM_REG_CTIMER_SCAPT1_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCAPT1_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCAPT2 - Capture Register C
+//
+//*****************************************************************************
+// Whenever the event is detected, the value in the COUNTER is copied into this
+// register and the corresponding interrupt status bit is set.
+#define AM_REG_CTIMER_SCAPT2_VALUE_S                 0
+#define AM_REG_CTIMER_SCAPT2_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCAPT2_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SCAPT3 - Capture Register D
+//
+//*****************************************************************************
+// Whenever the event is detected, the value in the COUNTER is copied into this
+// register and the corresponding interrupt status bit is set.
+#define AM_REG_CTIMER_SCAPT3_VALUE_S                 0
+#define AM_REG_CTIMER_SCAPT3_VALUE_M                 0xFFFFFFFF
+#define AM_REG_CTIMER_SCAPT3_VALUE(n)                (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SNVR0 - System Timer NVRAM_A Register
+//
+//*****************************************************************************
+// Value of the 32-bit counter as it ticks over.
+#define AM_REG_CTIMER_SNVR0_VALUE_S                  0
+#define AM_REG_CTIMER_SNVR0_VALUE_M                  0xFFFFFFFF
+#define AM_REG_CTIMER_SNVR0_VALUE(n)                 (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SNVR1 - System Timer NVRAM_B Register
+//
+//*****************************************************************************
+// Value of the 32-bit counter as it ticks over.
+#define AM_REG_CTIMER_SNVR1_VALUE_S                  0
+#define AM_REG_CTIMER_SNVR1_VALUE_M                  0xFFFFFFFF
+#define AM_REG_CTIMER_SNVR1_VALUE(n)                 (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// CTIMER_SNVR2 - System Timer NVRAM_C Register
+//
+//*****************************************************************************
+// Value of the 32-bit counter as it ticks over.
+#define AM_REG_CTIMER_SNVR2_VALUE_S                  0
+#define AM_REG_CTIMER_SNVR2_VALUE_M                  0xFFFFFFFF
+#define AM_REG_CTIMER_SNVR2_VALUE(n)                 (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+#endif // AM_REG_CTIMER_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h
new file mode 100644
index 0000000000..0b103ea6fb
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h
@@ -0,0 +1,68 @@
+//*****************************************************************************
+//
+//  am_reg_flashctrl.h
+//! @file
+//!
+//! @brief Register macros for the FLASHCTRL module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_FLASHCTRL_H
+#define AM_REG_FLASHCTRL_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_FLASHCTRL_NUM_MODULES                 1
+#define AM_REG_FLASHCTRLn(n) \
+    (REG_FLASHCTRL_BASEADDR + 0x00001000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Key values.
+//
+//*****************************************************************************
+
+#endif // AM_REG_FLASHCTRL_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h b/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h
new file mode 100644
index 0000000000..4690cd6111
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h
@@ -0,0 +1,5218 @@
+//*****************************************************************************
+//
+//  am_reg_gpio.h
+//! @file
+//!
+//! @brief Register macros for the GPIO module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_GPIO_H
+#define AM_REG_GPIO_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_GPIO_NUM_MODULES                      1
+#define AM_REG_GPIOn(n) \
+    (REG_GPIO_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_GPIO_PADREGA_O                        0x00000000
+#define AM_REG_GPIO_PADREGB_O                        0x00000004
+#define AM_REG_GPIO_PADREGC_O                        0x00000008
+#define AM_REG_GPIO_PADREGD_O                        0x0000000C
+#define AM_REG_GPIO_PADREGE_O                        0x00000010
+#define AM_REG_GPIO_PADREGF_O                        0x00000014
+#define AM_REG_GPIO_PADREGG_O                        0x00000018
+#define AM_REG_GPIO_PADREGH_O                        0x0000001C
+#define AM_REG_GPIO_PADREGI_O                        0x00000020
+#define AM_REG_GPIO_PADREGJ_O                        0x00000024
+#define AM_REG_GPIO_PADREGK_O                        0x00000028
+#define AM_REG_GPIO_PADREGL_O                        0x0000002C
+#define AM_REG_GPIO_PADREGM_O                        0x00000030
+#define AM_REG_GPIO_CFGA_O                           0x00000040
+#define AM_REG_GPIO_CFGB_O                           0x00000044
+#define AM_REG_GPIO_CFGC_O                           0x00000048
+#define AM_REG_GPIO_CFGD_O                           0x0000004C
+#define AM_REG_GPIO_CFGE_O                           0x00000050
+#define AM_REG_GPIO_CFGF_O                           0x00000054
+#define AM_REG_GPIO_CFGG_O                           0x00000058
+#define AM_REG_GPIO_RDA_O                            0x00000080
+#define AM_REG_GPIO_RDB_O                            0x00000084
+#define AM_REG_GPIO_WTA_O                            0x00000088
+#define AM_REG_GPIO_WTB_O                            0x0000008C
+#define AM_REG_GPIO_WTSA_O                           0x00000090
+#define AM_REG_GPIO_WTSB_O                           0x00000094
+#define AM_REG_GPIO_WTCA_O                           0x00000098
+#define AM_REG_GPIO_WTCB_O                           0x0000009C
+#define AM_REG_GPIO_ENA_O                            0x000000A0
+#define AM_REG_GPIO_ENB_O                            0x000000A4
+#define AM_REG_GPIO_ENSA_O                           0x000000A8
+#define AM_REG_GPIO_ENSB_O                           0x000000AC
+#define AM_REG_GPIO_ENCA_O                           0x000000B4
+#define AM_REG_GPIO_ENCB_O                           0x000000B8
+#define AM_REG_GPIO_STMRCAP_O                        0x000000BC
+#define AM_REG_GPIO_IOM0IRQ_O                        0x000000C0
+#define AM_REG_GPIO_IOM1IRQ_O                        0x000000C4
+#define AM_REG_GPIO_IOM2IRQ_O                        0x000000C8
+#define AM_REG_GPIO_IOM3IRQ_O                        0x000000CC
+#define AM_REG_GPIO_IOM4IRQ_O                        0x000000D0
+#define AM_REG_GPIO_IOM5IRQ_O                        0x000000D4
+#define AM_REG_GPIO_LOOPBACK_O                       0x000000D8
+#define AM_REG_GPIO_GPIOOBS_O                        0x000000DC
+#define AM_REG_GPIO_ALTPADCFGA_O                     0x000000E0
+#define AM_REG_GPIO_ALTPADCFGB_O                     0x000000E4
+#define AM_REG_GPIO_ALTPADCFGC_O                     0x000000E8
+#define AM_REG_GPIO_ALTPADCFGD_O                     0x000000EC
+#define AM_REG_GPIO_ALTPADCFGE_O                     0x000000F0
+#define AM_REG_GPIO_ALTPADCFGF_O                     0x000000F4
+#define AM_REG_GPIO_ALTPADCFGG_O                     0x000000F8
+#define AM_REG_GPIO_ALTPADCFGH_O                     0x000000FC
+#define AM_REG_GPIO_ALTPADCFGI_O                     0x00000100
+#define AM_REG_GPIO_ALTPADCFGJ_O                     0x00000104
+#define AM_REG_GPIO_ALTPADCFGK_O                     0x00000108
+#define AM_REG_GPIO_ALTPADCFGL_O                     0x0000010C
+#define AM_REG_GPIO_ALTPADCFGM_O                     0x00000110
+#define AM_REG_GPIO_PADKEY_O                         0x00000060
+#define AM_REG_GPIO_INT0EN_O                         0x00000200
+#define AM_REG_GPIO_INT0STAT_O                       0x00000204
+#define AM_REG_GPIO_INT0CLR_O                        0x00000208
+#define AM_REG_GPIO_INT0SET_O                        0x0000020C
+#define AM_REG_GPIO_INT1EN_O                         0x00000210
+#define AM_REG_GPIO_INT1STAT_O                       0x00000214
+#define AM_REG_GPIO_INT1CLR_O                        0x00000218
+#define AM_REG_GPIO_INT1SET_O                        0x0000021C
+
+//*****************************************************************************
+//
+// Key values.
+//
+//*****************************************************************************
+#define AM_REG_GPIO_PADKEY_KEYVAL                    0x00000073
+
+//*****************************************************************************
+//
+// GPIO_INT0EN - GPIO Interrupt Registers 31-0: Enable
+//
+//*****************************************************************************
+// GPIO31 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO31_S                  31
+#define AM_REG_GPIO_INT0EN_GPIO31_M                  0x80000000
+#define AM_REG_GPIO_INT0EN_GPIO31(n)                 (((uint32_t)(n) << 31) & 0x80000000)
+
+// GPIO30 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO30_S                  30
+#define AM_REG_GPIO_INT0EN_GPIO30_M                  0x40000000
+#define AM_REG_GPIO_INT0EN_GPIO30(n)                 (((uint32_t)(n) << 30) & 0x40000000)
+
+// GPIO29 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO29_S                  29
+#define AM_REG_GPIO_INT0EN_GPIO29_M                  0x20000000
+#define AM_REG_GPIO_INT0EN_GPIO29(n)                 (((uint32_t)(n) << 29) & 0x20000000)
+
+// GPIO28 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO28_S                  28
+#define AM_REG_GPIO_INT0EN_GPIO28_M                  0x10000000
+#define AM_REG_GPIO_INT0EN_GPIO28(n)                 (((uint32_t)(n) << 28) & 0x10000000)
+
+// GPIO27 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO27_S                  27
+#define AM_REG_GPIO_INT0EN_GPIO27_M                  0x08000000
+#define AM_REG_GPIO_INT0EN_GPIO27(n)                 (((uint32_t)(n) << 27) & 0x08000000)
+
+// GPIO26 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO26_S                  26
+#define AM_REG_GPIO_INT0EN_GPIO26_M                  0x04000000
+#define AM_REG_GPIO_INT0EN_GPIO26(n)                 (((uint32_t)(n) << 26) & 0x04000000)
+
+// GPIO25 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO25_S                  25
+#define AM_REG_GPIO_INT0EN_GPIO25_M                  0x02000000
+#define AM_REG_GPIO_INT0EN_GPIO25(n)                 (((uint32_t)(n) << 25) & 0x02000000)
+
+// GPIO24 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO24_S                  24
+#define AM_REG_GPIO_INT0EN_GPIO24_M                  0x01000000
+#define AM_REG_GPIO_INT0EN_GPIO24(n)                 (((uint32_t)(n) << 24) & 0x01000000)
+
+// GPIO23 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO23_S                  23
+#define AM_REG_GPIO_INT0EN_GPIO23_M                  0x00800000
+#define AM_REG_GPIO_INT0EN_GPIO23(n)                 (((uint32_t)(n) << 23) & 0x00800000)
+
+// GPIO22 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO22_S                  22
+#define AM_REG_GPIO_INT0EN_GPIO22_M                  0x00400000
+#define AM_REG_GPIO_INT0EN_GPIO22(n)                 (((uint32_t)(n) << 22) & 0x00400000)
+
+// GPIO21 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO21_S                  21
+#define AM_REG_GPIO_INT0EN_GPIO21_M                  0x00200000
+#define AM_REG_GPIO_INT0EN_GPIO21(n)                 (((uint32_t)(n) << 21) & 0x00200000)
+
+// GPIO20 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO20_S                  20
+#define AM_REG_GPIO_INT0EN_GPIO20_M                  0x00100000
+#define AM_REG_GPIO_INT0EN_GPIO20(n)                 (((uint32_t)(n) << 20) & 0x00100000)
+
+// GPIO19 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO19_S                  19
+#define AM_REG_GPIO_INT0EN_GPIO19_M                  0x00080000
+#define AM_REG_GPIO_INT0EN_GPIO19(n)                 (((uint32_t)(n) << 19) & 0x00080000)
+
+// GPIO18interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO18_S                  18
+#define AM_REG_GPIO_INT0EN_GPIO18_M                  0x00040000
+#define AM_REG_GPIO_INT0EN_GPIO18(n)                 (((uint32_t)(n) << 18) & 0x00040000)
+
+// GPIO17 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO17_S                  17
+#define AM_REG_GPIO_INT0EN_GPIO17_M                  0x00020000
+#define AM_REG_GPIO_INT0EN_GPIO17(n)                 (((uint32_t)(n) << 17) & 0x00020000)
+
+// GPIO16 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO16_S                  16
+#define AM_REG_GPIO_INT0EN_GPIO16_M                  0x00010000
+#define AM_REG_GPIO_INT0EN_GPIO16(n)                 (((uint32_t)(n) << 16) & 0x00010000)
+
+// GPIO15 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO15_S                  15
+#define AM_REG_GPIO_INT0EN_GPIO15_M                  0x00008000
+#define AM_REG_GPIO_INT0EN_GPIO15(n)                 (((uint32_t)(n) << 15) & 0x00008000)
+
+// GPIO14 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO14_S                  14
+#define AM_REG_GPIO_INT0EN_GPIO14_M                  0x00004000
+#define AM_REG_GPIO_INT0EN_GPIO14(n)                 (((uint32_t)(n) << 14) & 0x00004000)
+
+// GPIO13 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO13_S                  13
+#define AM_REG_GPIO_INT0EN_GPIO13_M                  0x00002000
+#define AM_REG_GPIO_INT0EN_GPIO13(n)                 (((uint32_t)(n) << 13) & 0x00002000)
+
+// GPIO12 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO12_S                  12
+#define AM_REG_GPIO_INT0EN_GPIO12_M                  0x00001000
+#define AM_REG_GPIO_INT0EN_GPIO12(n)                 (((uint32_t)(n) << 12) & 0x00001000)
+
+// GPIO11 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO11_S                  11
+#define AM_REG_GPIO_INT0EN_GPIO11_M                  0x00000800
+#define AM_REG_GPIO_INT0EN_GPIO11(n)                 (((uint32_t)(n) << 11) & 0x00000800)
+
+// GPIO10 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO10_S                  10
+#define AM_REG_GPIO_INT0EN_GPIO10_M                  0x00000400
+#define AM_REG_GPIO_INT0EN_GPIO10(n)                 (((uint32_t)(n) << 10) & 0x00000400)
+
+// GPIO9 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO9_S                   9
+#define AM_REG_GPIO_INT0EN_GPIO9_M                   0x00000200
+#define AM_REG_GPIO_INT0EN_GPIO9(n)                  (((uint32_t)(n) << 9) & 0x00000200)
+
+// GPIO8 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO8_S                   8
+#define AM_REG_GPIO_INT0EN_GPIO8_M                   0x00000100
+#define AM_REG_GPIO_INT0EN_GPIO8(n)                  (((uint32_t)(n) << 8) & 0x00000100)
+
+// GPIO7 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO7_S                   7
+#define AM_REG_GPIO_INT0EN_GPIO7_M                   0x00000080
+#define AM_REG_GPIO_INT0EN_GPIO7(n)                  (((uint32_t)(n) << 7) & 0x00000080)
+
+// GPIO6 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO6_S                   6
+#define AM_REG_GPIO_INT0EN_GPIO6_M                   0x00000040
+#define AM_REG_GPIO_INT0EN_GPIO6(n)                  (((uint32_t)(n) << 6) & 0x00000040)
+
+// GPIO5 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO5_S                   5
+#define AM_REG_GPIO_INT0EN_GPIO5_M                   0x00000020
+#define AM_REG_GPIO_INT0EN_GPIO5(n)                  (((uint32_t)(n) << 5) & 0x00000020)
+
+// GPIO4 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO4_S                   4
+#define AM_REG_GPIO_INT0EN_GPIO4_M                   0x00000010
+#define AM_REG_GPIO_INT0EN_GPIO4(n)                  (((uint32_t)(n) << 4) & 0x00000010)
+
+// GPIO3 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO3_S                   3
+#define AM_REG_GPIO_INT0EN_GPIO3_M                   0x00000008
+#define AM_REG_GPIO_INT0EN_GPIO3(n)                  (((uint32_t)(n) << 3) & 0x00000008)
+
+// GPIO2 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO2_S                   2
+#define AM_REG_GPIO_INT0EN_GPIO2_M                   0x00000004
+#define AM_REG_GPIO_INT0EN_GPIO2(n)                  (((uint32_t)(n) << 2) & 0x00000004)
+
+// GPIO1 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO1_S                   1
+#define AM_REG_GPIO_INT0EN_GPIO1_M                   0x00000002
+#define AM_REG_GPIO_INT0EN_GPIO1(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+
+// GPIO0 interrupt.
+#define AM_REG_GPIO_INT0EN_GPIO0_S                   0
+#define AM_REG_GPIO_INT0EN_GPIO0_M                   0x00000001
+#define AM_REG_GPIO_INT0EN_GPIO0(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_INT0STAT - GPIO Interrupt Registers 31-0: Status
+//
+//*****************************************************************************
+// GPIO31 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO31_S                31
+#define AM_REG_GPIO_INT0STAT_GPIO31_M                0x80000000
+#define AM_REG_GPIO_INT0STAT_GPIO31(n)               (((uint32_t)(n) << 31) & 0x80000000)
+
+// GPIO30 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO30_S                30
+#define AM_REG_GPIO_INT0STAT_GPIO30_M                0x40000000
+#define AM_REG_GPIO_INT0STAT_GPIO30(n)               (((uint32_t)(n) << 30) & 0x40000000)
+
+// GPIO29 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO29_S                29
+#define AM_REG_GPIO_INT0STAT_GPIO29_M                0x20000000
+#define AM_REG_GPIO_INT0STAT_GPIO29(n)               (((uint32_t)(n) << 29) & 0x20000000)
+
+// GPIO28 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO28_S                28
+#define AM_REG_GPIO_INT0STAT_GPIO28_M                0x10000000
+#define AM_REG_GPIO_INT0STAT_GPIO28(n)               (((uint32_t)(n) << 28) & 0x10000000)
+
+// GPIO27 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO27_S                27
+#define AM_REG_GPIO_INT0STAT_GPIO27_M                0x08000000
+#define AM_REG_GPIO_INT0STAT_GPIO27(n)               (((uint32_t)(n) << 27) & 0x08000000)
+
+// GPIO26 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO26_S                26
+#define AM_REG_GPIO_INT0STAT_GPIO26_M                0x04000000
+#define AM_REG_GPIO_INT0STAT_GPIO26(n)               (((uint32_t)(n) << 26) & 0x04000000)
+
+// GPIO25 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO25_S                25
+#define AM_REG_GPIO_INT0STAT_GPIO25_M                0x02000000
+#define AM_REG_GPIO_INT0STAT_GPIO25(n)               (((uint32_t)(n) << 25) & 0x02000000)
+
+// GPIO24 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO24_S                24
+#define AM_REG_GPIO_INT0STAT_GPIO24_M                0x01000000
+#define AM_REG_GPIO_INT0STAT_GPIO24(n)               (((uint32_t)(n) << 24) & 0x01000000)
+
+// GPIO23 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO23_S                23
+#define AM_REG_GPIO_INT0STAT_GPIO23_M                0x00800000
+#define AM_REG_GPIO_INT0STAT_GPIO23(n)               (((uint32_t)(n) << 23) & 0x00800000)
+
+// GPIO22 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO22_S                22
+#define AM_REG_GPIO_INT0STAT_GPIO22_M                0x00400000
+#define AM_REG_GPIO_INT0STAT_GPIO22(n)               (((uint32_t)(n) << 22) & 0x00400000)
+
+// GPIO21 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO21_S                21
+#define AM_REG_GPIO_INT0STAT_GPIO21_M                0x00200000
+#define AM_REG_GPIO_INT0STAT_GPIO21(n)               (((uint32_t)(n) << 21) & 0x00200000)
+
+// GPIO20 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO20_S                20
+#define AM_REG_GPIO_INT0STAT_GPIO20_M                0x00100000
+#define AM_REG_GPIO_INT0STAT_GPIO20(n)               (((uint32_t)(n) << 20) & 0x00100000)
+
+// GPIO19 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO19_S                19
+#define AM_REG_GPIO_INT0STAT_GPIO19_M                0x00080000
+#define AM_REG_GPIO_INT0STAT_GPIO19(n)               (((uint32_t)(n) << 19) & 0x00080000)
+
+// GPIO18interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO18_S                18
+#define AM_REG_GPIO_INT0STAT_GPIO18_M                0x00040000
+#define AM_REG_GPIO_INT0STAT_GPIO18(n)               (((uint32_t)(n) << 18) & 0x00040000)
+
+// GPIO17 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO17_S                17
+#define AM_REG_GPIO_INT0STAT_GPIO17_M                0x00020000
+#define AM_REG_GPIO_INT0STAT_GPIO17(n)               (((uint32_t)(n) << 17) & 0x00020000)
+
+// GPIO16 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO16_S                16
+#define AM_REG_GPIO_INT0STAT_GPIO16_M                0x00010000
+#define AM_REG_GPIO_INT0STAT_GPIO16(n)               (((uint32_t)(n) << 16) & 0x00010000)
+
+// GPIO15 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO15_S                15
+#define AM_REG_GPIO_INT0STAT_GPIO15_M                0x00008000
+#define AM_REG_GPIO_INT0STAT_GPIO15(n)               (((uint32_t)(n) << 15) & 0x00008000)
+
+// GPIO14 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO14_S                14
+#define AM_REG_GPIO_INT0STAT_GPIO14_M                0x00004000
+#define AM_REG_GPIO_INT0STAT_GPIO14(n)               (((uint32_t)(n) << 14) & 0x00004000)
+
+// GPIO13 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO13_S                13
+#define AM_REG_GPIO_INT0STAT_GPIO13_M                0x00002000
+#define AM_REG_GPIO_INT0STAT_GPIO13(n)               (((uint32_t)(n) << 13) & 0x00002000)
+
+// GPIO12 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO12_S                12
+#define AM_REG_GPIO_INT0STAT_GPIO12_M                0x00001000
+#define AM_REG_GPIO_INT0STAT_GPIO12(n)               (((uint32_t)(n) << 12) & 0x00001000)
+
+// GPIO11 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO11_S                11
+#define AM_REG_GPIO_INT0STAT_GPIO11_M                0x00000800
+#define AM_REG_GPIO_INT0STAT_GPIO11(n)               (((uint32_t)(n) << 11) & 0x00000800)
+
+// GPIO10 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO10_S                10
+#define AM_REG_GPIO_INT0STAT_GPIO10_M                0x00000400
+#define AM_REG_GPIO_INT0STAT_GPIO10(n)               (((uint32_t)(n) << 10) & 0x00000400)
+
+// GPIO9 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO9_S                 9
+#define AM_REG_GPIO_INT0STAT_GPIO9_M                 0x00000200
+#define AM_REG_GPIO_INT0STAT_GPIO9(n)                (((uint32_t)(n) << 9) & 0x00000200)
+
+// GPIO8 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO8_S                 8
+#define AM_REG_GPIO_INT0STAT_GPIO8_M                 0x00000100
+#define AM_REG_GPIO_INT0STAT_GPIO8(n)                (((uint32_t)(n) << 8) & 0x00000100)
+
+// GPIO7 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO7_S                 7
+#define AM_REG_GPIO_INT0STAT_GPIO7_M                 0x00000080
+#define AM_REG_GPIO_INT0STAT_GPIO7(n)                (((uint32_t)(n) << 7) & 0x00000080)
+
+// GPIO6 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO6_S                 6
+#define AM_REG_GPIO_INT0STAT_GPIO6_M                 0x00000040
+#define AM_REG_GPIO_INT0STAT_GPIO6(n)                (((uint32_t)(n) << 6) & 0x00000040)
+
+// GPIO5 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO5_S                 5
+#define AM_REG_GPIO_INT0STAT_GPIO5_M                 0x00000020
+#define AM_REG_GPIO_INT0STAT_GPIO5(n)                (((uint32_t)(n) << 5) & 0x00000020)
+
+// GPIO4 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO4_S                 4
+#define AM_REG_GPIO_INT0STAT_GPIO4_M                 0x00000010
+#define AM_REG_GPIO_INT0STAT_GPIO4(n)                (((uint32_t)(n) << 4) & 0x00000010)
+
+// GPIO3 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO3_S                 3
+#define AM_REG_GPIO_INT0STAT_GPIO3_M                 0x00000008
+#define AM_REG_GPIO_INT0STAT_GPIO3(n)                (((uint32_t)(n) << 3) & 0x00000008)
+
+// GPIO2 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO2_S                 2
+#define AM_REG_GPIO_INT0STAT_GPIO2_M                 0x00000004
+#define AM_REG_GPIO_INT0STAT_GPIO2(n)                (((uint32_t)(n) << 2) & 0x00000004)
+
+// GPIO1 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO1_S                 1
+#define AM_REG_GPIO_INT0STAT_GPIO1_M                 0x00000002
+#define AM_REG_GPIO_INT0STAT_GPIO1(n)                (((uint32_t)(n) << 1) & 0x00000002)
+
+// GPIO0 interrupt.
+#define AM_REG_GPIO_INT0STAT_GPIO0_S                 0
+#define AM_REG_GPIO_INT0STAT_GPIO0_M                 0x00000001
+#define AM_REG_GPIO_INT0STAT_GPIO0(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_INT0CLR - GPIO Interrupt Registers 31-0: Clear
+//
+//*****************************************************************************
+// GPIO31 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO31_S                 31
+#define AM_REG_GPIO_INT0CLR_GPIO31_M                 0x80000000
+#define AM_REG_GPIO_INT0CLR_GPIO31(n)                (((uint32_t)(n) << 31) & 0x80000000)
+
+// GPIO30 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO30_S                 30
+#define AM_REG_GPIO_INT0CLR_GPIO30_M                 0x40000000
+#define AM_REG_GPIO_INT0CLR_GPIO30(n)                (((uint32_t)(n) << 30) & 0x40000000)
+
+// GPIO29 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO29_S                 29
+#define AM_REG_GPIO_INT0CLR_GPIO29_M                 0x20000000
+#define AM_REG_GPIO_INT0CLR_GPIO29(n)                (((uint32_t)(n) << 29) & 0x20000000)
+
+// GPIO28 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO28_S                 28
+#define AM_REG_GPIO_INT0CLR_GPIO28_M                 0x10000000
+#define AM_REG_GPIO_INT0CLR_GPIO28(n)                (((uint32_t)(n) << 28) & 0x10000000)
+
+// GPIO27 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO27_S                 27
+#define AM_REG_GPIO_INT0CLR_GPIO27_M                 0x08000000
+#define AM_REG_GPIO_INT0CLR_GPIO27(n)                (((uint32_t)(n) << 27) & 0x08000000)
+
+// GPIO26 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO26_S                 26
+#define AM_REG_GPIO_INT0CLR_GPIO26_M                 0x04000000
+#define AM_REG_GPIO_INT0CLR_GPIO26(n)                (((uint32_t)(n) << 26) & 0x04000000)
+
+// GPIO25 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO25_S                 25
+#define AM_REG_GPIO_INT0CLR_GPIO25_M                 0x02000000
+#define AM_REG_GPIO_INT0CLR_GPIO25(n)                (((uint32_t)(n) << 25) & 0x02000000)
+
+// GPIO24 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO24_S                 24
+#define AM_REG_GPIO_INT0CLR_GPIO24_M                 0x01000000
+#define AM_REG_GPIO_INT0CLR_GPIO24(n)                (((uint32_t)(n) << 24) & 0x01000000)
+
+// GPIO23 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO23_S                 23
+#define AM_REG_GPIO_INT0CLR_GPIO23_M                 0x00800000
+#define AM_REG_GPIO_INT0CLR_GPIO23(n)                (((uint32_t)(n) << 23) & 0x00800000)
+
+// GPIO22 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO22_S                 22
+#define AM_REG_GPIO_INT0CLR_GPIO22_M                 0x00400000
+#define AM_REG_GPIO_INT0CLR_GPIO22(n)                (((uint32_t)(n) << 22) & 0x00400000)
+
+// GPIO21 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO21_S                 21
+#define AM_REG_GPIO_INT0CLR_GPIO21_M                 0x00200000
+#define AM_REG_GPIO_INT0CLR_GPIO21(n)                (((uint32_t)(n) << 21) & 0x00200000)
+
+// GPIO20 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO20_S                 20
+#define AM_REG_GPIO_INT0CLR_GPIO20_M                 0x00100000
+#define AM_REG_GPIO_INT0CLR_GPIO20(n)                (((uint32_t)(n) << 20) & 0x00100000)
+
+// GPIO19 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO19_S                 19
+#define AM_REG_GPIO_INT0CLR_GPIO19_M                 0x00080000
+#define AM_REG_GPIO_INT0CLR_GPIO19(n)                (((uint32_t)(n) << 19) & 0x00080000)
+
+// GPIO18interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO18_S                 18
+#define AM_REG_GPIO_INT0CLR_GPIO18_M                 0x00040000
+#define AM_REG_GPIO_INT0CLR_GPIO18(n)                (((uint32_t)(n) << 18) & 0x00040000)
+
+// GPIO17 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO17_S                 17
+#define AM_REG_GPIO_INT0CLR_GPIO17_M                 0x00020000
+#define AM_REG_GPIO_INT0CLR_GPIO17(n)                (((uint32_t)(n) << 17) & 0x00020000)
+
+// GPIO16 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO16_S                 16
+#define AM_REG_GPIO_INT0CLR_GPIO16_M                 0x00010000
+#define AM_REG_GPIO_INT0CLR_GPIO16(n)                (((uint32_t)(n) << 16) & 0x00010000)
+
+// GPIO15 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO15_S                 15
+#define AM_REG_GPIO_INT0CLR_GPIO15_M                 0x00008000
+#define AM_REG_GPIO_INT0CLR_GPIO15(n)                (((uint32_t)(n) << 15) & 0x00008000)
+
+// GPIO14 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO14_S                 14
+#define AM_REG_GPIO_INT0CLR_GPIO14_M                 0x00004000
+#define AM_REG_GPIO_INT0CLR_GPIO14(n)                (((uint32_t)(n) << 14) & 0x00004000)
+
+// GPIO13 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO13_S                 13
+#define AM_REG_GPIO_INT0CLR_GPIO13_M                 0x00002000
+#define AM_REG_GPIO_INT0CLR_GPIO13(n)                (((uint32_t)(n) << 13) & 0x00002000)
+
+// GPIO12 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO12_S                 12
+#define AM_REG_GPIO_INT0CLR_GPIO12_M                 0x00001000
+#define AM_REG_GPIO_INT0CLR_GPIO12(n)                (((uint32_t)(n) << 12) & 0x00001000)
+
+// GPIO11 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO11_S                 11
+#define AM_REG_GPIO_INT0CLR_GPIO11_M                 0x00000800
+#define AM_REG_GPIO_INT0CLR_GPIO11(n)                (((uint32_t)(n) << 11) & 0x00000800)
+
+// GPIO10 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO10_S                 10
+#define AM_REG_GPIO_INT0CLR_GPIO10_M                 0x00000400
+#define AM_REG_GPIO_INT0CLR_GPIO10(n)                (((uint32_t)(n) << 10) & 0x00000400)
+
+// GPIO9 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO9_S                  9
+#define AM_REG_GPIO_INT0CLR_GPIO9_M                  0x00000200
+#define AM_REG_GPIO_INT0CLR_GPIO9(n)                 (((uint32_t)(n) << 9) & 0x00000200)
+
+// GPIO8 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO8_S                  8
+#define AM_REG_GPIO_INT0CLR_GPIO8_M                  0x00000100
+#define AM_REG_GPIO_INT0CLR_GPIO8(n)                 (((uint32_t)(n) << 8) & 0x00000100)
+
+// GPIO7 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO7_S                  7
+#define AM_REG_GPIO_INT0CLR_GPIO7_M                  0x00000080
+#define AM_REG_GPIO_INT0CLR_GPIO7(n)                 (((uint32_t)(n) << 7) & 0x00000080)
+
+// GPIO6 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO6_S                  6
+#define AM_REG_GPIO_INT0CLR_GPIO6_M                  0x00000040
+#define AM_REG_GPIO_INT0CLR_GPIO6(n)                 (((uint32_t)(n) << 6) & 0x00000040)
+
+// GPIO5 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO5_S                  5
+#define AM_REG_GPIO_INT0CLR_GPIO5_M                  0x00000020
+#define AM_REG_GPIO_INT0CLR_GPIO5(n)                 (((uint32_t)(n) << 5) & 0x00000020)
+
+// GPIO4 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO4_S                  4
+#define AM_REG_GPIO_INT0CLR_GPIO4_M                  0x00000010
+#define AM_REG_GPIO_INT0CLR_GPIO4(n)                 (((uint32_t)(n) << 4) & 0x00000010)
+
+// GPIO3 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO3_S                  3
+#define AM_REG_GPIO_INT0CLR_GPIO3_M                  0x00000008
+#define AM_REG_GPIO_INT0CLR_GPIO3(n)                 (((uint32_t)(n) << 3) & 0x00000008)
+
+// GPIO2 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO2_S                  2
+#define AM_REG_GPIO_INT0CLR_GPIO2_M                  0x00000004
+#define AM_REG_GPIO_INT0CLR_GPIO2(n)                 (((uint32_t)(n) << 2) & 0x00000004)
+
+// GPIO1 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO1_S                  1
+#define AM_REG_GPIO_INT0CLR_GPIO1_M                  0x00000002
+#define AM_REG_GPIO_INT0CLR_GPIO1(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// GPIO0 interrupt.
+#define AM_REG_GPIO_INT0CLR_GPIO0_S                  0
+#define AM_REG_GPIO_INT0CLR_GPIO0_M                  0x00000001
+#define AM_REG_GPIO_INT0CLR_GPIO0(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_INT0SET - GPIO Interrupt Registers 31-0: Set
+//
+//*****************************************************************************
+// GPIO31 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO31_S                 31
+#define AM_REG_GPIO_INT0SET_GPIO31_M                 0x80000000
+#define AM_REG_GPIO_INT0SET_GPIO31(n)                (((uint32_t)(n) << 31) & 0x80000000)
+
+// GPIO30 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO30_S                 30
+#define AM_REG_GPIO_INT0SET_GPIO30_M                 0x40000000
+#define AM_REG_GPIO_INT0SET_GPIO30(n)                (((uint32_t)(n) << 30) & 0x40000000)
+
+// GPIO29 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO29_S                 29
+#define AM_REG_GPIO_INT0SET_GPIO29_M                 0x20000000
+#define AM_REG_GPIO_INT0SET_GPIO29(n)                (((uint32_t)(n) << 29) & 0x20000000)
+
+// GPIO28 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO28_S                 28
+#define AM_REG_GPIO_INT0SET_GPIO28_M                 0x10000000
+#define AM_REG_GPIO_INT0SET_GPIO28(n)                (((uint32_t)(n) << 28) & 0x10000000)
+
+// GPIO27 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO27_S                 27
+#define AM_REG_GPIO_INT0SET_GPIO27_M                 0x08000000
+#define AM_REG_GPIO_INT0SET_GPIO27(n)                (((uint32_t)(n) << 27) & 0x08000000)
+
+// GPIO26 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO26_S                 26
+#define AM_REG_GPIO_INT0SET_GPIO26_M                 0x04000000
+#define AM_REG_GPIO_INT0SET_GPIO26(n)                (((uint32_t)(n) << 26) & 0x04000000)
+
+// GPIO25 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO25_S                 25
+#define AM_REG_GPIO_INT0SET_GPIO25_M                 0x02000000
+#define AM_REG_GPIO_INT0SET_GPIO25(n)                (((uint32_t)(n) << 25) & 0x02000000)
+
+// GPIO24 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO24_S                 24
+#define AM_REG_GPIO_INT0SET_GPIO24_M                 0x01000000
+#define AM_REG_GPIO_INT0SET_GPIO24(n)                (((uint32_t)(n) << 24) & 0x01000000)
+
+// GPIO23 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO23_S                 23
+#define AM_REG_GPIO_INT0SET_GPIO23_M                 0x00800000
+#define AM_REG_GPIO_INT0SET_GPIO23(n)                (((uint32_t)(n) << 23) & 0x00800000)
+
+// GPIO22 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO22_S                 22
+#define AM_REG_GPIO_INT0SET_GPIO22_M                 0x00400000
+#define AM_REG_GPIO_INT0SET_GPIO22(n)                (((uint32_t)(n) << 22) & 0x00400000)
+
+// GPIO21 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO21_S                 21
+#define AM_REG_GPIO_INT0SET_GPIO21_M                 0x00200000
+#define AM_REG_GPIO_INT0SET_GPIO21(n)                (((uint32_t)(n) << 21) & 0x00200000)
+
+// GPIO20 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO20_S                 20
+#define AM_REG_GPIO_INT0SET_GPIO20_M                 0x00100000
+#define AM_REG_GPIO_INT0SET_GPIO20(n)                (((uint32_t)(n) << 20) & 0x00100000)
+
+// GPIO19 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO19_S                 19
+#define AM_REG_GPIO_INT0SET_GPIO19_M                 0x00080000
+#define AM_REG_GPIO_INT0SET_GPIO19(n)                (((uint32_t)(n) << 19) & 0x00080000)
+
+// GPIO18interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO18_S                 18
+#define AM_REG_GPIO_INT0SET_GPIO18_M                 0x00040000
+#define AM_REG_GPIO_INT0SET_GPIO18(n)                (((uint32_t)(n) << 18) & 0x00040000)
+
+// GPIO17 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO17_S                 17
+#define AM_REG_GPIO_INT0SET_GPIO17_M                 0x00020000
+#define AM_REG_GPIO_INT0SET_GPIO17(n)                (((uint32_t)(n) << 17) & 0x00020000)
+
+// GPIO16 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO16_S                 16
+#define AM_REG_GPIO_INT0SET_GPIO16_M                 0x00010000
+#define AM_REG_GPIO_INT0SET_GPIO16(n)                (((uint32_t)(n) << 16) & 0x00010000)
+
+// GPIO15 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO15_S                 15
+#define AM_REG_GPIO_INT0SET_GPIO15_M                 0x00008000
+#define AM_REG_GPIO_INT0SET_GPIO15(n)                (((uint32_t)(n) << 15) & 0x00008000)
+
+// GPIO14 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO14_S                 14
+#define AM_REG_GPIO_INT0SET_GPIO14_M                 0x00004000
+#define AM_REG_GPIO_INT0SET_GPIO14(n)                (((uint32_t)(n) << 14) & 0x00004000)
+
+// GPIO13 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO13_S                 13
+#define AM_REG_GPIO_INT0SET_GPIO13_M                 0x00002000
+#define AM_REG_GPIO_INT0SET_GPIO13(n)                (((uint32_t)(n) << 13) & 0x00002000)
+
+// GPIO12 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO12_S                 12
+#define AM_REG_GPIO_INT0SET_GPIO12_M                 0x00001000
+#define AM_REG_GPIO_INT0SET_GPIO12(n)                (((uint32_t)(n) << 12) & 0x00001000)
+
+// GPIO11 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO11_S                 11
+#define AM_REG_GPIO_INT0SET_GPIO11_M                 0x00000800
+#define AM_REG_GPIO_INT0SET_GPIO11(n)                (((uint32_t)(n) << 11) & 0x00000800)
+
+// GPIO10 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO10_S                 10
+#define AM_REG_GPIO_INT0SET_GPIO10_M                 0x00000400
+#define AM_REG_GPIO_INT0SET_GPIO10(n)                (((uint32_t)(n) << 10) & 0x00000400)
+
+// GPIO9 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO9_S                  9
+#define AM_REG_GPIO_INT0SET_GPIO9_M                  0x00000200
+#define AM_REG_GPIO_INT0SET_GPIO9(n)                 (((uint32_t)(n) << 9) & 0x00000200)
+
+// GPIO8 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO8_S                  8
+#define AM_REG_GPIO_INT0SET_GPIO8_M                  0x00000100
+#define AM_REG_GPIO_INT0SET_GPIO8(n)                 (((uint32_t)(n) << 8) & 0x00000100)
+
+// GPIO7 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO7_S                  7
+#define AM_REG_GPIO_INT0SET_GPIO7_M                  0x00000080
+#define AM_REG_GPIO_INT0SET_GPIO7(n)                 (((uint32_t)(n) << 7) & 0x00000080)
+
+// GPIO6 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO6_S                  6
+#define AM_REG_GPIO_INT0SET_GPIO6_M                  0x00000040
+#define AM_REG_GPIO_INT0SET_GPIO6(n)                 (((uint32_t)(n) << 6) & 0x00000040)
+
+// GPIO5 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO5_S                  5
+#define AM_REG_GPIO_INT0SET_GPIO5_M                  0x00000020
+#define AM_REG_GPIO_INT0SET_GPIO5(n)                 (((uint32_t)(n) << 5) & 0x00000020)
+
+// GPIO4 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO4_S                  4
+#define AM_REG_GPIO_INT0SET_GPIO4_M                  0x00000010
+#define AM_REG_GPIO_INT0SET_GPIO4(n)                 (((uint32_t)(n) << 4) & 0x00000010)
+
+// GPIO3 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO3_S                  3
+#define AM_REG_GPIO_INT0SET_GPIO3_M                  0x00000008
+#define AM_REG_GPIO_INT0SET_GPIO3(n)                 (((uint32_t)(n) << 3) & 0x00000008)
+
+// GPIO2 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO2_S                  2
+#define AM_REG_GPIO_INT0SET_GPIO2_M                  0x00000004
+#define AM_REG_GPIO_INT0SET_GPIO2(n)                 (((uint32_t)(n) << 2) & 0x00000004)
+
+// GPIO1 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO1_S                  1
+#define AM_REG_GPIO_INT0SET_GPIO1_M                  0x00000002
+#define AM_REG_GPIO_INT0SET_GPIO1(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// GPIO0 interrupt.
+#define AM_REG_GPIO_INT0SET_GPIO0_S                  0
+#define AM_REG_GPIO_INT0SET_GPIO0_M                  0x00000001
+#define AM_REG_GPIO_INT0SET_GPIO0(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_INT1EN - GPIO Interrupt Registers 49-32: Enable
+//
+//*****************************************************************************
+// GPIO49 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO49_S                  17
+#define AM_REG_GPIO_INT1EN_GPIO49_M                  0x00020000
+#define AM_REG_GPIO_INT1EN_GPIO49(n)                 (((uint32_t)(n) << 17) & 0x00020000)
+
+// GPIO48 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO48_S                  16
+#define AM_REG_GPIO_INT1EN_GPIO48_M                  0x00010000
+#define AM_REG_GPIO_INT1EN_GPIO48(n)                 (((uint32_t)(n) << 16) & 0x00010000)
+
+// GPIO47 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO47_S                  15
+#define AM_REG_GPIO_INT1EN_GPIO47_M                  0x00008000
+#define AM_REG_GPIO_INT1EN_GPIO47(n)                 (((uint32_t)(n) << 15) & 0x00008000)
+
+// GPIO46 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO46_S                  14
+#define AM_REG_GPIO_INT1EN_GPIO46_M                  0x00004000
+#define AM_REG_GPIO_INT1EN_GPIO46(n)                 (((uint32_t)(n) << 14) & 0x00004000)
+
+// GPIO45 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO45_S                  13
+#define AM_REG_GPIO_INT1EN_GPIO45_M                  0x00002000
+#define AM_REG_GPIO_INT1EN_GPIO45(n)                 (((uint32_t)(n) << 13) & 0x00002000)
+
+// GPIO44 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO44_S                  12
+#define AM_REG_GPIO_INT1EN_GPIO44_M                  0x00001000
+#define AM_REG_GPIO_INT1EN_GPIO44(n)                 (((uint32_t)(n) << 12) & 0x00001000)
+
+// GPIO43 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO43_S                  11
+#define AM_REG_GPIO_INT1EN_GPIO43_M                  0x00000800
+#define AM_REG_GPIO_INT1EN_GPIO43(n)                 (((uint32_t)(n) << 11) & 0x00000800)
+
+// GPIO42 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO42_S                  10
+#define AM_REG_GPIO_INT1EN_GPIO42_M                  0x00000400
+#define AM_REG_GPIO_INT1EN_GPIO42(n)                 (((uint32_t)(n) << 10) & 0x00000400)
+
+// GPIO41 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO41_S                  9
+#define AM_REG_GPIO_INT1EN_GPIO41_M                  0x00000200
+#define AM_REG_GPIO_INT1EN_GPIO41(n)                 (((uint32_t)(n) << 9) & 0x00000200)
+
+// GPIO40 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO40_S                  8
+#define AM_REG_GPIO_INT1EN_GPIO40_M                  0x00000100
+#define AM_REG_GPIO_INT1EN_GPIO40(n)                 (((uint32_t)(n) << 8) & 0x00000100)
+
+// GPIO39 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO39_S                  7
+#define AM_REG_GPIO_INT1EN_GPIO39_M                  0x00000080
+#define AM_REG_GPIO_INT1EN_GPIO39(n)                 (((uint32_t)(n) << 7) & 0x00000080)
+
+// GPIO38 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO38_S                  6
+#define AM_REG_GPIO_INT1EN_GPIO38_M                  0x00000040
+#define AM_REG_GPIO_INT1EN_GPIO38(n)                 (((uint32_t)(n) << 6) & 0x00000040)
+
+// GPIO37 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO37_S                  5
+#define AM_REG_GPIO_INT1EN_GPIO37_M                  0x00000020
+#define AM_REG_GPIO_INT1EN_GPIO37(n)                 (((uint32_t)(n) << 5) & 0x00000020)
+
+// GPIO36 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO36_S                  4
+#define AM_REG_GPIO_INT1EN_GPIO36_M                  0x00000010
+#define AM_REG_GPIO_INT1EN_GPIO36(n)                 (((uint32_t)(n) << 4) & 0x00000010)
+
+// GPIO35 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO35_S                  3
+#define AM_REG_GPIO_INT1EN_GPIO35_M                  0x00000008
+#define AM_REG_GPIO_INT1EN_GPIO35(n)                 (((uint32_t)(n) << 3) & 0x00000008)
+
+// GPIO34 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO34_S                  2
+#define AM_REG_GPIO_INT1EN_GPIO34_M                  0x00000004
+#define AM_REG_GPIO_INT1EN_GPIO34(n)                 (((uint32_t)(n) << 2) & 0x00000004)
+
+// GPIO33 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO33_S                  1
+#define AM_REG_GPIO_INT1EN_GPIO33_M                  0x00000002
+#define AM_REG_GPIO_INT1EN_GPIO33(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// GPIO32 interrupt.
+#define AM_REG_GPIO_INT1EN_GPIO32_S                  0
+#define AM_REG_GPIO_INT1EN_GPIO32_M                  0x00000001
+#define AM_REG_GPIO_INT1EN_GPIO32(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_INT1STAT - GPIO Interrupt Registers 49-32: Status
+//
+//*****************************************************************************
+// GPIO49 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO49_S                17
+#define AM_REG_GPIO_INT1STAT_GPIO49_M                0x00020000
+#define AM_REG_GPIO_INT1STAT_GPIO49(n)               (((uint32_t)(n) << 17) & 0x00020000)
+
+// GPIO48 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO48_S                16
+#define AM_REG_GPIO_INT1STAT_GPIO48_M                0x00010000
+#define AM_REG_GPIO_INT1STAT_GPIO48(n)               (((uint32_t)(n) << 16) & 0x00010000)
+
+// GPIO47 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO47_S                15
+#define AM_REG_GPIO_INT1STAT_GPIO47_M                0x00008000
+#define AM_REG_GPIO_INT1STAT_GPIO47(n)               (((uint32_t)(n) << 15) & 0x00008000)
+
+// GPIO46 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO46_S                14
+#define AM_REG_GPIO_INT1STAT_GPIO46_M                0x00004000
+#define AM_REG_GPIO_INT1STAT_GPIO46(n)               (((uint32_t)(n) << 14) & 0x00004000)
+
+// GPIO45 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO45_S                13
+#define AM_REG_GPIO_INT1STAT_GPIO45_M                0x00002000
+#define AM_REG_GPIO_INT1STAT_GPIO45(n)               (((uint32_t)(n) << 13) & 0x00002000)
+
+// GPIO44 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO44_S                12
+#define AM_REG_GPIO_INT1STAT_GPIO44_M                0x00001000
+#define AM_REG_GPIO_INT1STAT_GPIO44(n)               (((uint32_t)(n) << 12) & 0x00001000)
+
+// GPIO43 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO43_S                11
+#define AM_REG_GPIO_INT1STAT_GPIO43_M                0x00000800
+#define AM_REG_GPIO_INT1STAT_GPIO43(n)               (((uint32_t)(n) << 11) & 0x00000800)
+
+// GPIO42 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO42_S                10
+#define AM_REG_GPIO_INT1STAT_GPIO42_M                0x00000400
+#define AM_REG_GPIO_INT1STAT_GPIO42(n)               (((uint32_t)(n) << 10) & 0x00000400)
+
+// GPIO41 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO41_S                9
+#define AM_REG_GPIO_INT1STAT_GPIO41_M                0x00000200
+#define AM_REG_GPIO_INT1STAT_GPIO41(n)               (((uint32_t)(n) << 9) & 0x00000200)
+
+// GPIO40 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO40_S                8
+#define AM_REG_GPIO_INT1STAT_GPIO40_M                0x00000100
+#define AM_REG_GPIO_INT1STAT_GPIO40(n)               (((uint32_t)(n) << 8) & 0x00000100)
+
+// GPIO39 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO39_S                7
+#define AM_REG_GPIO_INT1STAT_GPIO39_M                0x00000080
+#define AM_REG_GPIO_INT1STAT_GPIO39(n)               (((uint32_t)(n) << 7) & 0x00000080)
+
+// GPIO38 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO38_S                6
+#define AM_REG_GPIO_INT1STAT_GPIO38_M                0x00000040
+#define AM_REG_GPIO_INT1STAT_GPIO38(n)               (((uint32_t)(n) << 6) & 0x00000040)
+
+// GPIO37 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO37_S                5
+#define AM_REG_GPIO_INT1STAT_GPIO37_M                0x00000020
+#define AM_REG_GPIO_INT1STAT_GPIO37(n)               (((uint32_t)(n) << 5) & 0x00000020)
+
+// GPIO36 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO36_S                4
+#define AM_REG_GPIO_INT1STAT_GPIO36_M                0x00000010
+#define AM_REG_GPIO_INT1STAT_GPIO36(n)               (((uint32_t)(n) << 4) & 0x00000010)
+
+// GPIO35 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO35_S                3
+#define AM_REG_GPIO_INT1STAT_GPIO35_M                0x00000008
+#define AM_REG_GPIO_INT1STAT_GPIO35(n)               (((uint32_t)(n) << 3) & 0x00000008)
+
+// GPIO34 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO34_S                2
+#define AM_REG_GPIO_INT1STAT_GPIO34_M                0x00000004
+#define AM_REG_GPIO_INT1STAT_GPIO34(n)               (((uint32_t)(n) << 2) & 0x00000004)
+
+// GPIO33 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO33_S                1
+#define AM_REG_GPIO_INT1STAT_GPIO33_M                0x00000002
+#define AM_REG_GPIO_INT1STAT_GPIO33(n)               (((uint32_t)(n) << 1) & 0x00000002)
+
+// GPIO32 interrupt.
+#define AM_REG_GPIO_INT1STAT_GPIO32_S                0
+#define AM_REG_GPIO_INT1STAT_GPIO32_M                0x00000001
+#define AM_REG_GPIO_INT1STAT_GPIO32(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_INT1CLR - GPIO Interrupt Registers 49-32: Clear
+//
+//*****************************************************************************
+// GPIO49 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO49_S                 17
+#define AM_REG_GPIO_INT1CLR_GPIO49_M                 0x00020000
+#define AM_REG_GPIO_INT1CLR_GPIO49(n)                (((uint32_t)(n) << 17) & 0x00020000)
+
+// GPIO48 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO48_S                 16
+#define AM_REG_GPIO_INT1CLR_GPIO48_M                 0x00010000
+#define AM_REG_GPIO_INT1CLR_GPIO48(n)                (((uint32_t)(n) << 16) & 0x00010000)
+
+// GPIO47 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO47_S                 15
+#define AM_REG_GPIO_INT1CLR_GPIO47_M                 0x00008000
+#define AM_REG_GPIO_INT1CLR_GPIO47(n)                (((uint32_t)(n) << 15) & 0x00008000)
+
+// GPIO46 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO46_S                 14
+#define AM_REG_GPIO_INT1CLR_GPIO46_M                 0x00004000
+#define AM_REG_GPIO_INT1CLR_GPIO46(n)                (((uint32_t)(n) << 14) & 0x00004000)
+
+// GPIO45 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO45_S                 13
+#define AM_REG_GPIO_INT1CLR_GPIO45_M                 0x00002000
+#define AM_REG_GPIO_INT1CLR_GPIO45(n)                (((uint32_t)(n) << 13) & 0x00002000)
+
+// GPIO44 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO44_S                 12
+#define AM_REG_GPIO_INT1CLR_GPIO44_M                 0x00001000
+#define AM_REG_GPIO_INT1CLR_GPIO44(n)                (((uint32_t)(n) << 12) & 0x00001000)
+
+// GPIO43 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO43_S                 11
+#define AM_REG_GPIO_INT1CLR_GPIO43_M                 0x00000800
+#define AM_REG_GPIO_INT1CLR_GPIO43(n)                (((uint32_t)(n) << 11) & 0x00000800)
+
+// GPIO42 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO42_S                 10
+#define AM_REG_GPIO_INT1CLR_GPIO42_M                 0x00000400
+#define AM_REG_GPIO_INT1CLR_GPIO42(n)                (((uint32_t)(n) << 10) & 0x00000400)
+
+// GPIO41 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO41_S                 9
+#define AM_REG_GPIO_INT1CLR_GPIO41_M                 0x00000200
+#define AM_REG_GPIO_INT1CLR_GPIO41(n)                (((uint32_t)(n) << 9) & 0x00000200)
+
+// GPIO40 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO40_S                 8
+#define AM_REG_GPIO_INT1CLR_GPIO40_M                 0x00000100
+#define AM_REG_GPIO_INT1CLR_GPIO40(n)                (((uint32_t)(n) << 8) & 0x00000100)
+
+// GPIO39 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO39_S                 7
+#define AM_REG_GPIO_INT1CLR_GPIO39_M                 0x00000080
+#define AM_REG_GPIO_INT1CLR_GPIO39(n)                (((uint32_t)(n) << 7) & 0x00000080)
+
+// GPIO38 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO38_S                 6
+#define AM_REG_GPIO_INT1CLR_GPIO38_M                 0x00000040
+#define AM_REG_GPIO_INT1CLR_GPIO38(n)                (((uint32_t)(n) << 6) & 0x00000040)
+
+// GPIO37 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO37_S                 5
+#define AM_REG_GPIO_INT1CLR_GPIO37_M                 0x00000020
+#define AM_REG_GPIO_INT1CLR_GPIO37(n)                (((uint32_t)(n) << 5) & 0x00000020)
+
+// GPIO36 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO36_S                 4
+#define AM_REG_GPIO_INT1CLR_GPIO36_M                 0x00000010
+#define AM_REG_GPIO_INT1CLR_GPIO36(n)                (((uint32_t)(n) << 4) & 0x00000010)
+
+// GPIO35 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO35_S                 3
+#define AM_REG_GPIO_INT1CLR_GPIO35_M                 0x00000008
+#define AM_REG_GPIO_INT1CLR_GPIO35(n)                (((uint32_t)(n) << 3) & 0x00000008)
+
+// GPIO34 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO34_S                 2
+#define AM_REG_GPIO_INT1CLR_GPIO34_M                 0x00000004
+#define AM_REG_GPIO_INT1CLR_GPIO34(n)                (((uint32_t)(n) << 2) & 0x00000004)
+
+// GPIO33 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO33_S                 1
+#define AM_REG_GPIO_INT1CLR_GPIO33_M                 0x00000002
+#define AM_REG_GPIO_INT1CLR_GPIO33(n)                (((uint32_t)(n) << 1) & 0x00000002)
+
+// GPIO32 interrupt.
+#define AM_REG_GPIO_INT1CLR_GPIO32_S                 0
+#define AM_REG_GPIO_INT1CLR_GPIO32_M                 0x00000001
+#define AM_REG_GPIO_INT1CLR_GPIO32(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_INT1SET - GPIO Interrupt Registers 49-32: Set
+//
+//*****************************************************************************
+// GPIO49 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO49_S                 17
+#define AM_REG_GPIO_INT1SET_GPIO49_M                 0x00020000
+#define AM_REG_GPIO_INT1SET_GPIO49(n)                (((uint32_t)(n) << 17) & 0x00020000)
+
+// GPIO48 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO48_S                 16
+#define AM_REG_GPIO_INT1SET_GPIO48_M                 0x00010000
+#define AM_REG_GPIO_INT1SET_GPIO48(n)                (((uint32_t)(n) << 16) & 0x00010000)
+
+// GPIO47 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO47_S                 15
+#define AM_REG_GPIO_INT1SET_GPIO47_M                 0x00008000
+#define AM_REG_GPIO_INT1SET_GPIO47(n)                (((uint32_t)(n) << 15) & 0x00008000)
+
+// GPIO46 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO46_S                 14
+#define AM_REG_GPIO_INT1SET_GPIO46_M                 0x00004000
+#define AM_REG_GPIO_INT1SET_GPIO46(n)                (((uint32_t)(n) << 14) & 0x00004000)
+
+// GPIO45 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO45_S                 13
+#define AM_REG_GPIO_INT1SET_GPIO45_M                 0x00002000
+#define AM_REG_GPIO_INT1SET_GPIO45(n)                (((uint32_t)(n) << 13) & 0x00002000)
+
+// GPIO44 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO44_S                 12
+#define AM_REG_GPIO_INT1SET_GPIO44_M                 0x00001000
+#define AM_REG_GPIO_INT1SET_GPIO44(n)                (((uint32_t)(n) << 12) & 0x00001000)
+
+// GPIO43 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO43_S                 11
+#define AM_REG_GPIO_INT1SET_GPIO43_M                 0x00000800
+#define AM_REG_GPIO_INT1SET_GPIO43(n)                (((uint32_t)(n) << 11) & 0x00000800)
+
+// GPIO42 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO42_S                 10
+#define AM_REG_GPIO_INT1SET_GPIO42_M                 0x00000400
+#define AM_REG_GPIO_INT1SET_GPIO42(n)                (((uint32_t)(n) << 10) & 0x00000400)
+
+// GPIO41 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO41_S                 9
+#define AM_REG_GPIO_INT1SET_GPIO41_M                 0x00000200
+#define AM_REG_GPIO_INT1SET_GPIO41(n)                (((uint32_t)(n) << 9) & 0x00000200)
+
+// GPIO40 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO40_S                 8
+#define AM_REG_GPIO_INT1SET_GPIO40_M                 0x00000100
+#define AM_REG_GPIO_INT1SET_GPIO40(n)                (((uint32_t)(n) << 8) & 0x00000100)
+
+// GPIO39 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO39_S                 7
+#define AM_REG_GPIO_INT1SET_GPIO39_M                 0x00000080
+#define AM_REG_GPIO_INT1SET_GPIO39(n)                (((uint32_t)(n) << 7) & 0x00000080)
+
+// GPIO38 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO38_S                 6
+#define AM_REG_GPIO_INT1SET_GPIO38_M                 0x00000040
+#define AM_REG_GPIO_INT1SET_GPIO38(n)                (((uint32_t)(n) << 6) & 0x00000040)
+
+// GPIO37 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO37_S                 5
+#define AM_REG_GPIO_INT1SET_GPIO37_M                 0x00000020
+#define AM_REG_GPIO_INT1SET_GPIO37(n)                (((uint32_t)(n) << 5) & 0x00000020)
+
+// GPIO36 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO36_S                 4
+#define AM_REG_GPIO_INT1SET_GPIO36_M                 0x00000010
+#define AM_REG_GPIO_INT1SET_GPIO36(n)                (((uint32_t)(n) << 4) & 0x00000010)
+
+// GPIO35 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO35_S                 3
+#define AM_REG_GPIO_INT1SET_GPIO35_M                 0x00000008
+#define AM_REG_GPIO_INT1SET_GPIO35(n)                (((uint32_t)(n) << 3) & 0x00000008)
+
+// GPIO34 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO34_S                 2
+#define AM_REG_GPIO_INT1SET_GPIO34_M                 0x00000004
+#define AM_REG_GPIO_INT1SET_GPIO34(n)                (((uint32_t)(n) << 2) & 0x00000004)
+
+// GPIO33 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO33_S                 1
+#define AM_REG_GPIO_INT1SET_GPIO33_M                 0x00000002
+#define AM_REG_GPIO_INT1SET_GPIO33(n)                (((uint32_t)(n) << 1) & 0x00000002)
+
+// GPIO32 interrupt.
+#define AM_REG_GPIO_INT1SET_GPIO32_S                 0
+#define AM_REG_GPIO_INT1SET_GPIO32_M                 0x00000001
+#define AM_REG_GPIO_INT1SET_GPIO32(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_PADREGA - Pad Configuration Register A
+//
+//*****************************************************************************
+// Pad 3 function select
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_S             27
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_M             0x38000000
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL(n)            (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_UA0RTS        0x00000000
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_SLnCE         0x08000000
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_M1nCE4        0x10000000
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_GPIO3         0x18000000
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_MxnCELB       0x20000000
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_M2nCE0        0x28000000
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_TRIG1         0x30000000
+#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK      0x38000000
+
+// Pad 3 drive strength.
+#define AM_REG_GPIO_PADREGA_PAD3STRNG_S              26
+#define AM_REG_GPIO_PADREGA_PAD3STRNG_M              0x04000000
+#define AM_REG_GPIO_PADREGA_PAD3STRNG(n)             (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGA_PAD3STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGA_PAD3STRNG_HIGH           0x04000000
+
+// Pad 3 input enable.
+#define AM_REG_GPIO_PADREGA_PAD3INPEN_S              25
+#define AM_REG_GPIO_PADREGA_PAD3INPEN_M              0x02000000
+#define AM_REG_GPIO_PADREGA_PAD3INPEN(n)             (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGA_PAD3INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGA_PAD3INPEN_EN             0x02000000
+
+// Pad 3 pullup enable
+#define AM_REG_GPIO_PADREGA_PAD3PULL_S               24
+#define AM_REG_GPIO_PADREGA_PAD3PULL_M               0x01000000
+#define AM_REG_GPIO_PADREGA_PAD3PULL(n)              (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGA_PAD3PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGA_PAD3PULL_EN              0x01000000
+
+// Pad 2 function select
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_S             19
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_M             0x00380000
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL(n)            (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_SLWIR3        0x00000000
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_SLMOSI        0x00080000
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_UART0RX       0x00100000
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_GPIO2         0x00180000
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_MxMOSILB      0x00200000
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_M2MOSI        0x00280000
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_MxWIR3LB      0x00300000
+#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_M2WIR3        0x00380000
+
+// Pad 2 drive strength
+#define AM_REG_GPIO_PADREGA_PAD2STRNG_S              18
+#define AM_REG_GPIO_PADREGA_PAD2STRNG_M              0x00040000
+#define AM_REG_GPIO_PADREGA_PAD2STRNG(n)             (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGA_PAD2STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGA_PAD2STRNG_HIGH           0x00040000
+
+// Pad 2 input enable
+#define AM_REG_GPIO_PADREGA_PAD2INPEN_S              17
+#define AM_REG_GPIO_PADREGA_PAD2INPEN_M              0x00020000
+#define AM_REG_GPIO_PADREGA_PAD2INPEN(n)             (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGA_PAD2INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGA_PAD2INPEN_EN             0x00020000
+
+// Pad 2 pullup enable
+#define AM_REG_GPIO_PADREGA_PAD2PULL_S               16
+#define AM_REG_GPIO_PADREGA_PAD2PULL_M               0x00010000
+#define AM_REG_GPIO_PADREGA_PAD2PULL(n)              (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGA_PAD2PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGA_PAD2PULL_EN              0x00010000
+
+// Pad 1 pullup resistor selection.
+#define AM_REG_GPIO_PADREGA_PAD1RSEL_S               14
+#define AM_REG_GPIO_PADREGA_PAD1RSEL_M               0x0000C000
+#define AM_REG_GPIO_PADREGA_PAD1RSEL(n)              (((uint32_t)(n) << 14) & 0x0000C000)
+#define AM_REG_GPIO_PADREGA_PAD1RSEL_PULL1_5K        0x00000000
+#define AM_REG_GPIO_PADREGA_PAD1RSEL_PULL6K          0x00004000
+#define AM_REG_GPIO_PADREGA_PAD1RSEL_PULL12K         0x00008000
+#define AM_REG_GPIO_PADREGA_PAD1RSEL_PULL24K         0x0000C000
+
+// Pad 1 function select
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_S             11
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_M             0x00003800
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL(n)            (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_SLSDA         0x00000000
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_SLMISO        0x00000800
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_UART0TX       0x00001000
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_GPIO1         0x00001800
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_MxMISOLB      0x00002000
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_M2MISO        0x00002800
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_MxSDALB       0x00003000
+#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_M2SDA         0x00003800
+
+// Pad 1 drive strength
+#define AM_REG_GPIO_PADREGA_PAD1STRNG_S              10
+#define AM_REG_GPIO_PADREGA_PAD1STRNG_M              0x00000400
+#define AM_REG_GPIO_PADREGA_PAD1STRNG(n)             (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGA_PAD1STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGA_PAD1STRNG_HIGH           0x00000400
+
+// Pad 1 input enable
+#define AM_REG_GPIO_PADREGA_PAD1INPEN_S              9
+#define AM_REG_GPIO_PADREGA_PAD1INPEN_M              0x00000200
+#define AM_REG_GPIO_PADREGA_PAD1INPEN(n)             (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGA_PAD1INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGA_PAD1INPEN_EN             0x00000200
+
+// Pad 1 pullup enable
+#define AM_REG_GPIO_PADREGA_PAD1PULL_S               8
+#define AM_REG_GPIO_PADREGA_PAD1PULL_M               0x00000100
+#define AM_REG_GPIO_PADREGA_PAD1PULL(n)              (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGA_PAD1PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGA_PAD1PULL_EN              0x00000100
+
+// Pad 0 pullup resistor selection.
+#define AM_REG_GPIO_PADREGA_PAD0RSEL_S               6
+#define AM_REG_GPIO_PADREGA_PAD0RSEL_M               0x000000C0
+#define AM_REG_GPIO_PADREGA_PAD0RSEL(n)              (((uint32_t)(n) << 6) & 0x000000C0)
+#define AM_REG_GPIO_PADREGA_PAD0RSEL_PULL1_5K        0x00000000
+#define AM_REG_GPIO_PADREGA_PAD0RSEL_PULL6K          0x00000040
+#define AM_REG_GPIO_PADREGA_PAD0RSEL_PULL12K         0x00000080
+#define AM_REG_GPIO_PADREGA_PAD0RSEL_PULL24K         0x000000C0
+
+// Pad 0 function select
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_S             3
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_M             0x00000038
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL(n)            (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_SLSCL         0x00000000
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_SLSCK         0x00000008
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_CLKOUT        0x00000010
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_GPIO0         0x00000018
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_MxSCKLB       0x00000020
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_M2SCK         0x00000028
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_MxSCLLB       0x00000030
+#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_M2SCL         0x00000038
+
+// Pad 0 drive strength
+#define AM_REG_GPIO_PADREGA_PAD0STRNG_S              2
+#define AM_REG_GPIO_PADREGA_PAD0STRNG_M              0x00000004
+#define AM_REG_GPIO_PADREGA_PAD0STRNG(n)             (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGA_PAD0STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGA_PAD0STRNG_HIGH           0x00000004
+
+// Pad 0 input enable
+#define AM_REG_GPIO_PADREGA_PAD0INPEN_S              1
+#define AM_REG_GPIO_PADREGA_PAD0INPEN_M              0x00000002
+#define AM_REG_GPIO_PADREGA_PAD0INPEN(n)             (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGA_PAD0INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGA_PAD0INPEN_EN             0x00000002
+
+// Pad 0 pullup enable
+#define AM_REG_GPIO_PADREGA_PAD0PULL_S               0
+#define AM_REG_GPIO_PADREGA_PAD0PULL_M               0x00000001
+#define AM_REG_GPIO_PADREGA_PAD0PULL(n)              (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGA_PAD0PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGA_PAD0PULL_EN              0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGB - Pad Configuration Register B
+//
+//*****************************************************************************
+// Pad 7 function select
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_S             27
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M             0x38000000
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL(n)            (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M0WIR3        0x00000000
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M0MOSI        0x08000000
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_CLKOUT        0x10000000
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_GPIO7         0x18000000
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_TRIG0         0x20000000
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_UART0TX       0x28000000
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_SLWIR3LB      0x30000000
+#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M1nCE1        0x38000000
+
+// Pad 7 drive strentgh
+#define AM_REG_GPIO_PADREGB_PAD7STRNG_S              26
+#define AM_REG_GPIO_PADREGB_PAD7STRNG_M              0x04000000
+#define AM_REG_GPIO_PADREGB_PAD7STRNG(n)             (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGB_PAD7STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD7STRNG_HIGH           0x04000000
+
+// Pad 7 input enable
+#define AM_REG_GPIO_PADREGB_PAD7INPEN_S              25
+#define AM_REG_GPIO_PADREGB_PAD7INPEN_M              0x02000000
+#define AM_REG_GPIO_PADREGB_PAD7INPEN(n)             (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGB_PAD7INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD7INPEN_EN             0x02000000
+
+// Pad 7 pullup enable
+#define AM_REG_GPIO_PADREGB_PAD7PULL_S               24
+#define AM_REG_GPIO_PADREGB_PAD7PULL_M               0x01000000
+#define AM_REG_GPIO_PADREGB_PAD7PULL(n)              (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGB_PAD7PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGB_PAD7PULL_EN              0x01000000
+
+// Pad 6 pullup resistor selection.
+#define AM_REG_GPIO_PADREGB_PAD6RSEL_S               22
+#define AM_REG_GPIO_PADREGB_PAD6RSEL_M               0x00C00000
+#define AM_REG_GPIO_PADREGB_PAD6RSEL(n)              (((uint32_t)(n) << 22) & 0x00C00000)
+#define AM_REG_GPIO_PADREGB_PAD6RSEL_PULL1_5K        0x00000000
+#define AM_REG_GPIO_PADREGB_PAD6RSEL_PULL6K          0x00400000
+#define AM_REG_GPIO_PADREGB_PAD6RSEL_PULL12K         0x00800000
+#define AM_REG_GPIO_PADREGB_PAD6RSEL_PULL24K         0x00C00000
+
+// Pad 6 function select
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_S             19
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_M             0x00380000
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL(n)            (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_M0SDA         0x00000000
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_M0MISO        0x00080000
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_UA0CTS        0x00100000
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_GPIO6         0x00180000
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_SLMISOLB      0x00200000
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_M1nCE0        0x00280000
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_SLSDALB       0x00300000
+#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_I2S_DAT       0x00380000
+
+// Pad 6 drive strength
+#define AM_REG_GPIO_PADREGB_PAD6STRNG_S              18
+#define AM_REG_GPIO_PADREGB_PAD6STRNG_M              0x00040000
+#define AM_REG_GPIO_PADREGB_PAD6STRNG(n)             (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGB_PAD6STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD6STRNG_HIGH           0x00040000
+
+// Pad 6 input enable
+#define AM_REG_GPIO_PADREGB_PAD6INPEN_S              17
+#define AM_REG_GPIO_PADREGB_PAD6INPEN_M              0x00020000
+#define AM_REG_GPIO_PADREGB_PAD6INPEN(n)             (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGB_PAD6INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD6INPEN_EN             0x00020000
+
+// Pad 6 pullup enable
+#define AM_REG_GPIO_PADREGB_PAD6PULL_S               16
+#define AM_REG_GPIO_PADREGB_PAD6PULL_M               0x00010000
+#define AM_REG_GPIO_PADREGB_PAD6PULL(n)              (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGB_PAD6PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGB_PAD6PULL_EN              0x00010000
+
+// Pad 5 pullup resistor selection.
+#define AM_REG_GPIO_PADREGB_PAD5RSEL_S               14
+#define AM_REG_GPIO_PADREGB_PAD5RSEL_M               0x0000C000
+#define AM_REG_GPIO_PADREGB_PAD5RSEL(n)              (((uint32_t)(n) << 14) & 0x0000C000)
+#define AM_REG_GPIO_PADREGB_PAD5RSEL_PULL1_5K        0x00000000
+#define AM_REG_GPIO_PADREGB_PAD5RSEL_PULL6K          0x00004000
+#define AM_REG_GPIO_PADREGB_PAD5RSEL_PULL12K         0x00008000
+#define AM_REG_GPIO_PADREGB_PAD5RSEL_PULL24K         0x0000C000
+
+// Pad 5 function select
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_S             11
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M             0x00003800
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL(n)            (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M0SCL         0x00000000
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M0SCK         0x00000800
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_UA0RTS        0x00001000
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_GPIO5         0x00001800
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M0SCKLB       0x00002000
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_EXTHFA        0x00002800
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M0SCLLB       0x00003000
+#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M1nCE2        0x00003800
+
+// Pad 5 drive strength
+#define AM_REG_GPIO_PADREGB_PAD5STRNG_S              10
+#define AM_REG_GPIO_PADREGB_PAD5STRNG_M              0x00000400
+#define AM_REG_GPIO_PADREGB_PAD5STRNG(n)             (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGB_PAD5STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD5STRNG_HIGH           0x00000400
+
+// Pad 5 input enable
+#define AM_REG_GPIO_PADREGB_PAD5INPEN_S              9
+#define AM_REG_GPIO_PADREGB_PAD5INPEN_M              0x00000200
+#define AM_REG_GPIO_PADREGB_PAD5INPEN(n)             (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGB_PAD5INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD5INPEN_EN             0x00000200
+
+// Pad 5 pullup enable
+#define AM_REG_GPIO_PADREGB_PAD5PULL_S               8
+#define AM_REG_GPIO_PADREGB_PAD5PULL_M               0x00000100
+#define AM_REG_GPIO_PADREGB_PAD5PULL(n)              (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGB_PAD5PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGB_PAD5PULL_EN              0x00000100
+
+// Pad 4 VSS power switch enable
+#define AM_REG_GPIO_PADREGB_PAD4PWRDN_S              7
+#define AM_REG_GPIO_PADREGB_PAD4PWRDN_M              0x00000080
+#define AM_REG_GPIO_PADREGB_PAD4PWRDN(n)             (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_GPIO_PADREGB_PAD4PWRDN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD4PWRDN_EN             0x00000080
+
+// Pad 4 function select
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_S             3
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_M             0x00000038
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL(n)            (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_UA0CTS        0x00000000
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_SLINT         0x00000008
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_M0nCE5        0x00000010
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_GPIO4         0x00000018
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_SLINTGP       0x00000020
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_M2nCE5        0x00000028
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_CLKOUT        0x00000030
+#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_32khz_XT      0x00000038
+
+// Pad 4 drive strength
+#define AM_REG_GPIO_PADREGB_PAD4STRNG_S              2
+#define AM_REG_GPIO_PADREGB_PAD4STRNG_M              0x00000004
+#define AM_REG_GPIO_PADREGB_PAD4STRNG(n)             (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGB_PAD4STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD4STRNG_HIGH           0x00000004
+
+// Pad 4 input enable
+#define AM_REG_GPIO_PADREGB_PAD4INPEN_S              1
+#define AM_REG_GPIO_PADREGB_PAD4INPEN_M              0x00000002
+#define AM_REG_GPIO_PADREGB_PAD4INPEN(n)             (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGB_PAD4INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGB_PAD4INPEN_EN             0x00000002
+
+// Pad 4 pullup enable
+#define AM_REG_GPIO_PADREGB_PAD4PULL_S               0
+#define AM_REG_GPIO_PADREGB_PAD4PULL_M               0x00000001
+#define AM_REG_GPIO_PADREGB_PAD4PULL(n)              (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGB_PAD4PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGB_PAD4PULL_EN              0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGC - Pad Configuration Register C
+//
+//*****************************************************************************
+// Pad 11 function select
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_S            27
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_ADCSE2       0x00000000
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_M0nCE0       0x08000000
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_CLKOUT       0x10000000
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_GPIO11       0x18000000
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_M2nCE7       0x20000000
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_UA1CTS       0x28000000
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_UART0RX      0x30000000
+#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_PDM_DATA     0x38000000
+
+// Pad 11 drive strentgh
+#define AM_REG_GPIO_PADREGC_PAD11STRNG_S             26
+#define AM_REG_GPIO_PADREGC_PAD11STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGC_PAD11STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGC_PAD11STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGC_PAD11STRNG_HIGH          0x04000000
+
+// Pad 11 input enable
+#define AM_REG_GPIO_PADREGC_PAD11INPEN_S             25
+#define AM_REG_GPIO_PADREGC_PAD11INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGC_PAD11INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGC_PAD11INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGC_PAD11INPEN_EN            0x02000000
+
+// Pad 11 pullup enable
+#define AM_REG_GPIO_PADREGC_PAD11PULL_S              24
+#define AM_REG_GPIO_PADREGC_PAD11PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGC_PAD11PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGC_PAD11PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGC_PAD11PULL_EN             0x01000000
+
+// Pad 10 function select
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_S            19
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M1WIR3       0x00000000
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M1MOSI       0x00080000
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M0nCE6       0x00100000
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_GPIO10       0x00180000
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M2nCE6       0x00200000
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_UA1RTS       0x00280000
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M4nCE4       0x00300000
+#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_SLWIR3LB     0x00380000
+
+// Pad 10 drive strength
+#define AM_REG_GPIO_PADREGC_PAD10STRNG_S             18
+#define AM_REG_GPIO_PADREGC_PAD10STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGC_PAD10STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGC_PAD10STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGC_PAD10STRNG_HIGH          0x00040000
+
+// Pad 10 input enable
+#define AM_REG_GPIO_PADREGC_PAD10INPEN_S             17
+#define AM_REG_GPIO_PADREGC_PAD10INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGC_PAD10INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGC_PAD10INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGC_PAD10INPEN_EN            0x00020000
+
+// Pad 10 pullup enable
+#define AM_REG_GPIO_PADREGC_PAD10PULL_S              16
+#define AM_REG_GPIO_PADREGC_PAD10PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGC_PAD10PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGC_PAD10PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGC_PAD10PULL_EN             0x00010000
+
+// Pad 9 pullup resistor selection
+#define AM_REG_GPIO_PADREGC_PAD9RSEL_S               14
+#define AM_REG_GPIO_PADREGC_PAD9RSEL_M               0x0000C000
+#define AM_REG_GPIO_PADREGC_PAD9RSEL(n)              (((uint32_t)(n) << 14) & 0x0000C000)
+#define AM_REG_GPIO_PADREGC_PAD9RSEL_PULL1_5K        0x00000000
+#define AM_REG_GPIO_PADREGC_PAD9RSEL_PULL6K          0x00004000
+#define AM_REG_GPIO_PADREGC_PAD9RSEL_PULL12K         0x00008000
+#define AM_REG_GPIO_PADREGC_PAD9RSEL_PULL24K         0x0000C000
+
+// Pad 9 function select
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_S             11
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M             0x00003800
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL(n)            (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M1SDA         0x00000000
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M1MISO        0x00000800
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M0nCE5        0x00001000
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_GPIO9         0x00001800
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M4nCE5        0x00002000
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_SLMISOLB      0x00002800
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_UART1RX       0x00003000
+#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_SLSDALB       0x00003800
+
+// Pad 9 drive strength
+#define AM_REG_GPIO_PADREGC_PAD9STRNG_S              10
+#define AM_REG_GPIO_PADREGC_PAD9STRNG_M              0x00000400
+#define AM_REG_GPIO_PADREGC_PAD9STRNG(n)             (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGC_PAD9STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGC_PAD9STRNG_HIGH           0x00000400
+
+// Pad 9 input enable
+#define AM_REG_GPIO_PADREGC_PAD9INPEN_S              9
+#define AM_REG_GPIO_PADREGC_PAD9INPEN_M              0x00000200
+#define AM_REG_GPIO_PADREGC_PAD9INPEN(n)             (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGC_PAD9INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGC_PAD9INPEN_EN             0x00000200
+
+// Pad 9 pullup enable
+#define AM_REG_GPIO_PADREGC_PAD9PULL_S               8
+#define AM_REG_GPIO_PADREGC_PAD9PULL_M               0x00000100
+#define AM_REG_GPIO_PADREGC_PAD9PULL(n)              (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGC_PAD9PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGC_PAD9PULL_EN              0x00000100
+
+// Pad 8 pullup resistor selection.
+#define AM_REG_GPIO_PADREGC_PAD8RSEL_S               6
+#define AM_REG_GPIO_PADREGC_PAD8RSEL_M               0x000000C0
+#define AM_REG_GPIO_PADREGC_PAD8RSEL(n)              (((uint32_t)(n) << 6) & 0x000000C0)
+#define AM_REG_GPIO_PADREGC_PAD8RSEL_PULL1_5K        0x00000000
+#define AM_REG_GPIO_PADREGC_PAD8RSEL_PULL6K          0x00000040
+#define AM_REG_GPIO_PADREGC_PAD8RSEL_PULL12K         0x00000080
+#define AM_REG_GPIO_PADREGC_PAD8RSEL_PULL24K         0x000000C0
+
+// Pad 8 function select
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_S             3
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M             0x00000038
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL(n)            (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M1SCL         0x00000000
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M1SCK         0x00000008
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M0nCE4        0x00000010
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_GPIO8         0x00000018
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M2nCE4        0x00000020
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M1SCKLB       0x00000028
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_UART1TX       0x00000030
+#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M1SCLLB       0x00000038
+
+// Pad 8 drive strength
+#define AM_REG_GPIO_PADREGC_PAD8STRNG_S              2
+#define AM_REG_GPIO_PADREGC_PAD8STRNG_M              0x00000004
+#define AM_REG_GPIO_PADREGC_PAD8STRNG(n)             (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGC_PAD8STRNG_LOW            0x00000000
+#define AM_REG_GPIO_PADREGC_PAD8STRNG_HIGH           0x00000004
+
+// Pad 8 input enable
+#define AM_REG_GPIO_PADREGC_PAD8INPEN_S              1
+#define AM_REG_GPIO_PADREGC_PAD8INPEN_M              0x00000002
+#define AM_REG_GPIO_PADREGC_PAD8INPEN(n)             (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGC_PAD8INPEN_DIS            0x00000000
+#define AM_REG_GPIO_PADREGC_PAD8INPEN_EN             0x00000002
+
+// Pad 8 pullup enable
+#define AM_REG_GPIO_PADREGC_PAD8PULL_S               0
+#define AM_REG_GPIO_PADREGC_PAD8PULL_M               0x00000001
+#define AM_REG_GPIO_PADREGC_PAD8PULL(n)              (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGC_PAD8PULL_DIS             0x00000000
+#define AM_REG_GPIO_PADREGC_PAD8PULL_EN              0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGD - Pad Configuration Register D
+//
+//*****************************************************************************
+// Pad 15 function select
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_S            27
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_ADCD1N       0x00000000
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_M1nCE3       0x08000000
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_UART1RX      0x10000000
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_GPIO15       0x18000000
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_M2nCE2       0x20000000
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_EXTXT        0x28000000
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWDIO        0x30000000
+#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWO          0x38000000
+
+// Pad 15 drive strentgh
+#define AM_REG_GPIO_PADREGD_PAD15STRNG_S             26
+#define AM_REG_GPIO_PADREGD_PAD15STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGD_PAD15STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGD_PAD15STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGD_PAD15STRNG_HIGH          0x04000000
+
+// Pad 15 input enable
+#define AM_REG_GPIO_PADREGD_PAD15INPEN_S             25
+#define AM_REG_GPIO_PADREGD_PAD15INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGD_PAD15INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGD_PAD15INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGD_PAD15INPEN_EN            0x02000000
+
+// Pad 15 pullup enable
+#define AM_REG_GPIO_PADREGD_PAD15PULL_S              24
+#define AM_REG_GPIO_PADREGD_PAD15PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGD_PAD15PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGD_PAD15PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGD_PAD15PULL_EN             0x01000000
+
+// Pad 14 function select
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_S            19
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_ADCD1P       0x00000000
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_M1nCE2       0x00080000
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_UART1TX      0x00100000
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_GPIO14       0x00180000
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_M2nCE1       0x00200000
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_EXTHFS       0x00280000
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_SWDCK        0x00300000
+#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_32khz_XT     0x00380000
+
+// Pad 14 drive strength
+#define AM_REG_GPIO_PADREGD_PAD14STRNG_S             18
+#define AM_REG_GPIO_PADREGD_PAD14STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGD_PAD14STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGD_PAD14STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGD_PAD14STRNG_HIGH          0x00040000
+
+// Pad 14 input enable
+#define AM_REG_GPIO_PADREGD_PAD14INPEN_S             17
+#define AM_REG_GPIO_PADREGD_PAD14INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGD_PAD14INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGD_PAD14INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGD_PAD14INPEN_EN            0x00020000
+
+// Pad 14 pullup enable
+#define AM_REG_GPIO_PADREGD_PAD14PULL_S              16
+#define AM_REG_GPIO_PADREGD_PAD14PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGD_PAD14PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGD_PAD14PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGD_PAD14PULL_EN             0x00010000
+
+// Pad 13 function select
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_S            11
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8    0x00000000
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_M1nCE1       0x00000800
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_TCTB0        0x00001000
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_GPIO13       0x00001800
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_M2nCE3       0x00002000
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_EXTHFB       0x00002800
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_UA0RTS       0x00003000
+#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_UART1RX      0x00003800
+
+// Pad 13 drive strength
+#define AM_REG_GPIO_PADREGD_PAD13STRNG_S             10
+#define AM_REG_GPIO_PADREGD_PAD13STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGD_PAD13STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGD_PAD13STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGD_PAD13STRNG_HIGH          0x00000400
+
+// Pad 13 input enable
+#define AM_REG_GPIO_PADREGD_PAD13INPEN_S             9
+#define AM_REG_GPIO_PADREGD_PAD13INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGD_PAD13INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGD_PAD13INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGD_PAD13INPEN_EN            0x00000200
+
+// Pad 13 pullup enable
+#define AM_REG_GPIO_PADREGD_PAD13PULL_S              8
+#define AM_REG_GPIO_PADREGD_PAD13PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGD_PAD13PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGD_PAD13PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGD_PAD13PULL_EN             0x00000100
+
+// Pad 12 function select
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_S            3
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9    0x00000000
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_M1nCE0       0x00000008
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_TCTA0        0x00000010
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_GPIO12       0x00000018
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_CLKOUT       0x00000020
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_PDM_CLK      0x00000028
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_UA0CTS       0x00000030
+#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_UART1TX      0x00000038
+
+// Pad 12 drive strength
+#define AM_REG_GPIO_PADREGD_PAD12STRNG_S             2
+#define AM_REG_GPIO_PADREGD_PAD12STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGD_PAD12STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGD_PAD12STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGD_PAD12STRNG_HIGH          0x00000004
+
+// Pad 12 input enable
+#define AM_REG_GPIO_PADREGD_PAD12INPEN_S             1
+#define AM_REG_GPIO_PADREGD_PAD12INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGD_PAD12INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGD_PAD12INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGD_PAD12INPEN_EN            0x00000002
+
+// Pad 12 pullup enable
+#define AM_REG_GPIO_PADREGD_PAD12PULL_S              0
+#define AM_REG_GPIO_PADREGD_PAD12PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGD_PAD12PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGD_PAD12PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGD_PAD12PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGE - Pad Configuration Register E
+//
+//*****************************************************************************
+// Pad 19 function select
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_S            27
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_CMPRF0       0x00000000
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_M0nCE3       0x08000000
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_TCTB1        0x10000000
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_GPIO19       0x18000000
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_TCTA1        0x20000000
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_ANATEST1     0x28000000
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_UART1RX      0x30000000
+#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_I2S_BCLK     0x38000000
+
+// Pad 19 drive strentgh
+#define AM_REG_GPIO_PADREGE_PAD19STRNG_S             26
+#define AM_REG_GPIO_PADREGE_PAD19STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGE_PAD19STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGE_PAD19STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGE_PAD19STRNG_HIGH          0x04000000
+
+// Pad 19 input enable
+#define AM_REG_GPIO_PADREGE_PAD19INPEN_S             25
+#define AM_REG_GPIO_PADREGE_PAD19INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGE_PAD19INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGE_PAD19INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGE_PAD19INPEN_EN            0x02000000
+
+// Pad 19 pullup enable
+#define AM_REG_GPIO_PADREGE_PAD19PULL_S              24
+#define AM_REG_GPIO_PADREGE_PAD19PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGE_PAD19PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGE_PAD19PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGE_PAD19PULL_EN             0x01000000
+
+// Pad 18 function select
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_S            19
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_CMPIN1       0x00000000
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_M0nCE2       0x00080000
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_TCTA1        0x00100000
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_GPIO18       0x00180000
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_M4nCE1       0x00200000
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_ANATEST2     0x00280000
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_UART1TX      0x00300000
+#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_32khz_XT     0x00380000
+
+// Pad 18 drive strength
+#define AM_REG_GPIO_PADREGE_PAD18STRNG_S             18
+#define AM_REG_GPIO_PADREGE_PAD18STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGE_PAD18STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGE_PAD18STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGE_PAD18STRNG_HIGH          0x00040000
+
+// Pad 18 input enable
+#define AM_REG_GPIO_PADREGE_PAD18INPEN_S             17
+#define AM_REG_GPIO_PADREGE_PAD18INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGE_PAD18INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGE_PAD18INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGE_PAD18INPEN_EN            0x00020000
+
+// Pad 18 pullup enable
+#define AM_REG_GPIO_PADREGE_PAD18PULL_S              16
+#define AM_REG_GPIO_PADREGE_PAD18PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGE_PAD18PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGE_PAD18PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGE_PAD18PULL_EN             0x00010000
+
+// Pad 17 function select
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_S            11
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_CMPRF1       0x00000000
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_M0nCE1       0x00000800
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_TRIG1        0x00001000
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_GPIO17       0x00001800
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_M4nCE3       0x00002000
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_EXTLF        0x00002800
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_UART0RX      0x00003000
+#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_UA1CTS       0x00003800
+
+// Pad 17 drive strength
+#define AM_REG_GPIO_PADREGE_PAD17STRNG_S             10
+#define AM_REG_GPIO_PADREGE_PAD17STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGE_PAD17STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGE_PAD17STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGE_PAD17STRNG_HIGH          0x00000400
+
+// Pad 17 input enable
+#define AM_REG_GPIO_PADREGE_PAD17INPEN_S             9
+#define AM_REG_GPIO_PADREGE_PAD17INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGE_PAD17INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGE_PAD17INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGE_PAD17INPEN_EN            0x00000200
+
+// Pad 17 pullup enable
+#define AM_REG_GPIO_PADREGE_PAD17PULL_S              8
+#define AM_REG_GPIO_PADREGE_PAD17PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGE_PAD17PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGE_PAD17PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGE_PAD17PULL_EN             0x00000100
+
+// Pad 16 function select
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_S            3
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_ADCSE0       0x00000000
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_M0nCE4       0x00000008
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_TRIG0        0x00000010
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_GPIO16       0x00000018
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_M2nCE3       0x00000020
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_CMPIN0       0x00000028
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_UART0TX      0x00000030
+#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_UA1RTS       0x00000038
+
+// Pad 16 drive strength
+#define AM_REG_GPIO_PADREGE_PAD16STRNG_S             2
+#define AM_REG_GPIO_PADREGE_PAD16STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGE_PAD16STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGE_PAD16STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGE_PAD16STRNG_HIGH          0x00000004
+
+// Pad 16 input enable
+#define AM_REG_GPIO_PADREGE_PAD16INPEN_S             1
+#define AM_REG_GPIO_PADREGE_PAD16INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGE_PAD16INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGE_PAD16INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGE_PAD16INPEN_EN            0x00000002
+
+// Pad 16 pullup enable
+#define AM_REG_GPIO_PADREGE_PAD16PULL_S              0
+#define AM_REG_GPIO_PADREGE_PAD16PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGE_PAD16PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGE_PAD16PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGE_PAD16PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGF - Pad Configuration Register F
+//
+//*****************************************************************************
+// Pad 23 function select
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_S            27
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_UART0RX      0x00000000
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_M0nCE0       0x08000000
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_TCTB3        0x10000000
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_GPIO23       0x18000000
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_PDM_DATA     0x20000000
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_CMPOUT       0x28000000
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_TCTB1        0x30000000
+#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_UNDEF7       0x38000000
+
+// Pad 23 drive strentgh
+#define AM_REG_GPIO_PADREGF_PAD23STRNG_S             26
+#define AM_REG_GPIO_PADREGF_PAD23STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGF_PAD23STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGF_PAD23STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD23STRNG_HIGH          0x04000000
+
+// Pad 23 input enable
+#define AM_REG_GPIO_PADREGF_PAD23INPEN_S             25
+#define AM_REG_GPIO_PADREGF_PAD23INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGF_PAD23INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGF_PAD23INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD23INPEN_EN            0x02000000
+
+// Pad 23 pullup enable
+#define AM_REG_GPIO_PADREGF_PAD23PULL_S              24
+#define AM_REG_GPIO_PADREGF_PAD23PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGF_PAD23PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGF_PAD23PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGF_PAD23PULL_EN             0x01000000
+
+// Pad 22  upper power switch enable
+#define AM_REG_GPIO_PADREGF_PAD22PWRUP_S             23
+#define AM_REG_GPIO_PADREGF_PAD22PWRUP_M             0x00800000
+#define AM_REG_GPIO_PADREGF_PAD22PWRUP(n)            (((uint32_t)(n) << 23) & 0x00800000)
+#define AM_REG_GPIO_PADREGF_PAD22PWRUP_DIS           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD22PWRUP_EN            0x00800000
+
+// Pad 22 function select
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_S            19
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_UART0TX      0x00000000
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_M1nCE7       0x00080000
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_TCTA3        0x00100000
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_GPIO22       0x00180000
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_PDM_CLK      0x00200000
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_UNDEF5       0x00280000
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_TCTB1        0x00300000
+#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_SWO          0x00380000
+
+// Pad 22 drive strength
+#define AM_REG_GPIO_PADREGF_PAD22STRNG_S             18
+#define AM_REG_GPIO_PADREGF_PAD22STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGF_PAD22STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGF_PAD22STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD22STRNG_HIGH          0x00040000
+
+// Pad 22 input enable
+#define AM_REG_GPIO_PADREGF_PAD22INPEN_S             17
+#define AM_REG_GPIO_PADREGF_PAD22INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGF_PAD22INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGF_PAD22INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD22INPEN_EN            0x00020000
+
+// Pad 22 pullup enable
+#define AM_REG_GPIO_PADREGF_PAD22PULL_S              16
+#define AM_REG_GPIO_PADREGF_PAD22PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGF_PAD22PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGF_PAD22PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGF_PAD22PULL_EN             0x00010000
+
+// Pad 21 function select
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_S            11
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_SWDIO        0x00000000
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_M1nCE6       0x00000800
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_TCTB2        0x00001000
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_GPIO21       0x00001800
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_UART0RX      0x00002000
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_UART1RX      0x00002800
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_UNDEF6       0x00003000
+#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_UNDEF7       0x00003800
+
+// Pad 21 drive strength
+#define AM_REG_GPIO_PADREGF_PAD21STRNG_S             10
+#define AM_REG_GPIO_PADREGF_PAD21STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGF_PAD21STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGF_PAD21STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD21STRNG_HIGH          0x00000400
+
+// Pad 21 input enable
+#define AM_REG_GPIO_PADREGF_PAD21INPEN_S             9
+#define AM_REG_GPIO_PADREGF_PAD21INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGF_PAD21INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGF_PAD21INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD21INPEN_EN            0x00000200
+
+// Pad 21 pullup enable
+#define AM_REG_GPIO_PADREGF_PAD21PULL_S              8
+#define AM_REG_GPIO_PADREGF_PAD21PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGF_PAD21PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGF_PAD21PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGF_PAD21PULL_EN             0x00000100
+
+// Pad 20 function select
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_S            3
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_SWDCK        0x00000000
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_M1nCE5       0x00000008
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_TCTA2        0x00000010
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_GPIO20       0x00000018
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_UART0TX      0x00000020
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_UART1TX      0x00000028
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_UNDEF6       0x00000030
+#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_UNDEF7       0x00000038
+
+// Pad 20 drive strength
+#define AM_REG_GPIO_PADREGF_PAD20STRNG_S             2
+#define AM_REG_GPIO_PADREGF_PAD20STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGF_PAD20STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGF_PAD20STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD20STRNG_HIGH          0x00000004
+
+// Pad 20 input enable
+#define AM_REG_GPIO_PADREGF_PAD20INPEN_S             1
+#define AM_REG_GPIO_PADREGF_PAD20INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGF_PAD20INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGF_PAD20INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGF_PAD20INPEN_EN            0x00000002
+
+// Pad 20 pulldown enable
+#define AM_REG_GPIO_PADREGF_PAD20PULL_S              0
+#define AM_REG_GPIO_PADREGF_PAD20PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGF_PAD20PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGF_PAD20PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGF_PAD20PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGG - Pad Configuration Register G
+//
+//*****************************************************************************
+// Pad 27 pullup resistor selection.
+#define AM_REG_GPIO_PADREGG_PAD27RSEL_S              30
+#define AM_REG_GPIO_PADREGG_PAD27RSEL_M              0xC0000000
+#define AM_REG_GPIO_PADREGG_PAD27RSEL(n)             (((uint32_t)(n) << 30) & 0xC0000000)
+#define AM_REG_GPIO_PADREGG_PAD27RSEL_PULL1_5K       0x00000000
+#define AM_REG_GPIO_PADREGG_PAD27RSEL_PULL6K         0x40000000
+#define AM_REG_GPIO_PADREGG_PAD27RSEL_PULL12K        0x80000000
+#define AM_REG_GPIO_PADREGG_PAD27RSEL_PULL24K        0xC0000000
+
+// Pad 27 function select
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_S            27
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_EXTHF        0x00000000
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M1nCE4       0x08000000
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_TCTA1        0x10000000
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_GPIO27       0x18000000
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCL        0x20000000
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCK        0x28000000
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCKLB      0x30000000
+#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCLLB      0x38000000
+
+// Pad 27 drive strentgh
+#define AM_REG_GPIO_PADREGG_PAD27STRNG_S             26
+#define AM_REG_GPIO_PADREGG_PAD27STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGG_PAD27STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGG_PAD27STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGG_PAD27STRNG_HIGH          0x04000000
+
+// Pad 27 input enable
+#define AM_REG_GPIO_PADREGG_PAD27INPEN_S             25
+#define AM_REG_GPIO_PADREGG_PAD27INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGG_PAD27INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGG_PAD27INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGG_PAD27INPEN_EN            0x02000000
+
+// Pad 27 pullup enable
+#define AM_REG_GPIO_PADREGG_PAD27PULL_S              24
+#define AM_REG_GPIO_PADREGG_PAD27PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGG_PAD27PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGG_PAD27PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGG_PAD27PULL_EN             0x01000000
+
+// Pad 26 function select
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_S            19
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_EXTLF        0x00000000
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M0nCE3       0x00080000
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_TCTB0        0x00100000
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_GPIO26       0x00180000
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M2nCE0       0x00200000
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_TCTA1        0x00280000
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M5nCE1       0x00300000
+#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M3nCE0       0x00380000
+
+// Pad 26 drive strength
+#define AM_REG_GPIO_PADREGG_PAD26STRNG_S             18
+#define AM_REG_GPIO_PADREGG_PAD26STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGG_PAD26STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGG_PAD26STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGG_PAD26STRNG_HIGH          0x00040000
+
+// Pad 26 input enable
+#define AM_REG_GPIO_PADREGG_PAD26INPEN_S             17
+#define AM_REG_GPIO_PADREGG_PAD26INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGG_PAD26INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGG_PAD26INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGG_PAD26INPEN_EN            0x00020000
+
+// Pad 26 pullup enable
+#define AM_REG_GPIO_PADREGG_PAD26PULL_S              16
+#define AM_REG_GPIO_PADREGG_PAD26PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGG_PAD26PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGG_PAD26PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGG_PAD26PULL_EN             0x00010000
+
+// Pad 25 pullup resistor selection.
+#define AM_REG_GPIO_PADREGG_PAD25RSEL_S              14
+#define AM_REG_GPIO_PADREGG_PAD25RSEL_M              0x0000C000
+#define AM_REG_GPIO_PADREGG_PAD25RSEL(n)             (((uint32_t)(n) << 14) & 0x0000C000)
+#define AM_REG_GPIO_PADREGG_PAD25RSEL_PULL1_5K       0x00000000
+#define AM_REG_GPIO_PADREGG_PAD25RSEL_PULL6K         0x00004000
+#define AM_REG_GPIO_PADREGG_PAD25RSEL_PULL12K        0x00008000
+#define AM_REG_GPIO_PADREGG_PAD25RSEL_PULL24K        0x0000C000
+
+// Pad 25 function select
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_S            11
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_EXTXT        0x00000000
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_M0nCE2       0x00000800
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_TCTA0        0x00001000
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_GPIO25       0x00001800
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_M2SDA        0x00002000
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_M2MISO       0x00002800
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_SLMISOLB     0x00003000
+#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_SLSDALB      0x00003800
+
+// Pad 25 drive strength
+#define AM_REG_GPIO_PADREGG_PAD25STRNG_S             10
+#define AM_REG_GPIO_PADREGG_PAD25STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGG_PAD25STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGG_PAD25STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGG_PAD25STRNG_HIGH          0x00000400
+
+// Pad 25 input enable
+#define AM_REG_GPIO_PADREGG_PAD25INPEN_S             9
+#define AM_REG_GPIO_PADREGG_PAD25INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGG_PAD25INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGG_PAD25INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGG_PAD25INPEN_EN            0x00000200
+
+// Pad 25 pullup enable
+#define AM_REG_GPIO_PADREGG_PAD25PULL_S              8
+#define AM_REG_GPIO_PADREGG_PAD25PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGG_PAD25PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGG_PAD25PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGG_PAD25PULL_EN             0x00000100
+
+// Pad 24 function select
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_S            3
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_M2nCE1       0x00000000
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_M0nCE1       0x00000008
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_CLKOUT       0x00000010
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_GPIO24       0x00000018
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_M5nCE0       0x00000020
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_TCTA1        0x00000028
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_I2S_BCLK     0x00000030
+#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_SWO          0x00000038
+
+// Pad 24 drive strength
+#define AM_REG_GPIO_PADREGG_PAD24STRNG_S             2
+#define AM_REG_GPIO_PADREGG_PAD24STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGG_PAD24STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGG_PAD24STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGG_PAD24STRNG_HIGH          0x00000004
+
+// Pad 24 input enable
+#define AM_REG_GPIO_PADREGG_PAD24INPEN_S             1
+#define AM_REG_GPIO_PADREGG_PAD24INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGG_PAD24INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGG_PAD24INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGG_PAD24INPEN_EN            0x00000002
+
+// Pad 24 pullup enable
+#define AM_REG_GPIO_PADREGG_PAD24PULL_S              0
+#define AM_REG_GPIO_PADREGG_PAD24PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGG_PAD24PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGG_PAD24PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGG_PAD24PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGH - Pad Configuration Register H
+//
+//*****************************************************************************
+// Pad 31 function select
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_S            27
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_ADCSE3       0x00000000
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_M0nCE4       0x08000000
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_TCTA3        0x10000000
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_GPIO31       0x18000000
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UART0RX      0x20000000
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_TCTB1        0x28000000
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF6       0x30000000
+#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF7       0x38000000
+
+// Pad 31 drive strentgh
+#define AM_REG_GPIO_PADREGH_PAD31STRNG_S             26
+#define AM_REG_GPIO_PADREGH_PAD31STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGH_PAD31STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGH_PAD31STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGH_PAD31STRNG_HIGH          0x04000000
+
+// Pad 31 input enable
+#define AM_REG_GPIO_PADREGH_PAD31INPEN_S             25
+#define AM_REG_GPIO_PADREGH_PAD31INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGH_PAD31INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGH_PAD31INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGH_PAD31INPEN_EN            0x02000000
+
+// Pad 31 pullup enable
+#define AM_REG_GPIO_PADREGH_PAD31PULL_S              24
+#define AM_REG_GPIO_PADREGH_PAD31PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGH_PAD31PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGH_PAD31PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGH_PAD31PULL_EN             0x01000000
+
+// Pad 30 function select
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_S            19
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_UNDEF0       0x00000000
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_M1nCE7       0x00080000
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_TCTB2        0x00100000
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_GPIO30       0x00180000
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_UART0TX      0x00200000
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_UA1RTS       0x00280000
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_UNDEF6       0x00300000
+#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_I2S_DAT      0x00380000
+
+// Pad 30 drive strength
+#define AM_REG_GPIO_PADREGH_PAD30STRNG_S             18
+#define AM_REG_GPIO_PADREGH_PAD30STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGH_PAD30STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGH_PAD30STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGH_PAD30STRNG_HIGH          0x00040000
+
+// Pad 30 input enable
+#define AM_REG_GPIO_PADREGH_PAD30INPEN_S             17
+#define AM_REG_GPIO_PADREGH_PAD30INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGH_PAD30INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGH_PAD30INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGH_PAD30INPEN_EN            0x00020000
+
+// Pad 30 pullup enable
+#define AM_REG_GPIO_PADREGH_PAD30PULL_S              16
+#define AM_REG_GPIO_PADREGH_PAD30PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGH_PAD30PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGH_PAD30PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGH_PAD30PULL_EN             0x00010000
+
+// Pad 29 function select
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_S            11
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_ADCSE1       0x00000000
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_M1nCE6       0x00000800
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_TCTA2        0x00001000
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_GPIO29       0x00001800
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_UA0CTS       0x00002000
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_UA1CTS       0x00002800
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_M4nCE0       0x00003000
+#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_PDM_DATA     0x00003800
+
+// Pad 29 drive strength
+#define AM_REG_GPIO_PADREGH_PAD29STRNG_S             10
+#define AM_REG_GPIO_PADREGH_PAD29STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGH_PAD29STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGH_PAD29STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGH_PAD29STRNG_HIGH          0x00000400
+
+// Pad 29 input enable
+#define AM_REG_GPIO_PADREGH_PAD29INPEN_S             9
+#define AM_REG_GPIO_PADREGH_PAD29INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGH_PAD29INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGH_PAD29INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGH_PAD29INPEN_EN            0x00000200
+
+// Pad 29 pullup enable
+#define AM_REG_GPIO_PADREGH_PAD29PULL_S              8
+#define AM_REG_GPIO_PADREGH_PAD29PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGH_PAD29PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGH_PAD29PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGH_PAD29PULL_EN             0x00000100
+
+// Pad 28 function select
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_S            3
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK     0x00000000
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M1nCE5       0x00000008
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_TCTB1        0x00000010
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_GPIO28       0x00000018
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M2WIR3       0x00000020
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M2MOSI       0x00000028
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M5nCE3       0x00000030
+#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_SLWIR3LB     0x00000038
+
+// Pad 28 drive strength
+#define AM_REG_GPIO_PADREGH_PAD28STRNG_S             2
+#define AM_REG_GPIO_PADREGH_PAD28STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGH_PAD28STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGH_PAD28STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGH_PAD28STRNG_HIGH          0x00000004
+
+// Pad 28 input enable
+#define AM_REG_GPIO_PADREGH_PAD28INPEN_S             1
+#define AM_REG_GPIO_PADREGH_PAD28INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGH_PAD28INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGH_PAD28INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGH_PAD28INPEN_EN            0x00000002
+
+// Pad 28 pullup enable
+#define AM_REG_GPIO_PADREGH_PAD28PULL_S              0
+#define AM_REG_GPIO_PADREGH_PAD28PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGH_PAD28PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGH_PAD28PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGH_PAD28PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGI - Pad Configuration Register I
+//
+//*****************************************************************************
+// Pad 35 function select
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_S            27
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_ADCSE7       0x00000000
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M1nCE0       0x08000000
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_UART1TX      0x10000000
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_GPIO35       0x18000000
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M4nCE6       0x20000000
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_TCTA1        0x28000000
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_UA0RTS       0x30000000
+#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M3nCE2       0x38000000
+
+// Pad 35 drive strentgh
+#define AM_REG_GPIO_PADREGI_PAD35STRNG_S             26
+#define AM_REG_GPIO_PADREGI_PAD35STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGI_PAD35STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGI_PAD35STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGI_PAD35STRNG_HIGH          0x04000000
+
+// Pad 35 input enable
+#define AM_REG_GPIO_PADREGI_PAD35INPEN_S             25
+#define AM_REG_GPIO_PADREGI_PAD35INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGI_PAD35INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGI_PAD35INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGI_PAD35INPEN_EN            0x02000000
+
+// Pad 35 pullup enable
+#define AM_REG_GPIO_PADREGI_PAD35PULL_S              24
+#define AM_REG_GPIO_PADREGI_PAD35PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGI_PAD35PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGI_PAD35PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGI_PAD35PULL_EN             0x01000000
+
+// Pad 34 function select
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_S            19
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_ADCSE6       0x00000000
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M0nCE7       0x00080000
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M2nCE3       0x00100000
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_GPIO34       0x00180000
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_CMPRF2       0x00200000
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M3nCE1       0x00280000
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M4nCE0       0x00300000
+#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M5nCE2       0x00380000
+
+// Pad 34 drive strength
+#define AM_REG_GPIO_PADREGI_PAD34STRNG_S             18
+#define AM_REG_GPIO_PADREGI_PAD34STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGI_PAD34STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGI_PAD34STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGI_PAD34STRNG_HIGH          0x00040000
+
+// Pad 34 input enable
+#define AM_REG_GPIO_PADREGI_PAD34INPEN_S             17
+#define AM_REG_GPIO_PADREGI_PAD34INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGI_PAD34INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGI_PAD34INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGI_PAD34INPEN_EN            0x00020000
+
+// Pad 34 pullup enable
+#define AM_REG_GPIO_PADREGI_PAD34PULL_S              16
+#define AM_REG_GPIO_PADREGI_PAD34PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGI_PAD34PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGI_PAD34PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGI_PAD34PULL_EN             0x00010000
+
+// Pad 33 function select
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_S            11
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_ADCSE5       0x00000000
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_M0nCE6       0x00000800
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_32khz_XT     0x00001000
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_GPIO33       0x00001800
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_UNDEF4       0x00002000
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_M3nCE7       0x00002800
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_TCTB1        0x00003000
+#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_SWO          0x00003800
+
+// Pad 33 drive strength
+#define AM_REG_GPIO_PADREGI_PAD33STRNG_S             10
+#define AM_REG_GPIO_PADREGI_PAD33STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGI_PAD33STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGI_PAD33STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGI_PAD33STRNG_HIGH          0x00000400
+
+// Pad 33 input enable
+#define AM_REG_GPIO_PADREGI_PAD33INPEN_S             9
+#define AM_REG_GPIO_PADREGI_PAD33INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGI_PAD33INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGI_PAD33INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGI_PAD33INPEN_EN            0x00000200
+
+// Pad 33 pullup enable
+#define AM_REG_GPIO_PADREGI_PAD33PULL_S              8
+#define AM_REG_GPIO_PADREGI_PAD33PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGI_PAD33PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGI_PAD33PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGI_PAD33PULL_EN             0x00000100
+
+// Pad 32 function select
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_S            3
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_ADCSE4       0x00000000
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_M0nCE5       0x00000008
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_TCTB3        0x00000010
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_GPIO32       0x00000018
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_UNDEF4       0x00000020
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_TCTB1        0x00000028
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_UNDEF6       0x00000030
+#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_UNDEF7       0x00000038
+
+// Pad 32 drive strength
+#define AM_REG_GPIO_PADREGI_PAD32STRNG_S             2
+#define AM_REG_GPIO_PADREGI_PAD32STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGI_PAD32STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGI_PAD32STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGI_PAD32STRNG_HIGH          0x00000004
+
+// Pad 32 input enable
+#define AM_REG_GPIO_PADREGI_PAD32INPEN_S             1
+#define AM_REG_GPIO_PADREGI_PAD32INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGI_PAD32INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGI_PAD32INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGI_PAD32INPEN_EN            0x00000002
+
+// Pad 32 pullup enable
+#define AM_REG_GPIO_PADREGI_PAD32PULL_S              0
+#define AM_REG_GPIO_PADREGI_PAD32PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGI_PAD32PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGI_PAD32PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGI_PAD32PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGJ - Pad Configuration Register J
+//
+//*****************************************************************************
+// Pad 39 pullup resistor selection.
+#define AM_REG_GPIO_PADREGJ_PAD39RSEL_S              30
+#define AM_REG_GPIO_PADREGJ_PAD39RSEL_M              0xC0000000
+#define AM_REG_GPIO_PADREGJ_PAD39RSEL(n)             (((uint32_t)(n) << 30) & 0xC0000000)
+#define AM_REG_GPIO_PADREGJ_PAD39RSEL_PULL1_5K       0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD39RSEL_PULL6K         0x40000000
+#define AM_REG_GPIO_PADREGJ_PAD39RSEL_PULL12K        0x80000000
+#define AM_REG_GPIO_PADREGJ_PAD39RSEL_PULL24K        0xC0000000
+
+// Pad 39 function select
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_S            27
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_UART0TX      0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_UART1TX      0x08000000
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_CLKOUT       0x10000000
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_GPIO39       0x18000000
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCL        0x20000000
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCK        0x28000000
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCKLB      0x30000000
+#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCLLB      0x38000000
+
+// Pad 39 drive strentgh
+#define AM_REG_GPIO_PADREGJ_PAD39STRNG_S             26
+#define AM_REG_GPIO_PADREGJ_PAD39STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGJ_PAD39STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGJ_PAD39STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD39STRNG_HIGH          0x04000000
+
+// Pad 39 input enable
+#define AM_REG_GPIO_PADREGJ_PAD39INPEN_S             25
+#define AM_REG_GPIO_PADREGJ_PAD39INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGJ_PAD39INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGJ_PAD39INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD39INPEN_EN            0x02000000
+
+// Pad 39 pullup enable
+#define AM_REG_GPIO_PADREGJ_PAD39PULL_S              24
+#define AM_REG_GPIO_PADREGJ_PAD39PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGJ_PAD39PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGJ_PAD39PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD39PULL_EN             0x01000000
+
+// Pad 38 function select
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_S            19
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_TRIG3        0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M1nCE3       0x00080000
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_UA0CTS       0x00100000
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_GPIO38       0x00180000
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M3WIR3       0x00200000
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M3MOSI       0x00280000
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M4nCE7       0x00300000
+#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_SLWIR3LB     0x00380000
+
+// Pad 38 drive strength
+#define AM_REG_GPIO_PADREGJ_PAD38STRNG_S             18
+#define AM_REG_GPIO_PADREGJ_PAD38STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGJ_PAD38STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGJ_PAD38STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD38STRNG_HIGH          0x00040000
+
+// Pad 38 input enable
+#define AM_REG_GPIO_PADREGJ_PAD38INPEN_S             17
+#define AM_REG_GPIO_PADREGJ_PAD38INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGJ_PAD38INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGJ_PAD38INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD38INPEN_EN            0x00020000
+
+// Pad 38 pullup enable
+#define AM_REG_GPIO_PADREGJ_PAD38PULL_S              16
+#define AM_REG_GPIO_PADREGJ_PAD38PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGJ_PAD38PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGJ_PAD38PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD38PULL_EN             0x00010000
+
+// Pad 37 function select
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_S            11
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_TRIG2        0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_M1nCE2       0x00000800
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_UA0RTS       0x00001000
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_GPIO37       0x00001800
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_M3nCE4       0x00002000
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_M4nCE1       0x00002800
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_PDM_CLK      0x00003000
+#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_TCTA1        0x00003800
+
+// Pad 37 drive strength
+#define AM_REG_GPIO_PADREGJ_PAD37STRNG_S             10
+#define AM_REG_GPIO_PADREGJ_PAD37STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGJ_PAD37STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGJ_PAD37STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD37STRNG_HIGH          0x00000400
+
+// Pad 37 input enable
+#define AM_REG_GPIO_PADREGJ_PAD37INPEN_S             9
+#define AM_REG_GPIO_PADREGJ_PAD37INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGJ_PAD37INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGJ_PAD37INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD37INPEN_EN            0x00000200
+
+// Pad 37 pullup enable
+#define AM_REG_GPIO_PADREGJ_PAD37PULL_S              8
+#define AM_REG_GPIO_PADREGJ_PAD37PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGJ_PAD37PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGJ_PAD37PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD37PULL_EN             0x00000100
+
+// Pad 36 function select
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_S            3
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_TRIG1        0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_M1nCE1       0x00000008
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_UART1RX      0x00000010
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_GPIO36       0x00000018
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_32khz_XT     0x00000020
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_M2nCE0       0x00000028
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_UA0CTS       0x00000030
+#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_M3nCE3       0x00000038
+
+// Pad 36 drive strength
+#define AM_REG_GPIO_PADREGJ_PAD36STRNG_S             2
+#define AM_REG_GPIO_PADREGJ_PAD36STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGJ_PAD36STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGJ_PAD36STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD36STRNG_HIGH          0x00000004
+
+// Pad 36 input enable
+#define AM_REG_GPIO_PADREGJ_PAD36INPEN_S             1
+#define AM_REG_GPIO_PADREGJ_PAD36INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGJ_PAD36INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGJ_PAD36INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD36INPEN_EN            0x00000002
+
+// Pad 36 pullup enable
+#define AM_REG_GPIO_PADREGJ_PAD36PULL_S              0
+#define AM_REG_GPIO_PADREGJ_PAD36PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGJ_PAD36PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGJ_PAD36PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGJ_PAD36PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGK - Pad Configuration Register K
+//
+//*****************************************************************************
+// Pad 43 pullup resistor selection.
+#define AM_REG_GPIO_PADREGK_PAD43RSEL_S              30
+#define AM_REG_GPIO_PADREGK_PAD43RSEL_M              0xC0000000
+#define AM_REG_GPIO_PADREGK_PAD43RSEL(n)             (((uint32_t)(n) << 30) & 0xC0000000)
+#define AM_REG_GPIO_PADREGK_PAD43RSEL_PULL1_5K       0x00000000
+#define AM_REG_GPIO_PADREGK_PAD43RSEL_PULL6K         0x40000000
+#define AM_REG_GPIO_PADREGK_PAD43RSEL_PULL12K        0x80000000
+#define AM_REG_GPIO_PADREGK_PAD43RSEL_PULL24K        0xC0000000
+
+// Pad 43 function select
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_S            27
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M2nCE4       0x00000000
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M0nCE1       0x08000000
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_TCTB0        0x10000000
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_GPIO43       0x18000000
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M3SDA        0x20000000
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M3MISO       0x28000000
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLMISOLB     0x30000000
+#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLSDALB      0x38000000
+
+// Pad 43 drive strentgh
+#define AM_REG_GPIO_PADREGK_PAD43STRNG_S             26
+#define AM_REG_GPIO_PADREGK_PAD43STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGK_PAD43STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGK_PAD43STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD43STRNG_HIGH          0x04000000
+
+// Pad 43 input enable
+#define AM_REG_GPIO_PADREGK_PAD43INPEN_S             25
+#define AM_REG_GPIO_PADREGK_PAD43INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGK_PAD43INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGK_PAD43INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD43INPEN_EN            0x02000000
+
+// Pad 43 pullup enable
+#define AM_REG_GPIO_PADREGK_PAD43PULL_S              24
+#define AM_REG_GPIO_PADREGK_PAD43PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGK_PAD43PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGK_PAD43PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGK_PAD43PULL_EN             0x01000000
+
+// Pad 42 pullup resistor selection.
+#define AM_REG_GPIO_PADREGK_PAD42RSEL_S              22
+#define AM_REG_GPIO_PADREGK_PAD42RSEL_M              0x00C00000
+#define AM_REG_GPIO_PADREGK_PAD42RSEL(n)             (((uint32_t)(n) << 22) & 0x00C00000)
+#define AM_REG_GPIO_PADREGK_PAD42RSEL_PULL1_5K       0x00000000
+#define AM_REG_GPIO_PADREGK_PAD42RSEL_PULL6K         0x00400000
+#define AM_REG_GPIO_PADREGK_PAD42RSEL_PULL12K        0x00800000
+#define AM_REG_GPIO_PADREGK_PAD42RSEL_PULL24K        0x00C00000
+
+// Pad 42 function select
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_S            19
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M2nCE2       0x00000000
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M0nCE0       0x00080000
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_TCTA0        0x00100000
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_GPIO42       0x00180000
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M3SCL        0x00200000
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M3SCK        0x00280000
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M3SCKLB      0x00300000
+#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M3SCLLB      0x00380000
+
+// Pad 42 drive strength
+#define AM_REG_GPIO_PADREGK_PAD42STRNG_S             18
+#define AM_REG_GPIO_PADREGK_PAD42STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGK_PAD42STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGK_PAD42STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD42STRNG_HIGH          0x00040000
+
+// Pad 42 input enable
+#define AM_REG_GPIO_PADREGK_PAD42INPEN_S             17
+#define AM_REG_GPIO_PADREGK_PAD42INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGK_PAD42INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGK_PAD42INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD42INPEN_EN            0x00020000
+
+// Pad 42 pullup enable
+#define AM_REG_GPIO_PADREGK_PAD42PULL_S              16
+#define AM_REG_GPIO_PADREGK_PAD42PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGK_PAD42PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGK_PAD42PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGK_PAD42PULL_EN             0x00010000
+
+// Pad 41 upper power switch enable
+#define AM_REG_GPIO_PADREGK_PAD41PWRUP_S             15
+#define AM_REG_GPIO_PADREGK_PAD41PWRUP_M             0x00008000
+#define AM_REG_GPIO_PADREGK_PAD41PWRUP(n)            (((uint32_t)(n) << 15) & 0x00008000)
+#define AM_REG_GPIO_PADREGK_PAD41PWRUP_DIS           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD41PWRUP_EN            0x00008000
+
+// Pad 41 function select
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_S            11
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M2nCE1       0x00000000
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_CLKOUT       0x00000800
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_SWO          0x00001000
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_GPIO41       0x00001800
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M3nCE5       0x00002000
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M5nCE7       0x00002800
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M4nCE2       0x00003000
+#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_UA0RTS       0x00003800
+
+// Pad 41 drive strength
+#define AM_REG_GPIO_PADREGK_PAD41STRNG_S             10
+#define AM_REG_GPIO_PADREGK_PAD41STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGK_PAD41STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGK_PAD41STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD41STRNG_HIGH          0x00000400
+
+// Pad 41 input enable
+#define AM_REG_GPIO_PADREGK_PAD41INPEN_S             9
+#define AM_REG_GPIO_PADREGK_PAD41INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGK_PAD41INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGK_PAD41INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD41INPEN_EN            0x00000200
+
+// Pad 41 pullup enable
+#define AM_REG_GPIO_PADREGK_PAD41PULL_S              8
+#define AM_REG_GPIO_PADREGK_PAD41PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGK_PAD41PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGK_PAD41PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGK_PAD41PULL_EN             0x00000100
+
+// Pad 40 pullup resistor selection.
+#define AM_REG_GPIO_PADREGK_PAD40RSEL_S              6
+#define AM_REG_GPIO_PADREGK_PAD40RSEL_M              0x000000C0
+#define AM_REG_GPIO_PADREGK_PAD40RSEL(n)             (((uint32_t)(n) << 6) & 0x000000C0)
+#define AM_REG_GPIO_PADREGK_PAD40RSEL_PULL1_5K       0x00000000
+#define AM_REG_GPIO_PADREGK_PAD40RSEL_PULL6K         0x00000040
+#define AM_REG_GPIO_PADREGK_PAD40RSEL_PULL12K        0x00000080
+#define AM_REG_GPIO_PADREGK_PAD40RSEL_PULL24K        0x000000C0
+
+// Pad 40 function select
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_S            3
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_UART0RX      0x00000000
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_UART1RX      0x00000008
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_TRIG0        0x00000010
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_GPIO40       0x00000018
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_M4SDA        0x00000020
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_M4MISO       0x00000028
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_SLMISOLB     0x00000030
+#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_SLSDALB      0x00000038
+
+// Pad 40 drive strength
+#define AM_REG_GPIO_PADREGK_PAD40STRNG_S             2
+#define AM_REG_GPIO_PADREGK_PAD40STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGK_PAD40STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGK_PAD40STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD40STRNG_HIGH          0x00000004
+
+// Pad 40 input enable
+#define AM_REG_GPIO_PADREGK_PAD40INPEN_S             1
+#define AM_REG_GPIO_PADREGK_PAD40INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGK_PAD40INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGK_PAD40INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGK_PAD40INPEN_EN            0x00000002
+
+// Pad 40 pullup enable
+#define AM_REG_GPIO_PADREGK_PAD40PULL_S              0
+#define AM_REG_GPIO_PADREGK_PAD40PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGK_PAD40PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGK_PAD40PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGK_PAD40PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGL - Pad Configuration Register L
+//
+//*****************************************************************************
+// Pad 47 function select
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_S            27
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M            0x38000000
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL(n)           (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M2nCE5       0x00000000
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M0nCE5       0x08000000
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_TCTB2        0x10000000
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_GPIO47       0x18000000
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M5WIR3       0x20000000
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M5MOSI       0x28000000
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M4nCE5       0x30000000
+#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_SLWIR3LB     0x38000000
+
+// Pad 47 drive strentgh
+#define AM_REG_GPIO_PADREGL_PAD47STRNG_S             26
+#define AM_REG_GPIO_PADREGL_PAD47STRNG_M             0x04000000
+#define AM_REG_GPIO_PADREGL_PAD47STRNG(n)            (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_GPIO_PADREGL_PAD47STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGL_PAD47STRNG_HIGH          0x04000000
+
+// Pad 47 input enable
+#define AM_REG_GPIO_PADREGL_PAD47INPEN_S             25
+#define AM_REG_GPIO_PADREGL_PAD47INPEN_M             0x02000000
+#define AM_REG_GPIO_PADREGL_PAD47INPEN(n)            (((uint32_t)(n) << 25) & 0x02000000)
+#define AM_REG_GPIO_PADREGL_PAD47INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGL_PAD47INPEN_EN            0x02000000
+
+// Pad 47 pullup enable
+#define AM_REG_GPIO_PADREGL_PAD47PULL_S              24
+#define AM_REG_GPIO_PADREGL_PAD47PULL_M              0x01000000
+#define AM_REG_GPIO_PADREGL_PAD47PULL(n)             (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_PADREGL_PAD47PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGL_PAD47PULL_EN             0x01000000
+
+// Pad 46 function select
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_S            19
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_M            0x00380000
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL(n)           (((uint32_t)(n) << 19) & 0x00380000)
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_32khz_XT     0x00000000
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_M0nCE4       0x00080000
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_TCTA2        0x00100000
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_GPIO46       0x00180000
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_TCTA1        0x00200000
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_M5nCE4       0x00280000
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_M4nCE4       0x00300000
+#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_SWO          0x00380000
+
+// Pad 46 drive strength
+#define AM_REG_GPIO_PADREGL_PAD46STRNG_S             18
+#define AM_REG_GPIO_PADREGL_PAD46STRNG_M             0x00040000
+#define AM_REG_GPIO_PADREGL_PAD46STRNG(n)            (((uint32_t)(n) << 18) & 0x00040000)
+#define AM_REG_GPIO_PADREGL_PAD46STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGL_PAD46STRNG_HIGH          0x00040000
+
+// Pad 46 input enable
+#define AM_REG_GPIO_PADREGL_PAD46INPEN_S             17
+#define AM_REG_GPIO_PADREGL_PAD46INPEN_M             0x00020000
+#define AM_REG_GPIO_PADREGL_PAD46INPEN(n)            (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_GPIO_PADREGL_PAD46INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGL_PAD46INPEN_EN            0x00020000
+
+// Pad 46 pullup enable
+#define AM_REG_GPIO_PADREGL_PAD46PULL_S              16
+#define AM_REG_GPIO_PADREGL_PAD46PULL_M              0x00010000
+#define AM_REG_GPIO_PADREGL_PAD46PULL(n)             (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_PADREGL_PAD46PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGL_PAD46PULL_EN             0x00010000
+
+// Pad 45 function select
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_S            11
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_UA1CTS       0x00000000
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M0nCE3       0x00000800
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_TCTB1        0x00001000
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_GPIO45       0x00001800
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M4nCE3       0x00002000
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M3nCE6       0x00002800
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M5nCE5       0x00003000
+#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_TCTA1        0x00003800
+
+// Pad 45 drive strength
+#define AM_REG_GPIO_PADREGL_PAD45STRNG_S             10
+#define AM_REG_GPIO_PADREGL_PAD45STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGL_PAD45STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGL_PAD45STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGL_PAD45STRNG_HIGH          0x00000400
+
+// Pad 45 input enable
+#define AM_REG_GPIO_PADREGL_PAD45INPEN_S             9
+#define AM_REG_GPIO_PADREGL_PAD45INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGL_PAD45INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGL_PAD45INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGL_PAD45INPEN_EN            0x00000200
+
+// Pad 45 pullup enable
+#define AM_REG_GPIO_PADREGL_PAD45PULL_S              8
+#define AM_REG_GPIO_PADREGL_PAD45PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGL_PAD45PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGL_PAD45PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGL_PAD45PULL_EN             0x00000100
+
+// Pad 44 function select
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_S            3
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_UA1RTS       0x00000000
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M0nCE2       0x00000008
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_TCTA1        0x00000010
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_GPIO44       0x00000018
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M4WIR3       0x00000020
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M4MOSI       0x00000028
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M5nCE6       0x00000030
+#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_SLWIR3LB     0x00000038
+
+// Pad 44 drive strength
+#define AM_REG_GPIO_PADREGL_PAD44STRNG_S             2
+#define AM_REG_GPIO_PADREGL_PAD44STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGL_PAD44STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGL_PAD44STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGL_PAD44STRNG_HIGH          0x00000004
+
+// Pad 44 input enable
+#define AM_REG_GPIO_PADREGL_PAD44INPEN_S             1
+#define AM_REG_GPIO_PADREGL_PAD44INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGL_PAD44INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGL_PAD44INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGL_PAD44INPEN_EN            0x00000002
+
+// Pad 44 pullup enable
+#define AM_REG_GPIO_PADREGL_PAD44PULL_S              0
+#define AM_REG_GPIO_PADREGL_PAD44PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGL_PAD44PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGL_PAD44PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGL_PAD44PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_PADREGM - Pad Configuration Register M
+//
+//*****************************************************************************
+// Pad 49 pullup resistor selection.
+#define AM_REG_GPIO_PADREGM_PAD49RSEL_S              14
+#define AM_REG_GPIO_PADREGM_PAD49RSEL_M              0x0000C000
+#define AM_REG_GPIO_PADREGM_PAD49RSEL(n)             (((uint32_t)(n) << 14) & 0x0000C000)
+#define AM_REG_GPIO_PADREGM_PAD49RSEL_PULL1_5K       0x00000000
+#define AM_REG_GPIO_PADREGM_PAD49RSEL_PULL6K         0x00004000
+#define AM_REG_GPIO_PADREGM_PAD49RSEL_PULL12K        0x00008000
+#define AM_REG_GPIO_PADREGM_PAD49RSEL_PULL24K        0x0000C000
+
+// Pad 49 function select
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_S            11
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M            0x00003800
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL(n)           (((uint32_t)(n) << 11) & 0x00003800)
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M2nCE7       0x00000000
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M0nCE7       0x00000800
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_TCTB3        0x00001000
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_GPIO49       0x00001800
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M5SDA        0x00002000
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M5MISO       0x00002800
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_SLMISOLB     0x00003000
+#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_SLSDALB      0x00003800
+
+// Pad 49 drive strength
+#define AM_REG_GPIO_PADREGM_PAD49STRNG_S             10
+#define AM_REG_GPIO_PADREGM_PAD49STRNG_M             0x00000400
+#define AM_REG_GPIO_PADREGM_PAD49STRNG(n)            (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_GPIO_PADREGM_PAD49STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGM_PAD49STRNG_HIGH          0x00000400
+
+// Pad 49 input enable
+#define AM_REG_GPIO_PADREGM_PAD49INPEN_S             9
+#define AM_REG_GPIO_PADREGM_PAD49INPEN_M             0x00000200
+#define AM_REG_GPIO_PADREGM_PAD49INPEN(n)            (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_GPIO_PADREGM_PAD49INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGM_PAD49INPEN_EN            0x00000200
+
+// Pad 49 pullup enable
+#define AM_REG_GPIO_PADREGM_PAD49PULL_S              8
+#define AM_REG_GPIO_PADREGM_PAD49PULL_M              0x00000100
+#define AM_REG_GPIO_PADREGM_PAD49PULL(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_PADREGM_PAD49PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGM_PAD49PULL_EN             0x00000100
+
+// Pad 48 pullup resistor selection.
+#define AM_REG_GPIO_PADREGM_PAD48RSEL_S              6
+#define AM_REG_GPIO_PADREGM_PAD48RSEL_M              0x000000C0
+#define AM_REG_GPIO_PADREGM_PAD48RSEL(n)             (((uint32_t)(n) << 6) & 0x000000C0)
+#define AM_REG_GPIO_PADREGM_PAD48RSEL_PULL1_5K       0x00000000
+#define AM_REG_GPIO_PADREGM_PAD48RSEL_PULL6K         0x00000040
+#define AM_REG_GPIO_PADREGM_PAD48RSEL_PULL12K        0x00000080
+#define AM_REG_GPIO_PADREGM_PAD48RSEL_PULL24K        0x000000C0
+
+// Pad 48 function select
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_S            3
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M            0x00000038
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL(n)           (((uint32_t)(n) << 3) & 0x00000038)
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M2nCE6       0x00000000
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M0nCE6       0x00000008
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_TCTA3        0x00000010
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_GPIO48       0x00000018
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M5SCL        0x00000020
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M5SCK        0x00000028
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M5SCKLB      0x00000030
+#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M5SCLLB      0x00000038
+
+// Pad 48 drive strength
+#define AM_REG_GPIO_PADREGM_PAD48STRNG_S             2
+#define AM_REG_GPIO_PADREGM_PAD48STRNG_M             0x00000004
+#define AM_REG_GPIO_PADREGM_PAD48STRNG(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_GPIO_PADREGM_PAD48STRNG_LOW           0x00000000
+#define AM_REG_GPIO_PADREGM_PAD48STRNG_HIGH          0x00000004
+
+// Pad 48 input enable
+#define AM_REG_GPIO_PADREGM_PAD48INPEN_S             1
+#define AM_REG_GPIO_PADREGM_PAD48INPEN_M             0x00000002
+#define AM_REG_GPIO_PADREGM_PAD48INPEN(n)            (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_GPIO_PADREGM_PAD48INPEN_DIS           0x00000000
+#define AM_REG_GPIO_PADREGM_PAD48INPEN_EN            0x00000002
+
+// Pad 48 pullup enable
+#define AM_REG_GPIO_PADREGM_PAD48PULL_S              0
+#define AM_REG_GPIO_PADREGM_PAD48PULL_M              0x00000001
+#define AM_REG_GPIO_PADREGM_PAD48PULL(n)             (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_PADREGM_PAD48PULL_DIS            0x00000000
+#define AM_REG_GPIO_PADREGM_PAD48PULL_EN             0x00000001
+
+//*****************************************************************************
+//
+// GPIO_CFGA - GPIO Configuration Register A
+//
+//*****************************************************************************
+// GPIO7 interrupt direction.
+#define AM_REG_GPIO_CFGA_GPIO7INTD_S                 31
+#define AM_REG_GPIO_CFGA_GPIO7INTD_M                 0x80000000
+#define AM_REG_GPIO_CFGA_GPIO7INTD(n)                (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_GPIO_CFGA_GPIO7INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO7INTD_INTHL             0x80000000
+
+// GPIO7 output configuration.
+#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_S               29
+#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_M               0x60000000
+#define AM_REG_GPIO_CFGA_GPIO7OUTCFG(n)              (((uint32_t)(n) << 29) & 0x60000000)
+#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_PUSHPULL        0x20000000
+#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_OD              0x40000000
+#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_TS              0x60000000
+
+// GPIO7 input enable.
+#define AM_REG_GPIO_CFGA_GPIO7INCFG_S                28
+#define AM_REG_GPIO_CFGA_GPIO7INCFG_M                0x10000000
+#define AM_REG_GPIO_CFGA_GPIO7INCFG(n)               (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_CFGA_GPIO7INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO7INCFG_RDZERO           0x10000000
+
+// GPIO6 interrupt direction.
+#define AM_REG_GPIO_CFGA_GPIO6INTD_S                 27
+#define AM_REG_GPIO_CFGA_GPIO6INTD_M                 0x08000000
+#define AM_REG_GPIO_CFGA_GPIO6INTD(n)                (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_GPIO_CFGA_GPIO6INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO6INTD_INTHL             0x08000000
+
+// GPIO6 output configuration.
+#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_S               25
+#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_M               0x06000000
+#define AM_REG_GPIO_CFGA_GPIO6OUTCFG(n)              (((uint32_t)(n) << 25) & 0x06000000)
+#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_PUSHPULL        0x02000000
+#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_OD              0x04000000
+#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_TS              0x06000000
+
+// GPIO6 input enable.
+#define AM_REG_GPIO_CFGA_GPIO6INCFG_S                24
+#define AM_REG_GPIO_CFGA_GPIO6INCFG_M                0x01000000
+#define AM_REG_GPIO_CFGA_GPIO6INCFG(n)               (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_CFGA_GPIO6INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO6INCFG_RDZERO           0x01000000
+
+// GPIO5 interrupt direction.
+#define AM_REG_GPIO_CFGA_GPIO5INTD_S                 23
+#define AM_REG_GPIO_CFGA_GPIO5INTD_M                 0x00800000
+#define AM_REG_GPIO_CFGA_GPIO5INTD(n)                (((uint32_t)(n) << 23) & 0x00800000)
+#define AM_REG_GPIO_CFGA_GPIO5INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO5INTD_INTHL             0x00800000
+
+// GPIO5 output configuration.
+#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_S               21
+#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_M               0x00600000
+#define AM_REG_GPIO_CFGA_GPIO5OUTCFG(n)              (((uint32_t)(n) << 21) & 0x00600000)
+#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_PUSHPULL        0x00200000
+#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_OD              0x00400000
+#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_TS              0x00600000
+
+// GPIO5 input enable.
+#define AM_REG_GPIO_CFGA_GPIO5INCFG_S                20
+#define AM_REG_GPIO_CFGA_GPIO5INCFG_M                0x00100000
+#define AM_REG_GPIO_CFGA_GPIO5INCFG(n)               (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_CFGA_GPIO5INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO5INCFG_RDZERO           0x00100000
+
+// GPIO4 interrupt direction.
+#define AM_REG_GPIO_CFGA_GPIO4INTD_S                 19
+#define AM_REG_GPIO_CFGA_GPIO4INTD_M                 0x00080000
+#define AM_REG_GPIO_CFGA_GPIO4INTD(n)                (((uint32_t)(n) << 19) & 0x00080000)
+#define AM_REG_GPIO_CFGA_GPIO4INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO4INTD_INTHL             0x00080000
+
+// GPIO4 output configuration.
+#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_S               17
+#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_M               0x00060000
+#define AM_REG_GPIO_CFGA_GPIO4OUTCFG(n)              (((uint32_t)(n) << 17) & 0x00060000)
+#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_PUSHPULL        0x00020000
+#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_OD              0x00040000
+#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_TS              0x00060000
+
+// GPIO4 input enable.
+#define AM_REG_GPIO_CFGA_GPIO4INCFG_S                16
+#define AM_REG_GPIO_CFGA_GPIO4INCFG_M                0x00010000
+#define AM_REG_GPIO_CFGA_GPIO4INCFG(n)               (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_CFGA_GPIO4INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO4INCFG_RDZERO           0x00010000
+
+// GPIO3 interrupt direction.
+#define AM_REG_GPIO_CFGA_GPIO3INTD_S                 15
+#define AM_REG_GPIO_CFGA_GPIO3INTD_M                 0x00008000
+#define AM_REG_GPIO_CFGA_GPIO3INTD(n)                (((uint32_t)(n) << 15) & 0x00008000)
+#define AM_REG_GPIO_CFGA_GPIO3INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO3INTD_INTHL             0x00008000
+
+// GPIO3 output configuration.
+#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_S               13
+#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_M               0x00006000
+#define AM_REG_GPIO_CFGA_GPIO3OUTCFG(n)              (((uint32_t)(n) << 13) & 0x00006000)
+#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_PUSHPULL        0x00002000
+#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_OD              0x00004000
+#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_TS              0x00006000
+
+// GPIO3 input enable.
+#define AM_REG_GPIO_CFGA_GPIO3INCFG_S                12
+#define AM_REG_GPIO_CFGA_GPIO3INCFG_M                0x00001000
+#define AM_REG_GPIO_CFGA_GPIO3INCFG(n)               (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_CFGA_GPIO3INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO3INCFG_RDZERO           0x00001000
+
+// GPIO2 interrupt direction.
+#define AM_REG_GPIO_CFGA_GPIO2INTD_S                 11
+#define AM_REG_GPIO_CFGA_GPIO2INTD_M                 0x00000800
+#define AM_REG_GPIO_CFGA_GPIO2INTD(n)                (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_GPIO_CFGA_GPIO2INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO2INTD_INTHL             0x00000800
+
+// GPIO2 output configuration.
+#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_S               9
+#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_M               0x00000600
+#define AM_REG_GPIO_CFGA_GPIO2OUTCFG(n)              (((uint32_t)(n) << 9) & 0x00000600)
+#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_PUSHPULL        0x00000200
+#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_OD              0x00000400
+#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_TS              0x00000600
+
+// GPIO2 input enable.
+#define AM_REG_GPIO_CFGA_GPIO2INCFG_S                8
+#define AM_REG_GPIO_CFGA_GPIO2INCFG_M                0x00000100
+#define AM_REG_GPIO_CFGA_GPIO2INCFG(n)               (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_CFGA_GPIO2INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO2INCFG_RDZERO           0x00000100
+
+// GPIO1 interrupt direction.
+#define AM_REG_GPIO_CFGA_GPIO1INTD_S                 7
+#define AM_REG_GPIO_CFGA_GPIO1INTD_M                 0x00000080
+#define AM_REG_GPIO_CFGA_GPIO1INTD(n)                (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_GPIO_CFGA_GPIO1INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO1INTD_INTHL             0x00000080
+
+// GPIO1 output configuration.
+#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_S               5
+#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_M               0x00000060
+#define AM_REG_GPIO_CFGA_GPIO1OUTCFG(n)              (((uint32_t)(n) << 5) & 0x00000060)
+#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_PUSHPULL        0x00000020
+#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_OD              0x00000040
+#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_TS              0x00000060
+
+// GPIO1 input enable.
+#define AM_REG_GPIO_CFGA_GPIO1INCFG_S                4
+#define AM_REG_GPIO_CFGA_GPIO1INCFG_M                0x00000010
+#define AM_REG_GPIO_CFGA_GPIO1INCFG(n)               (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_CFGA_GPIO1INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO1INCFG_RDZERO           0x00000010
+
+// GPIO0 interrupt direction.
+#define AM_REG_GPIO_CFGA_GPIO0INTD_S                 3
+#define AM_REG_GPIO_CFGA_GPIO0INTD_M                 0x00000008
+#define AM_REG_GPIO_CFGA_GPIO0INTD(n)                (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_GPIO_CFGA_GPIO0INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO0INTD_INTHL             0x00000008
+
+// GPIO0 output configuration.
+#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_S               1
+#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_M               0x00000006
+#define AM_REG_GPIO_CFGA_GPIO0OUTCFG(n)              (((uint32_t)(n) << 1) & 0x00000006)
+#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_PUSHPULL        0x00000002
+#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_OD              0x00000004
+#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_TS              0x00000006
+
+// GPIO0 input enable.
+#define AM_REG_GPIO_CFGA_GPIO0INCFG_S                0
+#define AM_REG_GPIO_CFGA_GPIO0INCFG_M                0x00000001
+#define AM_REG_GPIO_CFGA_GPIO0INCFG(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_CFGA_GPIO0INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGA_GPIO0INCFG_RDZERO           0x00000001
+
+//*****************************************************************************
+//
+// GPIO_CFGB - GPIO Configuration Register B
+//
+//*****************************************************************************
+// GPIO15 interrupt direction.
+#define AM_REG_GPIO_CFGB_GPIO15INTD_S                31
+#define AM_REG_GPIO_CFGB_GPIO15INTD_M                0x80000000
+#define AM_REG_GPIO_CFGB_GPIO15INTD(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_GPIO_CFGB_GPIO15INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO15INTD_INTHL            0x80000000
+
+// GPIO15 output configuration.
+#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_S              29
+#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_M              0x60000000
+#define AM_REG_GPIO_CFGB_GPIO15OUTCFG(n)             (((uint32_t)(n) << 29) & 0x60000000)
+#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_PUSHPULL       0x20000000
+#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_OD             0x40000000
+#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_TS             0x60000000
+
+// GPIO15 input enable.
+#define AM_REG_GPIO_CFGB_GPIO15INCFG_S               28
+#define AM_REG_GPIO_CFGB_GPIO15INCFG_M               0x10000000
+#define AM_REG_GPIO_CFGB_GPIO15INCFG(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_CFGB_GPIO15INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO15INCFG_RDZERO          0x10000000
+
+// GPIO14 interrupt direction.
+#define AM_REG_GPIO_CFGB_GPIO14INTD_S                27
+#define AM_REG_GPIO_CFGB_GPIO14INTD_M                0x08000000
+#define AM_REG_GPIO_CFGB_GPIO14INTD(n)               (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_GPIO_CFGB_GPIO14INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO14INTD_INTHL            0x08000000
+
+// GPIO14 output configuration.
+#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_S              25
+#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_M              0x06000000
+#define AM_REG_GPIO_CFGB_GPIO14OUTCFG(n)             (((uint32_t)(n) << 25) & 0x06000000)
+#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_PUSHPULL       0x02000000
+#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_OD             0x04000000
+#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_TS             0x06000000
+
+// GPIO14 input enable.
+#define AM_REG_GPIO_CFGB_GPIO14INCFG_S               24
+#define AM_REG_GPIO_CFGB_GPIO14INCFG_M               0x01000000
+#define AM_REG_GPIO_CFGB_GPIO14INCFG(n)              (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_CFGB_GPIO14INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO14INCFG_RDZERO          0x01000000
+
+// GPIO13 interrupt direction.
+#define AM_REG_GPIO_CFGB_GPIO13INTD_S                23
+#define AM_REG_GPIO_CFGB_GPIO13INTD_M                0x00800000
+#define AM_REG_GPIO_CFGB_GPIO13INTD(n)               (((uint32_t)(n) << 23) & 0x00800000)
+#define AM_REG_GPIO_CFGB_GPIO13INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO13INTD_INTHL            0x00800000
+
+// GPIO13 output configuration.
+#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_S              21
+#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_M              0x00600000
+#define AM_REG_GPIO_CFGB_GPIO13OUTCFG(n)             (((uint32_t)(n) << 21) & 0x00600000)
+#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_PUSHPULL       0x00200000
+#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_OD             0x00400000
+#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_TS             0x00600000
+
+// GPIO13 input enable.
+#define AM_REG_GPIO_CFGB_GPIO13INCFG_S               20
+#define AM_REG_GPIO_CFGB_GPIO13INCFG_M               0x00100000
+#define AM_REG_GPIO_CFGB_GPIO13INCFG(n)              (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_CFGB_GPIO13INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO13INCFG_RDZERO          0x00100000
+
+// GPIO12 interrupt direction.
+#define AM_REG_GPIO_CFGB_GPIO12INTD_S                19
+#define AM_REG_GPIO_CFGB_GPIO12INTD_M                0x00080000
+#define AM_REG_GPIO_CFGB_GPIO12INTD(n)               (((uint32_t)(n) << 19) & 0x00080000)
+#define AM_REG_GPIO_CFGB_GPIO12INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO12INTD_INTHL            0x00080000
+
+// GPIO12 output configuration.
+#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_S              17
+#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_M              0x00060000
+#define AM_REG_GPIO_CFGB_GPIO12OUTCFG(n)             (((uint32_t)(n) << 17) & 0x00060000)
+#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_PUSHPULL       0x00020000
+#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_OD             0x00040000
+#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_TS             0x00060000
+
+// GPIO12 input enable.
+#define AM_REG_GPIO_CFGB_GPIO12INCFG_S               16
+#define AM_REG_GPIO_CFGB_GPIO12INCFG_M               0x00010000
+#define AM_REG_GPIO_CFGB_GPIO12INCFG(n)              (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_CFGB_GPIO12INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO12INCFG_RDZERO          0x00010000
+
+// GPIO11 interrupt direction.
+#define AM_REG_GPIO_CFGB_GPIO11INTD_S                15
+#define AM_REG_GPIO_CFGB_GPIO11INTD_M                0x00008000
+#define AM_REG_GPIO_CFGB_GPIO11INTD(n)               (((uint32_t)(n) << 15) & 0x00008000)
+#define AM_REG_GPIO_CFGB_GPIO11INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO11INTD_INTHL            0x00008000
+
+// GPIO11 output configuration.
+#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_S              13
+#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_M              0x00006000
+#define AM_REG_GPIO_CFGB_GPIO11OUTCFG(n)             (((uint32_t)(n) << 13) & 0x00006000)
+#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_PUSHPULL       0x00002000
+#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_OD             0x00004000
+#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_TS             0x00006000
+
+// GPIO11 input enable.
+#define AM_REG_GPIO_CFGB_GPIO11INCFG_S               12
+#define AM_REG_GPIO_CFGB_GPIO11INCFG_M               0x00001000
+#define AM_REG_GPIO_CFGB_GPIO11INCFG(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_CFGB_GPIO11INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO11INCFG_RDZERO          0x00001000
+
+// GPIO10 interrupt direction.
+#define AM_REG_GPIO_CFGB_GPIO10INTD_S                11
+#define AM_REG_GPIO_CFGB_GPIO10INTD_M                0x00000800
+#define AM_REG_GPIO_CFGB_GPIO10INTD(n)               (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_GPIO_CFGB_GPIO10INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO10INTD_INTHL            0x00000800
+
+// GPIO10 output configuration.
+#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_S              9
+#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_M              0x00000600
+#define AM_REG_GPIO_CFGB_GPIO10OUTCFG(n)             (((uint32_t)(n) << 9) & 0x00000600)
+#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_PUSHPULL       0x00000200
+#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_OD             0x00000400
+#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_TS             0x00000600
+
+// GPIO10 input enable.
+#define AM_REG_GPIO_CFGB_GPIO10INCFG_S               8
+#define AM_REG_GPIO_CFGB_GPIO10INCFG_M               0x00000100
+#define AM_REG_GPIO_CFGB_GPIO10INCFG(n)              (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_CFGB_GPIO10INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGB_GPIO10INCFG_RDZERO          0x00000100
+
+// GPIO9 interrupt direction.
+#define AM_REG_GPIO_CFGB_GPIO9INTD_S                 7
+#define AM_REG_GPIO_CFGB_GPIO9INTD_M                 0x00000080
+#define AM_REG_GPIO_CFGB_GPIO9INTD(n)                (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_GPIO_CFGB_GPIO9INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGB_GPIO9INTD_INTHL             0x00000080
+
+// GPIO9 output configuration.
+#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_S               5
+#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_M               0x00000060
+#define AM_REG_GPIO_CFGB_GPIO9OUTCFG(n)              (((uint32_t)(n) << 5) & 0x00000060)
+#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_PUSHPULL        0x00000020
+#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_OD              0x00000040
+#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_TS              0x00000060
+
+// GPIO9 input enable.
+#define AM_REG_GPIO_CFGB_GPIO9INCFG_S                4
+#define AM_REG_GPIO_CFGB_GPIO9INCFG_M                0x00000010
+#define AM_REG_GPIO_CFGB_GPIO9INCFG(n)               (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_CFGB_GPIO9INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGB_GPIO9INCFG_RDZERO           0x00000010
+
+// GPIO8 interrupt direction.
+#define AM_REG_GPIO_CFGB_GPIO8INTD_S                 3
+#define AM_REG_GPIO_CFGB_GPIO8INTD_M                 0x00000008
+#define AM_REG_GPIO_CFGB_GPIO8INTD(n)                (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_GPIO_CFGB_GPIO8INTD_INTLH             0x00000000
+#define AM_REG_GPIO_CFGB_GPIO8INTD_INTHL             0x00000008
+
+// GPIO8 output configuration.
+#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_S               1
+#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_M               0x00000006
+#define AM_REG_GPIO_CFGB_GPIO8OUTCFG(n)              (((uint32_t)(n) << 1) & 0x00000006)
+#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_DIS             0x00000000
+#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_PUSHPULL        0x00000002
+#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_OD              0x00000004
+#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_TS              0x00000006
+
+// GPIO8 input enable.
+#define AM_REG_GPIO_CFGB_GPIO8INCFG_S                0
+#define AM_REG_GPIO_CFGB_GPIO8INCFG_M                0x00000001
+#define AM_REG_GPIO_CFGB_GPIO8INCFG(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_CFGB_GPIO8INCFG_READ             0x00000000
+#define AM_REG_GPIO_CFGB_GPIO8INCFG_RDZERO           0x00000001
+
+//*****************************************************************************
+//
+// GPIO_CFGC - GPIO Configuration Register C
+//
+//*****************************************************************************
+// GPIO23 interrupt direction.
+#define AM_REG_GPIO_CFGC_GPIO23INTD_S                31
+#define AM_REG_GPIO_CFGC_GPIO23INTD_M                0x80000000
+#define AM_REG_GPIO_CFGC_GPIO23INTD(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_GPIO_CFGC_GPIO23INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO23INTD_INTHL            0x80000000
+
+// GPIO23 output configuration.
+#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_S              29
+#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_M              0x60000000
+#define AM_REG_GPIO_CFGC_GPIO23OUTCFG(n)             (((uint32_t)(n) << 29) & 0x60000000)
+#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_PUSHPULL       0x20000000
+#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_OD             0x40000000
+#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_TS             0x60000000
+
+// GPIO23 input enable.
+#define AM_REG_GPIO_CFGC_GPIO23INCFG_S               28
+#define AM_REG_GPIO_CFGC_GPIO23INCFG_M               0x10000000
+#define AM_REG_GPIO_CFGC_GPIO23INCFG(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_CFGC_GPIO23INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO23INCFG_RDZERO          0x10000000
+
+// GPIO22 interrupt direction.
+#define AM_REG_GPIO_CFGC_GPIO22INTD_S                27
+#define AM_REG_GPIO_CFGC_GPIO22INTD_M                0x08000000
+#define AM_REG_GPIO_CFGC_GPIO22INTD(n)               (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_GPIO_CFGC_GPIO22INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO22INTD_INTHL            0x08000000
+
+// GPIO22 output configuration.
+#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_S              25
+#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_M              0x06000000
+#define AM_REG_GPIO_CFGC_GPIO22OUTCFG(n)             (((uint32_t)(n) << 25) & 0x06000000)
+#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_PUSHPULL       0x02000000
+#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_OD             0x04000000
+#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_TS             0x06000000
+
+// GPIO22 input enable.
+#define AM_REG_GPIO_CFGC_GPIO22INCFG_S               24
+#define AM_REG_GPIO_CFGC_GPIO22INCFG_M               0x01000000
+#define AM_REG_GPIO_CFGC_GPIO22INCFG(n)              (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_CFGC_GPIO22INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO22INCFG_RDZERO          0x01000000
+
+// GPIO21 interrupt direction.
+#define AM_REG_GPIO_CFGC_GPIO21INTD_S                23
+#define AM_REG_GPIO_CFGC_GPIO21INTD_M                0x00800000
+#define AM_REG_GPIO_CFGC_GPIO21INTD(n)               (((uint32_t)(n) << 23) & 0x00800000)
+#define AM_REG_GPIO_CFGC_GPIO21INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO21INTD_INTHL            0x00800000
+
+// GPIO21 output configuration.
+#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_S              21
+#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_M              0x00600000
+#define AM_REG_GPIO_CFGC_GPIO21OUTCFG(n)             (((uint32_t)(n) << 21) & 0x00600000)
+#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_PUSHPULL       0x00200000
+#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_OD             0x00400000
+#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_TS             0x00600000
+
+// GPIO21 input enable.
+#define AM_REG_GPIO_CFGC_GPIO21INCFG_S               20
+#define AM_REG_GPIO_CFGC_GPIO21INCFG_M               0x00100000
+#define AM_REG_GPIO_CFGC_GPIO21INCFG(n)              (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_CFGC_GPIO21INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO21INCFG_RDZERO          0x00100000
+
+// GPIO20 interrupt direction.
+#define AM_REG_GPIO_CFGC_GPIO20INTD_S                19
+#define AM_REG_GPIO_CFGC_GPIO20INTD_M                0x00080000
+#define AM_REG_GPIO_CFGC_GPIO20INTD(n)               (((uint32_t)(n) << 19) & 0x00080000)
+#define AM_REG_GPIO_CFGC_GPIO20INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO20INTD_INTHL            0x00080000
+
+// GPIO20 output configuration.
+#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_S              17
+#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_M              0x00060000
+#define AM_REG_GPIO_CFGC_GPIO20OUTCFG(n)             (((uint32_t)(n) << 17) & 0x00060000)
+#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_PUSHPULL       0x00020000
+#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_OD             0x00040000
+#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_TS             0x00060000
+
+// GPIO20 input enable.
+#define AM_REG_GPIO_CFGC_GPIO20INCFG_S               16
+#define AM_REG_GPIO_CFGC_GPIO20INCFG_M               0x00010000
+#define AM_REG_GPIO_CFGC_GPIO20INCFG(n)              (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_CFGC_GPIO20INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO20INCFG_RDZERO          0x00010000
+
+// GPIO19 interrupt direction.
+#define AM_REG_GPIO_CFGC_GPIO19INTD_S                15
+#define AM_REG_GPIO_CFGC_GPIO19INTD_M                0x00008000
+#define AM_REG_GPIO_CFGC_GPIO19INTD(n)               (((uint32_t)(n) << 15) & 0x00008000)
+#define AM_REG_GPIO_CFGC_GPIO19INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO19INTD_INTHL            0x00008000
+
+// GPIO19 output configuration.
+#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_S              13
+#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_M              0x00006000
+#define AM_REG_GPIO_CFGC_GPIO19OUTCFG(n)             (((uint32_t)(n) << 13) & 0x00006000)
+#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_PUSHPULL       0x00002000
+#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_OD             0x00004000
+#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_TS             0x00006000
+
+// GPIO19 input enable.
+#define AM_REG_GPIO_CFGC_GPIO19INCFG_S               12
+#define AM_REG_GPIO_CFGC_GPIO19INCFG_M               0x00001000
+#define AM_REG_GPIO_CFGC_GPIO19INCFG(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_CFGC_GPIO19INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO19INCFG_RDZERO          0x00001000
+
+// GPIO18 interrupt direction.
+#define AM_REG_GPIO_CFGC_GPIO18INTD_S                11
+#define AM_REG_GPIO_CFGC_GPIO18INTD_M                0x00000800
+#define AM_REG_GPIO_CFGC_GPIO18INTD(n)               (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_GPIO_CFGC_GPIO18INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO18INTD_INTHL            0x00000800
+
+// GPIO18 output configuration.
+#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_S              9
+#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_M              0x00000600
+#define AM_REG_GPIO_CFGC_GPIO18OUTCFG(n)             (((uint32_t)(n) << 9) & 0x00000600)
+#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_PUSHPULL       0x00000200
+#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_OD             0x00000400
+#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_TS             0x00000600
+
+// GPIO18 input enable.
+#define AM_REG_GPIO_CFGC_GPIO18INCFG_S               8
+#define AM_REG_GPIO_CFGC_GPIO18INCFG_M               0x00000100
+#define AM_REG_GPIO_CFGC_GPIO18INCFG(n)              (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_CFGC_GPIO18INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO18INCFG_RDZERO          0x00000100
+
+// GPIO17 interrupt direction.
+#define AM_REG_GPIO_CFGC_GPIO17INTD_S                7
+#define AM_REG_GPIO_CFGC_GPIO17INTD_M                0x00000080
+#define AM_REG_GPIO_CFGC_GPIO17INTD(n)               (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_GPIO_CFGC_GPIO17INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO17INTD_INTHL            0x00000080
+
+// GPIO17 output configuration.
+#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_S              5
+#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_M              0x00000060
+#define AM_REG_GPIO_CFGC_GPIO17OUTCFG(n)             (((uint32_t)(n) << 5) & 0x00000060)
+#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_PUSHPULL       0x00000020
+#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_OD             0x00000040
+#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_TS             0x00000060
+
+// GPIO17 input enable.
+#define AM_REG_GPIO_CFGC_GPIO17INCFG_S               4
+#define AM_REG_GPIO_CFGC_GPIO17INCFG_M               0x00000010
+#define AM_REG_GPIO_CFGC_GPIO17INCFG(n)              (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_CFGC_GPIO17INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO17INCFG_RDZERO          0x00000010
+
+// GPIO16 interrupt direction.
+#define AM_REG_GPIO_CFGC_GPIO16INTD_S                3
+#define AM_REG_GPIO_CFGC_GPIO16INTD_M                0x00000008
+#define AM_REG_GPIO_CFGC_GPIO16INTD(n)               (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_GPIO_CFGC_GPIO16INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO16INTD_INTHL            0x00000008
+
+// GPIO16 output configuration.
+#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_S              1
+#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_M              0x00000006
+#define AM_REG_GPIO_CFGC_GPIO16OUTCFG(n)             (((uint32_t)(n) << 1) & 0x00000006)
+#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_PUSHPULL       0x00000002
+#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_OD             0x00000004
+#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_TS             0x00000006
+
+// GPIO16 input enable.
+#define AM_REG_GPIO_CFGC_GPIO16INCFG_S               0
+#define AM_REG_GPIO_CFGC_GPIO16INCFG_M               0x00000001
+#define AM_REG_GPIO_CFGC_GPIO16INCFG(n)              (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_CFGC_GPIO16INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGC_GPIO16INCFG_RDZERO          0x00000001
+
+//*****************************************************************************
+//
+// GPIO_CFGD - GPIO Configuration Register D
+//
+//*****************************************************************************
+// GPIO31 interrupt direction.
+#define AM_REG_GPIO_CFGD_GPIO31INTD_S                31
+#define AM_REG_GPIO_CFGD_GPIO31INTD_M                0x80000000
+#define AM_REG_GPIO_CFGD_GPIO31INTD(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_GPIO_CFGD_GPIO31INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO31INTD_INTHL            0x80000000
+
+// GPIO31 output configuration.
+#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_S              29
+#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_M              0x60000000
+#define AM_REG_GPIO_CFGD_GPIO31OUTCFG(n)             (((uint32_t)(n) << 29) & 0x60000000)
+#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_PUSHPULL       0x20000000
+#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_OD             0x40000000
+#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_TS             0x60000000
+
+// GPIO31 input enable.
+#define AM_REG_GPIO_CFGD_GPIO31INCFG_S               28
+#define AM_REG_GPIO_CFGD_GPIO31INCFG_M               0x10000000
+#define AM_REG_GPIO_CFGD_GPIO31INCFG(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_CFGD_GPIO31INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO31INCFG_RDZERO          0x10000000
+
+// GPIO30 interrupt direction.
+#define AM_REG_GPIO_CFGD_GPIO30INTD_S                27
+#define AM_REG_GPIO_CFGD_GPIO30INTD_M                0x08000000
+#define AM_REG_GPIO_CFGD_GPIO30INTD(n)               (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_GPIO_CFGD_GPIO30INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO30INTD_INTHL            0x08000000
+
+// GPIO30 output configuration.
+#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_S              25
+#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_M              0x06000000
+#define AM_REG_GPIO_CFGD_GPIO30OUTCFG(n)             (((uint32_t)(n) << 25) & 0x06000000)
+#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_PUSHPULL       0x02000000
+#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_OD             0x04000000
+#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_TS             0x06000000
+
+// GPIO30 input enable.
+#define AM_REG_GPIO_CFGD_GPIO30INCFG_S               24
+#define AM_REG_GPIO_CFGD_GPIO30INCFG_M               0x01000000
+#define AM_REG_GPIO_CFGD_GPIO30INCFG(n)              (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_CFGD_GPIO30INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO30INCFG_RDZERO          0x01000000
+
+// GPIO29 interrupt direction.
+#define AM_REG_GPIO_CFGD_GPIO29INTD_S                23
+#define AM_REG_GPIO_CFGD_GPIO29INTD_M                0x00800000
+#define AM_REG_GPIO_CFGD_GPIO29INTD(n)               (((uint32_t)(n) << 23) & 0x00800000)
+#define AM_REG_GPIO_CFGD_GPIO29INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO29INTD_INTHL            0x00800000
+
+// GPIO29 output configuration.
+#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_S              21
+#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_M              0x00600000
+#define AM_REG_GPIO_CFGD_GPIO29OUTCFG(n)             (((uint32_t)(n) << 21) & 0x00600000)
+#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_PUSHPULL       0x00200000
+#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_OD             0x00400000
+#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_TS             0x00600000
+
+// GPIO29 input enable.
+#define AM_REG_GPIO_CFGD_GPIO29INCFG_S               20
+#define AM_REG_GPIO_CFGD_GPIO29INCFG_M               0x00100000
+#define AM_REG_GPIO_CFGD_GPIO29INCFG(n)              (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_CFGD_GPIO29INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO29INCFG_RDZERO          0x00100000
+
+// GPIO28 interrupt direction.
+#define AM_REG_GPIO_CFGD_GPIO28INTD_S                19
+#define AM_REG_GPIO_CFGD_GPIO28INTD_M                0x00080000
+#define AM_REG_GPIO_CFGD_GPIO28INTD(n)               (((uint32_t)(n) << 19) & 0x00080000)
+#define AM_REG_GPIO_CFGD_GPIO28INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO28INTD_INTHL            0x00080000
+
+// GPIO28 output configuration.
+#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_S              17
+#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_M              0x00060000
+#define AM_REG_GPIO_CFGD_GPIO28OUTCFG(n)             (((uint32_t)(n) << 17) & 0x00060000)
+#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_PUSHPULL       0x00020000
+#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_OD             0x00040000
+#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_TS             0x00060000
+
+// GPIO28 input enable.
+#define AM_REG_GPIO_CFGD_GPIO28INCFG_S               16
+#define AM_REG_GPIO_CFGD_GPIO28INCFG_M               0x00010000
+#define AM_REG_GPIO_CFGD_GPIO28INCFG(n)              (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_CFGD_GPIO28INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO28INCFG_RDZERO          0x00010000
+
+// GPIO27 interrupt direction.
+#define AM_REG_GPIO_CFGD_GPIO27INTD_S                15
+#define AM_REG_GPIO_CFGD_GPIO27INTD_M                0x00008000
+#define AM_REG_GPIO_CFGD_GPIO27INTD(n)               (((uint32_t)(n) << 15) & 0x00008000)
+#define AM_REG_GPIO_CFGD_GPIO27INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO27INTD_INTHL            0x00008000
+
+// GPIO27 output configuration.
+#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_S              13
+#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_M              0x00006000
+#define AM_REG_GPIO_CFGD_GPIO27OUTCFG(n)             (((uint32_t)(n) << 13) & 0x00006000)
+#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_PUSHPULL       0x00002000
+#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_OD             0x00004000
+#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_TS             0x00006000
+
+// GPIO27 input enable.
+#define AM_REG_GPIO_CFGD_GPIO27INCFG_S               12
+#define AM_REG_GPIO_CFGD_GPIO27INCFG_M               0x00001000
+#define AM_REG_GPIO_CFGD_GPIO27INCFG(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_CFGD_GPIO27INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO27INCFG_RDZERO          0x00001000
+
+// GPIO26 interrupt direction.
+#define AM_REG_GPIO_CFGD_GPIO26INTD_S                11
+#define AM_REG_GPIO_CFGD_GPIO26INTD_M                0x00000800
+#define AM_REG_GPIO_CFGD_GPIO26INTD(n)               (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_GPIO_CFGD_GPIO26INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO26INTD_INTHL            0x00000800
+
+// GPIO26 output configuration.
+#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_S              9
+#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_M              0x00000600
+#define AM_REG_GPIO_CFGD_GPIO26OUTCFG(n)             (((uint32_t)(n) << 9) & 0x00000600)
+#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_PUSHPULL       0x00000200
+#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_OD             0x00000400
+#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_TS             0x00000600
+
+// GPIO26 input enable.
+#define AM_REG_GPIO_CFGD_GPIO26INCFG_S               8
+#define AM_REG_GPIO_CFGD_GPIO26INCFG_M               0x00000100
+#define AM_REG_GPIO_CFGD_GPIO26INCFG(n)              (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_CFGD_GPIO26INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO26INCFG_RDZERO          0x00000100
+
+// GPIO25 interrupt direction.
+#define AM_REG_GPIO_CFGD_GPIO25INTD_S                7
+#define AM_REG_GPIO_CFGD_GPIO25INTD_M                0x00000080
+#define AM_REG_GPIO_CFGD_GPIO25INTD(n)               (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_GPIO_CFGD_GPIO25INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO25INTD_INTHL            0x00000080
+
+// GPIO25 output configuration.
+#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_S              5
+#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_M              0x00000060
+#define AM_REG_GPIO_CFGD_GPIO25OUTCFG(n)             (((uint32_t)(n) << 5) & 0x00000060)
+#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_PUSHPULL       0x00000020
+#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_OD             0x00000040
+#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_TS             0x00000060
+
+// GPIO25 input enable.
+#define AM_REG_GPIO_CFGD_GPIO25INCFG_S               4
+#define AM_REG_GPIO_CFGD_GPIO25INCFG_M               0x00000010
+#define AM_REG_GPIO_CFGD_GPIO25INCFG(n)              (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_CFGD_GPIO25INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO25INCFG_RDZERO          0x00000010
+
+// GPIO24 interrupt direction.
+#define AM_REG_GPIO_CFGD_GPIO24INTD_S                3
+#define AM_REG_GPIO_CFGD_GPIO24INTD_M                0x00000008
+#define AM_REG_GPIO_CFGD_GPIO24INTD(n)               (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_GPIO_CFGD_GPIO24INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO24INTD_INTHL            0x00000008
+
+// GPIO24 output configuration.
+#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_S              1
+#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_M              0x00000006
+#define AM_REG_GPIO_CFGD_GPIO24OUTCFG(n)             (((uint32_t)(n) << 1) & 0x00000006)
+#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_PUSHPULL       0x00000002
+#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_OD             0x00000004
+#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_TS             0x00000006
+
+// GPIO24 input enable.
+#define AM_REG_GPIO_CFGD_GPIO24INCFG_S               0
+#define AM_REG_GPIO_CFGD_GPIO24INCFG_M               0x00000001
+#define AM_REG_GPIO_CFGD_GPIO24INCFG(n)              (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_CFGD_GPIO24INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGD_GPIO24INCFG_RDZERO          0x00000001
+
+//*****************************************************************************
+//
+// GPIO_CFGE - GPIO Configuration Register E
+//
+//*****************************************************************************
+// GPIO39 interrupt direction.
+#define AM_REG_GPIO_CFGE_GPIO39INTD_S                31
+#define AM_REG_GPIO_CFGE_GPIO39INTD_M                0x80000000
+#define AM_REG_GPIO_CFGE_GPIO39INTD(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_GPIO_CFGE_GPIO39INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO39INTD_INTHL            0x80000000
+
+// GPIO39 output configuration.
+#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_S              29
+#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_M              0x60000000
+#define AM_REG_GPIO_CFGE_GPIO39OUTCFG(n)             (((uint32_t)(n) << 29) & 0x60000000)
+#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_PUSHPULL       0x20000000
+#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_OD             0x40000000
+#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_TS             0x60000000
+
+// GPIO39 input enable.
+#define AM_REG_GPIO_CFGE_GPIO39INCFG_S               28
+#define AM_REG_GPIO_CFGE_GPIO39INCFG_M               0x10000000
+#define AM_REG_GPIO_CFGE_GPIO39INCFG(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_CFGE_GPIO39INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO39INCFG_RDZERO          0x10000000
+
+// GPIO38 interrupt direction.
+#define AM_REG_GPIO_CFGE_GPIO38INTD_S                27
+#define AM_REG_GPIO_CFGE_GPIO38INTD_M                0x08000000
+#define AM_REG_GPIO_CFGE_GPIO38INTD(n)               (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_GPIO_CFGE_GPIO38INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO38INTD_INTHL            0x08000000
+
+// GPIO38 output configuration.
+#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_S              25
+#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_M              0x06000000
+#define AM_REG_GPIO_CFGE_GPIO38OUTCFG(n)             (((uint32_t)(n) << 25) & 0x06000000)
+#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_PUSHPULL       0x02000000
+#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_OD             0x04000000
+#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_TS             0x06000000
+
+// GPIO38 input enable.
+#define AM_REG_GPIO_CFGE_GPIO38INCFG_S               24
+#define AM_REG_GPIO_CFGE_GPIO38INCFG_M               0x01000000
+#define AM_REG_GPIO_CFGE_GPIO38INCFG(n)              (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_CFGE_GPIO38INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO38INCFG_RDZERO          0x01000000
+
+// GPIO37 interrupt direction.
+#define AM_REG_GPIO_CFGE_GPIO37INTD_S                23
+#define AM_REG_GPIO_CFGE_GPIO37INTD_M                0x00800000
+#define AM_REG_GPIO_CFGE_GPIO37INTD(n)               (((uint32_t)(n) << 23) & 0x00800000)
+#define AM_REG_GPIO_CFGE_GPIO37INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO37INTD_INTHL            0x00800000
+
+// GPIO37 output configuration.
+#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_S              21
+#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_M              0x00600000
+#define AM_REG_GPIO_CFGE_GPIO37OUTCFG(n)             (((uint32_t)(n) << 21) & 0x00600000)
+#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_PUSHPULL       0x00200000
+#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_OD             0x00400000
+#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_TS             0x00600000
+
+// GPIO37 input enable.
+#define AM_REG_GPIO_CFGE_GPIO37INCFG_S               20
+#define AM_REG_GPIO_CFGE_GPIO37INCFG_M               0x00100000
+#define AM_REG_GPIO_CFGE_GPIO37INCFG(n)              (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_CFGE_GPIO37INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO37INCFG_RDZERO          0x00100000
+
+// GPIO36 interrupt direction.
+#define AM_REG_GPIO_CFGE_GPIO36INTD_S                19
+#define AM_REG_GPIO_CFGE_GPIO36INTD_M                0x00080000
+#define AM_REG_GPIO_CFGE_GPIO36INTD(n)               (((uint32_t)(n) << 19) & 0x00080000)
+#define AM_REG_GPIO_CFGE_GPIO36INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO36INTD_INTHL            0x00080000
+
+// GPIO36 output configuration.
+#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_S              17
+#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_M              0x00060000
+#define AM_REG_GPIO_CFGE_GPIO36OUTCFG(n)             (((uint32_t)(n) << 17) & 0x00060000)
+#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_PUSHPULL       0x00020000
+#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_OD             0x00040000
+#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_TS             0x00060000
+
+// GPIO36 input enable.
+#define AM_REG_GPIO_CFGE_GPIO36INCFG_S               16
+#define AM_REG_GPIO_CFGE_GPIO36INCFG_M               0x00010000
+#define AM_REG_GPIO_CFGE_GPIO36INCFG(n)              (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_CFGE_GPIO36INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO36INCFG_RDZERO          0x00010000
+
+// GPIO35 interrupt direction.
+#define AM_REG_GPIO_CFGE_GPIO35INTD_S                15
+#define AM_REG_GPIO_CFGE_GPIO35INTD_M                0x00008000
+#define AM_REG_GPIO_CFGE_GPIO35INTD(n)               (((uint32_t)(n) << 15) & 0x00008000)
+#define AM_REG_GPIO_CFGE_GPIO35INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO35INTD_INTHL            0x00008000
+
+// GPIO35 output configuration.
+#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_S              13
+#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_M              0x00006000
+#define AM_REG_GPIO_CFGE_GPIO35OUTCFG(n)             (((uint32_t)(n) << 13) & 0x00006000)
+#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_PUSHPULL       0x00002000
+#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_OD             0x00004000
+#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_TS             0x00006000
+
+// GPIO35 input enable.
+#define AM_REG_GPIO_CFGE_GPIO35INCFG_S               12
+#define AM_REG_GPIO_CFGE_GPIO35INCFG_M               0x00001000
+#define AM_REG_GPIO_CFGE_GPIO35INCFG(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_CFGE_GPIO35INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO35INCFG_RDZERO          0x00001000
+
+// GPIO34 interrupt direction.
+#define AM_REG_GPIO_CFGE_GPIO34INTD_S                11
+#define AM_REG_GPIO_CFGE_GPIO34INTD_M                0x00000800
+#define AM_REG_GPIO_CFGE_GPIO34INTD(n)               (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_GPIO_CFGE_GPIO34INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO34INTD_INTHL            0x00000800
+
+// GPIO34 output configuration.
+#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_S              9
+#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_M              0x00000600
+#define AM_REG_GPIO_CFGE_GPIO34OUTCFG(n)             (((uint32_t)(n) << 9) & 0x00000600)
+#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_PUSHPULL       0x00000200
+#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_OD             0x00000400
+#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_TS             0x00000600
+
+// GPIO34 input enable.
+#define AM_REG_GPIO_CFGE_GPIO34INCFG_S               8
+#define AM_REG_GPIO_CFGE_GPIO34INCFG_M               0x00000100
+#define AM_REG_GPIO_CFGE_GPIO34INCFG(n)              (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_CFGE_GPIO34INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO34INCFG_RDZERO          0x00000100
+
+// GPIO33 interrupt direction.
+#define AM_REG_GPIO_CFGE_GPIO33INTD_S                7
+#define AM_REG_GPIO_CFGE_GPIO33INTD_M                0x00000080
+#define AM_REG_GPIO_CFGE_GPIO33INTD(n)               (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_GPIO_CFGE_GPIO33INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO33INTD_INTHL            0x00000080
+
+// GPIO33 output configuration.
+#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_S              5
+#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_M              0x00000060
+#define AM_REG_GPIO_CFGE_GPIO33OUTCFG(n)             (((uint32_t)(n) << 5) & 0x00000060)
+#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_PUSHPULL       0x00000020
+#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_OD             0x00000040
+#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_TS             0x00000060
+
+// GPIO33 input enable.
+#define AM_REG_GPIO_CFGE_GPIO33INCFG_S               4
+#define AM_REG_GPIO_CFGE_GPIO33INCFG_M               0x00000010
+#define AM_REG_GPIO_CFGE_GPIO33INCFG(n)              (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_CFGE_GPIO33INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO33INCFG_RDZERO          0x00000010
+
+// GPIO32 interrupt direction.
+#define AM_REG_GPIO_CFGE_GPIO32INTD_S                3
+#define AM_REG_GPIO_CFGE_GPIO32INTD_M                0x00000008
+#define AM_REG_GPIO_CFGE_GPIO32INTD(n)               (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_GPIO_CFGE_GPIO32INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO32INTD_INTHL            0x00000008
+
+// GPIO32 output configuration.
+#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_S              1
+#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_M              0x00000006
+#define AM_REG_GPIO_CFGE_GPIO32OUTCFG(n)             (((uint32_t)(n) << 1) & 0x00000006)
+#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_PUSHPULL       0x00000002
+#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_OD             0x00000004
+#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_TS             0x00000006
+
+// GPIO32 input enable.
+#define AM_REG_GPIO_CFGE_GPIO32INCFG_S               0
+#define AM_REG_GPIO_CFGE_GPIO32INCFG_M               0x00000001
+#define AM_REG_GPIO_CFGE_GPIO32INCFG(n)              (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_CFGE_GPIO32INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGE_GPIO32INCFG_RDZERO          0x00000001
+
+//*****************************************************************************
+//
+// GPIO_CFGF - GPIO Configuration Register F
+//
+//*****************************************************************************
+// GPIO47 interrupt direction.
+#define AM_REG_GPIO_CFGF_GPIO47INTD_S                31
+#define AM_REG_GPIO_CFGF_GPIO47INTD_M                0x80000000
+#define AM_REG_GPIO_CFGF_GPIO47INTD(n)               (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_GPIO_CFGF_GPIO47INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO47INTD_INTHL            0x80000000
+
+// GPIO47 output configuration.
+#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_S              29
+#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_M              0x60000000
+#define AM_REG_GPIO_CFGF_GPIO47OUTCFG(n)             (((uint32_t)(n) << 29) & 0x60000000)
+#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_PUSHPULL       0x20000000
+#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_OD             0x40000000
+#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_TS             0x60000000
+
+// GPIO47 input enable.
+#define AM_REG_GPIO_CFGF_GPIO47INCFG_S               28
+#define AM_REG_GPIO_CFGF_GPIO47INCFG_M               0x10000000
+#define AM_REG_GPIO_CFGF_GPIO47INCFG(n)              (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_CFGF_GPIO47INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO47INCFG_RDZERO          0x10000000
+
+// GPIO46 interrupt direction.
+#define AM_REG_GPIO_CFGF_GPIO46INTD_S                27
+#define AM_REG_GPIO_CFGF_GPIO46INTD_M                0x08000000
+#define AM_REG_GPIO_CFGF_GPIO46INTD(n)               (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_GPIO_CFGF_GPIO46INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO46INTD_INTHL            0x08000000
+
+// GPIO46 output configuration.
+#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_S              25
+#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_M              0x06000000
+#define AM_REG_GPIO_CFGF_GPIO46OUTCFG(n)             (((uint32_t)(n) << 25) & 0x06000000)
+#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_PUSHPULL       0x02000000
+#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_OD             0x04000000
+#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_TS             0x06000000
+
+// GPIO46 input enable.
+#define AM_REG_GPIO_CFGF_GPIO46INCFG_S               24
+#define AM_REG_GPIO_CFGF_GPIO46INCFG_M               0x01000000
+#define AM_REG_GPIO_CFGF_GPIO46INCFG(n)              (((uint32_t)(n) << 24) & 0x01000000)
+#define AM_REG_GPIO_CFGF_GPIO46INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO46INCFG_RDZERO          0x01000000
+
+// GPIO45 interrupt direction.
+#define AM_REG_GPIO_CFGF_GPIO45INTD_S                23
+#define AM_REG_GPIO_CFGF_GPIO45INTD_M                0x00800000
+#define AM_REG_GPIO_CFGF_GPIO45INTD(n)               (((uint32_t)(n) << 23) & 0x00800000)
+#define AM_REG_GPIO_CFGF_GPIO45INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO45INTD_INTHL            0x00800000
+
+// GPIO45 output configuration.
+#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_S              21
+#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_M              0x00600000
+#define AM_REG_GPIO_CFGF_GPIO45OUTCFG(n)             (((uint32_t)(n) << 21) & 0x00600000)
+#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_PUSHPULL       0x00200000
+#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_OD             0x00400000
+#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_TS             0x00600000
+
+// GPIO45 input enable.
+#define AM_REG_GPIO_CFGF_GPIO45INCFG_S               20
+#define AM_REG_GPIO_CFGF_GPIO45INCFG_M               0x00100000
+#define AM_REG_GPIO_CFGF_GPIO45INCFG(n)              (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_CFGF_GPIO45INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO45INCFG_RDZERO          0x00100000
+
+// GPIO44 interrupt direction.
+#define AM_REG_GPIO_CFGF_GPIO44INTD_S                19
+#define AM_REG_GPIO_CFGF_GPIO44INTD_M                0x00080000
+#define AM_REG_GPIO_CFGF_GPIO44INTD(n)               (((uint32_t)(n) << 19) & 0x00080000)
+#define AM_REG_GPIO_CFGF_GPIO44INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO44INTD_INTHL            0x00080000
+
+// GPIO44 output configuration.
+#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_S              17
+#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_M              0x00060000
+#define AM_REG_GPIO_CFGF_GPIO44OUTCFG(n)             (((uint32_t)(n) << 17) & 0x00060000)
+#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_PUSHPULL       0x00020000
+#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_OD             0x00040000
+#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_TS             0x00060000
+
+// GPIO44 input enable.
+#define AM_REG_GPIO_CFGF_GPIO44INCFG_S               16
+#define AM_REG_GPIO_CFGF_GPIO44INCFG_M               0x00010000
+#define AM_REG_GPIO_CFGF_GPIO44INCFG(n)              (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_GPIO_CFGF_GPIO44INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO44INCFG_RDZERO          0x00010000
+
+// GPIO43 interrupt direction.
+#define AM_REG_GPIO_CFGF_GPIO43INTD_S                15
+#define AM_REG_GPIO_CFGF_GPIO43INTD_M                0x00008000
+#define AM_REG_GPIO_CFGF_GPIO43INTD(n)               (((uint32_t)(n) << 15) & 0x00008000)
+#define AM_REG_GPIO_CFGF_GPIO43INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO43INTD_INTHL            0x00008000
+
+// GPIO43 output configuration.
+#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_S              13
+#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_M              0x00006000
+#define AM_REG_GPIO_CFGF_GPIO43OUTCFG(n)             (((uint32_t)(n) << 13) & 0x00006000)
+#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_PUSHPULL       0x00002000
+#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_OD             0x00004000
+#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_TS             0x00006000
+
+// GPIO43 input enable.
+#define AM_REG_GPIO_CFGF_GPIO43INCFG_S               12
+#define AM_REG_GPIO_CFGF_GPIO43INCFG_M               0x00001000
+#define AM_REG_GPIO_CFGF_GPIO43INCFG(n)              (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_CFGF_GPIO43INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO43INCFG_RDZERO          0x00001000
+
+// GPIO42 interrupt direction.
+#define AM_REG_GPIO_CFGF_GPIO42INTD_S                11
+#define AM_REG_GPIO_CFGF_GPIO42INTD_M                0x00000800
+#define AM_REG_GPIO_CFGF_GPIO42INTD(n)               (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_GPIO_CFGF_GPIO42INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO42INTD_INTHL            0x00000800
+
+// GPIO42 output configuration.
+#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_S              9
+#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_M              0x00000600
+#define AM_REG_GPIO_CFGF_GPIO42OUTCFG(n)             (((uint32_t)(n) << 9) & 0x00000600)
+#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_PUSHPULL       0x00000200
+#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_OD             0x00000400
+#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_TS             0x00000600
+
+// GPIO42 input enable.
+#define AM_REG_GPIO_CFGF_GPIO42INCFG_S               8
+#define AM_REG_GPIO_CFGF_GPIO42INCFG_M               0x00000100
+#define AM_REG_GPIO_CFGF_GPIO42INCFG(n)              (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_GPIO_CFGF_GPIO42INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO42INCFG_RDZERO          0x00000100
+
+// GPIO41 interrupt direction.
+#define AM_REG_GPIO_CFGF_GPIO41INTD_S                7
+#define AM_REG_GPIO_CFGF_GPIO41INTD_M                0x00000080
+#define AM_REG_GPIO_CFGF_GPIO41INTD(n)               (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_GPIO_CFGF_GPIO41INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO41INTD_INTHL            0x00000080
+
+// GPIO41 output configuration.
+#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_S              5
+#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_M              0x00000060
+#define AM_REG_GPIO_CFGF_GPIO41OUTCFG(n)             (((uint32_t)(n) << 5) & 0x00000060)
+#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_PUSHPULL       0x00000020
+#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_OD             0x00000040
+#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_TS             0x00000060
+
+// GPIO41 input enable.
+#define AM_REG_GPIO_CFGF_GPIO41INCFG_S               4
+#define AM_REG_GPIO_CFGF_GPIO41INCFG_M               0x00000010
+#define AM_REG_GPIO_CFGF_GPIO41INCFG(n)              (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_CFGF_GPIO41INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO41INCFG_RDZERO          0x00000010
+
+// GPIO40 interrupt direction.
+#define AM_REG_GPIO_CFGF_GPIO40INTD_S                3
+#define AM_REG_GPIO_CFGF_GPIO40INTD_M                0x00000008
+#define AM_REG_GPIO_CFGF_GPIO40INTD(n)               (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_GPIO_CFGF_GPIO40INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO40INTD_INTHL            0x00000008
+
+// GPIO40 output configuration.
+#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_S              1
+#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_M              0x00000006
+#define AM_REG_GPIO_CFGF_GPIO40OUTCFG(n)             (((uint32_t)(n) << 1) & 0x00000006)
+#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_PUSHPULL       0x00000002
+#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_OD             0x00000004
+#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_TS             0x00000006
+
+// GPIO40 input enable.
+#define AM_REG_GPIO_CFGF_GPIO40INCFG_S               0
+#define AM_REG_GPIO_CFGF_GPIO40INCFG_M               0x00000001
+#define AM_REG_GPIO_CFGF_GPIO40INCFG(n)              (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_CFGF_GPIO40INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGF_GPIO40INCFG_RDZERO          0x00000001
+
+//*****************************************************************************
+//
+// GPIO_CFGG - GPIO Configuration Register G
+//
+//*****************************************************************************
+// GPIO49 interrupt direction.
+#define AM_REG_GPIO_CFGG_GPIO49INTD_S                7
+#define AM_REG_GPIO_CFGG_GPIO49INTD_M                0x00000080
+#define AM_REG_GPIO_CFGG_GPIO49INTD(n)               (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_GPIO_CFGG_GPIO49INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGG_GPIO49INTD_INTHL            0x00000080
+
+// GPIO49 output configuration.
+#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_S              5
+#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_M              0x00000060
+#define AM_REG_GPIO_CFGG_GPIO49OUTCFG(n)             (((uint32_t)(n) << 5) & 0x00000060)
+#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_PUSHPULL       0x00000020
+#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_OD             0x00000040
+#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_TS             0x00000060
+
+// GPIO49 input enable.
+#define AM_REG_GPIO_CFGG_GPIO49INCFG_S               4
+#define AM_REG_GPIO_CFGG_GPIO49INCFG_M               0x00000010
+#define AM_REG_GPIO_CFGG_GPIO49INCFG(n)              (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_CFGG_GPIO49INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGG_GPIO49INCFG_RDZERO          0x00000010
+
+// GPIO48 interrupt direction.
+#define AM_REG_GPIO_CFGG_GPIO48INTD_S                3
+#define AM_REG_GPIO_CFGG_GPIO48INTD_M                0x00000008
+#define AM_REG_GPIO_CFGG_GPIO48INTD(n)               (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_GPIO_CFGG_GPIO48INTD_INTLH            0x00000000
+#define AM_REG_GPIO_CFGG_GPIO48INTD_INTHL            0x00000008
+
+// GPIO48 output configuration.
+#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_S              1
+#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_M              0x00000006
+#define AM_REG_GPIO_CFGG_GPIO48OUTCFG(n)             (((uint32_t)(n) << 1) & 0x00000006)
+#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_DIS            0x00000000
+#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_PUSHPULL       0x00000002
+#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_OD             0x00000004
+#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_TS             0x00000006
+
+// GPIO48 input enable.
+#define AM_REG_GPIO_CFGG_GPIO48INCFG_S               0
+#define AM_REG_GPIO_CFGG_GPIO48INCFG_M               0x00000001
+#define AM_REG_GPIO_CFGG_GPIO48INCFG(n)              (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_GPIO_CFGG_GPIO48INCFG_READ            0x00000000
+#define AM_REG_GPIO_CFGG_GPIO48INCFG_RDZERO          0x00000001
+
+//*****************************************************************************
+//
+// GPIO_RDA - GPIO Input Register A
+//
+//*****************************************************************************
+// GPIO31-0 read data.
+#define AM_REG_GPIO_RDA_RDA_S                        0
+#define AM_REG_GPIO_RDA_RDA_M                        0xFFFFFFFF
+#define AM_REG_GPIO_RDA_RDA(n)                       (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// GPIO_RDB - GPIO Input Register B
+//
+//*****************************************************************************
+// GPIO49-32 read data.
+#define AM_REG_GPIO_RDB_RDB_S                        0
+#define AM_REG_GPIO_RDB_RDB_M                        0x0003FFFF
+#define AM_REG_GPIO_RDB_RDB(n)                       (((uint32_t)(n) << 0) & 0x0003FFFF)
+
+//*****************************************************************************
+//
+// GPIO_WTA - GPIO Output Register A
+//
+//*****************************************************************************
+// GPIO31-0 write data.
+#define AM_REG_GPIO_WTA_WTA_S                        0
+#define AM_REG_GPIO_WTA_WTA_M                        0xFFFFFFFF
+#define AM_REG_GPIO_WTA_WTA(n)                       (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// GPIO_WTB - GPIO Output Register B
+//
+//*****************************************************************************
+// GPIO49-32 write data.
+#define AM_REG_GPIO_WTB_WTB_S                        0
+#define AM_REG_GPIO_WTB_WTB_M                        0x0003FFFF
+#define AM_REG_GPIO_WTB_WTB(n)                       (((uint32_t)(n) << 0) & 0x0003FFFF)
+
+//*****************************************************************************
+//
+// GPIO_WTSA - GPIO Output Register A Set
+//
+//*****************************************************************************
+// Set the GPIO31-0 write data.
+#define AM_REG_GPIO_WTSA_WTSA_S                      0
+#define AM_REG_GPIO_WTSA_WTSA_M                      0xFFFFFFFF
+#define AM_REG_GPIO_WTSA_WTSA(n)                     (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// GPIO_WTSB - GPIO Output Register B Set
+//
+//*****************************************************************************
+// Set the GPIO49-32 write data.
+#define AM_REG_GPIO_WTSB_WTSB_S                      0
+#define AM_REG_GPIO_WTSB_WTSB_M                      0x0003FFFF
+#define AM_REG_GPIO_WTSB_WTSB(n)                     (((uint32_t)(n) << 0) & 0x0003FFFF)
+
+//*****************************************************************************
+//
+// GPIO_WTCA - GPIO Output Register A Clear
+//
+//*****************************************************************************
+// Clear the GPIO31-0 write data.
+#define AM_REG_GPIO_WTCA_WTCA_S                      0
+#define AM_REG_GPIO_WTCA_WTCA_M                      0xFFFFFFFF
+#define AM_REG_GPIO_WTCA_WTCA(n)                     (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// GPIO_WTCB - GPIO Output Register B Clear
+//
+//*****************************************************************************
+// Clear the GPIO49-32 write data.
+#define AM_REG_GPIO_WTCB_WTCB_S                      0
+#define AM_REG_GPIO_WTCB_WTCB_M                      0x0003FFFF
+#define AM_REG_GPIO_WTCB_WTCB(n)                     (((uint32_t)(n) << 0) & 0x0003FFFF)
+
+//*****************************************************************************
+//
+// GPIO_ENA - GPIO Enable Register A
+//
+//*****************************************************************************
+// GPIO31-0 output enables
+#define AM_REG_GPIO_ENA_ENA_S                        0
+#define AM_REG_GPIO_ENA_ENA_M                        0xFFFFFFFF
+#define AM_REG_GPIO_ENA_ENA(n)                       (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// GPIO_ENB - GPIO Enable Register B
+//
+//*****************************************************************************
+// GPIO49-32 output enables
+#define AM_REG_GPIO_ENB_ENB_S                        0
+#define AM_REG_GPIO_ENB_ENB_M                        0x0003FFFF
+#define AM_REG_GPIO_ENB_ENB(n)                       (((uint32_t)(n) << 0) & 0x0003FFFF)
+
+//*****************************************************************************
+//
+// GPIO_ENSA - GPIO Enable Register A Set
+//
+//*****************************************************************************
+// Set the GPIO31-0 output enables
+#define AM_REG_GPIO_ENSA_ENSA_S                      0
+#define AM_REG_GPIO_ENSA_ENSA_M                      0xFFFFFFFF
+#define AM_REG_GPIO_ENSA_ENSA(n)                     (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// GPIO_ENSB - GPIO Enable Register B Set
+//
+//*****************************************************************************
+// Set the GPIO49-32 output enables
+#define AM_REG_GPIO_ENSB_ENSB_S                      0
+#define AM_REG_GPIO_ENSB_ENSB_M                      0x0003FFFF
+#define AM_REG_GPIO_ENSB_ENSB(n)                     (((uint32_t)(n) << 0) & 0x0003FFFF)
+
+//*****************************************************************************
+//
+// GPIO_ENCA - GPIO Enable Register A Clear
+//
+//*****************************************************************************
+// Clear the GPIO31-0 output enables
+#define AM_REG_GPIO_ENCA_ENCA_S                      0
+#define AM_REG_GPIO_ENCA_ENCA_M                      0xFFFFFFFF
+#define AM_REG_GPIO_ENCA_ENCA(n)                     (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// GPIO_ENCB - GPIO Enable Register B Clear
+//
+//*****************************************************************************
+// Clear the GPIO49-32 output enables
+#define AM_REG_GPIO_ENCB_ENCB_S                      0
+#define AM_REG_GPIO_ENCB_ENCB_M                      0x0003FFFF
+#define AM_REG_GPIO_ENCB_ENCB(n)                     (((uint32_t)(n) << 0) & 0x0003FFFF)
+
+//*****************************************************************************
+//
+// GPIO_STMRCAP - STIMER Capture Control
+//
+//*****************************************************************************
+// STIMER Capture 3 Polarity.
+#define AM_REG_GPIO_STMRCAP_STPOL3_S                 30
+#define AM_REG_GPIO_STMRCAP_STPOL3_M                 0x40000000
+#define AM_REG_GPIO_STMRCAP_STPOL3(n)                (((uint32_t)(n) << 30) & 0x40000000)
+#define AM_REG_GPIO_STMRCAP_STPOL3_CAPLH             0x00000000
+#define AM_REG_GPIO_STMRCAP_STPOL3_CAPHL             0x40000000
+
+// STIMER Capture 3 Select.
+#define AM_REG_GPIO_STMRCAP_STSEL3_S                 24
+#define AM_REG_GPIO_STMRCAP_STSEL3_M                 0x3F000000
+#define AM_REG_GPIO_STMRCAP_STSEL3(n)                (((uint32_t)(n) << 24) & 0x3F000000)
+
+// STIMER Capture 2 Polarity.
+#define AM_REG_GPIO_STMRCAP_STPOL2_S                 22
+#define AM_REG_GPIO_STMRCAP_STPOL2_M                 0x00400000
+#define AM_REG_GPIO_STMRCAP_STPOL2(n)                (((uint32_t)(n) << 22) & 0x00400000)
+#define AM_REG_GPIO_STMRCAP_STPOL2_CAPLH             0x00000000
+#define AM_REG_GPIO_STMRCAP_STPOL2_CAPHL             0x00400000
+
+// STIMER Capture 2 Select.
+#define AM_REG_GPIO_STMRCAP_STSEL2_S                 16
+#define AM_REG_GPIO_STMRCAP_STSEL2_M                 0x003F0000
+#define AM_REG_GPIO_STMRCAP_STSEL2(n)                (((uint32_t)(n) << 16) & 0x003F0000)
+
+// STIMER Capture 1 Polarity.
+#define AM_REG_GPIO_STMRCAP_STPOL1_S                 14
+#define AM_REG_GPIO_STMRCAP_STPOL1_M                 0x00004000
+#define AM_REG_GPIO_STMRCAP_STPOL1(n)                (((uint32_t)(n) << 14) & 0x00004000)
+#define AM_REG_GPIO_STMRCAP_STPOL1_CAPLH             0x00000000
+#define AM_REG_GPIO_STMRCAP_STPOL1_CAPHL             0x00004000
+
+// STIMER Capture 1 Select.
+#define AM_REG_GPIO_STMRCAP_STSEL1_S                 8
+#define AM_REG_GPIO_STMRCAP_STSEL1_M                 0x00003F00
+#define AM_REG_GPIO_STMRCAP_STSEL1(n)                (((uint32_t)(n) << 8) & 0x00003F00)
+
+// STIMER Capture 0 Polarity.
+#define AM_REG_GPIO_STMRCAP_STPOL0_S                 6
+#define AM_REG_GPIO_STMRCAP_STPOL0_M                 0x00000040
+#define AM_REG_GPIO_STMRCAP_STPOL0(n)                (((uint32_t)(n) << 6) & 0x00000040)
+#define AM_REG_GPIO_STMRCAP_STPOL0_CAPLH             0x00000000
+#define AM_REG_GPIO_STMRCAP_STPOL0_CAPHL             0x00000040
+
+// STIMER Capture 0 Select.
+#define AM_REG_GPIO_STMRCAP_STSEL0_S                 0
+#define AM_REG_GPIO_STMRCAP_STSEL0_M                 0x0000003F
+#define AM_REG_GPIO_STMRCAP_STSEL0(n)                (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// GPIO_IOM0IRQ - IOM0 Flow Control IRQ Select
+//
+//*****************************************************************************
+// IOMSTR0 IRQ pad select.
+#define AM_REG_GPIO_IOM0IRQ_IOM0IRQ_S                0
+#define AM_REG_GPIO_IOM0IRQ_IOM0IRQ_M                0x0000003F
+#define AM_REG_GPIO_IOM0IRQ_IOM0IRQ(n)               (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// GPIO_IOM1IRQ - IOM1 Flow Control IRQ Select
+//
+//*****************************************************************************
+// IOMSTR1 IRQ pad select.
+#define AM_REG_GPIO_IOM1IRQ_IOM1IRQ_S                0
+#define AM_REG_GPIO_IOM1IRQ_IOM1IRQ_M                0x0000003F
+#define AM_REG_GPIO_IOM1IRQ_IOM1IRQ(n)               (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// GPIO_IOM2IRQ - IOM2 Flow Control IRQ Select
+//
+//*****************************************************************************
+// IOMSTR2 IRQ pad select.
+#define AM_REG_GPIO_IOM2IRQ_IOM2IRQ_S                0
+#define AM_REG_GPIO_IOM2IRQ_IOM2IRQ_M                0x0000003F
+#define AM_REG_GPIO_IOM2IRQ_IOM2IRQ(n)               (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// GPIO_IOM3IRQ - IOM3 Flow Control IRQ Select
+//
+//*****************************************************************************
+// IOMSTR3 IRQ pad select.
+#define AM_REG_GPIO_IOM3IRQ_IOM3IRQ_S                0
+#define AM_REG_GPIO_IOM3IRQ_IOM3IRQ_M                0x0000003F
+#define AM_REG_GPIO_IOM3IRQ_IOM3IRQ(n)               (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// GPIO_IOM4IRQ - IOM4 Flow Control IRQ Select
+//
+//*****************************************************************************
+// IOMSTR4 IRQ pad select.
+#define AM_REG_GPIO_IOM4IRQ_IOM4IRQ_S                0
+#define AM_REG_GPIO_IOM4IRQ_IOM4IRQ_M                0x0000003F
+#define AM_REG_GPIO_IOM4IRQ_IOM4IRQ(n)               (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// GPIO_IOM5IRQ - IOM5 Flow Control IRQ Select
+//
+//*****************************************************************************
+// IOMSTR5 IRQ pad select.
+#define AM_REG_GPIO_IOM5IRQ_IOM5IRQ_S                0
+#define AM_REG_GPIO_IOM5IRQ_IOM5IRQ_M                0x0000003F
+#define AM_REG_GPIO_IOM5IRQ_IOM5IRQ(n)               (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// GPIO_LOOPBACK - IOM to IOS Loopback Control
+//
+//*****************************************************************************
+// IOM to IOS loopback control.
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_S              0
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_M              0x00000007
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK(n)             (((uint32_t)(n) << 0) & 0x00000007)
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP0          0x00000000
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP1          0x00000001
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP2          0x00000002
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP3          0x00000003
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP4          0x00000004
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP5          0x00000005
+#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOPNONE       0x00000006
+
+//*****************************************************************************
+//
+// GPIO_GPIOOBS - GPIO Observation Mode Sample register
+//
+//*****************************************************************************
+// Sample of the data output on the GPIO observation port.  May have async
+// sampling issues, as the data is not synronized to the read operation.
+// Intended for debug purposes only
+#define AM_REG_GPIO_GPIOOBS_OBS_DATA_S               0
+#define AM_REG_GPIO_GPIOOBS_OBS_DATA_M               0x0000FFFF
+#define AM_REG_GPIO_GPIOOBS_OBS_DATA(n)              (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGA - Alternate Pad Configuration reg0 (Pads 3,2,1,0)
+//
+//*****************************************************************************
+// Pad 3 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGA_PAD3_SR_S             28
+#define AM_REG_GPIO_ALTPADCFGA_PAD3_SR_M             0x10000000
+#define AM_REG_GPIO_ALTPADCFGA_PAD3_SR(n)            (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGA_PAD3_SR_SR_EN         0x10000000
+
+// Pad 3 high order drive strength selection.  Used in conjunction with
+// PAD3STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGA_PAD3_DS1_S            24
+#define AM_REG_GPIO_ALTPADCFGA_PAD3_DS1_M            0x01000000
+#define AM_REG_GPIO_ALTPADCFGA_PAD3_DS1(n)           (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 2 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGA_PAD2_SR_S             20
+#define AM_REG_GPIO_ALTPADCFGA_PAD2_SR_M             0x00100000
+#define AM_REG_GPIO_ALTPADCFGA_PAD2_SR(n)            (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGA_PAD2_SR_SR_EN         0x00100000
+
+// Pad 2 high order drive strength selection.  Used in conjunction with
+// PAD2STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGA_PAD2_DS1_S            16
+#define AM_REG_GPIO_ALTPADCFGA_PAD2_DS1_M            0x00010000
+#define AM_REG_GPIO_ALTPADCFGA_PAD2_DS1(n)           (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 1 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGA_PAD1_SR_S             12
+#define AM_REG_GPIO_ALTPADCFGA_PAD1_SR_M             0x00001000
+#define AM_REG_GPIO_ALTPADCFGA_PAD1_SR(n)            (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGA_PAD1_SR_SR_EN         0x00001000
+
+// Pad 1 high order drive strength selection.  Used in conjunction with
+// PAD1STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGA_PAD1_DS1_S            8
+#define AM_REG_GPIO_ALTPADCFGA_PAD1_DS1_M            0x00000100
+#define AM_REG_GPIO_ALTPADCFGA_PAD1_DS1(n)           (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 0 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGA_PAD0_SR_S             4
+#define AM_REG_GPIO_ALTPADCFGA_PAD0_SR_M             0x00000010
+#define AM_REG_GPIO_ALTPADCFGA_PAD0_SR(n)            (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGA_PAD0_SR_SR_EN         0x00000010
+
+// Pad 0 high order drive strength selection.  Used in conjunction with
+// PAD0STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGA_PAD0_DS1_S            0
+#define AM_REG_GPIO_ALTPADCFGA_PAD0_DS1_M            0x00000001
+#define AM_REG_GPIO_ALTPADCFGA_PAD0_DS1(n)           (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGB - Alternate Pad Configuration reg1 (Pads 7,6,5,4)
+//
+//*****************************************************************************
+// Pad 7 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGB_PAD7_SR_S             28
+#define AM_REG_GPIO_ALTPADCFGB_PAD7_SR_M             0x10000000
+#define AM_REG_GPIO_ALTPADCFGB_PAD7_SR(n)            (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGB_PAD7_SR_SR_EN         0x10000000
+
+// Pad 7 high order drive strength selection.  Used in conjunction with
+// PAD7STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGB_PAD7_DS1_S            24
+#define AM_REG_GPIO_ALTPADCFGB_PAD7_DS1_M            0x01000000
+#define AM_REG_GPIO_ALTPADCFGB_PAD7_DS1(n)           (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 6 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGB_PAD6_SR_S             20
+#define AM_REG_GPIO_ALTPADCFGB_PAD6_SR_M             0x00100000
+#define AM_REG_GPIO_ALTPADCFGB_PAD6_SR(n)            (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGB_PAD6_SR_SR_EN         0x00100000
+
+// Pad 6 high order drive strength selection.  Used in conjunction with
+// PAD6STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGB_PAD6_DS1_S            16
+#define AM_REG_GPIO_ALTPADCFGB_PAD6_DS1_M            0x00010000
+#define AM_REG_GPIO_ALTPADCFGB_PAD6_DS1(n)           (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 5 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGB_PAD5_SR_S             12
+#define AM_REG_GPIO_ALTPADCFGB_PAD5_SR_M             0x00001000
+#define AM_REG_GPIO_ALTPADCFGB_PAD5_SR(n)            (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGB_PAD5_SR_SR_EN         0x00001000
+
+// Pad 5 high order drive strength selection.  Used in conjunction with
+// PAD5STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGB_PAD5_DS1_S            8
+#define AM_REG_GPIO_ALTPADCFGB_PAD5_DS1_M            0x00000100
+#define AM_REG_GPIO_ALTPADCFGB_PAD5_DS1(n)           (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 4 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGB_PAD4_SR_S             4
+#define AM_REG_GPIO_ALTPADCFGB_PAD4_SR_M             0x00000010
+#define AM_REG_GPIO_ALTPADCFGB_PAD4_SR(n)            (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGB_PAD4_SR_SR_EN         0x00000010
+
+// Pad 4 high order drive strength selection.  Used in conjunction with
+// PAD4STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGB_PAD4_DS1_S            0
+#define AM_REG_GPIO_ALTPADCFGB_PAD4_DS1_M            0x00000001
+#define AM_REG_GPIO_ALTPADCFGB_PAD4_DS1(n)           (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGC - Alternate Pad Configuration reg2 (Pads 11,10,9,8)
+//
+//*****************************************************************************
+// Pad 11 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGC_PAD11_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGC_PAD11_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGC_PAD11_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGC_PAD11_SR_SR_EN        0x10000000
+
+// Pad 11 high order drive strength selection.  Used in conjunction with
+// PAD11STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGC_PAD11_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGC_PAD11_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGC_PAD11_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 10 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGC_PAD10_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGC_PAD10_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGC_PAD10_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGC_PAD10_SR_SR_EN        0x00100000
+
+// Pad 10 high order drive strength selection.  Used in conjunction with
+// PAD10STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGC_PAD10_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGC_PAD10_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGC_PAD10_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 9 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGC_PAD9_SR_S             12
+#define AM_REG_GPIO_ALTPADCFGC_PAD9_SR_M             0x00001000
+#define AM_REG_GPIO_ALTPADCFGC_PAD9_SR(n)            (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGC_PAD9_SR_SR_EN         0x00001000
+
+// Pad 9 high order drive strength selection.  Used in conjunction with
+// PAD9STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGC_PAD9_DS1_S            8
+#define AM_REG_GPIO_ALTPADCFGC_PAD9_DS1_M            0x00000100
+#define AM_REG_GPIO_ALTPADCFGC_PAD9_DS1(n)           (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 8 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGC_PAD8_SR_S             4
+#define AM_REG_GPIO_ALTPADCFGC_PAD8_SR_M             0x00000010
+#define AM_REG_GPIO_ALTPADCFGC_PAD8_SR(n)            (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGC_PAD8_SR_SR_EN         0x00000010
+
+// Pad 8 high order drive strength selection.  Used in conjunction with
+// PAD8STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGC_PAD8_DS1_S            0
+#define AM_REG_GPIO_ALTPADCFGC_PAD8_DS1_M            0x00000001
+#define AM_REG_GPIO_ALTPADCFGC_PAD8_DS1(n)           (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGD - Alternate Pad Configuration reg3 (Pads 15,14,13,12)
+//
+//*****************************************************************************
+// Pad 15 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGD_PAD15_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGD_PAD15_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGD_PAD15_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGD_PAD15_SR_SR_EN        0x10000000
+
+// Pad 15 high order drive strength selection.  Used in conjunction with
+// PAD15STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGD_PAD15_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGD_PAD15_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGD_PAD15_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 14 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGD_PAD14_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGD_PAD14_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGD_PAD14_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGD_PAD14_SR_SR_EN        0x00100000
+
+// Pad 14 high order drive strength selection.  Used in conjunction with
+// PAD14STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGD_PAD14_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGD_PAD14_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGD_PAD14_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 13 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGD_PAD13_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGD_PAD13_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGD_PAD13_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGD_PAD13_SR_SR_EN        0x00001000
+
+// Pad 13 high order drive strength selection.  Used in conjunction with
+// PAD13STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGD_PAD13_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGD_PAD13_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGD_PAD13_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 12 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGD_PAD12_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGD_PAD12_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGD_PAD12_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGD_PAD12_SR_SR_EN        0x00000010
+
+// Pad 12 high order drive strength selection.  Used in conjunction with
+// PAD12STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGD_PAD12_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGD_PAD12_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGD_PAD12_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGE - Alternate Pad Configuration reg4 (Pads 19,18,17,16)
+//
+//*****************************************************************************
+// Pad 19 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGE_PAD19_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGE_PAD19_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGE_PAD19_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGE_PAD19_SR_SR_EN        0x10000000
+
+// Pad 19 high order drive strength selection.  Used in conjunction with
+// PAD19STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGE_PAD19_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGE_PAD19_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGE_PAD19_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 18 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGE_PAD18_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGE_PAD18_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGE_PAD18_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGE_PAD18_SR_SR_EN        0x00100000
+
+// Pad 18 high order drive strength selection.  Used in conjunction with
+// PAD18STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGE_PAD18_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGE_PAD18_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGE_PAD18_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 17 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGE_PAD17_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGE_PAD17_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGE_PAD17_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGE_PAD17_SR_SR_EN        0x00001000
+
+// Pad 17 high order drive strength selection.  Used in conjunction with
+// PAD17STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGE_PAD17_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGE_PAD17_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGE_PAD17_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 16 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGE_PAD16_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGE_PAD16_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGE_PAD16_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGE_PAD16_SR_SR_EN        0x00000010
+
+// Pad 16 high order drive strength selection.  Used in conjunction with
+// PAD16STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGE_PAD16_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGE_PAD16_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGE_PAD16_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGF - Alternate Pad Configuration reg5 (Pads 23,22,21,20)
+//
+//*****************************************************************************
+// Pad 23 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGF_PAD23_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGF_PAD23_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGF_PAD23_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGF_PAD23_SR_SR_EN        0x10000000
+
+// Pad 23 high order drive strength selection.  Used in conjunction with
+// PAD23STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGF_PAD23_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGF_PAD23_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGF_PAD23_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 22 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGF_PAD22_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGF_PAD22_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGF_PAD22_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGF_PAD22_SR_SR_EN        0x00100000
+
+// Pad 22 high order drive strength selection.  Used in conjunction with
+// PAD22STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGF_PAD22_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGF_PAD22_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGF_PAD22_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 21 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGF_PAD21_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGF_PAD21_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGF_PAD21_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGF_PAD21_SR_SR_EN        0x00001000
+
+// Pad 21 high order drive strength selection.  Used in conjunction with
+// PAD21STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGF_PAD21_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGF_PAD21_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGF_PAD21_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 20 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGF_PAD20_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGF_PAD20_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGF_PAD20_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGF_PAD20_SR_SR_EN        0x00000010
+
+// Pad 20 high order drive strength selection.  Used in conjunction with
+// PAD20STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGF_PAD20_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGF_PAD20_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGF_PAD20_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGG - Alternate Pad Configuration reg6 (Pads 27,26,25,24)
+//
+//*****************************************************************************
+// Pad 27 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGG_PAD27_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGG_PAD27_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGG_PAD27_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGG_PAD27_SR_SR_EN        0x10000000
+
+// Pad 27 high order drive strength selection.  Used in conjunction with
+// PAD27STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGG_PAD27_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGG_PAD27_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGG_PAD27_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 26 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGG_PAD26_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGG_PAD26_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGG_PAD26_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGG_PAD26_SR_SR_EN        0x00100000
+
+// Pad 26 high order drive strength selection.  Used in conjunction with
+// PAD26STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGG_PAD26_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGG_PAD26_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGG_PAD26_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 25 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGG_PAD25_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGG_PAD25_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGG_PAD25_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGG_PAD25_SR_SR_EN        0x00001000
+
+// Pad 25 high order drive strength selection.  Used in conjunction with
+// PAD25STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGG_PAD25_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGG_PAD25_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGG_PAD25_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 24 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGG_PAD24_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGG_PAD24_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGG_PAD24_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGG_PAD24_SR_SR_EN        0x00000010
+
+// Pad 24 high order drive strength selection.  Used in conjunction with
+// PAD24STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGG_PAD24_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGG_PAD24_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGG_PAD24_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGH - Alternate Pad Configuration reg7 (Pads 31,30,29,28)
+//
+//*****************************************************************************
+// Pad 31 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGH_PAD31_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGH_PAD31_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGH_PAD31_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGH_PAD31_SR_SR_EN        0x10000000
+
+// Pad 31 high order drive strength selection.  Used in conjunction with
+// PAD31STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGH_PAD31_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGH_PAD31_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGH_PAD31_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 30 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGH_PAD30_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGH_PAD30_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGH_PAD30_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGH_PAD30_SR_SR_EN        0x00100000
+
+// Pad 30 high order drive strength selection.  Used in conjunction with
+// PAD30STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGH_PAD30_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGH_PAD30_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGH_PAD30_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 29 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGH_PAD29_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGH_PAD29_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGH_PAD29_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGH_PAD29_SR_SR_EN        0x00001000
+
+// Pad 29 high order drive strength selection.  Used in conjunction with
+// PAD29STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGH_PAD29_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGH_PAD29_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGH_PAD29_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 28 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGH_PAD28_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGH_PAD28_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGH_PAD28_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGH_PAD28_SR_SR_EN        0x00000010
+
+// Pad 28 high order drive strength selection.  Used in conjunction with
+// PAD28STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGH_PAD28_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGH_PAD28_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGH_PAD28_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGI - Alternate Pad Configuration reg8 (Pads 35,34,33,32)
+//
+//*****************************************************************************
+// Pad 35 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGI_PAD35_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGI_PAD35_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGI_PAD35_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGI_PAD35_SR_SR_EN        0x10000000
+
+// Pad 35 high order drive strength selection.  Used in conjunction with
+// PAD35STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGI_PAD35_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGI_PAD35_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGI_PAD35_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 34 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGI_PAD34_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGI_PAD34_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGI_PAD34_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGI_PAD34_SR_SR_EN        0x00100000
+
+// Pad 34 high order drive strength selection.  Used in conjunction with
+// PAD34STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGI_PAD34_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGI_PAD34_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGI_PAD34_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 33 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGI_PAD33_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGI_PAD33_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGI_PAD33_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGI_PAD33_SR_SR_EN        0x00001000
+
+// Pad 33 high order drive strength selection.  Used in conjunction with
+// PAD33STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGI_PAD33_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGI_PAD33_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGI_PAD33_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 32 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGI_PAD32_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGI_PAD32_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGI_PAD32_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGI_PAD32_SR_SR_EN        0x00000010
+
+// Pad 32 high order drive strength selection.  Used in conjunction with
+// PAD32STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGI_PAD32_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGI_PAD32_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGI_PAD32_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGJ - Alternate Pad Configuration reg9 (Pads 39,38,37,36)
+//
+//*****************************************************************************
+// Pad 39 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGJ_PAD39_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGJ_PAD39_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGJ_PAD39_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGJ_PAD39_SR_SR_EN        0x10000000
+
+// Pad 39 high order drive strength selection.  Used in conjunction with
+// PAD39STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGJ_PAD39_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGJ_PAD39_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGJ_PAD39_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 38 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGJ_PAD38_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGJ_PAD38_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGJ_PAD38_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGJ_PAD38_SR_SR_EN        0x00100000
+
+// Pad 38 high order drive strength selection.  Used in conjunction with
+// PAD38STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGJ_PAD38_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGJ_PAD38_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGJ_PAD38_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 37 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGJ_PAD37_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGJ_PAD37_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGJ_PAD37_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGJ_PAD37_SR_SR_EN        0x00001000
+
+// Pad 37 high order drive strength selection.  Used in conjunction with
+// PAD37STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGJ_PAD37_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGJ_PAD37_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGJ_PAD37_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 36 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGJ_PAD36_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGJ_PAD36_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGJ_PAD36_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGJ_PAD36_SR_SR_EN        0x00000010
+
+// Pad 36 high order drive strength selection.  Used in conjunction with
+// PAD36STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGJ_PAD36_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGJ_PAD36_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGJ_PAD36_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGK - Alternate Pad Configuration reg10 (Pads 43,42,41,40)
+//
+//*****************************************************************************
+// Pad 43 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGK_PAD43_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGK_PAD43_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGK_PAD43_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGK_PAD43_SR_SR_EN        0x10000000
+
+// Pad 43 high order drive strength selection.  Used in conjunction with
+// PAD43STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGK_PAD43_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGK_PAD43_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGK_PAD43_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 42 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGK_PAD42_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGK_PAD42_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGK_PAD42_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGK_PAD42_SR_SR_EN        0x00100000
+
+// Pad 42 high order drive strength selection.  Used in conjunction with
+// PAD42STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGK_PAD42_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGK_PAD42_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGK_PAD42_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 41 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGK_PAD41_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGK_PAD41_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGK_PAD41_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGK_PAD41_SR_SR_EN        0x00001000
+
+// Pad 41 high order drive strength selection.  Used in conjunction with
+// PAD41STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGK_PAD41_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGK_PAD41_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGK_PAD41_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 40 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGK_PAD40_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGK_PAD40_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGK_PAD40_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGK_PAD40_SR_SR_EN        0x00000010
+
+// Pad 40 high order drive strength selection.  Used in conjunction with
+// PAD40STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGK_PAD40_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGK_PAD40_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGK_PAD40_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGL - Alternate Pad Configuration reg11 (Pads 47,46,45,44)
+//
+//*****************************************************************************
+// Pad 47 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGL_PAD47_SR_S            28
+#define AM_REG_GPIO_ALTPADCFGL_PAD47_SR_M            0x10000000
+#define AM_REG_GPIO_ALTPADCFGL_PAD47_SR(n)           (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_GPIO_ALTPADCFGL_PAD47_SR_SR_EN        0x10000000
+
+// Pad 47 high order drive strength selection.  Used in conjunction with
+// PAD47STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGL_PAD47_DS1_S           24
+#define AM_REG_GPIO_ALTPADCFGL_PAD47_DS1_M           0x01000000
+#define AM_REG_GPIO_ALTPADCFGL_PAD47_DS1(n)          (((uint32_t)(n) << 24) & 0x01000000)
+
+// Pad 46 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGL_PAD46_SR_S            20
+#define AM_REG_GPIO_ALTPADCFGL_PAD46_SR_M            0x00100000
+#define AM_REG_GPIO_ALTPADCFGL_PAD46_SR(n)           (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_GPIO_ALTPADCFGL_PAD46_SR_SR_EN        0x00100000
+
+// Pad 46 high order drive strength selection.  Used in conjunction with
+// PAD46STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGL_PAD46_DS1_S           16
+#define AM_REG_GPIO_ALTPADCFGL_PAD46_DS1_M           0x00010000
+#define AM_REG_GPIO_ALTPADCFGL_PAD46_DS1(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Pad 45 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGL_PAD45_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGL_PAD45_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGL_PAD45_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGL_PAD45_SR_SR_EN        0x00001000
+
+// Pad 45 high order drive strength selection.  Used in conjunction with
+// PAD45STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGL_PAD45_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGL_PAD45_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGL_PAD45_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 44 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGL_PAD44_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGL_PAD44_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGL_PAD44_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGL_PAD44_SR_SR_EN        0x00000010
+
+// Pad 44 high order drive strength selection.  Used in conjunction with
+// PAD44STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGL_PAD44_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGL_PAD44_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGL_PAD44_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// GPIO_ALTPADCFGM - Alternate Pad Configuration reg12 (Pads 49,48)
+//
+//*****************************************************************************
+// Pad 49 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGM_PAD49_SR_S            12
+#define AM_REG_GPIO_ALTPADCFGM_PAD49_SR_M            0x00001000
+#define AM_REG_GPIO_ALTPADCFGM_PAD49_SR(n)           (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_GPIO_ALTPADCFGM_PAD49_SR_SR_EN        0x00001000
+
+// Pad 49 high order drive strength selection.  Used in conjunction with
+// PAD49STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGM_PAD49_DS1_S           8
+#define AM_REG_GPIO_ALTPADCFGM_PAD49_DS1_M           0x00000100
+#define AM_REG_GPIO_ALTPADCFGM_PAD49_DS1(n)          (((uint32_t)(n) << 8) & 0x00000100)
+
+// Pad 48 slew rate selection.
+#define AM_REG_GPIO_ALTPADCFGM_PAD48_SR_S            4
+#define AM_REG_GPIO_ALTPADCFGM_PAD48_SR_M            0x00000010
+#define AM_REG_GPIO_ALTPADCFGM_PAD48_SR(n)           (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_GPIO_ALTPADCFGM_PAD48_SR_SR_EN        0x00000010
+
+// Pad 48 high order drive strength selection.  Used in conjunction with
+// PAD48STRNG field to set the pad drive strength.
+#define AM_REG_GPIO_ALTPADCFGM_PAD48_DS1_S           0
+#define AM_REG_GPIO_ALTPADCFGM_PAD48_DS1_M           0x00000001
+#define AM_REG_GPIO_ALTPADCFGM_PAD48_DS1(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+#endif // AM_REG_GPIO_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h b/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h
new file mode 100644
index 0000000000..c04cd2c04a
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h
@@ -0,0 +1,587 @@
+//*****************************************************************************
+//
+//  am_reg_iomstr.h
+//! @file
+//!
+//! @brief Register macros for the IOMSTR module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_IOMSTR_H
+#define AM_REG_IOMSTR_H
+
+//*****************************************************************************
+//
+// Instance finder. (6 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_IOMSTR_NUM_MODULES                    6
+#define AM_REG_IOMSTRn(n) \
+    (REG_IOMSTR_BASEADDR + 0x00001000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_IOMSTR_FIFO_O                         0x00000000
+#define AM_REG_IOMSTR_FIFOPTR_O                      0x00000100
+#define AM_REG_IOMSTR_TLNGTH_O                       0x00000104
+#define AM_REG_IOMSTR_FIFOTHR_O                      0x00000108
+#define AM_REG_IOMSTR_CLKCFG_O                       0x0000010C
+#define AM_REG_IOMSTR_CMD_O                          0x00000110
+#define AM_REG_IOMSTR_CMDRPT_O                       0x00000114
+#define AM_REG_IOMSTR_STATUS_O                       0x00000118
+#define AM_REG_IOMSTR_CFG_O                          0x0000011C
+#define AM_REG_IOMSTR_INTEN_O                        0x00000200
+#define AM_REG_IOMSTR_INTSTAT_O                      0x00000204
+#define AM_REG_IOMSTR_INTCLR_O                       0x00000208
+#define AM_REG_IOMSTR_INTSET_O                       0x0000020C
+
+//*****************************************************************************
+//
+// IOMSTR_INTEN - IO Master Interrupts: Enable
+//
+//*****************************************************************************
+// This is the arbitration loss interrupt. This error occurs if another master
+// collides with an IO Master transfer. Generally, the IOM started an operation
+// but found SDA already low.
+#define AM_REG_IOMSTR_INTEN_ARB_S                    10
+#define AM_REG_IOMSTR_INTEN_ARB_M                    0x00000400
+#define AM_REG_IOMSTR_INTEN_ARB(n)                   (((uint32_t)(n) << 10) & 0x00000400)
+
+// This is the STOP command interrupt. A STOP bit was detected by the IOM.
+#define AM_REG_IOMSTR_INTEN_STOP_S                   9
+#define AM_REG_IOMSTR_INTEN_STOP_M                   0x00000200
+#define AM_REG_IOMSTR_INTEN_STOP(n)                  (((uint32_t)(n) << 9) & 0x00000200)
+
+// This is the START command interrupt. A START from another master was
+// detected. Software must wait for a STOP before proceeding.
+#define AM_REG_IOMSTR_INTEN_START_S                  8
+#define AM_REG_IOMSTR_INTEN_START_M                  0x00000100
+#define AM_REG_IOMSTR_INTEN_START(n)                 (((uint32_t)(n) << 8) & 0x00000100)
+
+// This is the illegal command interrupt. Software attempted to issue a CMD
+// while another CMD was already in progress. Or an attempt was made to issue a
+// non-zero-length write CMD with an empty FIFO.
+#define AM_REG_IOMSTR_INTEN_ICMD_S                   7
+#define AM_REG_IOMSTR_INTEN_ICMD_M                   0x00000080
+#define AM_REG_IOMSTR_INTEN_ICMD(n)                  (((uint32_t)(n) << 7) & 0x00000080)
+
+// This is the illegal FIFO access interrupt. An attempt was made to read the
+// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read
+// CMD.
+#define AM_REG_IOMSTR_INTEN_IACC_S                   6
+#define AM_REG_IOMSTR_INTEN_IACC_M                   0x00000040
+#define AM_REG_IOMSTR_INTEN_IACC(n)                  (((uint32_t)(n) << 6) & 0x00000040)
+
+// This is the WTLEN interrupt.
+#define AM_REG_IOMSTR_INTEN_WTLEN_S                  5
+#define AM_REG_IOMSTR_INTEN_WTLEN_M                  0x00000020
+#define AM_REG_IOMSTR_INTEN_WTLEN(n)                 (((uint32_t)(n) << 5) & 0x00000020)
+
+// This is the I2C NAK interrupt. The expected ACK from the slave was not
+// received by the IOM.
+#define AM_REG_IOMSTR_INTEN_NAK_S                    4
+#define AM_REG_IOMSTR_INTEN_NAK_M                    0x00000010
+#define AM_REG_IOMSTR_INTEN_NAK(n)                   (((uint32_t)(n) << 4) & 0x00000010)
+
+// This is the Write FIFO Overflow interrupt. An attempt was made to write the
+// FIFO while it was full (i.e. while FIFOSIZ > 124).
+#define AM_REG_IOMSTR_INTEN_FOVFL_S                  3
+#define AM_REG_IOMSTR_INTEN_FOVFL_M                  0x00000008
+#define AM_REG_IOMSTR_INTEN_FOVFL(n)                 (((uint32_t)(n) << 3) & 0x00000008)
+
+// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO
+// when empty (i.e. while FIFOSIZ less than 4).
+#define AM_REG_IOMSTR_INTEN_FUNDFL_S                 2
+#define AM_REG_IOMSTR_INTEN_FUNDFL_M                 0x00000004
+#define AM_REG_IOMSTR_INTEN_FUNDFL(n)                (((uint32_t)(n) << 2) & 0x00000004)
+
+// This is the FIFO Threshold interrupt.
+#define AM_REG_IOMSTR_INTEN_THR_S                    1
+#define AM_REG_IOMSTR_INTEN_THR_M                    0x00000002
+#define AM_REG_IOMSTR_INTEN_THR(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+
+// This is the Command Complete interrupt.
+#define AM_REG_IOMSTR_INTEN_CMDCMP_S                 0
+#define AM_REG_IOMSTR_INTEN_CMDCMP_M                 0x00000001
+#define AM_REG_IOMSTR_INTEN_CMDCMP(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOMSTR_INTSTAT - IO Master Interrupts: Status
+//
+//*****************************************************************************
+// This is the arbitration loss interrupt. This error occurs if another master
+// collides with an IO Master transfer. Generally, the IOM started an operation
+// but found SDA already low.
+#define AM_REG_IOMSTR_INTSTAT_ARB_S                  10
+#define AM_REG_IOMSTR_INTSTAT_ARB_M                  0x00000400
+#define AM_REG_IOMSTR_INTSTAT_ARB(n)                 (((uint32_t)(n) << 10) & 0x00000400)
+
+// This is the STOP command interrupt. A STOP bit was detected by the IOM.
+#define AM_REG_IOMSTR_INTSTAT_STOP_S                 9
+#define AM_REG_IOMSTR_INTSTAT_STOP_M                 0x00000200
+#define AM_REG_IOMSTR_INTSTAT_STOP(n)                (((uint32_t)(n) << 9) & 0x00000200)
+
+// This is the START command interrupt. A START from another master was
+// detected. Software must wait for a STOP before proceeding.
+#define AM_REG_IOMSTR_INTSTAT_START_S                8
+#define AM_REG_IOMSTR_INTSTAT_START_M                0x00000100
+#define AM_REG_IOMSTR_INTSTAT_START(n)               (((uint32_t)(n) << 8) & 0x00000100)
+
+// This is the illegal command interrupt. Software attempted to issue a CMD
+// while another CMD was already in progress. Or an attempt was made to issue a
+// non-zero-length write CMD with an empty FIFO.
+#define AM_REG_IOMSTR_INTSTAT_ICMD_S                 7
+#define AM_REG_IOMSTR_INTSTAT_ICMD_M                 0x00000080
+#define AM_REG_IOMSTR_INTSTAT_ICMD(n)                (((uint32_t)(n) << 7) & 0x00000080)
+
+// This is the illegal FIFO access interrupt. An attempt was made to read the
+// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read
+// CMD.
+#define AM_REG_IOMSTR_INTSTAT_IACC_S                 6
+#define AM_REG_IOMSTR_INTSTAT_IACC_M                 0x00000040
+#define AM_REG_IOMSTR_INTSTAT_IACC(n)                (((uint32_t)(n) << 6) & 0x00000040)
+
+// This is the WTLEN interrupt.
+#define AM_REG_IOMSTR_INTSTAT_WTLEN_S                5
+#define AM_REG_IOMSTR_INTSTAT_WTLEN_M                0x00000020
+#define AM_REG_IOMSTR_INTSTAT_WTLEN(n)               (((uint32_t)(n) << 5) & 0x00000020)
+
+// This is the I2C NAK interrupt. The expected ACK from the slave was not
+// received by the IOM.
+#define AM_REG_IOMSTR_INTSTAT_NAK_S                  4
+#define AM_REG_IOMSTR_INTSTAT_NAK_M                  0x00000010
+#define AM_REG_IOMSTR_INTSTAT_NAK(n)                 (((uint32_t)(n) << 4) & 0x00000010)
+
+// This is the Write FIFO Overflow interrupt. An attempt was made to write the
+// FIFO while it was full (i.e. while FIFOSIZ > 124).
+#define AM_REG_IOMSTR_INTSTAT_FOVFL_S                3
+#define AM_REG_IOMSTR_INTSTAT_FOVFL_M                0x00000008
+#define AM_REG_IOMSTR_INTSTAT_FOVFL(n)               (((uint32_t)(n) << 3) & 0x00000008)
+
+// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO
+// when empty (i.e. while FIFOSIZ less than 4).
+#define AM_REG_IOMSTR_INTSTAT_FUNDFL_S               2
+#define AM_REG_IOMSTR_INTSTAT_FUNDFL_M               0x00000004
+#define AM_REG_IOMSTR_INTSTAT_FUNDFL(n)              (((uint32_t)(n) << 2) & 0x00000004)
+
+// This is the FIFO Threshold interrupt.
+#define AM_REG_IOMSTR_INTSTAT_THR_S                  1
+#define AM_REG_IOMSTR_INTSTAT_THR_M                  0x00000002
+#define AM_REG_IOMSTR_INTSTAT_THR(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// This is the Command Complete interrupt.
+#define AM_REG_IOMSTR_INTSTAT_CMDCMP_S               0
+#define AM_REG_IOMSTR_INTSTAT_CMDCMP_M               0x00000001
+#define AM_REG_IOMSTR_INTSTAT_CMDCMP(n)              (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOMSTR_INTCLR - IO Master Interrupts: Clear
+//
+//*****************************************************************************
+// This is the arbitration loss interrupt. This error occurs if another master
+// collides with an IO Master transfer. Generally, the IOM started an operation
+// but found SDA already low.
+#define AM_REG_IOMSTR_INTCLR_ARB_S                   10
+#define AM_REG_IOMSTR_INTCLR_ARB_M                   0x00000400
+#define AM_REG_IOMSTR_INTCLR_ARB(n)                  (((uint32_t)(n) << 10) & 0x00000400)
+
+// This is the STOP command interrupt. A STOP bit was detected by the IOM.
+#define AM_REG_IOMSTR_INTCLR_STOP_S                  9
+#define AM_REG_IOMSTR_INTCLR_STOP_M                  0x00000200
+#define AM_REG_IOMSTR_INTCLR_STOP(n)                 (((uint32_t)(n) << 9) & 0x00000200)
+
+// This is the START command interrupt. A START from another master was
+// detected. Software must wait for a STOP before proceeding.
+#define AM_REG_IOMSTR_INTCLR_START_S                 8
+#define AM_REG_IOMSTR_INTCLR_START_M                 0x00000100
+#define AM_REG_IOMSTR_INTCLR_START(n)                (((uint32_t)(n) << 8) & 0x00000100)
+
+// This is the illegal command interrupt. Software attempted to issue a CMD
+// while another CMD was already in progress. Or an attempt was made to issue a
+// non-zero-length write CMD with an empty FIFO.
+#define AM_REG_IOMSTR_INTCLR_ICMD_S                  7
+#define AM_REG_IOMSTR_INTCLR_ICMD_M                  0x00000080
+#define AM_REG_IOMSTR_INTCLR_ICMD(n)                 (((uint32_t)(n) << 7) & 0x00000080)
+
+// This is the illegal FIFO access interrupt. An attempt was made to read the
+// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read
+// CMD.
+#define AM_REG_IOMSTR_INTCLR_IACC_S                  6
+#define AM_REG_IOMSTR_INTCLR_IACC_M                  0x00000040
+#define AM_REG_IOMSTR_INTCLR_IACC(n)                 (((uint32_t)(n) << 6) & 0x00000040)
+
+// This is the WTLEN interrupt.
+#define AM_REG_IOMSTR_INTCLR_WTLEN_S                 5
+#define AM_REG_IOMSTR_INTCLR_WTLEN_M                 0x00000020
+#define AM_REG_IOMSTR_INTCLR_WTLEN(n)                (((uint32_t)(n) << 5) & 0x00000020)
+
+// This is the I2C NAK interrupt. The expected ACK from the slave was not
+// received by the IOM.
+#define AM_REG_IOMSTR_INTCLR_NAK_S                   4
+#define AM_REG_IOMSTR_INTCLR_NAK_M                   0x00000010
+#define AM_REG_IOMSTR_INTCLR_NAK(n)                  (((uint32_t)(n) << 4) & 0x00000010)
+
+// This is the Write FIFO Overflow interrupt. An attempt was made to write the
+// FIFO while it was full (i.e. while FIFOSIZ > 124).
+#define AM_REG_IOMSTR_INTCLR_FOVFL_S                 3
+#define AM_REG_IOMSTR_INTCLR_FOVFL_M                 0x00000008
+#define AM_REG_IOMSTR_INTCLR_FOVFL(n)                (((uint32_t)(n) << 3) & 0x00000008)
+
+// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO
+// when empty (i.e. while FIFOSIZ less than 4).
+#define AM_REG_IOMSTR_INTCLR_FUNDFL_S                2
+#define AM_REG_IOMSTR_INTCLR_FUNDFL_M                0x00000004
+#define AM_REG_IOMSTR_INTCLR_FUNDFL(n)               (((uint32_t)(n) << 2) & 0x00000004)
+
+// This is the FIFO Threshold interrupt.
+#define AM_REG_IOMSTR_INTCLR_THR_S                   1
+#define AM_REG_IOMSTR_INTCLR_THR_M                   0x00000002
+#define AM_REG_IOMSTR_INTCLR_THR(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+
+// This is the Command Complete interrupt.
+#define AM_REG_IOMSTR_INTCLR_CMDCMP_S                0
+#define AM_REG_IOMSTR_INTCLR_CMDCMP_M                0x00000001
+#define AM_REG_IOMSTR_INTCLR_CMDCMP(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOMSTR_INTSET - IO Master Interrupts: Set
+//
+//*****************************************************************************
+// This is the arbitration loss interrupt. This error occurs if another master
+// collides with an IO Master transfer. Generally, the IOM started an operation
+// but found SDA already low.
+#define AM_REG_IOMSTR_INTSET_ARB_S                   10
+#define AM_REG_IOMSTR_INTSET_ARB_M                   0x00000400
+#define AM_REG_IOMSTR_INTSET_ARB(n)                  (((uint32_t)(n) << 10) & 0x00000400)
+
+// This is the STOP command interrupt. A STOP bit was detected by the IOM.
+#define AM_REG_IOMSTR_INTSET_STOP_S                  9
+#define AM_REG_IOMSTR_INTSET_STOP_M                  0x00000200
+#define AM_REG_IOMSTR_INTSET_STOP(n)                 (((uint32_t)(n) << 9) & 0x00000200)
+
+// This is the START command interrupt. A START from another master was
+// detected. Software must wait for a STOP before proceeding.
+#define AM_REG_IOMSTR_INTSET_START_S                 8
+#define AM_REG_IOMSTR_INTSET_START_M                 0x00000100
+#define AM_REG_IOMSTR_INTSET_START(n)                (((uint32_t)(n) << 8) & 0x00000100)
+
+// This is the illegal command interrupt. Software attempted to issue a CMD
+// while another CMD was already in progress. Or an attempt was made to issue a
+// non-zero-length write CMD with an empty FIFO.
+#define AM_REG_IOMSTR_INTSET_ICMD_S                  7
+#define AM_REG_IOMSTR_INTSET_ICMD_M                  0x00000080
+#define AM_REG_IOMSTR_INTSET_ICMD(n)                 (((uint32_t)(n) << 7) & 0x00000080)
+
+// This is the illegal FIFO access interrupt. An attempt was made to read the
+// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read
+// CMD.
+#define AM_REG_IOMSTR_INTSET_IACC_S                  6
+#define AM_REG_IOMSTR_INTSET_IACC_M                  0x00000040
+#define AM_REG_IOMSTR_INTSET_IACC(n)                 (((uint32_t)(n) << 6) & 0x00000040)
+
+// This is the WTLEN interrupt.
+#define AM_REG_IOMSTR_INTSET_WTLEN_S                 5
+#define AM_REG_IOMSTR_INTSET_WTLEN_M                 0x00000020
+#define AM_REG_IOMSTR_INTSET_WTLEN(n)                (((uint32_t)(n) << 5) & 0x00000020)
+
+// This is the I2C NAK interrupt. The expected ACK from the slave was not
+// received by the IOM.
+#define AM_REG_IOMSTR_INTSET_NAK_S                   4
+#define AM_REG_IOMSTR_INTSET_NAK_M                   0x00000010
+#define AM_REG_IOMSTR_INTSET_NAK(n)                  (((uint32_t)(n) << 4) & 0x00000010)
+
+// This is the Write FIFO Overflow interrupt. An attempt was made to write the
+// FIFO while it was full (i.e. while FIFOSIZ > 124).
+#define AM_REG_IOMSTR_INTSET_FOVFL_S                 3
+#define AM_REG_IOMSTR_INTSET_FOVFL_M                 0x00000008
+#define AM_REG_IOMSTR_INTSET_FOVFL(n)                (((uint32_t)(n) << 3) & 0x00000008)
+
+// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO
+// when empty (i.e. while FIFOSIZ less than 4).
+#define AM_REG_IOMSTR_INTSET_FUNDFL_S                2
+#define AM_REG_IOMSTR_INTSET_FUNDFL_M                0x00000004
+#define AM_REG_IOMSTR_INTSET_FUNDFL(n)               (((uint32_t)(n) << 2) & 0x00000004)
+
+// This is the FIFO Threshold interrupt.
+#define AM_REG_IOMSTR_INTSET_THR_S                   1
+#define AM_REG_IOMSTR_INTSET_THR_M                   0x00000002
+#define AM_REG_IOMSTR_INTSET_THR(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+
+// This is the Command Complete interrupt.
+#define AM_REG_IOMSTR_INTSET_CMDCMP_S                0
+#define AM_REG_IOMSTR_INTSET_CMDCMP_M                0x00000001
+#define AM_REG_IOMSTR_INTSET_CMDCMP(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOMSTR_FIFO - FIFO Access Port
+//
+//*****************************************************************************
+// FIFO access port.
+#define AM_REG_IOMSTR_FIFO_FIFO_S                    0
+#define AM_REG_IOMSTR_FIFO_FIFO_M                    0xFFFFFFFF
+#define AM_REG_IOMSTR_FIFO_FIFO(n)                   (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// IOMSTR_FIFOPTR - Current FIFO Pointers
+//
+//*****************************************************************************
+// The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or
+// 64-FIFOSIZ if FULLDUP = 1)).
+#define AM_REG_IOMSTR_FIFOPTR_FIFOREM_S              16
+#define AM_REG_IOMSTR_FIFOPTR_FIFOREM_M              0x00FF0000
+#define AM_REG_IOMSTR_FIFOPTR_FIFOREM(n)             (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// The number of bytes currently in the FIFO.
+#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ_S              0
+#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ_M              0x000000FF
+#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ(n)             (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// IOMSTR_TLNGTH - Transfer Length
+//
+//*****************************************************************************
+// Remaining transfer length.
+#define AM_REG_IOMSTR_TLNGTH_TLNGTH_S                0
+#define AM_REG_IOMSTR_TLNGTH_TLNGTH_M                0x00000FFF
+#define AM_REG_IOMSTR_TLNGTH_TLNGTH(n)               (((uint32_t)(n) << 0) & 0x00000FFF)
+
+//*****************************************************************************
+//
+// IOMSTR_FIFOTHR - FIFO Threshold Configuration
+//
+//*****************************************************************************
+// FIFO write threshold.
+#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR_S             8
+#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR_M             0x00007F00
+#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(n)            (((uint32_t)(n) << 8) & 0x00007F00)
+
+// FIFO read threshold.
+#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR_S             0
+#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR_M             0x0000007F
+#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR(n)            (((uint32_t)(n) << 0) & 0x0000007F)
+
+//*****************************************************************************
+//
+// IOMSTR_CLKCFG - I/O Clock Configuration
+//
+//*****************************************************************************
+// Clock total count minus 1.
+#define AM_REG_IOMSTR_CLKCFG_TOTPER_S                24
+#define AM_REG_IOMSTR_CLKCFG_TOTPER_M                0xFF000000
+#define AM_REG_IOMSTR_CLKCFG_TOTPER(n)               (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Clock low count minus 1.
+#define AM_REG_IOMSTR_CLKCFG_LOWPER_S                16
+#define AM_REG_IOMSTR_CLKCFG_LOWPER_M                0x00FF0000
+#define AM_REG_IOMSTR_CLKCFG_LOWPER(n)               (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Enable clock division by TOTPER.
+#define AM_REG_IOMSTR_CLKCFG_DIVEN_S                 12
+#define AM_REG_IOMSTR_CLKCFG_DIVEN_M                 0x00001000
+#define AM_REG_IOMSTR_CLKCFG_DIVEN(n)                (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_IOMSTR_CLKCFG_DIVEN_DIS               0x00000000
+#define AM_REG_IOMSTR_CLKCFG_DIVEN_EN                0x00001000
+
+// Enable divide by 3.
+#define AM_REG_IOMSTR_CLKCFG_DIV3_S                  11
+#define AM_REG_IOMSTR_CLKCFG_DIV3_M                  0x00000800
+#define AM_REG_IOMSTR_CLKCFG_DIV3(n)                 (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_IOMSTR_CLKCFG_DIV3_DIS                0x00000000
+#define AM_REG_IOMSTR_CLKCFG_DIV3_EN                 0x00000800
+
+// Select the input clock frequency.
+#define AM_REG_IOMSTR_CLKCFG_FSEL_S                  8
+#define AM_REG_IOMSTR_CLKCFG_FSEL_M                  0x00000700
+#define AM_REG_IOMSTR_CLKCFG_FSEL(n)                 (((uint32_t)(n) << 8) & 0x00000700)
+#define AM_REG_IOMSTR_CLKCFG_FSEL_MIN_PWR            0x00000000
+#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC               0x00000100
+#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV2          0x00000200
+#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV4          0x00000300
+#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV8          0x00000400
+#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV16         0x00000500
+#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV32         0x00000600
+#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV64         0x00000700
+
+//*****************************************************************************
+//
+// IOMSTR_CMD - Command Register
+//
+//*****************************************************************************
+// This register holds the I/O Command
+#define AM_REG_IOMSTR_CMD_CMD_S                      0
+#define AM_REG_IOMSTR_CMD_CMD_M                      0xFFFFFFFF
+#define AM_REG_IOMSTR_CMD_CMD(n)                     (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// IOMSTR_CMDRPT - Command Repeat Register
+//
+//*****************************************************************************
+// These bits hold the Command repeat count.
+#define AM_REG_IOMSTR_CMDRPT_CMDRPT_S                0
+#define AM_REG_IOMSTR_CMDRPT_CMDRPT_M                0x0000001F
+#define AM_REG_IOMSTR_CMDRPT_CMDRPT(n)               (((uint32_t)(n) << 0) & 0x0000001F)
+
+//*****************************************************************************
+//
+// IOMSTR_STATUS - Status Register
+//
+//*****************************************************************************
+// This bit indicates if the I/O state machine is IDLE.
+#define AM_REG_IOMSTR_STATUS_IDLEST_S                2
+#define AM_REG_IOMSTR_STATUS_IDLEST_M                0x00000004
+#define AM_REG_IOMSTR_STATUS_IDLEST(n)               (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_IOMSTR_STATUS_IDLEST_IDLE             0x00000004
+
+// This bit indicates if the I/O Command is active.
+#define AM_REG_IOMSTR_STATUS_CMDACT_S                1
+#define AM_REG_IOMSTR_STATUS_CMDACT_M                0x00000002
+#define AM_REG_IOMSTR_STATUS_CMDACT(n)               (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_IOMSTR_STATUS_CMDACT_ACTIVE           0x00000002
+
+// This bit indicates if an error interrupt has occurred.
+#define AM_REG_IOMSTR_STATUS_ERR_S                   0
+#define AM_REG_IOMSTR_STATUS_ERR_M                   0x00000001
+#define AM_REG_IOMSTR_STATUS_ERR(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_IOMSTR_STATUS_ERR_ERROR               0x00000001
+
+//*****************************************************************************
+//
+// IOMSTR_CFG - I/O Master Configuration
+//
+//*****************************************************************************
+// This bit enables the IO Master.
+#define AM_REG_IOMSTR_CFG_IFCEN_S                    31
+#define AM_REG_IOMSTR_CFG_IFCEN_M                    0x80000000
+#define AM_REG_IOMSTR_CFG_IFCEN(n)                   (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_IOMSTR_CFG_IFCEN_DIS                  0x00000000
+#define AM_REG_IOMSTR_CFG_IFCEN_EN                   0x80000000
+
+// This bit selects the read flow control signal polarity.
+#define AM_REG_IOMSTR_CFG_RDFCPOL_S                  14
+#define AM_REG_IOMSTR_CFG_RDFCPOL_M                  0x00004000
+#define AM_REG_IOMSTR_CFG_RDFCPOL(n)                 (((uint32_t)(n) << 14) & 0x00004000)
+#define AM_REG_IOMSTR_CFG_RDFCPOL_HIGH               0x00000000
+#define AM_REG_IOMSTR_CFG_RDFCPOL_LOW                0x00004000
+
+// This bit selects the write flow control signal polarity.
+#define AM_REG_IOMSTR_CFG_WTFCPOL_S                  13
+#define AM_REG_IOMSTR_CFG_WTFCPOL_M                  0x00002000
+#define AM_REG_IOMSTR_CFG_WTFCPOL(n)                 (((uint32_t)(n) << 13) & 0x00002000)
+#define AM_REG_IOMSTR_CFG_WTFCPOL_HIGH               0x00000000
+#define AM_REG_IOMSTR_CFG_WTFCPOL_LOW                0x00002000
+
+// This bit selects the write mode flow control signal.
+#define AM_REG_IOMSTR_CFG_WTFCIRQ_S                  12
+#define AM_REG_IOMSTR_CFG_WTFCIRQ_M                  0x00001000
+#define AM_REG_IOMSTR_CFG_WTFCIRQ(n)                 (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_IOMSTR_CFG_WTFCIRQ_MISO               0x00000000
+#define AM_REG_IOMSTR_CFG_WTFCIRQ_IRQ                0x00001000
+
+// This bit must be left at the default value of 0.
+#define AM_REG_IOMSTR_CFG_FCDEL_S                    11
+#define AM_REG_IOMSTR_CFG_FCDEL_M                    0x00000800
+#define AM_REG_IOMSTR_CFG_FCDEL(n)                   (((uint32_t)(n) << 11) & 0x00000800)
+
+// This bit invewrts MOSI when flow control is enabled.
+#define AM_REG_IOMSTR_CFG_MOSIINV_S                  10
+#define AM_REG_IOMSTR_CFG_MOSIINV_M                  0x00000400
+#define AM_REG_IOMSTR_CFG_MOSIINV(n)                 (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_IOMSTR_CFG_MOSIINV_NORMAL             0x00000000
+#define AM_REG_IOMSTR_CFG_MOSIINV_INVERT             0x00000400
+
+// This bit enables read mode flow control.
+#define AM_REG_IOMSTR_CFG_RDFC_S                     9
+#define AM_REG_IOMSTR_CFG_RDFC_M                     0x00000200
+#define AM_REG_IOMSTR_CFG_RDFC(n)                    (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_IOMSTR_CFG_RDFC_DIS                   0x00000000
+#define AM_REG_IOMSTR_CFG_RDFC_EN                    0x00000200
+
+// This bit enables write mode flow control.
+#define AM_REG_IOMSTR_CFG_WTFC_S                     8
+#define AM_REG_IOMSTR_CFG_WTFC_M                     0x00000100
+#define AM_REG_IOMSTR_CFG_WTFC(n)                    (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_IOMSTR_CFG_WTFC_DIS                   0x00000000
+#define AM_REG_IOMSTR_CFG_WTFC_EN                    0x00000100
+
+// This bit selects the preread timing.
+#define AM_REG_IOMSTR_CFG_STARTRD_S                  4
+#define AM_REG_IOMSTR_CFG_STARTRD_M                  0x00000030
+#define AM_REG_IOMSTR_CFG_STARTRD(n)                 (((uint32_t)(n) << 4) & 0x00000030)
+#define AM_REG_IOMSTR_CFG_STARTRD_PRERD0             0x00000000
+#define AM_REG_IOMSTR_CFG_STARTRD_PRERD1             0x00000010
+#define AM_REG_IOMSTR_CFG_STARTRD_PRERD2             0x00000020
+#define AM_REG_IOMSTR_CFG_STARTRD_PRERD3             0x00000030
+
+// This bit selects full duplex mode.
+#define AM_REG_IOMSTR_CFG_FULLDUP_S                  3
+#define AM_REG_IOMSTR_CFG_FULLDUP_M                  0x00000008
+#define AM_REG_IOMSTR_CFG_FULLDUP(n)                 (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_IOMSTR_CFG_FULLDUP_NORMAL             0x00000000
+#define AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP            0x00000008
+
+// This bit selects SPI phase.
+#define AM_REG_IOMSTR_CFG_SPHA_S                     2
+#define AM_REG_IOMSTR_CFG_SPHA_M                     0x00000004
+#define AM_REG_IOMSTR_CFG_SPHA(n)                    (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_IOMSTR_CFG_SPHA_SAMPLE_LEADING_EDGE   0x00000000
+#define AM_REG_IOMSTR_CFG_SPHA_SAMPLE_TRAILING_EDGE  0x00000004
+
+// This bit selects SPI polarity.
+#define AM_REG_IOMSTR_CFG_SPOL_S                     1
+#define AM_REG_IOMSTR_CFG_SPOL_M                     0x00000002
+#define AM_REG_IOMSTR_CFG_SPOL(n)                    (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_IOMSTR_CFG_SPOL_CLK_BASE_0            0x00000000
+#define AM_REG_IOMSTR_CFG_SPOL_CLK_BASE_1            0x00000002
+
+// This bit selects the I/O interface.
+#define AM_REG_IOMSTR_CFG_IFCSEL_S                   0
+#define AM_REG_IOMSTR_CFG_IFCSEL_M                   0x00000001
+#define AM_REG_IOMSTR_CFG_IFCSEL(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_IOMSTR_CFG_IFCSEL_I2C                 0x00000000
+#define AM_REG_IOMSTR_CFG_IFCSEL_SPI                 0x00000001
+
+#endif // AM_REG_IOMSTR_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h b/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h
new file mode 100644
index 0000000000..4a1c96ae3c
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h
@@ -0,0 +1,514 @@
+//*****************************************************************************
+//
+//  am_reg_ioslave.h
+//! @file
+//!
+//! @brief Register macros for the IOSLAVE module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_IOSLAVE_H
+#define AM_REG_IOSLAVE_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_IOSLAVE_NUM_MODULES                   1
+#define AM_REG_IOSLAVEn(n) \
+    (REG_IOSLAVE_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_IOSLAVE_FIFOPTR_O                     0x00000100
+#define AM_REG_IOSLAVE_FIFOCFG_O                     0x00000104
+#define AM_REG_IOSLAVE_FIFOTHR_O                     0x00000108
+#define AM_REG_IOSLAVE_FUPD_O                        0x0000010C
+#define AM_REG_IOSLAVE_FIFOCTR_O                     0x00000110
+#define AM_REG_IOSLAVE_FIFOINC_O                     0x00000114
+#define AM_REG_IOSLAVE_CFG_O                         0x00000118
+#define AM_REG_IOSLAVE_PRENC_O                       0x0000011C
+#define AM_REG_IOSLAVE_IOINTCTL_O                    0x00000120
+#define AM_REG_IOSLAVE_GENADD_O                      0x00000124
+#define AM_REG_IOSLAVE_INTEN_O                       0x00000200
+#define AM_REG_IOSLAVE_INTSTAT_O                     0x00000204
+#define AM_REG_IOSLAVE_INTCLR_O                      0x00000208
+#define AM_REG_IOSLAVE_INTSET_O                      0x0000020C
+#define AM_REG_IOSLAVE_REGACCINTEN_O                 0x00000210
+#define AM_REG_IOSLAVE_REGACCINTSTAT_O               0x00000214
+#define AM_REG_IOSLAVE_REGACCINTCLR_O                0x00000218
+#define AM_REG_IOSLAVE_REGACCINTSET_O                0x0000021C
+
+//*****************************************************************************
+//
+// IOSLAVE_INTEN - IO Slave Interrupts: Enable
+//
+//*****************************************************************************
+// Transfer complete interrupt, write to register space.
+#define AM_REG_IOSLAVE_INTEN_XCMPWR_S                9
+#define AM_REG_IOSLAVE_INTEN_XCMPWR_M                0x00000200
+#define AM_REG_IOSLAVE_INTEN_XCMPWR(n)               (((uint32_t)(n) << 9) & 0x00000200)
+
+// Transfer complete interrupt, write to FIFO space.
+#define AM_REG_IOSLAVE_INTEN_XCMPWF_S                8
+#define AM_REG_IOSLAVE_INTEN_XCMPWF_M                0x00000100
+#define AM_REG_IOSLAVE_INTEN_XCMPWF(n)               (((uint32_t)(n) << 8) & 0x00000100)
+
+// Transfer complete interrupt, read from register space.
+#define AM_REG_IOSLAVE_INTEN_XCMPRR_S                7
+#define AM_REG_IOSLAVE_INTEN_XCMPRR_M                0x00000080
+#define AM_REG_IOSLAVE_INTEN_XCMPRR(n)               (((uint32_t)(n) << 7) & 0x00000080)
+
+// Transfer complete interrupt, read from FIFO space.
+#define AM_REG_IOSLAVE_INTEN_XCMPRF_S                6
+#define AM_REG_IOSLAVE_INTEN_XCMPRF_M                0x00000040
+#define AM_REG_IOSLAVE_INTEN_XCMPRF(n)               (((uint32_t)(n) << 6) & 0x00000040)
+
+// I2C Interrupt Write interrupt.
+#define AM_REG_IOSLAVE_INTEN_IOINTW_S                5
+#define AM_REG_IOSLAVE_INTEN_IOINTW_M                0x00000020
+#define AM_REG_IOSLAVE_INTEN_IOINTW(n)               (((uint32_t)(n) << 5) & 0x00000020)
+
+// I2C General Address interrupt.
+#define AM_REG_IOSLAVE_INTEN_GENAD_S                 4
+#define AM_REG_IOSLAVE_INTEN_GENAD_M                 0x00000010
+#define AM_REG_IOSLAVE_INTEN_GENAD(n)                (((uint32_t)(n) << 4) & 0x00000010)
+
+// FIFO Read Error interrupt.
+#define AM_REG_IOSLAVE_INTEN_FRDERR_S                3
+#define AM_REG_IOSLAVE_INTEN_FRDERR_M                0x00000008
+#define AM_REG_IOSLAVE_INTEN_FRDERR(n)               (((uint32_t)(n) << 3) & 0x00000008)
+
+// FIFO Underflow interrupt.
+#define AM_REG_IOSLAVE_INTEN_FUNDFL_S                2
+#define AM_REG_IOSLAVE_INTEN_FUNDFL_M                0x00000004
+#define AM_REG_IOSLAVE_INTEN_FUNDFL(n)               (((uint32_t)(n) << 2) & 0x00000004)
+
+// FIFO Overflow interrupt.
+#define AM_REG_IOSLAVE_INTEN_FOVFL_S                 1
+#define AM_REG_IOSLAVE_INTEN_FOVFL_M                 0x00000002
+#define AM_REG_IOSLAVE_INTEN_FOVFL(n)                (((uint32_t)(n) << 1) & 0x00000002)
+
+// FIFO Size interrupt.
+#define AM_REG_IOSLAVE_INTEN_FSIZE_S                 0
+#define AM_REG_IOSLAVE_INTEN_FSIZE_M                 0x00000001
+#define AM_REG_IOSLAVE_INTEN_FSIZE(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOSLAVE_INTSTAT - IO Slave Interrupts: Status
+//
+//*****************************************************************************
+// Transfer complete interrupt, write to register space.
+#define AM_REG_IOSLAVE_INTSTAT_XCMPWR_S              9
+#define AM_REG_IOSLAVE_INTSTAT_XCMPWR_M              0x00000200
+#define AM_REG_IOSLAVE_INTSTAT_XCMPWR(n)             (((uint32_t)(n) << 9) & 0x00000200)
+
+// Transfer complete interrupt, write to FIFO space.
+#define AM_REG_IOSLAVE_INTSTAT_XCMPWF_S              8
+#define AM_REG_IOSLAVE_INTSTAT_XCMPWF_M              0x00000100
+#define AM_REG_IOSLAVE_INTSTAT_XCMPWF(n)             (((uint32_t)(n) << 8) & 0x00000100)
+
+// Transfer complete interrupt, read from register space.
+#define AM_REG_IOSLAVE_INTSTAT_XCMPRR_S              7
+#define AM_REG_IOSLAVE_INTSTAT_XCMPRR_M              0x00000080
+#define AM_REG_IOSLAVE_INTSTAT_XCMPRR(n)             (((uint32_t)(n) << 7) & 0x00000080)
+
+// Transfer complete interrupt, read from FIFO space.
+#define AM_REG_IOSLAVE_INTSTAT_XCMPRF_S              6
+#define AM_REG_IOSLAVE_INTSTAT_XCMPRF_M              0x00000040
+#define AM_REG_IOSLAVE_INTSTAT_XCMPRF(n)             (((uint32_t)(n) << 6) & 0x00000040)
+
+// I2C Interrupt Write interrupt.
+#define AM_REG_IOSLAVE_INTSTAT_IOINTW_S              5
+#define AM_REG_IOSLAVE_INTSTAT_IOINTW_M              0x00000020
+#define AM_REG_IOSLAVE_INTSTAT_IOINTW(n)             (((uint32_t)(n) << 5) & 0x00000020)
+
+// I2C General Address interrupt.
+#define AM_REG_IOSLAVE_INTSTAT_GENAD_S               4
+#define AM_REG_IOSLAVE_INTSTAT_GENAD_M               0x00000010
+#define AM_REG_IOSLAVE_INTSTAT_GENAD(n)              (((uint32_t)(n) << 4) & 0x00000010)
+
+// FIFO Read Error interrupt.
+#define AM_REG_IOSLAVE_INTSTAT_FRDERR_S              3
+#define AM_REG_IOSLAVE_INTSTAT_FRDERR_M              0x00000008
+#define AM_REG_IOSLAVE_INTSTAT_FRDERR(n)             (((uint32_t)(n) << 3) & 0x00000008)
+
+// FIFO Underflow interrupt.
+#define AM_REG_IOSLAVE_INTSTAT_FUNDFL_S              2
+#define AM_REG_IOSLAVE_INTSTAT_FUNDFL_M              0x00000004
+#define AM_REG_IOSLAVE_INTSTAT_FUNDFL(n)             (((uint32_t)(n) << 2) & 0x00000004)
+
+// FIFO Overflow interrupt.
+#define AM_REG_IOSLAVE_INTSTAT_FOVFL_S               1
+#define AM_REG_IOSLAVE_INTSTAT_FOVFL_M               0x00000002
+#define AM_REG_IOSLAVE_INTSTAT_FOVFL(n)              (((uint32_t)(n) << 1) & 0x00000002)
+
+// FIFO Size interrupt.
+#define AM_REG_IOSLAVE_INTSTAT_FSIZE_S               0
+#define AM_REG_IOSLAVE_INTSTAT_FSIZE_M               0x00000001
+#define AM_REG_IOSLAVE_INTSTAT_FSIZE(n)              (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOSLAVE_INTCLR - IO Slave Interrupts: Clear
+//
+//*****************************************************************************
+// Transfer complete interrupt, write to register space.
+#define AM_REG_IOSLAVE_INTCLR_XCMPWR_S               9
+#define AM_REG_IOSLAVE_INTCLR_XCMPWR_M               0x00000200
+#define AM_REG_IOSLAVE_INTCLR_XCMPWR(n)              (((uint32_t)(n) << 9) & 0x00000200)
+
+// Transfer complete interrupt, write to FIFO space.
+#define AM_REG_IOSLAVE_INTCLR_XCMPWF_S               8
+#define AM_REG_IOSLAVE_INTCLR_XCMPWF_M               0x00000100
+#define AM_REG_IOSLAVE_INTCLR_XCMPWF(n)              (((uint32_t)(n) << 8) & 0x00000100)
+
+// Transfer complete interrupt, read from register space.
+#define AM_REG_IOSLAVE_INTCLR_XCMPRR_S               7
+#define AM_REG_IOSLAVE_INTCLR_XCMPRR_M               0x00000080
+#define AM_REG_IOSLAVE_INTCLR_XCMPRR(n)              (((uint32_t)(n) << 7) & 0x00000080)
+
+// Transfer complete interrupt, read from FIFO space.
+#define AM_REG_IOSLAVE_INTCLR_XCMPRF_S               6
+#define AM_REG_IOSLAVE_INTCLR_XCMPRF_M               0x00000040
+#define AM_REG_IOSLAVE_INTCLR_XCMPRF(n)              (((uint32_t)(n) << 6) & 0x00000040)
+
+// I2C Interrupt Write interrupt.
+#define AM_REG_IOSLAVE_INTCLR_IOINTW_S               5
+#define AM_REG_IOSLAVE_INTCLR_IOINTW_M               0x00000020
+#define AM_REG_IOSLAVE_INTCLR_IOINTW(n)              (((uint32_t)(n) << 5) & 0x00000020)
+
+// I2C General Address interrupt.
+#define AM_REG_IOSLAVE_INTCLR_GENAD_S                4
+#define AM_REG_IOSLAVE_INTCLR_GENAD_M                0x00000010
+#define AM_REG_IOSLAVE_INTCLR_GENAD(n)               (((uint32_t)(n) << 4) & 0x00000010)
+
+// FIFO Read Error interrupt.
+#define AM_REG_IOSLAVE_INTCLR_FRDERR_S               3
+#define AM_REG_IOSLAVE_INTCLR_FRDERR_M               0x00000008
+#define AM_REG_IOSLAVE_INTCLR_FRDERR(n)              (((uint32_t)(n) << 3) & 0x00000008)
+
+// FIFO Underflow interrupt.
+#define AM_REG_IOSLAVE_INTCLR_FUNDFL_S               2
+#define AM_REG_IOSLAVE_INTCLR_FUNDFL_M               0x00000004
+#define AM_REG_IOSLAVE_INTCLR_FUNDFL(n)              (((uint32_t)(n) << 2) & 0x00000004)
+
+// FIFO Overflow interrupt.
+#define AM_REG_IOSLAVE_INTCLR_FOVFL_S                1
+#define AM_REG_IOSLAVE_INTCLR_FOVFL_M                0x00000002
+#define AM_REG_IOSLAVE_INTCLR_FOVFL(n)               (((uint32_t)(n) << 1) & 0x00000002)
+
+// FIFO Size interrupt.
+#define AM_REG_IOSLAVE_INTCLR_FSIZE_S                0
+#define AM_REG_IOSLAVE_INTCLR_FSIZE_M                0x00000001
+#define AM_REG_IOSLAVE_INTCLR_FSIZE(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOSLAVE_INTSET - IO Slave Interrupts: Set
+//
+//*****************************************************************************
+// Transfer complete interrupt, write to register space.
+#define AM_REG_IOSLAVE_INTSET_XCMPWR_S               9
+#define AM_REG_IOSLAVE_INTSET_XCMPWR_M               0x00000200
+#define AM_REG_IOSLAVE_INTSET_XCMPWR(n)              (((uint32_t)(n) << 9) & 0x00000200)
+
+// Transfer complete interrupt, write to FIFO space.
+#define AM_REG_IOSLAVE_INTSET_XCMPWF_S               8
+#define AM_REG_IOSLAVE_INTSET_XCMPWF_M               0x00000100
+#define AM_REG_IOSLAVE_INTSET_XCMPWF(n)              (((uint32_t)(n) << 8) & 0x00000100)
+
+// Transfer complete interrupt, read from register space.
+#define AM_REG_IOSLAVE_INTSET_XCMPRR_S               7
+#define AM_REG_IOSLAVE_INTSET_XCMPRR_M               0x00000080
+#define AM_REG_IOSLAVE_INTSET_XCMPRR(n)              (((uint32_t)(n) << 7) & 0x00000080)
+
+// Transfer complete interrupt, read from FIFO space.
+#define AM_REG_IOSLAVE_INTSET_XCMPRF_S               6
+#define AM_REG_IOSLAVE_INTSET_XCMPRF_M               0x00000040
+#define AM_REG_IOSLAVE_INTSET_XCMPRF(n)              (((uint32_t)(n) << 6) & 0x00000040)
+
+// I2C Interrupt Write interrupt.
+#define AM_REG_IOSLAVE_INTSET_IOINTW_S               5
+#define AM_REG_IOSLAVE_INTSET_IOINTW_M               0x00000020
+#define AM_REG_IOSLAVE_INTSET_IOINTW(n)              (((uint32_t)(n) << 5) & 0x00000020)
+
+// I2C General Address interrupt.
+#define AM_REG_IOSLAVE_INTSET_GENAD_S                4
+#define AM_REG_IOSLAVE_INTSET_GENAD_M                0x00000010
+#define AM_REG_IOSLAVE_INTSET_GENAD(n)               (((uint32_t)(n) << 4) & 0x00000010)
+
+// FIFO Read Error interrupt.
+#define AM_REG_IOSLAVE_INTSET_FRDERR_S               3
+#define AM_REG_IOSLAVE_INTSET_FRDERR_M               0x00000008
+#define AM_REG_IOSLAVE_INTSET_FRDERR(n)              (((uint32_t)(n) << 3) & 0x00000008)
+
+// FIFO Underflow interrupt.
+#define AM_REG_IOSLAVE_INTSET_FUNDFL_S               2
+#define AM_REG_IOSLAVE_INTSET_FUNDFL_M               0x00000004
+#define AM_REG_IOSLAVE_INTSET_FUNDFL(n)              (((uint32_t)(n) << 2) & 0x00000004)
+
+// FIFO Overflow interrupt.
+#define AM_REG_IOSLAVE_INTSET_FOVFL_S                1
+#define AM_REG_IOSLAVE_INTSET_FOVFL_M                0x00000002
+#define AM_REG_IOSLAVE_INTSET_FOVFL(n)               (((uint32_t)(n) << 1) & 0x00000002)
+
+// FIFO Size interrupt.
+#define AM_REG_IOSLAVE_INTSET_FSIZE_S                0
+#define AM_REG_IOSLAVE_INTSET_FSIZE_M                0x00000001
+#define AM_REG_IOSLAVE_INTSET_FSIZE(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOSLAVE_REGACCINTEN - Register Access Interrupts: Enable
+//
+//*****************************************************************************
+// Register access interrupts.
+#define AM_REG_IOSLAVE_REGACCINTEN_REGACC_S          0
+#define AM_REG_IOSLAVE_REGACCINTEN_REGACC_M          0xFFFFFFFF
+#define AM_REG_IOSLAVE_REGACCINTEN_REGACC(n)         (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// IOSLAVE_REGACCINTSTAT - Register Access Interrupts: Status
+//
+//*****************************************************************************
+// Register access interrupts.
+#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC_S        0
+#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC_M        0xFFFFFFFF
+#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC(n)       (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// IOSLAVE_REGACCINTCLR - Register Access Interrupts: Clear
+//
+//*****************************************************************************
+// Register access interrupts.
+#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC_S         0
+#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC_M         0xFFFFFFFF
+#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC(n)        (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// IOSLAVE_REGACCINTSET - Register Access Interrupts: Set
+//
+//*****************************************************************************
+// Register access interrupts.
+#define AM_REG_IOSLAVE_REGACCINTSET_REGACC_S         0
+#define AM_REG_IOSLAVE_REGACCINTSET_REGACC_M         0xFFFFFFFF
+#define AM_REG_IOSLAVE_REGACCINTSET_REGACC(n)        (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// IOSLAVE_FIFOPTR - Current FIFO Pointer
+//
+//*****************************************************************************
+// The number of bytes currently in the hardware FIFO.
+#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S             8
+#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M             0x0000FF00
+#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ(n)            (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Current FIFO pointer.
+#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_S             0
+#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_M             0x000000FF
+#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR(n)            (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// IOSLAVE_FIFOCFG - FIFO Configuration
+//
+//*****************************************************************************
+// Defines the read-only area.  The IO Slave read-only area is situated in LRAM
+// at (ROBASE*8) to (FIFOOBASE*8-1)
+#define AM_REG_IOSLAVE_FIFOCFG_ROBASE_S              24
+#define AM_REG_IOSLAVE_FIFOCFG_ROBASE_M              0x3F000000
+#define AM_REG_IOSLAVE_FIFOCFG_ROBASE(n)             (((uint32_t)(n) << 24) & 0x3F000000)
+
+// These bits hold the maximum FIFO address in 8 byte segments.  It is also the
+// beginning of the RAM area of the LRAM.  Note that no RAM area is configured
+// if FIFOMAX is set to 0x1F.
+#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX_S             8
+#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX_M             0x00003F00
+#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX(n)            (((uint32_t)(n) << 8) & 0x00003F00)
+
+// These bits hold the base address of the I/O FIFO in 8 byte segments. The IO
+// Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1).
+#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE_S            0
+#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE_M            0x0000001F
+#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE(n)           (((uint32_t)(n) << 0) & 0x0000001F)
+
+//*****************************************************************************
+//
+// IOSLAVE_FIFOTHR - FIFO Threshold Configuration
+//
+//*****************************************************************************
+// FIFO size interrupt threshold.
+#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR_S             0
+#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR_M             0x000000FF
+#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR(n)            (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// IOSLAVE_FUPD - FIFO Update Status
+//
+//*****************************************************************************
+// This bitfield indicates an IO read is active.
+#define AM_REG_IOSLAVE_FUPD_IOREAD_S                 1
+#define AM_REG_IOSLAVE_FUPD_IOREAD_M                 0x00000002
+#define AM_REG_IOSLAVE_FUPD_IOREAD(n)                (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit indicates that a FIFO update is underway.
+#define AM_REG_IOSLAVE_FUPD_FIFOUPD_S                0
+#define AM_REG_IOSLAVE_FUPD_FIFOUPD_M                0x00000001
+#define AM_REG_IOSLAVE_FUPD_FIFOUPD(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// IOSLAVE_FIFOCTR - Overall FIFO Counter
+//
+//*****************************************************************************
+// Virtual FIFO byte count
+#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR_S             0
+#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR_M             0x000003FF
+#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR(n)            (((uint32_t)(n) << 0) & 0x000003FF)
+
+//*****************************************************************************
+//
+// IOSLAVE_FIFOINC - Overall FIFO Counter Increment
+//
+//*****************************************************************************
+// Increment the Overall FIFO Counter by this value on a write
+#define AM_REG_IOSLAVE_FIFOINC_FIFOINC_S             0
+#define AM_REG_IOSLAVE_FIFOINC_FIFOINC_M             0x000003FF
+#define AM_REG_IOSLAVE_FIFOINC_FIFOINC(n)            (((uint32_t)(n) << 0) & 0x000003FF)
+
+//*****************************************************************************
+//
+// IOSLAVE_CFG - I/O Slave Configuration
+//
+//*****************************************************************************
+// IOSLAVE interface enable.
+#define AM_REG_IOSLAVE_CFG_IFCEN_S                   31
+#define AM_REG_IOSLAVE_CFG_IFCEN_M                   0x80000000
+#define AM_REG_IOSLAVE_CFG_IFCEN(n)                  (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_IOSLAVE_CFG_IFCEN_DIS                 0x00000000
+#define AM_REG_IOSLAVE_CFG_IFCEN_EN                  0x80000000
+
+// 7-bit or 10-bit I2C device address.
+#define AM_REG_IOSLAVE_CFG_I2CADDR_S                 8
+#define AM_REG_IOSLAVE_CFG_I2CADDR_M                 0x000FFF00
+#define AM_REG_IOSLAVE_CFG_I2CADDR(n)                (((uint32_t)(n) << 8) & 0x000FFF00)
+
+// This bit holds the cycle to initiate an I/O RAM read.
+#define AM_REG_IOSLAVE_CFG_STARTRD_S                 4
+#define AM_REG_IOSLAVE_CFG_STARTRD_M                 0x00000010
+#define AM_REG_IOSLAVE_CFG_STARTRD(n)                (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_IOSLAVE_CFG_STARTRD_LATE              0x00000000
+#define AM_REG_IOSLAVE_CFG_STARTRD_EARLY             0x00000010
+
+// This bit selects the transfer bit ordering.
+#define AM_REG_IOSLAVE_CFG_LSB_S                     2
+#define AM_REG_IOSLAVE_CFG_LSB_M                     0x00000004
+#define AM_REG_IOSLAVE_CFG_LSB(n)                    (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_IOSLAVE_CFG_LSB_MSB_FIRST             0x00000000
+#define AM_REG_IOSLAVE_CFG_LSB_LSB_FIRST             0x00000004
+
+// This bit selects SPI polarity.
+#define AM_REG_IOSLAVE_CFG_SPOL_S                    1
+#define AM_REG_IOSLAVE_CFG_SPOL_M                    0x00000002
+#define AM_REG_IOSLAVE_CFG_SPOL(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3        0x00000000
+#define AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2        0x00000002
+
+// This bit selects the I/O interface.
+#define AM_REG_IOSLAVE_CFG_IFCSEL_S                  0
+#define AM_REG_IOSLAVE_CFG_IFCSEL_M                  0x00000001
+#define AM_REG_IOSLAVE_CFG_IFCSEL(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_IOSLAVE_CFG_IFCSEL_I2C                0x00000000
+#define AM_REG_IOSLAVE_CFG_IFCSEL_SPI                0x00000001
+
+//*****************************************************************************
+//
+// IOSLAVE_PRENC - I/O Slave Interrupt Priority Encode
+//
+//*****************************************************************************
+// These bits hold the priority encode of the REGACC interrupts.
+#define AM_REG_IOSLAVE_PRENC_PRENC_S                 0
+#define AM_REG_IOSLAVE_PRENC_PRENC_M                 0x0000001F
+#define AM_REG_IOSLAVE_PRENC_PRENC(n)                (((uint32_t)(n) << 0) & 0x0000001F)
+
+//*****************************************************************************
+//
+// IOSLAVE_IOINTCTL - I/O Interrupt Control
+//
+//*****************************************************************************
+// These bits set the IOINT interrupts when written with a 1.
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET_S           24
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET_M           0xFF000000
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET(n)          (((uint32_t)(n) << 24) & 0xFF000000)
+
+// This bit clears all of the IOINT interrupts when written with a 1.
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR_S           16
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR_M           0x00010000
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// These bits read the IOINT interrupts.
+#define AM_REG_IOSLAVE_IOINTCTL_IOINT_S              8
+#define AM_REG_IOSLAVE_IOINTCTL_IOINT_M              0x0000FF00
+#define AM_REG_IOSLAVE_IOINTCTL_IOINT(n)             (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// These read-only bits indicate whether the IOINT interrupts are enabled.
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN_S            0
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN_M            0x000000FF
+#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN(n)           (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// IOSLAVE_GENADD - General Address Data
+//
+//*****************************************************************************
+// The data supplied on the last General Address reference.
+#define AM_REG_IOSLAVE_GENADD_GADATA_S               0
+#define AM_REG_IOSLAVE_GENADD_GADATA_M               0x000000FF
+#define AM_REG_IOSLAVE_GENADD_GADATA(n)              (((uint32_t)(n) << 0) & 0x000000FF)
+
+#endif // AM_REG_IOSLAVE_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h
new file mode 100644
index 0000000000..c007aa629a
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h
@@ -0,0 +1,657 @@
+//*****************************************************************************
+//
+//  am_reg_itm.h
+//! @file
+//!
+//! @brief Register macros for the ITM module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_ITM_H
+#define AM_REG_ITM_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_ITM_NUM_MODULES                       1
+#define AM_REG_ITMn(n) \
+    (REG_ITM_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_ITM_STIM0_O                           0xE0000000
+#define AM_REG_ITM_STIM1_O                           0xE0000004
+#define AM_REG_ITM_STIM2_O                           0xE0000008
+#define AM_REG_ITM_STIM3_O                           0xE000000C
+#define AM_REG_ITM_STIM4_O                           0xE0000010
+#define AM_REG_ITM_STIM5_O                           0xE0000014
+#define AM_REG_ITM_STIM6_O                           0xE0000018
+#define AM_REG_ITM_STIM7_O                           0xE000001C
+#define AM_REG_ITM_STIM8_O                           0xE0000020
+#define AM_REG_ITM_STIM9_O                           0xE0000024
+#define AM_REG_ITM_STIM10_O                          0xE0000028
+#define AM_REG_ITM_STIM11_O                          0xE000002C
+#define AM_REG_ITM_STIM12_O                          0xE0000030
+#define AM_REG_ITM_STIM13_O                          0xE0000034
+#define AM_REG_ITM_STIM14_O                          0xE0000038
+#define AM_REG_ITM_STIM15_O                          0xE000003C
+#define AM_REG_ITM_STIM16_O                          0xE0000040
+#define AM_REG_ITM_STIM17_O                          0xE0000044
+#define AM_REG_ITM_STIM18_O                          0xE0000048
+#define AM_REG_ITM_STIM19_O                          0xE000004C
+#define AM_REG_ITM_STIM20_O                          0xE0000050
+#define AM_REG_ITM_STIM21_O                          0xE0000054
+#define AM_REG_ITM_STIM22_O                          0xE0000058
+#define AM_REG_ITM_STIM23_O                          0xE000005C
+#define AM_REG_ITM_STIM24_O                          0xE0000060
+#define AM_REG_ITM_STIM25_O                          0xE0000064
+#define AM_REG_ITM_STIM26_O                          0xE0000068
+#define AM_REG_ITM_STIM27_O                          0xE000006C
+#define AM_REG_ITM_STIM28_O                          0xE0000070
+#define AM_REG_ITM_STIM29_O                          0xE0000074
+#define AM_REG_ITM_STIM30_O                          0xE0000078
+#define AM_REG_ITM_STIM31_O                          0xE000007C
+#define AM_REG_ITM_TER_O                             0xE0000E00
+#define AM_REG_ITM_TPR_O                             0xE0000E40
+#define AM_REG_ITM_TCR_O                             0xE0000E80
+#define AM_REG_ITM_LOCKSREG_O                        0xE0000FB4
+#define AM_REG_ITM_PID4_O                            0xE0000FD0
+#define AM_REG_ITM_PID5_O                            0xE0000FD4
+#define AM_REG_ITM_PID6_O                            0xE0000FD8
+#define AM_REG_ITM_PID7_O                            0xE0000FDC
+#define AM_REG_ITM_PID0_O                            0xE0000FE0
+#define AM_REG_ITM_PID1_O                            0xE0000FE4
+#define AM_REG_ITM_PID2_O                            0xE0000FE8
+#define AM_REG_ITM_PID3_O                            0xE0000FEC
+#define AM_REG_ITM_CID0_O                            0xE0000FF0
+#define AM_REG_ITM_CID1_O                            0xE0000FF4
+#define AM_REG_ITM_CID2_O                            0xE0000FF8
+#define AM_REG_ITM_CID3_O                            0xE0000FFC
+#define AM_REG_ITM_LOCKAREG_O                        0xE0000FB0
+
+//*****************************************************************************
+//
+// Key values.
+//
+//*****************************************************************************
+#define AM_REG_ITM_LOCKAREG_KEYVAL                   0xC5ACCE55
+
+//*****************************************************************************
+//
+// ITM_STIM0 - Stimulus Port Register 0
+//
+//*****************************************************************************
+// Stimulus Port Register 0.
+#define AM_REG_ITM_STIM0_STIM0_S                     0
+#define AM_REG_ITM_STIM0_STIM0_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM0_STIM0(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM1 - Stimulus Port Register 1
+//
+//*****************************************************************************
+// Stimulus Port Register 1.
+#define AM_REG_ITM_STIM1_STIM1_S                     0
+#define AM_REG_ITM_STIM1_STIM1_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM1_STIM1(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM2 - Stimulus Port Register 2
+//
+//*****************************************************************************
+// Stimulus Port Register 2.
+#define AM_REG_ITM_STIM2_STIM2_S                     0
+#define AM_REG_ITM_STIM2_STIM2_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM2_STIM2(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM3 - Stimulus Port Register 3
+//
+//*****************************************************************************
+// Stimulus Port Register 3.
+#define AM_REG_ITM_STIM3_STIM3_S                     0
+#define AM_REG_ITM_STIM3_STIM3_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM3_STIM3(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM4 - Stimulus Port Register 4
+//
+//*****************************************************************************
+// Stimulus Port Register 4.
+#define AM_REG_ITM_STIM4_STIM4_S                     0
+#define AM_REG_ITM_STIM4_STIM4_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM4_STIM4(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM5 - Stimulus Port Register 5
+//
+//*****************************************************************************
+// Stimulus Port Register 5.
+#define AM_REG_ITM_STIM5_STIM5_S                     0
+#define AM_REG_ITM_STIM5_STIM5_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM5_STIM5(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM6 - Stimulus Port Register 6
+//
+//*****************************************************************************
+// Stimulus Port Register 6.
+#define AM_REG_ITM_STIM6_STIM6_S                     0
+#define AM_REG_ITM_STIM6_STIM6_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM6_STIM6(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM7 - Stimulus Port Register 7
+//
+//*****************************************************************************
+// Stimulus Port Register 7.
+#define AM_REG_ITM_STIM7_STIM7_S                     0
+#define AM_REG_ITM_STIM7_STIM7_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM7_STIM7(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM8 - Stimulus Port Register 8
+//
+//*****************************************************************************
+// Stimulus Port Register 8.
+#define AM_REG_ITM_STIM8_STIM8_S                     0
+#define AM_REG_ITM_STIM8_STIM8_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM8_STIM8(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM9 - Stimulus Port Register 9
+//
+//*****************************************************************************
+// Stimulus Port Register 9.
+#define AM_REG_ITM_STIM9_STIM9_S                     0
+#define AM_REG_ITM_STIM9_STIM9_M                     0xFFFFFFFF
+#define AM_REG_ITM_STIM9_STIM9(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM10 - Stimulus Port Register 10
+//
+//*****************************************************************************
+// Stimulus Port Register 10.
+#define AM_REG_ITM_STIM10_STIM10_S                   0
+#define AM_REG_ITM_STIM10_STIM10_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM10_STIM10(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM11 - Stimulus Port Register 11
+//
+//*****************************************************************************
+// Stimulus Port Register 11.
+#define AM_REG_ITM_STIM11_STIM11_S                   0
+#define AM_REG_ITM_STIM11_STIM11_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM11_STIM11(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM12 - Stimulus Port Register 12
+//
+//*****************************************************************************
+// Stimulus Port Register 12.
+#define AM_REG_ITM_STIM12_STIM12_S                   0
+#define AM_REG_ITM_STIM12_STIM12_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM12_STIM12(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM13 - Stimulus Port Register 13
+//
+//*****************************************************************************
+// Stimulus Port Register 13.
+#define AM_REG_ITM_STIM13_STIM13_S                   0
+#define AM_REG_ITM_STIM13_STIM13_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM13_STIM13(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM14 - Stimulus Port Register 14
+//
+//*****************************************************************************
+// Stimulus Port Register 14.
+#define AM_REG_ITM_STIM14_STIM14_S                   0
+#define AM_REG_ITM_STIM14_STIM14_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM14_STIM14(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM15 - Stimulus Port Register 15
+//
+//*****************************************************************************
+// Stimulus Port Register 15.
+#define AM_REG_ITM_STIM15_STIM15_S                   0
+#define AM_REG_ITM_STIM15_STIM15_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM15_STIM15(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM16 - Stimulus Port Register 16
+//
+//*****************************************************************************
+// Stimulus Port Register 16.
+#define AM_REG_ITM_STIM16_STIM16_S                   0
+#define AM_REG_ITM_STIM16_STIM16_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM16_STIM16(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM17 - Stimulus Port Register 17
+//
+//*****************************************************************************
+// Stimulus Port Register 17.
+#define AM_REG_ITM_STIM17_STIM17_S                   0
+#define AM_REG_ITM_STIM17_STIM17_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM17_STIM17(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM18 - Stimulus Port Register 18
+//
+//*****************************************************************************
+// Stimulus Port Register 18.
+#define AM_REG_ITM_STIM18_STIM18_S                   0
+#define AM_REG_ITM_STIM18_STIM18_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM18_STIM18(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM19 - Stimulus Port Register 19
+//
+//*****************************************************************************
+// Stimulus Port Register 19.
+#define AM_REG_ITM_STIM19_STIM19_S                   0
+#define AM_REG_ITM_STIM19_STIM19_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM19_STIM19(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM20 - Stimulus Port Register 20
+//
+//*****************************************************************************
+// Stimulus Port Register 20.
+#define AM_REG_ITM_STIM20_STIM20_S                   0
+#define AM_REG_ITM_STIM20_STIM20_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM20_STIM20(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM21 - Stimulus Port Register 21
+//
+//*****************************************************************************
+// Stimulus Port Register 21.
+#define AM_REG_ITM_STIM21_STIM21_S                   0
+#define AM_REG_ITM_STIM21_STIM21_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM21_STIM21(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM22 - Stimulus Port Register 22
+//
+//*****************************************************************************
+// Stimulus Port Register 22.
+#define AM_REG_ITM_STIM22_STIM22_S                   0
+#define AM_REG_ITM_STIM22_STIM22_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM22_STIM22(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM23 - Stimulus Port Register 23
+//
+//*****************************************************************************
+// Stimulus Port Register 23.
+#define AM_REG_ITM_STIM23_STIM23_S                   0
+#define AM_REG_ITM_STIM23_STIM23_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM23_STIM23(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM24 - Stimulus Port Register 24
+//
+//*****************************************************************************
+// Stimulus Port Register 24.
+#define AM_REG_ITM_STIM24_STIM24_S                   0
+#define AM_REG_ITM_STIM24_STIM24_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM24_STIM24(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM25 - Stimulus Port Register 25
+//
+//*****************************************************************************
+// Stimulus Port Register 25.
+#define AM_REG_ITM_STIM25_STIM25_S                   0
+#define AM_REG_ITM_STIM25_STIM25_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM25_STIM25(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM26 - Stimulus Port Register 26
+//
+//*****************************************************************************
+// Stimulus Port Register 26.
+#define AM_REG_ITM_STIM26_STIM26_S                   0
+#define AM_REG_ITM_STIM26_STIM26_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM26_STIM26(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM27 - Stimulus Port Register 27
+//
+//*****************************************************************************
+// Stimulus Port Register 27.
+#define AM_REG_ITM_STIM27_STIM27_S                   0
+#define AM_REG_ITM_STIM27_STIM27_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM27_STIM27(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM28 - Stimulus Port Register 28
+//
+//*****************************************************************************
+// Stimulus Port Register 28.
+#define AM_REG_ITM_STIM28_STIM28_S                   0
+#define AM_REG_ITM_STIM28_STIM28_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM28_STIM28(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM29 - Stimulus Port Register 29
+//
+//*****************************************************************************
+// Stimulus Port Register 29.
+#define AM_REG_ITM_STIM29_STIM29_S                   0
+#define AM_REG_ITM_STIM29_STIM29_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM29_STIM29(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM30 - Stimulus Port Register 30
+//
+//*****************************************************************************
+// Stimulus Port Register 30.
+#define AM_REG_ITM_STIM30_STIM30_S                   0
+#define AM_REG_ITM_STIM30_STIM30_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM30_STIM30(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_STIM31 - Stimulus Port Register 31
+//
+//*****************************************************************************
+// Stimulus Port Register 31.
+#define AM_REG_ITM_STIM31_STIM31_S                   0
+#define AM_REG_ITM_STIM31_STIM31_M                   0xFFFFFFFF
+#define AM_REG_ITM_STIM31_STIM31(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_TER - Trace Enable Register.
+//
+//*****************************************************************************
+// Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port..
+#define AM_REG_ITM_TER_STIMENA_S                     0
+#define AM_REG_ITM_TER_STIMENA_M                     0xFFFFFFFF
+#define AM_REG_ITM_TER_STIMENA(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_TPR - Trace Privilege Register.
+//
+//*****************************************************************************
+// Bit mask to enable tracing on ITM stimulus ports. bit[0] = stimulus
+// ports[7:0], bit[1] = stimulus ports[15:8], bit[2] = stimulus ports[23:16],
+// bit[3] = stimulus ports[31:24].
+#define AM_REG_ITM_TPR_PRIVMASK_S                    0
+#define AM_REG_ITM_TPR_PRIVMASK_M                    0x0000000F
+#define AM_REG_ITM_TPR_PRIVMASK(n)                   (((uint32_t)(n) << 0) & 0x0000000F)
+
+//*****************************************************************************
+//
+// ITM_TCR - Trace Control Register.
+//
+//*****************************************************************************
+// Set when ITM events present and being drained.
+#define AM_REG_ITM_TCR_BUSY_S                        23
+#define AM_REG_ITM_TCR_BUSY_M                        0x00800000
+#define AM_REG_ITM_TCR_BUSY(n)                       (((uint32_t)(n) << 23) & 0x00800000)
+
+// ATB ID for CoreSight system.
+#define AM_REG_ITM_TCR_ATB_ID_S                      16
+#define AM_REG_ITM_TCR_ATB_ID_M                      0x007F0000
+#define AM_REG_ITM_TCR_ATB_ID(n)                     (((uint32_t)(n) << 16) & 0x007F0000)
+
+// Global Timestamp Frequency.
+#define AM_REG_ITM_TCR_TS_FREQ_S                     10
+#define AM_REG_ITM_TCR_TS_FREQ_M                     0x00000C00
+#define AM_REG_ITM_TCR_TS_FREQ(n)                    (((uint32_t)(n) << 10) & 0x00000C00)
+
+// Timestamp prescaler: 0b00 = no prescaling 0b01 = divide by 4 0b10 = divide by
+// 16 0b11 = divide by 64.
+#define AM_REG_ITM_TCR_TS_PRESCALE_S                 8
+#define AM_REG_ITM_TCR_TS_PRESCALE_M                 0x00000300
+#define AM_REG_ITM_TCR_TS_PRESCALE(n)                (((uint32_t)(n) << 8) & 0x00000300)
+
+// Enable SWV behavior 鈥� count on TPIUEMIT and TPIUBAUD.
+#define AM_REG_ITM_TCR_SWV_ENABLE_S                  4
+#define AM_REG_ITM_TCR_SWV_ENABLE_M                  0x00000010
+#define AM_REG_ITM_TCR_SWV_ENABLE(n)                 (((uint32_t)(n) << 4) & 0x00000010)
+
+// Enables the DWT stimulus.
+#define AM_REG_ITM_TCR_DWT_ENABLE_S                  3
+#define AM_REG_ITM_TCR_DWT_ENABLE_M                  0x00000008
+#define AM_REG_ITM_TCR_DWT_ENABLE(n)                 (((uint32_t)(n) << 3) & 0x00000008)
+
+// Enables sync packets for TPIU.
+#define AM_REG_ITM_TCR_SYNC_ENABLE_S                 2
+#define AM_REG_ITM_TCR_SYNC_ENABLE_M                 0x00000004
+#define AM_REG_ITM_TCR_SYNC_ENABLE(n)                (((uint32_t)(n) << 2) & 0x00000004)
+
+// Enables differential timestamps. Differential timestamps are emitted when a
+// packet is written to the FIFO with a non-zero timestamp counter, and when the
+// timestamp counter overflows. Timestamps are emitted during idle times after a
+// fixed number of cycles. This provides a time reference for packets and inter-
+// packet gaps.
+#define AM_REG_ITM_TCR_TS_ENABLE_S                   1
+#define AM_REG_ITM_TCR_TS_ENABLE_M                   0x00000002
+#define AM_REG_ITM_TCR_TS_ENABLE(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+
+// Enable ITM. This is the master enable, and must be set before ITM Stimulus
+// and Trace Enable registers can be written.
+#define AM_REG_ITM_TCR_ITM_ENABLE_S                  0
+#define AM_REG_ITM_TCR_ITM_ENABLE_M                  0x00000001
+#define AM_REG_ITM_TCR_ITM_ENABLE(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// ITM_LOCKSREG - Lock Status Register
+//
+//*****************************************************************************
+// You cannot implement 8-bit lock accesses.
+#define AM_REG_ITM_LOCKSREG_BYTEACC_S                2
+#define AM_REG_ITM_LOCKSREG_BYTEACC_M                0x00000004
+#define AM_REG_ITM_LOCKSREG_BYTEACC(n)               (((uint32_t)(n) << 2) & 0x00000004)
+
+// Write access to component is blocked. All writes are ignored, reads are
+// permitted.
+#define AM_REG_ITM_LOCKSREG_ACCESS_S                 1
+#define AM_REG_ITM_LOCKSREG_ACCESS_M                 0x00000002
+#define AM_REG_ITM_LOCKSREG_ACCESS(n)                (((uint32_t)(n) << 1) & 0x00000002)
+
+// Indicates that a lock mechanism exists for this component.
+#define AM_REG_ITM_LOCKSREG_PRESENT_S                0
+#define AM_REG_ITM_LOCKSREG_PRESENT_M                0x00000001
+#define AM_REG_ITM_LOCKSREG_PRESENT(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// ITM_PID4 - Peripheral Identification Register 4
+//
+//*****************************************************************************
+// Peripheral Identification 4.
+#define AM_REG_ITM_PID4_PID4_S                       0
+#define AM_REG_ITM_PID4_PID4_M                       0xFFFFFFFF
+#define AM_REG_ITM_PID4_PID4(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_PID5 - Peripheral Identification Register 5
+//
+//*****************************************************************************
+// Peripheral Identification 5.
+#define AM_REG_ITM_PID5_PID5_S                       0
+#define AM_REG_ITM_PID5_PID5_M                       0xFFFFFFFF
+#define AM_REG_ITM_PID5_PID5(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_PID6 - Peripheral Identification Register 6
+//
+//*****************************************************************************
+// Peripheral Identification 6.
+#define AM_REG_ITM_PID6_PID6_S                       0
+#define AM_REG_ITM_PID6_PID6_M                       0xFFFFFFFF
+#define AM_REG_ITM_PID6_PID6(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_PID7 - Peripheral Identification Register 7
+//
+//*****************************************************************************
+// Peripheral Identification 7.
+#define AM_REG_ITM_PID7_PID7_S                       0
+#define AM_REG_ITM_PID7_PID7_M                       0xFFFFFFFF
+#define AM_REG_ITM_PID7_PID7(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_PID0 - Peripheral Identification Register 0
+//
+//*****************************************************************************
+// Peripheral Identification 0.
+#define AM_REG_ITM_PID0_PID0_S                       0
+#define AM_REG_ITM_PID0_PID0_M                       0xFFFFFFFF
+#define AM_REG_ITM_PID0_PID0(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_PID1 - Peripheral Identification Register 1
+//
+//*****************************************************************************
+// Peripheral Identification 1.
+#define AM_REG_ITM_PID1_PID1_S                       0
+#define AM_REG_ITM_PID1_PID1_M                       0xFFFFFFFF
+#define AM_REG_ITM_PID1_PID1(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_PID2 - Peripheral Identification Register 2
+//
+//*****************************************************************************
+// Peripheral Identification 2.
+#define AM_REG_ITM_PID2_PID2_S                       0
+#define AM_REG_ITM_PID2_PID2_M                       0xFFFFFFFF
+#define AM_REG_ITM_PID2_PID2(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_PID3 - Peripheral Identification Register 3
+//
+//*****************************************************************************
+// Peripheral Identification 3.
+#define AM_REG_ITM_PID3_PID3_S                       0
+#define AM_REG_ITM_PID3_PID3_M                       0xFFFFFFFF
+#define AM_REG_ITM_PID3_PID3(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_CID0 - Component Identification Register 1
+//
+//*****************************************************************************
+// Component Identification 1.
+#define AM_REG_ITM_CID0_CID0_S                       0
+#define AM_REG_ITM_CID0_CID0_M                       0xFFFFFFFF
+#define AM_REG_ITM_CID0_CID0(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_CID1 - Component Identification Register 1
+//
+//*****************************************************************************
+// Component Identification 1.
+#define AM_REG_ITM_CID1_CID1_S                       0
+#define AM_REG_ITM_CID1_CID1_M                       0xFFFFFFFF
+#define AM_REG_ITM_CID1_CID1(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_CID2 - Component Identification Register 2
+//
+//*****************************************************************************
+// Component Identification 2.
+#define AM_REG_ITM_CID2_CID2_S                       0
+#define AM_REG_ITM_CID2_CID2_M                       0xFFFFFFFF
+#define AM_REG_ITM_CID2_CID2(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// ITM_CID3 - Component Identification Register 3
+//
+//*****************************************************************************
+// Component Identification 3.
+#define AM_REG_ITM_CID3_CID3_S                       0
+#define AM_REG_ITM_CID3_CID3_M                       0xFFFFFFFF
+#define AM_REG_ITM_CID3_CID3(n)                      (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+#endif // AM_REG_ITM_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h b/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h
new file mode 100644
index 0000000000..61560dc099
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h
@@ -0,0 +1,215 @@
+//*****************************************************************************
+//
+//  am_reg_jedec.h
+//! @file
+//!
+//! @brief Register macros for the JEDEC module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_JEDEC_H
+#define AM_REG_JEDEC_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_JEDEC_NUM_MODULES                     1
+#define AM_REG_JEDECn(n) \
+    (REG_JEDEC_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_JEDEC_PID4_O                          0xF0000FD0
+#define AM_REG_JEDEC_PID5_O                          0xF0000FD4
+#define AM_REG_JEDEC_PID6_O                          0xF0000FD8
+#define AM_REG_JEDEC_PID7_O                          0xF0000FDC
+#define AM_REG_JEDEC_PID0_O                          0xF0000FE0
+#define AM_REG_JEDEC_PID1_O                          0xF0000FE4
+#define AM_REG_JEDEC_PID2_O                          0xF0000FE8
+#define AM_REG_JEDEC_PID3_O                          0xF0000FEC
+#define AM_REG_JEDEC_CID0_O                          0xF0000FF0
+#define AM_REG_JEDEC_CID1_O                          0xF0000FF4
+#define AM_REG_JEDEC_CID2_O                          0xF0000FF8
+#define AM_REG_JEDEC_CID3_O                          0xF0000FFC
+
+//*****************************************************************************
+//
+// JEDEC_PID4 - JEP Continuation Register
+//
+//*****************************************************************************
+// Contains the JEP Continuation bits.
+#define AM_REG_JEDEC_PID4_JEPCONT_S                  0
+#define AM_REG_JEDEC_PID4_JEPCONT_M                  0x0000000F
+#define AM_REG_JEDEC_PID4_JEPCONT(n)                 (((uint32_t)(n) << 0) & 0x0000000F)
+
+//*****************************************************************************
+//
+// JEDEC_PID5 - JEP reserved Register
+//
+//*****************************************************************************
+// Contains the value of 0x00000000.
+#define AM_REG_JEDEC_PID5_VALUE_S                    0
+#define AM_REG_JEDEC_PID5_VALUE_M                    0xFFFFFFFF
+#define AM_REG_JEDEC_PID5_VALUE(n)                   (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// JEDEC_PID6 - JEP reserved Register
+//
+//*****************************************************************************
+// Contains the value of 0x00000000.
+#define AM_REG_JEDEC_PID6_VALUE_S                    0
+#define AM_REG_JEDEC_PID6_VALUE_M                    0xFFFFFFFF
+#define AM_REG_JEDEC_PID6_VALUE(n)                   (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// JEDEC_PID7 - JEP reserved Register
+//
+//*****************************************************************************
+// Contains the value of 0x00000000.
+#define AM_REG_JEDEC_PID7_VALUE_S                    0
+#define AM_REG_JEDEC_PID7_VALUE_M                    0xFFFFFFFF
+#define AM_REG_JEDEC_PID7_VALUE(n)                   (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// JEDEC_PID0 - Ambiq Partnum low byte
+//
+//*****************************************************************************
+// Contains the low 8 bits of the Ambiq Micro device part number.
+#define AM_REG_JEDEC_PID0_PNL8_S                     0
+#define AM_REG_JEDEC_PID0_PNL8_M                     0x000000FF
+#define AM_REG_JEDEC_PID0_PNL8(n)                    (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble.
+//
+//*****************************************************************************
+// Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID
+// is therefore 0x9B.
+#define AM_REG_JEDEC_PID1_JEPIDL_S                   4
+#define AM_REG_JEDEC_PID1_JEPIDL_M                   0x000000F0
+#define AM_REG_JEDEC_PID1_JEPIDL(n)                  (((uint32_t)(n) << 4) & 0x000000F0)
+
+// Contains the high 4 bits of the Ambiq Micro device part number.
+#define AM_REG_JEDEC_PID1_PNH4_S                     0
+#define AM_REG_JEDEC_PID1_PNH4_M                     0x0000000F
+#define AM_REG_JEDEC_PID1_PNH4(n)                    (((uint32_t)(n) << 0) & 0x0000000F)
+
+//*****************************************************************************
+//
+// JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble
+//
+//*****************************************************************************
+// Contains the high 4 bits of the Ambiq Micro CHIPREV (see also
+// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
+// chip.
+#define AM_REG_JEDEC_PID2_CHIPREVH4_S                4
+#define AM_REG_JEDEC_PID2_CHIPREVH4_M                0x000000F0
+#define AM_REG_JEDEC_PID2_CHIPREVH4(n)               (((uint32_t)(n) << 4) & 0x000000F0)
+
+// Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this
+// field is hard-coded to 1. The full JEPID is therefore 0x9B.
+#define AM_REG_JEDEC_PID2_JEPIDH_S                   0
+#define AM_REG_JEDEC_PID2_JEPIDH_M                   0x0000000F
+#define AM_REG_JEDEC_PID2_JEPIDH(n)                  (((uint32_t)(n) << 0) & 0x0000000F)
+
+//*****************************************************************************
+//
+// JEDEC_PID3 - Ambiq chip revision high-nibble.
+//
+//*****************************************************************************
+// Contains the low 4 bits of the Ambiq Micro CHIPREV (see also
+// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
+// chip.
+#define AM_REG_JEDEC_PID3_CHIPREVL4_S                4
+#define AM_REG_JEDEC_PID3_CHIPREVL4_M                0x000000F0
+#define AM_REG_JEDEC_PID3_CHIPREVL4(n)               (((uint32_t)(n) << 4) & 0x000000F0)
+
+// This field is hard-coded to 0x0.
+#define AM_REG_JEDEC_PID3_ZERO_S                     0
+#define AM_REG_JEDEC_PID3_ZERO_M                     0x0000000F
+#define AM_REG_JEDEC_PID3_ZERO(n)                    (((uint32_t)(n) << 0) & 0x0000000F)
+
+//*****************************************************************************
+//
+// JEDEC_CID0 - Coresight ROM Table.
+//
+//*****************************************************************************
+// Coresight ROM Table, CID0.
+#define AM_REG_JEDEC_CID0_CID_S                      0
+#define AM_REG_JEDEC_CID0_CID_M                      0x000000FF
+#define AM_REG_JEDEC_CID0_CID(n)                     (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// JEDEC_CID1 - Coresight ROM Table.
+//
+//*****************************************************************************
+// Coresight ROM Table, CID1.
+#define AM_REG_JEDEC_CID1_CID_S                      0
+#define AM_REG_JEDEC_CID1_CID_M                      0x000000FF
+#define AM_REG_JEDEC_CID1_CID(n)                     (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// JEDEC_CID2 - Coresight ROM Table.
+//
+//*****************************************************************************
+// Coresight ROM Table, CID2.
+#define AM_REG_JEDEC_CID2_CID_S                      0
+#define AM_REG_JEDEC_CID2_CID_M                      0x000000FF
+#define AM_REG_JEDEC_CID2_CID(n)                     (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// JEDEC_CID3 - Coresight ROM Table.
+//
+//*****************************************************************************
+// Coresight ROM Table, CID3.
+#define AM_REG_JEDEC_CID3_CID_S                      0
+#define AM_REG_JEDEC_CID3_CID_M                      0x000000FF
+#define AM_REG_JEDEC_CID3_CID(n)                     (((uint32_t)(n) << 0) & 0x000000FF)
+
+#endif // AM_REG_JEDEC_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h b/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h
new file mode 100644
index 0000000000..e9662958c1
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h
@@ -0,0 +1,312 @@
+//*****************************************************************************
+//
+//! @file am_reg_macros.h
+//!
+//! @brief Helper macros for using hardware registers.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_REG_MACROS_H
+#define AM_REG_MACROS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Include the inline assembly macros.
+//
+//*****************************************************************************
+#include "am_reg_macros_asm.h"
+
+//*****************************************************************************
+//
+// High-level Helper Macros.
+//
+// Usage:
+//
+// For direct 32-bit access to a register, use AM_REGVAL:
+//      AM_REGVAL(REG_VCOMP_BASEADDR + AM_VCOMP_VCMPCFG_O) |= 0xDEADBEEF;
+//
+// The AM_REG macro can also be used as a shorthand version of AM_REGVAL:
+//      AM_REG(VCOMP, VCMPCFG) |= 0xDEADBEEF;
+//
+// The AM_REGn macro is used for accessing registers of peripherals with
+// multiple instances, such as IOMSTR.
+//      AM_REGn(IOMSTR, 1, CLKCFG) |= 0xDEADBEEF;
+//
+// To write to a specific bitfield within a register, use AM_BFW or AM_BFWn:
+//      AM_BFW(CTIMER, 0, CTCTRL0, TMRB0FN, 0x3);
+//
+// To read a field, use AM_BFR or AM_BFRn:
+//      ui32Timer0Fn = AM_BFR((CTIMER, 0, CTCTRL0, TMRB0FN);
+//
+// Note:
+//
+// AM_REGn, AM_BFW and AM_BFR are concatenation-based, which means that
+// standalone macro definitions should not be used for the 'module', 'reg', and
+// 'field' arguments.All macro names in the various peripheral header files are
+// written in one of the following forms:
+//      - AM_REG_##module_reg_O
+//      - AM_REG_##module_reg_field_S
+//      - AM_REG_##module_reg_field_M
+//
+// The "module", "reg" and "field" fragments may be used as valid arguments to
+// the AM_REGn, AM_BFW, and AM_BFR macros, all of which are able to perform the
+// necessary concatenation operations to reconstruct the full macros and look
+// up the appropriate base address for the instance number given. For
+// peripherals with only one instance, use instance number 0.
+//
+// The AM_REGVAL macro does not perform any concatenation operations, so the
+// complete macro name (including any suffix) must be specified.
+//
+//*****************************************************************************
+#define AM_REGVAL(x)               (*((volatile uint32_t *)(x)))
+#define AM_REGVAL_FLOAT(x)         (*((volatile float *)(x)))
+
+//*****************************************************************************
+//
+// Register access macros for single-instance modules
+// AM_REG  - Write a register of a module.
+// AM_BFW  - Write a value to a bitfield of a register.
+// AM_BFWe - Use a defined enum value to write a value to a bitfield.
+// AM_BFR  - Read a bitfield value from a register.
+// AM_BFM  - Read and mask a bitfield, but leave the value in its bit position.
+//           (Useful for comparing with enums.)
+//
+//*****************************************************************************
+#define AM_REG(module, reg)                                                   \
+    AM_REGn(module, 0, reg)
+
+#define AM_BFW(module, reg, field, value)                                     \
+    AM_BFWn(module, 0, reg, field, value)
+
+#define AM_BFWe(module, reg, field, enumval)                                  \
+    AM_BFWen(module, 0, reg, field, enumval)
+
+#define AM_BFR(module, reg, field)                                            \
+    AM_BFRn(module, 0, reg, field)
+
+#define AM_BFM(module, reg, field)                                            \
+    AM_BFMn(module, 0, reg, field)
+
+#define AM_BFV(module, reg, field, value)                                     \
+    (((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) &           \
+     AM_REG_##module##_##reg##_##field##_M)
+
+#define AM_BFX(module, reg, field, value)                                     \
+    (((uint32_t)(value) & AM_REG_##module##_##reg##_##field##_M) >>           \
+     AM_REG_##module##_##reg##_##field##_S)
+
+
+//*****************************************************************************
+//
+// Register access macros for multi-instance modules
+// AM_REGn - Write a register of a multiple instance module.
+// AM_BFWn - Write a value to a bitfield of a register in a multiple instance.
+// AM_BFWen - Use a defined enum value to write a value to a bitfield of a
+//            register in a multiple instance.
+// AM_BFRn - Read a bitfield value from a register in a multiple instance.
+// AM_BFMn - Read a bitfield, but leave the value in its bitfield position.
+// AM_BFMn - Read and mask a bitfield, but leave the value in its bit position.
+//           (Useful for comparing with enums.)
+//
+//*****************************************************************************
+#define AM_REGn(module, instance, reg)                                        \
+    AM_REGVAL(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O)
+
+#define AM_BFWn(module, instance, reg, field, value)                          \
+    AM_REGn(module, instance, reg) =                                          \
+        (AM_BFV(module, reg, field, value) |                                  \
+         (AM_REGn(module, instance, reg) &                                    \
+          (~AM_REG_##module##_##reg##_##field##_M)))
+
+#define AM_BFWen(module, instance, reg, field, enumval)                       \
+    AM_REGn(module, instance, reg) =                                          \
+        (AM_REG_##module##_##reg##_##field##_##enumval |                      \
+         (AM_REGn(module, instance, reg) &                                    \
+          (~AM_REG_##module##_##reg##_##field##_M)))
+
+#define AM_BFRn(module, instance, reg, field)                                 \
+    AM_BFX(module, reg, field, AM_REGn(module, instance, reg))
+
+#define AM_BFMn(module, instance, reg, field)                                 \
+    (AM_REGn(module, instance, reg) & AM_REG_##module##_##reg##_##field##_M)
+
+//*****************************************************************************
+//
+// "Atomic" register access macros - use when a read-modify-write is required.
+//
+// These macros will be slower than the normal macros, but they will also
+// guarantee threadsafe hardware access.
+//
+// These macros require a nesting-friendly critical section implementation. If
+// you are using the HAL, you can use the default definitions below. If not,
+// you will need to supply your own.
+//
+// Atomic register access macros usage:
+// AM_REGa      - Write a register of a single instance module. Provide operator
+//                (&,|,etc) to perform that operation on the reg using value, or
+//                no operator to simply write the value atomically.
+// AM_REGa_SET  - Set bits in a single instance module according to the mask.
+// AM_REGa_CLR  - Clear bits in a single instance module according to the mask.
+// AM_REGna     - Multiple module version of AM_REGa.
+// AM_REGna_SET - Multiple instance version of AM_REGa_SET.
+// AM_REGna_CLR - Multiple instance version of AM_REGa_CLR.
+// AM_BFWa   - Write a value to a register bitfield.
+// AM_BFWae  - Use a defined enum value to write a value to a bitfield.
+// AM_BFWan  - Write a value to a bitfield of a register in a multiple instance.
+// AM_BFWaen - Use a defined enum value to write a value to a bitfield of a
+//             register in a multiple instance.
+//
+//*****************************************************************************
+#ifndef AM_CRITICAL_BEGIN
+#define AM_CRITICAL_BEGIN   uint32_t ui32Primask = am_hal_interrupt_master_disable()
+#define AM_CRITICAL_END     am_hal_interrupt_master_set(ui32Primask)
+#endif
+
+#define AM_REGan(module, instance, reg, operator, value)                    \
+    AM_CRITICAL_BEGIN_ASM                                                   \
+    AM_REGn(module, instance, reg) operator##= (value);                     \
+    AM_CRITICAL_END_ASM
+
+#define AM_REGan_SET(module, instance, reg, mask)                           \
+    AM_CRITICAL_BEGIN_ASM                                                   \
+    AM_REGn(module, instance, reg) |= (mask);                               \
+    AM_CRITICAL_END_ASM
+
+#define AM_REGan_CLR(module, instance, reg, mask)                           \
+    AM_CRITICAL_BEGIN_ASM                                                   \
+    AM_REGn(module, instance, reg) &= (~mask);                              \
+    AM_CRITICAL_END_ASM
+
+#define AM_REGa(module, reg, operator, value)                               \
+    AM_REGan(module, 0, reg, operator, value)
+
+#define AM_REGa_CLR(module, reg, mask)                                      \
+    AM_REGan_CLR(module, 0, reg, mask)
+
+#define AM_REGa_SET(module, reg, mask)                                      \
+    AM_REGan_SET(module, 0, reg, mask)
+
+#define AM_BFWa(module, reg, field, value)                                  \
+    AM_CRITICAL_BEGIN_ASM                                                   \
+    AM_BFW(module, reg, field, value);                                      \
+    AM_CRITICAL_END_ASM
+
+#define AM_BFWae(module, reg, field, enumval)                               \
+    AM_CRITICAL_BEGIN_ASM                                                   \
+    AM_BFWe(module, reg, field, enumval);                                   \
+    AM_CRITICAL_END_ASM
+
+#define AM_BFWan(module, instance, reg, field, value)                       \
+    AM_CRITICAL_BEGIN_ASM                                                   \
+    AM_BFWn(module, instance, reg, field, enumval);                         \
+    AM_CRITICAL_END_ASM
+
+#define AM_BFWaen(module, instance, reg, field, enumval)                    \
+    AM_CRITICAL_BEGIN_ASM                                                   \
+    AM_BFWen(module, instance reg, field, enumval);                         \
+    AM_CRITICAL_END_ASM
+
+//*****************************************************************************
+//
+// Other helper Macros.
+//
+// Note: These macros make use of macro concatenation, so the '_S' or '_M'
+// suffix on a register bitfield macro should not be supplied by the user.
+// The macro will apply each suffix as needed.
+//
+//*****************************************************************************
+
+//
+// AM_ENUMX extracts a register bitfield enumeration to the bit 0 position,
+//  which makes it possible to use enums directly with existing macros such
+//  as AM_BFR() or AM_BFW().
+// Brief overview: bitfield enumerations are pre-shifted such that the defined
+//  value lines up with the bitfield.  This is convenient for many operations,
+//  but not so when using AM_BFR() to read the value of a register bitfield
+//  as AM_BFR() shifts the bitfield value to the bit 0 position.
+// Note that this type of bitfield extraction is Cortex efficient via the
+//  UBFX (unsigned bit field extract) instruction.
+//
+// Alternately, AM_BFM() can also be used.  AM_BFM() reads a register and masks
+//  the bitfield value (without shifting), thereby allowing  direct comparison
+//  with a defined enum.
+//
+// Examples:
+//  if  ( AM_BFR(CLKGEN, CCTRL, CORESEL) ==
+//        AM_ENUMX(CLKGEN, CCTRL, CORESEL, HFRC) )
+//
+//  or alternatively:
+//  if  ( AM_BFM(CLKGEN, CCTRL, CORESEL) == AM_REG_CLKGEN_CCTRL_CORESEL_HFRC )
+//
+#define AM_ENUMX(module, reg, field, enumname)                              \
+    ((AM_REG_##module##_##reg##_##field##_##enumname) >>                    \
+     (AM_REG_##module##_##reg##_##field##_S))
+
+//
+// AM_WRITE_SM performs a shift/mask operation to prepare the value 'x' to be
+// written to the register field 'field'.
+//
+// For example:
+// AM_REGVAL(ui32Base + AM_VCOMP_VCMP_CFG_O) |=
+//     AM_WRITE_SM(AM_VCOMP_VCMP_CFG_LVLSEL, ui32Value);
+//
+#define AM_WRITE_SM(field, x)      (((x) << field##_S) & field##_M)
+
+//
+// AM_READ_SM performs a shift/mask operation to make it easier to interpret
+// the value of a given bitfield. This is essentially the reverse of the
+// AM_WRITE_SM operation. In most cases, you will want to use the shorter
+// AM_BFR macro instead of this one.
+//
+// For example:
+// ui32Value = AM_READ_SM(AM_VCOMP_VCMP_CFG_NSEL,
+//                        AM_REGVAL(ui32Base + AM_VCOMP_VCMP_CFG_O));
+//
+#define AM_READ_SM(field, x)       (((x) & field##_M) >> field##_S)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_REG_MACROS_H
+
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h
new file mode 100644
index 0000000000..f02624d8e3
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h
@@ -0,0 +1,162 @@
+//*****************************************************************************
+//
+//! @file am_reg_macros_asm.h
+//!
+//! @brief Inline assembly macros. Initially for critical section handling in
+//! protecting hardware registers.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_REG_MACROS_ASM_H
+#define AM_REG_MACROS_ASM_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Critical section assembly macros
+//
+// These macros implement critical section protection using inline assembly
+// for various compilers.  They are intended to be used in other register
+// macros or directly in sections of code.
+//
+// Important usage note: These macros create a local scope and therefore MUST
+// be used in pairs.
+//
+//*****************************************************************************
+
+#if defined(__GNUC_STDC_INLINE__)
+//
+// GCC macros.
+//
+#define AM_CRITICAL_BEGIN_ASM                                               \
+    if ( 1 )                                                                \
+    {                                                                       \
+        volatile uint32_t ui32Primask_04172010;                             \
+        __asm("    mrs %0, PRIMASK" : "=r"(ui32Primask_04172010));          \
+        __asm("    cpsid i");
+
+#define AM_CRITICAL_END_ASM                                                 \
+        __asm("    msr PRIMASK, %0" : : "r"(ui32Primask_04172010));         \
+    }
+
+#elif defined(__ARMCC_VERSION)
+//
+// ARM/Keil macros.
+//
+#define AM_CRITICAL_BEGIN_ASM                                               \
+    if ( 1 )                                                                \
+    {                                                                       \
+        volatile uint32_t ui32Primask_04172010;                             \
+        __asm                                                               \
+        {                                                                   \
+            mrs     ui32Primask_04172010, PRIMASK;                          \
+            cpsid   i;                                                      \
+        }
+
+#define AM_CRITICAL_END_ASM                                                 \
+        __asm                                                               \
+        {                                                                   \
+            msr     PRIMASK, ui32Primask_04172010;                          \
+        }                                                                   \
+    }
+
+#elif defined(__IAR_SYSTEMS_ICC__)
+//
+// IAR macros.
+//
+#define AM_CRITICAL_BEGIN_ASM                                               \
+    if ( 1 )                                                                \
+    {                                                                       \
+        volatile uint32_t ui32Primask_04172010;                             \
+        __asm("    mrs %0, PRIMASK" : "=r"(ui32Primask_04172010));          \
+        __asm("    cpsid i");
+
+#define AM_CRITICAL_END_ASM                                                 \
+        __asm("    msr PRIMASK, %0" : : "r"(ui32Primask_04172010));         \
+    }
+#endif
+
+
+//*****************************************************************************
+//
+// A collection of some common inline assembly instructions / intrinsics.
+//
+//*****************************************************************************
+//
+// AM_ASM_BKPT(n)
+//
+#if     defined(__ARMCC_VERSION)
+#define     AM_ASM_BKPT(n)  __breakpoint(n)
+#elif   defined(__IAR_SYSTEMS_ICC__)
+#define     AM_ASM_BKPT(n)  asm("    bkpt "#n);
+#else
+#define     AM_ASM_BKPT(n)  __asm("    bkpt "#n);
+#endif
+
+//
+// AM_ASM_WFI
+//
+#if     defined(__ARMCC_VERSION)
+#define     AM_ASM_WFI      __wfi();
+#elif   defined(__IAR_SYSTEMS_ICC__)
+#define     AM_ASM_WFI      asm("    wfi");
+#else
+#define     AM_ASM_WFI      __asm("    wfi");
+#endif
+
+//
+// AM_ASM_NOP
+//
+#if     defined(__ARMCC_VERSION)
+#define     AM_ASM_NOP      __nop();
+#elif   defined(__IAR_SYSTEMS_ICC__)
+#define     AM_ASM_NOP      asm("    nop");
+#else
+#define     AM_ASM_NOP      __asm("    nop");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_REG_MACROS_ASM_H
+
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h
new file mode 100644
index 0000000000..ae066bf85d
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h
@@ -0,0 +1,607 @@
+//*****************************************************************************
+//
+//  am_reg_mcuctrl.h
+//! @file
+//!
+//! @brief Register macros for the MCUCTRL module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_MCUCTRL_H
+#define AM_REG_MCUCTRL_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_MCUCTRL_NUM_MODULES                   1
+#define AM_REG_MCUCTRLn(n) \
+    (REG_MCUCTRL_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_MCUCTRL_CHIP_INFO_O                   0x00000000
+#define AM_REG_MCUCTRL_CHIPID0_O                     0x00000004
+#define AM_REG_MCUCTRL_CHIPID1_O                     0x00000008
+#define AM_REG_MCUCTRL_CHIPREV_O                     0x0000000C
+#define AM_REG_MCUCTRL_VENDORID_O                    0x00000010
+#define AM_REG_MCUCTRL_DEBUGGER_O                    0x00000014
+#define AM_REG_MCUCTRL_BUCK_O                        0x00000060
+#define AM_REG_MCUCTRL_BUCK3_O                       0x00000068
+#define AM_REG_MCUCTRL_LDOREG1_O                     0x00000080
+#define AM_REG_MCUCTRL_LDOREG3_O                     0x00000088
+#define AM_REG_MCUCTRL_BODPORCTRL_O                  0x00000100
+#define AM_REG_MCUCTRL_ADCPWRDLY_O                   0x00000104
+#define AM_REG_MCUCTRL_ADCCAL_O                      0x0000010C
+#define AM_REG_MCUCTRL_ADCBATTLOAD_O                 0x00000110
+#define AM_REG_MCUCTRL_BUCKTRIM_O                    0x00000114
+#define AM_REG_MCUCTRL_BOOTLOADERLOW_O               0x000001A0
+#define AM_REG_MCUCTRL_SHADOWVALID_O                 0x000001A4
+#define AM_REG_MCUCTRL_ICODEFAULTADDR_O              0x000001C0
+#define AM_REG_MCUCTRL_DCODEFAULTADDR_O              0x000001C4
+#define AM_REG_MCUCTRL_SYSFAULTADDR_O                0x000001C8
+#define AM_REG_MCUCTRL_FAULTSTATUS_O                 0x000001CC
+#define AM_REG_MCUCTRL_FAULTCAPTUREEN_O              0x000001D0
+#define AM_REG_MCUCTRL_DBGR1_O                       0x00000200
+#define AM_REG_MCUCTRL_DBGR2_O                       0x00000204
+#define AM_REG_MCUCTRL_PMUENABLE_O                   0x00000220
+#define AM_REG_MCUCTRL_TPIUCTRL_O                    0x00000250
+
+//*****************************************************************************
+//
+// Key values.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// MCUCTRL_CHIP_INFO - Chip Information Register
+//
+//*****************************************************************************
+// BCD part number.
+#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_S           0
+#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_M           0xFFFFFFFF
+#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM(n)          (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO2     0x03000000
+#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO      0x01000000
+#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_PN_M        0xFF000000
+
+//*****************************************************************************
+//
+// MCUCTRL_CHIPID0 - Unique Chip ID 0
+//
+//*****************************************************************************
+// Unique chip ID 0.
+#define AM_REG_MCUCTRL_CHIPID0_VALUE_S               0
+#define AM_REG_MCUCTRL_CHIPID0_VALUE_M               0xFFFFFFFF
+#define AM_REG_MCUCTRL_CHIPID0_VALUE(n)              (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+#define AM_REG_MCUCTRL_CHIPID0_VALUE_APOLLO2         0x00000000
+
+//*****************************************************************************
+//
+// MCUCTRL_CHIPID1 - Unique Chip ID 1
+//
+//*****************************************************************************
+// Unique chip ID 1.
+#define AM_REG_MCUCTRL_CHIPID1_VALUE_S               0
+#define AM_REG_MCUCTRL_CHIPID1_VALUE_M               0xFFFFFFFF
+#define AM_REG_MCUCTRL_CHIPID1_VALUE(n)              (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+#define AM_REG_MCUCTRL_CHIPID1_VALUE_APOLLO2         0x00000000
+
+//*****************************************************************************
+//
+// MCUCTRL_CHIPREV - Chip Revision
+//
+//*****************************************************************************
+// Major Revision ID.
+#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_S              4
+#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_M              0x000000F0
+#define AM_REG_MCUCTRL_CHIPREV_REVMAJ(n)             (((uint32_t)(n) << 4) & 0x000000F0)
+#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_B              0x00000020
+#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_A              0x00000010
+
+// Minor Revision ID.
+#define AM_REG_MCUCTRL_CHIPREV_REVMIN_S              0
+#define AM_REG_MCUCTRL_CHIPREV_REVMIN_M              0x0000000F
+#define AM_REG_MCUCTRL_CHIPREV_REVMIN(n)             (((uint32_t)(n) << 0) & 0x0000000F)
+#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0           0x00000000
+
+//*****************************************************************************
+//
+// MCUCTRL_VENDORID - Unique Vendor ID
+//
+//*****************************************************************************
+// Unique Vendor ID
+#define AM_REG_MCUCTRL_VENDORID_VALUE_S              0
+#define AM_REG_MCUCTRL_VENDORID_VALUE_M              0xFFFFFFFF
+#define AM_REG_MCUCTRL_VENDORID_VALUE(n)             (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+#define AM_REG_MCUCTRL_VENDORID_VALUE_AMBIQ          0x414D4251
+
+//*****************************************************************************
+//
+// MCUCTRL_DEBUGGER - Debugger Access Control
+//
+//*****************************************************************************
+// Lockout of debugger (SWD).
+#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT_S            0
+#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT_M            0x00000001
+#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT(n)           (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// MCUCTRL_BUCK - Analog Buck Control
+//
+//*****************************************************************************
+// Reset control override for Mem Buck; 0=enabled, 1=reset; Value is propagated
+// only when the BUCKSWE bit is active, otherwise contrl is from the power
+// control module.
+#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST_S             7
+#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST_M             0x00000080
+#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST(n)            (((uint32_t)(n) << 7) & 0x00000080)
+
+// Reset control override for Core Buck; 0=enabled, 1=reset; Value is propagated
+// only when the BUCKSWE bit is active, otherwise control is from the power
+// control module.
+#define AM_REG_MCUCTRL_BUCK_COREBUCKRST_S            6
+#define AM_REG_MCUCTRL_BUCK_COREBUCKRST_M            0x00000040
+#define AM_REG_MCUCTRL_BUCK_COREBUCKRST(n)           (((uint32_t)(n) << 6) & 0x00000040)
+
+// Not used.  Additional control of buck is available in the power control
+// module
+#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM_S             5
+#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM_M             0x00000020
+#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM(n)            (((uint32_t)(n) << 5) & 0x00000020)
+
+// Memory buck power down override. 1=Powered Down; 0=Enabled; Value is
+// propagated only when the BUCKSWE bit is active, otherwise control is from the
+// power control module.
+#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_S             4
+#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_M             0x00000010
+#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD(n)            (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_EN            0x00000000
+
+// HFRC clkgen bit 0 override. When set, this will override to 0 bit 0 of the
+// hfrc_freq_clkgen internal bus (see internal Shelby-1473)
+#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA_S           3
+#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA_M           0x00000008
+#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA(n)          (((uint32_t)(n) << 3) & 0x00000008)
+
+// Core buck power down override. 1=Powered Down; 0=Enabled; Value is propagated
+// only when the BUCKSWE bit is active, otherwise control is from the power
+// control module.
+#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_S            2
+#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_M            0x00000004
+#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD(n)           (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_EN           0x00000000
+
+// Not used.  Additional control of buck is available in the power control
+// module
+#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE_S            1
+#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE_M            0x00000002
+#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE(n)           (((uint32_t)(n) << 1) & 0x00000002)
+
+// Buck Register Software Override Enable.  This will enable the override values
+// for MEMBUCKPWD, COREBUCKPWD, COREBUCKRST, MEMBUCKRST, all to be propagated to
+// the control logic, instead of the normal power control module signal.  Note -
+// Must take care to have correct value for ALL the register bits when this SWE
+// is enabled.
+#define AM_REG_MCUCTRL_BUCK_BUCKSWE_S                0
+#define AM_REG_MCUCTRL_BUCK_BUCKSWE_M                0x00000001
+#define AM_REG_MCUCTRL_BUCK_BUCKSWE(n)               (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_BUCK_BUCKSWE_OVERRIDE_DIS     0x00000000
+#define AM_REG_MCUCTRL_BUCK_BUCKSWE_OVERRIDE_EN      0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_BUCK3 - Buck control reg 3
+//
+//*****************************************************************************
+// MEM Buck low TON trim value
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON_S          18
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON_M          0x003C0000
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON(n)         (((uint32_t)(n) << 18) & 0x003C0000)
+
+// MEM Buck burst enable 0=disable, 0=disabled, 1=enable.
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN_S        17
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN_M        0x00020000
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN(n)       (((uint32_t)(n) << 17) & 0x00020000)
+
+// Memory buck zero crossing trim value
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM_S         13
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM_M         0x0001E000
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM(n)        (((uint32_t)(n) << 13) & 0x0001E000)
+
+// Hysterisis trim for mem buck
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM_S       11
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM_M       0x00001800
+#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM(n)      (((uint32_t)(n) << 11) & 0x00001800)
+
+// Core Buck low TON trim value
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON_S         7
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON_M         0x00000780
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON(n)        (((uint32_t)(n) << 7) & 0x00000780)
+
+// Core Buck burst enable. 0=disabled, 1=enabled
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN_S       6
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN_M       0x00000040
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN(n)      (((uint32_t)(n) << 6) & 0x00000040)
+
+// Core buck  zero crossing trim value
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM_S        2
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM_M        0x0000003C
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM(n)       (((uint32_t)(n) << 2) & 0x0000003C)
+
+// Hysterisis trim for core buck
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM_S      0
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM_M      0x00000003
+#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM(n)     (((uint32_t)(n) << 0) & 0x00000003)
+
+//*****************************************************************************
+//
+// MCUCTRL_LDOREG1 - Analog LDO Reg 1
+//
+//*****************************************************************************
+// CORE LDO IBIAS Trim
+#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM_S       20
+#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM_M       0x00100000
+#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM(n)      (((uint32_t)(n) << 20) & 0x00100000)
+
+// CORE LDO Low Power Trim
+#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM_S       14
+#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM_M       0x000FC000
+#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM(n)      (((uint32_t)(n) << 14) & 0x000FC000)
+
+// CORE LDO tempco trim (R3).
+#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3_S       10
+#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3_M       0x00003C00
+#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3(n)      (((uint32_t)(n) << 10) & 0x00003C00)
+
+// CORE LDO Active mode ouput trim (R1).
+#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1_S       0
+#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1_M       0x000003FF
+#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1(n)      (((uint32_t)(n) << 0) & 0x000003FF)
+
+//*****************************************************************************
+//
+// MCUCTRL_LDOREG3 - LDO Control Register 3
+//
+//*****************************************************************************
+// MEM LDO active mode trim (R1).
+#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1_S        12
+#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1_M        0x0003F000
+#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1(n)       (((uint32_t)(n) << 12) & 0x0003F000)
+
+// MEM LDO TRIM for low power mode with ADC active
+#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM_S     6
+#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM_M     0x00000FC0
+#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM(n)    (((uint32_t)(n) << 6) & 0x00000FC0)
+
+// MEM LDO TRIM for low power mode with ADC inactive
+#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM_S        0
+#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM_M        0x0000003F
+#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM(n)       (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// MCUCTRL_BODPORCTRL - BOD and PDR control Register
+//
+//*****************************************************************************
+// BOD External Reference Select.
+#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_S     3
+#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_M     0x00000008
+#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL(n)    (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_SELECT 0x00000008
+
+// PDR External Reference Select.
+#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_S     2
+#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_M     0x00000004
+#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL(n)    (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_SELECT 0x00000004
+
+// BOD Power Down.
+#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_S           1
+#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_M           0x00000002
+#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD(n)          (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_PWR_DN      0x00000002
+
+// PDR Power Down.
+#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_S           0
+#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_M           0x00000001
+#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR(n)          (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_PWR_DN      0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_ADCPWRDLY - ADC Power Up Delay Control
+//
+//*****************************************************************************
+// ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL =
+// 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.
+#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1_S           8
+#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1_M           0x0000FF00
+#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1(n)          (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for
+// ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.
+#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0_S           0
+#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0_M           0x000000FF
+#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0(n)          (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// MCUCTRL_ADCCAL - ADC Calibration Control
+//
+//*****************************************************************************
+// Status for ADC Calibration
+#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_S        1
+#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_M        0x00000002
+#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED(n)       (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE    0x00000000
+#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE     0x00000002
+
+// Run ADC Calibration on initial power up sequence
+#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_S           0
+#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_M           0x00000001
+#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP(n)          (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_DIS         0x00000000
+#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_EN          0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_ADCBATTLOAD - ADC Battery Load Enable
+//
+//*****************************************************************************
+// Enable the ADC battery load resistor
+#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_S        0
+#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_M        0x00000001
+#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD(n)       (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS      0x00000000
+#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_EN       0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_BUCKTRIM - Trim settings for Core and Mem buck modules
+//
+//*****************************************************************************
+// RESERVED.
+#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2_S              24
+#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2_M              0x3F000000
+#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2(n)             (((uint32_t)(n) << 24) & 0x3F000000)
+
+// Core Buck voltage output trim bits[9:6]. Concatenate with field COREBUCKR1_LO
+// for the full trim value.
+#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI_S      16
+#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI_M      0x000F0000
+#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI(n)     (((uint32_t)(n) << 16) & 0x000F0000)
+
+// Core Buck voltage output trim bits[5:0], Concatenate with field COREBUCKR1_HI
+// for the full trim value.
+#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO_S      8
+#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO_M      0x00003F00
+#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO(n)     (((uint32_t)(n) << 8) & 0x00003F00)
+
+// Trim values for BUCK regulator.
+#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1_S          0
+#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1_M          0x0000003F
+#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1(n)         (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// MCUCTRL_BOOTLOADERLOW - Determines whether the bootloader code is visible at
+// address 0x00000000
+//
+//*****************************************************************************
+// Determines whether the bootloader code is visible at address 0x00000000 or
+// not.
+#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_S         0
+#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_M         0x00000001
+#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE(n)        (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_ADDR0     0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_SHADOWVALID - Register to indicate whether the shadow registers have
+// been successfully loaded from the Flash Information Space.
+//
+//*****************************************************************************
+// Indicates whether the bootloader should sleep or deep sleep if no image
+// loaded.
+#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_S       1
+#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_M       0x00000002
+#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP(n)      (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_DEEPSLEEP 0x00000002
+
+// Indicates whether the shadow registers contain valid data from the Flash
+// Information Space.
+#define AM_REG_MCUCTRL_SHADOWVALID_VALID_S           0
+#define AM_REG_MCUCTRL_SHADOWVALID_VALID_M           0x00000001
+#define AM_REG_MCUCTRL_SHADOWVALID_VALID(n)          (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_SHADOWVALID_VALID_VALID       0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_ICODEFAULTADDR - ICODE bus address which was present when a bus fault
+// occurred.
+//
+//*****************************************************************************
+// The ICODE bus address observed when a Bus Fault occurred. Once an address is
+// captured in this field, it is held until the corresponding Fault Observed bit
+// is cleared in the FAULTSTATUS register.
+#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR_S         0
+#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR_M         0xFFFFFFFF
+#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR(n)        (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// MCUCTRL_DCODEFAULTADDR - DCODE bus address which was present when a bus fault
+// occurred.
+//
+//*****************************************************************************
+// The DCODE bus address observed when a Bus Fault occurred. Once an address is
+// captured in this field, it is held until the corresponding Fault Observed bit
+// is cleared in the FAULTSTATUS register.
+#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR_S         0
+#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR_M         0xFFFFFFFF
+#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR(n)        (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// MCUCTRL_SYSFAULTADDR - System bus address which was present when a bus fault
+// occurred.
+//
+//*****************************************************************************
+// SYS bus address observed when a Bus Fault occurred. Once an address is
+// captured in this field, it is held until the corresponding Fault Observed bit
+// is cleared in the FAULTSTATUS register.
+#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR_S           0
+#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR_M           0xFFFFFFFF
+#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR(n)          (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// MCUCTRL_FAULTSTATUS - Reflects the status of the bus decoders' fault
+// detection. Any write to this register will clear all of the status bits
+// within the register.
+//
+//*****************************************************************************
+// SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and
+// the SYSFAULTADDR register will contain the bus address which generated the
+// fault.
+#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_S             2
+#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_M             0x00000004
+#define AM_REG_MCUCTRL_FAULTSTATUS_SYS(n)            (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_NOFAULT       0x00000000
+#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_FAULT         0x00000004
+
+// DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected,
+// and the DCODEFAULTADDR register will contain the bus address which generated
+// the fault.
+#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_S           1
+#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_M           0x00000002
+#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE(n)          (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_NOFAULT     0x00000000
+#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_FAULT       0x00000002
+
+// The ICODE Bus Decoder Fault Detected bit. When set, a fault has been
+// detected, and the ICODEFAULTADDR register will contain the bus address which
+// generated the fault.
+#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_S           0
+#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_M           0x00000001
+#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE(n)          (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_NOFAULT     0x00000000
+#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_FAULT       0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_FAULTCAPTUREEN - Enable the fault capture registers
+//
+//*****************************************************************************
+// Fault Capture Enable field. When set, the Fault Capture monitors are enabled
+// and addresses which generate a hard fault are captured into the FAULTADDR
+// registers.
+#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_S       0
+#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_M       0x00000001
+#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE(n)      (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_DIS     0x00000000
+#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_EN      0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_DBGR1 - Read-only debug register 1
+//
+//*****************************************************************************
+// Read-only register for communication validation
+#define AM_REG_MCUCTRL_DBGR1_ONETO8_S                0
+#define AM_REG_MCUCTRL_DBGR1_ONETO8_M                0xFFFFFFFF
+#define AM_REG_MCUCTRL_DBGR1_ONETO8(n)               (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// MCUCTRL_DBGR2 - Read-only debug register 2
+//
+//*****************************************************************************
+// Read-only register for communication validation
+#define AM_REG_MCUCTRL_DBGR2_COOLCODE_S              0
+#define AM_REG_MCUCTRL_DBGR2_COOLCODE_M              0xFFFFFFFF
+#define AM_REG_MCUCTRL_DBGR2_COOLCODE(n)             (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// MCUCTRL_PMUENABLE - Control bit to enable/disable the PMU
+//
+//*****************************************************************************
+// PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the
+// lowest power consuming Deep Sleep mode upon execution of a WFI instruction
+// (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When
+// cleared, regardless of the requested sleep mode, the PMU will not enter the
+// lowest power Deep Sleep mode, instead entering the Sleep mode.
+#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_S            0
+#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_M            0x00000001
+#define AM_REG_MCUCTRL_PMUENABLE_ENABLE(n)           (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_DIS          0x00000000
+#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_EN           0x00000001
+
+//*****************************************************************************
+//
+// MCUCTRL_TPIUCTRL - TPIU Control Register. Determines the clock enable and
+// frequency for the M4's TPIU interface.
+//
+//*****************************************************************************
+// This field selects the frequency of the ARM M4 TPIU port.
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_S             8
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_M             0x00000700
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(n)            (((uint32_t)(n) << 8) & 0x00000700)
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_LOW_PWR       0x00000000
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz          0x00000000
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_2    0x00000100
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_8    0x00000200
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_16   0x00000300
+#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_32   0x00000400
+
+// TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be
+// streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.
+#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_S             0
+#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_M             0x00000001
+#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE(n)            (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS           0x00000000
+#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_EN            0x00000001
+
+#endif // AM_REG_MCUCTRL_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h b/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h
new file mode 100644
index 0000000000..349991e28f
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h
@@ -0,0 +1,325 @@
+//*****************************************************************************
+//
+//  am_reg_nvic.h
+//! @file
+//!
+//! @brief Register macros for the NVIC module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_NVIC_H
+#define AM_REG_NVIC_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_NVIC_NUM_MODULES                      1
+#define AM_REG_NVICn(n) \
+    (REG_NVIC_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_NVIC_ISER0_O                          0xE000E100
+#define AM_REG_NVIC_ICER0_O                          0xE000E180
+#define AM_REG_NVIC_ISPR0_O                          0xE000E200
+#define AM_REG_NVIC_ICPR0_O                          0xE000E280
+#define AM_REG_NVIC_IABR0_O                          0xE000E300
+#define AM_REG_NVIC_IPR0_O                           0xE000E400
+#define AM_REG_NVIC_IPR1_O                           0xE000E404
+#define AM_REG_NVIC_IPR2_O                           0xE000E408
+#define AM_REG_NVIC_IPR3_O                           0xE000E40C
+#define AM_REG_NVIC_IPR4_O                           0xE000E410
+#define AM_REG_NVIC_IPR5_O                           0xE000E414
+#define AM_REG_NVIC_IPR6_O                           0xE000E418
+#define AM_REG_NVIC_IPR7_O                           0xE000E41C
+
+//*****************************************************************************
+//
+// NVIC_ISER0 - Interrupt Set-Enable Register 0
+//
+//*****************************************************************************
+// NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0.
+#define AM_REG_NVIC_ISER0_BITS_S                     0
+#define AM_REG_NVIC_ISER0_BITS_M                     0xFFFFFFFF
+#define AM_REG_NVIC_ISER0_BITS(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// NVIC_ICER0 - Interrupt Clear-Enable Register 0
+//
+//*****************************************************************************
+// NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0.
+#define AM_REG_NVIC_ICER0_BITS_S                     0
+#define AM_REG_NVIC_ICER0_BITS_M                     0xFFFFFFFF
+#define AM_REG_NVIC_ICER0_BITS(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// NVIC_ISPR0 - Interrupt Set-Pending Register 0
+//
+//*****************************************************************************
+// NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0.
+#define AM_REG_NVIC_ISPR0_BITS_S                     0
+#define AM_REG_NVIC_ISPR0_BITS_M                     0xFFFFFFFF
+#define AM_REG_NVIC_ISPR0_BITS(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// NVIC_ICPR0 - Interrupt Clear-Pending Register 0
+//
+//*****************************************************************************
+// NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0.
+#define AM_REG_NVIC_ICPR0_BITS_S                     0
+#define AM_REG_NVIC_ICPR0_BITS_M                     0xFFFFFFFF
+#define AM_REG_NVIC_ICPR0_BITS(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// NVIC_IABR0 - Interrupt Active Bit Register 0
+//
+//*****************************************************************************
+// NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0.
+#define AM_REG_NVIC_IABR0_BITS_S                     0
+#define AM_REG_NVIC_IABR0_BITS_M                     0xFFFFFFFF
+#define AM_REG_NVIC_IABR0_BITS(n)                    (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// NVIC_IPR0 - Interrupt Priority Register 0
+//
+//*****************************************************************************
+// Priority assignment for interrupt vector 3.
+#define AM_REG_NVIC_IPR0_PRI_N3_S                    24
+#define AM_REG_NVIC_IPR0_PRI_N3_M                    0xFF000000
+#define AM_REG_NVIC_IPR0_PRI_N3(n)                   (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority assignment for interrupt vector 2.
+#define AM_REG_NVIC_IPR0_PRI_N2_S                    16
+#define AM_REG_NVIC_IPR0_PRI_N2_M                    0x00FF0000
+#define AM_REG_NVIC_IPR0_PRI_N2(n)                   (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority assignment for interrupt vector 1.
+#define AM_REG_NVIC_IPR0_PRI_N1_S                    8
+#define AM_REG_NVIC_IPR0_PRI_N1_M                    0x0000FF00
+#define AM_REG_NVIC_IPR0_PRI_N1(n)                   (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority assignment for interrupt vector 0.
+#define AM_REG_NVIC_IPR0_PRI_N0_S                    0
+#define AM_REG_NVIC_IPR0_PRI_N0_M                    0x000000FF
+#define AM_REG_NVIC_IPR0_PRI_N0(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// NVIC_IPR1 - Interrupt Priority Register 1
+//
+//*****************************************************************************
+// Priority assignment for interrupt vector 7.
+#define AM_REG_NVIC_IPR1_PRI_N3_S                    24
+#define AM_REG_NVIC_IPR1_PRI_N3_M                    0xFF000000
+#define AM_REG_NVIC_IPR1_PRI_N3(n)                   (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority assignment for interrupt vector 6.
+#define AM_REG_NVIC_IPR1_PRI_N2_S                    16
+#define AM_REG_NVIC_IPR1_PRI_N2_M                    0x00FF0000
+#define AM_REG_NVIC_IPR1_PRI_N2(n)                   (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority assignment for interrupt vector 5.
+#define AM_REG_NVIC_IPR1_PRI_N1_S                    8
+#define AM_REG_NVIC_IPR1_PRI_N1_M                    0x0000FF00
+#define AM_REG_NVIC_IPR1_PRI_N1(n)                   (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority assignment for interrupt vector 4.
+#define AM_REG_NVIC_IPR1_PRI_N0_S                    0
+#define AM_REG_NVIC_IPR1_PRI_N0_M                    0x000000FF
+#define AM_REG_NVIC_IPR1_PRI_N0(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// NVIC_IPR2 - Interrupt Priority Register 2
+//
+//*****************************************************************************
+// Priority assignment for interrupt vector 11.
+#define AM_REG_NVIC_IPR2_PRI_N3_S                    24
+#define AM_REG_NVIC_IPR2_PRI_N3_M                    0xFF000000
+#define AM_REG_NVIC_IPR2_PRI_N3(n)                   (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority assignment for interrupt vector 10.
+#define AM_REG_NVIC_IPR2_PRI_N2_S                    16
+#define AM_REG_NVIC_IPR2_PRI_N2_M                    0x00FF0000
+#define AM_REG_NVIC_IPR2_PRI_N2(n)                   (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority assignment for interrupt vector 9.
+#define AM_REG_NVIC_IPR2_PRI_N1_S                    8
+#define AM_REG_NVIC_IPR2_PRI_N1_M                    0x0000FF00
+#define AM_REG_NVIC_IPR2_PRI_N1(n)                   (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority assignment for interrupt vector 8.
+#define AM_REG_NVIC_IPR2_PRI_N0_S                    0
+#define AM_REG_NVIC_IPR2_PRI_N0_M                    0x000000FF
+#define AM_REG_NVIC_IPR2_PRI_N0(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// NVIC_IPR3 - Interrupt Priority Register 3
+//
+//*****************************************************************************
+// Priority assignment for interrupt vector 15.
+#define AM_REG_NVIC_IPR3_PRI_N3_S                    24
+#define AM_REG_NVIC_IPR3_PRI_N3_M                    0xFF000000
+#define AM_REG_NVIC_IPR3_PRI_N3(n)                   (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority assignment for interrupt vector 14.
+#define AM_REG_NVIC_IPR3_PRI_N2_S                    16
+#define AM_REG_NVIC_IPR3_PRI_N2_M                    0x00FF0000
+#define AM_REG_NVIC_IPR3_PRI_N2(n)                   (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority assignment for interrupt vector 13.
+#define AM_REG_NVIC_IPR3_PRI_N1_S                    8
+#define AM_REG_NVIC_IPR3_PRI_N1_M                    0x0000FF00
+#define AM_REG_NVIC_IPR3_PRI_N1(n)                   (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority assignment for interrupt vector 12.
+#define AM_REG_NVIC_IPR3_PRI_N0_S                    0
+#define AM_REG_NVIC_IPR3_PRI_N0_M                    0x000000FF
+#define AM_REG_NVIC_IPR3_PRI_N0(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// NVIC_IPR4 - Interrupt Priority Register 4
+//
+//*****************************************************************************
+// Priority assignment for interrupt vector 19.
+#define AM_REG_NVIC_IPR4_PRI_N3_S                    24
+#define AM_REG_NVIC_IPR4_PRI_N3_M                    0xFF000000
+#define AM_REG_NVIC_IPR4_PRI_N3(n)                   (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority assignment for interrupt vector 18.
+#define AM_REG_NVIC_IPR4_PRI_N2_S                    16
+#define AM_REG_NVIC_IPR4_PRI_N2_M                    0x00FF0000
+#define AM_REG_NVIC_IPR4_PRI_N2(n)                   (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority assignment for interrupt vector 17.
+#define AM_REG_NVIC_IPR4_PRI_N1_S                    8
+#define AM_REG_NVIC_IPR4_PRI_N1_M                    0x0000FF00
+#define AM_REG_NVIC_IPR4_PRI_N1(n)                   (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority assignment for interrupt vector 16.
+#define AM_REG_NVIC_IPR4_PRI_N0_S                    0
+#define AM_REG_NVIC_IPR4_PRI_N0_M                    0x000000FF
+#define AM_REG_NVIC_IPR4_PRI_N0(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// NVIC_IPR5 - Interrupt Priority Register 5
+//
+//*****************************************************************************
+// Priority assignment for interrupt vector 23.
+#define AM_REG_NVIC_IPR5_PRI_N3_S                    24
+#define AM_REG_NVIC_IPR5_PRI_N3_M                    0xFF000000
+#define AM_REG_NVIC_IPR5_PRI_N3(n)                   (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority assignment for interrupt vector 22.
+#define AM_REG_NVIC_IPR5_PRI_N2_S                    16
+#define AM_REG_NVIC_IPR5_PRI_N2_M                    0x00FF0000
+#define AM_REG_NVIC_IPR5_PRI_N2(n)                   (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority assignment for interrupt vector 21.
+#define AM_REG_NVIC_IPR5_PRI_N1_S                    8
+#define AM_REG_NVIC_IPR5_PRI_N1_M                    0x0000FF00
+#define AM_REG_NVIC_IPR5_PRI_N1(n)                   (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority assignment for interrupt vector 20.
+#define AM_REG_NVIC_IPR5_PRI_N0_S                    0
+#define AM_REG_NVIC_IPR5_PRI_N0_M                    0x000000FF
+#define AM_REG_NVIC_IPR5_PRI_N0(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// NVIC_IPR6 - Interrupt Priority Register 6
+//
+//*****************************************************************************
+// Priority assignment for interrupt vector 27.
+#define AM_REG_NVIC_IPR6_PRI_N3_S                    24
+#define AM_REG_NVIC_IPR6_PRI_N3_M                    0xFF000000
+#define AM_REG_NVIC_IPR6_PRI_N3(n)                   (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority assignment for interrupt vector 26.
+#define AM_REG_NVIC_IPR6_PRI_N2_S                    16
+#define AM_REG_NVIC_IPR6_PRI_N2_M                    0x00FF0000
+#define AM_REG_NVIC_IPR6_PRI_N2(n)                   (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority assignment for interrupt vector 25.
+#define AM_REG_NVIC_IPR6_PRI_N1_S                    8
+#define AM_REG_NVIC_IPR6_PRI_N1_M                    0x0000FF00
+#define AM_REG_NVIC_IPR6_PRI_N1(n)                   (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority assignment for interrupt vector 24.
+#define AM_REG_NVIC_IPR6_PRI_N0_S                    0
+#define AM_REG_NVIC_IPR6_PRI_N0_M                    0x000000FF
+#define AM_REG_NVIC_IPR6_PRI_N0(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// NVIC_IPR7 - Interrupt Priority Register 7
+//
+//*****************************************************************************
+// Priority assignment for interrupt vector 31.
+#define AM_REG_NVIC_IPR7_PRI_N3_S                    24
+#define AM_REG_NVIC_IPR7_PRI_N3_M                    0xFF000000
+#define AM_REG_NVIC_IPR7_PRI_N3(n)                   (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority assignment for interrupt vector 30.
+#define AM_REG_NVIC_IPR7_PRI_N2_S                    16
+#define AM_REG_NVIC_IPR7_PRI_N2_M                    0x00FF0000
+#define AM_REG_NVIC_IPR7_PRI_N2(n)                   (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority assignment for interrupt vector 29.
+#define AM_REG_NVIC_IPR7_PRI_N1_S                    8
+#define AM_REG_NVIC_IPR7_PRI_N1_M                    0x0000FF00
+#define AM_REG_NVIC_IPR7_PRI_N1(n)                   (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority assignment for interrupt vector 28.
+#define AM_REG_NVIC_IPR7_PRI_N0_S                    0
+#define AM_REG_NVIC_IPR7_PRI_N0_M                    0x000000FF
+#define AM_REG_NVIC_IPR7_PRI_N0(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+#endif // AM_REG_NVIC_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h
new file mode 100644
index 0000000000..6a7c6aa3cf
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h
@@ -0,0 +1,374 @@
+//*****************************************************************************
+//
+//  am_reg_pdm.h
+//! @file
+//!
+//! @brief Register macros for the PDM module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_PDM_H
+#define AM_REG_PDM_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_PDM_NUM_MODULES                       1
+#define AM_REG_PDMn(n) \
+    (REG_PDM_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_PDM_PCFG_O                            0x00000000
+#define AM_REG_PDM_VCFG_O                            0x00000004
+#define AM_REG_PDM_FR_O                              0x00000008
+#define AM_REG_PDM_FRD_O                             0x0000000C
+#define AM_REG_PDM_FLUSH_O                           0x00000010
+#define AM_REG_PDM_FTHR_O                            0x00000014
+#define AM_REG_PDM_INTEN_O                           0x00000200
+#define AM_REG_PDM_INTSTAT_O                         0x00000204
+#define AM_REG_PDM_INTCLR_O                          0x00000208
+#define AM_REG_PDM_INTSET_O                          0x0000020C
+
+//*****************************************************************************
+//
+// PDM_INTEN - IO Master Interrupts: Enable
+//
+//*****************************************************************************
+// This is the FIFO underflow interrupt.
+#define AM_REG_PDM_INTEN_UNDFL_S                     2
+#define AM_REG_PDM_INTEN_UNDFL_M                     0x00000004
+#define AM_REG_PDM_INTEN_UNDFL(n)                    (((uint32_t)(n) << 2) & 0x00000004)
+
+// This is the FIFO overflow interrupt.
+#define AM_REG_PDM_INTEN_OVF_S                       1
+#define AM_REG_PDM_INTEN_OVF_M                       0x00000002
+#define AM_REG_PDM_INTEN_OVF(n)                      (((uint32_t)(n) << 1) & 0x00000002)
+
+// This is the FIFO threshold interrupt.
+#define AM_REG_PDM_INTEN_THR_S                       0
+#define AM_REG_PDM_INTEN_THR_M                       0x00000001
+#define AM_REG_PDM_INTEN_THR(n)                      (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// PDM_INTSTAT - IO Master Interrupts: Status
+//
+//*****************************************************************************
+// This is the FIFO underflow interrupt.
+#define AM_REG_PDM_INTSTAT_UNDFL_S                   2
+#define AM_REG_PDM_INTSTAT_UNDFL_M                   0x00000004
+#define AM_REG_PDM_INTSTAT_UNDFL(n)                  (((uint32_t)(n) << 2) & 0x00000004)
+
+// This is the FIFO overflow interrupt.
+#define AM_REG_PDM_INTSTAT_OVF_S                     1
+#define AM_REG_PDM_INTSTAT_OVF_M                     0x00000002
+#define AM_REG_PDM_INTSTAT_OVF(n)                    (((uint32_t)(n) << 1) & 0x00000002)
+
+// This is the FIFO threshold interrupt.
+#define AM_REG_PDM_INTSTAT_THR_S                     0
+#define AM_REG_PDM_INTSTAT_THR_M                     0x00000001
+#define AM_REG_PDM_INTSTAT_THR(n)                    (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// PDM_INTCLR - IO Master Interrupts: Clear
+//
+//*****************************************************************************
+// This is the FIFO underflow interrupt.
+#define AM_REG_PDM_INTCLR_UNDFL_S                    2
+#define AM_REG_PDM_INTCLR_UNDFL_M                    0x00000004
+#define AM_REG_PDM_INTCLR_UNDFL(n)                   (((uint32_t)(n) << 2) & 0x00000004)
+
+// This is the FIFO overflow interrupt.
+#define AM_REG_PDM_INTCLR_OVF_S                      1
+#define AM_REG_PDM_INTCLR_OVF_M                      0x00000002
+#define AM_REG_PDM_INTCLR_OVF(n)                     (((uint32_t)(n) << 1) & 0x00000002)
+
+// This is the FIFO threshold interrupt.
+#define AM_REG_PDM_INTCLR_THR_S                      0
+#define AM_REG_PDM_INTCLR_THR_M                      0x00000001
+#define AM_REG_PDM_INTCLR_THR(n)                     (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// PDM_INTSET - IO Master Interrupts: Set
+//
+//*****************************************************************************
+// This is the FIFO underflow interrupt.
+#define AM_REG_PDM_INTSET_UNDFL_S                    2
+#define AM_REG_PDM_INTSET_UNDFL_M                    0x00000004
+#define AM_REG_PDM_INTSET_UNDFL(n)                   (((uint32_t)(n) << 2) & 0x00000004)
+
+// This is the FIFO overflow interrupt.
+#define AM_REG_PDM_INTSET_OVF_S                      1
+#define AM_REG_PDM_INTSET_OVF_M                      0x00000002
+#define AM_REG_PDM_INTSET_OVF(n)                     (((uint32_t)(n) << 1) & 0x00000002)
+
+// This is the FIFO threshold interrupt.
+#define AM_REG_PDM_INTSET_THR_S                      0
+#define AM_REG_PDM_INTSET_THR_M                      0x00000001
+#define AM_REG_PDM_INTSET_THR(n)                     (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// PDM_PCFG - PDM Configuration Register
+//
+//*****************************************************************************
+// Left/right channel swap.
+#define AM_REG_PDM_PCFG_LRSWAP_S                     31
+#define AM_REG_PDM_PCFG_LRSWAP_M                     0x80000000
+#define AM_REG_PDM_PCFG_LRSWAP(n)                    (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_PDM_PCFG_LRSWAP_EN                    0x80000000
+#define AM_REG_PDM_PCFG_LRSWAP_NOSWAP                0x00000000
+
+// Right channel PGA gain.
+#define AM_REG_PDM_PCFG_PGARIGHT_S                   27
+#define AM_REG_PDM_PCFG_PGARIGHT_M                   0x78000000
+#define AM_REG_PDM_PCFG_PGARIGHT(n)                  (((uint32_t)(n) << 27) & 0x78000000)
+#define AM_REG_PDM_PCFG_PGARIGHT_M15DB               0x78000000
+#define AM_REG_PDM_PCFG_PGARIGHT_M300DB              0x70000000
+#define AM_REG_PDM_PCFG_PGARIGHT_M45DB               0x68000000
+#define AM_REG_PDM_PCFG_PGARIGHT_M60DB               0x60000000
+#define AM_REG_PDM_PCFG_PGARIGHT_M75DB               0x58000000
+#define AM_REG_PDM_PCFG_PGARIGHT_M90DB               0x50000000
+#define AM_REG_PDM_PCFG_PGARIGHT_M105DB              0x48000000
+#define AM_REG_PDM_PCFG_PGARIGHT_M120DB              0x40000000
+#define AM_REG_PDM_PCFG_PGARIGHT_P105DB              0x38000000
+#define AM_REG_PDM_PCFG_PGARIGHT_P90DB               0x30000000
+#define AM_REG_PDM_PCFG_PGARIGHT_P75DB               0x28000000
+#define AM_REG_PDM_PCFG_PGARIGHT_P60DB               0x20000000
+#define AM_REG_PDM_PCFG_PGARIGHT_P45DB               0x18000000
+#define AM_REG_PDM_PCFG_PGARIGHT_P30DB               0x10000000
+#define AM_REG_PDM_PCFG_PGARIGHT_P15DB               0x08000000
+#define AM_REG_PDM_PCFG_PGARIGHT_0DB                 0x00000000
+
+// Left channel PGA gain.
+#define AM_REG_PDM_PCFG_PGALEFT_S                    23
+#define AM_REG_PDM_PCFG_PGALEFT_M                    0x07800000
+#define AM_REG_PDM_PCFG_PGALEFT(n)                   (((uint32_t)(n) << 23) & 0x07800000)
+#define AM_REG_PDM_PCFG_PGALEFT_M15DB                0x07800000
+#define AM_REG_PDM_PCFG_PGALEFT_M300DB               0x07000000
+#define AM_REG_PDM_PCFG_PGALEFT_M45DB                0x06800000
+#define AM_REG_PDM_PCFG_PGALEFT_M60DB                0x06000000
+#define AM_REG_PDM_PCFG_PGALEFT_M75DB                0x05800000
+#define AM_REG_PDM_PCFG_PGALEFT_M90DB                0x05000000
+#define AM_REG_PDM_PCFG_PGALEFT_M105DB               0x04800000
+#define AM_REG_PDM_PCFG_PGALEFT_M120DB               0x04000000
+#define AM_REG_PDM_PCFG_PGALEFT_P105DB               0x03800000
+#define AM_REG_PDM_PCFG_PGALEFT_P90DB                0x03000000
+#define AM_REG_PDM_PCFG_PGALEFT_P75DB                0x02800000
+#define AM_REG_PDM_PCFG_PGALEFT_P60DB                0x02000000
+#define AM_REG_PDM_PCFG_PGALEFT_P45DB                0x01800000
+#define AM_REG_PDM_PCFG_PGALEFT_P30DB                0x01000000
+#define AM_REG_PDM_PCFG_PGALEFT_P15DB                0x00800000
+#define AM_REG_PDM_PCFG_PGALEFT_0DB                  0x00000000
+
+// PDM_CLK frequency divisor.
+#define AM_REG_PDM_PCFG_MCLKDIV_S                    17
+#define AM_REG_PDM_PCFG_MCLKDIV_M                    0x00060000
+#define AM_REG_PDM_PCFG_MCLKDIV(n)                   (((uint32_t)(n) << 17) & 0x00060000)
+#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV4              0x00060000
+#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV3              0x00040000
+#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV2              0x00020000
+#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV1              0x00000000
+
+// SINC decimation rate.
+#define AM_REG_PDM_PCFG_SINCRATE_S                   10
+#define AM_REG_PDM_PCFG_SINCRATE_M                   0x0001FC00
+#define AM_REG_PDM_PCFG_SINCRATE(n)                  (((uint32_t)(n) << 10) & 0x0001FC00)
+
+// High pass filter control.
+#define AM_REG_PDM_PCFG_ADCHPD_S                     9
+#define AM_REG_PDM_PCFG_ADCHPD_M                     0x00000200
+#define AM_REG_PDM_PCFG_ADCHPD(n)                    (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_PDM_PCFG_ADCHPD_EN                    0x00000200
+#define AM_REG_PDM_PCFG_ADCHPD_DIS                   0x00000000
+
+// High pass filter coefficients.
+#define AM_REG_PDM_PCFG_HPCUTOFF_S                   5
+#define AM_REG_PDM_PCFG_HPCUTOFF_M                   0x000001E0
+#define AM_REG_PDM_PCFG_HPCUTOFF(n)                  (((uint32_t)(n) << 5) & 0x000001E0)
+
+// Number of clocks during gain-setting changes.
+#define AM_REG_PDM_PCFG_CYCLES_S                     2
+#define AM_REG_PDM_PCFG_CYCLES_M                     0x0000001C
+#define AM_REG_PDM_PCFG_CYCLES(n)                    (((uint32_t)(n) << 2) & 0x0000001C)
+
+// Soft mute control.
+#define AM_REG_PDM_PCFG_SOFTMUTE_S                   1
+#define AM_REG_PDM_PCFG_SOFTMUTE_M                   0x00000002
+#define AM_REG_PDM_PCFG_SOFTMUTE(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_PDM_PCFG_SOFTMUTE_EN                  0x00000002
+#define AM_REG_PDM_PCFG_SOFTMUTE_DIS                 0x00000000
+
+// Data Streaming Control.
+#define AM_REG_PDM_PCFG_PDMCORE_S                    0
+#define AM_REG_PDM_PCFG_PDMCORE_M                    0x00000001
+#define AM_REG_PDM_PCFG_PDMCORE(n)                   (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_PDM_PCFG_PDMCORE_EN                   0x00000001
+#define AM_REG_PDM_PCFG_PDMCORE_DIS                  0x00000000
+
+//*****************************************************************************
+//
+// PDM_VCFG - Voice Configuration Register
+//
+//*****************************************************************************
+// Enable the IO clock.
+#define AM_REG_PDM_VCFG_IOCLKEN_S                    31
+#define AM_REG_PDM_VCFG_IOCLKEN_M                    0x80000000
+#define AM_REG_PDM_VCFG_IOCLKEN(n)                   (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_PDM_VCFG_IOCLKEN_DIS                  0x00000000
+#define AM_REG_PDM_VCFG_IOCLKEN_EN                   0x80000000
+
+// Reset the IP core.
+#define AM_REG_PDM_VCFG_RSTB_S                       30
+#define AM_REG_PDM_VCFG_RSTB_M                       0x40000000
+#define AM_REG_PDM_VCFG_RSTB(n)                      (((uint32_t)(n) << 30) & 0x40000000)
+#define AM_REG_PDM_VCFG_RSTB_RESET                   0x00000000
+#define AM_REG_PDM_VCFG_RSTB_NORM                    0x40000000
+
+// Select the PDM input clock.
+#define AM_REG_PDM_VCFG_PDMCLKSEL_S                  27
+#define AM_REG_PDM_VCFG_PDMCLKSEL_M                  0x38000000
+#define AM_REG_PDM_VCFG_PDMCLKSEL(n)                 (((uint32_t)(n) << 27) & 0x38000000)
+#define AM_REG_PDM_VCFG_PDMCLKSEL_DISABLE            0x00000000
+#define AM_REG_PDM_VCFG_PDMCLKSEL_12MHz              0x08000000
+#define AM_REG_PDM_VCFG_PDMCLKSEL_6MHz               0x10000000
+#define AM_REG_PDM_VCFG_PDMCLKSEL_3MHz               0x18000000
+#define AM_REG_PDM_VCFG_PDMCLKSEL_1_5MHz             0x20000000
+#define AM_REG_PDM_VCFG_PDMCLKSEL_750KHz             0x28000000
+#define AM_REG_PDM_VCFG_PDMCLKSEL_375KHz             0x30000000
+#define AM_REG_PDM_VCFG_PDMCLKSEL_187KHz             0x38000000
+
+// Enable the serial clock.
+#define AM_REG_PDM_VCFG_PDMCLK_S                     26
+#define AM_REG_PDM_VCFG_PDMCLK_M                     0x04000000
+#define AM_REG_PDM_VCFG_PDMCLK(n)                    (((uint32_t)(n) << 26) & 0x04000000)
+#define AM_REG_PDM_VCFG_PDMCLK_DIS                   0x00000000
+#define AM_REG_PDM_VCFG_PDMCLK_EN                    0x04000000
+
+// I2S interface enable.
+#define AM_REG_PDM_VCFG_I2SMODE_S                    20
+#define AM_REG_PDM_VCFG_I2SMODE_M                    0x00100000
+#define AM_REG_PDM_VCFG_I2SMODE(n)                   (((uint32_t)(n) << 20) & 0x00100000)
+#define AM_REG_PDM_VCFG_I2SMODE_DIS                  0x00000000
+#define AM_REG_PDM_VCFG_I2SMODE_EN                   0x00100000
+
+// I2S BCLK input inversion.
+#define AM_REG_PDM_VCFG_BCLKINV_S                    19
+#define AM_REG_PDM_VCFG_BCLKINV_M                    0x00080000
+#define AM_REG_PDM_VCFG_BCLKINV(n)                   (((uint32_t)(n) << 19) & 0x00080000)
+#define AM_REG_PDM_VCFG_BCLKINV_INV                  0x00000000
+#define AM_REG_PDM_VCFG_BCLKINV_NORM                 0x00080000
+
+// PDM clock sampling delay.
+#define AM_REG_PDM_VCFG_DMICKDEL_S                   17
+#define AM_REG_PDM_VCFG_DMICKDEL_M                   0x00020000
+#define AM_REG_PDM_VCFG_DMICKDEL(n)                  (((uint32_t)(n) << 17) & 0x00020000)
+#define AM_REG_PDM_VCFG_DMICKDEL_0CYC                0x00000000
+#define AM_REG_PDM_VCFG_DMICKDEL_1CYC                0x00020000
+
+// Select PDM input clock source.
+#define AM_REG_PDM_VCFG_SELAP_S                      16
+#define AM_REG_PDM_VCFG_SELAP_M                      0x00010000
+#define AM_REG_PDM_VCFG_SELAP(n)                     (((uint32_t)(n) << 16) & 0x00010000)
+#define AM_REG_PDM_VCFG_SELAP_I2S                    0x00010000
+#define AM_REG_PDM_VCFG_SELAP_INTERNAL               0x00000000
+
+// PCM data packing enable.
+#define AM_REG_PDM_VCFG_PCMPACK_S                    8
+#define AM_REG_PDM_VCFG_PCMPACK_M                    0x00000100
+#define AM_REG_PDM_VCFG_PCMPACK(n)                   (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_PDM_VCFG_PCMPACK_DIS                  0x00000000
+#define AM_REG_PDM_VCFG_PCMPACK_EN                   0x00000100
+
+// Set PCM channels.
+#define AM_REG_PDM_VCFG_CHSET_S                      3
+#define AM_REG_PDM_VCFG_CHSET_M                      0x00000018
+#define AM_REG_PDM_VCFG_CHSET(n)                     (((uint32_t)(n) << 3) & 0x00000018)
+#define AM_REG_PDM_VCFG_CHSET_DIS                    0x00000000
+#define AM_REG_PDM_VCFG_CHSET_LEFT                   0x00000008
+#define AM_REG_PDM_VCFG_CHSET_RIGHT                  0x00000010
+#define AM_REG_PDM_VCFG_CHSET_STEREO                 0x00000018
+
+//*****************************************************************************
+//
+// PDM_FR - Voice Status Register
+//
+//*****************************************************************************
+// Valid 32-bit entries currently in the FIFO.
+#define AM_REG_PDM_FR_FIFOCNT_S                      0
+#define AM_REG_PDM_FR_FIFOCNT_M                      0x000001FF
+#define AM_REG_PDM_FR_FIFOCNT(n)                     (((uint32_t)(n) << 0) & 0x000001FF)
+
+//*****************************************************************************
+//
+// PDM_FRD - FIFO Read
+//
+//*****************************************************************************
+// FIFO read data.
+#define AM_REG_PDM_FRD_FIFOREAD_S                    0
+#define AM_REG_PDM_FRD_FIFOREAD_M                    0xFFFFFFFF
+#define AM_REG_PDM_FRD_FIFOREAD(n)                   (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// PDM_FLUSH - FIFO Flush
+//
+//*****************************************************************************
+// FIFO FLUSH.
+#define AM_REG_PDM_FLUSH_FIFOFLUSH_S                 0
+#define AM_REG_PDM_FLUSH_FIFOFLUSH_M                 0x00000001
+#define AM_REG_PDM_FLUSH_FIFOFLUSH(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// PDM_FTHR - FIFO Threshold
+//
+//*****************************************************************************
+// FIFO interrupt threshold.
+#define AM_REG_PDM_FTHR_FIFOTHR_S                    0
+#define AM_REG_PDM_FTHR_FIFOTHR_M                    0x000000FF
+#define AM_REG_PDM_FTHR_FIFOTHR(n)                   (((uint32_t)(n) << 0) & 0x000000FF)
+
+#endif // AM_REG_PDM_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h
new file mode 100644
index 0000000000..cac7cab36c
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h
@@ -0,0 +1,485 @@
+//*****************************************************************************
+//
+//  am_reg_pwrctrl.h
+//! @file
+//!
+//! @brief Register macros for the PWRCTRL module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_PWRCTRL_H
+#define AM_REG_PWRCTRL_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_PWRCTRL_NUM_MODULES                   1
+#define AM_REG_PWRCTRLn(n) \
+    (REG_PWRCTRL_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_PWRCTRL_SUPPLYSRC_O                   0x00000000
+#define AM_REG_PWRCTRL_POWERSTATUS_O                 0x00000004
+#define AM_REG_PWRCTRL_DEVICEEN_O                    0x00000008
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_O              0x0000000C
+#define AM_REG_PWRCTRL_MEMEN_O                       0x00000010
+#define AM_REG_PWRCTRL_PWRONSTATUS_O                 0x00000014
+#define AM_REG_PWRCTRL_SRAMCTRL_O                    0x00000018
+#define AM_REG_PWRCTRL_ADCSTATUS_O                   0x0000001C
+#define AM_REG_PWRCTRL_MISCOPT_O                     0x00000020
+
+//*****************************************************************************
+//
+// PWRCTRL_SUPPLYSRC - Memory and Core Voltage Supply Source Select Register
+//
+//*****************************************************************************
+// Switches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in
+// DEEP SLEEP. If all the devices are off then this does not matter and LDO (low
+// power mode) is used
+#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_S 2
+#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_M 0x00000004
+#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP(n) (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_EN 0x00000004
+
+// Enables and Selects the Core Buck as the supply for the low-voltage power
+// domain.
+#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_S        1
+#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_M        0x00000002
+#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN(n)       (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_EN       0x00000002
+
+// Enables and select the Memory Buck as the supply for the Flash and SRAM power
+// domain.
+#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_S         0
+#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_M         0x00000001
+#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN(n)        (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_EN        0x00000001
+
+//*****************************************************************************
+//
+// PWRCTRL_POWERSTATUS - Power Status Register for MCU supplies and peripherals
+//
+//*****************************************************************************
+// Indicates whether the Core low-voltage domain is supplied from the LDO or the
+// Buck.
+#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_S      1
+#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M      0x00000002
+#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON(n)     (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_LDO    0x00000000
+#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_BUCK   0x00000002
+
+// Indicate whether the Memory power domain is supplied from the LDO or the
+// Buck.
+#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_S       0
+#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M       0x00000001
+#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON(n)      (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_LDO     0x00000000
+#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_BUCK    0x00000001
+
+//*****************************************************************************
+//
+// PWRCTRL_DEVICEEN - DEVICE ENABLES for SHELBY
+//
+//*****************************************************************************
+// Enable PDM Digital Block
+#define AM_REG_PWRCTRL_DEVICEEN_PDM_S                10
+#define AM_REG_PWRCTRL_DEVICEEN_PDM_M                0x00000400
+#define AM_REG_PWRCTRL_DEVICEEN_PDM(n)               (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_PWRCTRL_DEVICEEN_PDM_EN               0x00000400
+#define AM_REG_PWRCTRL_DEVICEEN_PDM_DIS              0x00000000
+
+// Enable ADC Digital Block
+#define AM_REG_PWRCTRL_DEVICEEN_ADC_S                9
+#define AM_REG_PWRCTRL_DEVICEEN_ADC_M                0x00000200
+#define AM_REG_PWRCTRL_DEVICEEN_ADC(n)               (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_PWRCTRL_DEVICEEN_ADC_EN               0x00000200
+#define AM_REG_PWRCTRL_DEVICEEN_ADC_DIS              0x00000000
+
+// Enable UART 1
+#define AM_REG_PWRCTRL_DEVICEEN_UART1_S              8
+#define AM_REG_PWRCTRL_DEVICEEN_UART1_M              0x00000100
+#define AM_REG_PWRCTRL_DEVICEEN_UART1(n)             (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_PWRCTRL_DEVICEEN_UART1_EN             0x00000100
+#define AM_REG_PWRCTRL_DEVICEEN_UART1_DIS            0x00000000
+
+// Enable UART 0
+#define AM_REG_PWRCTRL_DEVICEEN_UART0_S              7
+#define AM_REG_PWRCTRL_DEVICEEN_UART0_M              0x00000080
+#define AM_REG_PWRCTRL_DEVICEEN_UART0(n)             (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_PWRCTRL_DEVICEEN_UART0_EN             0x00000080
+#define AM_REG_PWRCTRL_DEVICEEN_UART0_DIS            0x00000000
+
+// Enable IO MASTER 5
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_S         6
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_M         0x00000040
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5(n)        (((uint32_t)(n) << 6) & 0x00000040)
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN        0x00000040
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_DIS       0x00000000
+
+// Enable IO MASTER 4
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_S         5
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_M         0x00000020
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4(n)        (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN        0x00000020
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_DIS       0x00000000
+
+// Enable IO MASTER 3
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_S         4
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_M         0x00000010
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3(n)        (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN        0x00000010
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_DIS       0x00000000
+
+// Enable IO MASTER 2
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_S         3
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_M         0x00000008
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2(n)        (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN        0x00000008
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_DIS       0x00000000
+
+// Enable IO MASTER 1
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_S         2
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_M         0x00000004
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1(n)        (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN        0x00000004
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_DIS       0x00000000
+
+// Enable IO MASTER 0
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_S         1
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_M         0x00000002
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0(n)        (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN        0x00000002
+#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_DIS       0x00000000
+
+// Enable IO SLAVE
+#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_S           0
+#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_M           0x00000001
+#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE(n)          (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN          0x00000001
+#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_DIS         0x00000000
+
+//*****************************************************************************
+//
+// PWRCTRL_SRAMPWDINSLEEP - Powerdown an SRAM Banks in Deep Sleep mode
+//
+//*****************************************************************************
+// Enable CACHE BANKS to power down in deep sleep
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_S 31
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_M 0x80000000
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP(n) (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_EN 0x80000000
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_DIS 0x00000000
+
+// Selects which SRAM banks are powered down in deep sleep mode, causing the
+// contents of the bank to be lost.
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_S 0
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_M 0x000007FF
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN(n) (((uint32_t)(n) << 0) & 0x000007FF)
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_NONE 0x00000000
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM0 0x00000001
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM1 0x00000002
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM2 0x00000004
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM3 0x00000008
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP1 0x00000010
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP2 0x00000020
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP3 0x00000040
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP4 0x00000080
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP5 0x00000100
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP6 0x00000200
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP7 0x00000400
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM8K 0x00000001
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM16K 0x00000003
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM32K 0x0000000F
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM64K 0x0000001F
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM128K 0x0000007F
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER8K 0x000007FE
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER16K 0x000007FC
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER24K 0x000007F8
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER32K 0x000007F0
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER64K 0x000007E0
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER128K 0x00000780
+#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALL 0x000007FF
+
+//*****************************************************************************
+//
+// PWRCTRL_MEMEN - Disables individual banks of the MEMORY array
+//
+//*****************************************************************************
+// Enable CACHE BANK 2
+#define AM_REG_PWRCTRL_MEMEN_CACHEB2_S               31
+#define AM_REG_PWRCTRL_MEMEN_CACHEB2_M               0x80000000
+#define AM_REG_PWRCTRL_MEMEN_CACHEB2(n)              (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_PWRCTRL_MEMEN_CACHEB2_EN              0x80000000
+#define AM_REG_PWRCTRL_MEMEN_CACHEB2_DIS             0x00000000
+
+// Enable CACHE BANK 0
+#define AM_REG_PWRCTRL_MEMEN_CACHEB0_S               29
+#define AM_REG_PWRCTRL_MEMEN_CACHEB0_M               0x20000000
+#define AM_REG_PWRCTRL_MEMEN_CACHEB0(n)              (((uint32_t)(n) << 29) & 0x20000000)
+#define AM_REG_PWRCTRL_MEMEN_CACHEB0_EN              0x20000000
+#define AM_REG_PWRCTRL_MEMEN_CACHEB0_DIS             0x00000000
+
+// Enable FLASH1
+#define AM_REG_PWRCTRL_MEMEN_FLASH1_S                12
+#define AM_REG_PWRCTRL_MEMEN_FLASH1_M                0x00001000
+#define AM_REG_PWRCTRL_MEMEN_FLASH1(n)               (((uint32_t)(n) << 12) & 0x00001000)
+#define AM_REG_PWRCTRL_MEMEN_FLASH1_EN               0x00001000
+#define AM_REG_PWRCTRL_MEMEN_FLASH1_DIS              0x00000000
+
+// Enable FLASH 0
+#define AM_REG_PWRCTRL_MEMEN_FLASH0_S                11
+#define AM_REG_PWRCTRL_MEMEN_FLASH0_M                0x00000800
+#define AM_REG_PWRCTRL_MEMEN_FLASH0(n)               (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_PWRCTRL_MEMEN_FLASH0_EN               0x00000800
+#define AM_REG_PWRCTRL_MEMEN_FLASH0_DIS              0x00000000
+
+// Enables power for selected SRAM banks (else an access to its address space to
+// generate a Hard Fault).
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_S                0
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_M                0x000007FF
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN(n)               (((uint32_t)(n) << 0) & 0x000007FF)
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_NONE             0x00000000
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0     0x00000001
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1     0x00000002
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2     0x00000004
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM3     0x00000008
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP1           0x00000010
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2           0x00000020
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP3           0x00000040
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4           0x00000080
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5           0x00000100
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6           0x00000200
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP7           0x00000400
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K           0x00000001
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K          0x00000003
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K          0x0000000F
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K          0x0000001F
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K         0x0000007F
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K         0x000007FF
+#define AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL              0x000007FF
+
+//*****************************************************************************
+//
+// PWRCTRL_PWRONSTATUS - POWER ON Status
+//
+//*****************************************************************************
+// This bit is 1 if power is supplied to CACHE BANK 2
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_S      21
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M      0x00200000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2(n)     (((uint32_t)(n) << 21) & 0x00200000)
+
+// This bit is 1 if power is supplied to CACHE BANK 0
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_S      19
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M      0x00080000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0(n)     (((uint32_t)(n) << 19) & 0x00080000)
+
+// This bit is 1 if power is supplied to SRAM domain PD_GRP7
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_S    18
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M    0x00040000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM(n)   (((uint32_t)(n) << 18) & 0x00040000)
+
+// This bit is 1 if power is supplied to SRAM domain PD_GRP6
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_S    17
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M    0x00020000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM(n)   (((uint32_t)(n) << 17) & 0x00020000)
+
+// This bit is 1 if power is supplied to SRAM domain PD_GRP5
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_S    16
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M    0x00010000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM(n)   (((uint32_t)(n) << 16) & 0x00010000)
+
+// This bit is 1 if power is supplied to SRAM domain PD_GRP4
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_S    15
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M    0x00008000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM(n)   (((uint32_t)(n) << 15) & 0x00008000)
+
+// This bit is 1 if power is supplied to SRAM domain PD_GRP3
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_S    14
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M    0x00004000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM(n)   (((uint32_t)(n) << 14) & 0x00004000)
+
+// This bit is 1 if power is supplied to SRAM domain PD_GRP2
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_S    13
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M    0x00002000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM(n)   (((uint32_t)(n) << 13) & 0x00002000)
+
+// This bit is 1 if power is supplied to SRAM domain PD_GRP1
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_S    12
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M    0x00001000
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM(n)   (((uint32_t)(n) << 12) & 0x00001000)
+
+// This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_S   11
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M   0x00000800
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3(n)  (((uint32_t)(n) << 11) & 0x00000800)
+
+// This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_S   10
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M   0x00000400
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2(n)  (((uint32_t)(n) << 10) & 0x00000400)
+
+// This bit is 1 if power is supplied to SRAM domain SRAM0_1
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_S   9
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M   0x00000200
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1(n)  (((uint32_t)(n) << 9) & 0x00000200)
+
+// This bit is 1 if power is supplied to SRAM domain SRAM0_0
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_S   8
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M   0x00000100
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0(n)  (((uint32_t)(n) << 8) & 0x00000100)
+
+// This bit is 1 if power is supplied to domain PD_ADC
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC_S           7
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M           0x00000080
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC(n)          (((uint32_t)(n) << 7) & 0x00000080)
+
+// This bit is 1 if power is supplied to domain PD_FLAM1
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_S        6
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M        0x00000040
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1(n)       (((uint32_t)(n) << 6) & 0x00000040)
+
+// This bit is 1 if power is supplied to domain PD_FLAM0
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_S        5
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M        0x00000020
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0(n)       (((uint32_t)(n) << 5) & 0x00000020)
+
+// This bit is 1 if power is supplied to domain PD_PDM
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_S          4
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M          0x00000010
+#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM(n)         (((uint32_t)(n) << 4) & 0x00000010)
+
+// This bit is 1 if power is supplied to power domain C, which supplies IOM3-5.
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDC_S             3
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDC_M             0x00000008
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDC(n)            (((uint32_t)(n) << 3) & 0x00000008)
+
+// This bit is 1 if power is supplied to power domain B, which supplies IOM0-2.
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDB_S             2
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDB_M             0x00000004
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDB(n)            (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bit is 1 if power is supplied to power domain A, which supplies IOS and
+// UART0,1.
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDA_S             1
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDA_M             0x00000002
+#define AM_REG_PWRCTRL_PWRONSTATUS_PDA(n)            (((uint32_t)(n) << 1) & 0x00000002)
+
+//*****************************************************************************
+//
+// PWRCTRL_SRAMCTRL - SRAM Control register
+//
+//*****************************************************************************
+// Enables top-level clock gating in the SRAM block.  This bit should be enabled
+// for lowest power operation.
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_S 2
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_M 0x00000004
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE(n) (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_EN 0x00000004
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_DIS 0x00000000
+
+// Enables individual per-RAM clock gating in the SRAM block.  This bit should
+// be enabled for lowest power operation.
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_S       1
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_M       0x00000002
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE(n)      (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_EN      0x00000002
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_DIS     0x00000000
+
+// Enable LS (light sleep) of cache RAMs.  When this bit is set, the RAMS will
+// be put into light sleep mode while inactive.  NOTE:  if the SRAM is actively
+// used, this may have an adverse affect on power since entering/exiting LS mode
+// may consume more power than would be saved.
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_S   0
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_M   0x00000001
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP(n)  (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_EN  0x00000001
+#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_DIS 0x00000000
+
+//*****************************************************************************
+//
+// PWRCTRL_ADCSTATUS - Power Status Register for ADC Block
+//
+//*****************************************************************************
+// This bit indicates that the ADC REFBUF is powered down
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_S    5
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_M    0x00000020
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD(n)   (((uint32_t)(n) << 5) & 0x00000020)
+
+// This bit indicates that the ADC REFKEEP is powered down
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_S   4
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_M   0x00000010
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD(n)  (((uint32_t)(n) << 4) & 0x00000010)
+
+// This bit indicates that the ADC VBAT resistor divider is powered down
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_S      3
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_M      0x00000008
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD(n)     (((uint32_t)(n) << 3) & 0x00000008)
+
+// This bit indicates that the ADC temperature sensor input buffer is powered
+// down
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_S     2
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_M     0x00000004
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD(n)    (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bit indicates that the ADC Band Gap is powered down
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD_S       1
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD_M       0x00000002
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD(n)      (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit indicates that the ADC is powered down
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD_S           0
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD_M           0x00000001
+#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// PWRCTRL_MISCOPT - Power Optimization Control Bits
+//
+//*****************************************************************************
+// Setting this bit will enable the MEM LDO to be in LPMODE during deep sleep
+// even when the ctimers or stimers are running
+#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_S 2
+#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_M 0x00000004
+#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS(n) (((uint32_t)(n) << 2) & 0x00000004)
+
+#endif // AM_REG_PWRCTRL_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h b/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h
new file mode 100644
index 0000000000..1e76519744
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h
@@ -0,0 +1,211 @@
+//*****************************************************************************
+//
+//  am_reg_rstgen.h
+//! @file
+//!
+//! @brief Register macros for the RSTGEN module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_RSTGEN_H
+#define AM_REG_RSTGEN_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_RSTGEN_NUM_MODULES                    1
+#define AM_REG_RSTGENn(n) \
+    (REG_RSTGEN_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_RSTGEN_CFG_O                          0x00000000
+#define AM_REG_RSTGEN_SWPOI_O                        0x00000004
+#define AM_REG_RSTGEN_SWPOR_O                        0x00000008
+#define AM_REG_RSTGEN_STAT_O                         0x0000000C
+#define AM_REG_RSTGEN_CLRSTAT_O                      0x00000010
+#define AM_REG_RSTGEN_TPIU_RST_O                     0x00000014
+#define AM_REG_RSTGEN_INTEN_O                        0x00000200
+#define AM_REG_RSTGEN_INTSTAT_O                      0x00000204
+#define AM_REG_RSTGEN_INTCLR_O                       0x00000208
+#define AM_REG_RSTGEN_INTSET_O                       0x0000020C
+
+//*****************************************************************************
+//
+// RSTGEN_INTEN - Reset Interrupt register: Enable
+//
+//*****************************************************************************
+// Enables an interrupt that triggers when VCC is below BODH level.
+#define AM_REG_RSTGEN_INTEN_BODH_S                   0
+#define AM_REG_RSTGEN_INTEN_BODH_M                   0x00000001
+#define AM_REG_RSTGEN_INTEN_BODH(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RSTGEN_INTSTAT - Reset Interrupt register: Status
+//
+//*****************************************************************************
+// Enables an interrupt that triggers when VCC is below BODH level.
+#define AM_REG_RSTGEN_INTSTAT_BODH_S                 0
+#define AM_REG_RSTGEN_INTSTAT_BODH_M                 0x00000001
+#define AM_REG_RSTGEN_INTSTAT_BODH(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RSTGEN_INTCLR - Reset Interrupt register: Clear
+//
+//*****************************************************************************
+// Enables an interrupt that triggers when VCC is below BODH level.
+#define AM_REG_RSTGEN_INTCLR_BODH_S                  0
+#define AM_REG_RSTGEN_INTCLR_BODH_M                  0x00000001
+#define AM_REG_RSTGEN_INTCLR_BODH(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RSTGEN_INTSET - Reset Interrupt register: Set
+//
+//*****************************************************************************
+// Enables an interrupt that triggers when VCC is below BODH level.
+#define AM_REG_RSTGEN_INTSET_BODH_S                  0
+#define AM_REG_RSTGEN_INTSET_BODH_M                  0x00000001
+#define AM_REG_RSTGEN_INTSET_BODH(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RSTGEN_CFG - Configuration Register
+//
+//*****************************************************************************
+// Watchdog Timer Reset Enable.  NOTE: The WDT module must also be configured
+// for WDT reset.
+#define AM_REG_RSTGEN_CFG_WDREN_S                    1
+#define AM_REG_RSTGEN_CFG_WDREN_M                    0x00000002
+#define AM_REG_RSTGEN_CFG_WDREN(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+
+// Brown out high (2.1v) reset enable.
+#define AM_REG_RSTGEN_CFG_BODHREN_S                  0
+#define AM_REG_RSTGEN_CFG_BODHREN_M                  0x00000001
+#define AM_REG_RSTGEN_CFG_BODHREN(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RSTGEN_SWPOI - Software POI Reset
+//
+//*****************************************************************************
+// 0x1B generates a software POI reset.
+#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_S               0
+#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_M               0x000000FF
+#define AM_REG_RSTGEN_SWPOI_SWPOIKEY(n)              (((uint32_t)(n) << 0) & 0x000000FF)
+#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_KEYVALUE        0x0000001B
+
+//*****************************************************************************
+//
+// RSTGEN_SWPOR - Software POR Reset
+//
+//*****************************************************************************
+// 0xD4 generates a software POR reset.
+#define AM_REG_RSTGEN_SWPOR_SWPORKEY_S               0
+#define AM_REG_RSTGEN_SWPOR_SWPORKEY_M               0x000000FF
+#define AM_REG_RSTGEN_SWPOR_SWPORKEY(n)              (((uint32_t)(n) << 0) & 0x000000FF)
+#define AM_REG_RSTGEN_SWPOR_SWPORKEY_KEYVALUE        0x000000D4
+
+//*****************************************************************************
+//
+// RSTGEN_STAT - Status Register
+//
+//*****************************************************************************
+// Reset was initiated by a Watchdog Timer Reset.
+#define AM_REG_RSTGEN_STAT_WDRSTAT_S                 6
+#define AM_REG_RSTGEN_STAT_WDRSTAT_M                 0x00000040
+#define AM_REG_RSTGEN_STAT_WDRSTAT(n)                (((uint32_t)(n) << 6) & 0x00000040)
+
+// Reset was a initiated by Debugger Reset.
+#define AM_REG_RSTGEN_STAT_DBGRSTAT_S                5
+#define AM_REG_RSTGEN_STAT_DBGRSTAT_M                0x00000020
+#define AM_REG_RSTGEN_STAT_DBGRSTAT(n)               (((uint32_t)(n) << 5) & 0x00000020)
+
+// Reset was a initiated by Software POI Reset.
+#define AM_REG_RSTGEN_STAT_POIRSTAT_S                4
+#define AM_REG_RSTGEN_STAT_POIRSTAT_M                0x00000010
+#define AM_REG_RSTGEN_STAT_POIRSTAT(n)               (((uint32_t)(n) << 4) & 0x00000010)
+
+// Reset was a initiated by SW POR or AIRCR Reset.
+#define AM_REG_RSTGEN_STAT_SWRSTAT_S                 3
+#define AM_REG_RSTGEN_STAT_SWRSTAT_M                 0x00000008
+#define AM_REG_RSTGEN_STAT_SWRSTAT(n)                (((uint32_t)(n) << 3) & 0x00000008)
+
+// Reset was initiated by a Brown-Out Reset.
+#define AM_REG_RSTGEN_STAT_BORSTAT_S                 2
+#define AM_REG_RSTGEN_STAT_BORSTAT_M                 0x00000004
+#define AM_REG_RSTGEN_STAT_BORSTAT(n)                (((uint32_t)(n) << 2) & 0x00000004)
+
+// Reset was initiated by a Power-On Reset.
+#define AM_REG_RSTGEN_STAT_PORSTAT_S                 1
+#define AM_REG_RSTGEN_STAT_PORSTAT_M                 0x00000002
+#define AM_REG_RSTGEN_STAT_PORSTAT(n)                (((uint32_t)(n) << 1) & 0x00000002)
+
+// Reset was initiated by an External Reset.
+#define AM_REG_RSTGEN_STAT_EXRSTAT_S                 0
+#define AM_REG_RSTGEN_STAT_EXRSTAT_M                 0x00000001
+#define AM_REG_RSTGEN_STAT_EXRSTAT(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RSTGEN_CLRSTAT - Clear the status register
+//
+//*****************************************************************************
+// Writing a 1 to this bit clears all bits in the RST_STAT.
+#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_S              0
+#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_M              0x00000001
+#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT(n)             (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RSTGEN_TPIU_RST - TPIU reset
+//
+//*****************************************************************************
+// Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0'
+// to clear the reset.
+#define AM_REG_RSTGEN_TPIU_RST_TPIURST_S             0
+#define AM_REG_RSTGEN_TPIU_RST_TPIURST_M             0x00000001
+#define AM_REG_RSTGEN_TPIU_RST_TPIURST(n)            (((uint32_t)(n) << 0) & 0x00000001)
+
+#endif // AM_REG_RSTGEN_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h b/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h
new file mode 100644
index 0000000000..9da5bc816c
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h
@@ -0,0 +1,326 @@
+//*****************************************************************************
+//
+//  am_reg_rtc.h
+//! @file
+//!
+//! @brief Register macros for the RTC module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_RTC_H
+#define AM_REG_RTC_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_RTC_NUM_MODULES                       1
+#define AM_REG_RTCn(n) \
+    (REG_RTC_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_RTC_CTRLOW_O                          0x00000040
+#define AM_REG_RTC_CTRUP_O                           0x00000044
+#define AM_REG_RTC_ALMLOW_O                          0x00000048
+#define AM_REG_RTC_ALMUP_O                           0x0000004C
+#define AM_REG_RTC_RTCCTL_O                          0x00000050
+#define AM_REG_RTC_INTEN_O                           0x00000100
+#define AM_REG_RTC_INTSTAT_O                         0x00000104
+#define AM_REG_RTC_INTCLR_O                          0x00000108
+#define AM_REG_RTC_INTSET_O                          0x0000010C
+
+//*****************************************************************************
+//
+// RTC_INTEN - RTC Interrupt Register: Enable
+//
+//*****************************************************************************
+// RTC Alarm interrupt
+#define AM_REG_RTC_INTEN_ALM_S                       3
+#define AM_REG_RTC_INTEN_ALM_M                       0x00000008
+#define AM_REG_RTC_INTEN_ALM(n)                      (((uint32_t)(n) << 3) & 0x00000008)
+
+// XT Oscillator Fail interrupt
+#define AM_REG_RTC_INTEN_OF_S                        2
+#define AM_REG_RTC_INTEN_OF_M                        0x00000004
+#define AM_REG_RTC_INTEN_OF(n)                       (((uint32_t)(n) << 2) & 0x00000004)
+
+// Autocalibration Complete interrupt
+#define AM_REG_RTC_INTEN_ACC_S                       1
+#define AM_REG_RTC_INTEN_ACC_M                       0x00000002
+#define AM_REG_RTC_INTEN_ACC(n)                      (((uint32_t)(n) << 1) & 0x00000002)
+
+// Autocalibration Fail interrupt
+#define AM_REG_RTC_INTEN_ACF_S                       0
+#define AM_REG_RTC_INTEN_ACF_M                       0x00000001
+#define AM_REG_RTC_INTEN_ACF(n)                      (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RTC_INTSTAT - RTC Interrupt Register: Status
+//
+//*****************************************************************************
+// RTC Alarm interrupt
+#define AM_REG_RTC_INTSTAT_ALM_S                     3
+#define AM_REG_RTC_INTSTAT_ALM_M                     0x00000008
+#define AM_REG_RTC_INTSTAT_ALM(n)                    (((uint32_t)(n) << 3) & 0x00000008)
+
+// XT Oscillator Fail interrupt
+#define AM_REG_RTC_INTSTAT_OF_S                      2
+#define AM_REG_RTC_INTSTAT_OF_M                      0x00000004
+#define AM_REG_RTC_INTSTAT_OF(n)                     (((uint32_t)(n) << 2) & 0x00000004)
+
+// Autocalibration Complete interrupt
+#define AM_REG_RTC_INTSTAT_ACC_S                     1
+#define AM_REG_RTC_INTSTAT_ACC_M                     0x00000002
+#define AM_REG_RTC_INTSTAT_ACC(n)                    (((uint32_t)(n) << 1) & 0x00000002)
+
+// Autocalibration Fail interrupt
+#define AM_REG_RTC_INTSTAT_ACF_S                     0
+#define AM_REG_RTC_INTSTAT_ACF_M                     0x00000001
+#define AM_REG_RTC_INTSTAT_ACF(n)                    (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RTC_INTCLR - RTC Interrupt Register: Clear
+//
+//*****************************************************************************
+// RTC Alarm interrupt
+#define AM_REG_RTC_INTCLR_ALM_S                      3
+#define AM_REG_RTC_INTCLR_ALM_M                      0x00000008
+#define AM_REG_RTC_INTCLR_ALM(n)                     (((uint32_t)(n) << 3) & 0x00000008)
+
+// XT Oscillator Fail interrupt
+#define AM_REG_RTC_INTCLR_OF_S                       2
+#define AM_REG_RTC_INTCLR_OF_M                       0x00000004
+#define AM_REG_RTC_INTCLR_OF(n)                      (((uint32_t)(n) << 2) & 0x00000004)
+
+// Autocalibration Complete interrupt
+#define AM_REG_RTC_INTCLR_ACC_S                      1
+#define AM_REG_RTC_INTCLR_ACC_M                      0x00000002
+#define AM_REG_RTC_INTCLR_ACC(n)                     (((uint32_t)(n) << 1) & 0x00000002)
+
+// Autocalibration Fail interrupt
+#define AM_REG_RTC_INTCLR_ACF_S                      0
+#define AM_REG_RTC_INTCLR_ACF_M                      0x00000001
+#define AM_REG_RTC_INTCLR_ACF(n)                     (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RTC_INTSET - RTC Interrupt Register: Set
+//
+//*****************************************************************************
+// RTC Alarm interrupt
+#define AM_REG_RTC_INTSET_ALM_S                      3
+#define AM_REG_RTC_INTSET_ALM_M                      0x00000008
+#define AM_REG_RTC_INTSET_ALM(n)                     (((uint32_t)(n) << 3) & 0x00000008)
+
+// XT Oscillator Fail interrupt
+#define AM_REG_RTC_INTSET_OF_S                       2
+#define AM_REG_RTC_INTSET_OF_M                       0x00000004
+#define AM_REG_RTC_INTSET_OF(n)                      (((uint32_t)(n) << 2) & 0x00000004)
+
+// Autocalibration Complete interrupt
+#define AM_REG_RTC_INTSET_ACC_S                      1
+#define AM_REG_RTC_INTSET_ACC_M                      0x00000002
+#define AM_REG_RTC_INTSET_ACC(n)                     (((uint32_t)(n) << 1) & 0x00000002)
+
+// Autocalibration Fail interrupt
+#define AM_REG_RTC_INTSET_ACF_S                      0
+#define AM_REG_RTC_INTSET_ACF_M                      0x00000001
+#define AM_REG_RTC_INTSET_ACF(n)                     (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// RTC_CTRLOW - RTC Counters Lower
+//
+//*****************************************************************************
+// Hours Counter
+#define AM_REG_RTC_CTRLOW_CTRHR_S                    24
+#define AM_REG_RTC_CTRLOW_CTRHR_M                    0x3F000000
+#define AM_REG_RTC_CTRLOW_CTRHR(n)                   (((uint32_t)(n) << 24) & 0x3F000000)
+
+// Minutes Counter
+#define AM_REG_RTC_CTRLOW_CTRMIN_S                   16
+#define AM_REG_RTC_CTRLOW_CTRMIN_M                   0x007F0000
+#define AM_REG_RTC_CTRLOW_CTRMIN(n)                  (((uint32_t)(n) << 16) & 0x007F0000)
+
+// Seconds Counter
+#define AM_REG_RTC_CTRLOW_CTRSEC_S                   8
+#define AM_REG_RTC_CTRLOW_CTRSEC_M                   0x00007F00
+#define AM_REG_RTC_CTRLOW_CTRSEC(n)                  (((uint32_t)(n) << 8) & 0x00007F00)
+
+// 100ths of a second Counter
+#define AM_REG_RTC_CTRLOW_CTR100_S                   0
+#define AM_REG_RTC_CTRLOW_CTR100_M                   0x000000FF
+#define AM_REG_RTC_CTRLOW_CTR100(n)                  (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// RTC_CTRUP - RTC Counters Upper
+//
+//*****************************************************************************
+// Counter read error status
+#define AM_REG_RTC_CTRUP_CTERR_S                     31
+#define AM_REG_RTC_CTRUP_CTERR_M                     0x80000000
+#define AM_REG_RTC_CTRUP_CTERR(n)                    (((uint32_t)(n) << 31) & 0x80000000)
+#define AM_REG_RTC_CTRUP_CTERR_NOERR                 0x00000000
+#define AM_REG_RTC_CTRUP_CTERR_RDERR                 0x80000000
+
+// Century enable
+#define AM_REG_RTC_CTRUP_CEB_S                       28
+#define AM_REG_RTC_CTRUP_CEB_M                       0x10000000
+#define AM_REG_RTC_CTRUP_CEB(n)                      (((uint32_t)(n) << 28) & 0x10000000)
+#define AM_REG_RTC_CTRUP_CEB_DIS                     0x00000000
+#define AM_REG_RTC_CTRUP_CEB_EN                      0x10000000
+
+// Century
+#define AM_REG_RTC_CTRUP_CB_S                        27
+#define AM_REG_RTC_CTRUP_CB_M                        0x08000000
+#define AM_REG_RTC_CTRUP_CB(n)                       (((uint32_t)(n) << 27) & 0x08000000)
+#define AM_REG_RTC_CTRUP_CB_2000                     0x00000000
+#define AM_REG_RTC_CTRUP_CB_1900_2100                0x08000000
+
+// Weekdays Counter
+#define AM_REG_RTC_CTRUP_CTRWKDY_S                   24
+#define AM_REG_RTC_CTRUP_CTRWKDY_M                   0x07000000
+#define AM_REG_RTC_CTRUP_CTRWKDY(n)                  (((uint32_t)(n) << 24) & 0x07000000)
+
+// Years Counter
+#define AM_REG_RTC_CTRUP_CTRYR_S                     16
+#define AM_REG_RTC_CTRUP_CTRYR_M                     0x00FF0000
+#define AM_REG_RTC_CTRUP_CTRYR(n)                    (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Months Counter
+#define AM_REG_RTC_CTRUP_CTRMO_S                     8
+#define AM_REG_RTC_CTRUP_CTRMO_M                     0x00001F00
+#define AM_REG_RTC_CTRUP_CTRMO(n)                    (((uint32_t)(n) << 8) & 0x00001F00)
+
+// Date Counter
+#define AM_REG_RTC_CTRUP_CTRDATE_S                   0
+#define AM_REG_RTC_CTRUP_CTRDATE_M                   0x0000003F
+#define AM_REG_RTC_CTRUP_CTRDATE(n)                  (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// RTC_ALMLOW - RTC Alarms Lower
+//
+//*****************************************************************************
+// Hours Alarm
+#define AM_REG_RTC_ALMLOW_ALMHR_S                    24
+#define AM_REG_RTC_ALMLOW_ALMHR_M                    0x3F000000
+#define AM_REG_RTC_ALMLOW_ALMHR(n)                   (((uint32_t)(n) << 24) & 0x3F000000)
+
+// Minutes Alarm
+#define AM_REG_RTC_ALMLOW_ALMMIN_S                   16
+#define AM_REG_RTC_ALMLOW_ALMMIN_M                   0x007F0000
+#define AM_REG_RTC_ALMLOW_ALMMIN(n)                  (((uint32_t)(n) << 16) & 0x007F0000)
+
+// Seconds Alarm
+#define AM_REG_RTC_ALMLOW_ALMSEC_S                   8
+#define AM_REG_RTC_ALMLOW_ALMSEC_M                   0x00007F00
+#define AM_REG_RTC_ALMLOW_ALMSEC(n)                  (((uint32_t)(n) << 8) & 0x00007F00)
+
+// 100ths of a second Alarm
+#define AM_REG_RTC_ALMLOW_ALM100_S                   0
+#define AM_REG_RTC_ALMLOW_ALM100_M                   0x000000FF
+#define AM_REG_RTC_ALMLOW_ALM100(n)                  (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// RTC_ALMUP - RTC Alarms Upper
+//
+//*****************************************************************************
+// Weekdays Alarm
+#define AM_REG_RTC_ALMUP_ALMWKDY_S                   16
+#define AM_REG_RTC_ALMUP_ALMWKDY_M                   0x00070000
+#define AM_REG_RTC_ALMUP_ALMWKDY(n)                  (((uint32_t)(n) << 16) & 0x00070000)
+
+// Months Alarm
+#define AM_REG_RTC_ALMUP_ALMMO_S                     8
+#define AM_REG_RTC_ALMUP_ALMMO_M                     0x00001F00
+#define AM_REG_RTC_ALMUP_ALMMO(n)                    (((uint32_t)(n) << 8) & 0x00001F00)
+
+// Date Alarm
+#define AM_REG_RTC_ALMUP_ALMDATE_S                   0
+#define AM_REG_RTC_ALMUP_ALMDATE_M                   0x0000003F
+#define AM_REG_RTC_ALMUP_ALMDATE(n)                  (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// RTC_RTCCTL - RTC Control Register
+//
+//*****************************************************************************
+// Hours Counter mode
+#define AM_REG_RTC_RTCCTL_HR1224_S                   5
+#define AM_REG_RTC_RTCCTL_HR1224_M                   0x00000020
+#define AM_REG_RTC_RTCCTL_HR1224(n)                  (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_RTC_RTCCTL_HR1224_24HR                0x00000000
+#define AM_REG_RTC_RTCCTL_HR1224_12HR                0x00000020
+
+// RTC input clock control
+#define AM_REG_RTC_RTCCTL_RSTOP_S                    4
+#define AM_REG_RTC_RTCCTL_RSTOP_M                    0x00000010
+#define AM_REG_RTC_RTCCTL_RSTOP(n)                   (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_RTC_RTCCTL_RSTOP_RUN                  0x00000000
+#define AM_REG_RTC_RTCCTL_RSTOP_STOP                 0x00000010
+
+// Alarm repeat interval
+#define AM_REG_RTC_RTCCTL_RPT_S                      1
+#define AM_REG_RTC_RTCCTL_RPT_M                      0x0000000E
+#define AM_REG_RTC_RTCCTL_RPT(n)                     (((uint32_t)(n) << 1) & 0x0000000E)
+#define AM_REG_RTC_RTCCTL_RPT_DIS                    0x00000000
+#define AM_REG_RTC_RTCCTL_RPT_YEAR                   0x00000002
+#define AM_REG_RTC_RTCCTL_RPT_MONTH                  0x00000004
+#define AM_REG_RTC_RTCCTL_RPT_WEEK                   0x00000006
+#define AM_REG_RTC_RTCCTL_RPT_DAY                    0x00000008
+#define AM_REG_RTC_RTCCTL_RPT_HR                     0x0000000A
+#define AM_REG_RTC_RTCCTL_RPT_MIN                    0x0000000C
+#define AM_REG_RTC_RTCCTL_RPT_SEC                    0x0000000E
+
+// Counter write control
+#define AM_REG_RTC_RTCCTL_WRTC_S                     0
+#define AM_REG_RTC_RTCCTL_WRTC_M                     0x00000001
+#define AM_REG_RTC_RTCCTL_WRTC(n)                    (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_RTC_RTCCTL_WRTC_DIS                   0x00000000
+#define AM_REG_RTC_RTCCTL_WRTC_EN                    0x00000001
+
+#endif // AM_REG_RTC_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h
new file mode 100644
index 0000000000..4a00cc21d5
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h
@@ -0,0 +1,653 @@
+//*****************************************************************************
+//
+//  am_reg_sysctrl.h
+//! @file
+//!
+//! @brief Register macros for the SYSCTRL module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_SYSCTRL_H
+#define AM_REG_SYSCTRL_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_SYSCTRL_NUM_MODULES                   1
+#define AM_REG_SYSCTRLn(n) \
+    (REG_SYSCTRL_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_SYSCTRL_ICSR_O                        0xE000ED04
+#define AM_REG_SYSCTRL_VTOR_O                        0xE000ED08
+#define AM_REG_SYSCTRL_AIRCR_O                       0xE000ED0C
+#define AM_REG_SYSCTRL_SCR_O                         0xE000ED10
+#define AM_REG_SYSCTRL_CCR_O                         0xE000ED14
+#define AM_REG_SYSCTRL_SHPR1_O                       0xE000ED18
+#define AM_REG_SYSCTRL_SHPR2_O                       0xE000ED1C
+#define AM_REG_SYSCTRL_SHPR3_O                       0xE000ED20
+#define AM_REG_SYSCTRL_SHCSR_O                       0xE000ED24
+#define AM_REG_SYSCTRL_CFSR_O                        0xE000ED28
+#define AM_REG_SYSCTRL_HFSR_O                        0xE000ED2C
+#define AM_REG_SYSCTRL_MMFAR_O                       0xE000ED34
+#define AM_REG_SYSCTRL_BFAR_O                        0xE000ED38
+#define AM_REG_SYSCTRL_CPACR_O                       0xE000ED88
+#define AM_REG_SYSCTRL_DEMCR_O                       0xE000EDFC
+#define AM_REG_SYSCTRL_STIR_O                        0xE000EF00
+#define AM_REG_SYSCTRL_FPCCR_O                       0xE000EF34
+#define AM_REG_SYSCTRL_FPCAR_O                       0xE000EF38
+#define AM_REG_SYSCTRL_FPDSCR_O                      0xE000EF3C
+
+//*****************************************************************************
+//
+// SYSCTRL_ICSR - Interrupt Control and State Register
+//
+//*****************************************************************************
+// Pend an NMI exception.
+#define AM_REG_SYSCTRL_ICSR_NMIPENDSET_S             31
+#define AM_REG_SYSCTRL_ICSR_NMIPENDSET_M             0x80000000
+#define AM_REG_SYSCTRL_ICSR_NMIPENDSET(n)            (((uint32_t)(n) << 31) & 0x80000000)
+
+// Set the PendSV interrupt as pending.
+#define AM_REG_SYSCTRL_ICSR_PENDSVSET_S              28
+#define AM_REG_SYSCTRL_ICSR_PENDSVSET_M              0x10000000
+#define AM_REG_SYSCTRL_ICSR_PENDSVSET(n)             (((uint32_t)(n) << 28) & 0x10000000)
+
+// Remove the pending status of the PendSV exception.
+#define AM_REG_SYSCTRL_ICSR_PENDSVCLR_S              27
+#define AM_REG_SYSCTRL_ICSR_PENDSVCLR_M              0x08000000
+#define AM_REG_SYSCTRL_ICSR_PENDSVCLR(n)             (((uint32_t)(n) << 27) & 0x08000000)
+
+// Set the SysTick exception as pending.
+#define AM_REG_SYSCTRL_ICSR_PENDSTSET_S              26
+#define AM_REG_SYSCTRL_ICSR_PENDSTSET_M              0x04000000
+#define AM_REG_SYSCTRL_ICSR_PENDSTSET(n)             (((uint32_t)(n) << 26) & 0x04000000)
+
+// Remove the pending status of the SysTick exception.
+#define AM_REG_SYSCTRL_ICSR_PENDSTCLR_S              25
+#define AM_REG_SYSCTRL_ICSR_PENDSTCLR_M              0x02000000
+#define AM_REG_SYSCTRL_ICSR_PENDSTCLR(n)             (((uint32_t)(n) << 25) & 0x02000000)
+
+// Indicates whether a pending exception will be serviced on exit from debug
+// halt state.
+#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT_S             23
+#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT_M             0x00800000
+#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT(n)            (((uint32_t)(n) << 23) & 0x00800000)
+
+// Indicates whether an external interrupt, generated by the NVIC, is pending.
+#define AM_REG_SYSCTRL_ICSR_ISRPENDING_S             22
+#define AM_REG_SYSCTRL_ICSR_ISRPENDING_M             0x00400000
+#define AM_REG_SYSCTRL_ICSR_ISRPENDING(n)            (((uint32_t)(n) << 22) & 0x00400000)
+
+// The exception number of the highest priority pending exception.
+#define AM_REG_SYSCTRL_ICSR_VECTPENDING_S            12
+#define AM_REG_SYSCTRL_ICSR_VECTPENDING_M            0x001FF000
+#define AM_REG_SYSCTRL_ICSR_VECTPENDING(n)           (((uint32_t)(n) << 12) & 0x001FF000)
+
+// Indicates whether there is an active exception other than the exception shown
+// by IPSR.
+#define AM_REG_SYSCTRL_ICSR_RETTOBASE_S              11
+#define AM_REG_SYSCTRL_ICSR_RETTOBASE_M              0x00000800
+#define AM_REG_SYSCTRL_ICSR_RETTOBASE(n)             (((uint32_t)(n) << 11) & 0x00000800)
+
+// The exception number of the current executing exception.
+#define AM_REG_SYSCTRL_ICSR_VECTACTIVE_S             0
+#define AM_REG_SYSCTRL_ICSR_VECTACTIVE_M             0x000001FF
+#define AM_REG_SYSCTRL_ICSR_VECTACTIVE(n)            (((uint32_t)(n) << 0) & 0x000001FF)
+
+//*****************************************************************************
+//
+// SYSCTRL_VTOR - Vector Table Offset Register.
+//
+//*****************************************************************************
+// Vector table base address.
+#define AM_REG_SYSCTRL_VTOR_VALUE_S                  0
+#define AM_REG_SYSCTRL_VTOR_VALUE_M                  0xFFFFFFFF
+#define AM_REG_SYSCTRL_VTOR_VALUE(n)                 (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// SYSCTRL_AIRCR - Application Interrupt and Reset Control Register.
+//
+//*****************************************************************************
+// Register writes must write 0x5FA to this field, otherwise the write is
+// ignored.
+#define AM_REG_SYSCTRL_AIRCR_VECTKEY_S               16
+#define AM_REG_SYSCTRL_AIRCR_VECTKEY_M               0xFFFF0000
+#define AM_REG_SYSCTRL_AIRCR_VECTKEY(n)              (((uint32_t)(n) << 16) & 0xFFFF0000)
+
+// Indicates endianness of memory architecture. (Little = 0, Big = 1)
+#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS_S            15
+#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS_M            0x00008000
+#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS(n)           (((uint32_t)(n) << 15) & 0x00008000)
+
+// Priority grouping, indicates the binary point position.
+#define AM_REG_SYSCTRL_AIRCR_PRIGROUP_S              8
+#define AM_REG_SYSCTRL_AIRCR_PRIGROUP_M              0x00000700
+#define AM_REG_SYSCTRL_AIRCR_PRIGROUP(n)             (((uint32_t)(n) << 8) & 0x00000700)
+
+// Writing a 1 to this bit reqests a local reset.
+#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ_S           2
+#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ_M           0x00000004
+#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ(n)          (((uint32_t)(n) << 2) & 0x00000004)
+
+// Writing a 1 to this bit clears all active state information for fixed and
+// configurable exceptions.
+#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE_S         1
+#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE_M         0x00000002
+#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE(n)        (((uint32_t)(n) << 1) & 0x00000002)
+
+// Writing a 1 to this bit causes a local system reset.
+#define AM_REG_SYSCTRL_AIRCR_VECTRESET_S             0
+#define AM_REG_SYSCTRL_AIRCR_VECTRESET_M             0x00000001
+#define AM_REG_SYSCTRL_AIRCR_VECTRESET(n)            (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// SYSCTRL_SCR - System Control Register.
+//
+//*****************************************************************************
+// Determines whether a pending interrupt is a wakeup event.
+#define AM_REG_SYSCTRL_SCR_SEVONPEND_S               4
+#define AM_REG_SYSCTRL_SCR_SEVONPEND_M               0x00000010
+#define AM_REG_SYSCTRL_SCR_SEVONPEND(n)              (((uint32_t)(n) << 4) & 0x00000010)
+
+// Determines whether the sleep mode should be regular or deep sleep
+#define AM_REG_SYSCTRL_SCR_SLEEPDEEP_S               2
+#define AM_REG_SYSCTRL_SCR_SLEEPDEEP_M               0x00000004
+#define AM_REG_SYSCTRL_SCR_SLEEPDEEP(n)              (((uint32_t)(n) << 2) & 0x00000004)
+
+// Determines whether the processor shoudl automatically sleep when an ISR
+// returns to the base-level.
+#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT_S             1
+#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT_M             0x00000002
+#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT(n)            (((uint32_t)(n) << 1) & 0x00000002)
+
+//*****************************************************************************
+//
+// SYSCTRL_CCR - Configuration and Control Register.
+//
+//*****************************************************************************
+// Set to force 8-byte alignment for the stack pointer.
+#define AM_REG_SYSCTRL_CCR_STKALIGN_S                9
+#define AM_REG_SYSCTRL_CCR_STKALIGN_M                0x00000200
+#define AM_REG_SYSCTRL_CCR_STKALIGN(n)               (((uint32_t)(n) << 9) & 0x00000200)
+
+// Set to ignore precise data access faults during hard fault handlers.
+#define AM_REG_SYSCTRL_CCR_BFHFNMIGN_S               8
+#define AM_REG_SYSCTRL_CCR_BFHFNMIGN_M               0x00000100
+#define AM_REG_SYSCTRL_CCR_BFHFNMIGN(n)              (((uint32_t)(n) << 8) & 0x00000100)
+
+// Set to enable trapping on divide-by-zero.
+#define AM_REG_SYSCTRL_CCR_DIV0TRP_S                 4
+#define AM_REG_SYSCTRL_CCR_DIV0TRP_M                 0x00000010
+#define AM_REG_SYSCTRL_CCR_DIV0TRP(n)                (((uint32_t)(n) << 4) & 0x00000010)
+
+// Set to enable trapping of unaligned word or halfword accesses.
+#define AM_REG_SYSCTRL_CCR_UNALIGNTRP_S              3
+#define AM_REG_SYSCTRL_CCR_UNALIGNTRP_M              0x00000008
+#define AM_REG_SYSCTRL_CCR_UNALIGNTRP(n)             (((uint32_t)(n) << 3) & 0x00000008)
+
+// Set to allow unpriveleged software to access the STIR
+#define AM_REG_SYSCTRL_CCR_USERSETMPEND_S            1
+#define AM_REG_SYSCTRL_CCR_USERSETMPEND_M            0x00000002
+#define AM_REG_SYSCTRL_CCR_USERSETMPEND(n)           (((uint32_t)(n) << 1) & 0x00000002)
+
+// Set to enable the processor to enter Thread mode at an execution priority
+// other than base level.
+#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA_S          0
+#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA_M          0x00000001
+#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA(n)         (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// SYSCTRL_SHPR1 - System Handler Priority Register 1.
+//
+//*****************************************************************************
+// Reserved for priority of system handler 7.
+#define AM_REG_SYSCTRL_SHPR1_PRI_7_S                 24
+#define AM_REG_SYSCTRL_SHPR1_PRI_7_M                 0xFF000000
+#define AM_REG_SYSCTRL_SHPR1_PRI_7(n)                (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority of system handler 6, UsageFault.
+#define AM_REG_SYSCTRL_SHPR1_PRI_6_S                 16
+#define AM_REG_SYSCTRL_SHPR1_PRI_6_M                 0x00FF0000
+#define AM_REG_SYSCTRL_SHPR1_PRI_6(n)                (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Priority of system handler 5, BusFault.
+#define AM_REG_SYSCTRL_SHPR1_PRI_5_S                 8
+#define AM_REG_SYSCTRL_SHPR1_PRI_5_M                 0x0000FF00
+#define AM_REG_SYSCTRL_SHPR1_PRI_5(n)                (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority of system handler 4, MemManage.
+#define AM_REG_SYSCTRL_SHPR1_PRI_4_S                 0
+#define AM_REG_SYSCTRL_SHPR1_PRI_4_M                 0x000000FF
+#define AM_REG_SYSCTRL_SHPR1_PRI_4(n)                (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// SYSCTRL_SHPR2 - System Handler Priority Register 2.
+//
+//*****************************************************************************
+// Priority of system handler 11, SVCall.
+#define AM_REG_SYSCTRL_SHPR2_PRI_11_S                24
+#define AM_REG_SYSCTRL_SHPR2_PRI_11_M                0xFF000000
+#define AM_REG_SYSCTRL_SHPR2_PRI_11(n)               (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Reserved for priority of system handler 10.
+#define AM_REG_SYSCTRL_SHPR2_PRI_10_S                16
+#define AM_REG_SYSCTRL_SHPR2_PRI_10_M                0x00FF0000
+#define AM_REG_SYSCTRL_SHPR2_PRI_10(n)               (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Reserved for priority of system handler 9.
+#define AM_REG_SYSCTRL_SHPR2_PRI_9_S                 8
+#define AM_REG_SYSCTRL_SHPR2_PRI_9_M                 0x0000FF00
+#define AM_REG_SYSCTRL_SHPR2_PRI_9(n)                (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Reserved for priority of system handler 8.
+#define AM_REG_SYSCTRL_SHPR2_PRI_8_S                 0
+#define AM_REG_SYSCTRL_SHPR2_PRI_8_M                 0x000000FF
+#define AM_REG_SYSCTRL_SHPR2_PRI_8(n)                (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// SYSCTRL_SHPR3 - System Handler Priority Register 3.
+//
+//*****************************************************************************
+// Priority of system handler 15, SysTick.
+#define AM_REG_SYSCTRL_SHPR3_PRI_15_S                24
+#define AM_REG_SYSCTRL_SHPR3_PRI_15_M                0xFF000000
+#define AM_REG_SYSCTRL_SHPR3_PRI_15(n)               (((uint32_t)(n) << 24) & 0xFF000000)
+
+// Priority of system handler 14, PendSV.
+#define AM_REG_SYSCTRL_SHPR3_PRI_14_S                16
+#define AM_REG_SYSCTRL_SHPR3_PRI_14_M                0x00FF0000
+#define AM_REG_SYSCTRL_SHPR3_PRI_14(n)               (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// Reserved for priority of system handler 13.
+#define AM_REG_SYSCTRL_SHPR3_PRI_13_S                8
+#define AM_REG_SYSCTRL_SHPR3_PRI_13_M                0x0000FF00
+#define AM_REG_SYSCTRL_SHPR3_PRI_13(n)               (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// Priority of system handler 12, DebugMonitor.
+#define AM_REG_SYSCTRL_SHPR3_PRI_12_S                0
+#define AM_REG_SYSCTRL_SHPR3_PRI_12_M                0x000000FF
+#define AM_REG_SYSCTRL_SHPR3_PRI_12(n)               (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// SYSCTRL_SHCSR - System Handler Control and State Register.
+//
+//*****************************************************************************
+// Set to enable UsageFault.
+#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA_S         18
+#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA_M         0x00040000
+#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA(n)        (((uint32_t)(n) << 18) & 0x00040000)
+
+// Set to enable BusFault.
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA_S           17
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA_M           0x00020000
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA(n)          (((uint32_t)(n) << 17) & 0x00020000)
+
+// Set to enable MemManageFault.
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA_S           16
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA_M           0x00010000
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Set to pend the SVCall exception.
+#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED_S          15
+#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED_M          0x00008000
+#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED(n)         (((uint32_t)(n) << 15) & 0x00008000)
+
+// Set to pend the BusFault exception.
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED_S        14
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED_M        0x00004000
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED(n)       (((uint32_t)(n) << 14) & 0x00004000)
+
+// Set to pend the MemManageFault exception.
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED_S        13
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED_M        0x00002000
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED(n)       (((uint32_t)(n) << 13) & 0x00002000)
+
+// Set to pend the UsageFault exception.
+#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED_S        12
+#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED_M        0x00001000
+#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED(n)       (((uint32_t)(n) << 12) & 0x00001000)
+
+// Set when SysTick is active.
+#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT_S            11
+#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT_M            0x00000800
+#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT(n)           (((uint32_t)(n) << 11) & 0x00000800)
+
+// Set when PendSV is active.
+#define AM_REG_SYSCTRL_SHCSR_PENDSVACT_S             10
+#define AM_REG_SYSCTRL_SHCSR_PENDSVACT_M             0x00000400
+#define AM_REG_SYSCTRL_SHCSR_PENDSVACT(n)            (((uint32_t)(n) << 10) & 0x00000400)
+
+// Set when Monitor is active.
+#define AM_REG_SYSCTRL_SHCSR_MONITORACT_S            8
+#define AM_REG_SYSCTRL_SHCSR_MONITORACT_M            0x00000100
+#define AM_REG_SYSCTRL_SHCSR_MONITORACT(n)           (((uint32_t)(n) << 8) & 0x00000100)
+
+// Set when SVCall is active.
+#define AM_REG_SYSCTRL_SHCSR_SVCALLACT_S             7
+#define AM_REG_SYSCTRL_SHCSR_SVCALLACT_M             0x00000080
+#define AM_REG_SYSCTRL_SHCSR_SVCALLACT(n)            (((uint32_t)(n) << 7) & 0x00000080)
+
+// Set when UsageFault is active.
+#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT_S           3
+#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT_M           0x00000008
+#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT(n)          (((uint32_t)(n) << 3) & 0x00000008)
+
+// Set when BusFault is active.
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT_S           1
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT_M           0x00000002
+#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT(n)          (((uint32_t)(n) << 1) & 0x00000002)
+
+// Set when MemManageFault is active.
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT_S           0
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT_M           0x00000001
+#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT(n)          (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// SYSCTRL_CFSR - Configurable Fault Status Register.
+//
+//*****************************************************************************
+// Divide by zero error has occurred.
+#define AM_REG_SYSCTRL_CFSR_DIVBYZERO_S              25
+#define AM_REG_SYSCTRL_CFSR_DIVBYZERO_M              0x02000000
+#define AM_REG_SYSCTRL_CFSR_DIVBYZERO(n)             (((uint32_t)(n) << 25) & 0x02000000)
+
+// Unaligned access error has occurred.
+#define AM_REG_SYSCTRL_CFSR_UNALIGNED_S              24
+#define AM_REG_SYSCTRL_CFSR_UNALIGNED_M              0x01000000
+#define AM_REG_SYSCTRL_CFSR_UNALIGNED(n)             (((uint32_t)(n) << 24) & 0x01000000)
+
+// A coprocessor access error has occurred.
+#define AM_REG_SYSCTRL_CFSR_NOCP_S                   19
+#define AM_REG_SYSCTRL_CFSR_NOCP_M                   0x00080000
+#define AM_REG_SYSCTRL_CFSR_NOCP(n)                  (((uint32_t)(n) << 19) & 0x00080000)
+
+// An integrity check error has occurred on EXC_RETURN.
+#define AM_REG_SYSCTRL_CFSR_INVPC_S                  18
+#define AM_REG_SYSCTRL_CFSR_INVPC_M                  0x00040000
+#define AM_REG_SYSCTRL_CFSR_INVPC(n)                 (((uint32_t)(n) << 18) & 0x00040000)
+
+// Instruction executed with invalid EPSR.T or EPSR.IT field.
+#define AM_REG_SYSCTRL_CFSR_INVSTATE_S               17
+#define AM_REG_SYSCTRL_CFSR_INVSTATE_M               0x00020000
+#define AM_REG_SYSCTRL_CFSR_INVSTATE(n)              (((uint32_t)(n) << 17) & 0x00020000)
+
+// Processor attempted to execute an undefined instruction.
+#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR_S             16
+#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR_M             0x00010000
+#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR(n)            (((uint32_t)(n) << 16) & 0x00010000)
+
+// BFAR has valid contents.
+#define AM_REG_SYSCTRL_CFSR_BFARVALID_S              15
+#define AM_REG_SYSCTRL_CFSR_BFARVALID_M              0x00008000
+#define AM_REG_SYSCTRL_CFSR_BFARVALID(n)             (((uint32_t)(n) << 15) & 0x00008000)
+
+// A bus fault occurred during FP lazy state preservation.
+#define AM_REG_SYSCTRL_CFSR_LSPERR_S                 13
+#define AM_REG_SYSCTRL_CFSR_LSPERR_M                 0x00002000
+#define AM_REG_SYSCTRL_CFSR_LSPERR(n)                (((uint32_t)(n) << 13) & 0x00002000)
+
+// A derived bus fault has occurred on exception entry.
+#define AM_REG_SYSCTRL_CFSR_STKERR_S                 12
+#define AM_REG_SYSCTRL_CFSR_STKERR_M                 0x00001000
+#define AM_REG_SYSCTRL_CFSR_STKERR(n)                (((uint32_t)(n) << 12) & 0x00001000)
+
+// A derived bus fault has occurred on exception return.
+#define AM_REG_SYSCTRL_CFSR_UNSTKERR_S               11
+#define AM_REG_SYSCTRL_CFSR_UNSTKERR_M               0x00000800
+#define AM_REG_SYSCTRL_CFSR_UNSTKERR(n)              (((uint32_t)(n) << 11) & 0x00000800)
+
+// Imprecise data access error has occurred.
+#define AM_REG_SYSCTRL_CFSR_IMPRECISERR_S            10
+#define AM_REG_SYSCTRL_CFSR_IMPRECISERR_M            0x00000400
+#define AM_REG_SYSCTRL_CFSR_IMPRECISERR(n)           (((uint32_t)(n) << 10) & 0x00000400)
+
+// A precise data access has occurrred. The faulting address is in BFAR.
+#define AM_REG_SYSCTRL_CFSR_PRECISERR_S              9
+#define AM_REG_SYSCTRL_CFSR_PRECISERR_M              0x00000200
+#define AM_REG_SYSCTRL_CFSR_PRECISERR(n)             (((uint32_t)(n) << 9) & 0x00000200)
+
+// A bus fault on an instruction prefetch has occurred.
+#define AM_REG_SYSCTRL_CFSR_IBUSERR_S                8
+#define AM_REG_SYSCTRL_CFSR_IBUSERR_M                0x00000100
+#define AM_REG_SYSCTRL_CFSR_IBUSERR(n)               (((uint32_t)(n) << 8) & 0x00000100)
+
+// MMAR has valid contents.
+#define AM_REG_SYSCTRL_CFSR_MMARVALID_S              7
+#define AM_REG_SYSCTRL_CFSR_MMARVALID_M              0x00000080
+#define AM_REG_SYSCTRL_CFSR_MMARVALID(n)             (((uint32_t)(n) << 7) & 0x00000080)
+
+// MemManage fault occurred during FP lazy state preservation.
+#define AM_REG_SYSCTRL_CFSR_MLSPERR_S                5
+#define AM_REG_SYSCTRL_CFSR_MLSPERR_M                0x00000020
+#define AM_REG_SYSCTRL_CFSR_MLSPERR(n)               (((uint32_t)(n) << 5) & 0x00000020)
+
+// Derived MemManage fault occurred on exception entry.
+#define AM_REG_SYSCTRL_CFSR_MSTKERR_S                4
+#define AM_REG_SYSCTRL_CFSR_MSTKERR_M                0x00000010
+#define AM_REG_SYSCTRL_CFSR_MSTKERR(n)               (((uint32_t)(n) << 4) & 0x00000010)
+
+// Derived MemManage fault occurred on exception return.
+#define AM_REG_SYSCTRL_CFSR_MUNSTKER_S               3
+#define AM_REG_SYSCTRL_CFSR_MUNSTKER_M               0x00000008
+#define AM_REG_SYSCTRL_CFSR_MUNSTKER(n)              (((uint32_t)(n) << 3) & 0x00000008)
+
+// Data access violation. Address is in MMAR.
+#define AM_REG_SYSCTRL_CFSR_DACCVIOL_S               1
+#define AM_REG_SYSCTRL_CFSR_DACCVIOL_M               0x00000002
+#define AM_REG_SYSCTRL_CFSR_DACCVIOL(n)              (((uint32_t)(n) << 1) & 0x00000002)
+
+// MPU or Execute Never default memory map access violation.
+#define AM_REG_SYSCTRL_CFSR_IACCVIOL_S               0
+#define AM_REG_SYSCTRL_CFSR_IACCVIOL_M               0x00000001
+#define AM_REG_SYSCTRL_CFSR_IACCVIOL(n)              (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// SYSCTRL_HFSR - Hard Fault Status Register.
+//
+//*****************************************************************************
+// Debug event has occurred.
+#define AM_REG_SYSCTRL_HFSR_DEBUGEVT_S               31
+#define AM_REG_SYSCTRL_HFSR_DEBUGEVT_M               0x80000000
+#define AM_REG_SYSCTRL_HFSR_DEBUGEVT(n)              (((uint32_t)(n) << 31) & 0x80000000)
+
+// Processor has elevated a configurable-priority fault to a HardFault.
+#define AM_REG_SYSCTRL_HFSR_FORCED_S                 30
+#define AM_REG_SYSCTRL_HFSR_FORCED_M                 0x40000000
+#define AM_REG_SYSCTRL_HFSR_FORCED(n)                (((uint32_t)(n) << 30) & 0x40000000)
+
+// Vector table read fault has occurred.
+#define AM_REG_SYSCTRL_HFSR_VECTTBL_S                1
+#define AM_REG_SYSCTRL_HFSR_VECTTBL_M                0x00000002
+#define AM_REG_SYSCTRL_HFSR_VECTTBL(n)               (((uint32_t)(n) << 1) & 0x00000002)
+
+//*****************************************************************************
+//
+// SYSCTRL_MMFAR - MemManage Fault Address Register.
+//
+//*****************************************************************************
+// Address of the memory location that caused an MMU fault.
+#define AM_REG_SYSCTRL_MMFAR_ADDRESS_S               0
+#define AM_REG_SYSCTRL_MMFAR_ADDRESS_M               0xFFFFFFFF
+#define AM_REG_SYSCTRL_MMFAR_ADDRESS(n)              (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// SYSCTRL_BFAR - Bus Fault Address Register.
+//
+//*****************************************************************************
+// Address of the memory location that caused an Bus fault.
+#define AM_REG_SYSCTRL_BFAR_ADDRESS_S                0
+#define AM_REG_SYSCTRL_BFAR_ADDRESS_M                0xFFFFFFFF
+#define AM_REG_SYSCTRL_BFAR_ADDRESS(n)               (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// SYSCTRL_CPACR - Coprocessor Access Control Register.
+//
+//*****************************************************************************
+// Access priveleges for the Floating point unit. Must always match CP10.
+#define AM_REG_SYSCTRL_CPACR_CP11_S                  22
+#define AM_REG_SYSCTRL_CPACR_CP11_M                  0x00C00000
+#define AM_REG_SYSCTRL_CPACR_CP11(n)                 (((uint32_t)(n) << 22) & 0x00C00000)
+
+// Access priveleges for the Floating point unit. Must always match CP11.
+#define AM_REG_SYSCTRL_CPACR_CP10_S                  20
+#define AM_REG_SYSCTRL_CPACR_CP10_M                  0x00300000
+#define AM_REG_SYSCTRL_CPACR_CP10(n)                 (((uint32_t)(n) << 20) & 0x00300000)
+
+//*****************************************************************************
+//
+// SYSCTRL_DEMCR - Debug Exception and Monitor Control Register
+//
+//*****************************************************************************
+// Global enable for all DWT and ITM features.
+#define AM_REG_SYSCTRL_DEMCR_TRCENA_S                24
+#define AM_REG_SYSCTRL_DEMCR_TRCENA_M                0x01000000
+#define AM_REG_SYSCTRL_DEMCR_TRCENA(n)               (((uint32_t)(n) << 24) & 0x01000000)
+
+//*****************************************************************************
+//
+// SYSCTRL_STIR - Software Triggered Interrupt Register
+//
+//*****************************************************************************
+// Vector number of the interrupt that should be triggered.
+#define AM_REG_SYSCTRL_STIR_INTID_S                  0
+#define AM_REG_SYSCTRL_STIR_INTID_M                  0xFFFFFFFF
+#define AM_REG_SYSCTRL_STIR_INTID(n)                 (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// SYSCTRL_FPCCR - Floating-Point Context Control Register.
+//
+//*****************************************************************************
+// Set to enable automatic saving of FP registers on exception entry.
+#define AM_REG_SYSCTRL_FPCCR_ASPEN_S                 31
+#define AM_REG_SYSCTRL_FPCCR_ASPEN_M                 0x80000000
+#define AM_REG_SYSCTRL_FPCCR_ASPEN(n)                (((uint32_t)(n) << 31) & 0x80000000)
+
+// Set to enable lazy context saving of FP registers on exception entry.
+#define AM_REG_SYSCTRL_FPCCR_LSPEN_S                 30
+#define AM_REG_SYSCTRL_FPCCR_LSPEN_M                 0x40000000
+#define AM_REG_SYSCTRL_FPCCR_LSPEN(n)                (((uint32_t)(n) << 30) & 0x40000000)
+
+// Able to set DebugMonitor exception to pending on last FP stack allocation.
+#define AM_REG_SYSCTRL_FPCCR_MONRDY_S                8
+#define AM_REG_SYSCTRL_FPCCR_MONRDY_M                0x00000100
+#define AM_REG_SYSCTRL_FPCCR_MONRDY(n)               (((uint32_t)(n) << 8) & 0x00000100)
+
+// Able to set BusFault exception to pending on last FP stack allocation.
+#define AM_REG_SYSCTRL_FPCCR_BFRDY_S                 6
+#define AM_REG_SYSCTRL_FPCCR_BFRDY_M                 0x00000040
+#define AM_REG_SYSCTRL_FPCCR_BFRDY(n)                (((uint32_t)(n) << 6) & 0x00000040)
+
+// Able to set MemManage exception to pending on last FP stack allocation.
+#define AM_REG_SYSCTRL_FPCCR_MMRDY_S                 5
+#define AM_REG_SYSCTRL_FPCCR_MMRDY_M                 0x00000020
+#define AM_REG_SYSCTRL_FPCCR_MMRDY(n)                (((uint32_t)(n) << 5) & 0x00000020)
+
+// Able to set HardFault exception to pending on last FP stack allocation.
+#define AM_REG_SYSCTRL_FPCCR_HFRDY_S                 4
+#define AM_REG_SYSCTRL_FPCCR_HFRDY_M                 0x00000010
+#define AM_REG_SYSCTRL_FPCCR_HFRDY(n)                (((uint32_t)(n) << 4) & 0x00000010)
+
+// Running from Thread mode on last FP stack allocation.
+#define AM_REG_SYSCTRL_FPCCR_THREAD_S                3
+#define AM_REG_SYSCTRL_FPCCR_THREAD_M                0x00000008
+#define AM_REG_SYSCTRL_FPCCR_THREAD(n)               (((uint32_t)(n) << 3) & 0x00000008)
+
+// Running from unprivileged mode on last FP stack allocation.
+#define AM_REG_SYSCTRL_FPCCR_USER_S                  1
+#define AM_REG_SYSCTRL_FPCCR_USER_M                  0x00000002
+#define AM_REG_SYSCTRL_FPCCR_USER(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// Lazy state preservation is active.
+#define AM_REG_SYSCTRL_FPCCR_LSPACT_S                0
+#define AM_REG_SYSCTRL_FPCCR_LSPACT_M                0x00000001
+#define AM_REG_SYSCTRL_FPCCR_LSPACT(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// SYSCTRL_FPCAR - Floating-Point Context Address Register.
+//
+//*****************************************************************************
+// Address of the unpopulated floating-point register space allocated on the
+// exception stack frame.
+#define AM_REG_SYSCTRL_FPCAR_ADDRESS_S               0
+#define AM_REG_SYSCTRL_FPCAR_ADDRESS_M               0xFFFFFFFF
+#define AM_REG_SYSCTRL_FPCAR_ADDRESS(n)              (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+
+//*****************************************************************************
+//
+// SYSCTRL_FPDSCR - Floating-Point Default Status Control Register.
+//
+//*****************************************************************************
+// Default value for FPSCR.AHP.
+#define AM_REG_SYSCTRL_FPDSCR_AHP_S                  26
+#define AM_REG_SYSCTRL_FPDSCR_AHP_M                  0x04000000
+#define AM_REG_SYSCTRL_FPDSCR_AHP(n)                 (((uint32_t)(n) << 26) & 0x04000000)
+
+// Default value for FPSCR.DN.
+#define AM_REG_SYSCTRL_FPDSCR_DN_S                   25
+#define AM_REG_SYSCTRL_FPDSCR_DN_M                   0x02000000
+#define AM_REG_SYSCTRL_FPDSCR_DN(n)                  (((uint32_t)(n) << 25) & 0x02000000)
+
+// Default value for FPSCR.FZ.
+#define AM_REG_SYSCTRL_FPDSCR_FZ_S                   24
+#define AM_REG_SYSCTRL_FPDSCR_FZ_M                   0x01000000
+#define AM_REG_SYSCTRL_FPDSCR_FZ(n)                  (((uint32_t)(n) << 24) & 0x01000000)
+
+// Default value for FPSCR.RMode.
+#define AM_REG_SYSCTRL_FPDSCR_RMODE_S                22
+#define AM_REG_SYSCTRL_FPDSCR_RMODE_M                0x00C00000
+#define AM_REG_SYSCTRL_FPDSCR_RMODE(n)               (((uint32_t)(n) << 22) & 0x00C00000)
+
+#endif // AM_REG_SYSCTRL_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h b/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h
new file mode 100644
index 0000000000..d68a8c4063
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h
@@ -0,0 +1,137 @@
+//*****************************************************************************
+//
+//  am_reg_systick.h
+//! @file
+//!
+//! @brief Register macros for the SYSTICK module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_SYSTICK_H
+#define AM_REG_SYSTICK_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_SYSTICK_NUM_MODULES                   1
+#define AM_REG_SYSTICKn(n) \
+    (REG_SYSTICK_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_SYSTICK_SYSTCSR_O                     0xE000E010
+#define AM_REG_SYSTICK_SYSTRVR_O                     0xE000E014
+#define AM_REG_SYSTICK_SYSTCVR_O                     0xE000E018
+#define AM_REG_SYSTICK_SYSTCALIB_O                   0xE000E01C
+
+//*****************************************************************************
+//
+// SYSTICK_SYSTCSR - SysTick Control and Status Register.
+//
+//*****************************************************************************
+// Returns 1 if timer counted to 0 since last time this was read.
+#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_S           16
+#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_M           0x00010000
+#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG(n)          (((uint32_t)(n) << 16) & 0x00010000)
+
+// Enables SysTick exception request. Software can use COUNTFLAG to determine if
+// SysTick has ever counted to zero. 0 = counting down to zero does not assert
+// the SysTick exception request; 1 = counting down to zero asserts the SysTick
+// exception request.
+#define AM_REG_SYSTICK_SYSTCSR_TICKINT_S             1
+#define AM_REG_SYSTICK_SYSTCSR_TICKINT_M             0x00000002
+#define AM_REG_SYSTICK_SYSTCSR_TICKINT(n)            (((uint32_t)(n) << 1) & 0x00000002)
+
+// Enables the counter. 0 = counter disabled; 1 = counter enabled.
+#define AM_REG_SYSTICK_SYSTCSR_ENABLE_S              0
+#define AM_REG_SYSTICK_SYSTCSR_ENABLE_M              0x00000001
+#define AM_REG_SYSTICK_SYSTCSR_ENABLE(n)             (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// SYSTICK_SYSTRVR - SysTick Reload Value Register.
+//
+//*****************************************************************************
+// Value to load into the SYSTCVR register when the counter is enabled and when
+// it reaches 0.
+#define AM_REG_SYSTICK_SYSTRVR_RELOAD_S              0
+#define AM_REG_SYSTICK_SYSTRVR_RELOAD_M              0x00FFFFFF
+#define AM_REG_SYSTICK_SYSTRVR_RELOAD(n)             (((uint32_t)(n) << 0) & 0x00FFFFFF)
+
+//*****************************************************************************
+//
+// SYSTICK_SYSTCVR - SysTick Current Value Register.
+//
+//*****************************************************************************
+// Reads return the current value of the SysTick counter. A write of any value
+// clears the field to 0, and also clears the SYSTCSR COUNTFLAG bit to 0.
+#define AM_REG_SYSTICK_SYSTCVR_CURRENT_S             0
+#define AM_REG_SYSTICK_SYSTCVR_CURRENT_M             0x00FFFFFF
+#define AM_REG_SYSTICK_SYSTCVR_CURRENT(n)            (((uint32_t)(n) << 0) & 0x00FFFFFF)
+
+//*****************************************************************************
+//
+// SYSTICK_SYSTCALIB - SysTick Calibration Value Register.
+//
+//*****************************************************************************
+// Indicates whether the device provides a reference clock to the processor. 0 =
+// reference clock provided; 1 = no reference clock provided. If your device
+// does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one
+// and ignores writes.
+#define AM_REG_SYSTICK_SYSTCALIB_NOREF_S             31
+#define AM_REG_SYSTICK_SYSTCALIB_NOREF_M             0x80000000
+#define AM_REG_SYSTICK_SYSTCALIB_NOREF(n)            (((uint32_t)(n) << 31) & 0x80000000)
+
+// Indicates whether the TENMS value is exact. 0 = TENMS value is exact; 1 =
+// TENMS value is inexact, or not given. An inexact TENMS value can affect the
+// suitability of SysTick as a software real time clock.
+#define AM_REG_SYSTICK_SYSTCALIB_SKEW_S              30
+#define AM_REG_SYSTICK_SYSTCALIB_SKEW_M              0x40000000
+#define AM_REG_SYSTICK_SYSTCALIB_SKEW(n)             (((uint32_t)(n) << 30) & 0x40000000)
+
+// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If
+// the value reads as zero, the calibration value is not known.
+#define AM_REG_SYSTICK_SYSTCALIB_TENMS_S             0
+#define AM_REG_SYSTICK_SYSTCALIB_TENMS_M             0x00FFFFFF
+#define AM_REG_SYSTICK_SYSTCALIB_TENMS(n)            (((uint32_t)(n) << 0) & 0x00FFFFFF)
+
+#endif // AM_REG_SYSTICK_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h b/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h
new file mode 100644
index 0000000000..e3719b60f8
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h
@@ -0,0 +1,164 @@
+//*****************************************************************************
+//
+//  am_reg_tpiu.h
+//! @file
+//!
+//! @brief Register macros for the TPIU module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_TPIU_H
+#define AM_REG_TPIU_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_TPIU_NUM_MODULES                      1
+#define AM_REG_TPIUn(n) \
+    (REG_TPIU_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_TPIU_SSPSR_O                          0xE0040000
+#define AM_REG_TPIU_CSPSR_O                          0xE0040004
+#define AM_REG_TPIU_ACPR_O                           0xE0040010
+#define AM_REG_TPIU_SPPR_O                           0xE00400F0
+#define AM_REG_TPIU_FFCR_O                           0xE0040304
+#define AM_REG_TPIU_ITCTRL_O                         0xE0040F00
+#define AM_REG_TPIU_TYPE_O                           0xE0040FC8
+
+//*****************************************************************************
+//
+// TPIU_SSPSR - Supported Parallel Port Sizes.
+//
+//*****************************************************************************
+// Parallel Port Width 1 supported
+#define AM_REG_TPIU_SSPSR_SWIDTH0_S                  0
+#define AM_REG_TPIU_SSPSR_SWIDTH0_M                  0x00000001
+#define AM_REG_TPIU_SSPSR_SWIDTH0(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// TPIU_CSPSR - Current Parallel Port Size.
+//
+//*****************************************************************************
+// One-hot representation of the current port width.
+#define AM_REG_TPIU_CSPSR_CWIDTH_S                   0
+#define AM_REG_TPIU_CSPSR_CWIDTH_M                   0xFFFFFFFF
+#define AM_REG_TPIU_CSPSR_CWIDTH(n)                  (((uint32_t)(n) << 0) & 0xFFFFFFFF)
+#define AM_REG_TPIU_CSPSR_CWIDTH_1BIT                0x00000001
+
+//*****************************************************************************
+//
+// TPIU_ACPR - Asynchronous Clock Prescaler.
+//
+//*****************************************************************************
+// Prescaler value for the baudrate of SWO.
+#define AM_REG_TPIU_ACPR_SWOSCALER_S                 0
+#define AM_REG_TPIU_ACPR_SWOSCALER_M                 0x0000FFFF
+#define AM_REG_TPIU_ACPR_SWOSCALER(n)                (((uint32_t)(n) << 0) & 0x0000FFFF)
+#define AM_REG_TPIU_ACPR_SWOSCALER_115200            0x00000033
+
+//*****************************************************************************
+//
+// TPIU_SPPR - Selected Pin Protocol.
+//
+//*****************************************************************************
+// Selects the protocol used for trace output.
+#define AM_REG_TPIU_SPPR_TXMODE_S                    0
+#define AM_REG_TPIU_SPPR_TXMODE_M                    0x00000003
+#define AM_REG_TPIU_SPPR_TXMODE(n)                   (((uint32_t)(n) << 0) & 0x00000003)
+#define AM_REG_TPIU_SPPR_TXMODE_PARALLEL             0x00000000
+#define AM_REG_TPIU_SPPR_TXMODE_MANCHESTER           0x00000001
+#define AM_REG_TPIU_SPPR_TXMODE_NRZ                  0x00000002
+#define AM_REG_TPIU_SPPR_TXMODE_UART                 0x00000002
+
+//*****************************************************************************
+//
+// TPIU_FFCR - Formatter and Flush Control Register.
+//
+//*****************************************************************************
+// Enable continuous formatting.
+#define AM_REG_TPIU_FFCR_ENFCONT_S                   1
+#define AM_REG_TPIU_FFCR_ENFCONT_M                   0x00000002
+#define AM_REG_TPIU_FFCR_ENFCONT(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+
+//*****************************************************************************
+//
+// TPIU_ITCTRL - Specifies normal or integration mode for the TPIU.
+//
+//*****************************************************************************
+// Specifies the current mode for the TPIU.
+#define AM_REG_TPIU_ITCTRL_MODE_S                    0
+#define AM_REG_TPIU_ITCTRL_MODE_M                    0x00000003
+#define AM_REG_TPIU_ITCTRL_MODE(n)                   (((uint32_t)(n) << 0) & 0x00000003)
+#define AM_REG_TPIU_ITCTRL_MODE_NORMAL               0x00000000
+#define AM_REG_TPIU_ITCTRL_MODE_TEST                 0x00000001
+#define AM_REG_TPIU_ITCTRL_MODE_DATA_TEST            0x00000002
+
+//*****************************************************************************
+//
+// TPIU_TYPE - TPIU Type.
+//
+//*****************************************************************************
+// 1 Indicates UART/NRZ support.
+#define AM_REG_TPIU_TYPE_NRZVALID_S                  11
+#define AM_REG_TPIU_TYPE_NRZVALID_M                  0x00000800
+#define AM_REG_TPIU_TYPE_NRZVALID(n)                 (((uint32_t)(n) << 11) & 0x00000800)
+
+// 1 Indicates Manchester support.
+#define AM_REG_TPIU_TYPE_MANCVALID_S                 10
+#define AM_REG_TPIU_TYPE_MANCVALID_M                 0x00000400
+#define AM_REG_TPIU_TYPE_MANCVALID(n)                (((uint32_t)(n) << 10) & 0x00000400)
+
+// 0 Indicates Parallel Trace support.
+#define AM_REG_TPIU_TYPE_PTINVALID_S                 9
+#define AM_REG_TPIU_TYPE_PTINVALID_M                 0x00000200
+#define AM_REG_TPIU_TYPE_PTINVALID(n)                (((uint32_t)(n) << 9) & 0x00000200)
+
+// FIFO Size reported as a power of two. For instance, 0x3 indicates a FIFO size
+// of 8 bytes.
+#define AM_REG_TPIU_TYPE_FIFOSZ_S                    6
+#define AM_REG_TPIU_TYPE_FIFOSZ_M                    0x000001C0
+#define AM_REG_TPIU_TYPE_FIFOSZ(n)                   (((uint32_t)(n) << 6) & 0x000001C0)
+
+#endif // AM_REG_TPIU_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h b/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h
new file mode 100644
index 0000000000..493a947630
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h
@@ -0,0 +1,612 @@
+//*****************************************************************************
+//
+//  am_reg_uart.h
+//! @file
+//!
+//! @brief Register macros for the UART module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_UART_H
+#define AM_REG_UART_H
+
+//*****************************************************************************
+//
+// Instance finder. (2 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_UART_NUM_MODULES                      2
+#define AM_REG_UARTn(n) \
+    (REG_UART_BASEADDR + 0x00001000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_UART_DR_O                             0x00000000
+#define AM_REG_UART_RSR_O                            0x00000004
+#define AM_REG_UART_FR_O                             0x00000018
+#define AM_REG_UART_ILPR_O                           0x00000020
+#define AM_REG_UART_IBRD_O                           0x00000024
+#define AM_REG_UART_FBRD_O                           0x00000028
+#define AM_REG_UART_LCRH_O                           0x0000002C
+#define AM_REG_UART_CR_O                             0x00000030
+#define AM_REG_UART_IFLS_O                           0x00000034
+#define AM_REG_UART_IER_O                            0x00000038
+#define AM_REG_UART_IES_O                            0x0000003C
+#define AM_REG_UART_MIS_O                            0x00000040
+#define AM_REG_UART_IEC_O                            0x00000044
+
+//*****************************************************************************
+//
+// UART_DR - UART Data Register
+//
+//*****************************************************************************
+// This is the overrun error indicator.
+#define AM_REG_UART_DR_OEDATA_S                      11
+#define AM_REG_UART_DR_OEDATA_M                      0x00000800
+#define AM_REG_UART_DR_OEDATA(n)                     (((uint32_t)(n) << 11) & 0x00000800)
+#define AM_REG_UART_DR_OEDATA_NOERR                  0x00000000
+#define AM_REG_UART_DR_OEDATA_ERR                    0x00000800
+
+// This is the break error indicator.
+#define AM_REG_UART_DR_BEDATA_S                      10
+#define AM_REG_UART_DR_BEDATA_M                      0x00000400
+#define AM_REG_UART_DR_BEDATA(n)                     (((uint32_t)(n) << 10) & 0x00000400)
+#define AM_REG_UART_DR_BEDATA_NOERR                  0x00000000
+#define AM_REG_UART_DR_BEDATA_ERR                    0x00000400
+
+// This is the parity error indicator.
+#define AM_REG_UART_DR_PEDATA_S                      9
+#define AM_REG_UART_DR_PEDATA_M                      0x00000200
+#define AM_REG_UART_DR_PEDATA(n)                     (((uint32_t)(n) << 9) & 0x00000200)
+#define AM_REG_UART_DR_PEDATA_NOERR                  0x00000000
+#define AM_REG_UART_DR_PEDATA_ERR                    0x00000200
+
+// This is the framing error indicator.
+#define AM_REG_UART_DR_FEDATA_S                      8
+#define AM_REG_UART_DR_FEDATA_M                      0x00000100
+#define AM_REG_UART_DR_FEDATA(n)                     (((uint32_t)(n) << 8) & 0x00000100)
+#define AM_REG_UART_DR_FEDATA_NOERR                  0x00000000
+#define AM_REG_UART_DR_FEDATA_ERR                    0x00000100
+
+// This is the UART data port.
+#define AM_REG_UART_DR_DATA_S                        0
+#define AM_REG_UART_DR_DATA_M                        0x000000FF
+#define AM_REG_UART_DR_DATA(n)                       (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// UART_RSR - UART Status Register
+//
+//*****************************************************************************
+// This is the overrun error indicator.
+#define AM_REG_UART_RSR_OESTAT_S                     3
+#define AM_REG_UART_RSR_OESTAT_M                     0x00000008
+#define AM_REG_UART_RSR_OESTAT(n)                    (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_UART_RSR_OESTAT_NOERR                 0x00000000
+#define AM_REG_UART_RSR_OESTAT_ERR                   0x00000008
+
+// This is the break error indicator.
+#define AM_REG_UART_RSR_BESTAT_S                     2
+#define AM_REG_UART_RSR_BESTAT_M                     0x00000004
+#define AM_REG_UART_RSR_BESTAT(n)                    (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_UART_RSR_BESTAT_NOERR                 0x00000000
+#define AM_REG_UART_RSR_BESTAT_ERR                   0x00000004
+
+// This is the parity error indicator.
+#define AM_REG_UART_RSR_PESTAT_S                     1
+#define AM_REG_UART_RSR_PESTAT_M                     0x00000002
+#define AM_REG_UART_RSR_PESTAT(n)                    (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_UART_RSR_PESTAT_NOERR                 0x00000000
+#define AM_REG_UART_RSR_PESTAT_ERR                   0x00000002
+
+// This is the framing error indicator.
+#define AM_REG_UART_RSR_FESTAT_S                     0
+#define AM_REG_UART_RSR_FESTAT_M                     0x00000001
+#define AM_REG_UART_RSR_FESTAT(n)                    (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_UART_RSR_FESTAT_NOERR                 0x00000000
+#define AM_REG_UART_RSR_FESTAT_ERR                   0x00000001
+
+//*****************************************************************************
+//
+// UART_FR - Flag Register
+//
+//*****************************************************************************
+// This bit holds the transmit BUSY indicator.
+#define AM_REG_UART_FR_TXBUSY_S                      8
+#define AM_REG_UART_FR_TXBUSY_M                      0x00000100
+#define AM_REG_UART_FR_TXBUSY(n)                     (((uint32_t)(n) << 8) & 0x00000100)
+
+// This bit holds the transmit FIFO empty indicator.
+#define AM_REG_UART_FR_TXFE_S                        7
+#define AM_REG_UART_FR_TXFE_M                        0x00000080
+#define AM_REG_UART_FR_TXFE(n)                       (((uint32_t)(n) << 7) & 0x00000080)
+#define AM_REG_UART_FR_TXFE_XMTFIFO_EMPTY            0x00000080
+
+// This bit holds the receive FIFO full indicator.
+#define AM_REG_UART_FR_RXFF_S                        6
+#define AM_REG_UART_FR_RXFF_M                        0x00000040
+#define AM_REG_UART_FR_RXFF(n)                       (((uint32_t)(n) << 6) & 0x00000040)
+#define AM_REG_UART_FR_RXFF_RCVFIFO_FULL             0x00000040
+
+// This bit holds the transmit FIFO full indicator.
+#define AM_REG_UART_FR_TXFF_S                        5
+#define AM_REG_UART_FR_TXFF_M                        0x00000020
+#define AM_REG_UART_FR_TXFF(n)                       (((uint32_t)(n) << 5) & 0x00000020)
+#define AM_REG_UART_FR_TXFF_XMTFIFO_FULL             0x00000020
+
+// This bit holds the receive FIFO empty indicator.
+#define AM_REG_UART_FR_RXFE_S                        4
+#define AM_REG_UART_FR_RXFE_M                        0x00000010
+#define AM_REG_UART_FR_RXFE(n)                       (((uint32_t)(n) << 4) & 0x00000010)
+#define AM_REG_UART_FR_RXFE_RCVFIFO_EMPTY            0x00000010
+
+// This bit holds the busy indicator.
+#define AM_REG_UART_FR_BUSY_S                        3
+#define AM_REG_UART_FR_BUSY_M                        0x00000008
+#define AM_REG_UART_FR_BUSY(n)                       (((uint32_t)(n) << 3) & 0x00000008)
+#define AM_REG_UART_FR_BUSY_BUSY                     0x00000008
+
+// This bit holds the data carrier detect indicator.
+#define AM_REG_UART_FR_DCD_S                         2
+#define AM_REG_UART_FR_DCD_M                         0x00000004
+#define AM_REG_UART_FR_DCD(n)                        (((uint32_t)(n) << 2) & 0x00000004)
+#define AM_REG_UART_FR_DCD_DETECTED                  0x00000004
+
+// This bit holds the data set ready indicator.
+#define AM_REG_UART_FR_DSR_S                         1
+#define AM_REG_UART_FR_DSR_M                         0x00000002
+#define AM_REG_UART_FR_DSR(n)                        (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_UART_FR_DSR_READY                     0x00000002
+
+// This bit holds the clear to send indicator.
+#define AM_REG_UART_FR_CTS_S                         0
+#define AM_REG_UART_FR_CTS_M                         0x00000001
+#define AM_REG_UART_FR_CTS(n)                        (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_UART_FR_CTS_CLEARTOSEND               0x00000001
+
+//*****************************************************************************
+//
+// UART_ILPR - IrDA Counter
+//
+//*****************************************************************************
+// These bits hold the IrDA counter divisor.
+#define AM_REG_UART_ILPR_ILPDVSR_S                   0
+#define AM_REG_UART_ILPR_ILPDVSR_M                   0x000000FF
+#define AM_REG_UART_ILPR_ILPDVSR(n)                  (((uint32_t)(n) << 0) & 0x000000FF)
+
+//*****************************************************************************
+//
+// UART_IBRD - Integer Baud Rate Divisor
+//
+//*****************************************************************************
+// These bits hold the baud integer divisor.
+#define AM_REG_UART_IBRD_DIVINT_S                    0
+#define AM_REG_UART_IBRD_DIVINT_M                    0x0000FFFF
+#define AM_REG_UART_IBRD_DIVINT(n)                   (((uint32_t)(n) << 0) & 0x0000FFFF)
+
+//*****************************************************************************
+//
+// UART_FBRD - Fractional Baud Rate Divisor
+//
+//*****************************************************************************
+// These bits hold the baud fractional divisor.
+#define AM_REG_UART_FBRD_DIVFRAC_S                   0
+#define AM_REG_UART_FBRD_DIVFRAC_M                   0x0000003F
+#define AM_REG_UART_FBRD_DIVFRAC(n)                  (((uint32_t)(n) << 0) & 0x0000003F)
+
+//*****************************************************************************
+//
+// UART_LCRH - Line Control High
+//
+//*****************************************************************************
+// This bit holds the stick parity select.
+#define AM_REG_UART_LCRH_SPS_S                       7
+#define AM_REG_UART_LCRH_SPS_M                       0x00000080
+#define AM_REG_UART_LCRH_SPS(n)                      (((uint32_t)(n) << 7) & 0x00000080)
+
+// These bits hold the write length.
+#define AM_REG_UART_LCRH_WLEN_S                      5
+#define AM_REG_UART_LCRH_WLEN_M                      0x00000060
+#define AM_REG_UART_LCRH_WLEN(n)                     (((uint32_t)(n) << 5) & 0x00000060)
+
+// This bit holds the FIFO enable.
+#define AM_REG_UART_LCRH_FEN_S                       4
+#define AM_REG_UART_LCRH_FEN_M                       0x00000010
+#define AM_REG_UART_LCRH_FEN(n)                      (((uint32_t)(n) << 4) & 0x00000010)
+
+// This bit holds the two stop bits select.
+#define AM_REG_UART_LCRH_STP2_S                      3
+#define AM_REG_UART_LCRH_STP2_M                      0x00000008
+#define AM_REG_UART_LCRH_STP2(n)                     (((uint32_t)(n) << 3) & 0x00000008)
+
+// This bit holds the even parity select.
+#define AM_REG_UART_LCRH_EPS_S                       2
+#define AM_REG_UART_LCRH_EPS_M                       0x00000004
+#define AM_REG_UART_LCRH_EPS(n)                      (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bit holds the parity enable.
+#define AM_REG_UART_LCRH_PEN_S                       1
+#define AM_REG_UART_LCRH_PEN_M                       0x00000002
+#define AM_REG_UART_LCRH_PEN(n)                      (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit holds the break set.
+#define AM_REG_UART_LCRH_BRK_S                       0
+#define AM_REG_UART_LCRH_BRK_M                       0x00000001
+#define AM_REG_UART_LCRH_BRK(n)                      (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// UART_CR - Control Register
+//
+//*****************************************************************************
+// This bit enables CTS hardware flow control.
+#define AM_REG_UART_CR_CTSEN_S                       15
+#define AM_REG_UART_CR_CTSEN_M                       0x00008000
+#define AM_REG_UART_CR_CTSEN(n)                      (((uint32_t)(n) << 15) & 0x00008000)
+
+// This bit enables RTS hardware flow control.
+#define AM_REG_UART_CR_RTSEN_S                       14
+#define AM_REG_UART_CR_RTSEN_M                       0x00004000
+#define AM_REG_UART_CR_RTSEN(n)                      (((uint32_t)(n) << 14) & 0x00004000)
+
+// This bit holds modem Out2.
+#define AM_REG_UART_CR_OUT2_S                        13
+#define AM_REG_UART_CR_OUT2_M                        0x00002000
+#define AM_REG_UART_CR_OUT2(n)                       (((uint32_t)(n) << 13) & 0x00002000)
+
+// This bit holds modem Out1.
+#define AM_REG_UART_CR_OUT1_S                        12
+#define AM_REG_UART_CR_OUT1_M                        0x00001000
+#define AM_REG_UART_CR_OUT1(n)                       (((uint32_t)(n) << 12) & 0x00001000)
+
+// This bit enables request to send.
+#define AM_REG_UART_CR_RTS_S                         11
+#define AM_REG_UART_CR_RTS_M                         0x00000800
+#define AM_REG_UART_CR_RTS(n)                        (((uint32_t)(n) << 11) & 0x00000800)
+
+// This bit enables data transmit ready.
+#define AM_REG_UART_CR_DTR_S                         10
+#define AM_REG_UART_CR_DTR_M                         0x00000400
+#define AM_REG_UART_CR_DTR(n)                        (((uint32_t)(n) << 10) & 0x00000400)
+
+// This bit is the receive enable.
+#define AM_REG_UART_CR_RXE_S                         9
+#define AM_REG_UART_CR_RXE_M                         0x00000200
+#define AM_REG_UART_CR_RXE(n)                        (((uint32_t)(n) << 9) & 0x00000200)
+
+// This bit is the transmit enable.
+#define AM_REG_UART_CR_TXE_S                         8
+#define AM_REG_UART_CR_TXE_M                         0x00000100
+#define AM_REG_UART_CR_TXE(n)                        (((uint32_t)(n) << 8) & 0x00000100)
+
+// This bit is the loopback enable.
+#define AM_REG_UART_CR_LBE_S                         7
+#define AM_REG_UART_CR_LBE_M                         0x00000080
+#define AM_REG_UART_CR_LBE(n)                        (((uint32_t)(n) << 7) & 0x00000080)
+
+// This bitfield is the UART clock select.
+#define AM_REG_UART_CR_CLKSEL_S                      4
+#define AM_REG_UART_CR_CLKSEL_M                      0x00000070
+#define AM_REG_UART_CR_CLKSEL(n)                     (((uint32_t)(n) << 4) & 0x00000070)
+#define AM_REG_UART_CR_CLKSEL_NOCLK                  0x00000000
+#define AM_REG_UART_CR_CLKSEL_24MHZ                  0x00000010
+#define AM_REG_UART_CR_CLKSEL_12MHZ                  0x00000020
+#define AM_REG_UART_CR_CLKSEL_6MHZ                   0x00000030
+#define AM_REG_UART_CR_CLKSEL_3MHZ                   0x00000040
+#define AM_REG_UART_CR_CLKSEL_RSVD5                  0x00000050
+#define AM_REG_UART_CR_CLKSEL_RSVD6                  0x00000060
+#define AM_REG_UART_CR_CLKSEL_RSVD7                  0x00000070
+
+// This bit is the UART clock enable.
+#define AM_REG_UART_CR_CLKEN_S                       3
+#define AM_REG_UART_CR_CLKEN_M                       0x00000008
+#define AM_REG_UART_CR_CLKEN(n)                      (((uint32_t)(n) << 3) & 0x00000008)
+
+// This bit is the SIR low power select.
+#define AM_REG_UART_CR_SIRLP_S                       2
+#define AM_REG_UART_CR_SIRLP_M                       0x00000004
+#define AM_REG_UART_CR_SIRLP(n)                      (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bit is the SIR ENDEC enable.
+#define AM_REG_UART_CR_SIREN_S                       1
+#define AM_REG_UART_CR_SIREN_M                       0x00000002
+#define AM_REG_UART_CR_SIREN(n)                      (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit is the UART enable.
+#define AM_REG_UART_CR_UARTEN_S                      0
+#define AM_REG_UART_CR_UARTEN_M                      0x00000001
+#define AM_REG_UART_CR_UARTEN(n)                     (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// UART_IFLS - FIFO Interrupt Level Select
+//
+//*****************************************************************************
+// These bits hold the receive FIFO interrupt level.
+#define AM_REG_UART_IFLS_RXIFLSEL_S                  3
+#define AM_REG_UART_IFLS_RXIFLSEL_M                  0x00000038
+#define AM_REG_UART_IFLS_RXIFLSEL(n)                 (((uint32_t)(n) << 3) & 0x00000038)
+
+// These bits hold the transmit FIFO interrupt level.
+#define AM_REG_UART_IFLS_TXIFLSEL_S                  0
+#define AM_REG_UART_IFLS_TXIFLSEL_M                  0x00000007
+#define AM_REG_UART_IFLS_TXIFLSEL(n)                 (((uint32_t)(n) << 0) & 0x00000007)
+
+//*****************************************************************************
+//
+// UART_IER - Interrupt Enable
+//
+//*****************************************************************************
+// This bit holds the overflow interrupt enable.
+#define AM_REG_UART_IER_OEIM_S                       10
+#define AM_REG_UART_IER_OEIM_M                       0x00000400
+#define AM_REG_UART_IER_OEIM(n)                      (((uint32_t)(n) << 10) & 0x00000400)
+
+// This bit holds the break error interrupt enable.
+#define AM_REG_UART_IER_BEIM_S                       9
+#define AM_REG_UART_IER_BEIM_M                       0x00000200
+#define AM_REG_UART_IER_BEIM(n)                      (((uint32_t)(n) << 9) & 0x00000200)
+
+// This bit holds the parity error interrupt enable.
+#define AM_REG_UART_IER_PEIM_S                       8
+#define AM_REG_UART_IER_PEIM_M                       0x00000100
+#define AM_REG_UART_IER_PEIM(n)                      (((uint32_t)(n) << 8) & 0x00000100)
+
+// This bit holds the framing error interrupt enable.
+#define AM_REG_UART_IER_FEIM_S                       7
+#define AM_REG_UART_IER_FEIM_M                       0x00000080
+#define AM_REG_UART_IER_FEIM(n)                      (((uint32_t)(n) << 7) & 0x00000080)
+
+// This bit holds the receive timeout interrupt enable.
+#define AM_REG_UART_IER_RTIM_S                       6
+#define AM_REG_UART_IER_RTIM_M                       0x00000040
+#define AM_REG_UART_IER_RTIM(n)                      (((uint32_t)(n) << 6) & 0x00000040)
+
+// This bit holds the transmit interrupt enable.
+#define AM_REG_UART_IER_TXIM_S                       5
+#define AM_REG_UART_IER_TXIM_M                       0x00000020
+#define AM_REG_UART_IER_TXIM(n)                      (((uint32_t)(n) << 5) & 0x00000020)
+
+// This bit holds the receive interrupt enable.
+#define AM_REG_UART_IER_RXIM_S                       4
+#define AM_REG_UART_IER_RXIM_M                       0x00000010
+#define AM_REG_UART_IER_RXIM(n)                      (((uint32_t)(n) << 4) & 0x00000010)
+
+// This bit holds the modem DSR interrupt enable.
+#define AM_REG_UART_IER_DSRMIM_S                     3
+#define AM_REG_UART_IER_DSRMIM_M                     0x00000008
+#define AM_REG_UART_IER_DSRMIM(n)                    (((uint32_t)(n) << 3) & 0x00000008)
+
+// This bit holds the modem DCD interrupt enable.
+#define AM_REG_UART_IER_DCDMIM_S                     2
+#define AM_REG_UART_IER_DCDMIM_M                     0x00000004
+#define AM_REG_UART_IER_DCDMIM(n)                    (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bit holds the modem CTS interrupt enable.
+#define AM_REG_UART_IER_CTSMIM_S                     1
+#define AM_REG_UART_IER_CTSMIM_M                     0x00000002
+#define AM_REG_UART_IER_CTSMIM(n)                    (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit holds the modem TXCMP interrupt enable.
+#define AM_REG_UART_IER_TXCMPMIM_S                   0
+#define AM_REG_UART_IER_TXCMPMIM_M                   0x00000001
+#define AM_REG_UART_IER_TXCMPMIM(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// UART_IES - Interrupt Status
+//
+//*****************************************************************************
+// This bit holds the overflow interrupt status.
+#define AM_REG_UART_IES_OERIS_S                      10
+#define AM_REG_UART_IES_OERIS_M                      0x00000400
+#define AM_REG_UART_IES_OERIS(n)                     (((uint32_t)(n) << 10) & 0x00000400)
+
+// This bit holds the break error interrupt status.
+#define AM_REG_UART_IES_BERIS_S                      9
+#define AM_REG_UART_IES_BERIS_M                      0x00000200
+#define AM_REG_UART_IES_BERIS(n)                     (((uint32_t)(n) << 9) & 0x00000200)
+
+// This bit holds the parity error interrupt status.
+#define AM_REG_UART_IES_PERIS_S                      8
+#define AM_REG_UART_IES_PERIS_M                      0x00000100
+#define AM_REG_UART_IES_PERIS(n)                     (((uint32_t)(n) << 8) & 0x00000100)
+
+// This bit holds the framing error interrupt status.
+#define AM_REG_UART_IES_FERIS_S                      7
+#define AM_REG_UART_IES_FERIS_M                      0x00000080
+#define AM_REG_UART_IES_FERIS(n)                     (((uint32_t)(n) << 7) & 0x00000080)
+
+// This bit holds the receive timeout interrupt status.
+#define AM_REG_UART_IES_RTRIS_S                      6
+#define AM_REG_UART_IES_RTRIS_M                      0x00000040
+#define AM_REG_UART_IES_RTRIS(n)                     (((uint32_t)(n) << 6) & 0x00000040)
+
+// This bit holds the transmit interrupt status.
+#define AM_REG_UART_IES_TXRIS_S                      5
+#define AM_REG_UART_IES_TXRIS_M                      0x00000020
+#define AM_REG_UART_IES_TXRIS(n)                     (((uint32_t)(n) << 5) & 0x00000020)
+
+// This bit holds the receive interrupt status.
+#define AM_REG_UART_IES_RXRIS_S                      4
+#define AM_REG_UART_IES_RXRIS_M                      0x00000010
+#define AM_REG_UART_IES_RXRIS(n)                     (((uint32_t)(n) << 4) & 0x00000010)
+
+// This bit holds the modem DSR interrupt status.
+#define AM_REG_UART_IES_DSRMRIS_S                    3
+#define AM_REG_UART_IES_DSRMRIS_M                    0x00000008
+#define AM_REG_UART_IES_DSRMRIS(n)                   (((uint32_t)(n) << 3) & 0x00000008)
+
+// This bit holds the modem DCD interrupt status.
+#define AM_REG_UART_IES_DCDMRIS_S                    2
+#define AM_REG_UART_IES_DCDMRIS_M                    0x00000004
+#define AM_REG_UART_IES_DCDMRIS(n)                   (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bit holds the modem CTS interrupt status.
+#define AM_REG_UART_IES_CTSMRIS_S                    1
+#define AM_REG_UART_IES_CTSMRIS_M                    0x00000002
+#define AM_REG_UART_IES_CTSMRIS(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit holds the modem TXCMP interrupt status.
+#define AM_REG_UART_IES_TXCMPMRIS_S                  0
+#define AM_REG_UART_IES_TXCMPMRIS_M                  0x00000001
+#define AM_REG_UART_IES_TXCMPMRIS(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// UART_MIS - Masked Interrupt Status
+//
+//*****************************************************************************
+// This bit holds the overflow interrupt status masked.
+#define AM_REG_UART_MIS_OEMIS_S                      10
+#define AM_REG_UART_MIS_OEMIS_M                      0x00000400
+#define AM_REG_UART_MIS_OEMIS(n)                     (((uint32_t)(n) << 10) & 0x00000400)
+
+// This bit holds the break error interrupt status masked.
+#define AM_REG_UART_MIS_BEMIS_S                      9
+#define AM_REG_UART_MIS_BEMIS_M                      0x00000200
+#define AM_REG_UART_MIS_BEMIS(n)                     (((uint32_t)(n) << 9) & 0x00000200)
+
+// This bit holds the parity error interrupt status masked.
+#define AM_REG_UART_MIS_PEMIS_S                      8
+#define AM_REG_UART_MIS_PEMIS_M                      0x00000100
+#define AM_REG_UART_MIS_PEMIS(n)                     (((uint32_t)(n) << 8) & 0x00000100)
+
+// This bit holds the framing error interrupt status masked.
+#define AM_REG_UART_MIS_FEMIS_S                      7
+#define AM_REG_UART_MIS_FEMIS_M                      0x00000080
+#define AM_REG_UART_MIS_FEMIS(n)                     (((uint32_t)(n) << 7) & 0x00000080)
+
+// This bit holds the receive timeout interrupt status masked.
+#define AM_REG_UART_MIS_RTMIS_S                      6
+#define AM_REG_UART_MIS_RTMIS_M                      0x00000040
+#define AM_REG_UART_MIS_RTMIS(n)                     (((uint32_t)(n) << 6) & 0x00000040)
+
+// This bit holds the transmit interrupt status masked.
+#define AM_REG_UART_MIS_TXMIS_S                      5
+#define AM_REG_UART_MIS_TXMIS_M                      0x00000020
+#define AM_REG_UART_MIS_TXMIS(n)                     (((uint32_t)(n) << 5) & 0x00000020)
+
+// This bit holds the receive interrupt status masked.
+#define AM_REG_UART_MIS_RXMIS_S                      4
+#define AM_REG_UART_MIS_RXMIS_M                      0x00000010
+#define AM_REG_UART_MIS_RXMIS(n)                     (((uint32_t)(n) << 4) & 0x00000010)
+
+// This bit holds the modem DSR interrupt status masked.
+#define AM_REG_UART_MIS_DSRMMIS_S                    3
+#define AM_REG_UART_MIS_DSRMMIS_M                    0x00000008
+#define AM_REG_UART_MIS_DSRMMIS(n)                   (((uint32_t)(n) << 3) & 0x00000008)
+
+// This bit holds the modem DCD interrupt status masked.
+#define AM_REG_UART_MIS_DCDMMIS_S                    2
+#define AM_REG_UART_MIS_DCDMMIS_M                    0x00000004
+#define AM_REG_UART_MIS_DCDMMIS(n)                   (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bit holds the modem CTS interrupt status masked.
+#define AM_REG_UART_MIS_CTSMMIS_S                    1
+#define AM_REG_UART_MIS_CTSMMIS_M                    0x00000002
+#define AM_REG_UART_MIS_CTSMMIS(n)                   (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit holds the modem TXCMP interrupt status masked.
+#define AM_REG_UART_MIS_TXCMPMMIS_S                  0
+#define AM_REG_UART_MIS_TXCMPMMIS_M                  0x00000001
+#define AM_REG_UART_MIS_TXCMPMMIS(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// UART_IEC - Interrupt Clear
+//
+//*****************************************************************************
+// This bit holds the overflow interrupt clear.
+#define AM_REG_UART_IEC_OEIC_S                       10
+#define AM_REG_UART_IEC_OEIC_M                       0x00000400
+#define AM_REG_UART_IEC_OEIC(n)                      (((uint32_t)(n) << 10) & 0x00000400)
+
+// This bit holds the break error interrupt clear.
+#define AM_REG_UART_IEC_BEIC_S                       9
+#define AM_REG_UART_IEC_BEIC_M                       0x00000200
+#define AM_REG_UART_IEC_BEIC(n)                      (((uint32_t)(n) << 9) & 0x00000200)
+
+// This bit holds the parity error interrupt clear.
+#define AM_REG_UART_IEC_PEIC_S                       8
+#define AM_REG_UART_IEC_PEIC_M                       0x00000100
+#define AM_REG_UART_IEC_PEIC(n)                      (((uint32_t)(n) << 8) & 0x00000100)
+
+// This bit holds the framing error interrupt clear.
+#define AM_REG_UART_IEC_FEIC_S                       7
+#define AM_REG_UART_IEC_FEIC_M                       0x00000080
+#define AM_REG_UART_IEC_FEIC(n)                      (((uint32_t)(n) << 7) & 0x00000080)
+
+// This bit holds the receive timeout interrupt clear.
+#define AM_REG_UART_IEC_RTIC_S                       6
+#define AM_REG_UART_IEC_RTIC_M                       0x00000040
+#define AM_REG_UART_IEC_RTIC(n)                      (((uint32_t)(n) << 6) & 0x00000040)
+
+// This bit holds the transmit interrupt clear.
+#define AM_REG_UART_IEC_TXIC_S                       5
+#define AM_REG_UART_IEC_TXIC_M                       0x00000020
+#define AM_REG_UART_IEC_TXIC(n)                      (((uint32_t)(n) << 5) & 0x00000020)
+
+// This bit holds the receive interrupt clear.
+#define AM_REG_UART_IEC_RXIC_S                       4
+#define AM_REG_UART_IEC_RXIC_M                       0x00000010
+#define AM_REG_UART_IEC_RXIC(n)                      (((uint32_t)(n) << 4) & 0x00000010)
+
+// This bit holds the modem DSR interrupt clear.
+#define AM_REG_UART_IEC_DSRMIC_S                     3
+#define AM_REG_UART_IEC_DSRMIC_M                     0x00000008
+#define AM_REG_UART_IEC_DSRMIC(n)                    (((uint32_t)(n) << 3) & 0x00000008)
+
+// This bit holds the modem DCD interrupt clear.
+#define AM_REG_UART_IEC_DCDMIC_S                     2
+#define AM_REG_UART_IEC_DCDMIC_M                     0x00000004
+#define AM_REG_UART_IEC_DCDMIC(n)                    (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bit holds the modem CTS interrupt clear.
+#define AM_REG_UART_IEC_CTSMIC_S                     1
+#define AM_REG_UART_IEC_CTSMIC_M                     0x00000002
+#define AM_REG_UART_IEC_CTSMIC(n)                    (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit holds the modem TXCMP interrupt clear.
+#define AM_REG_UART_IEC_TXCMPMIC_S                   0
+#define AM_REG_UART_IEC_TXCMPMIC_M                   0x00000001
+#define AM_REG_UART_IEC_TXCMPMIC(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+
+#endif // AM_REG_UART_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h b/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h
new file mode 100644
index 0000000000..93c610e123
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h
@@ -0,0 +1,200 @@
+//*****************************************************************************
+//
+//  am_reg_vcomp.h
+//! @file
+//!
+//! @brief Register macros for the VCOMP module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_VCOMP_H
+#define AM_REG_VCOMP_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_VCOMP_NUM_MODULES                     1
+#define AM_REG_VCOMPn(n) \
+    (REG_VCOMP_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_VCOMP_CFG_O                           0x00000000
+#define AM_REG_VCOMP_STAT_O                          0x00000004
+#define AM_REG_VCOMP_PWDKEY_O                        0x00000008
+#define AM_REG_VCOMP_INTEN_O                         0x00000200
+#define AM_REG_VCOMP_INTSTAT_O                       0x00000204
+#define AM_REG_VCOMP_INTCLR_O                        0x00000208
+#define AM_REG_VCOMP_INTSET_O                        0x0000020C
+
+//*****************************************************************************
+//
+// Key values.
+//
+//*****************************************************************************
+#define AM_REG_VCOMP_PWDKEY_KEYVAL                   0x00000037
+
+//*****************************************************************************
+//
+// VCOMP_INTEN - Voltage Comparator Interrupt registers: Enable
+//
+//*****************************************************************************
+// This bit is the vcompout high interrupt.
+#define AM_REG_VCOMP_INTEN_OUTHI_S                   1
+#define AM_REG_VCOMP_INTEN_OUTHI_M                   0x00000002
+#define AM_REG_VCOMP_INTEN_OUTHI(n)                  (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit is the vcompout low interrupt.
+#define AM_REG_VCOMP_INTEN_OUTLOW_S                  0
+#define AM_REG_VCOMP_INTEN_OUTLOW_M                  0x00000001
+#define AM_REG_VCOMP_INTEN_OUTLOW(n)                 (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// VCOMP_INTSTAT - Voltage Comparator Interrupt registers: Status
+//
+//*****************************************************************************
+// This bit is the vcompout high interrupt.
+#define AM_REG_VCOMP_INTSTAT_OUTHI_S                 1
+#define AM_REG_VCOMP_INTSTAT_OUTHI_M                 0x00000002
+#define AM_REG_VCOMP_INTSTAT_OUTHI(n)                (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit is the vcompout low interrupt.
+#define AM_REG_VCOMP_INTSTAT_OUTLOW_S                0
+#define AM_REG_VCOMP_INTSTAT_OUTLOW_M                0x00000001
+#define AM_REG_VCOMP_INTSTAT_OUTLOW(n)               (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// VCOMP_INTCLR - Voltage Comparator Interrupt registers: Clear
+//
+//*****************************************************************************
+// This bit is the vcompout high interrupt.
+#define AM_REG_VCOMP_INTCLR_OUTHI_S                  1
+#define AM_REG_VCOMP_INTCLR_OUTHI_M                  0x00000002
+#define AM_REG_VCOMP_INTCLR_OUTHI(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit is the vcompout low interrupt.
+#define AM_REG_VCOMP_INTCLR_OUTLOW_S                 0
+#define AM_REG_VCOMP_INTCLR_OUTLOW_M                 0x00000001
+#define AM_REG_VCOMP_INTCLR_OUTLOW(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// VCOMP_INTSET - Voltage Comparator Interrupt registers: Set
+//
+//*****************************************************************************
+// This bit is the vcompout high interrupt.
+#define AM_REG_VCOMP_INTSET_OUTHI_S                  1
+#define AM_REG_VCOMP_INTSET_OUTHI_M                  0x00000002
+#define AM_REG_VCOMP_INTSET_OUTHI(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bit is the vcompout low interrupt.
+#define AM_REG_VCOMP_INTSET_OUTLOW_S                 0
+#define AM_REG_VCOMP_INTSET_OUTLOW_M                 0x00000001
+#define AM_REG_VCOMP_INTSET_OUTLOW(n)                (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// VCOMP_CFG - Configuration Register
+//
+//*****************************************************************************
+// When the reference input NSEL is set to NSEL_DAC, this bitfield selects the
+// voltage level for the negative input to the comparator.
+#define AM_REG_VCOMP_CFG_LVLSEL_S                    16
+#define AM_REG_VCOMP_CFG_LVLSEL_M                    0x000F0000
+#define AM_REG_VCOMP_CFG_LVLSEL(n)                   (((uint32_t)(n) << 16) & 0x000F0000)
+#define AM_REG_VCOMP_CFG_LVLSEL_0P58V                0x00000000
+#define AM_REG_VCOMP_CFG_LVLSEL_0P77V                0x00010000
+#define AM_REG_VCOMP_CFG_LVLSEL_0P97V                0x00020000
+#define AM_REG_VCOMP_CFG_LVLSEL_1P16V                0x00030000
+#define AM_REG_VCOMP_CFG_LVLSEL_1P35V                0x00040000
+#define AM_REG_VCOMP_CFG_LVLSEL_1P55V                0x00050000
+#define AM_REG_VCOMP_CFG_LVLSEL_1P74V                0x00060000
+#define AM_REG_VCOMP_CFG_LVLSEL_1P93V                0x00070000
+#define AM_REG_VCOMP_CFG_LVLSEL_2P13V                0x00080000
+#define AM_REG_VCOMP_CFG_LVLSEL_2P32V                0x00090000
+#define AM_REG_VCOMP_CFG_LVLSEL_2P51V                0x000A0000
+#define AM_REG_VCOMP_CFG_LVLSEL_2P71V                0x000B0000
+#define AM_REG_VCOMP_CFG_LVLSEL_2P90V                0x000C0000
+#define AM_REG_VCOMP_CFG_LVLSEL_3P09V                0x000D0000
+#define AM_REG_VCOMP_CFG_LVLSEL_3P29V                0x000E0000
+#define AM_REG_VCOMP_CFG_LVLSEL_3P48V                0x000F0000
+
+// This bitfield selects the negative input to the comparator.
+#define AM_REG_VCOMP_CFG_NSEL_S                      8
+#define AM_REG_VCOMP_CFG_NSEL_M                      0x00000300
+#define AM_REG_VCOMP_CFG_NSEL(n)                     (((uint32_t)(n) << 8) & 0x00000300)
+#define AM_REG_VCOMP_CFG_NSEL_VREFEXT1               0x00000000
+#define AM_REG_VCOMP_CFG_NSEL_VREFEXT2               0x00000100
+#define AM_REG_VCOMP_CFG_NSEL_VREFEXT3               0x00000200
+#define AM_REG_VCOMP_CFG_NSEL_DAC                    0x00000300
+
+// This bitfield selects the positive input to the comparator.
+#define AM_REG_VCOMP_CFG_PSEL_S                      0
+#define AM_REG_VCOMP_CFG_PSEL_M                      0x00000003
+#define AM_REG_VCOMP_CFG_PSEL(n)                     (((uint32_t)(n) << 0) & 0x00000003)
+#define AM_REG_VCOMP_CFG_PSEL_VDDADJ                 0x00000000
+#define AM_REG_VCOMP_CFG_PSEL_VTEMP                  0x00000001
+#define AM_REG_VCOMP_CFG_PSEL_VEXT1                  0x00000002
+#define AM_REG_VCOMP_CFG_PSEL_VEXT2                  0x00000003
+
+//*****************************************************************************
+//
+// VCOMP_STAT - Status Register
+//
+//*****************************************************************************
+// This bit indicates the power down state of the voltage comparator.
+#define AM_REG_VCOMP_STAT_PWDSTAT_S                  1
+#define AM_REG_VCOMP_STAT_PWDSTAT_M                  0x00000002
+#define AM_REG_VCOMP_STAT_PWDSTAT(n)                 (((uint32_t)(n) << 1) & 0x00000002)
+#define AM_REG_VCOMP_STAT_PWDSTAT_POWERED_DOWN       0x00000002
+
+// This bit is 1 if the positive input of the comparator is greater than the
+// negative input.
+#define AM_REG_VCOMP_STAT_CMPOUT_S                   0
+#define AM_REG_VCOMP_STAT_CMPOUT_M                   0x00000001
+#define AM_REG_VCOMP_STAT_CMPOUT(n)                  (((uint32_t)(n) << 0) & 0x00000001)
+#define AM_REG_VCOMP_STAT_CMPOUT_VOUT_LOW            0x00000000
+#define AM_REG_VCOMP_STAT_CMPOUT_VOUT_HIGH           0x00000001
+
+#endif // AM_REG_VCOMP_H
diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h b/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h
new file mode 100644
index 0000000000..f95ddc1e8d
--- /dev/null
+++ b/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h
@@ -0,0 +1,189 @@
+//*****************************************************************************
+//
+//  am_reg_wdt.h
+//! @file
+//!
+//! @brief Register macros for the WDT module
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_REG_WDT_H
+#define AM_REG_WDT_H
+
+//*****************************************************************************
+//
+// Instance finder. (1 instance(s) available)
+//
+//*****************************************************************************
+#define AM_REG_WDT_NUM_MODULES                       1
+#define AM_REG_WDTn(n) \
+    (REG_WDT_BASEADDR + 0x00000000 * n)
+
+//*****************************************************************************
+//
+// Register offsets.
+//
+//*****************************************************************************
+#define AM_REG_WDT_CFG_O                             0x00000000
+#define AM_REG_WDT_RSTRT_O                           0x00000004
+#define AM_REG_WDT_LOCK_O                            0x00000008
+#define AM_REG_WDT_COUNT_O                           0x0000000C
+#define AM_REG_WDT_INTEN_O                           0x00000200
+#define AM_REG_WDT_INTSTAT_O                         0x00000204
+#define AM_REG_WDT_INTCLR_O                          0x00000208
+#define AM_REG_WDT_INTSET_O                          0x0000020C
+
+//*****************************************************************************
+//
+// WDT_INTEN - WDT Interrupt register: Enable
+//
+//*****************************************************************************
+// Watchdog Timer Interrupt.
+#define AM_REG_WDT_INTEN_WDT_S                       0
+#define AM_REG_WDT_INTEN_WDT_M                       0x00000001
+#define AM_REG_WDT_INTEN_WDT(n)                      (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// WDT_INTSTAT - WDT Interrupt register: Status
+//
+//*****************************************************************************
+// Watchdog Timer Interrupt.
+#define AM_REG_WDT_INTSTAT_WDT_S                     0
+#define AM_REG_WDT_INTSTAT_WDT_M                     0x00000001
+#define AM_REG_WDT_INTSTAT_WDT(n)                    (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// WDT_INTCLR - WDT Interrupt register: Clear
+//
+//*****************************************************************************
+// Watchdog Timer Interrupt.
+#define AM_REG_WDT_INTCLR_WDT_S                      0
+#define AM_REG_WDT_INTCLR_WDT_M                      0x00000001
+#define AM_REG_WDT_INTCLR_WDT(n)                     (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// WDT_INTSET - WDT Interrupt register: Set
+//
+//*****************************************************************************
+// Watchdog Timer Interrupt.
+#define AM_REG_WDT_INTSET_WDT_S                      0
+#define AM_REG_WDT_INTSET_WDT_M                      0x00000001
+#define AM_REG_WDT_INTSET_WDT(n)                     (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// WDT_CFG - Configuration Register
+//
+//*****************************************************************************
+// Select the frequency for the WDT.  All values not enumerated below are
+// undefined.
+#define AM_REG_WDT_CFG_CLKSEL_S                      24
+#define AM_REG_WDT_CFG_CLKSEL_M                      0x07000000
+#define AM_REG_WDT_CFG_CLKSEL(n)                     (((uint32_t)(n) << 24) & 0x07000000)
+#define AM_REG_WDT_CFG_CLKSEL_OFF                    0x00000000
+#define AM_REG_WDT_CFG_CLKSEL_128HZ                  0x01000000
+#define AM_REG_WDT_CFG_CLKSEL_16HZ                   0x02000000
+#define AM_REG_WDT_CFG_CLKSEL_1HZ                    0x03000000
+#define AM_REG_WDT_CFG_CLKSEL_1_16HZ                 0x04000000
+
+// This bitfield is the compare value for counter bits 7:0 to generate a
+// watchdog interrupt.
+#define AM_REG_WDT_CFG_INTVAL_S                      16
+#define AM_REG_WDT_CFG_INTVAL_M                      0x00FF0000
+#define AM_REG_WDT_CFG_INTVAL(n)                     (((uint32_t)(n) << 16) & 0x00FF0000)
+
+// This bitfield is the compare value for counter bits 7:0 to generate a
+// watchdog reset.
+#define AM_REG_WDT_CFG_RESVAL_S                      8
+#define AM_REG_WDT_CFG_RESVAL_M                      0x0000FF00
+#define AM_REG_WDT_CFG_RESVAL(n)                     (((uint32_t)(n) << 8) & 0x0000FF00)
+
+// This bitfield enables the WDT reset.
+#define AM_REG_WDT_CFG_RESEN_S                       2
+#define AM_REG_WDT_CFG_RESEN_M                       0x00000004
+#define AM_REG_WDT_CFG_RESEN(n)                      (((uint32_t)(n) << 2) & 0x00000004)
+
+// This bitfield enables the WDT interrupt. Note : This bit must be set before
+// the interrupt status bit will reflect a watchdog timer expiration.  The IER
+// interrupt register must also be enabled for a WDT interrupt to be sent to the
+// NVIC.
+#define AM_REG_WDT_CFG_INTEN_S                       1
+#define AM_REG_WDT_CFG_INTEN_M                       0x00000002
+#define AM_REG_WDT_CFG_INTEN(n)                      (((uint32_t)(n) << 1) & 0x00000002)
+
+// This bitfield enables the WDT.
+#define AM_REG_WDT_CFG_WDTEN_S                       0
+#define AM_REG_WDT_CFG_WDTEN_M                       0x00000001
+#define AM_REG_WDT_CFG_WDTEN(n)                      (((uint32_t)(n) << 0) & 0x00000001)
+
+//*****************************************************************************
+//
+// WDT_RSTRT - Restart the watchdog timer
+//
+//*****************************************************************************
+// Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
+#define AM_REG_WDT_RSTRT_RSTRT_S                     0
+#define AM_REG_WDT_RSTRT_RSTRT_M                     0x000000FF
+#define AM_REG_WDT_RSTRT_RSTRT(n)                    (((uint32_t)(n) << 0) & 0x000000FF)
+#define AM_REG_WDT_RSTRT_RSTRT_KEYVALUE              0x000000B2
+
+//*****************************************************************************
+//
+// WDT_LOCK - Locks the WDT
+//
+//*****************************************************************************
+// Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be
+// written and WDTEN is set.
+#define AM_REG_WDT_LOCK_LOCK_S                       0
+#define AM_REG_WDT_LOCK_LOCK_M                       0x000000FF
+#define AM_REG_WDT_LOCK_LOCK(n)                      (((uint32_t)(n) << 0) & 0x000000FF)
+#define AM_REG_WDT_LOCK_LOCK_KEYVALUE                0x0000003A
+
+//*****************************************************************************
+//
+// WDT_COUNT - Current Counter Value for WDT
+//
+//*****************************************************************************
+// Read-Only current value of the WDT counter
+#define AM_REG_WDT_COUNT_COUNT_S                     0
+#define AM_REG_WDT_COUNT_COUNT_M                     0x000000FF
+#define AM_REG_WDT_COUNT_COUNT(n)                    (((uint32_t)(n) << 0) & 0x000000FF)
+
+#endif // AM_REG_WDT_H
diff --git a/bsp/apollo2/libraries/startup/SConscript b/bsp/apollo2/libraries/startup/SConscript
new file mode 100644
index 0000000000..e4758f1e2e
--- /dev/null
+++ b/bsp/apollo2/libraries/startup/SConscript
@@ -0,0 +1,26 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Split("""
+
+""")
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    src = src + ['gcc_ride7/' + 'startup_gcc.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src = src + ['arm/' + 'startup_keil.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src = src + ['iar/' + 'startup_iar.c']
+
+path = [cwd]
+
+CPPDEFINES = ['AM_PACKAGE_BGA', 'AM_PART_APOLLO2', 'keil']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/apollo2/libraries/startup/arm/startup_keil.s b/bsp/apollo2/libraries/startup/arm/startup_keil.s
new file mode 100644
index 0000000000..9c14224cc6
--- /dev/null
+++ b/bsp/apollo2/libraries/startup/arm/startup_keil.s
@@ -0,0 +1,359 @@
+;******************************************************************************
+;
+;! @file startup_keil.s
+;!
+;! @brief Definitions for Apollo2 interrupt handlers, the vector table, and the stack.
+;
+;******************************************************************************
+
+;******************************************************************************
+;
+; Copyright (c) 2017, Ambiq Micro
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; 
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 
+; 2. Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; 
+; 3. Neither the name of the copyright holder nor the names of its
+; contributors may be used to endorse or promote products derived from this
+; software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;
+; This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+;
+;******************************************************************************
+
+;******************************************************************************
+;
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;************************************************************************
+Stack   EQU     0x00001000
+
+;******************************************************************************
+;
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+;******************************************************************************
+Heap    EQU     0x00000000
+
+;******************************************************************************
+;
+; Allocate space for the stack.
+;
+;******************************************************************************
+        AREA    STACK, NOINIT, READWRITE, ALIGN=3
+StackMem
+        SPACE   Stack
+__initial_sp
+
+;******************************************************************************
+;
+; Allocate space for the heap.
+;
+;******************************************************************************
+        AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+HeapMem
+        SPACE   Heap
+__heap_limit
+
+;******************************************************************************
+;
+; Indicate that the code in this file preserves 8-byte alignment of the stack.
+;
+;******************************************************************************
+        PRESERVE8
+
+;******************************************************************************
+;
+; Place code into the reset code section.
+;
+;******************************************************************************
+        AREA    RESET, CODE, READONLY
+        THUMB
+
+;******************************************************************************
+;
+; The vector table.
+;
+;******************************************************************************
+;
+; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
+; am_usagefault_isr does not work if am_fault_isr is defined externally.
+; Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
+;
+
+        EXPORT  __Vectors
+__Vectors
+        DCD     StackMem + Stack            ; Top of Stack
+        DCD     Reset_Handler               ; Reset Handler
+        DCD     NMI_Handler                 ; NMI Handler
+        DCD     HardFault_Handler           ; Hard Fault Handler
+        DCD     MemoryManagement_Handler    ; The MPU fault handler
+        DCD     BusFault_Handler            ; The bus fault handler
+        DCD     UsageFault_Handler          ; The usage fault handler
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     SVC_Handler               	; SVCall handler
+        DCD     DebugMon_Handler            ; Debug monitor handler
+        DCD     0                           ; Reserved
+        DCD     PendSV_Handler              ; The PendSV handler
+        DCD     SysTick_Handler             ; The SysTick handler
+
+        ; Peripheral Interrupts
+        DCD     am_brownout_isr             ;  0: Reserved
+        DCD     am_watchdog_isr             ;  1: Reserved
+        DCD     am_clkgen_isr               ;  2: CLKGEN
+        DCD     am_vcomp_isr                ;  3: Voltage Comparator
+        DCD     am_ioslave_ios_isr          ;  4: I/O Slave general
+        DCD     am_ioslave_acc_isr          ;  5: I/O Slave access
+        DCD     am_iomaster0_isr            ;  6: I/O Master 0
+        DCD     am_iomaster1_isr            ;  7: I/O Master 1
+        DCD     am_iomaster2_isr            ;  8: I/O Master 2
+        DCD     am_iomaster3_isr            ;  9: I/O Master 3
+        DCD     am_iomaster4_isr            ; 10: I/O Master 4
+        DCD     am_iomaster5_isr            ; 11: I/O Master 5
+        DCD     am_gpio_isr                 ; 12: GPIO
+        DCD     am_ctimer_isr               ; 13: CTIMER
+        DCD     am_uart0_isr                ; 14: UART0
+        DCD     am_uart1_isr                ; 15: UART1
+        DCD     am_adc_isr                  ; 16: ADC
+        DCD     am_pdm_isr                  ; 17: PDM
+        DCD     am_stimer_isr               ; 18: SYSTEM TIMER
+        DCD     am_stimer_cmpr0_isr         ; 19: SYSTEM TIMER COMPARE0
+        DCD     am_stimer_cmpr1_isr         ; 20: SYSTEM TIMER COMPARE1
+        DCD     am_stimer_cmpr2_isr         ; 21: SYSTEM TIMER COMPARE2
+        DCD     am_stimer_cmpr3_isr         ; 22: SYSTEM TIMER COMPARE3
+        DCD     am_stimer_cmpr4_isr         ; 23: SYSTEM TIMER COMPARE4
+        DCD     am_stimer_cmpr5_isr         ; 24: SYSTEM TIMER COMPARE5
+        DCD     am_stimer_cmpr6_isr         ; 25: SYSTEM TIMER COMPARE6
+        DCD     am_stimer_cmpr7_isr         ; 26: SYSTEM TIMER COMPARE7
+        DCD     am_flash_isr                ; 27: FLASH
+        DCD     am_software0_isr            ; 28: SOFTWARE0
+        DCD     am_software1_isr            ; 29: SOFTWARE1
+        DCD     am_software2_isr            ; 30: SOFTWARE2
+        DCD     am_software3_isr            ; 31: SOFTWARE3
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor first starts execution
+; following a reset event.
+;
+;******************************************************************************
+Reset_Handler   PROC
+                EXPORT  Reset_Handler               [WEAK]
+                IMPORT  __main
+
+                ; Enable the FPU.
+                MOVW    R0, #0xED88
+                MOVT    R0, #0xE000
+                LDR     R1, [R0]
+                ORR     R1, #0x00F00000
+                STR     R1, [R0]
+                DSB
+                ISB
+
+                ; Branch to main.
+                LDR     R0, =__main
+                BX      R0
+
+                ENDP
+
+;******************************************************************************
+;
+; Weak Exception Handlers.
+;
+;******************************************************************************
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                  [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler             [WEAK]
+                B       .
+                ENDP
+MemoryManagement_Handler\
+                PROC
+                EXPORT  MemoryManagement_Handler      [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler              [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler            [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+am_default_isr	PROC
+
+                EXPORT  am_brownout_isr             [WEAK]
+                EXPORT  am_watchdog_isr             [WEAK]
+                EXPORT  am_clkgen_isr               [WEAK]
+                EXPORT  am_vcomp_isr                [WEAK]
+                EXPORT  am_ioslave_ios_isr          [WEAK]
+                EXPORT  am_ioslave_acc_isr          [WEAK]
+                EXPORT  am_iomaster0_isr            [WEAK]
+                EXPORT  am_iomaster1_isr            [WEAK]
+                EXPORT  am_iomaster2_isr            [WEAK]
+                EXPORT  am_iomaster3_isr            [WEAK]
+                EXPORT  am_iomaster4_isr            [WEAK]
+                EXPORT  am_iomaster5_isr            [WEAK]
+                EXPORT  am_gpio_isr                 [WEAK]
+                EXPORT  am_ctimer_isr               [WEAK]
+                EXPORT  am_uart0_isr                [WEAK]
+                EXPORT  am_uart1_isr                [WEAK]
+				EXPORT  am_adc_isr                  [WEAK]
+                EXPORT  am_pdm_isr                  [WEAK]
+                EXPORT  am_stimer_isr               [WEAK]
+                EXPORT  am_stimer_cmpr0_isr         [WEAK]
+                EXPORT  am_stimer_cmpr1_isr         [WEAK]
+                EXPORT  am_stimer_cmpr2_isr         [WEAK]
+                EXPORT  am_stimer_cmpr3_isr         [WEAK]
+                EXPORT  am_stimer_cmpr4_isr         [WEAK]
+                EXPORT  am_stimer_cmpr5_isr         [WEAK]
+                EXPORT  am_stimer_cmpr6_isr         [WEAK]
+                EXPORT  am_stimer_cmpr7_isr         [WEAK]
+                EXPORT  am_flash_isr                [WEAK]
+                EXPORT  am_software0_isr            [WEAK]
+                EXPORT  am_software1_isr            [WEAK]
+                EXPORT  am_software2_isr            [WEAK]
+                EXPORT  am_software3_isr            [WEAK]
+
+am_brownout_isr
+am_watchdog_isr
+am_clkgen_isr
+am_vcomp_isr
+am_ioslave_ios_isr
+am_ioslave_acc_isr
+am_iomaster0_isr
+am_iomaster1_isr
+am_iomaster2_isr
+am_iomaster3_isr
+am_iomaster4_isr
+am_iomaster5_isr
+am_gpio_isr
+am_ctimer_isr
+am_uart0_isr
+am_uart1_isr
+am_adc_isr
+am_pdm_isr
+am_stimer_isr
+am_stimer_cmpr0_isr
+am_stimer_cmpr1_isr
+am_stimer_cmpr2_isr
+am_stimer_cmpr3_isr
+am_stimer_cmpr4_isr
+am_stimer_cmpr5_isr
+am_stimer_cmpr6_isr
+am_stimer_cmpr7_isr
+am_flash_isr
+am_software0_isr
+am_software1_isr
+am_software2_isr
+am_software3_isr
+
+                ; all device interrupts go here unless the weak label is over
+                ; ridden in the linker hard spin so the debugger will know it
+                ; was an unhandled interrupt request a come-from-buffer or
+                ; instruction trace hardware would sure be nice if you get here
+                B       .
+
+                ENDP
+
+;******************************************************************************
+;
+; Align the end of the section.
+;
+;******************************************************************************
+                ALIGN
+
+;******************************************************************************
+;
+; Initialization of the heap and stack.
+;
+;******************************************************************************
+                AREA    |.text|, CODE, READONLY
+
+;******************************************************************************
+;
+; User Initial Stack & Heap.
+;
+;******************************************************************************
+    IF :DEF: __MICROLIB
+        EXPORT  __initial_sp
+        EXPORT  __heap_base
+        EXPORT  __heap_limit
+    ELSE
+        IMPORT  __use_two_region_memory
+        EXPORT  __user_initial_stackheap
+__user_initial_stackheap PROC
+        LDR     R0, =HeapMem
+        LDR     R1, =(StackMem + Stack)
+        LDR     R2, =(HeapMem + Heap)
+        LDR     R3, =StackMem
+        BX      LR
+
+        ENDP
+
+    ENDIF
+
+;******************************************************************************
+;
+; Align the end of the section.
+;
+;******************************************************************************
+                ALIGN
+
+;******************************************************************************
+;
+; All Done
+;
+;******************************************************************************
+                END
+
+
diff --git a/bsp/apollo2/libraries/startup/gcc/startup_gcc.c b/bsp/apollo2/libraries/startup/gcc/startup_gcc.c
new file mode 100644
index 0000000000..a67dff41f4
--- /dev/null
+++ b/bsp/apollo2/libraries/startup/gcc/startup_gcc.c
@@ -0,0 +1,316 @@
+//*****************************************************************************
+//
+//! @file startup_gcc.c
+//!
+//! @brief Definitions for interrupt handlers, the vector table, and the stack.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Forward declaration of interrupt handlers.
+//
+//*****************************************************************************
+extern void am_reset_isr(void)        __attribute ((naked));
+extern void am_nmi_isr(void)          __attribute ((weak));
+extern void am_fault_isr(void)        __attribute ((weak));
+extern void am_mpufault_isr(void)     __attribute ((weak, alias ("am_fault_isr")));
+extern void am_busfault_isr(void)     __attribute ((weak, alias ("am_fault_isr")));
+extern void am_usagefault_isr(void)   __attribute ((weak, alias ("am_fault_isr")));
+extern void am_svcall_isr(void)       __attribute ((weak, alias ("am_default_isr")));
+extern void am_debugmon_isr(void)     __attribute ((weak, alias ("am_default_isr")));
+extern void am_pendsv_isr(void)       __attribute ((weak, alias ("am_default_isr")));
+extern void am_systick_isr(void)      __attribute ((weak, alias ("am_default_isr")));
+
+extern void am_brownout_isr(void)     __attribute ((weak, alias ("am_default_isr")));
+extern void am_watchdog_isr(void)     __attribute ((weak, alias ("am_default_isr")));
+extern void am_clkgen_isr(void)       __attribute ((weak, alias ("am_default_isr")));
+extern void am_vcomp_isr(void)        __attribute ((weak, alias ("am_default_isr")));
+extern void am_ioslave_ios_isr(void)  __attribute ((weak, alias ("am_default_isr")));
+extern void am_ioslave_acc_isr(void)  __attribute ((weak, alias ("am_default_isr")));
+extern void am_iomaster0_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_iomaster1_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_iomaster2_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_iomaster3_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_iomaster4_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_iomaster5_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_gpio_isr(void)         __attribute ((weak, alias ("am_default_isr")));
+extern void am_ctimer_isr(void)       __attribute ((weak, alias ("am_default_isr")));
+extern void am_uart_isr(void)         __attribute ((weak, alias ("am_default_isr")));
+extern void am_uart1_isr(void)        __attribute ((weak, alias ("am_default_isr")));
+extern void am_adc_isr(void)          __attribute ((weak, alias ("am_default_isr")));
+extern void am_pdm_isr(void)          __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_isr(void)       __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_cmpr0_isr(void) __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_cmpr1_isr(void) __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_cmpr2_isr(void) __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_cmpr3_isr(void) __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_cmpr4_isr(void) __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_cmpr5_isr(void) __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_cmpr6_isr(void) __attribute ((weak, alias ("am_default_isr")));
+extern void am_stimer_cmpr7_isr(void) __attribute ((weak, alias ("am_default_isr")));
+extern void am_flash_isr(void)        __attribute ((weak, alias ("am_default_isr")));
+extern void am_software0_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_software1_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_software2_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+extern void am_software3_isr(void)    __attribute ((weak, alias ("am_default_isr")));
+
+extern void am_default_isr(void)      __attribute ((weak));
+
+//*****************************************************************************
+//
+// The entry point for the application.
+//
+//*****************************************************************************
+extern int main(void);
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+__attribute__ ((section(".stack")))
+static uint32_t g_pui32Stack[1024];
+
+//*****************************************************************************
+//
+// The vector table.  Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
+// am_usagefault_isr does not work if am_fault_isr is defined externally.
+// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
+//
+//*****************************************************************************
+__attribute__ ((section(".isr_vector")))
+void (* const g_am_pfnVectors[])(void) =
+{
+    (void (*)(void))((uint32_t)g_pui32Stack + sizeof(g_pui32Stack)),
+                                            // The initial stack pointer
+    am_reset_isr,                           // The reset handler
+    am_nmi_isr,                             // The NMI handler
+    am_fault_isr,                           // The hard fault handler
+    am_fault_isr,                           // The MPU fault handler
+    am_fault_isr,                           // The bus fault handler
+    am_fault_isr,                           // The usage fault handler
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    am_svcall_isr,                          // SVCall handle
+    am_debugmon_isr,                        // Debug monitor handler
+    0,                                      // Reserved
+    am_pendsv_isr,                          // The PendSV handler
+    am_systick_isr,                         // The SysTick handler
+
+    //
+    // Peripheral Interrupts
+    //
+    am_brownout_isr,                        //  0: Brownout
+    am_watchdog_isr,                        //  1: Watchdog
+    am_clkgen_isr,                          //  2: CLKGEN
+    am_vcomp_isr,                           //  3: Voltage Comparator
+    am_ioslave_ios_isr,                     //  4: I/O Slave general
+    am_ioslave_acc_isr,                     //  5: I/O Slave access
+    am_iomaster0_isr,                       //  6: I/O Master 0
+    am_iomaster1_isr,                       //  7: I/O Master 1
+    am_iomaster2_isr,                       //  8: I/O Master 2
+    am_iomaster3_isr,                       //  9: I/O Master 3
+    am_iomaster4_isr,                       // 10: I/O Master 4
+    am_iomaster5_isr,                       // 11: I/O Master 5
+    am_gpio_isr,                            // 12: GPIO
+    am_ctimer_isr,                          // 13: CTIMER
+    am_uart_isr,                            // 14: UART
+    am_uart1_isr,                           // 15: UART
+    am_adc_isr,                             // 16: ADC
+    am_pdm_isr,                             // 17: ADC
+    am_stimer_isr,                          // 18: SYSTEM TIMER
+    am_stimer_cmpr0_isr,                    // 19: SYSTEM TIMER COMPARE0
+    am_stimer_cmpr1_isr,                    // 20: SYSTEM TIMER COMPARE1
+    am_stimer_cmpr2_isr,                    // 21: SYSTEM TIMER COMPARE2
+    am_stimer_cmpr3_isr,                    // 22: SYSTEM TIMER COMPARE3
+    am_stimer_cmpr4_isr,                    // 23: SYSTEM TIMER COMPARE4
+    am_stimer_cmpr5_isr,                    // 24: SYSTEM TIMER COMPARE5
+    am_stimer_cmpr6_isr,                    // 25: SYSTEM TIMER COMPARE6
+    am_stimer_cmpr7_isr,                    // 26: SYSTEM TIMER COMPARE7
+    am_flash_isr,                           // 27: FLASH
+    am_software0_isr,                       // 28: SOFTWARE0
+    am_software1_isr,                       // 29: SOFTWARE1
+    am_software2_isr,                       // 30: SOFTWARE2
+    am_software3_isr                        // 31: SOFTWARE3
+};
+
+//*****************************************************************************
+//
+// The following are constructs created by the linker, indicating where the
+// the "data" and "bss" segments reside in memory.  The initializers for the
+// "data" segment resides immediately following the "text" segment.
+//
+//*****************************************************************************
+extern uint32_t _etext;
+extern uint32_t _sdata;
+extern uint32_t _edata;
+extern uint32_t _sbss;
+extern uint32_t _ebss;
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event.  Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+void
+am_reset_isr(void)
+{
+    //
+    // Set the vector table pointer.
+    //
+    __asm("    ldr    r0, =0xE000ED08\n"
+          "    ldr    r1, =g_am_pfnVectors\n"
+          "    str    r1, [r0]");
+
+    //
+    // Set the stack pointer.
+    //
+    __asm("    ldr    sp, [r1]");
+#ifndef NOFPU
+    //
+    // Enable the FPU.
+    //
+    __asm("ldr  r0, =0xE000ED88\n"
+          "ldr  r1,[r0]\n"
+          "orr  r1,#(0xF << 20)\n"
+          "str  r1,[r0]\n"
+          "dsb\n"
+          "isb\n");
+#endif
+    //
+    // Copy the data segment initializers from flash to SRAM.
+    //
+    __asm("    ldr     r0, =_init_data\n"
+          "    ldr     r1, =_sdata\n"
+          "    ldr     r2, =_edata\n"
+          "copy_loop:\n"
+          "        ldr   r3, [r0], #4\n"
+          "        str   r3, [r1], #4\n"
+          "        cmp     r1, r2\n"
+          "        blt     copy_loop\n");
+    //
+    // Zero fill the bss segment.
+    //
+    __asm("    ldr     r0, =_sbss\n"
+          "    ldr     r1, =_ebss\n"
+          "    mov     r2, #0\n"
+          "zero_loop:\n"
+          "        cmp     r0, r1\n"
+          "        it      lt\n"
+          "        strlt   r2, [r0], #4\n"
+          "        blt     zero_loop");
+
+    //
+    // Call the application's entry point.
+    //
+    main();
+
+    //
+    // If main returns then execute a break point instruction
+    //
+    __asm("    bkpt     ");
+}
+#else
+#error GNU STDC inline not supported.
+#endif
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI.  This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+void
+am_nmi_isr(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a fault
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+void
+am_fault_isr(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+void
+am_default_isr(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
diff --git a/bsp/apollo2/libraries/startup/iar/startup_iar.c b/bsp/apollo2/libraries/startup/iar/startup_iar.c
new file mode 100644
index 0000000000..3264300cb4
--- /dev/null
+++ b/bsp/apollo2/libraries/startup/iar/startup_iar.c
@@ -0,0 +1,312 @@
+//*****************************************************************************
+//
+//! @file startup_iar.c
+//!
+//! @brief Definitions for interrupt handlers, the vector table, and the stack.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Enable the IAR extensions for this source file.
+//
+//*****************************************************************************
+#pragma language = extended
+
+//*****************************************************************************
+//
+// Weak function links.
+//
+//*****************************************************************************
+#pragma weak am_mpufault_isr        = am_fault_isr
+#pragma weak am_busfault_isr        = am_fault_isr
+#pragma weak am_usagefault_isr      = am_fault_isr
+#pragma weak am_svcall_isr          = am_default_isr
+#pragma weak am_debugmon_isr        = am_default_isr
+#pragma weak am_pendsv_isr          = am_default_isr
+#pragma weak am_systick_isr         = am_default_isr
+#pragma weak am_brownout_isr        = am_default_isr
+#pragma weak am_watchdog_isr        = am_default_isr
+#pragma weak am_clkgen_isr          = am_default_isr
+#pragma weak am_vcomp_isr           = am_default_isr
+#pragma weak am_ioslave_ios_isr     = am_default_isr
+#pragma weak am_ioslave_acc_isr     = am_default_isr
+#pragma weak am_iomaster0_isr       = am_default_isr
+#pragma weak am_iomaster1_isr       = am_default_isr
+#pragma weak am_iomaster2_isr       = am_default_isr
+#pragma weak am_iomaster3_isr       = am_default_isr
+#pragma weak am_iomaster4_isr       = am_default_isr
+#pragma weak am_iomaster5_isr       = am_default_isr
+#pragma weak am_gpio_isr            = am_default_isr
+#pragma weak am_ctimer_isr          = am_default_isr
+#pragma weak am_uart_isr            = am_default_isr
+#pragma weak am_uart1_isr           = am_default_isr
+#pragma weak am_adc_isr             = am_default_isr
+#pragma weak am_pdm_isr             = am_default_isr
+#pragma weak am_stimer_isr          = am_default_isr
+#pragma weak am_stimer_cmpr0_isr    = am_default_isr
+#pragma weak am_stimer_cmpr1_isr    = am_default_isr
+#pragma weak am_stimer_cmpr2_isr    = am_default_isr
+#pragma weak am_stimer_cmpr3_isr    = am_default_isr
+#pragma weak am_stimer_cmpr4_isr    = am_default_isr
+#pragma weak am_stimer_cmpr5_isr    = am_default_isr
+#pragma weak am_stimer_cmpr6_isr    = am_default_isr
+#pragma weak am_stimer_cmpr7_isr    = am_default_isr
+#pragma weak am_flash_isr           = am_default_isr
+#pragma weak am_software0_isr       = am_default_isr
+#pragma weak am_software1_isr       = am_default_isr
+#pragma weak am_software2_isr       = am_default_isr
+#pragma weak am_software3_isr       = am_default_isr
+
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+extern __stackless void am_reset_isr(void);
+extern __weak void am_nmi_isr(void);
+extern __weak void am_fault_isr(void);
+extern void am_mpufault_isr(void);
+extern void am_busfault_isr(void);
+extern void am_usagefault_isr(void);
+extern void am_svcall_isr(void);
+extern void am_debugmon_isr(void);
+extern void am_pendsv_isr(void);
+extern void am_systick_isr(void);
+extern void am_brownout_isr(void);
+extern void am_watchdog_isr(void);
+extern void am_clkgen_isr(void);
+extern void am_vcomp_isr(void);
+extern void am_ioslave_ios_isr(void);
+extern void am_ioslave_acc_isr(void);
+extern void am_iomaster0_isr(void);
+extern void am_iomaster1_isr(void);
+extern void am_iomaster2_isr(void);
+extern void am_iomaster3_isr(void);
+extern void am_iomaster4_isr(void);
+extern void am_iomaster5_isr(void);
+extern void am_gpio_isr(void);
+extern void am_ctimer_isr(void);
+extern void am_uart_isr(void);
+extern void am_uart1_isr(void);
+extern void am_adc_isr(void);
+extern void am_pdm_isr(void);
+extern void am_stimer_isr(void);
+extern void am_stimer_cmpr0_isr(void);
+extern void am_stimer_cmpr1_isr(void);
+extern void am_stimer_cmpr2_isr(void);
+extern void am_stimer_cmpr3_isr(void);
+extern void am_stimer_cmpr4_isr(void);
+extern void am_stimer_cmpr5_isr(void);
+extern void am_stimer_cmpr6_isr(void);
+extern void am_stimer_cmpr7_isr(void);
+extern void am_flash_isr(void);
+extern void am_software0_isr(void);
+extern void am_software1_isr(void);
+extern void am_software2_isr(void);
+extern void am_software3_isr(void);
+
+extern void am_default_isr(void);
+
+//*****************************************************************************
+//
+// The entry point for the application startup code.
+//
+//*****************************************************************************
+extern void __iar_program_start(void);
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+static uint32_t pui32Stack[1024] @ ".noinit";
+
+//*****************************************************************************
+//
+// A union that describes the entries of the vector table.  The union is needed
+// since the first entry is the stack pointer and the remainder are function
+// pointers.
+//
+//*****************************************************************************
+typedef union
+{
+    void (*pfnHandler)(void);
+    uint32_t ui32Ptr;
+}
+uVectorEntry;
+
+//*****************************************************************************
+//
+// The vector table.  Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
+// am_usagefault_isr does not work if am_fault_isr is defined externally.
+// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
+//
+//*****************************************************************************
+__root const uVectorEntry __vector_table[] @ ".intvec" =
+{
+    { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) },
+                                                // The initial stack pointer
+    am_reset_isr,                               // The reset handler
+    am_nmi_isr,                                 // The NMI handler
+    am_fault_isr,                               // The hard fault handler
+    am_fault_isr,                               // The MPU fault handler
+    am_fault_isr,                               // The bus fault handler
+    am_fault_isr,                               // The usage fault handler
+    0,                                          // Reserved
+    0,                                          // Reserved
+    0,                                          // Reserved
+    0,                                          // Reserved
+    am_svcall_isr,                              // SVCall handle
+    am_debugmon_isr,                            // Debug monitor handler
+    0,                                          // Reserved
+    am_pendsv_isr,                              // The PendSV handler
+    am_systick_isr,                             // The SysTick handler
+
+    //
+    // Peripheral Interrupts
+    //
+    am_brownout_isr,                            //  0: Brownout
+    am_watchdog_isr,                            //  1: Watchdog
+    am_clkgen_isr,                              //  2: CLKGEN
+    am_vcomp_isr,                               //  3: Voltage Comparator
+    am_ioslave_ios_isr,                         //  4: I/O Slave general
+    am_ioslave_acc_isr,                         //  5: I/O Slave access
+    am_iomaster0_isr,                           //  6: I/O Master 0
+    am_iomaster1_isr,                           //  7: I/O Master 1
+    am_iomaster2_isr,                           //  8: I/O Master 2
+    am_iomaster3_isr,                           //  9: I/O Master 3
+    am_iomaster4_isr,                           // 10: I/O Master 4
+    am_iomaster5_isr,                           // 11: I/O Master 5
+    am_gpio_isr,                                // 12: GPIO
+    am_ctimer_isr,                              // 13: CTIMER
+    am_uart_isr,                                // 14: UART0
+    am_uart1_isr,                               // 15: UART1
+    am_adc_isr,                                 // 16: ADC
+    am_pdm_isr,                                 // 17: PDM
+    am_stimer_isr,                              // 18: STIMER
+    am_stimer_cmpr0_isr,                        // 19: STIMER COMPARE0
+    am_stimer_cmpr1_isr,                        // 20: STIMER COMPARE1
+    am_stimer_cmpr2_isr,                        // 21: STIMER COMPARE2
+    am_stimer_cmpr3_isr,                        // 22: STIMER COMPARE3
+    am_stimer_cmpr4_isr,                        // 23: STIMER COMPARE4
+    am_stimer_cmpr5_isr,                        // 24: STIMER COMPARE5
+    am_stimer_cmpr6_isr,                        // 25: STIMER COMPARE6
+    am_stimer_cmpr7_isr,                        // 26: STIMER COMPARE7
+    am_flash_isr,                               // 27: FLASH
+    am_software0_isr,                           // 28: SOFTWARE0
+    am_software1_isr,                           // 29: SOFTWARE1
+    am_software2_isr,                           // 30: SOFTWARE2
+    am_software3_isr                            // 31: SOFTWARE3
+};
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event.  Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called.
+//
+//*****************************************************************************
+void
+am_reset_isr(void)
+{
+    //
+    // Call the application's entry point.
+    //
+    __iar_program_start();
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI.  This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+__weak void
+am_nmi_isr(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a fault
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+__weak void
+am_fault_isr(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+am_default_isr(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
diff --git a/bsp/apollo2/project.uvprojx b/bsp/apollo2/project.uvprojx
new file mode 100644
index 0000000000..a528b27b90
--- /dev/null
+++ b/bsp/apollo2/project.uvprojx
@@ -0,0 +1,750 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread-apollo2</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060061::V5.06 update 1 (build 61)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>AMAPH1KK-KBR</Device>
+          <Vendor>Ambiq Micro</Vendor>
+          <PackID>AmbiqMicro.Apollo_DFP.1.0.0</PackID>
+          <PackURL>http://s3.asia.ambiqmicro.com/pack/</PackURL>
+          <Cpu>IROM(0x00000000,0x100000) IRAM(0x10000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC4000 -FN1 -FF0Apollo2 -FS00 -FL010000 -FP0($$Device:AMAPH1KK-KBR$Flash\Apollo2.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:AMAPH1KK-KBR$Device\Include\apollo2.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:AMAPH1KK-KBR$SVD\apollo2.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>6</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>Segger\JL2CM3.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x40000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>AM_PART_APOLLO2, AM_PACKAGE_BGA, keil</Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;.;board;libraries\drivers;libraries\startup;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\build\rtthread.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc> --keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab) </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Board</GroupName>
+          <Files>
+            <File>
+              <FileName>adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>led.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\led.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Libraries</GroupName>
+          <Files>
+            <File>
+              <FileName>am_hal_clkgen.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_clkgen.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_debug.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_debug.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_cachectrl.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_cachectrl.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_pwrctrl.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_pwrctrl.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_sysctrl.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_sysctrl.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_stimer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_stimer.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_ctimer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_ctimer.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_interrupt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_interrupt.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_vcomp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_vcomp.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>am_hal_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\drivers\hal\am_hal_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_keil.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>libraries\startup\arm\startup_keil.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORTEX-M4</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>portal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\portal.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\symbol.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_token.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/apollo2/rtconfig.h b/bsp/apollo2/rtconfig.h
new file mode 100644
index 0000000000..6126e294fa
--- /dev/null
+++ b/bsp/apollo2/rtconfig.h
@@ -0,0 +1,99 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	   6
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	8
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	200
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+//#define RT_DEBUG
+//#define RT_DEBUG_INIT 1
+//#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+//#define RT_USING_HOOK
+
+#define RT_USING_IDLE_HOOK
+
+#define IDLE_THREAD_STACK_SIZE	384
+
+/* Using Software Timer */
+//#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO		1
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	200
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+/* #define RT_USING_MAILBOX */
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+/* #define RT_USING_MEMPOOL */
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+#define RT_USING_TINY_SIZE
+
+/* Using USER MAIN */
+#define RT_USING_USER_MAIN
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
+#define RT_USING_SERIAL
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	    "uart0"
+
+/* Using GPIO pin framework */
+#define RT_USING_PIN
+
+// #define RT_USING_SPI
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+/* configure finsh parameters */
+#define FINSH_THREAD_PRIORITY 6
+#define FINSH_THREAD_STACK_SIZE	1024
+#define FINSH_HISTORY_LINES	1
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+#endif
diff --git a/bsp/apollo2/rtconfig.py b/bsp/apollo2/rtconfig.py
new file mode 100644
index 0000000000..5e40e7201e
--- /dev/null
+++ b/bsp/apollo2/rtconfig.py
@@ -0,0 +1,84 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'D:/SourceryGCC/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-nrf52832.map,-cref,-u,Reset_Handler -T nrf52_xxaa.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-nrf52832.map --scatter rtthread-nrf52832.sct'
+
+    CFLAGS += ' --c99'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
diff --git a/bsp/apollo2/template.uvoptx b/bsp/apollo2/template.uvoptx
new file mode 100644
index 0000000000..e6bfeb7bb2
--- /dev/null
+++ b/bsp/apollo2/template.uvoptx
@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread-apollo2</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>48000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>6</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U4294967295 -O78 -S0 -ZTIFSpeedSel20000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD10000000 -FC4000 -FN1 -FF0Apollo2.FLM -FS00 -FL010000 -FP0($$Device:AMAPH1KK-KBR$Flash\Apollo2.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC4000 -FN1 -FF0Apollo2 -FS00 -FL010000 -FP0($$Device:AMAPH1KK-KBR$Flash\Apollo2.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
diff --git a/bsp/apollo2/template.uvprojx b/bsp/apollo2/template.uvprojx
new file mode 100644
index 0000000000..29ce82bf53
--- /dev/null
+++ b/bsp/apollo2/template.uvprojx
@@ -0,0 +1,418 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread-apollo2</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060061::V5.06 update 1 (build 61)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>AMAPH1KK-KBR</Device>
+          <Vendor>Ambiq Micro</Vendor>
+          <PackID>AmbiqMicro.Apollo_DFP.1.0.0</PackID>
+          <PackURL>http://s3.asia.ambiqmicro.com/pack/</PackURL>
+          <Cpu>IROM(0x00000000,0x100000) IRAM(0x10000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC4000 -FN1 -FF0Apollo2 -FS00 -FL010000 -FP0($$Device:AMAPH1KK-KBR$Flash\Apollo2.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:AMAPH1KK-KBR$Device\Include\apollo2.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:AMAPH1KK-KBR$SVD\apollo2.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>6</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>Segger\JL2CM3.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x40000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>AM_PACKAGE_BGA,AM_PART_APOLLO2,keil,USE_APDPERIPH_DRIVER</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\build\rtthread.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/frdm-k64f/rtconfig.py b/bsp/frdm-k64f/rtconfig.py
index a40c66dcf2..baaf4905fa 100644
--- a/bsp/frdm-k64f/rtconfig.py
+++ b/bsp/frdm-k64f/rtconfig.py
@@ -74,7 +74,7 @@ elif PLATFORM == 'armcc':
     EXEC_PATH += '/arm/bin40/'
 
     if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
+        CFLAGS += ' --c99 -g -O0'
         AFLAGS += ' -g'
     else:
         CFLAGS += ' -O2'
diff --git a/bsp/ls1cdev/applications/startup.c b/bsp/ls1cdev/applications/startup.c
index ed2854e97e..cb1025dec6 100644
--- a/bsp/ls1cdev/applications/startup.c
+++ b/bsp/ls1cdev/applications/startup.c
@@ -51,9 +51,9 @@ void rtthread_startup(void)
     rt_hw_interrupt_init();
 
     /* copy vector */
-    rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
-    rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
-    rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
+    rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x80);
+    rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x80);
+    rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x80);
 
     invalidate_writeback_dcache_all();
     invalidate_icache_all();
diff --git a/bsp/ls1cdev/drivers/board.c b/bsp/ls1cdev/drivers/board.c
index 29d7fa7142..cb5fbdae09 100644
--- a/bsp/ls1cdev/drivers/board.c
+++ b/bsp/ls1cdev/drivers/board.c
@@ -94,8 +94,10 @@ void rt_hw_board_init(void)
 	/* init operating system timer */
 	rt_hw_timer_init();
 
+#ifdef RT_USING_FPU
     /* init hardware fpu */
     rt_hw_fpu_init();
+#endif
 
 	rt_kprintf("current sr: 0x%08x\n", read_c0_status());
 }
diff --git a/bsp/ls1cdev/libraries/ls1c_gpio.c b/bsp/ls1cdev/libraries/ls1c_gpio.c
index d0f0633b4e..ee073b7c4b 100644
--- a/bsp/ls1cdev/libraries/ls1c_gpio.c
+++ b/bsp/ls1cdev/libraries/ls1c_gpio.c
@@ -211,8 +211,8 @@ unsigned int gpio_get(unsigned int gpio)
  */
 void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type)
 {
-    volatile unsigned int *int_pol;     // 中断极性选择寄存器
-    volatile unsigned int *int_edge;    // 中断边沿选择寄存器
+    volatile unsigned int *int_pol = NULL;     // 中断极性选择寄存器
+    volatile unsigned int *int_edge = NULL;    // 中断边沿选择寄存器
     unsigned int port = GPIO_GET_PORT(gpio);
     unsigned int pin  = GPIO_GET_PIN(gpio);
 
@@ -257,6 +257,9 @@ void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type)
             *int_pol    &= ~(1 << pin);
             *int_edge   &= ~(1 << pin);
             break;
+
+        default:
+            break;
     }
 
     return ;
diff --git a/bsp/ls1cdev/libraries/ls1c_i2c.c b/bsp/ls1cdev/libraries/ls1c_i2c.c
new file mode 100644
index 0000000000..6a1622471c
--- /dev/null
+++ b/bsp/ls1cdev/libraries/ls1c_i2c.c
@@ -0,0 +1,373 @@
+/*
+ * File      : ls1c_i2c.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ */
+
+// 封装硬件i2c接口
+
+
+#include "ls1c_public.h"
+#include "ls1c_regs.h"
+#include "ls1c_clock.h"
+#include "ls1c_i2c.h"
+#include "ls1c_delay.h"
+
+
+
+/*
+ * I2C各个寄存器相对基地址的偏移
+ * 发送数据寄存器和接收数据寄存器的偏移是相同的
+ * 命令寄存器和状态寄存器的偏移是相同的，不同的是命令寄存器只写，状态寄存器只读
+ */
+#define LS1C_I2C_PRER_LOW_OFFSET            (0)     // 分频锁存器低字节寄存器偏移
+#define LS1C_I2C_PRER_HIGH_OFFSET           (1)     // 分频锁存器高字节寄存器偏移
+#define LS1C_I2C_CONTROL_OFFSET             (2)     // 控制寄存器偏移
+#define LS1C_I2C_DATA_OFFSET                (3)     // 发送数据寄存器和接收数据寄存器的偏移是相同的
+#define LS1C_I2C_CMD_OFFSET                 (4)     // 命令寄存器偏移，只写
+#define LS1C_I2C_STATUS_OFFSET              (4)     // 状态寄存器偏移，只读
+
+
+// 控制寄存器的位域
+#define LS1C_I2C_CONTROL_EN                 (0x80)  // i2c模块使能
+#define LS1C_I2C_CONTROL_IEN                (0x40)  // 中断使能
+
+// 命令寄存器的位域
+#define LS1C_I2C_CMD_START                  (0x90)  // 产生START信号
+#define LS1C_I2C_CMD_STOP                   (0x40)  // 产生STOP信号
+#define LS1C_I2C_CMD_READ                   (0x20)  // 产生读信号，即产生ACK信号
+#define LS1C_I2C_CMD_WRITE                  (0x10)  // 产生写信号
+#define LS1C_I2C_CMD_READ_ACK               (0x20)  // 产生ACK信号，与读信号相同
+#define LS1C_I2C_CMD_READ_NACK              (0x28)  // 产生NACK信号
+#define LS1C_I2C_CMD_IACK                   (0x00)  // 产生中断应答信号
+
+// 状态寄存器的位域
+#define LS1C_I2C_STATUS_IF                  (0x01)  // 中断标志位
+#define LS1C_I2C_STATUS_TIP                 (0x02)  // 指示传输的过程。1，正在传输；0，传输完成
+#define LS1C_I2C_STATUS_ARBLOST             (0x20)  // I2C核失去I2C总线的控制权
+#define LS1C_I2C_STATUS_BUSY                (0x40)  // I2C总线忙标志
+#define LS1C_I2C_STATUS_NACK                (0x80)  // 应答位标志。1，没收到应答位；0，收到应答位
+
+
+/*
+ * 获取指定i2c模块的基地址
+ * @I2Cx I2C模块的编号
+ */
+void *i2c_get_base(ls1c_i2c_t I2Cx)
+{
+    void *base = NULL;
+    
+    switch (I2Cx)
+    {
+        case LS1C_I2C_0:
+            base = (void *)LS1C_I2C0_BASE;
+            break;
+
+        case LS1C_I2C_1:
+            base = (void *)LS1C_I2C1_BASE;
+            break;
+
+        case LS1C_I2C_2:
+            base = (void *)LS1C_I2C2_BASE;
+            break;
+
+        default:
+            base = NULL;
+            break;
+    }
+
+    return base;
+}
+
+
+/*
+ * 向命令寄存器写命令
+ * @i2c_info_p i2c模块信息
+ * @cmd 命令
+ */
+void i2c_cmd(ls1c_i2c_info_t *i2c_info_p, unsigned char cmd)
+{
+    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
+
+    reg_write_8(cmd, i2c_base + LS1C_I2C_CMD_OFFSET);
+
+    return ;
+}
+
+
+/*
+ * 执行START命令，发送START信号
+ * @i2c_info_p i2c模块信息
+ */
+void i2c_cmd_start(ls1c_i2c_info_t *i2c_info_p)
+{
+    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_START);
+    return ;
+}
+
+
+/*
+ * 执行STOP命令，发送STOP信号
+ * @i2c_info_p i2c模块信息
+ */
+void i2c_cmd_stop(ls1c_i2c_info_t *i2c_info_p)
+{
+    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_STOP);
+    return ;
+}
+
+
+/*
+ * 执行写命令
+ * @i2c_info_p i2c模块信息
+ */
+void i2c_cmd_write(ls1c_i2c_info_t *i2c_info_p)
+{
+    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_WRITE);
+    return ;
+}
+
+
+/*
+ * 执行读ack命令，发送读ack信号
+ * @i2c_info_p i2c模块信息
+ */
+void i2c_cmd_read_ack(ls1c_i2c_info_t *i2c_info_p)
+{
+    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_READ_ACK);
+    return ;
+}
+
+
+/*
+ * 执行读nack命令,发送读nack信号
+ * @i2c_info_p i2c模块信息
+ */
+void i2c_cmd_read_nack(ls1c_i2c_info_t *i2c_info_p)
+{
+    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_READ_NACK);
+    return ;
+}
+
+
+/*
+ * 发送中断应答信号
+ * @i2c_info_p i2c模块信息
+ */
+void i2c_cmd_iack(ls1c_i2c_info_t *i2c_info_p)
+{
+    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_IACK);
+    return ;
+}
+
+
+/*
+ * 获取状态寄存器的值
+ * @i2c_info_p i2c模块信息
+ * @ret 状态寄存器的值
+ */
+unsigned char i2c_get_status(ls1c_i2c_info_t *i2c_info_p)
+{
+    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
+
+    return reg_read_8(i2c_base + LS1C_I2C_STATUS_OFFSET);
+}
+
+
+/*
+ * Poll the i2c status register until the specified bit is set.
+ * Returns 0 if timed out (100 msec).
+ * @i2c_info_p i2c模块信息
+ * @bit 寄存器的某一位
+ * @ret true or false
+ */
+int i2c_poll_status(ls1c_i2c_info_t *i2c_info_p, unsigned long bit)
+{
+    int loop_cntr = 20000;
+
+    do {
+        delay_us(1);
+    } while ((i2c_get_status(i2c_info_p) & bit) && (0 < --loop_cntr));
+
+    return (0 < loop_cntr);
+}
+
+
+/*
+ * 初始化指定i2c模块
+ * @i2c_info_p 某个i2c模块的信息
+ */
+void i2c_init(ls1c_i2c_info_t *i2c_info_p)
+{
+    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
+    unsigned long i2c_clock = i2c_info_p->clock;
+    unsigned char ctrl = reg_read_8(i2c_base + LS1C_I2C_CONTROL_OFFSET);
+    unsigned long prescale = 0;
+
+    /* make sure the device is disabled */
+    ctrl = ctrl & ~(LS1C_I2C_CONTROL_EN | LS1C_I2C_CONTROL_IEN);
+    reg_write_8(ctrl, i2c_base + LS1C_I2C_CONTROL_OFFSET);
+
+    // 设置时钟
+    i2c_clock = MIN(i2c_clock, LS1C_I2C_CLOCK_MAX);     // 限制在最大允许范围内
+    prescale = clk_get_apb_rate();
+    prescale = (prescale / (5 * i2c_clock)) - 1;
+    reg_write_8(prescale & 0xff, i2c_base + LS1C_I2C_PRER_LOW_OFFSET);
+    reg_write_8(prescale >> 8, i2c_base + LS1C_I2C_PRER_HIGH_OFFSET);
+    
+    // 使能
+    i2c_cmd_iack(i2c_info_p);
+    ctrl = ctrl | LS1C_I2C_CONTROL_EN;
+    reg_write_8(ctrl, i2c_base + LS1C_I2C_CONTROL_OFFSET);
+
+    return ;
+}
+
+
+/*
+ * (再发送一个字节数据之后)接收从机发送的ACK信号
+ * @i2c_info_p i2c模块信息
+ * @ret LS1C_I2C_ACK or LS1C_I2C_NACK
+ */
+ls1c_i2c_ack_t i2c_receive_ack(ls1c_i2c_info_t *i2c_info_p)
+{
+    ls1c_i2c_ack_t ret = LS1C_I2C_NACK;
+    
+    if (LS1C_I2C_STATUS_NACK & i2c_get_status(i2c_info_p))
+    {
+        ret = LS1C_I2C_NACK;
+    }
+    else
+    {
+        ret = LS1C_I2C_ACK;
+    }
+
+    return ret;
+}
+
+
+/*
+ * 接收数据
+ * @i2c_info_p i2c模块信息
+ * @buf 数据缓存
+ * @len 待接收数据的长度
+ */
+ls1c_i2c_ret_t i2c_receive_data(ls1c_i2c_info_t *i2c_info_p, unsigned char *buf, int len)
+{
+    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
+    int i = 0;
+
+    for (i=0; i<len; i++)
+    {
+        // 开始接收
+        if (i != (len - 1))
+            i2c_cmd_read_ack(i2c_info_p);
+        else 
+            i2c_cmd_read_nack(i2c_info_p);
+
+        // 等待，直到接收完成
+        if (!i2c_poll_status(i2c_info_p, LS1C_I2C_STATUS_TIP))
+            return LS1C_I2C_RET_TIMEOUT;
+
+        // 读取数据，并保存
+        *buf++ = reg_read_8(i2c_base + LS1C_I2C_DATA_OFFSET);
+    }
+
+    return LS1C_I2C_RET_OK;
+}
+
+
+/*
+ * 发送START信号和地址
+ * @i2c_info_p i2c模块信息
+ * @slave_addr 从机地址
+ * @direction 数据传输方向(读、写)
+ */
+ls1c_i2c_ret_t i2c_send_start_and_addr(ls1c_i2c_info_t *i2c_info_p, 
+                                       unsigned char slave_addr,
+                                       ls1c_i2c_direction_t direction)
+{
+    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
+    unsigned char data = 0;
+    
+    // 等待i2c总线空闲
+    if (!i2c_poll_status(i2c_info_p, LS1C_I2C_STATUS_BUSY))
+        return LS1C_I2C_RET_TIMEOUT;
+
+    // 填充地址到数据寄存器
+    data = (slave_addr << 1) | ((LS1C_I2C_DIRECTION_READ == direction) ? 1 : 0);
+    reg_write_8(data , i2c_base + LS1C_I2C_DATA_OFFSET);
+
+    // 开始发送
+    i2c_cmd_start(i2c_info_p);
+
+    // 等待，直到发送完成
+    if (!i2c_poll_status(i2c_info_p, LS1C_I2C_STATUS_TIP))
+        return LS1C_I2C_RET_TIMEOUT;
+
+    return LS1C_I2C_RET_OK;
+}
+
+
+/*
+ * 发送数据
+ * @i2c_info_p i2c模块信息
+ * @data 待发送的数据
+ * @len 待发送数据的长度
+ */
+ls1c_i2c_ret_t i2c_send_data(ls1c_i2c_info_t *i2c_info_p, unsigned char *data, int len)
+{
+    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
+    int i = 0;
+
+    for (i=0; i<len; i++)
+    {
+        // 将一个字节数据写入数据寄存器
+        reg_write_8(*data++, i2c_base + LS1C_I2C_DATA_OFFSET);
+
+        // 开始发送
+        reg_write_8(LS1C_I2C_CMD_WRITE, i2c_base + LS1C_I2C_CMD_OFFSET);
+
+        // 等待，直到发送完成
+        if (!i2c_poll_status(i2c_info_p, LS1C_I2C_STATUS_TIP))
+            return LS1C_I2C_RET_TIMEOUT;
+
+        // 读取应答信号
+        if (LS1C_I2C_ACK != i2c_receive_ack(i2c_info_p))
+            return len;
+    }
+
+    return LS1C_I2C_RET_OK;
+}
+
+
+
+/*
+ * 发送STOP信号
+ * @i2c_info_p i2c模块信息
+ */
+void i2c_send_stop(ls1c_i2c_info_t *i2c_info_p)
+{
+    i2c_cmd_stop(i2c_info_p);
+    return ;
+}
+
+
diff --git a/bsp/ls1cdev/libraries/ls1c_i2c.h b/bsp/ls1cdev/libraries/ls1c_i2c.h
new file mode 100644
index 0000000000..ada22242fb
--- /dev/null
+++ b/bsp/ls1cdev/libraries/ls1c_i2c.h
@@ -0,0 +1,134 @@
+/*
+ * File      : ls1c_i2c.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ */
+
+
+// 硬件i2c接口的头文件
+
+#ifndef __OPENLOONGSON_I2C_H
+#define __OPENLOONGSON_I2C_H
+
+
+
+// I2C的时钟频率
+#define LS1C_I2C_CLOCK_DEFAULT              (100000)  // Hz. 默认频率
+#define LS1C_I2C_CLOCK_MAX                  (400000)  // Hz, max 400 Kbits/sec
+
+
+// I2C模块编号
+typedef enum
+{
+    LS1C_I2C_0 = 0,
+    LS1C_I2C_1,
+    LS1C_I2C_2
+}ls1c_i2c_t;
+
+
+// I2C数据传输方向
+typedef enum
+{
+    LS1C_I2C_DIRECTION_WRITE = 0,       // 主机向从机写信息
+    LS1C_I2C_DIRECTION_READ,            // 主机向从机读信息
+}ls1c_i2c_direction_t;
+
+
+// 硬件I2C信息
+typedef struct
+{
+    ls1c_i2c_t I2Cx;                    // i2c模块编号
+    unsigned long clock;                // i2c时钟频率，单位hz
+}ls1c_i2c_info_t;
+
+
+// I2C应答
+typedef enum
+{
+    LS1C_I2C_ACK = 0,                   // 收到应答
+    LS1C_I2C_NACK = 1,                  // 没收到应答
+}ls1c_i2c_ack_t;
+
+
+// 函数返回值
+typedef enum
+{
+    LS1C_I2C_RET_OK = 0,                // OK
+    LS1C_I2C_RET_TIMEOUT,               // 超时
+}ls1c_i2c_ret_t;
+
+
+
+/*
+ * 初始化指定i2c模块
+ * @i2c_info_p 某个i2c模块的信息
+ */
+void i2c_init(ls1c_i2c_info_t *i2c_info_p);
+
+
+/*
+ * (再发送一个字节数据之后)接收从机发送的ACK信号
+ * @i2c_info_p i2c模块信息
+ * @ret LS1C_I2C_ACK or LS1C_I2C_NACK
+ */
+ls1c_i2c_ack_t i2c_receive_ack(ls1c_i2c_info_t *i2c_info_p);
+
+
+/*
+ * 接收数据
+ * @i2c_info_p i2c模块信息
+ * @buf 数据缓存
+ * @len 待接收数据的长度
+ */
+ls1c_i2c_ret_t i2c_receive_data(ls1c_i2c_info_t *i2c_info_p, unsigned char *buf, int len);
+
+
+
+/*
+ * 发送START信号和地址
+ * @i2c_info_p i2c模块信息
+ * @slave_addr 从机地址
+ * @direction 数据传输方向(读、写)
+ */
+ls1c_i2c_ret_t i2c_send_start_and_addr(ls1c_i2c_info_t *i2c_info_p, 
+                                       unsigned char slave_addr,
+                                       ls1c_i2c_direction_t direction);
+
+
+/*
+ * 发送数据
+ * @i2c_info_p i2c模块信息
+ * @data 待发送的数据
+ * @len 待发送数据的长度
+ */
+ls1c_i2c_ret_t i2c_send_data(ls1c_i2c_info_t *i2c_info_p, unsigned char *data, int len);
+
+
+/*
+ * 发送STOP信号
+ * @i2c_info_p i2c模块信息
+ */
+void i2c_send_stop(ls1c_i2c_info_t *i2c_info_p);
+
+
+
+#endif
+
diff --git a/bsp/ls1cdev/libraries/ls1c_public.c b/bsp/ls1cdev/libraries/ls1c_public.c
index 84518f0bd0..a04f68a877 100644
--- a/bsp/ls1cdev/libraries/ls1c_public.c
+++ b/bsp/ls1cdev/libraries/ls1c_public.c
@@ -54,6 +54,28 @@ unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit)
 }
 
 
+/*
+ * 向寄存器中写入8bit(一个字节)数据
+ * @data 待写入的数据
+ * @addr 寄存器地址
+ */
+void reg_write_8(unsigned char data, volatile unsigned char *addr)
+{
+    *addr = data;
+}
+
+
+/*
+ * 从寄存器读出8bit(一个字节)数据
+ * @addr 寄存器地址
+ * @ret 读出的数据
+ */
+unsigned char reg_read_8(volatile unsigned char *addr)
+{
+    return (*addr);
+}
+
+
 /*
  * 向寄存器中写一个32bit的数据
  * @data 待写入的数据
diff --git a/bsp/ls1cdev/libraries/ls1c_public.h b/bsp/ls1cdev/libraries/ls1c_public.h
index 3ecabeafaa..34164d8c1c 100644
--- a/bsp/ls1cdev/libraries/ls1c_public.h
+++ b/bsp/ls1cdev/libraries/ls1c_public.h
@@ -57,6 +57,22 @@ void reg_clr_one_bit(volatile unsigned int *reg, unsigned int bit);
 unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit);
 
 
+/*
+ * 向寄存器中写入8bit(一个字节)数据
+ * @data 待写入的数据
+ * @addr 寄存器地址
+ */
+void reg_write_8(unsigned char data, volatile unsigned char *addr);
+
+
+/*
+ * 从寄存器读出8bit(一个字节)数据
+ * @addr 寄存器地址
+ * @ret 读出的数据
+ */
+unsigned char reg_read_8(volatile unsigned char *addr);
+
+
 /*
  * 向寄存器中写一个32bit的数据
  * @data 待写入的数据
diff --git a/bsp/ls1cdev/libraries/ls1c_regs.h b/bsp/ls1cdev/libraries/ls1c_regs.h
index fb67086d34..3d23429865 100644
--- a/bsp/ls1cdev/libraries/ls1c_regs.h
+++ b/bsp/ls1cdev/libraries/ls1c_regs.h
@@ -111,6 +111,11 @@
 #define LS1C_INT4_EDGE                      (0xbfd010b4)
 
 
+// I2C寄存器
+#define LS1C_I2C0_BASE                      (0xbfe58000)
+#define LS1C_I2C1_BASE                      (0xbfe68000)
+#define LS1C_I2C2_BASE                      (0xbfe70000)
+
 
 #endif
 
diff --git a/bsp/ls1cdev/rtconfig.h b/bsp/ls1cdev/rtconfig.h
index 99bb973b90..8f87497875 100644
--- a/bsp/ls1cdev/rtconfig.h
+++ b/bsp/ls1cdev/rtconfig.h
@@ -75,6 +75,8 @@
 #define RT_UART_RX_BUFFER_SIZE	64
 // </section>
 
+#define RT_USING_FPU
+
 // <section name="RT_USING_CONSOLE" description="Using console" default="true" >
 #define RT_USING_CONSOLE
 // <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
diff --git a/bsp/nv32f100x/SConscript b/bsp/nv32f100x/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/nv32f100x/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nv32f100x/SConstruct b/bsp/nv32f100x/SConstruct
new file mode 100644
index 0000000000..47ac06abf2
--- /dev/null
+++ b/bsp/nv32f100x/SConstruct
@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-nv32f100x.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/nv32f100x/app/SConscript b/bsp/nv32f100x/app/SConscript
new file mode 100644
index 0000000000..5260088eb3
--- /dev/null
+++ b/bsp/nv32f100x/app/SConscript
@@ -0,0 +1,15 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'app')
+
+src	= Glob('./src/*.c')
+
+path = [cwd + '/inc',
+	cwd + '/..',
+	]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nv32f100x/app/src/ledapp.c b/bsp/nv32f100x/app/src/ledapp.c
new file mode 100644
index 0000000000..a52b0eb8a9
--- /dev/null
+++ b/bsp/nv32f100x/app/src/ledapp.c
@@ -0,0 +1,39 @@
+/*
+ * File      : ledapp.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+ 
+#include <stdio.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+#include <rtthread.h>
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+#include "gpio.h"
+
+
+void led_thread_entry(void* parameter)
+{
+
+    GPIO_Init  (GPIOA, GPIO_PTB5_MASK, GPIO_PinOutput);
+    
+	while(1)
+	{
+        GPIO_Toggle  (GPIOA, GPIO_PTB5_MASK);
+        rt_thread_delay(RT_TICK_PER_SECOND / 10);
+
+	}
+}
diff --git a/bsp/nv32f100x/app/src/main.c b/bsp/nv32f100x/app/src/main.c
new file mode 100644
index 0000000000..b63fa2f4dc
--- /dev/null
+++ b/bsp/nv32f100x/app/src/main.c
@@ -0,0 +1,46 @@
+/*
+ * File      : _main.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-11-19     Urey         the first version
+ * 2017-09-20     Quintin.Z    modify for nv32
+ */
+#include "rtthread.h"
+#include "finsh.h"
+
+extern void led_thread_entry(void* parameter);
+
+int main(void)
+{
+    rt_thread_t thread;
+
+#ifdef  RT_USING_FINSH
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Create led thread */
+    thread = rt_thread_create("led",
+                              led_thread_entry, RT_NULL,
+                              256, 20, 20);
+    if(thread != RT_NULL)
+        rt_thread_startup(thread);
+
+    return 0;
+}
diff --git a/bsp/nv32f100x/board/SConscript b/bsp/nv32f100x/board/SConscript
new file mode 100644
index 0000000000..90fe4bb007
--- /dev/null
+++ b/bsp/nv32f100x/board/SConscript
@@ -0,0 +1,12 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'board')
+src	= Glob('./src/*.c')
+path = [cwd + '/inc'
+	]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nv32f100x/board/inc/board.h b/bsp/nv32f100x/board/inc/board.h
new file mode 100644
index 0000000000..3639fa0b03
--- /dev/null
+++ b/bsp/nv32f100x/board/inc/board.h
@@ -0,0 +1,30 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+
+// <o> Internal SRAM memory size[Kbytes] <8>
+#define NV32_SRAM_SIZE         8
+#define NV32_SRAM_END          (0x1FFFF800 + NV32_SRAM_SIZE * 1024)
+
+void rt_hw_board_init(void);
+
+
+#endif
diff --git a/bsp/nv32f100x/board/inc/drv_uart.h b/bsp/nv32f100x/board/inc/drv_uart.h
new file mode 100644
index 0000000000..d1e0c6c109
--- /dev/null
+++ b/bsp/nv32f100x/board/inc/drv_uart.h
@@ -0,0 +1,23 @@
+/*
+ * File      : drv_uart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+void rt_hw_uart_init(void);
+
+#endif
diff --git a/bsp/nv32f100x/board/inc/start.h b/bsp/nv32f100x/board/inc/start.h
new file mode 100644
index 0000000000..5a4f7d0991
--- /dev/null
+++ b/bsp/nv32f100x/board/inc/start.h
@@ -0,0 +1,9 @@
+/******************************************************************************
+* @brief provide high-level startup routines for NV32Fxx.
+*
+*******************************************************************************/
+
+/* Function prototypes */
+void cpu_identify(void);
+void flash_identify(void);
+void start(void);
diff --git a/bsp/nv32f100x/board/inc/sysinit.h b/bsp/nv32f100x/board/inc/sysinit.h
new file mode 100644
index 0000000000..e7606b5a29
--- /dev/null
+++ b/bsp/nv32f100x/board/inc/sysinit.h
@@ -0,0 +1,38 @@
+/******************************************************************************
+* @brief provide system init routine/configuration for KExx.
+*
+*******************************************************************************/
+
+/********************************************************************/
+
+#ifndef SYSINIT_H_
+#define SYSINIT_H_
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+
+/******************************************************************************
+* Macros
+******************************************************************************/ 
+#define SIM_SCGC_VALUE      0x00003000L  
+
+  
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void sysinit (void);
+void enable_abort_button(void);
+void end_test(void);
+
+/********************************************************************/
+#endif /* SYSINIT_H_ */
diff --git a/bsp/nv32f100x/board/src/board.c b/bsp/nv32f100x/board/src/board.c
new file mode 100644
index 0000000000..23ec89f114
--- /dev/null
+++ b/bsp/nv32f100x/board/src/board.c
@@ -0,0 +1,127 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "sysinit.h"
+#include "board.h"
+#include "drv_uart.h"
+#include "nv32.h"
+
+/* RT_USING_COMPONENTS_INIT */
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif
+
+
+#define portNVIC_SYSTICK_CTRL           ( ( volatile uint32_t *) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD           ( ( volatile uint32_t *) 0xe000e014 )
+#define portNVIC_INT_CTRL               ( ( volatile uint32_t *) 0xe000ed04 )
+#define portNVIC_SYSPRI2                ( ( volatile uint32_t *) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK            0x00000004
+#define portNVIC_SYSTICK_INT            0x00000002
+#define portNVIC_SYSTICK_ENABLE         0x00000001
+#define portNVIC_PENDSVSET              0x10000000
+#define portMIN_INTERRUPT_PRIORITY      ( 255UL )
+#define portNVIC_PENDSV_PRI             ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI            ( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define NV32_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define NV32_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define NV32_SRAM_BEGIN    (&__bss_end)
+#endif
+
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+	rt_kprintf("       file  %s\r\n", file);
+	rt_kprintf("       line  %d\r\n", line);
+
+	while (1) ;
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+/**
+ * This function will initial STM32 board.
+ */
+void rt_hw_board_init()
+{
+    /* Configure the SysTick */
+    *(portNVIC_SYSTICK_LOAD) = ( 40000000 / RT_TICK_PER_SECOND ) - 1UL;
+    *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+
+    rt_hw_uart_init();
+
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void*)NV32_SRAM_BEGIN, (void*)NV32_SRAM_END);
+#endif
+
+
+
+
+}
+
+long cmd_reset(int argc, char** argv)
+{
+    NVIC_SystemReset();
+
+    return 0;
+}
+
+FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, Reset Board.);
+
+
+
+/*@}*/
diff --git a/bsp/nv32f100x/board/src/drv_uart.c b/bsp/nv32f100x/board/src/drv_uart.c
new file mode 100644
index 0000000000..d8629d804d
--- /dev/null
+++ b/bsp/nv32f100x/board/src/drv_uart.c
@@ -0,0 +1,189 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+
+#include <rtdevice.h>
+#include <board.h>
+#include "drv_uart.h"
+#include "nv32.h"
+#include "uart.h"
+#include "sim.h"
+
+/* NV32 uart driver */
+struct nv32_uart
+{
+    UART_Type* uart_device;
+    IRQn_Type irq;
+};
+
+static rt_err_t nv32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct nv32_uart* uart;
+
+    UART_ConfigBaudrateType uart_config;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = (struct nv32_uart *)serial->parent.user_data;
+
+    uart_config.u32SysClkHz = BUS_CLK_HZ;
+    uart_config.u32Baudrate = cfg->baud_rate;
+
+    UART_SetBaudrate(uart->uart_device, &uart_config);
+
+
+    if (cfg->data_bits == DATA_BITS_8)
+    {
+        UART_Set8BitMode(uart->uart_device);
+    }
+    else if(cfg->data_bits == DATA_BITS_9)
+    {
+        UART_Set9BitMode(uart->uart_device);
+    }
+
+    if (cfg->stop_bits == STOP_BITS_1)
+    {
+        uart->uart_device->BDH  &= (~UART_BDH_SBNS_MASK);
+    }
+    else if (cfg->stop_bits == STOP_BITS_2)
+    {
+        uart->uart_device->BDH  |= UART_BDH_SBNS_MASK;
+    }
+
+    /* Enable receiver and transmitter */
+    uart->uart_device->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
+
+
+    UART_EnableInterrupt(UART0, UART_RxBuffFullInt);
+    NVIC_EnableIRQ(UART0_IRQn);
+
+
+    return RT_EOK;
+}
+
+static rt_err_t nv32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct nv32_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct nv32_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+        case RT_DEVICE_CTRL_CLR_INT:
+            /* disable rx irq */
+            NVIC_DisableIRQ(uart->irq);
+            break;
+        case RT_DEVICE_CTRL_SET_INT:
+            /* enable rx irq */
+            NVIC_EnableIRQ(uart->irq);
+            break;
+    }
+
+    return RT_EOK;
+}
+
+static int nv32_putc(struct rt_serial_device *serial, char c)
+{
+    struct nv32_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct nv32_uart *)serial->parent.user_data;
+
+    while (!(uart->uart_device->S1 & UART_S1_TDRE_MASK));
+
+    uart->uart_device->D = (uint8_t)c;
+
+    return 1;
+}
+
+
+static int nv32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct nv32_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct nv32_uart *)serial->parent.user_data;
+
+    ch = -1;
+    if (uart->uart_device->S1 & UART_S1_RDRF_MASK)
+    {
+        ch = uart->uart_device->D;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops nv32_uart_ops =
+{
+    nv32_configure,
+    nv32_control,
+    nv32_putc,
+    nv32_getc,
+};
+
+#ifdef RT_USING_UART0
+
+struct nv32_uart uart0 =
+{
+    UART0,
+    UART0_IRQn,
+};
+
+struct rt_serial_device serial0;
+
+void UART0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if(UART0->S1 & UART_S1_RDRF_MASK)
+    {
+        rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif
+
+
+void rt_hw_uart_init(void)
+{
+    struct nv32_uart* uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART0
+    uart = &uart0;
+
+    serial0.ops    = &nv32_uart_ops;
+    serial0.config = config;
+
+
+    SIM->PINSEL |= SIM_PINSEL_UART0PS_MASK;
+
+    SIM->SCGC |= SIM_SCGC_UART0_MASK;
+
+    uart->uart_device->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
+
+    /* Configure the UART for 8-bit mode, no parity */
+    uart->uart_device->C1 = 0;
+
+    rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+#endif
+
+}
+
diff --git a/bsp/nv32f100x/board/src/start.c b/bsp/nv32f100x/board/src/start.c
new file mode 100644
index 0000000000..9fdaeed0c2
--- /dev/null
+++ b/bsp/nv32f100x/board/src/start.c
@@ -0,0 +1,36 @@
+/******************************************************************************
+* @brief provide high-level startup routines for NV32Fxx.
+*
+*******************************************************************************/
+
+#include "start.h"
+#include "common.h"
+#include "wdog.h"
+#include "sysinit.h"
+
+/********************************************************************/
+/********************************************************************/
+/*!
+ * \brief   flash SystemInit
+ * \return  None
+ *
+ * this is a system initialization function which dediu16Cated in Keil
+ * others complier don't use it.
+ * it is similar to start function
+ */
+void SystemInit( void )
+{
+#if !defined(ENABLE_WDOG)
+    /* Disable the watchdog ETMer */
+    WDOG_Disable();
+#else
+    /* Disable the watchdog ETMer but enable update */
+    WDOG_DisableWDOGEnableUpdate();
+#endif
+
+    sysinit();
+
+}
+
+
+
diff --git a/bsp/nv32f100x/board/src/sysinit.c b/bsp/nv32f100x/board/src/sysinit.c
new file mode 100644
index 0000000000..c317327643
--- /dev/null
+++ b/bsp/nv32f100x/board/src/sysinit.c
@@ -0,0 +1,124 @@
+/*****************************************************************************
+* @brief provide system init routine/configuration for NV32Fxx.
+*
+*******************************************************************************/
+
+#include "common.h"
+#include "sysinit.h"
+#include "sim.h"
+#include "uart.h"
+#include "ics.h"
+
+/********************************************************************/
+
+uint16_t global_pass_count = 0;
+uint16_t global_fail_count = 0;
+
+
+void print_sys_log(void);
+void UART_InitPrint(void);
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: sysinit
+*
+* @brief  initalize system including SIM, ICS, UART, etc
+*
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void sysinit (void)
+{
+    SIM_ConfigType  sSIMConfig = {{0}, 0};
+    ICS_ConfigType  sICSConfig = {0};
+
+    /* initialize the Pass/Fail counts to 0 */
+    global_pass_count = 0;
+    global_fail_count = 0;
+
+    EFMCR &= 0xFFFF0001; // set wait state 1
+
+#if defined(TRIM_IRC)
+    /* if not trimmed, do trim first */
+    ICS_Trim(ICS_TRIM_VALUE);
+#endif
+    /*
+     * Enable SWD pin, RESET pin
+     */
+    /*
+     * NOTE: please make sure other register bits are also write-once and
+     * need add other bit mask here if needed.
+     */
+#if defined(SPI0_PINREMAP)
+    sSIMConfig.u32PinSel |= SIM_PINSEL_SPI0PS_MASK;
+#endif
+
+#if defined(OUTPUT_BUSCLK)
+    sSIMConfig.sBits.bEnableCLKOUT = 1;      /* output bus clock if enabled */
+#endif
+
+#if defined(DISABLE_NMI)
+    sSIMConfig.sBits.bDisableNMI = 1;
+#endif
+
+#if !defined(CPU_NV32M3)
+    /* make sure clocks to peripheral modules are enabled */
+    sSIMConfig.u32SCGC |= SIM_SCGC_SWD_MASK | SIM_SCGC_FLASH_MASK |
+                          SIM_SCGC_UART0_MASK | SIM_SCGC_UART1_MASK |
+                          SIM_SCGC_UART2_MASK
+                          ;
+#else
+    sSIMConfig.u32SCGC |= SIM_SCGC_SWD_MASK | SIM_SCGC_FLASH_MASK |
+                          SIM_SCGC_UART0_MASK
+                          ;
+#endif
+
+#if !defined(CPU_NV32)
+    /* bus clock divided by 2 */
+    // sSIMConfig.u32BusDiv |= SIM_CLKDIV_OUTDIV2_MASK;
+#endif
+
+//  sSIMConfig.sBits.bBusDiv |= SIM_BUSDIV_BUSDIV_MASK;
+
+    SIM_Init(&sSIMConfig);                   /* initialize SIM */
+
+#if defined(XOSC_STOP_ENABLE)
+    sICSConfig.oscConfig.bStopEnable = 1;    /*  enabled in stop mode */
+#endif
+
+#if defined(CRYST_HIGH_GAIN)
+    sICSConfig.oscConfig.bGain = 1;           /* high gain */
+#endif
+
+
+#if  (EXT_CLK_FREQ_KHZ >=4000)
+    sICSConfig.oscConfig.bRange = 1;           /* high range */
+#endif
+
+    sICSConfig.oscConfig.bEnable = 1;          /* enable OSC */
+    sICSConfig.u32ClkFreq = EXT_CLK_FREQ_KHZ;
+
+#if     defined(USE_FEE)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FEE;
+#elif   defined(USE_FBE_OSC)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FBE_OSC;
+#elif   defined(USE_FEE_OSC)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FEE_OSC;
+#elif   defined(USE_FBILP)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FBILP;
+#elif   defined(USE_FBELP)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FBELP;
+#endif
+
+    ICS_Init(&sICSConfig);   /* initialize ICS */
+
+
+}
+
+void NMI_Handler(void)
+{
+    while(1);
+}
diff --git a/bsp/nv32f100x/lib/SConscript b/bsp/nv32f100x/lib/SConscript
new file mode 100644
index 0000000000..9f78108059
--- /dev/null
+++ b/bsp/nv32f100x/lib/SConscript
@@ -0,0 +1,16 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'lib')
+src	= Glob('./src/*.c')
+
+src += Glob('./src/*.s')
+path = [cwd + '/inc'
+	]
+
+CPPDEFINES = ['NV32', 'KEIL']
+
+group = DefineGroup('Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/nv32f100x/lib/inc/BME.h b/bsp/nv32f100x/lib/inc/BME.h
new file mode 100644
index 0000000000..291cd4a0ad
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/BME.h
@@ -0,0 +1,606 @@
+
+/******************************************************************************
+******************************************************************************/
+
+#ifndef __BME_H
+#define __BME_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* BME operation code
+*
+*//*! @addtogroup BME_OPCode
+* @{
+*******************************************************************************/
+
+#define BME_OPCODE_AND		1               /*!< AND opcode */
+#define BME_OPCODE_OR		2               /*!< OR opcode */
+#define BME_OPCODE_XOR		3               /*!< XOR opcode */
+#define BME_OPCODE_BITFIELD	4               /*!< Bit field opcode */
+
+#define BME_OPCODE_BIT_CLEAR    2           /*!< Bit clear opcode */
+#define BME_OPCODE_BIT_SET      3           /*!< Bit set opcode */
+/*! @} End of BME_OPCode                                                   */
+
+/******************************************************************************
+* BME macro used to generate hardcoded BME addresses
+*
+*//*! @addtogroup BME_Utilities
+* @{
+*******************************************************************************/
+
+/******************************************************************************
+* macro used to generate hardcoded AND address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME AND operation addresss (hardcoded 32-bit address).
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+#define BME_AND(ADDR)           (*(volatile uint32_t *)(((uint32_t)ADDR) | (BME_OPCODE_AND<<26)))  
+
+/******************************************************************************
+* macro used to generate hardcoded OR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME OR operation addresss (hardcoded 32-bit address).
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_OR(ADDR)           (*(volatile uint32_t *)(((uint32_t)ADDR) | (BME_OPCODE_OR<<26)))     
+
+
+/******************************************************************************
+* macro used to generate hardcoded XOR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME XOR operation addresss (hardcoded 32-bit address).
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_XOR(ADDR)           (*(volatile uint32_t *)(((uint32_t)ADDR) | (BME_OPCODE_XOR<<26)))   
+
+#if !defined(BME_SANITY_CHECK)
+   /*!
+     * @brief This is fastest way for BME without sanity check.
+     */
+  /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+  /*****************************************************************************//*!
+       *
+       * @brief  generates BME bit clear operation addresss (hardcoded 32-bit address).
+       *        
+       * @param[in]   ADDR  32-bit address.
+       * @param[in]   bit     bit number, 0-based.
+       *  
+       * @return  hardcoded 32-bit address.
+       *
+       * @ Pass/ Fail criteria: none.
+       *
+    *****************************************************************************/
+    
+    #define BME_BIT_CLEAR(ADDR,bit)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit)<<21)))                                                
+
+  /******************************************************************************
+    * macro used to generate hardcoded load 1 bit set address (LAS1).
+    *
+    *******************************************************************************/
+   /*****************************************************************************//*!
+         *
+         * @brief  generates BME bit set operation addresss (hardcoded 32-bit address).
+         *        
+         * @param[in]   ADDR  32-bit address.
+         * @param[in]   bit     bit number, 0-based.
+         *  
+         * @return  hardcoded 32-bit address.
+         *
+         * @ Pass/ Fail criteria: none.
+         *
+      *****************************************************************************/
+
+    #define BME_BIT_SET(ADDR,bit)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit)<<21)))                                                
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+   /*****************************************************************************//*!
+         *
+         * @brief  generates BME bitfield insert operation addresss (hardcoded 32-bit address).
+         *        
+         * @param[in]   ADDR  32-bit address.
+         * @param[in]   bit      bit number, 0-based.
+         * @param[in]   width  bitfield width, 1-based.
+         *  
+         * @return  hardcoded 32-bit address.
+         *
+         * @ Pass/ Fail criteria: none.
+         *
+      *****************************************************************************/    
+    #define BME_BITFIELD_INSERT(ADDR,bit,width)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                        
+
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+      /*****************************************************************************//*!
+              *
+              * @brief  generates BME bitfield extract operation addresss (hardcoded 32-bit address).
+              *        
+              * @param[in]   ADDR  32-bit address.
+              * @param[in]   bit      bit number, 0-based.
+              * @param[in]   width  bitfield width, 1-based.
+              *  
+              * @return  hardcoded 32-bit address.
+              *
+              * @ Pass/ Fail criteria: none.
+              *
+           *****************************************************************************/    
+
+    #define BME_BITFIELD_EXTRACT(ADDR,bit,width)        (*(volatile uint32_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                            
+#else
+    /*!
+     * @brief This is slow way for BME as it has sanity check.
+     */
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_CLEAR(ADDR,bit)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit clear operation */
+
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit set address (LAS1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_SET(ADDR,bit)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit set operation */
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_INSERT(ADDR,bit,width)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield insert operation */
+
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_EXTRACT(ADDR,bit,width)        (*(volatile uint32_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield extract operation */
+
+#endif
+
+/******************************************************************************
+* The following macros are used to generate hardcoded address for 8-bit operation.
+*
+*******************************************************************************/
+
+/******************************************************************************
+* macro used to generate hardcoded AND address for 8-bit operation.
+*
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME AND operation addresss (hardcoded 32-bit address) for 8-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_AND_8b(ADDR)           (*(volatile uint8_t *)(((uint32_t)ADDR) | (BME_OPCODE_AND<<26)))   
+
+/******************************************************************************
+* macro used to generate hardcoded OR address.
+*
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME OR operation addresss (hardcoded 32-bit address) for 8-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_OR_8b(ADDR)           (*(volatile uint8_t *)(((uint32_t)ADDR) | (BME_OPCODE_OR<<26)))    
+
+
+/******************************************************************************
+* macro used to generate hardcoded XOR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME XOR operation addresss (hardcoded 32-bit address) for 8-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_XOR_8b(ADDR)           (*(volatile uint8_t *)(((uint32_t)ADDR) | (BME_OPCODE_XOR<<26)))   
+
+#if !defined(BME_SANITY_CHECK)
+     /*!
+         * @brief This is fastest way for BME without sanity check.
+         */
+    /******************************************************************************
+        * macro used to generate hardcoded load 1 bit clear address (LAC1).
+        *
+        *******************************************************************************/
+
+    /*****************************************************************************//*!
+         *
+         * @brief  generates BME bit clear operation addresss (hardcoded 32-bit address) for 8-bit data.
+         *        
+         * @param[in]   ADDR  32-bit address.
+         * @param[in]   bit     bit number, 0-based.
+         *  
+         * @return  hardcoded 32-bit address.
+         *
+         * @ Pass/ Fail criteria: none.
+         *
+      *****************************************************************************/
+    
+    #define BME_BIT_CLEAR_8b(ADDR,bit)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit)<<21)))                                                
+
+    /******************************************************************************
+        * macro used to generate hardcoded load 1 bit set address (LAS1).
+        *
+        *******************************************************************************/
+    /*****************************************************************************//*!
+             *
+             * @brief  generates BME bit set operation addresss (hardcoded 32-bit address) for 8-bit data.
+             *        
+             * @param[in]   ADDR  32-bit address.
+             * @param[in]   bit     bit number, 0-based.
+             *  
+             * @return  hardcoded 32-bit address.
+             *
+             * @ Pass/ Fail criteria: none.
+             *
+        *****************************************************************************/
+    
+    #define BME_BIT_SET_8b(ADDR,bit)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit)<<21)))                                                
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+
+    /*****************************************************************************//*!
+          *
+          * @brief  generates BME bitfield insert operation addresss (hardcoded 32-bit address) for 8-bit data.
+          *        
+          * @param[in]   ADDR  32-bit address.
+          * @param[in]   bit      bit number, 0-based.
+          * @param[in]   width  bitfield width, 1-based.
+          *  
+          * @return  hardcoded 32-bit address.
+          *
+          * @ Pass/ Fail criteria: none.
+          *
+       *****************************************************************************/        
+
+    #define BME_BITFIELD_INSERT_8b(ADDR,bit,width)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                        
+  /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+   /*****************************************************************************//*!
+         *
+         * @brief  generates BME bitfield extract operation addresss (hardcoded 32-bit address) for 8-bit data.
+         *        
+         * @param[in]   ADDR  32-bit address.
+         * @param[in]   bit      bit number, 0-based.
+         * @param[in]   width  bitfield width, 1-based.
+         *  
+         * @return  hardcoded 32-bit address.
+         *
+         * @ Pass/ Fail criteria: none.
+         *
+      *****************************************************************************/        
+    #define BME_BITFIELD_EXTRACT_8b(ADDR,bit,width)        (*(volatile uint8_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit<<23) | ((width-1))<<19))                        
+#else
+    /*!
+     * @brief This is slow way for BME as it has sanity check.
+     */
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_CLEAR_8b(ADDR,bit)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit clear operation on 8-bit*/
+
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit set address (LAS1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_SET_8b(ADDR,bit)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit set operation on 8-bit */
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_INSERT_8b(ADDR,bit,width)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield insert operation on 8-bit */
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+
+    #define BME_BITFIELD_EXTRACT_8b(ADDR,bit,width)        (*(volatile uint8_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield extract operation on 8-bit*/
+#endif
+
+
+/******************************************************************************
+* The following macros are used to generate hardcoded address for 16-bit operation.
+*
+*******************************************************************************/
+
+/******************************************************************************
+* macro used to generate hardcoded AND address for 16-bit operation.
+*
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME AND operation addresss (hardcoded 32-bit address) for 16-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_AND_16b(ADDR)           (*(volatile uint16_t *)(((uint32_t)ADDR) | (BME_OPCODE_AND<<26)))   
+
+/******************************************************************************
+* macro used to generate hardcoded OR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME OR operation addresss (hardcoded 32-bit address) for 16-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_OR_16b(ADDR)           (*(volatile uint16_t *)(((uint32_t)ADDR) | (BME_OPCODE_OR<<26)))    
+
+
+/******************************************************************************
+* macro used to generate hardcoded XOR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME XOR operation addresss (hardcoded 32-bit address) for 16-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_XOR_16b(ADDR)           (*(volatile uint16_t *)(((uint32_t)ADDR) | (BME_OPCODE_XOR<<26)))   
+
+
+#if !defined(BME_SANITY_CHECK)
+  /*!
+     * @brief This is fastest way for BME without sanity check.
+     */
+
+  /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+    /*****************************************************************************//*!
+             *
+             * @brief  generates BME bit clear operation addresss (hardcoded 32-bit address) for 16-bit data.
+             *        
+             * @param[in]   ADDR  32-bit address.
+             * @param[in]   bit     bit number, 0-based.
+             *  
+             * @return  hardcoded 32-bit address.
+             *
+             * @ Pass/ Fail criteria: none.
+             *
+        *****************************************************************************/
+    
+    #define BME_BIT_CLEAR_16b(ADDR,bit)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit)<<21)))                                               
+
+    /******************************************************************************
+        * macro used to generate hardcoded load 1 bit set address (LAS1).
+        *
+        *******************************************************************************/
+    /*****************************************************************************//*!
+             *
+             * @brief  generates BME bit set operation addresss (hardcoded 32-bit address) for 16-bit data.
+             *        
+             * @param[in]   ADDR  32-bit address.
+             * @param[in]   bit     bit number, 0-based.
+             *  
+             * @return  hardcoded 32-bit address.
+             *
+             * @ Pass/ Fail criteria: none.
+             *
+        *****************************************************************************/
+    
+    #define BME_BIT_SET_16b(ADDR,bit)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit)<<21)))                                                
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+    /*****************************************************************************//*!
+          *
+          * @brief  generates BME bitfield insert operation addresss (hardcoded 32-bit address) for 16-bit data.
+          *        
+          * @param[in]   ADDR  32-bit address.
+          * @param[in]   bit      bit number, 0-based.
+          * @param[in]   width  bitfield width, 1-based.
+          *  
+          * @return  hardcoded 32-bit address.
+          *
+          * @ Pass/ Fail criteria: none.
+          *
+       *****************************************************************************/        
+    
+    #define BME_BITFIELD_INSERT_16b(ADDR,bit,width)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                        
+
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+    /*****************************************************************************//*!
+          *
+          * @brief  generates BME bitfield extract operation addresss (hardcoded 32-bit address) for 16-bit data.
+          *        
+          * @param[in]   ADDR  32-bit address.
+          * @param[in]   bit      bit number, 0-based.
+          * @param[in]   width  bitfield width, 1-based.
+          *  
+          * @return  hardcoded 32-bit address.
+          *
+          * @ Pass/ Fail criteria: none.
+          *
+       *****************************************************************************/        
+
+    #define BME_BITFIELD_EXTRACT_16b(ADDR,bit,width)        (*(volatile uint16_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                        
+
+#else
+    /*!
+     * @brief This is slow way for BME as it has sanity check.
+     */
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_CLEAR_16b(ADDR,bit)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit clear operation on 16-bit*/
+
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit set address (LAS1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_SET_16b(ADDR,bit)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit set operation on 16-bit */
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_INSERT_16b(ADDR,bit,width)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield insert operation on 16-bit */
+
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_EXTRACT_16b(ADDR,bit,width)        (*(volatile uint16_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield extract operation on 16-bit*/
+#endif
+
+/*! @} End of BME_Utilities                                                   */
+#ifdef __cplusplus
+}
+#endif
+#endif /* __BME_H */
+
+
diff --git a/bsp/nv32f100x/lib/inc/NV32.h b/bsp/nv32f100x/lib/inc/NV32.h
new file mode 100644
index 0000000000..eb16c781c1
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/NV32.h
@@ -0,0 +1,2829 @@
+/*
+ * @brief CMSIS Peripheral Access Layer for NV32
+ *
+ * CMSIS Peripheral Access Layer for NV32
+ */
+
+#if !defined(NV32_H_)
+#define NV32_H_                               /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0004u
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  Reserved16_IRQn              = 0,                /**< Reserved interrupt 16 */
+  Reserved17_IRQn              = 1,                /**< Reserved interrupt 17 */
+  Reserved18_IRQn              = 2,                /**< Reserved interrupt 18 */
+  Reserved19_IRQn              = 3,                /**< Reserved interrupt 19 */
+  Reserved20_IRQn              = 4,                /**< Reserved interrupt 20 */
+  ETMRH_IRQn                   = 5,                /**< ETMRH command complete/read collision interrupt */
+  LVD_LVW_IRQn                 = 6,                /**< Low Voltage Detect, Low Voltage Warning */
+  IRQ_IRQn                     = 7,                /**< External interrupt */
+  I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
+  Reserved25_IRQn              = 9,                /**< Reserved interrupt 25 */
+  SPI0_IRQn                    = 10,               /**< SPI0 interrupt */
+  SPI1_IRQn                    = 11,               /**< SPI1 interrupt */
+  UART0_IRQn                   = 12,               /**< UART0 status/error interrupt */
+  UART1_IRQn                   = 13,               /**< UART1 status/error interrupt */
+  UART2_IRQn                   = 14,               /**< UART2 status/error interrupt */
+  ADC0_IRQn                    = 15,               /**< ADC0 interrupt */
+  ACMP0_IRQn                   = 16,               /**< ACMP0 interrupt */
+  ETM0_IRQn                    = 17,               /**< ETM0 Single interrupt vector for all sources */
+  ETM1_IRQn                    = 18,               /**< ETM1 Single interrupt vector for all sources */
+  ETM2_IRQn                    = 19,               /**< ETM2 Single interrupt vector for all sources */
+  RTC_IRQn                     = 20,               /**< RTC overflow */
+  ACMP1_IRQn                   = 21,               /**< ACMP1 interrupt */
+  PIT_CH0_IRQn                 = 22,               /**< PIT CH0 overflow */
+  PIT_CH1_IRQn                 = 23,               /**< PIT CH1 overflow */
+  KBI0_IRQn                    = 24,               /**< Keyboard interrupt 0 */
+  KBI1_IRQn                    = 25,               /**< Keyboard interrupt 1 */
+  Reserved42_IRQn              = 26,               /**< Reserved interrupt 42 */
+  ICS_IRQn                     = 27,               /**< ICS interrupt */
+  Watchdog_IRQn                = 28,               /**< WDOG Interrupt */
+  Reserved45_IRQn              = 29,               /**< Reserved interrupt 45 */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt 46 */
+  Reserved47_IRQn              = 31                /**< Reserved interrupt 47 */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M0 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT                 1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
+//#include "system_nv32.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ACMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACMP_Peripheral_Access_Layer ACMP Peripheral Access Layer
+ * @{
+ */
+
+/** ACMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CS;                                 /**< ACMP Control and Status Register, offset: 0x0 */
+  __IO uint8_t C0;                                 /**< ACMP Control Register 0, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< ACMP Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< ACMP Control Register 2, offset: 0x3 */
+} ACMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ACMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACMP_Register_Masks ACMP Register Masks
+ * @{
+ */
+
+/* CS Bit Fields */
+#define ACMP_CS_ACMOD_MASK                       0x3u
+#define ACMP_CS_ACMOD_SHIFT                      0
+#define ACMP_CS_ACMOD(x)                         (((uint8_t)(((uint8_t)(x))<<ACMP_CS_ACMOD_SHIFT))&ACMP_CS_ACMOD_MASK)
+#define ACMP_CS_ACOPE_MASK                       0x4u
+#define ACMP_CS_ACOPE_SHIFT                      2
+#define ACMP_CS_ACO_MASK                         0x8u
+#define ACMP_CS_ACO_SHIFT                        3
+#define ACMP_CS_ACIE_MASK                        0x10u
+#define ACMP_CS_ACIE_SHIFT                       4
+#define ACMP_CS_ACF_MASK                         0x20u
+#define ACMP_CS_ACF_SHIFT                        5
+#define ACMP_CS_HYST_MASK                        0x40u
+#define ACMP_CS_HYST_SHIFT                       6
+#define ACMP_CS_ACE_MASK                         0x80u
+#define ACMP_CS_ACE_SHIFT                        7
+/* C0 Bit Fields */
+#define ACMP_C0_ACNSEL_MASK                      0x3u
+#define ACMP_C0_ACNSEL_SHIFT                     0
+#define ACMP_C0_ACNSEL(x)                        (((uint8_t)(((uint8_t)(x))<<ACMP_C0_ACNSEL_SHIFT))&ACMP_C0_ACNSEL_MASK)
+#define ACMP_C0_ACPSEL_MASK                      0x30u
+#define ACMP_C0_ACPSEL_SHIFT                     4
+#define ACMP_C0_ACPSEL(x)                        (((uint8_t)(((uint8_t)(x))<<ACMP_C0_ACPSEL_SHIFT))&ACMP_C0_ACPSEL_MASK)
+/* C1 Bit Fields */
+#define ACMP_C1_DACVAL_MASK                      0x3Fu
+#define ACMP_C1_DACVAL_SHIFT                     0
+#define ACMP_C1_DACVAL(x)                        (((uint8_t)(((uint8_t)(x))<<ACMP_C1_DACVAL_SHIFT))&ACMP_C1_DACVAL_MASK)
+#define ACMP_C1_DACREF_MASK                      0x40u
+#define ACMP_C1_DACREF_SHIFT                     6
+#define ACMP_C1_DACEN_MASK                       0x80u
+#define ACMP_C1_DACEN_SHIFT                      7
+/* C2 Bit Fields */
+#define ACMP_C2_ACIPE_MASK                       0x7u
+#define ACMP_C2_ACIPE_SHIFT                      0
+#define ACMP_C2_ACIPE(x)                         (((uint8_t)(((uint8_t)(x))<<ACMP_C2_ACIPE_SHIFT))&ACMP_C2_ACIPE_MASK)
+
+/*!
+ * @}
+ */ /* end of group ACMP_Register_Masks */
+
+
+/* ACMP - Peripheral instance base addresses */
+/** Peripheral ACMP0 base address */
+#define ACMP0_BASE                               (0x40073000u)
+/** Peripheral ACMP0 base pointer */
+#define ACMP0                                    ((ACMP_Type *)ACMP0_BASE)
+/** Peripheral ACMP1 base address */
+#define ACMP1_BASE                               (0x40074000u)
+/** Peripheral ACMP1 base pointer */
+#define ACMP1                                    ((ACMP_Type *)ACMP1_BASE)
+/** Array initializer of ACMP peripheral base pointers */
+#define ACMP_BASES                               { ACMP0, ACMP1 }
+
+/*!
+ * @}
+ */ /* end of group ACMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1;                               /**< Status and Control Register 1, offset: 0x0 */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x4 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x8 */
+  __IO uint32_t SC4;                               /**< Status and Control Register 4, offset: 0xC */
+  __I  uint32_t R;                                 /**< Conversion Result Register, offset: 0x10 */
+  __IO uint32_t CV;                                /**< Compare Value Register, offset: 0x14 */
+  __IO uint32_t APCTL1;                            /**< Pin Control 1 Register, offset: 0x18 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_ADCO_MASK                        0x20u
+#define ADC_SC1_ADCO_SHIFT                       5
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_FFULL_MASK                       0x4u
+#define ADC_SC2_FFULL_SHIFT                      2
+#define ADC_SC2_FEMPTY_MASK                      0x8u
+#define ADC_SC2_FEMPTY_SHIFT                     3
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+/* SC3 Bit Fields */
+#define ADC_SC3_ADICLK_MASK                      0x3u
+#define ADC_SC3_ADICLK_SHIFT                     0
+#define ADC_SC3_ADICLK(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADICLK_SHIFT))&ADC_SC3_ADICLK_MASK)
+#define ADC_SC3_MODE_MASK                        0xCu
+#define ADC_SC3_MODE_SHIFT                       2
+#define ADC_SC3_MODE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_MODE_SHIFT))&ADC_SC3_MODE_MASK)
+#define ADC_SC3_ADLSMP_MASK                      0x10u
+#define ADC_SC3_ADLSMP_SHIFT                     4
+#define ADC_SC3_ADIV_MASK                        0x60u
+#define ADC_SC3_ADIV_SHIFT                       5
+#define ADC_SC3_ADIV(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADIV_SHIFT))&ADC_SC3_ADIV_MASK)
+#define ADC_SC3_ADLPC_MASK                       0x80u
+#define ADC_SC3_ADLPC_SHIFT                      7
+/* SC4 Bit Fields */
+#define ADC_SC4_AFDEP_MASK                       0x7u
+#define ADC_SC4_AFDEP_SHIFT                      0
+#define ADC_SC4_AFDEP(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC4_AFDEP_SHIFT))&ADC_SC4_AFDEP_MASK)
+#define ADC_SC4_ACFSEL_MASK                      0x20u
+#define ADC_SC4_ACFSEL_SHIFT                     5
+#define ADC_SC4_ASCANE_MASK                      0x40u
+#define ADC_SC4_ASCANE_SHIFT                     6
+/* R Bit Fields */
+#define ADC_R_ADR_MASK                           0xFFFu
+#define ADC_R_ADR_SHIFT                          0
+#define ADC_R_ADR(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_R_ADR_SHIFT))&ADC_R_ADR_MASK)
+/* CV Bit Fields */
+#define ADC_CV_CV_MASK                           0xFFFu
+#define ADC_CV_CV_SHIFT                          0
+#define ADC_CV_CV(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV_SHIFT))&ADC_CV_CV_MASK)
+/* APCTL1 Bit Fields */
+#define ADC_APCTL1_ADPC_MASK                     0xFFFFFFFFu
+#define ADC_APCTL1_ADPC_SHIFT                    0
+#define ADC_APCTL1_ADPC(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_APCTL1_ADPC_SHIFT))&ADC_APCTL1_ADPC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC base address */
+#define ADC_BASE                                 (0x4003B000u)
+/** Peripheral ADC base pointer */
+#define ADC                                      ((ADC_Type *)ADC_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES                                { ADC }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASES                                { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+  __IO uint32_t PIDR;                              /**< Port Input Disable Register, offset: 0x18 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK                      0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT                     0
+#define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK                     0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT                    0
+#define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK                     0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT                    0
+#define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK                     0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT                    0
+#define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK                      0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT                     0
+#define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK                      0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT                     0
+#define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+/* PIDR Bit Fields */
+#define FGPIO_PIDR_PID_MASK                      0xFFFFFFFFu
+#define FGPIO_PIDR_PID_SHIFT                     0
+#define FGPIO_PIDR_PID(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PIDR_PID_SHIFT))&FGPIO_PIDR_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FGPIOA base address */
+#define FGPIOA_BASE                              (0xF8000000u)
+/** Peripheral FGPIOA base pointer */
+#define FGPIOA                                   ((FGPIO_Type *)FGPIOA_BASE)
+/** Peripheral FGPIOB base address */
+#define FGPIOB_BASE                              (0xF8000040u)
+/** Peripheral FGPIOB base pointer */
+#define FGPIOB                                   ((FGPIO_Type *)FGPIOB_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES                              { FGPIOA, FGPIOB }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ETM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETM_Peripheral_Access_Layer ETM Peripheral Access Layer
+ * @{
+ */
+
+/** ETM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[6];
+       uint8_t RESERVED_0[16];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __I  uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADETME;                          /**< DeadETMe Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< ETM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< ETM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< ETM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< ETM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< ETM PWM Load, offset: 0x98 */
+} ETM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ETM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETM_Register_Masks ETM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define ETM_SC_PS_MASK                           0x7u
+#define ETM_SC_PS_SHIFT                          0
+#define ETM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<ETM_SC_PS_SHIFT))&ETM_SC_PS_MASK)
+#define ETM_SC_CLKS_MASK                         0x18u
+#define ETM_SC_CLKS_SHIFT                        3
+#define ETM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<ETM_SC_CLKS_SHIFT))&ETM_SC_CLKS_MASK)
+#define ETM_SC_CPWMS_MASK                        0x20u
+#define ETM_SC_CPWMS_SHIFT                       5
+#define ETM_SC_TOIE_MASK                         0x40u
+#define ETM_SC_TOIE_SHIFT                        6
+#define ETM_SC_TOF_MASK                          0x80u
+#define ETM_SC_TOF_SHIFT                         7
+/* CNT Bit Fields */
+#define ETM_CNT_COUNT_MASK                       0xFFFFu
+#define ETM_CNT_COUNT_SHIFT                      0
+#define ETM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<ETM_CNT_COUNT_SHIFT))&ETM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define ETM_MOD_MOD_MASK                         0xFFFFu
+#define ETM_MOD_MOD_SHIFT                        0
+#define ETM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<ETM_MOD_MOD_SHIFT))&ETM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define ETM_CnSC_ELSA_MASK                       0x4u
+#define ETM_CnSC_ELSA_SHIFT                      2
+#define ETM_CnSC_ELSB_MASK                       0x8u
+#define ETM_CnSC_ELSB_SHIFT                      3
+#define ETM_CnSC_MSA_MASK                        0x10u
+#define ETM_CnSC_MSA_SHIFT                       4
+#define ETM_CnSC_MSB_MASK                        0x20u
+#define ETM_CnSC_MSB_SHIFT                       5
+#define ETM_CnSC_CHIE_MASK                       0x40u
+#define ETM_CnSC_CHIE_SHIFT                      6
+#define ETM_CnSC_CHF_MASK                        0x80u
+#define ETM_CnSC_CHF_SHIFT                       7
+/* CnV Bit Fields */
+#define ETM_CnV_VAL_MASK                         0xFFFFu
+#define ETM_CnV_VAL_SHIFT                        0
+#define ETM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<ETM_CnV_VAL_SHIFT))&ETM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define ETM_CNTIN_INIT_MASK                      0xFFFFu
+#define ETM_CNTIN_INIT_SHIFT                     0
+#define ETM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<ETM_CNTIN_INIT_SHIFT))&ETM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define ETM_STATUS_CH0F_MASK                     0x1u
+#define ETM_STATUS_CH0F_SHIFT                    0
+#define ETM_STATUS_CH1F_MASK                     0x2u
+#define ETM_STATUS_CH1F_SHIFT                    1
+#define ETM_STATUS_CH2F_MASK                     0x4u
+#define ETM_STATUS_CH2F_SHIFT                    2
+#define ETM_STATUS_CH3F_MASK                     0x8u
+#define ETM_STATUS_CH3F_SHIFT                    3
+#define ETM_STATUS_CH4F_MASK                     0x10u
+#define ETM_STATUS_CH4F_SHIFT                    4
+#define ETM_STATUS_CH5F_MASK                     0x20u
+#define ETM_STATUS_CH5F_SHIFT                    5
+#define ETM_STATUS_CH6F_MASK                     0x40u
+#define ETM_STATUS_CH6F_SHIFT                    6
+#define ETM_STATUS_CH7F_MASK                     0x80u
+#define ETM_STATUS_CH7F_SHIFT                    7
+/* MODE Bit Fields */
+#define ETM_MODE_ETMEN_MASK                      0x1u
+#define ETM_MODE_ETMEN_SHIFT                     0
+#define ETM_MODE_INIT_MASK                       0x2u
+#define ETM_MODE_INIT_SHIFT                      1
+#define ETM_MODE_WPDIS_MASK                      0x4u
+#define ETM_MODE_WPDIS_SHIFT                     2
+#define ETM_MODE_PWMSYNC_MASK                    0x8u
+#define ETM_MODE_PWMSYNC_SHIFT                   3
+#define ETM_MODE_CAPTEST_MASK                    0x10u
+#define ETM_MODE_CAPTEST_SHIFT                   4
+#define ETM_MODE_FAULTM_MASK                     0x60u
+#define ETM_MODE_FAULTM_SHIFT                    5
+#define ETM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<ETM_MODE_FAULTM_SHIFT))&ETM_MODE_FAULTM_MASK)
+#define ETM_MODE_FAULTIE_MASK                    0x80u
+#define ETM_MODE_FAULTIE_SHIFT                   7
+/* SYNC Bit Fields */
+#define ETM_SYNC_CNTMIN_MASK                     0x1u
+#define ETM_SYNC_CNTMIN_SHIFT                    0
+#define ETM_SYNC_CNTMAX_MASK                     0x2u
+#define ETM_SYNC_CNTMAX_SHIFT                    1
+#define ETM_SYNC_REINIT_MASK                     0x4u
+#define ETM_SYNC_REINIT_SHIFT                    2
+#define ETM_SYNC_SYNCHOM_MASK                    0x8u
+#define ETM_SYNC_SYNCHOM_SHIFT                   3
+#define ETM_SYNC_TRIG0_MASK                      0x10u
+#define ETM_SYNC_TRIG0_SHIFT                     4
+#define ETM_SYNC_TRIG1_MASK                      0x20u
+#define ETM_SYNC_TRIG1_SHIFT                     5
+#define ETM_SYNC_TRIG2_MASK                      0x40u
+#define ETM_SYNC_TRIG2_SHIFT                     6
+#define ETM_SYNC_SWSYNC_MASK                     0x80u
+#define ETM_SYNC_SWSYNC_SHIFT                    7
+/* OUTINIT Bit Fields */
+#define ETM_OUTINIT_CH0OI_MASK                   0x1u
+#define ETM_OUTINIT_CH0OI_SHIFT                  0
+#define ETM_OUTINIT_CH1OI_MASK                   0x2u
+#define ETM_OUTINIT_CH1OI_SHIFT                  1
+#define ETM_OUTINIT_CH2OI_MASK                   0x4u
+#define ETM_OUTINIT_CH2OI_SHIFT                  2
+#define ETM_OUTINIT_CH3OI_MASK                   0x8u
+#define ETM_OUTINIT_CH3OI_SHIFT                  3
+#define ETM_OUTINIT_CH4OI_MASK                   0x10u
+#define ETM_OUTINIT_CH4OI_SHIFT                  4
+#define ETM_OUTINIT_CH5OI_MASK                   0x20u
+#define ETM_OUTINIT_CH5OI_SHIFT                  5
+#define ETM_OUTINIT_CH6OI_MASK                   0x40u
+#define ETM_OUTINIT_CH6OI_SHIFT                  6
+#define ETM_OUTINIT_CH7OI_MASK                   0x80u
+#define ETM_OUTINIT_CH7OI_SHIFT                  7
+/* OUTMASK Bit Fields */
+#define ETM_OUTMASK_CH0OM_MASK                   0x1u
+#define ETM_OUTMASK_CH0OM_SHIFT                  0
+#define ETM_OUTMASK_CH1OM_MASK                   0x2u
+#define ETM_OUTMASK_CH1OM_SHIFT                  1
+#define ETM_OUTMASK_CH2OM_MASK                   0x4u
+#define ETM_OUTMASK_CH2OM_SHIFT                  2
+#define ETM_OUTMASK_CH3OM_MASK                   0x8u
+#define ETM_OUTMASK_CH3OM_SHIFT                  3
+#define ETM_OUTMASK_CH4OM_MASK                   0x10u
+#define ETM_OUTMASK_CH4OM_SHIFT                  4
+#define ETM_OUTMASK_CH5OM_MASK                   0x20u
+#define ETM_OUTMASK_CH5OM_SHIFT                  5
+#define ETM_OUTMASK_CH6OM_MASK                   0x40u
+#define ETM_OUTMASK_CH6OM_SHIFT                  6
+#define ETM_OUTMASK_CH7OM_MASK                   0x80u
+#define ETM_OUTMASK_CH7OM_SHIFT                  7
+/* COMBINE Bit Fields */
+#define ETM_COMBINE_COMBINE0_MASK                0x1u
+#define ETM_COMBINE_COMBINE0_SHIFT               0
+#define ETM_COMBINE_COMP0_MASK                   0x2u
+#define ETM_COMBINE_COMP0_SHIFT                  1
+#define ETM_COMBINE_DECAPEN0_MASK                0x4u
+#define ETM_COMBINE_DECAPEN0_SHIFT               2
+#define ETM_COMBINE_DECAP0_MASK                  0x8u
+#define ETM_COMBINE_DECAP0_SHIFT                 3
+#define ETM_COMBINE_DTEN0_MASK                   0x10u
+#define ETM_COMBINE_DTEN0_SHIFT                  4
+#define ETM_COMBINE_SYNCEN0_MASK                 0x20u
+#define ETM_COMBINE_SYNCEN0_SHIFT                5
+#define ETM_COMBINE_FAULTEN0_MASK                0x40u
+#define ETM_COMBINE_FAULTEN0_SHIFT               6
+#define ETM_COMBINE_COMBINE1_MASK                0x100u
+#define ETM_COMBINE_COMBINE1_SHIFT               8
+#define ETM_COMBINE_COMP1_MASK                   0x200u
+#define ETM_COMBINE_COMP1_SHIFT                  9
+#define ETM_COMBINE_DECAPEN1_MASK                0x400u
+#define ETM_COMBINE_DECAPEN1_SHIFT               10
+#define ETM_COMBINE_DECAP1_MASK                  0x800u
+#define ETM_COMBINE_DECAP1_SHIFT                 11
+#define ETM_COMBINE_DTEN1_MASK                   0x1000u
+#define ETM_COMBINE_DTEN1_SHIFT                  12
+#define ETM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define ETM_COMBINE_SYNCEN1_SHIFT                13
+#define ETM_COMBINE_FAULTEN1_MASK                0x4000u
+#define ETM_COMBINE_FAULTEN1_SHIFT               14
+#define ETM_COMBINE_COMBINE2_MASK                0x10000u
+#define ETM_COMBINE_COMBINE2_SHIFT               16
+#define ETM_COMBINE_COMP2_MASK                   0x20000u
+#define ETM_COMBINE_COMP2_SHIFT                  17
+#define ETM_COMBINE_DECAPEN2_MASK                0x40000u
+#define ETM_COMBINE_DECAPEN2_SHIFT               18
+#define ETM_COMBINE_DECAP2_MASK                  0x80000u
+#define ETM_COMBINE_DECAP2_SHIFT                 19
+#define ETM_COMBINE_DTEN2_MASK                   0x100000u
+#define ETM_COMBINE_DTEN2_SHIFT                  20
+#define ETM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define ETM_COMBINE_SYNCEN2_SHIFT                21
+#define ETM_COMBINE_FAULTEN2_MASK                0x400000u
+#define ETM_COMBINE_FAULTEN2_SHIFT               22
+#define ETM_COMBINE_COMBINE3_MASK                0x1000000u
+#define ETM_COMBINE_COMBINE3_SHIFT               24
+#define ETM_COMBINE_COMP3_MASK                   0x2000000u
+#define ETM_COMBINE_COMP3_SHIFT                  25
+#define ETM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define ETM_COMBINE_DECAPEN3_SHIFT               26
+#define ETM_COMBINE_DECAP3_MASK                  0x8000000u
+#define ETM_COMBINE_DECAP3_SHIFT                 27
+#define ETM_COMBINE_DTEN3_MASK                   0x10000000u
+#define ETM_COMBINE_DTEN3_SHIFT                  28
+#define ETM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define ETM_COMBINE_SYNCEN3_SHIFT                29
+#define ETM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define ETM_COMBINE_FAULTEN3_SHIFT               30
+/* DEADETME Bit Fields */
+#define ETM_DEADETME_DTVAL_MASK                  0x3Fu
+#define ETM_DEADETME_DTVAL_SHIFT                 0
+#define ETM_DEADETME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_DEADETME_DTVAL_SHIFT))&ETM_DEADETME_DTVAL_MASK)
+#define ETM_DEADETME_DTPS_MASK                   0xC0u
+#define ETM_DEADETME_DTPS_SHIFT                  6
+#define ETM_DEADETME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<ETM_DEADETME_DTPS_SHIFT))&ETM_DEADETME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define ETM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define ETM_EXTTRIG_CH2TRIG_SHIFT                0
+#define ETM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define ETM_EXTTRIG_CH3TRIG_SHIFT                1
+#define ETM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define ETM_EXTTRIG_CH4TRIG_SHIFT                2
+#define ETM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define ETM_EXTTRIG_CH5TRIG_SHIFT                3
+#define ETM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define ETM_EXTTRIG_CH0TRIG_SHIFT                4
+#define ETM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define ETM_EXTTRIG_CH1TRIG_SHIFT                5
+#define ETM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define ETM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define ETM_EXTTRIG_TRIGF_MASK                   0x80u
+#define ETM_EXTTRIG_TRIGF_SHIFT                  7
+/* POL Bit Fields */
+#define ETM_POL_POL0_MASK                        0x1u
+#define ETM_POL_POL0_SHIFT                       0
+#define ETM_POL_POL1_MASK                        0x2u
+#define ETM_POL_POL1_SHIFT                       1
+#define ETM_POL_POL2_MASK                        0x4u
+#define ETM_POL_POL2_SHIFT                       2
+#define ETM_POL_POL3_MASK                        0x8u
+#define ETM_POL_POL3_SHIFT                       3
+#define ETM_POL_POL4_MASK                        0x10u
+#define ETM_POL_POL4_SHIFT                       4
+#define ETM_POL_POL5_MASK                        0x20u
+#define ETM_POL_POL5_SHIFT                       5
+#define ETM_POL_POL6_MASK                        0x40u
+#define ETM_POL_POL6_SHIFT                       6
+#define ETM_POL_POL7_MASK                        0x80u
+#define ETM_POL_POL7_SHIFT                       7
+/* FMS Bit Fields */
+#define ETM_FMS_FAULTF0_MASK                     0x1u
+#define ETM_FMS_FAULTF0_SHIFT                    0
+#define ETM_FMS_FAULTF1_MASK                     0x2u
+#define ETM_FMS_FAULTF1_SHIFT                    1
+#define ETM_FMS_FAULTF2_MASK                     0x4u
+#define ETM_FMS_FAULTF2_SHIFT                    2
+#define ETM_FMS_FAULTF3_MASK                     0x8u
+#define ETM_FMS_FAULTF3_SHIFT                    3
+#define ETM_FMS_FAULTIN_MASK                     0x20u
+#define ETM_FMS_FAULTIN_SHIFT                    5
+#define ETM_FMS_WPEN_MASK                        0x40u
+#define ETM_FMS_WPEN_SHIFT                       6
+#define ETM_FMS_FAULTF_MASK                      0x80u
+#define ETM_FMS_FAULTF_SHIFT                     7
+/* FILTER Bit Fields */
+#define ETM_FILTER_CH0FVAL_MASK                  0xFu
+#define ETM_FILTER_CH0FVAL_SHIFT                 0
+#define ETM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_FILTER_CH0FVAL_SHIFT))&ETM_FILTER_CH0FVAL_MASK)
+#define ETM_FILTER_CH1FVAL_MASK                  0xF0u
+#define ETM_FILTER_CH1FVAL_SHIFT                 4
+#define ETM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_FILTER_CH1FVAL_SHIFT))&ETM_FILTER_CH1FVAL_MASK)
+#define ETM_FILTER_CH2FVAL_MASK                  0xF00u
+#define ETM_FILTER_CH2FVAL_SHIFT                 8
+#define ETM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_FILTER_CH2FVAL_SHIFT))&ETM_FILTER_CH2FVAL_MASK)
+#define ETM_FILTER_CH3FVAL_MASK                  0xF000u
+#define ETM_FILTER_CH3FVAL_SHIFT                 12
+#define ETM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_FILTER_CH3FVAL_SHIFT))&ETM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define ETM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define ETM_FLTCTRL_FAULT0EN_SHIFT               0
+#define ETM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define ETM_FLTCTRL_FAULT1EN_SHIFT               1
+#define ETM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define ETM_FLTCTRL_FAULT2EN_SHIFT               2
+#define ETM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define ETM_FLTCTRL_FAULT3EN_SHIFT               3
+#define ETM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define ETM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define ETM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define ETM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define ETM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define ETM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define ETM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define ETM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define ETM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define ETM_FLTCTRL_FFVAL_SHIFT                  8
+#define ETM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<ETM_FLTCTRL_FFVAL_SHIFT))&ETM_FLTCTRL_FFVAL_MASK)
+/* CONF Bit Fields */
+#define ETM_CONF_NUMTOF_MASK                     0x1Fu
+#define ETM_CONF_NUMTOF_SHIFT                    0
+#define ETM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<ETM_CONF_NUMTOF_SHIFT))&ETM_CONF_NUMTOF_MASK)
+#define ETM_CONF_BDMMODE_MASK                    0xC0u
+#define ETM_CONF_BDMMODE_SHIFT                   6
+#define ETM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<ETM_CONF_BDMMODE_SHIFT))&ETM_CONF_BDMMODE_MASK)
+#define ETM_CONF_GTBEEN_MASK                     0x200u
+#define ETM_CONF_GTBEEN_SHIFT                    9
+#define ETM_CONF_GTBEOUT_MASK                    0x400u
+#define ETM_CONF_GTBEOUT_SHIFT                   10
+/* FLTPOL Bit Fields */
+#define ETM_FLTPOL_FLT0POL_MASK                  0x1u
+#define ETM_FLTPOL_FLT0POL_SHIFT                 0
+#define ETM_FLTPOL_FLT1POL_MASK                  0x2u
+#define ETM_FLTPOL_FLT1POL_SHIFT                 1
+#define ETM_FLTPOL_FLT2POL_MASK                  0x4u
+#define ETM_FLTPOL_FLT2POL_SHIFT                 2
+#define ETM_FLTPOL_FLT3POL_MASK                  0x8u
+#define ETM_FLTPOL_FLT3POL_SHIFT                 3
+/* SYNCONF Bit Fields */
+#define ETM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define ETM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define ETM_SYNCONF_CNTINC_MASK                  0x4u
+#define ETM_SYNCONF_CNTINC_SHIFT                 2
+#define ETM_SYNCONF_INVC_MASK                    0x10u
+#define ETM_SYNCONF_INVC_SHIFT                   4
+#define ETM_SYNCONF_SWOC_MASK                    0x20u
+#define ETM_SYNCONF_SWOC_SHIFT                   5
+#define ETM_SYNCONF_SYNCMODE_MASK                0x80u
+#define ETM_SYNCONF_SYNCMODE_SHIFT               7
+#define ETM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define ETM_SYNCONF_SWRSTCNT_SHIFT               8
+#define ETM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define ETM_SYNCONF_SWWRBUF_SHIFT                9
+#define ETM_SYNCONF_SWOM_MASK                    0x400u
+#define ETM_SYNCONF_SWOM_SHIFT                   10
+#define ETM_SYNCONF_SWINVC_MASK                  0x800u
+#define ETM_SYNCONF_SWINVC_SHIFT                 11
+#define ETM_SYNCONF_SWSOC_MASK                   0x1000u
+#define ETM_SYNCONF_SWSOC_SHIFT                  12
+#define ETM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define ETM_SYNCONF_HWRSTCNT_SHIFT               16
+#define ETM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define ETM_SYNCONF_HWWRBUF_SHIFT                17
+#define ETM_SYNCONF_HWOM_MASK                    0x40000u
+#define ETM_SYNCONF_HWOM_SHIFT                   18
+#define ETM_SYNCONF_HWINVC_MASK                  0x80000u
+#define ETM_SYNCONF_HWINVC_SHIFT                 19
+#define ETM_SYNCONF_HWSOC_MASK                   0x100000u
+#define ETM_SYNCONF_HWSOC_SHIFT                  20
+/* INVCTRL Bit Fields */
+#define ETM_INVCTRL_INV0EN_MASK                  0x1u
+#define ETM_INVCTRL_INV0EN_SHIFT                 0
+#define ETM_INVCTRL_INV1EN_MASK                  0x2u
+#define ETM_INVCTRL_INV1EN_SHIFT                 1
+#define ETM_INVCTRL_INV2EN_MASK                  0x4u
+#define ETM_INVCTRL_INV2EN_SHIFT                 2
+#define ETM_INVCTRL_INV3EN_MASK                  0x8u
+#define ETM_INVCTRL_INV3EN_SHIFT                 3
+/* SWOCTRL Bit Fields */
+#define ETM_SWOCTRL_CH0OC_MASK                   0x1u
+#define ETM_SWOCTRL_CH0OC_SHIFT                  0
+#define ETM_SWOCTRL_CH1OC_MASK                   0x2u
+#define ETM_SWOCTRL_CH1OC_SHIFT                  1
+#define ETM_SWOCTRL_CH2OC_MASK                   0x4u
+#define ETM_SWOCTRL_CH2OC_SHIFT                  2
+#define ETM_SWOCTRL_CH3OC_MASK                   0x8u
+#define ETM_SWOCTRL_CH3OC_SHIFT                  3
+#define ETM_SWOCTRL_CH4OC_MASK                   0x10u
+#define ETM_SWOCTRL_CH4OC_SHIFT                  4
+#define ETM_SWOCTRL_CH5OC_MASK                   0x20u
+#define ETM_SWOCTRL_CH5OC_SHIFT                  5
+#define ETM_SWOCTRL_CH6OC_MASK                   0x40u
+#define ETM_SWOCTRL_CH6OC_SHIFT                  6
+#define ETM_SWOCTRL_CH7OC_MASK                   0x80u
+#define ETM_SWOCTRL_CH7OC_SHIFT                  7
+#define ETM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define ETM_SWOCTRL_CH0OCV_SHIFT                 8
+#define ETM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define ETM_SWOCTRL_CH1OCV_SHIFT                 9
+#define ETM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define ETM_SWOCTRL_CH2OCV_SHIFT                 10
+#define ETM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define ETM_SWOCTRL_CH3OCV_SHIFT                 11
+#define ETM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define ETM_SWOCTRL_CH4OCV_SHIFT                 12
+#define ETM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define ETM_SWOCTRL_CH5OCV_SHIFT                 13
+#define ETM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define ETM_SWOCTRL_CH6OCV_SHIFT                 14
+#define ETM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define ETM_SWOCTRL_CH7OCV_SHIFT                 15
+/* PWMLOAD Bit Fields */
+#define ETM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define ETM_PWMLOAD_CH0SEL_SHIFT                 0
+#define ETM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define ETM_PWMLOAD_CH1SEL_SHIFT                 1
+#define ETM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define ETM_PWMLOAD_CH2SEL_SHIFT                 2
+#define ETM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define ETM_PWMLOAD_CH3SEL_SHIFT                 3
+#define ETM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define ETM_PWMLOAD_CH4SEL_SHIFT                 4
+#define ETM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define ETM_PWMLOAD_CH5SEL_SHIFT                 5
+#define ETM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define ETM_PWMLOAD_CH6SEL_SHIFT                 6
+#define ETM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define ETM_PWMLOAD_CH7SEL_SHIFT                 7
+#define ETM_PWMLOAD_LDOK_MASK                    0x200u
+#define ETM_PWMLOAD_LDOK_SHIFT                   9
+
+/*!
+ * @}
+ */ /* end of group ETM_Register_Masks */
+
+
+/* ETM - Peripheral instance base addresses */
+/** Peripheral ETM0 base address */
+#define ETM0_BASE                                (0x40038000u)
+/** Peripheral ETM0 base pointer */
+#define ETM0                                     ((ETM_Type *)ETM0_BASE)
+/** Peripheral ETM1 base address */
+#define ETM1_BASE                                (0x40039000u)
+/** Peripheral ETM1 base pointer */
+#define ETM1                                     ((ETM_Type *)ETM1_BASE)
+/** Peripheral ETM2 base address */
+#define ETM2_BASE                                (0x4003A000u)
+/** Peripheral ETM2 base pointer */
+#define ETM2                                     ((ETM_Type *)ETM2_BASE)
+/** Array initializer of ETM peripheral base pointers */
+#define ETM_BASES                                { ETM0, ETM1, ETM2 }
+
+/*!
+ * @}
+ */ /* end of group ETM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ETMRH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETMRH_Peripheral_Access_Layer ETMRH Peripheral Access Layer
+ * @{
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV
+   ---------------------------------------------------------------------------- */
+typedef struct ETMRA_MemMap {
+  volatile unsigned long EFMCR;
+	volatile unsigned long EFMSEC0;
+	volatile unsigned long EFMSEC1;
+	volatile unsigned long EFMSEC2;
+	volatile unsigned long EFMETM0;
+	volatile unsigned long EFMETM1;
+	volatile unsigned long EFMCMD;
+} *ETMRH_MemMapPtr;
+
+#define EFM_CR_reg(base)    ((base)->EFMCR)
+#define EFM_SEC0_reg(base)  ((base)->EFMSEC0)
+#define EFM_SEC1_reg(base)  ((base)->EFMSEC1)
+#define EFM_SEC2_reg(base)  ((base)->EFMSEC2)   
+#define EFM_ETM0_reg(base)  ((base)->EFMETM0)
+#define EFM_ETM1_reg(base)  ((base)->EFMETM1)
+#define EFM_CMD_reg(base)		((base)->EFMCMD)
+
+/** Peripheral Map **/
+#define ETMRH                           ((ETMRH_MemMapPtr)0x40020000u)
+
+
+#define ETMRH_FCLKDIV_FDIVLD_MASK                0x80u
+#define ETMRH_FSTAT_CCIF_MASK                    0x80u
+#define ETMRH_FSTAT_ACCERR_MASK                  0x20u
+#define ETMRH_FSTAT_FPVIOL_MASK                  0x10u
+#define ETMRH_FSTAT_MGSTAT_MASK                  0x3u
+#define ETMRH_ERROR                              (ETMRH_FSTAT_ACCERR_MASK | ETMRH_FSTAT_FPVIOL_MASK | ETMRH_FSTAT_MGSTAT_MASK)
+#define ETMRH_FCCOB                              *((volatile uint16_t *)(0x0a + 0x40020000))
+
+#define EFMCR      EFM_CR_reg(ETMRH)
+#define EFMSEC0    EFM_SEC0_reg(ETMRH)
+#define EFMSEC1    EFM_SEC1_reg(ETMRH)
+#define EFMSEC2    EFM_SEC2_reg(ETMRH)
+#define EFMETM0    EFM_ETM0_reg(ETMRH)
+#define EFMETM1    EFM_ETM1_reg(ETMRH)
+#define EFMCMD     EFM_CMD_reg(ETMRH)
+
+typedef struct NVR_BKDOOR_MemMap{
+	  volatile unsigned long Custombkd;
+} *NVR_BKDOOR_MemMapPtr;
+
+
+#define Custombkd_reg(base)    ((base)->Custombkd)
+#define NVR_BKDOOR             ((NVR_BKDOOR_MemMapPtr)0x40020038u)
+
+#define Custombkd             Custombkd_reg(NVR_BKDOOR)
+
+/*!
+ * @}
+ */ /* end of group ETMRH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+  __IO uint32_t PIDR;                              /**< Port Input Disable Register, offset: 0x18 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+/* PIDR Bit Fields */
+#define GPIO_PIDR_PID_MASK                       0xFFFFFFFFu
+#define GPIO_PIDR_PID_SHIFT                      0
+#define GPIO_PIDR_PID(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES                               { GPIOA, GPIOB }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low ETMeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low ETMeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0x1Fu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES                                { I2C0 }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ICS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ICS_Peripheral_Access_Layer ICS Peripheral Access Layer
+ * @{
+ */
+
+/** ICS - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< ICS Control Register 1, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< ICS Control Register 2, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< ICS Control Register 3, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< ICS Control Register 4, offset: 0x3 */
+  __IO uint8_t S;                                  /**< ICS Status Register, offset: 0x4 */
+} ICS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ICS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ICS_Register_Masks ICS Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define ICS_C1_IREFSTEN_MASK                     0x1u
+#define ICS_C1_IREFSTEN_SHIFT                    0
+#define ICS_C1_IRCLKEN_MASK                      0x2u
+#define ICS_C1_IRCLKEN_SHIFT                     1
+#define ICS_C1_IREFS_MASK                        0x4u
+#define ICS_C1_IREFS_SHIFT                       2
+#define ICS_C1_RDIV_MASK                         0x38u
+#define ICS_C1_RDIV_SHIFT                        3
+#define ICS_C1_RDIV(x)                           (((uint8_t)(((uint8_t)(x))<<ICS_C1_RDIV_SHIFT))&ICS_C1_RDIV_MASK)
+#define ICS_C1_CLKS_MASK                         0xC0u
+#define ICS_C1_CLKS_SHIFT                        6
+#define ICS_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<ICS_C1_CLKS_SHIFT))&ICS_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define ICS_C2_LP_MASK                           0x10u
+#define ICS_C2_LP_SHIFT                          4
+#define ICS_C2_BDIV_MASK                         0xE0u
+#define ICS_C2_BDIV_SHIFT                        5
+#define ICS_C2_BDIV(x)                           (((uint8_t)(((uint8_t)(x))<<ICS_C2_BDIV_SHIFT))&ICS_C2_BDIV_MASK)
+/* C3 Bit Fields */
+#define ICS_C3_SCTRIM_MASK                       0xFFu
+#define ICS_C3_SCTRIM_SHIFT                      0
+#define ICS_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<ICS_C3_SCTRIM_SHIFT))&ICS_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define ICS_C4_SCFTRIM_MASK                      0x1u
+#define ICS_C4_SCFTRIM_SHIFT                     0
+#define ICS_C4_CME_MASK                          0x20u
+#define ICS_C4_CME_SHIFT                         5
+#define ICS_C4_LOLIE_MASK                        0x80u
+#define ICS_C4_LOLIE_SHIFT                       7
+/* S Bit Fields */
+#define ICS_S_CLKST_MASK                         0xCu
+#define ICS_S_CLKST_SHIFT                        2
+#define ICS_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<ICS_S_CLKST_SHIFT))&ICS_S_CLKST_MASK)
+#define ICS_S_IREFST_MASK                        0x10u
+#define ICS_S_IREFST_SHIFT                       4
+#define ICS_S_LOCK_MASK                          0x40u
+#define ICS_S_LOCK_SHIFT                         6
+#define ICS_S_LOLS_MASK                          0x80u
+#define ICS_S_LOLS_SHIFT                         7
+
+/*!
+ * @}
+ */ /* end of group ICS_Register_Masks */
+
+
+/* ICS - Peripheral instance base addresses */
+/** Peripheral ICS base address */
+#define ICS_BASE                                 (0x40064000u)
+/** Peripheral ICS base pointer */
+#define ICS                                      ((ICS_Type *)ICS_BASE)
+/** Array initializer of ICS peripheral base pointers */
+#define ICS_BASES                                { ICS }
+
+/*!
+ * @}
+ */ /* end of group ICS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- IRQ Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IRQ_Peripheral_Access_Layer IRQ Peripheral Access Layer
+ * @{
+ */
+
+/** IRQ - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t SC;                                 /**< Interrupt Pin Request Status and Control Register, offset: 0x0 */
+} IRQ_Type;
+
+/* ----------------------------------------------------------------------------
+   -- IRQ Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IRQ_Register_Masks IRQ Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define IRQ_SC_IRQMOD_MASK                       0x1u
+#define IRQ_SC_IRQMOD_SHIFT                      0
+#define IRQ_SC_IRQIE_MASK                        0x2u
+#define IRQ_SC_IRQIE_SHIFT                       1
+#define IRQ_SC_IRQACK_MASK                       0x4u
+#define IRQ_SC_IRQACK_SHIFT                      2
+#define IRQ_SC_IRQF_MASK                         0x8u
+#define IRQ_SC_IRQF_SHIFT                        3
+#define IRQ_SC_IRQPE_MASK                        0x10u
+#define IRQ_SC_IRQPE_SHIFT                       4
+#define IRQ_SC_IRQEDG_MASK                       0x20u
+#define IRQ_SC_IRQEDG_SHIFT                      5
+#define IRQ_SC_IRQPDD_MASK                       0x40u
+#define IRQ_SC_IRQPDD_SHIFT                      6
+
+/*!
+ * @}
+ */ /* end of group IRQ_Register_Masks */
+
+
+/* IRQ - Peripheral instance base addresses */
+/** Peripheral IRQ base address */
+#define IRQ_BASE                                 (0x40031000u)
+/** Peripheral IRQ base pointer */
+#define IRQ                                      ((IRQ_Type *)IRQ_BASE)
+/** Array initializer of IRQ peripheral base pointers */
+#define IRQ_BASES                                { IRQ }
+
+/*!
+ * @}
+ */ /* end of group IRQ_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- KBI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup KBI_Peripheral_Access_Layer KBI Peripheral Access Layer
+ * @{
+ */
+
+/** KBI - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t SC;                                 /**< KBI Status and Control Register, offset: 0x0 */
+  __IO uint8_t PE;                                 /**< KBIx Pin Enable Register, offset: 0x1 */
+  __IO uint8_t ES;                                 /**< KBIx Edge Select Register, offset: 0x2 */
+} KBI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- KBI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup KBI_Register_Masks KBI Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define KBI_SC_KBMOD_MASK                        0x1u
+#define KBI_SC_KBMOD_SHIFT                       0
+#define KBI_SC_KBIE_MASK                         0x2u
+#define KBI_SC_KBIE_SHIFT                        1
+#define KBI_SC_KBACK_MASK                        0x4u
+#define KBI_SC_KBACK_SHIFT                       2
+#define KBI_SC_KBF_MASK                          0x8u
+#define KBI_SC_KBF_SHIFT                         3
+/* PE Bit Fields */
+#define KBI_PE_KBIPE_MASK                        0xFFu
+#define KBI_PE_KBIPE_SHIFT                       0
+#define KBI_PE_KBIPE(x)                          (((uint8_t)(((uint8_t)(x))<<KBI_PE_KBIPE_SHIFT))&KBI_PE_KBIPE_MASK)
+/* ES Bit Fields */
+#define KBI_ES_KBEDG_MASK                        0xFFu
+#define KBI_ES_KBEDG_SHIFT                       0
+#define KBI_ES_KBEDG(x)                          (((uint8_t)(((uint8_t)(x))<<KBI_ES_KBEDG_SHIFT))&KBI_ES_KBEDG_MASK)
+
+/*!
+ * @}
+ */ /* end of group KBI_Register_Masks */
+
+
+/* KBI - Peripheral instance base addresses */
+/** Peripheral KBI0 base address */
+#define KBI0_BASE                                (0x40079000u)
+/** Peripheral KBI0 base pointer */
+#define KBI0                                     ((KBI_Type *)KBI0_BASE)
+/** Peripheral KBI1 base address */
+#define KBI1_BASE                                (0x4007A000u)
+/** Peripheral KBI1 base pointer */
+#define KBI1                                     ((KBI_Type *)KBI1_BASE)
+/** Array initializer of KBI peripheral base pointers */
+#define KBI_BASES                                { KBI0, KBI1 }
+
+/*!
+ * @}
+ */ /* end of group KBI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_CFCC_MASK                      0x400u
+#define MCM_PLACR_CFCC_SHIFT                     10
+#define MCM_PLACR_DFCDA_MASK                     0x800u
+#define MCM_PLACR_DFCDA_SHIFT                    11
+#define MCM_PLACR_DFCIC_MASK                     0x1000u
+#define MCM_PLACR_DFCIC_SHIFT                    12
+#define MCM_PLACR_DFCC_MASK                      0x2000u
+#define MCM_PLACR_DFCC_SHIFT                     13
+#define MCM_PLACR_EFDS_MASK                      0x4000u
+#define MCM_PLACR_EFDS_SHIFT                     14
+#define MCM_PLACR_DFCS_MASK                      0x8000u
+#define MCM_PLACR_DFCS_SHIFT                     15
+#define MCM_PLACR_ESFC_MASK                      0x10000u
+#define MCM_PLACR_ESFC_SHIFT                     16
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES                                { MCM }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0, offset: 0x0 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1, offset: 0x1 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2, offset: 0x2 */
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3, offset: 0x3 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4, offset: 0x4 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5, offset: 0x5 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6, offset: 0x6 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7, offset: 0x7 */
+       uint8_t RESERVED_0[4];
+  __I  uint8_t EEPROT;                             /**< Non-volatile E-Flash Protection Register, offset: 0xC */
+  __I  uint8_t FPROT;                              /**< Non-volatile P-Flash Protection Register, offset: 0xD */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xE */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* EEPROT Bit Fields */
+#define NV_EEPROT_DPS_MASK                       0x7u
+#define NV_EEPROT_DPS_SHIFT                      0
+#define NV_EEPROT_DPS(x)                         (((uint8_t)(((uint8_t)(x))<<NV_EEPROT_DPS_SHIFT))&NV_EEPROT_DPS_MASK)
+#define NV_EEPROT_DPOPEN_MASK                    0x80u
+#define NV_EEPROT_DPOPEN_SHIFT                   7
+/* FPROT Bit Fields */
+#define NV_FPROT_FPLS_MASK                       0x3u
+#define NV_FPROT_FPLS_SHIFT                      0
+#define NV_FPROT_FPLS(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FPROT_FPLS_SHIFT))&NV_FPROT_FPLS_MASK)
+#define NV_FPROT_FPLDIS_MASK                     0x4u
+#define NV_FPROT_FPLDIS_SHIFT                    2
+#define NV_FPROT_FPHS_MASK                       0x18u
+#define NV_FPROT_FPHS_SHIFT                      3
+#define NV_FPROT_FPHS(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FPROT_FPHS_SHIFT))&NV_FPROT_FPHS_MASK)
+#define NV_FPROT_FPHDIS_MASK                     0x20u
+#define NV_FPROT_FPHDIS_SHIFT                    5
+#define NV_FPROT_FPOPEN_MASK                     0x80u
+#define NV_FPROT_FPOPEN_SHIFT                    7
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral ETMRH_FlashConfig base address */
+#define ETMRH_FlashConfig_BASE                   (0x400u)
+/** Peripheral ETMRH_FlashConfig base pointer */
+#define ETMRH_FlashConfig                        ((NV_Type *)ETMRH_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES                                 { ETMRH_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_OSCINIT_MASK                      0x1u
+#define OSC_CR_OSCINIT_SHIFT                     0
+#define OSC_CR_HGO_MASK                          0x2u
+#define OSC_CR_HGO_SHIFT                         1
+#define OSC_CR_RANGE_MASK                        0x4u
+#define OSC_CR_RANGE_SHIFT                       2
+#define OSC_CR_OSCOS_MASK                        0x10u
+#define OSC_CR_OSCOS_SHIFT                       4
+#define OSC_CR_OSCSTEN_MASK                      0x20u
+#define OSC_CR_OSCSTEN_SHIFT                     5
+#define OSC_CR_OSCEN_MASK                        0x80u
+#define OSC_CR_OSCEN_SHIFT                       7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES                                { OSC }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< ETMer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current ETMer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< ETMer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< ETMer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES                                { PIT }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t SPMSC1;                             /**< System Power Management Status and Control 1 Register, offset: 0x0 */
+  __IO uint8_t SPMSC2;                             /**< System Power Management Status and Control 2 Register, offset: 0x1 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* SPMSC1 Bit Fields */
+#define PMC_SPMSC1_BGBE_MASK                     0x1u
+#define PMC_SPMSC1_BGBE_SHIFT                    0
+#define PMC_SPMSC1_BGBDS_MASK                    0x2u
+#define PMC_SPMSC1_BGBDS_SHIFT                   1
+#define PMC_SPMSC1_LVDE_MASK                     0x4u
+#define PMC_SPMSC1_LVDE_SHIFT                    2
+#define PMC_SPMSC1_LVDSE_MASK                    0x8u
+#define PMC_SPMSC1_LVDSE_SHIFT                   3
+#define PMC_SPMSC1_LVDRE_MASK                    0x10u
+#define PMC_SPMSC1_LVDRE_SHIFT                   4
+#define PMC_SPMSC1_LVWIE_MASK                    0x20u
+#define PMC_SPMSC1_LVWIE_SHIFT                   5
+#define PMC_SPMSC1_LVWACK_MASK                   0x40u
+#define PMC_SPMSC1_LVWACK_SHIFT                  6
+#define PMC_SPMSC1_LVWF_MASK                     0x80u
+#define PMC_SPMSC1_LVWF_SHIFT                    7
+/* SPMSC2 Bit Fields */
+#define PMC_SPMSC2_LVWV_MASK                     0x30u
+#define PMC_SPMSC2_LVWV_SHIFT                    4
+#define PMC_SPMSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_SPMSC2_LVWV_SHIFT))&PMC_SPMSC2_LVWV_MASK)
+#define PMC_SPMSC2_LVDV_MASK                     0x40u
+#define PMC_SPMSC2_LVDV_SHIFT                    6
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES                                { PMC }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IOFLT;                             /**< Port Filter Register, offset: 0x0 */
+  __IO uint32_t PUEL;                              /**< Port Pullup Enable Low Register, offset: 0x4 */
+  __IO uint32_t PUEH;                              /**< Port Pullup Enable High Register, offset: 0x8 */
+  __IO uint32_t HDRVE;                             /**< Port High Drive Enable Register, offset: 0xC */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* IOFLT Bit Fields */
+#define PORT_IOFLT_FLTA_MASK                     0x3u
+#define PORT_IOFLT_FLTA_SHIFT                    0
+#define PORT_IOFLT_FLTA(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTA_SHIFT))&PORT_IOFLT_FLTA_MASK)
+#define PORT_IOFLT_FLTB_MASK                     0xCu
+#define PORT_IOFLT_FLTB_SHIFT                    2
+#define PORT_IOFLT_FLTB(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTB_SHIFT))&PORT_IOFLT_FLTB_MASK)
+#define PORT_IOFLT_FLTC_MASK                     0x30u
+#define PORT_IOFLT_FLTC_SHIFT                    4
+#define PORT_IOFLT_FLTC(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTC_SHIFT))&PORT_IOFLT_FLTC_MASK)
+#define PORT_IOFLT_FLTD_MASK                     0xC0u
+#define PORT_IOFLT_FLTD_SHIFT                    6
+#define PORT_IOFLT_FLTD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTD_SHIFT))&PORT_IOFLT_FLTD_MASK)
+#define PORT_IOFLT_FLTE_MASK                     0x300u
+#define PORT_IOFLT_FLTE_SHIFT                    8
+#define PORT_IOFLT_FLTE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTE_SHIFT))&PORT_IOFLT_FLTE_MASK)
+#define PORT_IOFLT_FLTF_MASK                     0xC00u
+#define PORT_IOFLT_FLTF_SHIFT                    10
+#define PORT_IOFLT_FLTF(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTF_SHIFT))&PORT_IOFLT_FLTF_MASK)
+#define PORT_IOFLT_FLTG_MASK                     0x3000u
+#define PORT_IOFLT_FLTG_SHIFT                    12
+#define PORT_IOFLT_FLTG(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTG_SHIFT))&PORT_IOFLT_FLTG_MASK)
+#define PORT_IOFLT_FLTH_MASK                     0xC000u
+#define PORT_IOFLT_FLTH_SHIFT                    14
+#define PORT_IOFLT_FLTH(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTH_SHIFT))&PORT_IOFLT_FLTH_MASK)
+#define PORT_IOFLT_FLTRST_MASK                   0x30000u
+#define PORT_IOFLT_FLTRST_SHIFT                  16
+#define PORT_IOFLT_FLTRST(x)                     (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTRST_SHIFT))&PORT_IOFLT_FLTRST_MASK)
+#define PORT_IOFLT_FLTKBI0_MASK                  0xC0000u
+#define PORT_IOFLT_FLTKBI0_SHIFT                 18
+#define PORT_IOFLT_FLTKBI0(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTKBI0_SHIFT))&PORT_IOFLT_FLTKBI0_MASK)
+#define PORT_IOFLT_FLTKBI1_MASK                  0x300000u
+#define PORT_IOFLT_FLTKBI1_SHIFT                 20
+#define PORT_IOFLT_FLTKBI1(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTKBI1_SHIFT))&PORT_IOFLT_FLTKBI1_MASK)
+#define PORT_IOFLT_FLTNMI_MASK                   0xC00000u
+#define PORT_IOFLT_FLTNMI_SHIFT                  22
+#define PORT_IOFLT_FLTNMI(x)                     (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTNMI_SHIFT))&PORT_IOFLT_FLTNMI_MASK)
+#define PORT_IOFLT_FLTDIV1_MASK                  0x3000000u
+#define PORT_IOFLT_FLTDIV1_SHIFT                 24
+#define PORT_IOFLT_FLTDIV1(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTDIV1_SHIFT))&PORT_IOFLT_FLTDIV1_MASK)
+#define PORT_IOFLT_FLTDIV2_MASK                  0x1C000000u
+#define PORT_IOFLT_FLTDIV2_SHIFT                 26
+#define PORT_IOFLT_FLTDIV2(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTDIV2_SHIFT))&PORT_IOFLT_FLTDIV2_MASK)
+#define PORT_IOFLT_FLTDIV3_MASK                  0xE0000000u
+#define PORT_IOFLT_FLTDIV3_SHIFT                 29
+#define PORT_IOFLT_FLTDIV3(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTDIV3_SHIFT))&PORT_IOFLT_FLTDIV3_MASK)
+/* PUEL Bit Fields */
+#define PORT_PUEL_PTAPE0_MASK                    0x1u
+#define PORT_PUEL_PTAPE0_SHIFT                   0
+#define PORT_PUEL_PTAPE1_MASK                    0x2u
+#define PORT_PUEL_PTAPE1_SHIFT                   1
+#define PORT_PUEL_PTAPE2_MASK                    0x4u
+#define PORT_PUEL_PTAPE2_SHIFT                   2
+#define PORT_PUEL_PTAPE3_MASK                    0x8u
+#define PORT_PUEL_PTAPE3_SHIFT                   3
+#define PORT_PUEL_PTAPE4_MASK                    0x10u
+#define PORT_PUEL_PTAPE4_SHIFT                   4
+#define PORT_PUEL_PTAPE5_MASK                    0x20u
+#define PORT_PUEL_PTAPE5_SHIFT                   5
+#define PORT_PUEL_PTAPE6_MASK                    0x40u
+#define PORT_PUEL_PTAPE6_SHIFT                   6
+#define PORT_PUEL_PTAPE7_MASK                    0x80u
+#define PORT_PUEL_PTAPE7_SHIFT                   7
+#define PORT_PUEL_PTBPE0_MASK                    0x100u
+#define PORT_PUEL_PTBPE0_SHIFT                   8
+#define PORT_PUEL_PTBPE1_MASK                    0x200u
+#define PORT_PUEL_PTBPE1_SHIFT                   9
+#define PORT_PUEL_PTBPE2_MASK                    0x400u
+#define PORT_PUEL_PTBPE2_SHIFT                   10
+#define PORT_PUEL_PTBPE3_MASK                    0x800u
+#define PORT_PUEL_PTBPE3_SHIFT                   11
+#define PORT_PUEL_PTBPE4_MASK                    0x1000u
+#define PORT_PUEL_PTBPE4_SHIFT                   12
+#define PORT_PUEL_PTBPE5_MASK                    0x2000u
+#define PORT_PUEL_PTBPE5_SHIFT                   13
+#define PORT_PUEL_PTBPE6_MASK                    0x4000u
+#define PORT_PUEL_PTBPE6_SHIFT                   14
+#define PORT_PUEL_PTBPE7_MASK                    0x8000u
+#define PORT_PUEL_PTBPE7_SHIFT                   15
+#define PORT_PUEL_PTCPE0_MASK                    0x10000u
+#define PORT_PUEL_PTCPE0_SHIFT                   16
+#define PORT_PUEL_PTCPE1_MASK                    0x20000u
+#define PORT_PUEL_PTCPE1_SHIFT                   17
+#define PORT_PUEL_PTCPE2_MASK                    0x40000u
+#define PORT_PUEL_PTCPE2_SHIFT                   18
+#define PORT_PUEL_PTCPE3_MASK                    0x80000u
+#define PORT_PUEL_PTCPE3_SHIFT                   19
+#define PORT_PUEL_PTCPE4_MASK                    0x100000u
+#define PORT_PUEL_PTCPE4_SHIFT                   20
+#define PORT_PUEL_PTCPE5_MASK                    0x200000u
+#define PORT_PUEL_PTCPE5_SHIFT                   21
+#define PORT_PUEL_PTCPE6_MASK                    0x400000u
+#define PORT_PUEL_PTCPE6_SHIFT                   22
+#define PORT_PUEL_PTCPE7_MASK                    0x800000u
+#define PORT_PUEL_PTCPE7_SHIFT                   23
+#define PORT_PUEL_PTDPE0_MASK                    0x1000000u
+#define PORT_PUEL_PTDPE0_SHIFT                   24
+#define PORT_PUEL_PTDPE1_MASK                    0x2000000u
+#define PORT_PUEL_PTDPE1_SHIFT                   25
+#define PORT_PUEL_PTDPE2_MASK                    0x4000000u
+#define PORT_PUEL_PTDPE2_SHIFT                   26
+#define PORT_PUEL_PTDPE3_MASK                    0x8000000u
+#define PORT_PUEL_PTDPE3_SHIFT                   27
+#define PORT_PUEL_PTDPE4_MASK                    0x10000000u
+#define PORT_PUEL_PTDPE4_SHIFT                   28
+#define PORT_PUEL_PTDPE5_MASK                    0x20000000u
+#define PORT_PUEL_PTDPE5_SHIFT                   29
+#define PORT_PUEL_PTDPE6_MASK                    0x40000000u
+#define PORT_PUEL_PTDPE6_SHIFT                   30
+#define PORT_PUEL_PTDPE7_MASK                    0x80000000u
+#define PORT_PUEL_PTDPE7_SHIFT                   31
+/* PUEH Bit Fields */
+#define PORT_PUEH_PTEPE0_MASK                    0x1u
+#define PORT_PUEH_PTEPE0_SHIFT                   0
+#define PORT_PUEH_PTEPE1_MASK                    0x2u
+#define PORT_PUEH_PTEPE1_SHIFT                   1
+#define PORT_PUEH_PTEPE2_MASK                    0x4u
+#define PORT_PUEH_PTEPE2_SHIFT                   2
+#define PORT_PUEH_PTEPE3_MASK                    0x8u
+#define PORT_PUEH_PTEPE3_SHIFT                   3
+#define PORT_PUEH_PTEPE4_MASK                    0x10u
+#define PORT_PUEH_PTEPE4_SHIFT                   4
+#define PORT_PUEH_PTEPE5_MASK                    0x20u
+#define PORT_PUEH_PTEPE5_SHIFT                   5
+#define PORT_PUEH_PTEPE6_MASK                    0x40u
+#define PORT_PUEH_PTEPE6_SHIFT                   6
+#define PORT_PUEH_PTEPE7_MASK                    0x80u
+#define PORT_PUEH_PTEPE7_SHIFT                   7
+#define PORT_PUEH_PTFPE0_MASK                    0x100u
+#define PORT_PUEH_PTFPE0_SHIFT                   8
+#define PORT_PUEH_PTFPE1_MASK                    0x200u
+#define PORT_PUEH_PTFPE1_SHIFT                   9
+#define PORT_PUEH_PTFPE2_MASK                    0x400u
+#define PORT_PUEH_PTFPE2_SHIFT                   10
+#define PORT_PUEH_PTFPE3_MASK                    0x800u
+#define PORT_PUEH_PTFPE3_SHIFT                   11
+#define PORT_PUEH_PTFPE4_MASK                    0x1000u
+#define PORT_PUEH_PTFPE4_SHIFT                   12
+#define PORT_PUEH_PTFPE5_MASK                    0x2000u
+#define PORT_PUEH_PTFPE5_SHIFT                   13
+#define PORT_PUEH_PTFPE6_MASK                    0x4000u
+#define PORT_PUEH_PTFPE6_SHIFT                   14
+#define PORT_PUEH_PTFPE7_MASK                    0x8000u
+#define PORT_PUEH_PTFPE7_SHIFT                   15
+#define PORT_PUEH_PTGPE0_MASK                    0x10000u
+#define PORT_PUEH_PTGPE0_SHIFT                   16
+#define PORT_PUEH_PTGPE1_MASK                    0x20000u
+#define PORT_PUEH_PTGPE1_SHIFT                   17
+#define PORT_PUEH_PTGPE2_MASK                    0x40000u
+#define PORT_PUEH_PTGPE2_SHIFT                   18
+#define PORT_PUEH_PTGPE3_MASK                    0x80000u
+#define PORT_PUEH_PTGPE3_SHIFT                   19
+#define PORT_PUEH_PTHPE0_MASK                    0x1000000u
+#define PORT_PUEH_PTHPE0_SHIFT                   24
+#define PORT_PUEH_PTHPE1_MASK                    0x2000000u
+#define PORT_PUEH_PTHPE1_SHIFT                   25
+#define PORT_PUEH_PTHPE2_MASK                    0x4000000u
+#define PORT_PUEH_PTHPE2_SHIFT                   26
+#define PORT_PUEH_PTHPE6_MASK                    0x40000000u
+#define PORT_PUEH_PTHPE6_SHIFT                   30
+#define PORT_PUEH_PTHPE7_MASK                    0x80000000u
+#define PORT_PUEH_PTHPE7_SHIFT                   31
+/* HDRVE Bit Fields */
+#define PORT_HDRVE_PTB4_MASK                     0x1u
+#define PORT_HDRVE_PTB4_SHIFT                    0
+#define PORT_HDRVE_PTB5_MASK                     0x2u
+#define PORT_HDRVE_PTB5_SHIFT                    1
+#define PORT_HDRVE_PTD0_MASK                     0x4u
+#define PORT_HDRVE_PTD0_SHIFT                    2
+#define PORT_HDRVE_PTD1_MASK                     0x8u
+#define PORT_HDRVE_PTD1_SHIFT                    3
+#define PORT_HDRVE_PTE0_MASK                     0x10u
+#define PORT_HDRVE_PTE0_SHIFT                    4
+#define PORT_HDRVE_PTE1_MASK                     0x20u
+#define PORT_HDRVE_PTE1_SHIFT                    5
+#define PORT_HDRVE_PTH0_MASK                     0x40u
+#define PORT_HDRVE_PTH0_SHIFT                    6
+#define PORT_HDRVE_PTH1_MASK                     0x80u
+#define PORT_HDRVE_PTH1_SHIFT                    7
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORT base address */
+#define PORT_BASE                                (0x40049000u)
+/** Peripheral PORT base pointer */
+#define PORT                                     ((PORT_Type *)PORT_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES                               { PORT }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< RTC Status and Control Register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< RTC Modulo Register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< RTC Counter Register, offset: 0x8 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define RTC_SC_RTCO_MASK                         0x10u
+#define RTC_SC_RTCO_SHIFT                        4
+#define RTC_SC_RTIE_MASK                         0x40u
+#define RTC_SC_RTIE_SHIFT                        6
+#define RTC_SC_RTIF_MASK                         0x80u
+#define RTC_SC_RTIF_SHIFT                        7
+#define RTC_SC_RTCPS_MASK                        0x700u
+#define RTC_SC_RTCPS_SHIFT                       8
+#define RTC_SC_RTCPS(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_SC_RTCPS_SHIFT))&RTC_SC_RTCPS_MASK)
+#define RTC_SC_RTCLKS_MASK                       0xC000u
+#define RTC_SC_RTCLKS_SHIFT                      14
+#define RTC_SC_RTCLKS(x)                         (((uint32_t)(((uint32_t)(x))<<RTC_SC_RTCLKS_SHIFT))&RTC_SC_RTCLKS_MASK)
+/* MOD Bit Fields */
+#define RTC_MOD_MOD_MASK                         0xFFFFu
+#define RTC_MOD_MOD_SHIFT                        0
+#define RTC_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_MOD_MOD_SHIFT))&RTC_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define RTC_CNT_CNT_MASK                         0xFFFFu
+#define RTC_CNT_CNT_SHIFT                        0
+#define RTC_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CNT_CNT_SHIFT))&RTC_CNT_CNT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES                                { RTC }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t SRSID;                             /**< System Reset Status and ID Register, offset: 0x0 */
+  __IO uint32_t SOPT;                              /**< System Options Register, offset: 0x4 */
+  __IO uint32_t PINSEL;                            /**< Pin Selection Register, offset: 0x8 */
+  __IO uint32_t SCGC;                              /**< System Clock Gating Control Register, offset: 0xC */
+  __I  uint32_t UUIDL;                             /**< Universally Unique Identifier Low Register, offset: 0x10 */
+  __I  uint32_t UUIDM; 
+  __I  uint32_t UUIDH;                             /**< Universally Unique Identifier High Register, offset: 0x14 */
+  __IO uint32_t BUSDIV;                            /**< BUS Clock Divider Register, offset: 0x18 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SRSID Bit Fields */
+#define SIM_SRSID_LVD_MASK                       0x2u
+#define SIM_SRSID_LVD_SHIFT                      1
+#define SIM_SRSID_LOC_MASK                       0x4u
+#define SIM_SRSID_LOC_SHIFT                      2
+#define SIM_SRSID_WDOG_MASK                      0x20u
+#define SIM_SRSID_WDOG_SHIFT                     5
+#define SIM_SRSID_PIN_MASK                       0x40u
+#define SIM_SRSID_PIN_SHIFT                      6
+#define SIM_SRSID_POR_MASK                       0x80u
+#define SIM_SRSID_POR_SHIFT                      7
+#define SIM_SRSID_LOCKUP_MASK                    0x200u
+#define SIM_SRSID_LOCKUP_SHIFT                   9
+#define SIM_SRSID_SW_MASK                        0x400u
+#define SIM_SRSID_SW_SHIFT                       10
+#define SIM_SRSID_MDMAP_MASK                     0x800u
+#define SIM_SRSID_MDMAP_SHIFT                    11
+#define SIM_SRSID_SACKERR_MASK                   0x2000u
+#define SIM_SRSID_SACKERR_SHIFT                  13
+#define SIM_SRSID_PINID_MASK                     0xF0000u
+#define SIM_SRSID_PINID_SHIFT                    16
+#define SIM_SRSID_PINID(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SRSID_PINID_SHIFT))&SIM_SRSID_PINID_MASK)
+#define SIM_SRSID_RevID_MASK                     0xF00000u
+#define SIM_SRSID_RevID_SHIFT                    20
+#define SIM_SRSID_RevID(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SRSID_RevID_SHIFT))&SIM_SRSID_RevID_MASK)
+#define SIM_SRSID_SUBFAMID_MASK                  0xF000000u
+#define SIM_SRSID_SUBFAMID_SHIFT                 24
+#define SIM_SRSID_SUBFAMID(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SRSID_SUBFAMID_SHIFT))&SIM_SRSID_SUBFAMID_MASK)
+#define SIM_SRSID_FAMID_MASK                     0xF0000000u
+#define SIM_SRSID_FAMID_SHIFT                    28
+#define SIM_SRSID_FAMID(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SRSID_FAMID_SHIFT))&SIM_SRSID_FAMID_MASK)
+/* SOPT Bit Fields */
+#define SIM_SOPT_NMIE_MASK                       0x2u
+#define SIM_SOPT_NMIE_SHIFT                      1
+#define SIM_SOPT_RSTPE_MASK                      0x4u
+#define SIM_SOPT_RSTPE_SHIFT                     2
+#define SIM_SOPT_SWDE_MASK                       0x8u
+#define SIM_SOPT_SWDE_SHIFT                      3
+#define SIM_SOPT_ADHWT_MASK                      0x300u
+#define SIM_SOPT_ADHWT_SHIFT                     8
+#define SIM_SOPT_ADHWT(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT_ADHWT_SHIFT))&SIM_SOPT_ADHWT_MASK)
+#define SIM_SOPT_RTCC_MASK                       0x400u
+#define SIM_SOPT_RTCC_SHIFT                      10
+#define SIM_SOPT_ACIC_MASK                       0x800u
+#define SIM_SOPT_ACIC_SHIFT                      11
+#define SIM_SOPT_RXDCE_MASK                      0x1000u
+#define SIM_SOPT_RXDCE_SHIFT                     12
+#define SIM_SOPT_RXDFE_MASK                      0x2000u
+#define SIM_SOPT_RXDFE_SHIFT                     13
+#define SIM_SOPT_ETMSYNC_MASK                    0x4000u
+#define SIM_SOPT_ETMSYNC_SHIFT                   14
+#define SIM_SOPT_TXDME_MASK                      0x8000u
+#define SIM_SOPT_TXDME_SHIFT                     15
+#define SIM_SOPT_BUSREF_MASK                     0x70000u
+#define SIM_SOPT_BUSREF_SHIFT                    16
+#define SIM_SOPT_BUSREF(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SOPT_BUSREF_SHIFT))&SIM_SOPT_BUSREF_MASK)
+#define SIM_SOPT_CLKOE_MASK                      0x80000u
+#define SIM_SOPT_CLKOE_SHIFT                     19
+#define SIM_SOPT_DLYACT_MASK                     0x800000u
+#define SIM_SOPT_DLYACT_SHIFT                    23
+#define SIM_SOPT_DELAY_MASK                      0xFF000000u
+#define SIM_SOPT_DELAY_SHIFT                     24
+#define SIM_SOPT_DELAY(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT_DELAY_SHIFT))&SIM_SOPT_DELAY_MASK)
+/* PINSEL Bit Fields */
+#define SIM_PINSEL_RTCPS_MASK                    0x10u
+#define SIM_PINSEL_RTCPS_SHIFT                   4
+#define SIM_PINSEL_IICPS_MASK                    0x20u
+#define SIM_PINSEL_IICPS_SHIFT                   5
+#define SIM_PINSEL_SPI0PS_MASK                   0x40u
+#define SIM_PINSEL_SPI0PS_SHIFT                  6
+#define SIM_PINSEL_UART0PS_MASK                  0x80u
+#define SIM_PINSEL_UART0PS_SHIFT                 7
+#define SIM_PINSEL_ETM0PS0_MASK                  0x100u
+#define SIM_PINSEL_ETM0PS0_SHIFT                 8
+#define SIM_PINSEL_ETM0PS1_MASK                  0x200u
+#define SIM_PINSEL_ETM0PS1_SHIFT                 9
+#define SIM_PINSEL_ETM1PS0_MASK                  0x400u
+#define SIM_PINSEL_ETM1PS0_SHIFT                 10
+#define SIM_PINSEL_ETM1PS1_MASK                  0x800u
+#define SIM_PINSEL_ETM1PS1_SHIFT                 11
+#define SIM_PINSEL_ETM2PS0_MASK                  0x1000u
+#define SIM_PINSEL_ETM2PS0_SHIFT                 12
+#define SIM_PINSEL_ETM2PS1_MASK                  0x2000u
+#define SIM_PINSEL_ETM2PS1_SHIFT                 13
+#define SIM_PINSEL_ETM2PS2_MASK                  0x4000u
+#define SIM_PINSEL_ETM2PS2_SHIFT                 14
+#define SIM_PINSEL_ETM2PS3_MASK                  0x8000u
+#define SIM_PINSEL_ETM2PS3_SHIFT                 15
+/* SCGC Bit Fields */
+#define SIM_SCGC_RTC_MASK                        0x1u
+#define SIM_SCGC_RTC_SHIFT                       0
+#define SIM_SCGC_PIT_MASK                        0x2u
+#define SIM_SCGC_PIT_SHIFT                       1
+#define SIM_SCGC_ETM0_MASK                       0x20u
+#define SIM_SCGC_ETM0_SHIFT                      5
+#define SIM_SCGC_ETM1_MASK                       0x40u
+#define SIM_SCGC_ETM1_SHIFT                      6
+#define SIM_SCGC_ETM2_MASK                       0x80u
+#define SIM_SCGC_ETM2_SHIFT                      7
+#define SIM_SCGC_CRC_MASK                        0x400u
+#define SIM_SCGC_CRC_SHIFT                       10
+#define SIM_SCGC_FLASH_MASK                      0x1000u
+#define SIM_SCGC_FLASH_SHIFT                     12
+#define SIM_SCGC_SWD_MASK                        0x2000u
+#define SIM_SCGC_SWD_SHIFT                       13
+#define SIM_SCGC_IIC_MASK                        0x20000u
+#define SIM_SCGC_IIC_SHIFT                       17
+#define SIM_SCGC_SPI0_MASK                       0x40000u
+#define SIM_SCGC_SPI0_SHIFT                      18
+#define SIM_SCGC_SPI1_MASK                       0x80000u
+#define SIM_SCGC_SPI1_SHIFT                      19
+#define SIM_SCGC_UART0_MASK                      0x100000u
+#define SIM_SCGC_UART0_SHIFT                     20
+#define SIM_SCGC_UART1_MASK                      0x200000u
+#define SIM_SCGC_UART1_SHIFT                     21
+#define SIM_SCGC_UART2_MASK                      0x400000u
+#define SIM_SCGC_UART2_SHIFT                     22
+#define SIM_SCGC_KBI0_MASK                       0x1000000u
+#define SIM_SCGC_KBI0_SHIFT                      24
+#define SIM_SCGC_KBI1_MASK                       0x2000000u
+#define SIM_SCGC_KBI1_SHIFT                      25
+#define SIM_SCGC_IRQ_MASK                        0x8000000u
+#define SIM_SCGC_IRQ_SHIFT                       27
+#define SIM_SCGC_ADC_MASK                        0x20000000u
+#define SIM_SCGC_ADC_SHIFT                       29
+#define SIM_SCGC_ACMP0_MASK                      0x40000000u
+#define SIM_SCGC_ACMP0_SHIFT                     30
+#define SIM_SCGC_ACMP1_MASK                      0x80000000u
+#define SIM_SCGC_ACMP1_SHIFT                     31
+/* UUIDL Bit Fields */
+#define SIM_UUIDL_ID_MASK                        0xFFFFFFFFu
+#define SIM_UUIDL_ID_SHIFT                       0
+#define SIM_UUIDL_ID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UUIDL_ID_SHIFT))&SIM_UUIDL_ID_MASK)
+/* UUIDH Bit Fields */
+#define SIM_UUIDM_ID_MASK                        0xFFFFFFFFu
+#define SIM_UUIDM_ID_SHIFT                       0
+#define SIM_UUIDM_ID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UUIDM_ID_SHIFT))&SIM_UUIDM_ID_MASK)
+/* UUIDM Bit Fields */
+#define SIM_UUIDH_ID_MASK                        0xFFFFFFFFu
+#define SIM_UUIDH_ID_SHIFT                       0
+#define SIM_UUIDH_ID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UUIDH_ID_SHIFT))&SIM_UUIDH_ID_MASK)
+/* BUSDIV Bit Fields */
+#define SIM_BUSDIV_BUSDIV_MASK                   0x1u
+#define SIM_BUSDIV_BUSDIV_SHIFT                  0
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40048000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES                                { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< SPI control register 1, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< SPI control register 2, offset: 0x1 */
+  __IO uint8_t BR;                                 /**< SPI baud rate register, offset: 0x2 */
+  __I  uint8_t S;                                  /**< SPI status register, offset: 0x3 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t D;                                  /**< SPI data register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t M;                                  /**< SPI match register, offset: 0x7 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK                        0x1u
+#define SPI_C1_LSBFE_SHIFT                       0
+#define SPI_C1_SSOE_MASK                         0x2u
+#define SPI_C1_SSOE_SHIFT                        1
+#define SPI_C1_CPHA_MASK                         0x4u
+#define SPI_C1_CPHA_SHIFT                        2
+#define SPI_C1_CPOL_MASK                         0x8u
+#define SPI_C1_CPOL_SHIFT                        3
+#define SPI_C1_MSTR_MASK                         0x10u
+#define SPI_C1_MSTR_SHIFT                        4
+#define SPI_C1_SPTIE_MASK                        0x20u
+#define SPI_C1_SPTIE_SHIFT                       5
+#define SPI_C1_SPE_MASK                          0x40u
+#define SPI_C1_SPE_SHIFT                         6
+#define SPI_C1_SPIE_MASK                         0x80u
+#define SPI_C1_SPIE_SHIFT                        7
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK                         0x1u
+#define SPI_C2_SPC0_SHIFT                        0
+#define SPI_C2_SPISWAI_MASK                      0x2u
+#define SPI_C2_SPISWAI_SHIFT                     1
+#define SPI_C2_BIDIROE_MASK                      0x8u
+#define SPI_C2_BIDIROE_SHIFT                     3
+#define SPI_C2_MODFEN_MASK                       0x10u
+#define SPI_C2_MODFEN_SHIFT                      4
+#define SPI_C2_SPMIE_MASK                        0x80u
+#define SPI_C2_SPMIE_SHIFT                       7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK                          0xFu
+#define SPI_BR_SPR_SHIFT                         0
+#define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK                         0x70u
+#define SPI_BR_SPPR_SHIFT                        4
+#define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* S Bit Fields */
+#define SPI_S_MODF_MASK                          0x10u
+#define SPI_S_MODF_SHIFT                         4
+#define SPI_S_SPTEF_MASK                         0x20u
+#define SPI_S_SPTEF_SHIFT                        5
+#define SPI_S_SPMF_MASK                          0x40u
+#define SPI_S_SPMF_SHIFT                         6
+#define SPI_S_SPRF_MASK                          0x80u
+#define SPI_S_SPRF_SHIFT                         7
+/* D Bit Fields */
+#define SPI_D_Bits_MASK                          0xFFu
+#define SPI_D_Bits_SHIFT                         0
+#define SPI_D_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
+/* M Bit Fields */
+#define SPI_M_Bits_MASK                          0xFFu
+#define SPI_M_Bits_SHIFT                         0
+#define SPI_M_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES                                { SPI0, SPI1 }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Register: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Register: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+/* D Bit Fields */
+#define UART_D_R0T0_MASK                         0x1u
+#define UART_D_R0T0_SHIFT                        0
+#define UART_D_R1T1_MASK                         0x2u
+#define UART_D_R1T1_SHIFT                        1
+#define UART_D_R2T2_MASK                         0x4u
+#define UART_D_R2T2_SHIFT                        2
+#define UART_D_R3T3_MASK                         0x8u
+#define UART_D_R3T3_SHIFT                        3
+#define UART_D_R4T4_MASK                         0x10u
+#define UART_D_R4T4_SHIFT                        4
+#define UART_D_R5T5_MASK                         0x20u
+#define UART_D_R5T5_SHIFT                        5
+#define UART_D_R6T6_MASK                         0x40u
+#define UART_D_R6T6_SHIFT                        6
+#define UART_D_R7T7_MASK                         0x80u
+#define UART_D_R7T7_SHIFT                        7
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES                               { UART0, UART1, UART2 }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CS1;                                /**< Watchdog Control and Status Register 1, offset: 0x0 */
+  __IO uint8_t CS2;                                /**< Watchdog Control and Status Register 2, offset: 0x1 */
+  union {                                          /* offset: 0x2 */
+    __IO uint16_t CNT;                               /**< WDOG_CNT register., offset: 0x2 */
+    struct {                                         /* offset: 0x2 */
+      __I  uint8_t CNTH;                               /**< Watchdog Counter Register: High, offset: 0x2 */
+      __I  uint8_t CNTL;                               /**< Watchdog Counter Register: Low, offset: 0x3 */
+    } CNT8B;
+  };
+  union {                                          /* offset: 0x4 */
+    __IO uint16_t TOVAL;                             /**< WDOG_TOVAL register., offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t TOVALH;                             /**< Watchdog ETMeout Value Register: High, offset: 0x4 */
+      __IO uint8_t TOVALL;                             /**< Watchdog ETMeout Value Register: Low, offset: 0x5 */
+    } TOVAL8B;
+  };
+  union {                                          /* offset: 0x6 */
+    __IO uint16_t WIN;                               /**< WDOG_WIN register., offset: 0x6 */
+    struct {                                         /* offset: 0x6 */
+      __IO uint8_t WINH;                               /**< Watchdog Window Register: High, offset: 0x6 */
+      __IO uint8_t WINL;                               /**< Watchdog Window Register: Low, offset: 0x7 */
+    } WIN8B;
+  };
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* CS1 Bit Fields */
+#define WDOG_CS1_STOP_MASK                       0x1u
+#define WDOG_CS1_STOP_SHIFT                      0
+#define WDOG_CS1_WAIT_MASK                       0x2u
+#define WDOG_CS1_WAIT_SHIFT                      1
+#define WDOG_CS1_DBG_MASK                        0x4u
+#define WDOG_CS1_DBG_SHIFT                       2
+#define WDOG_CS1_TST_MASK                        0x18u
+#define WDOG_CS1_TST_SHIFT                       3
+#define WDOG_CS1_TST(x)                          (((uint8_t)(((uint8_t)(x))<<WDOG_CS1_TST_SHIFT))&WDOG_CS1_TST_MASK)
+#define WDOG_CS1_UPDATE_MASK                     0x20u
+#define WDOG_CS1_UPDATE_SHIFT                    5
+#define WDOG_CS1_INT_MASK                        0x40u
+#define WDOG_CS1_INT_SHIFT                       6
+#define WDOG_CS1_EN_MASK                         0x80u
+#define WDOG_CS1_EN_SHIFT                        7
+/* CS2 Bit Fields */
+#define WDOG_CS2_CLK_MASK                        0x3u
+#define WDOG_CS2_CLK_SHIFT                       0
+#define WDOG_CS2_CLK(x)                          (((uint8_t)(((uint8_t)(x))<<WDOG_CS2_CLK_SHIFT))&WDOG_CS2_CLK_MASK)
+#define WDOG_CS2_PRES_MASK                       0x10u
+#define WDOG_CS2_PRES_SHIFT                      4
+#define WDOG_CS2_FLG_MASK                        0x40u
+#define WDOG_CS2_FLG_SHIFT                       6
+#define WDOG_CS2_WIN_MASK                        0x80u
+#define WDOG_CS2_WIN_SHIFT                       7
+/* CNT Bit Fields */
+#define WDOG_CNT_CNT_MASK                        0xFFFFu
+#define WDOG_CNT_CNT_SHIFT                       0
+#define WDOG_CNT_CNT(x)                          (((uint16_t)(((uint16_t)(x))<<WDOG_CNT_CNT_SHIFT))&WDOG_CNT_CNT_MASK)
+/* CNTH Bit Fields */
+#define WDOG_CNTH_CNTHIGH_MASK                   0xFFu
+#define WDOG_CNTH_CNTHIGH_SHIFT                  0
+#define WDOG_CNTH_CNTHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<WDOG_CNTH_CNTHIGH_SHIFT))&WDOG_CNTH_CNTHIGH_MASK)
+/* CNTL Bit Fields */
+#define WDOG_CNTL_CNTLOW_MASK                    0xFFu
+#define WDOG_CNTL_CNTLOW_SHIFT                   0
+#define WDOG_CNTL_CNTLOW(x)                      (((uint8_t)(((uint8_t)(x))<<WDOG_CNTL_CNTLOW_SHIFT))&WDOG_CNTL_CNTLOW_MASK)
+/* TOVAL Bit Fields */
+#define WDOG_TOVAL_TOVAL_MASK                    0xFFFFu
+#define WDOG_TOVAL_TOVAL_SHIFT                   0
+#define WDOG_TOVAL_TOVAL(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_TOVAL_TOVAL_SHIFT))&WDOG_TOVAL_TOVAL_MASK)
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint8_t)(((uint8_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint8_t)(((uint8_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WIN Bit Fields */
+#define WDOG_WIN_WIN_MASK                        0xFFFFu
+#define WDOG_WIN_WIN_SHIFT                       0
+#define WDOG_WIN_WIN(x)                          (((uint16_t)(((uint16_t)(x))<<WDOG_WIN_WIN_SHIFT))&WDOG_WIN_WIN_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW(x)                      (((uint8_t)(((uint8_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASES                               { WDOG }
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define NV_DFPROT_DPS_MASK                NV_EEPROT_DPS_MASK
+#define NV_DFPROT_DPS_SHIFT               NV_EEPROT_DPS_SHIFT
+#define NV_DFPROT_DPS(x)                  NV_EEPROT_DPS(x)
+#define NV_DFPROT_DPOPEN_MASK             NV_EEPROT_DPOPEN_MASK
+#define NV_DFPROT_DPOPEN_SHIFT            NV_EEPROT_DPOPEN_SHIFT
+#define NV_DFPROT_DPOPEN_SHIFT            NV_EEPROT_DPOPEN_SHIFT
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif  /* #if !defined(NV32_H_) */
+
+/* NV32.h, eof. */
diff --git a/bsp/nv32f100x/lib/inc/NV32_config.h b/bsp/nv32f100x/lib/inc/NV32_config.h
new file mode 100644
index 0000000000..17b17e7977
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/NV32_config.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* NOTE:系统所使用的一些宏定义，以及时钟模式的选择。
+******************************************************************************/
+
+#ifndef _NVxx_CONFIG_H_
+#define _NVxx_CONFIG_H_
+
+
+#include <stdint.h>
+
+#define CPU_NV32
+#define TEST
+
+
+//#define TRIM_IRC                    /*!< 是否使用定义的TRIM值来校准内部IRC，若注释则使用出厂校准的TRIM值出厂校准至37.5K--48M */
+//#define SPI0_PINREMAP               /*!< SPI0的管脚映射定义 */
+//#define ENABLE_WDOG               /*!< 使能看门狗 */
+//#define DISABLE_NMI               /*!< 禁用NMI中断输入引脚 */
+
+/*! 定义是否打印系统信息 */      
+//#define PRINT_SYS_LOG           
+
+#if     !defined(BOOT_LOADER)
+#endif
+
+//#define OUTPUT_BUSCLK             /*!< 定义是否输出系统时钟，输出引脚为PH2 */
+#define ICS_TRIM_VALUE  0x2c   
+
+
+    /*! 定义时钟的时钟模式以及频率
+     */
+   //#define USE_FEE                         /*!< 使用外部时钟FEE模式 */
+   //#define USE_FEE_OSC                     /*!< 使用外部时钟输入OSC模式 */
+     #define USE_FEI                         /*!< 使用系统内部时钟IRC */
+  // #define USE_FBELP	
+   //#define USE_FBE_OSC
+
+   /*! 定义外部晶振频率. */
+   //#define EXT_CLK_FREQ_KHZ	32          /* in KHz */
+   //#define EXT_CLK_FREQ_KHZ	4000        /* in KHz */
+   //#define EXT_CLK_FREQ_KHZ	4000        /* in KHz */
+   //#define EXT_CLK_FREQ_KHZ	1000        /* in KHz */
+     #define EXT_CLK_FREQ_KHZ	10000       /* in KHz */
+    /*! 定义所使用的UART口 */
+    #define TERM_PORT   UART1               /*!< 定义使用UART1口，开发板上默认使用UART1口 */
+
+
+    /* 定义总线时钟主频 */
+    #if	defined(USE_FEI)
+        #define  BUS_CLK_HZ		40000000L
+
+    #elif  (EXT_CLK_FREQ_KHZ == 10000)
+        #define  BUS_CLK_HZ		50000000L
+    #elif  (EXT_CLK_FREQ_KHZ == 12000)
+        #define  BUS_CLK_HZ   30000000L
+    #elif  (EXT_CLK_FREQ_KHZ == 8000)
+        #define  BUS_CLK_HZ		24000000L
+    #elif  (EXT_CLK_FREQ_KHZ == 4000)
+        #define  BUS_CLK_HZ		40000000L
+    #elif  (EXT_CLK_FREQ_KHZ == 32)
+        #define  BUS_CLK_HZ		16777216L
+    #else   
+        #define  BUS_CLK_HZ		60000000L
+    #endif
+
+    /*! define UART baud rate */
+    #define UART_PRINT_BITRATE              115200      /*! UART波特率 */
+
+
+#endif /* NVxx_CONFIG_H_ */
diff --git a/bsp/nv32f100x/lib/inc/acmp.h b/bsp/nv32f100x/lib/inc/acmp.h
new file mode 100644
index 0000000000..7b06be070e
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/acmp.h
@@ -0,0 +1,568 @@
+/******************************************************************************
+* @brief header file for ACMP utilities. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing ACMP
+******************************************************************************/
+#ifndef _MY_ACMP_H_
+#define _MY_ACMP_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/* DAC reference select */
+enum
+{
+    DAC_REF_BANDGAP = 0,
+    DAC_REF_VDDA
+};
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+ * ACMP module number definition                                               *
+ ******************************************************************************/
+#define     MAX_ACMP_NO             2
+
+/******************************************************************************
+* ACMP positive and negative pin select definition
+*
+*//*! @addtogroup acmp_pinsel_list
+* @{
+*******************************************************************************/
+#define     ACMP_INPUT_P_EXT0       (0<<4)  /*!< positive pin select external pin 0 */
+#define     ACMP_INPUT_P_EXT1       (1<<4)  /*!< positive pin select external pin 1 */
+#define     ACMP_INPUT_P_EXT2       (2<<4)  /*!< positive pin select external pin 2 */
+#define     ACMP_INPUT_P_DAC        (3<<4)  /*!< positive pin select internal DAC */
+
+#define     ACMP_INPUT_N_EXT0       0       /*!< positive pin select external pin 0 */
+#define     ACMP_INPUT_N_EXT1       1       /*!< positive pin select external pin 1 */
+#define     ACMP_INPUT_N_EXT2       2       /*!< positive pin select external pin 2 */
+#define     ACMP_INPUT_N_DAC        3       /*!< positive pin select internal DAC */
+/*! @} End of acmp_pinsel_list                                                */
+
+/******************************************************************************
+* ACMP interrupt sensitivity edge definition
+*
+*//*! @addtogroup acmp_intedgesel
+* @{
+*******************************************************************************/
+#define     ACMP_SENSITIVITYMODE_FALLING   0    /*!< interrupt on falling edge  */
+#define     ACMP_SENSITIVITYMODE_RISING    1    /*!< interrupt on rising edge  */
+#define     ACMP_SENSITIVITYMODE_ANY       3    /*!< interrupt on falling or rising edge */ 
+/*! @} End of acmp_intedgesel                                                 */
+
+
+/******************************************************************************
+* ACMP hysterisis selection definition
+*
+*//*! @addtogroup acmp_hyst
+* @{
+*******************************************************************************/
+#define     ACMP_HYST_20MV                 (0<<6)  /*!< 20mv hyst */
+#define     ACMP_HYST_30MV                 (1<<6)  /*!< 30mv hyst */
+/*! @} End of acmp_hyst                                                       */
+
+
+/******************************************************************************
+* ACMP internal DAC reference selection definition
+*
+*//*! @addtogroup acmp_dacref
+* @{
+*******************************************************************************/
+#define     ACMP_DAC_REFERENCE_BANDGAP     (0<<6)  /*!< select bandgap as refference */
+#define     ACMP_DAC_REFERENCE_VDDA        (1<<6)  /*!< select VDDA as refference */
+/*! @} End of acmp_dacref                                                     */
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/*! @brief ACMP_CALLBACK function declaration                                  */
+typedef void (*ACMP_CallbackPtr)(void);
+/*! @} End of acmp_callback                                                    */
+
+/******************************************************************************
+* ACMP control status struct
+*
+*//*! @addtogroup acmp_ctrlstatusstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief ACMP control and status fields type.
+ *
+ */
+
+typedef union 
+{
+    uint8_t byte;    				 /*!< byte field of union type */
+    struct 
+    {
+        uint8_t bMod        : 2;     /*!< Sensitivity modes of the interrupt trigger */
+        uint8_t bOutEn      : 1;     /*!< Output can be placed onto an external pin */
+        uint8_t bOutState   : 1;     /*!< The current value of the analog comparator output */
+        uint8_t bIntEn      : 1;     /*!< ACMP interrupt enable */
+        uint8_t bIntFlag    : 1;     /*!< ACMP Interrupt Flag Bit */
+        uint8_t bHyst       : 1;     /*!< Selects ACMP hystersis */
+        uint8_t bEn         : 1;     /*!< Enables the ACMP module */
+    }bits;      				     /*!< bitfield of union type */
+}ACMP_CtrlStatusType, *ACMP_CtrlStatusPtr;  /*!< ACMP Control/Status reg structure */
+/*! @} End of acmp_ctrlstatusstruct                                           */
+
+/******************************************************************************
+* ACMP pin select struct
+*
+*//*! @addtogroup acmp_pinselectstruct
+* @{
+*******************************************************************************/
+/*!
+* @brief ACMP external pins control struct.
+*
+*/
+
+typedef union 
+{
+    uint8_t byte;    				 /*!< byte field of union type */
+    struct 
+    {
+        uint8_t bNegPin  : 2;        /*!< Negative pin select */
+        uint8_t          : 2;
+        uint8_t bPosPin  : 2;        /*!< Positive pin select */
+        uint8_t          : 2;
+    }bits;      				     /*!< bitfield of union type */  
+}ACMP_PinSelType, *ACMP_PinSelPtr; 	     /*!< ACMP Pin select structure */ 
+/*! @} End of acmp_pinselectstruct                                            */
+
+/******************************************************************************
+* ACMP DAC control struct
+*
+*//*! @addtogroup acmp_dacctrlstruct
+* @{
+*******************************************************************************/
+/*!
+* @brief ACMP internal ADC control struct.
+*
+*/
+typedef union 
+{
+    uint8_t byte;    				 /*!< byte field of union type */
+    struct 
+    {
+        uint8_t bVal  : 6;           /*!< 6 bit DAC value */
+        uint8_t bRef  : 1;           /*!< 6 bit DAC reference select */
+        uint8_t bEn   : 1;           /*!< 6 bit DAC enable bit */
+    }bits;      				     /*!< bitfield of union type */  
+}ACMP_DACType, *ACMP_DACPtr;	     /*!< ACMP DAC control structure */ 
+/*! @} End of acmp_dacctrlstruct                                              */
+
+/******************************************************************************
+* ACMP pin enable union
+*
+*//*! @addtogroup acmp_pinenunion
+* @{
+*******************************************************************************/
+/*!
+* @brief ACMP external input pin enable control struct.
+*
+*/
+typedef union 
+{
+    uint8_t byte;    				 /*!< byte field of union type */
+    struct 
+    {
+        uint8_t bEn   : 3;           /*!< ACMP external input pin enable */
+        uint8_t bRsvd : 5;
+    }bits;      				     /*!< bitfield of union type */  
+}ACMP_PinEnType, *ACMP_PinEnPtr;	 /*!< ACMP Pin enable structure */ 
+/*! @} End of acmp_pinenunion                                                 */
+
+/******************************************************************************
+* ACMP config struct
+*
+*//*! @addtogroup acmp_configstruct
+* @{
+*******************************************************************************/
+/*!
+* @brief ACMP module configuration struct.
+*
+*/
+
+typedef struct 
+{
+    ACMP_CtrlStatusType  sCtrlStatus;     /*!< ACMP control and status */
+    ACMP_PinSelType      sPinSelect;      /*!< ACMP pin select */
+    ACMP_DACType         sDacSet;         /*!< ACMP internal dac set */
+    ACMP_PinEnType       sPinEnable;      /*!< ACMP external pin control */
+}ACMP_ConfigType, *ACMP_ConfigPtr;
+/*! @} End of acmp_configstruct                                               */
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/*!
+ * inline functions
+ */
+/******************************************************************************
+* ACMP api list.
+*
+*//*! @addtogroup acmp_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief  enable the acmp module.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_Disable.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_Enable(ACMP_Type *pACMPx)
+{
+    pACMPx->CS |= ACMP_CS_ACE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the acmp module.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_Enable.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_Disable(ACMP_Type *pACMPx)
+{
+    pACMPx->CS &= ~ACMP_CS_ACE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  select sensitivity modes of the interrupt trigger.
+*        
+* @param[in]  pACMPx         pointer to an ACMP module.
+* @param[in]  u8EdgeSelect   falling or rising selction, 0~3. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_SelectIntMode(ACMP_Type *pACMPx, uint8_t u8EdgeSelect)
+{
+    pACMPx->CS &= ~ACMP_CS_ACMOD_MASK;
+    pACMPx->CS |= ACMP_CS_ACMOD(u8EdgeSelect & 0x3);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable the ACMP module analog comparator output.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_DisablePinOut.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_EnablePinOut(ACMP_Type *pACMPx)
+{
+    pACMPx->CS |= ACMP_CS_ACOPE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the ACMP module analog comparator output.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_EnablePinOut.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DisablePinOut(ACMP_Type *pACMPx)
+{
+    pACMPx->CS &= ~ACMP_CS_ACOPE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  select ACMP hystersis. 
+*        
+* @param[in]  pACMPx           pointer to an ACMP module.
+* @param[in]  u8HystSelect     ACMP_HYST_20MV or ACMP_HYST_30MV.   
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_SelectHyst(ACMP_Type *pACMPx, uint8_t u8HystSelect)
+{
+    pACMPx->CS &= ~ACMP_CS_HYST_MASK;
+    pACMPx->CS |= u8HystSelect;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable the acmp module interrupt.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_DisableInterrupt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_EnableInterrupt(ACMP_Type *pACMPx)
+{
+    pACMPx->CS |= ACMP_CS_ACIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the acmp module interrupt.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_EnableInterrupt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DisableInterrupt(ACMP_Type *pACMPx)
+{
+    pACMPx->CS &= ~ACMP_CS_ACIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  get the interrupt flag bit.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_ClrFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t ACMP_GetFlag(ACMP_Type *pACMPx)
+{
+    return (pACMPx->CS & ACMP_CS_ACF_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the interrupt flag bit.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_GetFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_ClrFlag(ACMP_Type *pACMPx)
+{
+    pACMPx->CS &= ~ACMP_CS_ACF_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP Positive Input Select.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8PosPinSel   positive input select, ACMP_INPUT_P_EXT0~2 or ACMP_INPUT_P_DAC.     
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_NegativeInputSelect.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_PositiveInputSelect(ACMP_Type *pACMPx, uint8_t u8PosPinSel)
+{
+    pACMPx->C0 &= ~ACMP_C0_ACPSEL_MASK;
+    pACMPx->C0 |= u8PosPinSel;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP Negative Input Select.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8NegPinSel   negative input select, ACMP_INPUT_N_EXT0~2 or ACMP_INPUT_N_DAC.  
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_PositiveInputSelect.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_NegativeInputSelect(ACMP_Type *pACMPx, uint8_t u8NegPinSel)
+{
+    pACMPx->C0 &= ~ACMP_C0_ACNSEL_MASK;
+    pACMPx->C0 |= u8NegPinSel;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Enable 6 bit DAC in ACMP module.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_DacDisable.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DacEnable(ACMP_Type *pACMPx)
+{
+    pACMPx->C1 |= ACMP_C1_DACEN_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Disable 6 bit DAC in ACMP module.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_DacEnable.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DacDisable(ACMP_Type *pACMPx)
+{
+    pACMPx->C1 &= ~ACMP_C1_DACEN_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP 6 bit DAC Reference Select.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8RefSelect   dac reference select:ACMP_DAC_REFERENCE_BANDGAP or ACMP_DAC_REFERENCE_VDDA.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DacReferenceSelect(ACMP_Type *pACMPx, uint8_t u8RefSelect)
+{
+    pACMPx->C1 &= ~ACMP_C1_DACREF_MASK;
+    pACMPx->C1 |= u8RefSelect;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP 6 bit DAC Output Value Set.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8DacValue    dac output set, Voutput= (Vin/64)x(DACVAL[5:0]+1).
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DacOutputSet(ACMP_Type *pACMPx, uint8_t u8DacValue)
+{
+    ASSERT(!(u8DacValue & (~ACMP_C1_DACVAL_MASK)));
+    pACMPx->C1 &= ~ACMP_C1_DACVAL_MASK;
+    pACMPx->C1 |= ACMP_C1_DACVAL(u8DacValue);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Enable ACMP input pin.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8InputPin    ACMP external pin, 0~2.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_InputPinEnable(ACMP_Type *pACMPx, uint8_t u8InputPin)
+{
+    ASSERT(!(u8InputPin & (~ACMP_C2_ACIPE_MASK)));
+    pACMPx->C2 |= ACMP_C2_ACIPE(u8InputPin);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Disable ACMP input pin.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8InputPin    ACMP external pin, 0~2.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_InputPinDisable(ACMP_Type *pACMPx, uint8_t u8InputPin)
+{
+    ASSERT(!(u8InputPin & (~ACMP_C2_ACIPE_MASK)));
+    pACMPx->C2 &= ~ACMP_C2_ACIPE(u8InputPin);
+}
+
+/*! @} End of acmp_api_list                                                  */
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void ACMP_Init(ACMP_Type *pACMPx, ACMP_ConfigType *pConfig);
+void ACMP_DeInit(ACMP_Type *pACMPx); 
+void ACMP_ConfigDAC(ACMP_Type *pACMPx, ACMP_DACType *pDACConfig);
+void ACMP_SetCallback(ACMP_Type *pACMPx, ACMP_CallbackPtr pfnCallback);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _MY_ACMP_H_ */
+
+
+
diff --git a/bsp/nv32f100x/lib/inc/adc.h b/bsp/nv32f100x/lib/inc/adc.h
new file mode 100644
index 0000000000..31babb0a58
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/adc.h
@@ -0,0 +1,711 @@
+/******************************************************************************
+*
+* @brief header file for ADC module utilities (ADC). 
+*
+*******************************************************************************
+*
+* provide APIs for accessing ADC module (ADC)
+******************************************************************************/
+
+#ifndef ADC_H_
+#define ADC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Macros
+******************************************************************************/
+/******************************************************************************
+*define ADC refernce voltage 
+*
+*//*! @addtogroup adc_ref_list
+* @{
+*******************************************************************************/
+
+#define ADC_VREF_VREFH                 0x00			/*!< ADC reference voltage is VREFH*/
+#define ADC_VREF_VDDA                  0x01			/*!< ADC reference voltage is VDDA*/
+
+/*! @} End of adc_ref_list                                                    						*/
+
+/******************************************************************************
+* define ADC clock source 
+*
+*//*! @addtogroup adc_clock_source_list
+* @{
+*******************************************************************************/
+
+#define CLOCK_SOURCE_BUS_CLOCK							0x00	/*!< ADC clock source is bus clock*/
+#define CLOCK_SOURCE_BUS_CLOCK_DIVIDE_2			        0x01	/*!< ADC clock source is bus clock devided by 2*/
+#define CLOCK_SOURCE_ALTCLK								0x02	/*!< ADC clock source is alternative clcok*/
+#define CLOCK_SOURCE_ADACK								0x03	/*!< ADC clock source is asynchronous clock*/
+/*! @} End of adc_clock_source_list                                          						*/
+
+
+/******************************************************************************
+* define ADC divider 
+*
+*//*! @addtogroup adc_clock_divider_list
+* @{
+*******************************************************************************/
+
+#define ADC_ADIV_DIVIDE_1								0x00		/*!< ADC clock divide by 1*/
+#define ADC_ADIV_DIVIDE_2								0x01		/*!< ADC clock divide by 2*/
+#define ADC_ADIV_DIVIDE_4								0x02		/*!< ADC clock divide by 4*/
+#define ADC_ADIV_DIVIDE_8								0x03		/*!< ADC clock divide by 8*/
+/*! @} End of adc_clock_divider_list                                          						*/
+
+/******************************************************************************
+* define ADC mode 
+*
+*//*! @addtogroup adc_mode_list
+* @{
+*******************************************************************************/
+
+#define ADC_MODE_8BIT									0x00		/*!< ADC 8bit mode*/
+#define ADC_MODE_10BIT									0x01		/*!< ADC 10bit mode*/
+#define ADC_MODE_12BIT									0x02		/*!< ADC 12bit mode */
+/*! @} End of adc_mode_list                                               						*/
+
+/******************************************************************************
+* define ADC channel
+*
+*//*! @addtogroup adc_channel_list
+* @{
+*******************************************************************************/
+
+#define ADC_CHANNEL_AD0                                 0x0 /*!< ADC input channel 0 */
+#define ADC_CHANNEL_AD1                                 0x1 /*!< ADC input channel 1 */
+#define ADC_CHANNEL_AD2                                 0x2 /*!< ADC input channel 2 */
+#define ADC_CHANNEL_AD3                                 0x3 /*!< ADC input channel 3 */
+#define ADC_CHANNEL_AD4                                 0x4 /*!< ADC input channel 4 */
+#define ADC_CHANNEL_AD5                                 0x5 /*!< ADC input channel 5 */
+#define ADC_CHANNEL_AD6                                 0x6 /*!< ADC input channel 6 */
+#define ADC_CHANNEL_AD7                                 0x7 /*!< ADC input channel 7 */
+#define ADC_CHANNEL_AD8                                 0x8 /*!< ADC input channel 8 */
+#define ADC_CHANNEL_AD9                                 0x9 /*!< ADC input channel 9 */
+#define ADC_CHANNEL_AD10                                 0xa /*!< ADC input channel 10 */
+#define ADC_CHANNEL_AD11                                 0xb /*!< ADC input channel 11 */
+#define ADC_CHANNEL_AD12                                 0xc /*!< ADC input channel 12 */
+#define ADC_CHANNEL_AD13                                 0xd /*!< ADC input channel 13 */
+#define ADC_CHANNEL_AD14                                 0xe /*!< ADC input channel 14 */
+#define ADC_CHANNEL_AD15                                 0xf /*!< ADC input channel 15 */
+#define ADC_CHANNEL_AD18_VSS                            0x12 /*!< ADC input channel VSS */ 
+#define ADC_CHANNEL_AD22_TEMPSENSOR                     0x16 /*!< ADC input channel internal temperature sensor */
+#define ADC_CHANNEL_AD23_BANDGAP                        0x17 /*!< ADC input channel bandgap */ 
+#define ADC_CHANNEL_AD29_VREFH                          0x1D /*!< ADC input channel Vrefh */ 
+#define ADC_CHANNEL_AD30_VREFL                          0x1E /*!< ADC input channel Vrefl */ 
+#define ADC_CHANNEL_DISABLE                             0x1F /*!< ADC disable */
+/*! @} End of adc_channel_list                                               						*/
+
+
+/******************************************************************************
+* define ADC FIFO_LEVEL
+*
+*//*! @addtogroup adc_fifo_level_list
+* @{
+*******************************************************************************/
+#define ADC_FIFO_DISABLE                                0 /*!< FIFO Level 0 */
+#define ADC_FIFO_LEVEL2                                 1 /*!< FIFO Level 1 */
+#define ADC_FIFO_LEVEL3                                 2 /*!< FIFO Level 2 */
+#define ADC_FIFO_LEVEL4                                 3 /*!< FIFO Level 3 */
+#define ADC_FIFO_LEVEL5                                 4 /*!< FIFO Level 4 */
+#define ADC_FIFO_LEVEL6                                 5 /*!< FIFO Level 5 */
+#define ADC_FIFO_LEVEL7                                 6 /*!< FIFO Level 6 */
+#define ADC_FIFO_LEVEL8                                 7	/*!< FIFO Level 7 */
+/*! @} End of adc_fifo_level_list                                               						*/
+
+
+/******************************************************************************
+* define ADC trigger source
+*
+*//*! @addtogroup adc_trigger_list
+* @{
+*******************************************************************************/
+#define ADC_HARDWARE_TRIGGER                            0x01  /*!< hardware trigger */
+#define ADC_SOFTWARE_TRIGGER                            0x00	/*!< software trigger */
+#define ADC_TRIGGER_RTC                                 0x00  /*!< RTC act as trigger source */          
+#define ADC_TRIGGER_PIT                                 0x01  /*!< PIT act as trigger source */ 
+#define ADC_TRIGGER_ETM2INIT                            0x10  /*!< ETM2 initialization act as trigger source */ 
+#define ADC_TRIGGER_ETM2MATCH                           0x11  /*!< ETM2 match interrupt act as trigger source */
+/*! @} End of adc_trigger_list                                               						*/
+
+
+#define ADC_COMPARE_LESS                                0x00
+#define ADC_COMPARE_GREATER                             0x01
+
+
+/******************************************************************************
+* define ADC call back
+*
+*//*! @addtogroup adc_callback
+* @{
+*******************************************************************************/
+typedef void (*ADC_CallbackType)(void);							/*!< ADC call back function */
+/*! @} End of adc_callback                                               						*/
+
+/******************************************************************************
+* 
+*
+*//*! @addtogroup adc_setting_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief ADC setting type.
+ *
+ */
+typedef struct
+{
+    uint16_t bIntEn                 :1;     /*!< 1: Interrupt Enable, 0: Interrupt disable */
+    uint16_t bContinuousEn          :1;     /*!< 1: Continuous Conversion Enable, 0: Continuous Conversion disable */
+    uint16_t bHardwareTriggerEn     :1;     /*!< 1: hardware trigger, 0: software trigger */
+    uint16_t bCompareEn             :1;     /*!< 1: compare mode Enable, 0: compare mode disable */
+    uint16_t bCompareGreaterEn      :1;     /*!< 1: Compare greater mode, 0: compare less than mode */
+    uint16_t bLowPowerEn            :1;     /*!< 1: Low power mode, 0: high speed mode */
+    uint16_t bLongSampleEn          :1;     /*!< 1: long sample mode, 0: short sample mode */
+    uint16_t bFiFoScanModeEn        :1;     /*!< 1: FIFO scan mode enable, 0: FIFO scan mode disable */
+    uint16_t bCompareAndEn          :1;     /*!< 1: Compare and logic, 0: Compare and logic */
+#ifdef CPU_NV32 
+    uint16_t bReverse               :7;    
+#else
+    uint16_t bHTRGMEn               :1;     /*!< one hardware trigger pulse trigger multiple conversions in fifo mode */      
+    uint16_t bHTRGMASKEn            :1;		/*!< Hardware trigger mask enable. */
+    uint16_t bHTRGMASKSEL           :1;		/*!< This field selects hardware trigger mask mode. */
+    uint16_t Reserve                :4;
+#endif
+}ADC_SettingType;
+/*! @} End of adc_setting_type                                               						*/
+
+/******************************************************************************
+* 
+*
+*//*! @addtogroup adc_config_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief ADC configure type.
+ *
+ */
+typedef struct
+{
+    ADC_SettingType sSetting;               /*!< ADC setting structure*/
+    uint16_t u16PinControl;                 /*!< pin control */
+    uint8_t u8ClockSource;                  /*!< clock source selection */
+    uint8_t u8ClockDiv;                     /*!< set clock divider */
+    uint8_t u8Mode;                         /*!< set clcok mode(8/10/12 bit mode) */
+    uint8_t u8FiFoLevel;                    /*!< set FIFO level */
+}ADC_ConfigType,*ADC_ConfigTypePtr;
+/*! @} End of adc_config_type                                               */
+
+/******************************************************************************
+* define ADC APIs
+*
+*//*! @addtogroup adc_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC interrupt.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_IntEnable( ADC_Type *pADC )
+{
+    pADC->SC1 |= ADC_SC1_AIEN_MASK;   
+}
+/*****************************************************************************//*!
+   *
+   * @brief disable ADC interrupt.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_IntDisable( ADC_Type *pADC )
+{
+    pADC->SC1 &= ~ADC_SC1_AIEN_MASK;   
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC continuous conversion.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_ContinuousConversion( ADC_Type *pADC )
+{
+    pADC->SC1 |= ADC_SC1_ADCO_MASK;   
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC single conversion
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SingleConversion( ADC_Type *pADC )
+{
+    pADC->SC1 &= ~ADC_SC1_ADCO_MASK;   
+}
+/*****************************************************************************//*!
+   *
+   * @brief set the ADC to hardware trigger.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetHardwareTrigger( ADC_Type *pADC )
+{
+    pADC->SC2 |= ADC_SC2_ADTRG_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set the ADC to software trigger.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetSoftwareTrigger( ADC_Type *pADC )
+{
+    pADC->SC2 &= ~ADC_SC2_ADTRG_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC compare function.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareEnable( ADC_Type *pADC )
+{
+    pADC->SC2 |= ADC_SC2_ACFE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief disable ADC compare function.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareDisable( ADC_Type *pADC )
+{
+    pADC->SC2 &= ~ADC_SC2_ACFE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC compare greater function.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareGreaterFunction( ADC_Type *pADC )
+{
+    pADC->SC2 |= ADC_SC2_ACFGT_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC compare less function.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareLessFunction( ADC_Type *pADC )
+{
+    pADC->SC2 &= ~ADC_SC2_ACFGT_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set ADC to low power configuration.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetLowPower( ADC_Type *pADC )
+{
+    pADC->SC3 |= ADC_SC3_ADLPC_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set ADC to high speed configuration.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetHighSpeed( ADC_Type *pADC )
+{
+    pADC->SC3 &= ~ADC_SC3_ADLPC_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Long Sample ETMe Configuration.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetLongSample( ADC_Type *pADC )
+{
+    pADC->SC3 |= ADC_SC3_ADLSMP_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Short Sample ETMe Configuration.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetShortSample( ADC_Type *pADC )
+{
+    pADC->SC3 &= ~ADC_SC3_ADLSMP_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief FIFO scan mode enable.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+__STATIC_INLINE void ADC_FifoScanModeEnable( ADC_Type *pADC )
+{
+    pADC->SC4 |= ADC_SC4_ASCANE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief FIFO scan mode disable.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_FifoScanModeDisable( ADC_Type *pADC )
+{
+    pADC->SC4 &= ~ADC_SC4_ASCANE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief OR all of compare trigger.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareFifoOr( ADC_Type *pADC )
+{
+    pADC->SC4 &= ~ADC_SC4_ACFSEL_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief And all of compare trigger.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareFifoAnd( ADC_Type *pADC )
+{
+    pADC->SC4 |= ADC_SC4_ACFSEL_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief read ADC result register.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return ADC result value.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint16_t ADC_ReadResultReg( ADC_Type *pADC )
+{
+    return (uint16_t)pADC->R;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set ADC compare value.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u16Compare compare value. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetCompareValue( ADC_Type *pADC, uint16_t u16Compare )
+{
+    pADC->CV = u16Compare;
+}
+/*****************************************************************************//*!
+   *
+   * @brief ADC pin control enable.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u16PinNumber enable ADC function to specified pin number. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_PinControlEnable( ADC_Type *pADC, uint16_t u16PinNumber)
+{
+    ASSERT((u16PinNumber<16));
+    pADC->APCTL1 &= ~(0x01<<u16PinNumber);
+}
+/*****************************************************************************//*!
+   *
+   * @brief ADC pin control disable.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u16PinNumber  disable ADC function to specified pin number. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_PinControlDisable( ADC_Type *pADC, uint16_t u16PinNumber)
+{
+    ASSERT((u16PinNumber<16));
+    pADC->APCTL1 |= (0x01<<u16PinNumber);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check conversion active status
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint8_t ADC_IsConversionActiveFlag( ADC_Type *pADC )
+{
+    return(pADC->SC2 & ADC_SC2_ADACT_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check COCO flag
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint8_t ADC_IsCOCOFlag( ADC_Type *pADC )
+{
+    return(pADC->SC1 & ADC_SC1_COCO_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check Result FIFO empty
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint8_t ADC_IsFIFOEmptyFlag( ADC_Type *pADC )
+{
+    return(pADC->SC2 & ADC_SC2_FEMPTY_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check Result FIFO full
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint8_t ADC_IsFIFOFullFlag( ADC_Type *pADC )
+{
+    return(pADC->SC2 & ADC_SC2_FFULL_MASK);
+}
+#ifndef CPU_NV32
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Multiple Conversion Enable
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMultiple( ADC_Type *pADC )
+{
+    pADC->SC4 |= ADC_SC4_HTRGME_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Single Conversion
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerSingle( ADC_Type *pADC )
+{
+    pADC->SC4 &= ~ADC_SC4_HTRGME_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Mask Enable
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMaskEnable( ADC_Type *pADC )
+{
+    pADC->SC5 |= ADC_SC5_HTRGMASKE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Mask Disable
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMaskDisable( ADC_Type *pADC )
+{
+    pADC->SC5 &= ~ADC_SC5_HTRGMASKE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Mask Mode Select Automatic Mode
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMaskAuto( ADC_Type *pADC )
+{
+    pADC->SC5 |= ADC_SC5_HTRGMASKSEL_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Mask Mode Select to be with HTRGMASKE
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMaskNonAuto( ADC_Type *pADC )
+{
+    pADC->SC5 &= ~ADC_SC5_HTRGMASKSEL_MASK;
+}
+#endif
+/******************************************************************************
+* Global function
+******************************************************************************/
+
+void ADC_SetChannel( ADC_Type *pADC, uint8_t u8Channel );
+void ADC_IntEnable( ADC_Type *pADC );
+void ADC_IntDisable( ADC_Type *pADC );
+void ADC_ContinuousConversion( ADC_Type *pADC );
+void ADC_SingleConversion( ADC_Type *pADC );
+void ADC_SetSoftwareTrigger( ADC_Type *pADC );
+void ADC_SetHardwareTrigger( ADC_Type *pADC );
+void ADC_VrefSelect( ADC_Type *pADC, uint8_t u8Vref );
+void ADC_CompareEnable( ADC_Type *pADC );
+void ADC_CompareDisable( ADC_Type *pADC );
+void ADC_CompareGreaterFunction( ADC_Type *pADC );
+void ADC_CompareLessFunction( ADC_Type *pADC );
+void ADC_SetLowPower( ADC_Type *pADC );
+void ADC_SetHighSpeed( ADC_Type *pADC );
+void ADC_SelectClockDivide( ADC_Type *pADC, uint8_t u8Div);
+void ADC_SetLongSample(ADC_Type *pADC);
+void ADC_SetShortSample(ADC_Type *pADC);
+void ADC_SetMode(ADC_Type *pADC, uint8_t u8Mode);
+void ADC_SelectClock(ADC_Type *pADC, uint8_t u8Clock);
+void ADC_FifoScanModeEnable(ADC_Type *pADC);
+void ADC_FifoScanModeDisable(ADC_Type *pADC);
+void ADC_CompareFifoOr(ADC_Type *pADC);
+void ADC_CompareFifoAnd(ADC_Type *pADC);
+void ADC_SetFifoLevel(ADC_Type *pADC, uint8_t u8FifoLevel);
+uint16_t ADC_ReadResultReg(ADC_Type *pADC );
+void ADC_SetCompareValue(ADC_Type *pADC, uint16_t u16Compare );
+void ADC_PinControlEnable(ADC_Type *pADC, uint16_t u16PinNumber);
+void ADC_PinControlDisable(ADC_Type *pADC, uint16_t u16PinNumber);
+uint8_t ADC_IsConversionActiveFlag(ADC_Type *pADC);
+uint8_t ADC_IsCOCOFlag(ADC_Type *pADC);
+uint8_t ADC_IsFIFOEmptyFlag(ADC_Type *pADC);
+uint8_t ADC_IsFIFOFullFlag(ADC_Type *pADC);
+void ADC_HardwareTriggerMaskNonAuto(ADC_Type *pADC);
+void ADC_HardwareTriggerMaskAuto(ADC_Type *pADC);
+void ADC_HardwareTriggerMaskDisable( ADC_Type *pADC );
+void ADC_HardwareTriggerMaskEnable( ADC_Type *pADC );
+void ADC_HardwareTriggerSingle( ADC_Type *pADC );
+void ADC_HardwareTriggerMultiple( ADC_Type *pADC );
+unsigned int ADC_PollRead( ADC_Type *pADC, uint8_t u8Channel);
+void ADC_SetCallBack(ADC_CallbackType pADC_CallBack);
+void ADC_DeInit(ADC_Type *pADC);
+void ADC_Init(ADC_Type *pADC, ADC_ConfigTypePtr pADC_Config);
+/*! @} End of adc_api_list                                               						*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ADC_H_ */
diff --git a/bsp/nv32f100x/lib/inc/arm_cm0.h b/bsp/nv32f100x/lib/inc/arm_cm0.h
new file mode 100644
index 0000000000..481507f4bc
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/arm_cm0.h
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* @brief provide generic high-level routines for ARM Cortex M0/M0+ processors. 
+*
+*******************************************************************************/
+
+#ifndef _CPU_ARM_CM0_H
+#define _CPU_ARM_CM0_H
+
+/*ARM Cortex M0 implementation for interrupt priority shift*/
+#define ARM_INTERRUPT_LEVEL_BITS          2
+
+
+/***********************************************************************/
+  /*!< Macro to enable all interrupts. */
+#ifndef KEIL
+#define EnableInterrupts asm(" CPSIE i");
+#else
+#define EnableInterrupts  __enable_irq()
+#endif
+
+  /*!< Macro to disable all interrupts. */
+#ifndef KEIL
+#define DisableInterrupts asm(" CPSID i");
+#else
+#define DisableInterrupts __disable_irq()
+#endif
+
+#define disable_irq(irq)             NVIC_DisableIRQ(irq)
+#define enable_irq(irq)              NVIC_EnableIRQ(irq)
+#define set_irq_priority(irq, prio)  NVIC_SetPriority(irq, prio)
+/***********************************************************************/
+
+
+/*
+ * Misc. Defines
+ */
+#ifdef	FALSE
+#undef	FALSE
+#endif
+#define FALSE	(0)
+
+#ifdef	TRUE
+#undef	TRUE
+#endif
+#define	TRUE	(1)
+
+#ifdef	NULL
+#undef	NULL
+#endif
+#define NULL	(0)
+
+#ifdef  ON
+#undef  ON
+#endif
+#define ON      (1)
+
+#ifdef  OFF
+#undef  OFF
+#endif
+#define OFF     (0)
+
+#undef  ENABLE
+#define ENABLE  (1)
+
+#undef  DISABLE
+#define DISABLE  (0)
+
+
+/***********************************************************************/
+/*
+ * The basic data types
+ */
+typedef unsigned char		uint8;  /*  8 bits */
+typedef unsigned short int	uint16; /* 16 bits */
+typedef unsigned long int	uint32; /* 32 bits */
+
+typedef char			int8;   /*  8 bits */
+typedef short int	        int16;  /* 16 bits */
+typedef int		        int32;  /* 32 bits */
+
+typedef volatile int8		vint8;  /*  8 bits */
+typedef volatile int16		vint16; /* 16 bits */
+typedef volatile int32		vint32; /* 32 bits */
+
+typedef volatile uint8		vuint8;  /*  8 bits */
+typedef volatile uint16		vuint16; /* 16 bits */
+typedef volatile uint32		vuint32; /* 32 bits */
+
+// function prototype for main function
+int main(void);
+/***********************************************************************/
+// function prototypes for arm_cm0.c
+void stop (void);
+void wait (void);
+void write_vtor (int);
+
+/***********************************************************************/
+#endif	/* _CPU_ARM_CM4_H */
+
diff --git a/bsp/nv32f100x/lib/inc/common.h b/bsp/nv32f100x/lib/inc/common.h
new file mode 100644
index 0000000000..f943e6f8fc
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/common.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* @brief provide header files to be included by all project files. 
+*
+*******************************************************************************/
+
+
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+#define swap_bytes(ptrWord)   *ptrWord = (*ptrWord >>8) | (*ptrWord<<8)
+typedef unsigned long   dword;
+typedef unsigned short  word;
+
+/********************************************************************/
+
+/*
+ * Debug prints ON (#define) or OFF (#undef)
+ */
+
+#define DEBUG
+#define DEBUG_PRINT
+
+/* 
+ * Include the generic CPU header file 
+ */
+#include "arm_cm0.h"
+
+/* 
+ * Include the platform specific header file 
+ */
+#if (defined(NV32))
+ #include  "NV32_config.h"
+#elif (defined(FRDM_NV32M3))
+ #include  "NV32M3_config.h"
+#elif (defined(FRDM_NV32M4))
+ #include  "NV32M4_config.h"
+#else
+  #error "No valid board defined"
+#endif
+
+/* 
+ * Include the cpu specific header file 
+*/
+#if (defined(CPU_NV32))
+ #include "NV32.h"
+#elif (defined(CPU_NV32M3))
+ #include "NV32M3.h"
+#elif (defined(CPU_NV32M4))
+ #include "NV32M4.h"
+#else
+  #error "No valid CPU defined"
+#endif
+
+
+/* 
+ * Include any toolchain specfic header files 
+ */
+#if (defined(__MWERKS__))
+  #include "mwerks.h"
+#elif (defined(__DCC__))
+  #include "build/wrs/diab.h"
+#elif (defined(__ghs__))
+  #include "build/ghs/ghs.h"
+#elif (defined(__GNUC__))
+  #if (defined(IAR))
+    #include "build/gnu/gnu.h"
+  #endif
+#elif (defined(IAR))
+  #include "iar.h"
+#elif (defined(KEIL))
+  
+#else
+#warning "No toolchain specific header included"
+#endif
+
+/* 
+ * Include common utilities
+ */
+
+#define ASSERT(x)
+
+#if (defined(IAR))
+#include "intrinsics.h"
+#endif
+/********************************************************************/
+
+#endif /* _COMMON_H_ */
diff --git a/bsp/nv32f100x/lib/inc/core_cm0plus.h b/bsp/nv32f100x/lib/inc/core_cm0plus.h
new file mode 100644
index 0000000000..17e43984fc
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/core_cm0plus.h
@@ -0,0 +1,822 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nv32f100x/lib/inc/core_cmFunc.h b/bsp/nv32f100x/lib/inc/core_cmFunc.h
new file mode 100644
index 0000000000..01089f1333
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/core_cmFunc.h
@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/nv32f100x/lib/inc/core_cmInstr.h b/bsp/nv32f100x/lib/inc/core_cmInstr.h
new file mode 100644
index 0000000000..d14110b2ab
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/core_cmInstr.h
@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/nv32f100x/lib/inc/core_cmSimd.h b/bsp/nv32f100x/lib/inc/core_cmSimd.h
new file mode 100644
index 0000000000..ee58eee56d
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/bsp/nv32f100x/lib/inc/crc.h b/bsp/nv32f100x/lib/inc/crc.h
new file mode 100644
index 0000000000..64824624c5
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/crc.h
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* @brief    Cyclic redundancy check (CRC) header file. 
+*
+******************************************************************************/
+#ifndef CRC_H_
+#define CRC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+
+/******************************************************************************
+* CRC control bit definition
+*
+*//*! @addtogroup crc_controlbit
+* @{
+*******************************************************************************/
+
+/*!
+ * @brief CRC control register bit definition.
+ *
+ */
+
+#define CRC_WIDTH_16BIT                 0	/*!< select CRC16 protocol */   
+#define CRC_WIDTH_32BIT                 1	/*!< select CRC32 protocol */ 
+#define CRC_DATA_SEED                   1	/*!< Write CRC Data Register are seed */  
+#define CRC_DATA_DATA                   0	/*!< Write CRC Data Register are data */ 
+#define CRC_READ_COMPLETE               1	/*!< Invert or complement read CRC Data register */ 
+#define CRC_READ_NONE                   0	/*!< No XOR on reading */ 
+#define CRC_READ_TRANSPOSE_NONE         0	/*!< No transposition in read */ 
+#define CRC_READ_TRANSPOSE_BIT          1	/*!< only bits in bytes are transposed in read */
+#define CRC_READ_TRANSPOSE_ALL          2	/*!< both bits in bytes and bytes are transposed in read */
+#define CRC_READ_TRANSPOSE_BYTE         3	/*!< only bytes are transposed in read */
+#define CRC_WRITE_TRANSPOSE_NONE        0	/*!< No transposition write */
+#define CRC_WRITE_TRANSPOSE_BIT         1	/*!< only bits in bytes are transposed in write */ 
+#define CRC_WRITE_TRANSPOSE_ALL         2	/*!< both bits in bytes and bytes are transposed in write */
+#define CRC_WRITE_TRANSPOSE_BYTE        3	/*!< only bytes are transposed in write */
+
+/*! @} End of crc_controlbit                                                */
+
+     
+/******************************************************************************
+* Types
+******************************************************************************/
+/* CRC configuration structure 
+ */  
+/******************************************************************************
+* CRC Configuration Structure type.
+*
+*//*! @addtogroup crc_config_type
+* @{
+*******************************************************************************/ 
+/*!
+ * @brief CRC Configuration Structure.
+ *
+ */
+
+typedef struct
+{          
+    uint8_t bWidth                  : 1;    /*!< 1: 32-bit CRC protocol , 0: 16-bit CRC protocol */
+    uint8_t bDataType               : 1;    /*!< 1: write seed , 0: write data */
+    uint8_t bFinalXOR               : 1;    /*!< 1: Invert or complement read , 0: No XOR on reading */
+    uint8_t bRESERVED               : 1;    /*!< reserved bit */  
+    uint8_t bTransposeReadType      : 2;    /*!< type of transpose For read, see reference manual */
+    uint8_t bTransposeWriteType     : 2;    /*!< type of transpose For write, see reference manual */      
+    uint32_t u32PolyData               ;    /*!< 32bit or 16-biy poly data */           
+} CRC_ConfigType, *CRC_ConfigPtr  ; 
+/*! @} End of crc_config_type                                                */
+
+           
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* CRC API list
+*
+*//*! @addtogroup crc_api_list
+* @{
+*******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void        CRC_Init(CRC_ConfigType *pConfig);
+uint32_t    CRC_Cal16(uint32_t u32Seed, uint8_t *msg, uint32_t u32SizeBytes);
+uint32_t    CRC_Cal32(uint32_t u32Seed, uint8_t *msg, uint32_t u32SizeBytes);
+void        CRC_DeInit(void);
+/*! @} End of crc_api_list                                                   */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* CRC_H_ */
+
+
+
diff --git a/bsp/nv32f100x/lib/inc/eeprom.h b/bsp/nv32f100x/lib/inc/eeprom.h
new file mode 100644
index 0000000000..711aeda089
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/eeprom.h
@@ -0,0 +1,28 @@
+#ifndef EEPROM_H_
+#define EEPROM_H_
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+#include "common.h"
+
+#define EERPOM_SIZE	1024		// in bytes
+#define EEPROM_START_ADR 0x00401000
+#define EEPROM_ERR_SUCCESS 0x01
+#define EEPROM_ADR_OverFlow 0x02
+#define EEPROM_ERR_INVALID_PARAM 0x04
+#define EEPROM_BLANK 0xffffffff
+#define EEPROM_SECTOR_MASK 0x00401200
+#define EEPROM_ARRAY_ADR_MASK 0x1ff
+
+
+uint16_t Adress_Js(uint32_t adr);
+uint16_t EEPROM_Erase(uint32_t adr);
+uint32_t EEPROM_Read(uint32_t adr);
+uint8_t EEPROM_ReadByte(uint32_t adr);
+
+
+uint16_t EEPROM_Write(uint32_t adr, uint32_t Data);
+uint16_t EEPROM_WriteByte(uint32_t adr, uint8_t Data);
+uint16_t EERPOM_Writeup4byte(uint32_t adr, uint8_t *pData,uint32_t length);
+#endif
diff --git a/bsp/nv32f100x/lib/inc/etm.h b/bsp/nv32f100x/lib/inc/etm.h
new file mode 100644
index 0000000000..4800c4fa99
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/etm.h
@@ -0,0 +1,1166 @@
+/******************************************************************************
+* @brief header file for ETM. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing ETM
+******************************************************************************/
+#ifndef ETM_H_
+#define ETM_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+* ETM return status definition
+*
+*//*! @addtogroup ETM_returnstatus
+* @{
+*******************************************************************************/
+#define ETM_ERR_SUCCESS         0               /*!< return ok */
+#define ETM_ERR_INVALID_PARAM   1               /*!< return invalid parameter */
+/*! @} End of ETM_returnstatus                                                */
+
+
+/******************************************************************************
+* ETM channel number definition
+*
+*//*! @addtogroup ETM_channelnumber
+* @{
+*******************************************************************************/
+#define ETM_CHANNEL_CHANNEL0    0               /*!< channel 0 */
+#define ETM_CHANNEL_CHANNEL1    1               /*!< channel 1 */
+#define ETM_CHANNEL_CHANNEL2    2               /*!< channel 2 */
+#define ETM_CHANNEL_CHANNEL3    3               /*!< channel 3 */
+#define ETM_CHANNEL_CHANNEL4    4               /*!< channel 4 */
+#define ETM_CHANNEL_CHANNEL5    5               /*!< channel 5 */
+
+#define ETM_CHANNELPAIR0        0               /*!< channel pair 0:ch0 & ch1 */
+#define ETM_CHANNELPAIR1        2               /*!< channel pair 1:ch2 & ch3 */
+#define ETM_CHANNELPAIR2        4               /*!< channel pair 2:ch4 & ch5 */
+
+/*! @} End of ETM_channelnumber                                               */
+
+/******************************************************************************
+* ETM pwm mode definition
+*
+*//*! @addtogroup ETM_pwmmode
+* @{
+*******************************************************************************/
+#define ETM_PWMMODE_EDGEALLIGNED      1          /*!< EPWM */
+#define ETM_PWMMODE_CENTERALLIGNED    2          /*!< CPWM */
+#define ETM_PWMMODE_COMBINE           3          /*!< Combine PWM */
+/*! @} End of ETM_pwmmode                                                     */
+
+/******************************************************************************
+* ETM init value definition
+*
+*//*! @addtogroup ETM_initvalue
+* @{
+*******************************************************************************/
+#define ETM_MOD_INIT	(20000-1)                /*!< MOD inite value */
+#define ETM_C0V_INIT	1000                     /*!< C0V inite value */
+#define ETM_C1V_INIT	1000                     /*!< C1V inite value */
+#define ETM_C2V_INIT	1000                     /*!< C2V inite value */    
+#define ETM_C3V_INIT	1000                     /*!< C3V inite value */
+#define ETM_C4V_INIT	1000                     /*!< C4V inite value */
+#define ETM_C5V_INIT	1000                     /*!< C5V inite value */
+/*! @} End of ETM_initvalue                                                   */
+
+/******************************************************************************
+* ETM combine feature definition
+*
+*//*! @addtogroup ETM_combinefeature
+* @{
+*******************************************************************************/
+#define ETM_COMBINE_FAULTEN_MASK  0x40       /*!< fault enable */
+#define ETM_COMBINE_SYNCEN_MASK   0x20       /*!< sync enable */
+#define ETM_COMBINE_DTEN_MASK     0x10       /*!< dead ETMe insertion enable */
+#define ETM_COMBINE_DECAP_MASK    0x08       /*!< dual capture status */
+#define ETM_COMBINE_DECAPEN_MASK  0x04       /*!< dual capture enable */
+#define ETM_COMBINE_COMP_MASK     0x02       /*!< complementary enable */
+#define ETM_COMBINE_COMBINE_MASK  0x01       /*!< combine enable */
+/*! @} End of ETM_combinefeature                                              */
+
+/******************************************************************************
+* ETM clock sources definition
+*
+*//*! @addtogroup ETM_clocksource
+* @{
+*******************************************************************************/
+#define ETM_CLOCK_NOCLOCK             0                 /*!< No Clock */
+#define ETM_CLOCK_SYSTEMCLOCK         1                 /*!< System clock/2 */
+#define ETM_CLOCK_FIXEDFREQCLOCK      2                 /*!< Fixed Freq Clock */
+#define ETM_CLOCK_EXTERNALCLOCK       3                 /*!< External Clock */
+
+/* clock prescale */
+#define ETM_CLOCK_PS_DIV1             0                 /*!< DIV 1 */
+#define ETM_CLOCK_PS_DIV2             1                 /*!< DIV 2 */
+#define ETM_CLOCK_PS_DIV4             2                 /*!< DIV 4 */
+#define ETM_CLOCK_PS_DIV8             3                 /*!< DIV 8 */
+#define ETM_CLOCK_PS_DIV16            4                 /*!< DIV 16 */
+#define ETM_CLOCK_PS_DIV32            5                 /*!< DIV 32 */
+#define ETM_CLOCK_PS_DIV64            6                 /*!< DIV 64 */
+#define ETM_CLOCK_PS_DIV128           7                 /*!< DIV 128 */
+/*! @} End of ETM_clocksource                                                 */
+
+/******************************************************************************
+* ETM dead ETMe clock prescale definition
+*
+*//*! @addtogroup ETM_deadETMeprescale
+* @{
+*******************************************************************************/
+/*  */
+#define ETM_DEADETME_DTPS_DIV1        0                 /*!< DIV 1 */
+#define ETM_DEADETME_DTPS_DIV4        2                 /*!< DIV 4 */
+#define ETM_DEADETME_DTPS_DIV16       3                 /*!< DIV 16 */
+/*! @} End of ETM_deadETMeprescale                                            */
+
+/******************************************************************************
+* ETM output mode definition
+*
+*//*! @addtogroup ETM_outputmode
+* @{
+*******************************************************************************/
+/* output mode */
+#define ETM_OUTPUT_TOGGLE   1                    /*!< toggle output on match */
+#define ETM_OUTPUT_CLEAR    2                    /*!< clear output on match */
+#define ETM_OUTPUT_SET      3                    /*!< set output on match */
+/*! @} End of ETM_outputmode                                                  */
+
+/******************************************************************************
+* ETM input capture edge definition
+*
+*//*! @addtogroup ETM_inputcaptureedge
+* @{
+*******************************************************************************/
+/* mode edge select*/
+#define ETM_INPUTCAPTURE_RISINGEDGE           1     /*!< rising edge */
+#define ETM_INPUTCAPTURE_FALLINGEDGE          2     /*!< falling edge */
+#define ETM_INPUTCAPTURE_BOTHEDGE             3     /*!< both edge */
+
+#define ETM_INPUTCAPTURE_DUALEDGE_NOEDGE      0     /*!< none */
+#define ETM_INPUTCAPTURE_DUALEDGE_RISINGEDGE  1     /*!< rising edge*/
+#define ETM_INPUTCAPTURE_DUALEDGE_FALLInGEDGE 2     /*!< falling edge*/
+#define ETM_INPUTCAPTURE_DUALEDGE_BOTHEDGE    3     /*!< both edge */
+/*! @} End of ETM_inputcaptureedge                                            */
+
+/******************************************************************************
+* ETM dual edge capture mode definition
+*
+*//*! @addtogroup ETM_dualcapturemode
+* @{
+*******************************************************************************/
+#define ETM_INPUTCAPTURE_DUALEDGE_ONESHOT     4  /*!< dual edge one shot mode*/ 
+#define ETM_INPUTCAPTURE_DUALEDGE_CONTINUOUS  5  /*!< dual edge continuouse mode*/
+/*! @} End of ETM_dualcapturemode                                            */
+
+/******************************************************************************
+* ETM PWM edge definition
+*
+*//*! @addtogroup ETM_pwmedge
+* @{
+*******************************************************************************/
+#define ETM_PWM_HIGHTRUEPULSE        1            /*!< high true pulses */
+#define ETM_PWM_LOWTRUEPULSE         2            /*!< low true pulses */
+/*! @} End of ETM_pwmedge                                                     */
+
+/******************************************************************************
+* ETM sync trigger source definition
+*
+*//*! @addtogroup ETM_syncsource
+* @{
+*******************************************************************************/
+#define ETM_SYNC_TRIGGER_SOFTWARE    1        /*!< Software synchronization */
+#define ETM_SYNC_TRIGGER_TRIGGER2    2        /*!< Tigger2 synchronization, SIM_SOPT[ETMSYNC] */
+#define ETM_SYNC_TRIGGER_TRIGGER1    3        /*!< Tigger1 synchronization, ETM0CH0 */
+#define ETM_SYNC_TRIGGER_TRIGGER0    4        /*!< Tigger0 synchronization, ACMP0 */
+/*! @} End of ETM_syncsource                                                  */
+
+/******************************************************************************
+* ETM SW output control definition
+*
+*//*! @addtogroup ETM_swoutputcontrol
+* @{
+*******************************************************************************/ 
+#define ETM_SWOCTRL_HIGH    1                /*!< software output high */
+#define ETM_SWOCTRL_LOW     0                /*!< software output low */
+/*! @} End of ETM_swoutputcontrol                                             */
+
+/******************************************************************************
+* ETM  polarity definition
+*
+*//*! @addtogroup ETM_polarity
+* @{
+*******************************************************************************/
+#define ETM_POLARITY_HIGHACTIVE     0        /*!< active high */
+#define ETM_POLARITY_LOWACTIVE      1        /*!< active low */
+/*! @} End of ETM_polarity                                                    */
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+/*! @brief ETM_CALLBACK function declaration                                  */
+typedef void (*ETM_CallbackPtr)(void);
+/*! @} End of ETM_callback                                                    */
+
+/******************************************************************************
+* ETM configure struct.
+*
+*//*! @addtogroup ETM_configsturct
+* @{
+*******************************************************************************/
+/*!
+* @brief ETM configure struct.
+*
+*/
+
+typedef struct
+{
+  uint8_t   clk_source;       /*!< clock source */
+  uint8_t   prescaler;        /*!< clock prescaler */
+  uint8_t   sc;               /*!< status and control */
+  uint16_t  modulo;           /*!< counter mod */
+  uint16_t  cnt;              /*!< counter value */
+  uint16_t  cntin;            /*!< counter inite */
+  uint8_t   mode;             /*!< features mode selction */
+  uint8_t   sync;             /*!< synchronization */
+  uint8_t   outinit;          /*!< initial state for channels output  */
+  uint8_t   outmask;          /*!< output mask */
+  uint32_t  combine;          /*!< function for linked channels */
+  uint16_t  deadETMe;         /*!< dead ETMe insertion control */
+  uint8_t   exttrig;          /*!< external trigger */
+  uint8_t   pol;              /*!< channels polarity */
+  uint16_t  filter;           /*!< input filter control */
+  uint8_t   fms;              /*!< fault mode status */
+  uint16_t  fltctrl;          /*!< fault control */
+  uint8_t   fltpol;           /*!< fault input polarity */
+  uint16_t  conf;             /*!< ETM configuration */
+  uint32_t  synconf;          /*!< synchronization configuration*/
+  uint8_t   invctrl;          /*!< inverting control */
+  uint16_t  swoctrl;          /*!< software output control */
+  uint16_t  pwmload;          /*!< pwm load control */
+} ETM_ConfigType, *ETM_ConfigPtr;
+/*! @} End of ETM_configsturct                                                */
+
+/******************************************************************************
+* ETM channel configure struct.
+*
+*//*! @addtogroup ETM_chconfigsturct
+* @{
+*******************************************************************************/
+/*!
+* @brief ETM channel configure struct.
+*
+*/
+typedef struct
+{
+  uint8_t         u8CnSC;                  /*!< ETM channel status and control */
+  uint16_t        u16CnV;                  /*!< ETM channel value control */
+  union
+  {
+    uint32_t      u32dw;
+    struct 
+    {
+      uint32_t    bMode         : 3;        /*!< flexETMer mode: GPIO, INPUT_CAPTURE, OUTPUT_COMPARE, EDGE_ALIGNED_PWM, CENTER_ALIGNED_PWM,
+                                             * COMBINE_PWM, DUAL_EDGE_CAPTURE 
+                                             */
+      uint32_t    bEdge         : 2;        /*!< edge select */
+      uint32_t    bOutCmp       : 2;        /*!< toggle, clear, set */
+      uint32_t    bPWMPol       : 1;        /*!< high-true pulse, low-true pulses */
+      uint32_t    bDualCapMode  : 1;        /*!< dual edge capture mode: one-shot, continuous mode */
+      uint32_t    bCHIE         : 1;        /*!< enable channel interrupt */
+    }bits;
+  }ctrl;                                    /*!< ETM channel feature control */
+} ETM_ChParamsType;
+
+/*! @} End of ETM_chconfigsturct                                              */
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/*!
+ * inline functions
+ */
+/******************************************************************************
+* ETM inline functions
+*
+*//*! @addtogroup ETM_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief  enable the over flow interrupt.
+*        
+* @param[in]    pETM          pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_DisableOverflowInt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_EnableOverflowInt(ETM_Type *pETM)
+{
+    if(pETM->SC & ETM_SC_TOF_MASK)
+    {
+        pETM->SC &= ~ETM_SC_TOF_MASK;
+    }
+    pETM->SC |= ETM_SC_TOIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the over flow interrupt.
+*        
+* @param[in]    pETM          pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see ETM_EnableOverflowInt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_DisableOverflowInt(ETM_Type *pETM)
+{
+    pETM->SC &= ~ETM_SC_TOIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable the channel interrupt.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel  channel number.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_DisableChannelInt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_EnableChannelInt(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    pETM->CONTROLS[u8ETM_Channel].CnSC |= ETM_CnSC_CHIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the channel interrupt.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel  channel number.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_EnableChannelInt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_DisableChannelInt(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    pETM->CONTROLS[u8ETM_Channel].CnSC &= ~ETM_CnSC_CHIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  get the over flow flag.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_ClrOverFlowFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetOverFlowFlag(ETM_Type *pETM)
+{
+    return (pETM->SC & ETM_SC_TOF_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the over flow flag.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetOverFlowFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_ClrOverFlowFlag(ETM_Type *pETM)
+{
+    if(pETM->SC & ETM_SC_TOF_MASK)
+    {
+         pETM->SC &= ~ETM_SC_TOF_MASK;
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  get the channel flag.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel  channel number.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_ClrChannelFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetChannelFlag(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    return (pETM->CONTROLS[u8ETM_Channel].CnSC & ETM_CnSC_CHF_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the channel flag.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetChannelFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_ClrChannelFlag(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    pETM->CONTROLS[u8ETM_Channel].CnSC &= ~ETM_CnSC_CHF_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief enable the write protection function.Write protected bits cannot be written. 
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_WriteProtectionDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_WriteProtectionEnable(ETM_Type *pETM)
+{
+    pETM->FMS |= ETM_FMS_WPEN_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable the write protection function.Write protected bits can be written. 
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_WriteProtectionDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_WriteProtectionDisable(ETM_Type *pETM)
+{
+    if (pETM->FMS & ETM_FMS_WPEN_MASK)
+    {
+        pETM->MODE |= ETM_MODE_WPDIS_MASK;
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set ETMEN bit to enable ETM-specific register.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetETMBasic.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetETMEnhanced(ETM_Type *pETM)
+{
+    if(pETM->MODE & ETM_MODE_WPDIS_MASK)   /* if not write protected */
+    {
+        pETM->MODE |= ETM_MODE_ETMEN_MASK;
+    }
+    else
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->MODE |= ETM_MODE_ETMEN_MASK;
+        ETM_WriteProtectionEnable(pETM);
+    }    
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear ETMEN bit to disable ETM-specific registers, only TPM-compatible
+*         registers can be used.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetETMEnhanced.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetETMBasic(ETM_Type *pETM)
+{
+    if(pETM->MODE & ETM_MODE_WPDIS_MASK)    /* if not write protected */
+    {
+        pETM->MODE &= ~ETM_MODE_ETMEN_MASK;
+    }
+    else
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->MODE &= ~ETM_MODE_ETMEN_MASK;
+        ETM_WriteProtectionEnable(pETM);
+    }  
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the ETM mod value.
+*              
+* @param[in]    pETM           pointer to one of three ETM base register address.
+* @param[in]    u16ModValue    the mod value required to set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetChannelValue.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetModValue(ETM_Type *pETM, uint16_t u16ModValue)
+{
+    pETM->CNT = 0;
+    pETM->MOD = u16ModValue;
+    if(ETM2 == pETM)
+    {
+        if(pETM->MODE & ETM_MODE_ETMEN_MASK)
+        {
+            pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK;
+        }
+        else
+        {
+        }
+    }
+    else
+    {
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the ETM channel value.
+*                
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u16ChannelValue  the CnV value required to set.
+* @param[in]    u8ETM_Channel    ETM channel number.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetModValue.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetChannelValue(ETM_Type *pETM, uint8_t u8ETM_Channel, uint16_t u16ChannelValue)
+{
+    pETM->CONTROLS[u8ETM_Channel].CnV = u16ChannelValue;
+    if(ETM2 == pETM)
+    {
+        if(pETM->MODE & ETM_MODE_ETMEN_MASK)
+        {
+            if(u8ETM_Channel < 2)
+            {
+                pETM->COMBINE |= ETM_COMBINE_SYNCEN0_MASK;  /* enable the sync function */
+            }
+            else if (u8ETM_Channel < 4)
+            {
+                pETM->COMBINE |= ETM_COMBINE_SYNCEN1_MASK;
+            }
+            else
+            {
+                pETM->COMBINE |= ETM_COMBINE_SYNCEN2_MASK;
+            }
+            pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK;  
+        }
+        else
+        {
+        }
+    }
+    else
+    {
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the ETM channel value.
+*               
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u16CounterValue   the CNTIN value required to set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see ETM_SetModValue.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetCounterInitValue(ETM_Type *pETM, uint16_t u16CounterValue)
+{
+    pETM->CNTIN = u16CounterValue;
+    if(pETM->MODE & ETM_MODE_ETMEN_MASK)
+    {
+        pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK;
+    }
+    else
+    {
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the channel output mask value, ETM2 used only.
+*               
+* @param[in]    pETM            pointer to one of three ETM base register address.
+* @param[in]    u16ChMask       the CNTIN value required to set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see ETM_UnMaskChannels.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_MaskChannels(ETM_Type *pETM, uint16_t u16ChMask)
+{
+     pETM->OUTMASK |= u16ChMask;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the channel output mask value, ETM2 used only.
+*               
+* @param[in]    pETM            pointer to one of three ETM base register address.
+* @param[in]    u16ChMask       the CNTIN value required to set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see ETM_MaskChannels.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_UnMaskChannels(ETM_Type *pETM, uint16_t u16ChMask)
+{
+     pETM->OUTMASK &= ~u16ChMask;
+}
+
+/*********************************************************************************//*!
+*
+* @brief set ETM channels polarity.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    u8ChsPolValue         the channels value need to be set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetChannelsPolarity.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_SetChannelsPolarity(ETM_Type *pETM, uint8_t u8ChsPolValue)
+{
+    pETM->POL = u8ChsPolValue;
+}
+
+/*********************************************************************************//*!
+*
+* @brief get ETM channels polarity.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+*
+* @return uint8_t the channels polarity.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetChannelsPolarity.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetChannelsPolarity(ETM_Type *pETM)
+{
+    return (pETM->POL);
+}
+
+/*********************************************************************************//*!
+*
+* @brief select the enhanced SYNC mode.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_DisableEnhancedSYNCMode.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_EnableEnhancedSYNCMode(ETM_Type *pETM)
+{
+    pETM->SYNCONF   |= ETM_SYNCONF_SYNCMODE_MASK;   /* recommend enhanced sync mode */
+}
+
+/*********************************************************************************//*!
+*
+* @brief select the legacy SYNC mode.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_EnableEnhancedSYNCMode.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_DisableEnhancedSYNCMode(ETM_Type *pETM)
+{
+    pETM->SYNCONF   &= ~ETM_SYNCONF_SYNCMODE_MASK;   /* recommend enhanced sync mode */
+}
+
+/*********************************************************************************//*!
+*
+* @brief set the external trigger source.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8TirggerSource   initial trigger or CHn(0~5)trigger
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetExternalTriggerFlag.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_SetExternalTrigger(ETM_Type *pETM, uint8_t u8TirggerSource)
+{
+    pETM->EXTTRIG   = u8TirggerSource;
+}
+
+/*********************************************************************************//*!
+*
+* @brief get the external trigger flag.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return ex trigger flag.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetExternalTrigger.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetExternalTriggerFlag(ETM_Type *pETM)
+{
+    return (pETM->EXTTRIG & ETM_EXTTRIG_TRIGF_MASK);
+}
+
+/*********************************************************************************//*!
+*
+* @brief set LDOK bit.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetLoadMatchChannel.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_SetLoadEnable(ETM_Type *pETM)
+{
+    pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief set the channel in the matching process.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8Matchchannel    the channel in the matching process.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetLoadEnable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_SetLoadMatchChannel(ETM_Type *pETM, uint8_t u8Matchchannel)
+{
+    pETM->PWMLOAD |= u8Matchchannel;
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable the channel input capture filter.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel     the channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_InputCaptureFilterSet.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_InputCaptureFilterClr(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    pETM->FILTER &= ~(0x000F << (u8ETM_Channel << 2));
+}
+
+/*********************************************************************************//*!
+*
+* @brief set the channel input capture filter value.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel     the channel number: 0~3.
+* @param[in]    u8FilterValue     fliter cycles:1~15, 0: disable channel filter.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_InputCaptureFilterClr.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_InputCaptureFilterSet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8FilterValue)
+{
+    if (u8FilterValue)
+    {
+        pETM->FILTER |= (u8FilterValue << (u8ETM_Channel << 2));
+    }
+    else
+    {
+        ETM_InputCaptureFilterClr(pETM, u8ETM_Channel);
+    }
+}
+
+
+/*********************************************************************************//*!
+*
+* @brief enable the fault input pin.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        the fault input channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinEnable(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    if (pETM->MODE & ETM_MODE_WPDIS_MASK) /* if not protected */
+    {
+        pETM->FLTCTRL |= (1 << u8FaultPin);
+    }
+    else                                  /* if protected */ 
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->FLTCTRL |= (1 << u8FaultPin);
+        ETM_WriteProtectionEnable(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable the fault input pin.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        the fault input channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinEnable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinDisable(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    if (pETM->MODE & ETM_MODE_WPDIS_MASK) /* if not protected */
+    {
+        pETM->FLTCTRL &= ~(1 << u8FaultPin);
+    }
+    else                                  /* if protected */ 
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->FLTCTRL &= ~(1 << u8FaultPin);
+        ETM_WriteProtectionEnable(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief enable the fault pin filter.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        the fault input channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinFilterDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinFilterEnable(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    if (pETM->MODE & ETM_MODE_WPDIS_MASK) /* if not protected */
+    {
+        pETM->FLTCTRL |= (0x10 << u8FaultPin);
+    }
+    else                                  /* if protected */ 
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->FLTCTRL |= (0x10 << u8FaultPin);
+        ETM_WriteProtectionEnable(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable the fault pin filter.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        the fault input channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinFilterDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinFilterDisable(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    if (pETM->MODE & ETM_MODE_WPDIS_MASK) /* if not protected */
+    {
+        pETM->FLTCTRL &= ~(0x10 << u8FaultPin);
+    }
+    else                                  /* if protected */ 
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->FLTCTRL &= ~(0x10 << u8FaultPin);
+        ETM_WriteProtectionEnable(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable all the fault pins filter together. 
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinFilterSet.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinFilterCDisableAll(ETM_Type *pETM)
+{
+    pETM->FLTCTRL &= ~ETM_FLTCTRL_FFVAL_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief set the fault filter value. All channels share the same filter value.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FilterValue     the fault input filter value: 1~15, 0 disable the filter.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinFilterCDisableAll.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinFilterSet(ETM_Type *pETM, uint8_t u8FilterValue)
+{
+    if (u8FilterValue)
+    {
+        pETM->FLTCTRL |= ETM_FLTCTRL_FFVAL(u8FilterValue);
+    }
+    else
+    {
+        ETM_FaultPinFilterCDisableAll(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief get the logic OR of all the fault detection flags
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetFaultDetectionFlag.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetFaultDetectionLogicORFlag(ETM_Type *pETM)
+{
+    return (pETM->FMS & ETM_FMS_FAULTF_MASK);
+}
+
+/*********************************************************************************//*!
+*
+* @brief get the fault detection flag
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        fault input pin number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetFaultDetectionLogicORFlag.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetFaultDetectionFlag(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    return (pETM->FMS & (1 << u8FaultPin));
+}
+
+/*********************************************************************************//*!
+*
+* @brief get the logic OR value of the fault inputs
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetFaultInputsLogicORValue(ETM_Type *pETM)
+{
+    return (pETM->FMS & ETM_FMS_FAULTIN_MASK);
+}
+
+/*! @} End of ETM_api_list                                                    */
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+void ETM_ClockSet(ETM_Type *pETM, uint8_t u8ClockSource, uint8_t u8ClockPrescale);
+void ETM_PWMInit(ETM_Type *pETM, uint8_t u8PWMModeSelect, uint8_t u8PWMEdgeSelect);
+void ETM_InputCaptureInit(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8CaptureMode);
+void ETM_DualEdgeCaptureInit(ETM_Type *pETM, uint8_t u8ChannelPair, uint8_t u8CaptureMode, 
+                             uint8_t u8Channel_N_Edge, uint8_t u8Channel_Np1_Edge);
+void ETM_OutputCompareInit(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8CompareMode);
+void ETM_SoftwareSync(ETM_Type *pETM);
+void ETM_HardwareSync(ETM_Type *pETM, uint8_t u8TriggerN);
+void ETM_HardwareSyncCombine(ETM_Type *pETM, uint8_t u8TriggerMask);
+void ETM_GenerateTrig2(ETM_Type *pETM);
+void ETM_PWMDeadETMeSet(ETM_Type *pETM, uint8_t u8PrescalerValue, uint8_t u8DeadETMeValue);
+void ETM_OutputMaskSet(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_SWOutputControlSet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8ChannelValue);
+void ETM_SetDebugModeBehavior(ETM_Type *pETM, uint8_t u8DebugMode);
+void ETM_SetTOFFrequency(ETM_Type *pETM, uint8_t u8TOFNUM);
+void ETM_PolaritySet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8ActiveValue);
+void ETM_InvertChannel(ETM_Type *pETM, uint8_t u8ChannelPair);
+void ETM_Init(ETM_Type *pETM, ETM_ConfigType *pConfig);
+void ETM_DeInit(ETM_Type *pETM);
+void ETM_ChannelInit(ETM_Type *pETM, uint8_t u8ETM_Channel, ETM_ChParamsType *pETM_ChParams);
+void ETM_SetDutyCycleCombine(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8DutyCycle);
+void ETM_SetCallback(ETM_Type *pETM, ETM_CallbackPtr pfnCallback);
+void  ETM_SyncConfigActivate(ETM_Type *pETM, uint32_t u32ConfigValue);
+void ETM_SyncConfigDeactivate(ETM_Type * pETM, uint32_t u32ConfigValue);
+uint8_t ETM_GetFaultDetectionLogicORFlag(ETM_Type *pETM);
+uint8_t ETM_GetFaultDetectionFlag(ETM_Type *pETM, uint8_t u8FaultPin);
+uint8_t ETM_GetFaultInputsLogicORValue(ETM_Type *pETM);
+void ETM_WriteProtectionEnable(ETM_Type *pETM);
+void ETM_WriteProtectionDisable(ETM_Type *pETM);
+void ETM_FaultPinFilterCDisableAll(ETM_Type *pETM);
+void ETM_FaultPinFilterSet(ETM_Type *pETM, uint8_t u8FilterValue);
+void ETM_FaultPinFilterDisable(ETM_Type *pETM, uint8_t u8FaultPin);
+void ETM_FaultPinFilterEnable(ETM_Type *pETM, uint8_t u8FaultPin);
+void ETM_FaultPinEnable(ETM_Type *pETM, uint8_t u8FaultPin);
+void ETM_FaultPinDisable(ETM_Type *pETM, uint8_t u8FaultPin);
+void ETM_InputCaptureFilterClr(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_InputCaptureFilterSet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8FilterValue);
+void ETM_SetLoadMatchChannel(ETM_Type *pETM, uint8_t u8Matchchannel);
+void ETM_SetLoadEnable(ETM_Type *pETM);
+uint8_t ETM_GetExternalTriggerFlag(ETM_Type *pETM);
+void ETM_DisableEnhancedSYNCMode(ETM_Type *pETM);
+void ETM_EnableEnhancedSYNCMode(ETM_Type *pETM);
+uint8_t ETM_GetChannelsPolarity(ETM_Type *pETM);
+void ETM_SetChannelsPolarity(ETM_Type *pETM, uint8_t u8ChsPolValue);
+void ETM_UnMaskChannels(ETM_Type *pETM, uint16_t u16ChMask);
+void ETM_MaskChannels(ETM_Type *pETM, uint16_t u16ChMask);
+void ETM_SetCounterInitValue(ETM_Type *pETM, uint16_t u16CounterValue);
+void ETM_SetChannelValue(ETM_Type *pETM, uint8_t u8ETM_Channel, uint16_t u16ChannelValue);
+void ETM_SetModValue(ETM_Type *pETM, uint16_t u16ModValue);
+void ETM_SetETMBasic(ETM_Type *pETM);
+void ETM_SetETMEnhanced(ETM_Type *pETM);
+void ETM_ClrChannelFlag(ETM_Type *pETM, uint8_t u8ETM_Channel);
+uint8_t ETM_GetChannelFlag(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_ClrOverFlowFlag(ETM_Type *pETM);
+uint8_t ETM_GetOverFlowFlag(ETM_Type *pETM);
+void ETM_DisableChannelInt(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_EnableChannelInt(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_DisableOverflowInt(ETM_Type *pETM);
+void ETM_EnableOverflowInt(ETM_Type *pETM);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ETM_H_ */
diff --git a/bsp/nv32f100x/lib/inc/flash.h b/bsp/nv32f100x/lib/inc/flash.h
new file mode 100644
index 0000000000..9d6c52b797
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/flash.h
@@ -0,0 +1,118 @@
+/******************************************************************************
+******************************************************************************
+*
+* @file flash.h
+*
+* @brief application entry point which performs application specific tasks. 
+*
+*******************************************************************************
+*
+* provide a demo for how to initialize the NV32, output messages via SCI, 
+* flash operations, etc.
+* NOTE:
+*	printf call may occupy a lot of memory (around 1924 bytes), so please
+*	consider your code size before using printf.
+******************************************************************************
+*
+* provide FLASH driver
+*
+******************************************************************************/
+
+
+
+#ifndef FLASH_H_
+#define FLASH_H_
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+#include "common.h"
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+/* Uncomment the following line to support programming flash while running code from flash */
+// #define FLASH_ENABLE_STALLING_FLASH_CONTROLLER
+
+#define ETMRH_FSTAT_MGSTAT0_MASK  (1)
+#define ETMRH_FSTAT_MGSTAT1_MASK  (1<<1)
+
+#define FLASH_SECTOR_SIZE	512		// in bytes
+
+/* Flash driver errors */
+#define FLASH_ERR_BASE				0x3000
+#define FLASH_ERR_SUCCESS			0
+#define FLASH_ERR_INVALID_PARAM		(FLASH_ERR_BASE+1)	// invalid parameter error code
+#define EEPROM_ERR_SINGLE_BIT_FAULT	(FLASH_ERR_BASE+2)	// EEPROM single bit fault error code
+#define EEPROM_ERR_DOUBLE_BIT_FAULT	(FLASH_ERR_BASE+4)	// EEPROM double bits fault error code
+#define FLASH_ERR_ACCESS			(FLASH_ERR_BASE+8)	// flash access error code
+#define FLASH_ERR_PROTECTION		(FLASH_ERR_BASE+0x10)	// flash protection error code
+#define FLASH_ERR_MGSTAT0			(FLASH_ERR_BASE+0x11)	// flash verification error code
+#define FLASH_ERR_MGSTAT1			(FLASH_ERR_BASE+0x12)	// flash non-correctable error code
+#define FLASH_ERR_INIT_CCIF			(FLASH_ERR_BASE+0x14)	// flash driver init error with CCIF = 1
+#define FLASH_ERR_INIT_FDIV			(FLASH_ERR_BASE+0x18)	// flash driver init error with wrong FDIV 
+
+/* Flash and EEPROM commands */
+
+
+#define FLASH_CMD_PROGRAM			0x20000000
+#define FLASH_CMD_CLEAR       0x00005000
+#define FLASH_CMD_ERASE_ALL   0x41000000
+#define FLASH_CMD_ERASE_SECTOR		0x40000000
+#define FLASH_FACTORY_KEY 0x0065fe9a
+
+#define EFM_DONE_MASK    0x00006000
+#define EFM_STATUS_DONE  0x00006000
+#define EFM_STATUS_READY 0x00002000
+
+#define FLASH_ACCERR_MASK 0x10
+
+#define M8(adr)  (*((volatile unsigned char  *) (adr)))
+#define M16(adr) (*((volatile unsigned short *) (adr)))
+#define M32(adr) (*((volatile unsigned long  *) (adr)))
+
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+typedef  uint16_t (*TFlash_Fun1)(uint32_t wNVMTargetAddress, uint8_t *pbData, uint8_t bByteCount);
+typedef  uint16_t (*TFlash_Fun2)(uint32_t wNVMTargetAddress, uint32_t dwData0, uint32_t dwData1);
+typedef  uint16_t (*TFlash_Fun3)(uint32_t wNVMTargetAddress, uint32_t dwData);
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+uint16_t Flash_Program(uint32_t wNVMTargetAddress, uint8_t *pData, uint16_t sizeBytes);
+uint16_t Flash_Program1LongWord(uint32_t wNVMTargetAddress, uint32_t dwData);
+uint16_t Flash_Program2LongWords(uint32_t wNVMTargetAddress, uint32_t dwData0, uint32_t dwData1);
+
+uint16_t Flash_EraseSector(uint32_t wNVMTargetAddress);
+
+uint16_t Flash_VerifyBackdoorKey(void);
+
+uint16_t NVM_EraseAll(void);
+
+uint16_t NVM_Unsecure(void);
+
+uint16_t Flash_Init(void);
+
+#ifdef IAR
+void __ramfunc EFM_LaunchCMD(uint32_t EFM_CMD);
+#else
+void EFM_LaunchCMD(uint32_t EFM_CMD);
+#endif
+
+
+void	Flash_CopyInRAM(void);
+void	Flash_CopyRouinte2RAM(char *func, uint16_t sizeFunc);
+/********************************************************************/
+
+#endif /* FLASH_H_ */
diff --git a/bsp/nv32f100x/lib/inc/gpio.h b/bsp/nv32f100x/lib/inc/gpio.h
new file mode 100644
index 0000000000..2fd7a3c323
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/gpio.h
@@ -0,0 +1,278 @@
+/******************************************************************************
+*
+* @brief provide commond GPIO utilities. 
+*
+*******************************************************************************/
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "common.h"
+#include "stdint.h"
+
+/******************************************************************************
+*define gpio pin name
+*
+*//*! @addtogroup gpio_pin_name_list
+* @{
+*******************************************************************************/
+typedef enum
+{
+    /* in GPIOA register */
+    GPIO_PTA0 = 0,              /*!< GPIO Pin PTA0 */
+    GPIO_PTA1,                  /*!< GPIO Pin PTA1 */
+    GPIO_PTA2,                  /*!< GPIO Pin PTA2 */
+    GPIO_PTA3,                  /*!< GPIO Pin PTA3 */
+    GPIO_PTA4,                  /*!< GPIO Pin PTA4 */
+    GPIO_PTA5,                  /*!< GPIO Pin PTA5 */
+    GPIO_PTA6,                  /*!< GPIO Pin PTA6 */
+    GPIO_PTA7,                  /*!< GPIO Pin PTA7 */
+    GPIO_PTB0,                  /*!< GPIO Pin PTB0 */
+    GPIO_PTB1,                  /*!< GPIO Pin PTB1 */
+    GPIO_PTB2,                  /*!< GPIO Pin PTB2 */
+    GPIO_PTB3,                  /*!< GPIO Pin PTB3 */
+    GPIO_PTB4,                  /*!< GPIO Pin PTB4 */
+    GPIO_PTB5,                  /*!< GPIO Pin PTB5 */
+    GPIO_PTB6,                  /*!< GPIO Pin PTB6 */
+    GPIO_PTB7,                  /*!< GPIO Pin PTB7 */
+    GPIO_PTC0,                  /*!< GPIO Pin PTC0 */
+    GPIO_PTC1,                  /*!< GPIO Pin PTC1 */
+    GPIO_PTC2,                  /*!< GPIO Pin PTC2 */
+    GPIO_PTC3,                  /*!< GPIO Pin PTC3 */
+    GPIO_PTC4,                  /*!< GPIO Pin PTC4 */
+    GPIO_PTC5,                  /*!< GPIO Pin PTC5 */
+    GPIO_PTC6,                  /*!< GPIO Pin PTC6 */
+    GPIO_PTC7,                  /*!< GPIO Pin PTC7 */
+    GPIO_PTD0,                  /*!< GPIO Pin PTD0 */
+    GPIO_PTD1,                  /*!< GPIO Pin PTD1 */
+    GPIO_PTD2,                  /*!< GPIO Pin PTD2 */
+    GPIO_PTD3,                  /*!< GPIO Pin PTD3 */
+    GPIO_PTD4,                  /*!< GPIO Pin PTD4 */
+    GPIO_PTD5,                  /*!< GPIO Pin PTD5 */
+    GPIO_PTD6,                  /*!< GPIO Pin PTD6 */
+    GPIO_PTD7,                  /*!< GPIO Pin PTD7 */
+    /* in GPIOB register */
+    GPIO_PTE0,                  /*!< GPIO Pin PTE0 */
+    GPIO_PTE1,                  /*!< GPIO Pin PTE1 */
+    GPIO_PTE2,                  /*!< GPIO Pin PTE2 */
+    GPIO_PTE3,                  /*!< GPIO Pin PTE3 */
+    GPIO_PTE4,                  /*!< GPIO Pin PTE4 */
+    GPIO_PTE5,                  /*!< GPIO Pin PTE5 */
+    GPIO_PTE6,                  /*!< GPIO Pin PTE6 */
+    GPIO_PTE7,                  /*!< GPIO Pin PTE7 */
+    GPIO_PTF0,                  /*!< GPIO Pin PTF0 */
+    GPIO_PTF1,                  /*!< GPIO Pin PTF1 */
+    GPIO_PTF2,                  /*!< GPIO Pin PTF2 */
+    GPIO_PTF3,                  /*!< GPIO Pin PTF3 */
+    GPIO_PTF4,                  /*!< GPIO Pin PTF4 */
+    GPIO_PTF5,                  /*!< GPIO Pin PTF5 */
+    GPIO_PTF6,                  /*!< GPIO Pin PTF6 */
+    GPIO_PTF7,                  /*!< GPIO Pin PTF7 */
+    GPIO_PTG0,                  /*!< GPIO Pin PTG0 */
+    GPIO_PTG1,                  /*!< GPIO Pin PTG1 */
+    GPIO_PTG2,                  /*!< GPIO Pin PTG2 */
+    GPIO_PTG3,                  /*!< GPIO Pin PTG3 */
+    GPIO_PTG4,                  /*!< GPIO Pin PTG4 */
+    GPIO_PTG5,                  /*!< GPIO Pin PTG5 */
+    GPIO_PTG6,                  /*!< GPIO Pin PTG6 */
+    GPIO_PTG7,                  /*!< GPIO Pin PTG7 */
+    GPIO_PTH0,                  /*!< GPIO Pin PTH0 */
+    GPIO_PTH1,                  /*!< GPIO Pin PTH1 */
+    GPIO_PTH2,                  /*!< GPIO Pin PTH2 */
+    GPIO_PTH3,                  /*!< GPIO Pin PTH3 */
+    GPIO_PTH4,                  /*!< GPIO Pin PTH4 */
+    GPIO_PTH5,                  /*!< GPIO Pin PTH5 */
+    GPIO_PTH6,                  /*!< GPIO Pin PTH6 */
+    GPIO_PTH7,                  /*!< GPIO Pin PTH7 */
+    /* the following pins are not in NV322 */
+    GPIO_PTI0,                  /*!< GPIO Pin PTI0 */
+    GPIO_PTI1,                  /*!< GPIO Pin PTI1 */
+    GPIO_PTI2,                  /*!< GPIO Pin PTI2 */
+    GPIO_PTI3,                  /*!< GPIO Pin PTI3 */
+    GPIO_PTI4,                  /*!< GPIO Pin PTI4 */
+    GPIO_PTI5,                  /*!< GPIO Pin PTI5 */
+    GPIO_PTI6,                  /*!< GPIO Pin PTI6 */
+    GPIO_PTI7,                  /*!< GPIO Pin PTI7 */
+    GPIO_PIN_MAX,
+} GPIO_PinType;
+/*! @} End of gpio_pin_name_list    */
+
+/******************************************************************************
+*define gpio pin mask
+*
+*//*! @addtogroup gpio_pin_mask_list
+* @{
+*******************************************************************************/
+typedef enum
+{
+    /* in GPIOA register */
+    GPIO_PTA0_MASK = (1<<0),    /*!< GPIO Pin PTA0 bit mask */        
+    GPIO_PTA1_MASK = (1<<1),    /*!< GPIO Pin PTA1 bit mask */
+    GPIO_PTA2_MASK = (1<<2),    /*!< GPIO Pin PTA2 bit mask */
+    GPIO_PTA3_MASK = (1<<3),    /*!< GPIO Pin PTA3 bit mask */
+    GPIO_PTA4_MASK = (1<<4),    /*!< GPIO Pin PTA4 bit mask */
+    GPIO_PTA5_MASK = (1<<5),    /*!< GPIO Pin PTA5 bit mask */
+    GPIO_PTA6_MASK = (1<<6),    /*!< GPIO Pin PTA6 bit mask */
+    GPIO_PTA7_MASK = (1<<7),    /*!< GPIO Pin PTA7 bit mask */
+    GPIO_PTB0_MASK = (1<<8),    /*!< GPIO Pin PTB0 bit mask */
+    GPIO_PTB1_MASK = (1<<9),    /*!< GPIO Pin PTB1 bit mask */
+    GPIO_PTB2_MASK = (1<<10),   /*!< GPIO Pin PTB2 bit mask */
+    GPIO_PTB3_MASK = (1<<11),   /*!< GPIO Pin PTB3 bit mask */
+    GPIO_PTB4_MASK = (1<<12),   /*!< GPIO Pin PTB4 bit mask */
+    GPIO_PTB5_MASK = (1<<13),   /*!< GPIO Pin PTB5 bit mask */
+    GPIO_PTB6_MASK = (1<<14),   /*!< GPIO Pin PTB6 bit mask */
+    GPIO_PTB7_MASK = (1<<15),   /*!< GPIO Pin PTB7 bit mask */
+    GPIO_PTC0_MASK = (1<<16),   /*!< GPIO Pin PTC0 bit mask */
+    GPIO_PTC1_MASK = (1<<17),   /*!< GPIO Pin PTC1 bit mask */
+    GPIO_PTC2_MASK = (1<<18),   /*!< GPIO Pin PTC2 bit mask */
+    GPIO_PTC3_MASK = (1<<19),   /*!< GPIO Pin PTC3 bit mask */
+    GPIO_PTC4_MASK = (1<<20),   /*!< GPIO Pin PTC4 bit mask */
+    GPIO_PTC5_MASK = (1<<21),   /*!< GPIO Pin PTC5 bit mask */
+    GPIO_PTC6_MASK = (1<<22),   /*!< GPIO Pin PTC6 bit mask */
+    GPIO_PTC7_MASK = (1<<23),   /*!< GPIO Pin PTC7 bit mask */
+    GPIO_PTD0_MASK = (1<<24),   /*!< GPIO Pin PTD0 bit mask */
+    GPIO_PTD1_MASK = (1<<25),   /*!< GPIO Pin PTD1 bit mask */
+    GPIO_PTD2_MASK = (1<<26),   /*!< GPIO Pin PTD2 bit mask */
+    GPIO_PTD3_MASK = (1<<27),   /*!< GPIO Pin PTD3 bit mask */
+    GPIO_PTD4_MASK = (1<<28),   /*!< GPIO Pin PTD4 bit mask */
+    GPIO_PTD5_MASK = (1<<29),   /*!< GPIO Pin PTD5 bit mask */
+    GPIO_PTD6_MASK = (1<<30),   /*!< GPIO Pin PTD6 bit mask */
+    GPIO_PTD7_MASK = (1<<31),   /*!< GPIO Pin PTD7 bit mask */
+    /* in GPIOB register */
+    GPIO_PTE0_MASK = (1<<0),    /*!< GPIO Pin PTE0 bit mask */
+    GPIO_PTE1_MASK = (1<<1),    /*!< GPIO Pin PTE1 bit mask */
+    GPIO_PTE2_MASK = (1<<2),    /*!< GPIO Pin PTE2 bit mask */
+    GPIO_PTE3_MASK = (1<<3),    /*!< GPIO Pin PTE3 bit mask */
+    GPIO_PTE4_MASK = (1<<4),    /*!< GPIO Pin PTE4 bit mask */
+    GPIO_PTE5_MASK = (1<<5),    /*!< GPIO Pin PTE5 bit mask */
+    GPIO_PTE6_MASK = (1<<6),    /*!< GPIO Pin PTE6 bit mask */
+    GPIO_PTE7_MASK = (1<<7),    /*!< GPIO Pin PTE7 bit mask */
+    GPIO_PTF0_MASK = (1<<8),    /*!< GPIO Pin PTF0 bit mask */
+    GPIO_PTF1_MASK = (1<<9),    /*!< GPIO Pin PTF1 bit mask */
+    GPIO_PTF2_MASK = (1<<10),   /*!< GPIO Pin PTF2 bit mask */
+    GPIO_PTF3_MASK = (1<<11),   /*!< GPIO Pin PTF3 bit mask */
+    GPIO_PTF4_MASK = (1<<12),   /*!< GPIO Pin PTF4 bit mask */
+    GPIO_PTF5_MASK = (1<<13),   /*!< GPIO Pin PTF5 bit mask */
+    GPIO_PTF6_MASK = (1<<14),   /*!< GPIO Pin PTF6 bit mask */
+    GPIO_PTF7_MASK = (1<<15),   /*!< GPIO Pin PTF7 bit mask */
+    GPIO_PTG0_MASK = (1<<16),   /*!< GPIO Pin PTG0 bit mask */
+    GPIO_PTG1_MASK = (1<<17),   /*!< GPIO Pin PTG1 bit mask */
+    GPIO_PTG2_MASK = (1<<18),   /*!< GPIO Pin PTG2 bit mask */
+    GPIO_PTG3_MASK = (1<<19),   /*!< GPIO Pin PTG3 bit mask */
+    GPIO_PTG4_MASK = (1<<20),   /*!< GPIO Pin PTG4 bit mask */
+    GPIO_PTG5_MASK = (1<<21),   /*!< GPIO Pin PTG5 bit mask */
+    GPIO_PTG6_MASK = (1<<22),   /*!< GPIO Pin PTG6 bit mask */
+    GPIO_PTG7_MASK = (1<<23),   /*!< GPIO Pin PTG7 bit mask */
+    GPIO_PTH0_MASK = (1<<24),   /*!< GPIO Pin PTH0 bit mask */
+    GPIO_PTH1_MASK = (1<<25),   /*!< GPIO Pin PTH1 bit mask */
+    GPIO_PTH2_MASK = (1<<26),   /*!< GPIO Pin PTH2 bit mask */
+    GPIO_PTH3_MASK = (1<<27),   /*!< GPIO Pin PTH3 bit mask */
+    GPIO_PTH4_MASK = (1<<28),   /*!< GPIO Pin PTH4 bit mask */
+    GPIO_PTH5_MASK = (1<<29),   /*!< GPIO Pin PTH5 bit mask */
+    GPIO_PTH6_MASK = (1<<30),   /*!< GPIO Pin PTH6 bit mask */
+    GPIO_PTH7_MASK = (1<<31),   /*!< GPIO Pin PTH7 bit mask */
+    /* in GPIOC register */
+    GPIO_PTI0_MASK = (1<<0),    /*!< GPIO Pin PTI0 bit mask */
+    GPIO_PTI1_MASK = (1<<1),    /*!< GPIO Pin PTI1 bit mask */
+    GPIO_PTI2_MASK = (1<<2),    /*!< GPIO Pin PTI2 bit mask */
+    GPIO_PTI3_MASK = (1<<3),    /*!< GPIO Pin PTI3 bit mask */
+    GPIO_PTI4_MASK = (1<<4),    /*!< GPIO Pin PTI4 bit mask */
+    GPIO_PTI5_MASK = (1<<5),    /*!< GPIO Pin PTI5 bit mask */
+    GPIO_PTI6_MASK = (1<<6),    /*!< GPIO Pin PTI6 bit mask */
+    GPIO_PTI7_MASK = (1<<7),    /*!< GPIO Pin PTI7 bit mask */
+} GPIO_PinMaskType;
+/*! @} End of gpio_pin_mask_list    */
+
+
+/******************************************************************************
+*define gpio pin config type
+*
+*//*! @addtogroup gpio_pin_config_type_list
+* @{
+*******************************************************************************/
+/*
+*   . Internal pullup is disabled if the pin is configured as an output
+*   . High-current drive function is disabled, if the pin is configured as an input
+*       Only PTH1/0, PTE1/0, PTD1/0, PTB5/4 support Hight-current Drive.
+*/
+typedef enum
+{
+    GPIO_PinOutput = 0,                 /*!< set pin as outout */
+    GPIO_PinInput,                      /*!< set pin as input */
+    GPIO_PinInput_InternalPullup,       /*!< set internal pullup for input pin */
+    GPIO_PinOutput_HighCurrent,         /*!< set high drive for output pin */
+} GPIO_PinConfigType;
+/*! @} End of gpio_pin_config_type_list */
+
+/******************************************************************************
+* define GPIO APIs
+*
+*//*! @addtogroup gpio_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+* @brief    Toggle the pins which are specified by u32PinMask in single cycle.
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be FGPIOA/FGPIOB.
+* @param[in] u32PinMask  Specify GPIO pin need to be toggled
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void FGPIO_Toggle(FGPIO_Type *pFGPIO, uint32_t u32PinMask)
+{
+    pFGPIO->PTOR = u32PinMask;   /* Toggle the pins specified by u32PinMask */
+}
+
+/*****************************************************************************//*!
+* @brief Read input data from GPIO which is specified by pGPIO in single cycle.
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be FGPIOA/FGPIOB.
+*
+* @return   GPIO input value unsigned int 32-bit
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+ __STATIC_INLINE uint32_t FGPIO_Read(FGPIO_Type *pFGPIO)
+{
+    return (pFGPIO->PDIR);      /* Read Port Data Input Register */
+  
+}
+
+/*****************************************************************************//*!
+* @brief    Write output data to GPIO which is specified by pGPIO in single cycle.
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be FGPIOA/FGPIOB.
+* @param[in] u32Value    value to output
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void FGPIO_Write(FGPIO_Type *pFGPIO, uint32_t u32Value)
+{    
+    pFGPIO->PDOR = u32Value;    /* Write Port Ouput Data Register */
+}
+
+void GPIO_DeInit(GPIO_Type *pGPIO);
+void GPIO_Init(GPIO_Type *pGPIO, uint32_t u32PinMask, GPIO_PinConfigType sGpioType);
+void GPIO_Toggle(GPIO_Type *pGPIO, uint32_t u32PinMask);
+uint32_t GPIO_Read(GPIO_Type *pGPIO);
+void GPIO_Write(GPIO_Type *pGPIO, uint32_t u32Value);
+void GPIO_PinInit(GPIO_PinType GPIO_Pin, GPIO_PinConfigType GPIO_PinConfig);
+void GPIO_PinToggle(GPIO_PinType GPIO_Pin);
+void GPIO_PinSet(GPIO_PinType GPIO_Pin);
+void GPIO_PinClear(GPIO_PinType GPIO_Pin);
+uint8_t GPIO_BitRead(GPIO_PinType GPIO_Pin);
+    
+/*! @} End of gpio_api_list */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* #ifndef _GPIO_H_ */
diff --git a/bsp/nv32f100x/lib/inc/i2c.h b/bsp/nv32f100x/lib/inc/i2c.h
new file mode 100644
index 0000000000..2e4eced543
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/i2c.h
@@ -0,0 +1,524 @@
+/******************************************************************************
+* @brief header file for I2C module utilities (I2C). 
+*
+*******************************************************************************
+*
+* provide APIs for accessing I2C module (I2C)
+******************************************************************************/
+#ifndef _I2C_H__
+#define _I2C_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+/******************************************************************************
+* define I2C work read or write 
+*
+*//*! @addtogroup i2c_read_write_list
+* @{
+*******************************************************************************/
+#define I2C_READ                        0x01				/*!< I2C read */
+#define I2C_WRITE                       0x0  				/*!< I2C write */
+/*! @} End of i2c_read_write_list                                             */
+
+#define I2C_SEND_ACK                    0						/*!< I2C send ACK */
+#define I2C_SEND_NACK                   1						/*!< I2C send NACK */
+
+#define I2C_WAIT_STATUS_ETMEOUT         200000
+
+/******************************************************************************
+* define I2C error state
+*
+*//*! @addtogroup i2c_error_state_list
+* @{
+*******************************************************************************/
+#define I2C_ERROR_NULL                  0x00			/*!< I2C sucess*/
+#define I2C_ERROR_NO_WAIT_TCF_FLAG      0x01			/*!< I2C wait TCF overETMe*/
+#define I2C_ERROR_NO_WAIT_IICIF_FLAG    0x02			/*!< I2C wait IICIF overETMe */
+#define I2C_ERROR_NO_GET_ACK            0x04			/*!< I2C no get ACK */
+#define I2C_ERROR_START_NO_BUSY_FLAG    0x10			/*!< I2C fail to send start signals */
+#define I2C_ERROR_STOP_BUSY_FLAG        0x20			/*!< I2C fail to send stop signal */
+#define I2C_ERROR_BUS_BUSY              0x80			/*!< I2C bus busy error */
+/*! @} End of i2c_error_state_list                                            */
+
+/******************************************************************************
+* define I2C bus state
+*
+*//*! @addtogroup i2c_bus_state_list
+* @{
+*******************************************************************************/
+#define I2C_BUS_NORMAL				0x00								/*!< I2C bus normal */
+#define I2C_BUS_SLTF					0x01								/*!< I2C bus SLTF flag */
+#define I2C_BUS_SHTF2					0x02								/*!< I2C bus SHTF2 flag */
+/*! @} End of i2c_bus_state_list                                             */
+
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+#define I2C_MODE_MASTER             1
+#define I2C_MODE_SLAVE              0
+#define I2C_ADDRESS_7BIT            0
+#define I2C_ADDRESS_10BIT           1
+#define I2C_ETMEOUT_BUS_CLOCK_DIV64 0
+#define I2C_ETMEOUT_BUS_CLOCK       1
+
+/******************************************************************************
+*
+*//*! @addtogroup i2c_setting_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief I2C setting type.
+ *
+ */
+typedef struct
+{
+	uint16_t bI2CEn         :1;     			/*!< enable I2C module */
+	uint16_t bIntEn         :1;    			 	/*!< enable I2C enable */
+	uint16_t bWakeUpEn      :1;     			/*!< I2C wake up enable */
+	uint16_t bGCAEn         :1;     			/*!< I2C General call address enable */
+	uint16_t bAddressExt    :1;     			/*!< I2C extertion address selection */
+	uint16_t bRangeAddEn    :1;     			/*!< enable range address */
+	uint16_t bFackEn        :1;     			/*!< enable fast ack */
+	uint16_t bSMB_AlertEn   :1;     			/*!< SMB Alert enable */
+	uint16_t bSecondAddressEn:1;    			/*!< enable the second address */
+	uint16_t bETMeoutCountClockSelect:1;  /*!< ETMeoutCountClockSelect */
+    uint16_t bSHTF2IntEn    :1;					/*!< SHTF2 interrupt enable */
+    uint16_t Reserve        :5;
+}I2C_SettingType;
+/*! @} End of i2c_setting_type                                       						*/
+
+/******************************************************************************
+*
+*//*! @addtogroup i2c_config_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief I2C configure type.
+ *
+ */
+typedef struct
+{
+    I2C_SettingType sSetting;
+    uint16_t u16F;              /*!< setting the band rate for I2C */
+    uint16_t u16OwnA1;          /*!< slave address */
+    uint16_t u16OwnA2;          /*!< the second slave address */
+    uint16_t u16RangeA;         /*!< range address */
+    uint16_t u16Filt;           /*!< Filter for I2C   */
+    uint16_t u16Slt;            /*!< SCL Low ETMeout register low */
+    
+}I2C_ConfigType, *I2C_ConfigPtr;
+/*! @} End of i2c_config_type                                             				*/
+
+/******************************************************************************
+*
+*//*! @addtogroup i2c_callback
+* @{
+*******************************************************************************/
+typedef void (*I2C_CallbackType)(void);		/*!< I2C call back function */
+/*! @} End of i2c_callback                                             						*/
+
+/******************************************************************************
+* inline functions
+******************************************************************************/
+/******************************************************************************
+*
+*//*! @addtogroup i2c_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief enable I2C to transmit data.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_TxEnable(I2C_Type *pI2Cx)
+{
+    pI2Cx->C1 |= I2C_C1_TX_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable I2C to receive data.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_RxEnable(I2C_Type *pI2Cx)
+{
+    pI2Cx->C1 &= ~I2C_C1_TX_MASK;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set IIC band rate. 
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_SetBaudRate(I2C_Type *pI2Cx,uint32_t u32Bps)
+{
+    pI2Cx->F = (uint8_t)u32Bps;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable general call.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_GeneralCallEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->C2 |= I2C_C2_GCAEN_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SMBus Alert Response Address Enable. 
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_SMBusAlertEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->SMB|= I2C_SMB_ALERTEN_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Range Address Matching Enable.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_RangeAddressEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->C2 |= I2C_C2_RMEN_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SHTF2 Interrupt Enable.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_SHTF2IntEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->SMB |= I2C_SMB_SHTF2IE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief ETMeout Counter Clock Select.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_ETMeoutCounterClockSelect(I2C_Type *pI2Cx, uint8_t u8Clock)
+{
+    if( u8Clock )
+    {
+        pI2Cx->SMB |= I2C_SMB_TCKSEL_MASK;
+    }
+    else
+    {
+        pI2Cx->SMB &= ~I2C_SMB_TCKSEL_MASK;
+    }
+}
+/*****************************************************************************//*!
+   *
+   * @brief get I2C status.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return I2C status
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_GetStatus(I2C_Type *pI2Cx)
+{
+    return pI2Cx->S;
+}
+/*****************************************************************************//*!
+   *
+   * @brief clear specified status.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_ClearStatus(I2C_Type *pI2Cx, uint8_t u8ClearFlag)
+{
+    pI2Cx->S |= u8ClearFlag;
+}
+/*****************************************************************************//*!
+   *
+   * @brief write data to data register.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_WriteDataReg(I2C_Type *pI2Cx, uint8_t u8DataBuff)
+{
+    pI2Cx->D = u8DataBuff;
+}
+/*****************************************************************************//*!
+   *
+   * @brief read data from data register.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return I2C data register value
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_ReadDataReg(I2C_Type *pI2Cx )
+{
+    return pI2Cx->D;
+}
+/*****************************************************************************//*!
+   *
+   * @brief check if is Tx mode.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return result  TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsTxMode(I2C_Type *pI2Cx )
+{
+    return(pI2Cx->C1 & I2C_C1_TX_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check I2C if busy.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return result  TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsBusy(I2C_Type *pI2Cx )
+{
+    return (pI2Cx->S & I2C_S_BUSY_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check I2C receive ack or nack.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return result    TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsReceivedAck(I2C_Type *pI2Cx )
+{
+    return (pI2Cx->S & I2C_S_RXAK_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check I2C if is master mode.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return result    TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsMasterMode(I2C_Type *pI2Cx )
+{
+    return(pI2Cx->C1 & I2C_C1_MST_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SCL Low ETMeout Flag.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return result    TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsSMB_SLTF(I2C_Type *pI2Cx )
+{
+    return (pI2Cx->SMB & I2C_SMB_SLTF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SCL High ETMeout Flag is set or clear.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return result    TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsSMB_SHTF2(I2C_Type *pI2Cx )
+{
+    return(pI2Cx->SMB & I2C_SMB_SHTF2_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief clear SLTF flag.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_ClearSLTF(I2C_Type *pI2Cx )
+{
+    pI2Cx->SMB |= I2C_SMB_SLTF_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief clear SHTF2 flag.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_ClearSHTF2(I2C_Type *pI2Cx )
+{
+    pI2Cx->SMB |= I2C_SMB_SHTF2_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief send out ACK.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_SendAck(I2C_Type *pI2Cx )
+{
+    pI2Cx->C1 &= ~I2C_C1_TXAK_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief send out NACK.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_SendNack(I2C_Type *pI2Cx )
+{
+    pI2Cx->C1 |= I2C_C1_TXAK_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Second I2C Address Enable.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_SecondAddressEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->SMB |= I2C_SMB_SIICAEN_MASK;
+}
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void I2C_Init(I2C_Type *pI2Cx,I2C_ConfigPtr pI2CConfig);
+uint8_t I2C_Start(I2C_Type *pI2Cx);
+uint8_t I2C_Stop(I2C_Type *pI2Cx);
+uint8_t I2C_RepeatStart(I2C_Type *pI2Cx);
+uint8_t I2C_IsTxMode(I2C_Type *pI2Cx );
+uint8_t I2C_IsBusy(I2C_Type *pI2Cx );
+uint8_t I2C_IsReceivedAck(I2C_Type *pI2Cx );
+uint8_t I2C_IsMasterMode(I2C_Type *pI2Cx );
+void I2C_ClearSHTF2(I2C_Type *pI2Cx );
+void I2C_ClearSLTF(I2C_Type *pI2Cx );
+uint8_t I2C_IsSMB_SHTF2(I2C_Type *pI2Cx );
+uint8_t I2C_IsSMB_SLTF(I2C_Type *pI2Cx );
+void I2C_TxEnable(I2C_Type *pI2Cx);
+void I2C_RxEnable(I2C_Type *pI2Cx);
+void I2C_IntEnable(I2C_Type *pI2Cx);
+void I2C_IntDisable(I2C_Type *pI2Cx);
+void I2C_SetBaudRate(I2C_Type *pI2Cx,uint32_t u32Bps);
+void I2C_SetSlaveAddress(I2C_Type *pI2Cx,uint16_t u16SlaveAddress);
+void I2C_GeneralCallEnable(I2C_Type *pI2Cx);
+void I2C_SMBusAlertEnable(I2C_Type *pI2Cx);
+void I2C_RangeAddressEnable(I2C_Type *pI2Cx);
+void I2C_SHTF2IntEnable(I2C_Type *pI2Cx);
+void I2C_ETMeoutCounterClockSelect(I2C_Type *pI2Cx, uint8_t u8Clock);
+void I2C_SetSCLLowETMeout(I2C_Type *pI2Cx, uint16_t u16ETMeout);
+uint8_t I2C_GetStatus(I2C_Type *pI2Cx);
+void I2C_ClearStatus(I2C_Type *pI2Cx, uint8_t u8ClearFlag);
+void I2C_SendAck(I2C_Type *pI2Cx );
+void I2C_SendNack(I2C_Type *pI2Cx );
+void I2C_SecondAddressEnable(I2C_Type *pI2Cx);
+void I2C_ClearStatus(I2C_Type *pI2Cx, uint8_t u8ClearFlag);
+void I2C_WriteDataReg(I2C_Type *pI2Cx, uint8_t u8DataBuff);
+uint8_t I2C_ReadDataReg(I2C_Type *pI2Cx );
+void I2C_Deinit(I2C_Type *pI2Cx);
+uint8_t I2C_WriteOneByte(I2C_Type *pI2Cx, uint8_t u8WrBuff);
+uint8_t I2C_ReadOneByte(I2C_Type *pI2Cx, uint8_t *pRdBuff, uint8_t u8Ack);
+uint8_t I2C_MasterSendWait(I2C_Type *pI2Cx,uint16_t u16SlaveAddress,uint8_t *pWrBuff,uint32_t u32Length);
+uint8_t I2C_MasterReadWait(I2C_Type *pI2Cx,uint16_t u16SlaveAddress,uint8_t *pRdBuff,uint32_t u32Length);
+void I2C0_SetCallBack( I2C_CallbackType pCallBack );
+void I2C1_SetCallBack( I2C_CallbackType pCallBack );
+
+/*! @} End of i2c_bus_state_list                                             						*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif //
+
+
diff --git a/bsp/nv32f100x/lib/inc/ics.h b/bsp/nv32f100x/lib/inc/ics.h
new file mode 100644
index 0000000000..899775dcd8
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/ics.h
@@ -0,0 +1,347 @@
+/******************************************************************************
+*
+* @brief  ICS 驱动头文件.  
+*
+******************************************************************************/
+#ifndef ICS_H_
+#define ICS_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "common.h"
+/****************************************************************************!
+ * @brief 时钟模式常量定义
+ *
+ ***************************************************************************/
+enum
+{
+    ICS_CLK_MODE_FEI = 1,       /*!< FEI 模式 */
+    ICS_CLK_MODE_FEE,           /*!< FEE 模式 */
+    ICS_CLK_MODE_FEE_OSC,       /*!< FEE 模式 OSC输出时钟源选择来自EXTAL引脚的外部时钟源 */    
+    ICS_CLK_MODE_FBE,           /*!< FBE 模式 */
+    ICS_CLK_MODE_FBE_OSC,       /*!< FBE 模式 OSC输出时钟源选择来自EXTAL引脚的外部时钟源  */    
+    ICS_CLK_MODE_FBI,           /*!< FBI 模式 */
+    ICS_CLK_MODE_FBILP,         /*!< FBILP 模式 */    
+    ICS_CLK_MODE_FBELP,         /*!< FBELP 模式 */        
+};			
+  
+/*****************************************************************************//*!
+   *
+   * @brief 将时钟模式从当前模式切换到另一个时钟模式.
+   *
+   *  时钟模式宏观定义如下:
+   *      FEI, FBI, FEE, FBE, FBILP, FBELP, FEE_OSC, FBE_OSC
+   *   注：FEE_OSC, FBE_OSC 不能用作当前时钟模式. 当前时钟模式和要切换到的时钟模式组合如下： 
+   *    < 当前时钟模式，要切换到的时钟模式>     
+   *    <FEI,FEE>, <FEI,FBI>, <FEI,FBE>, <FEI,FBE_OSC>, <FEI,FEE_OSC>, <FEE,FEI>,
+   *    <FEE,FBI>, <FEE,FBE>, <FBI,FBE>, <FBI,FEE>, <FBI,FBILP>, <FBI,FEI>,
+   *    <FBE,FBI>, <FBE,FEE>, <FBE,FEI>, <FBE,FBELP>, <FBELP,FBE>, <FBILP,FBI>.
+   *    
+   * @param[in] CurMode   当前时钟模式
+   * @param[in] NewMode   要切换到的时钟模式
+   * @param[in] clkFreq     参考时钟频率
+   *       
+   * @return none
+   * @warning   FEE_OSC, FBE_OSC 不能用作当前时钟模式. 
+   *
+   *****************************************************************************/
+
+#define ICS_SwitchMode(CurMode, NewMode, clkFreq)   CurMode##_to_##NewMode(clkFreq)
+       
+ 
+/******************************************************************************
+* 定义 OSC 配置结构体
+*
+*******************************************************************************/
+typedef struct
+{
+	uint8_t bRange      : 1;        /*!< 1: 高频范围, 0: 低频范围 */
+	uint8_t bGain       : 1;        /*!< 1: 高增益, 0:低增益 */
+	uint8_t bEnable     : 1;        /*!< 1: 使能OSC, 0: 禁用OSC */
+	uint8_t bStopEnable : 1;        /*!< 1: 停止模式下OSC使能, 0: 停止模式下OSC禁用 */
+	uint8_t bIsCryst    : 1;        /*!< 1: OSC输出选择振荡器时钟, 0: OSC输出选择来自extal引脚的外部时钟 */
+	uint8_t bWaitInit   : 1;        /*!< 1: 等待振荡器初始化完成, 0: 不等待 */
+} OSC_ConfigType, *OSC_ConfigPtr;
+
+
+
+/******************************************************************************
+* 
+* ICS配置结构体
+*
+*******************************************************************************/
+typedef struct
+{
+   uint8_t    u8ClkMode;        /*!< 选择时钟模式*/
+   uint8_t    bLPEnable;        /*!< 低功耗模式下使能 */
+   uint32_t   u32ClkFreq;       /*!< 参考时钟频率 */  
+   OSC_ConfigType  oscConfig;   /*!< OSC 配置 */
+} ICS_ConfigType ;
+
+/*****************************************************************************//*!
+*
+* @brief 使能中断.
+*        
+* @param   none
+*
+* @return none
+* 
+* @see    ICS_DisableInt
+*****************************************************************************/
+__STATIC_INLINE void ICS_EnableInt(void)
+{
+    ICS->C4 |= (ICS_C4_LOLIE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 禁用中断
+*        
+* @param   none
+*
+* @return none
+*
+* @see    ICS_EnableInt
+*****************************************************************************/
+__STATIC_INLINE void ICS_DisableInt(void)
+{
+    ICS->C4 &= ~(ICS_C4_LOLIE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 使能时钟监控
+*        
+* @param   none
+*
+* @return none
+*
+* @see    ICS_DisableClockMonitor
+*****************************************************************************/
+__STATIC_INLINE void ICS_EnableClockMonitor(void)
+{
+    ICS->C4 |= (ICS_C4_CME_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 禁用时钟监控
+*        
+* @param   none
+*
+* @return none
+*
+* @see    ICS_EnableClockMonitor
+*****************************************************************************/
+__STATIC_INLINE void ICS_DisableClockMonitor(void)
+{
+    ICS->C4 &= ~(ICS_C4_CME_MASK);    
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief 设置ICS输出时钟源分频
+   *        
+   * @param[in] busDivide   -- 分频值
+   *
+   * @return  depends on commands
+   *****************************************************************************/
+__STATIC_INLINE void ICS_SetBusDivider(uint8_t u8BusDivide)
+{
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(u8BusDivide);
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief 使能OSC
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_Enable(void)
+{
+    OSC->CR |= (OSC_CR_OSCEN_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 禁用OSC
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_Disable(void)
+{
+    OSC->CR &= ~(OSC_CR_OSCEN_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 设置OSC模块的频率范围为低频范围
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SetLowRange(void)
+{
+    OSC->CR &= ~(OSC_CR_RANGE_MASK);    
+}
+
+/*!***************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+*
+* @brief 设置OSC模块的频率范围为高频范围
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SetHighRange(void)
+{
+    OSC->CR |= (OSC_CR_RANGE_MASK);    
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief 设置OSC的工作模式为高增益模式
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SetHighGain(void)
+{
+    OSC->CR |= (OSC_CR_HGO_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 设置OSC的工作模式为低功耗模式
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SetLowGain(void)
+{
+    OSC->CR &= ~(OSC_CR_HGO_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 选择OSC模块的输出时钟源为振荡器时钟源
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SelectCrystal(void)
+{
+    OSC->CR |= (OSC_CR_OSCOS_MASK);    
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief OSC输出选择来自extal引脚的外部时钟 
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SelectClock(void)
+{
+    OSC->CR &= ~(OSC_CR_OSCOS_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 在停止模式下OSC模块使能
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_ActiveInStop(void)
+{
+    OSC->CR |= (OSC_CR_OSCSTEN_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 在停止模式下OSC模块禁用
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_InactiveInStop(void)
+{
+    OSC->CR &= ~(OSC_CR_OSCSTEN_MASK);    
+}
+
+/******************************************************************************/
+
+void ICS_Init(ICS_ConfigType *pConfig);
+void ICS_DeInit(void);
+void ICS_SetClkDivider(uint32_t u32ClkFreqKHz);
+void ICS_Trim(uint16 u16TrimValue);
+void OSC_Init(OSC_ConfigType *pConfig);
+void OSC_DeInit(void);
+
+/************** 内联函数 ******************/
+void ICS_DisableClockMonitor(void);
+void ICS_DisableInt(void);
+void ICS_EnableClockMonitor(void);
+void ICS_EnableInt(void);
+void ICS_SetBusDivider(uint8_t u8BusDivide);
+void OSC_ActiveInStop(void);
+void OSC_Enable(void);
+void OSC_Disable(void);
+void OSC_InactiveInStop(void);
+void OSC_SelectClock(void);
+void OSC_SelectCrystal(void);
+void OSC_SetHighGain(void);
+void OSC_SetHighRange(void);
+void OSC_SetLowGain(void);
+void OSC_SetLowRange(void);
+
+/* do not touch the following functions */
+void FEI_to_FEE(ICS_ConfigType *pConfig);
+void FEI_to_FBI(ICS_ConfigType *pConfig);
+void FEI_to_FBE(ICS_ConfigType *pConfig);
+void FEE_to_FBI(ICS_ConfigType *pConfig);
+void FEE_to_FEI(ICS_ConfigType *pConfig);
+void FEE_to_FBE(ICS_ConfigType *pConfig);
+void FBE_to_FEE(ICS_ConfigType *pConfig);
+void FBE_to_FEI(ICS_ConfigType *pConfig);
+void FBE_to_FBI(ICS_ConfigType *pConfig);
+void FBE_to_FBELP(ICS_ConfigType *pConfig);
+void FBI_to_FEI(ICS_ConfigType *pConfig);
+void FBI_to_FBE(ICS_ConfigType *pConfig);
+void FBI_to_FEE(ICS_ConfigType *pConfig);
+void FBI_to_FBILP(ICS_ConfigType *pConfig);
+void FBILP_to_FBI(ICS_ConfigType *pConfig);
+void FBELP_to_FBE(ICS_ConfigType *pConfig);
+void FEI_to_FBE_OSC(ICS_ConfigType *pConfig);
+void FEI_to_FEE_OSC(ICS_ConfigType *pConfig);
+#ifdef __cplusplus
+}
+#endif
+#endif 
diff --git a/bsp/nv32f100x/lib/inc/kbi.h b/bsp/nv32f100x/lib/inc/kbi.h
new file mode 100644
index 0000000000..5a91d8a13f
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/kbi.h
@@ -0,0 +1,428 @@
+/******************************************************************************
+**
+* @brief header file for KBI. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing KBI
+******************************************************************************/
+#ifndef _KBI_H_
+#define _KBI_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/*!
+* @brief KBI MODE select enum.
+*
+*/
+typedef enum
+{
+    KBI_MODE_EDGE_ONLY = 0,             /*!< select  edge only mode  */         
+    KBI_MODE_EDGE_LEVEL                 /*!< select  both edge and level  mode */
+}KBI_ModeType;
+
+
+ /*!
+ * @brief KBI Edge select enum.
+ *
+ */
+typedef enum
+{
+    KBI_FALLING_EDGE_LOW_LEVEL = 0,     /*!< select falling edge and/or low level  */
+    KBI_RISING_EDGE_HIGH_LEVEL          /*!< select rising edge and/or high level  */
+}KBI_EdgeType;
+
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+* KBI module max number and port pins definition
+*
+*//*! @addtogroup kbi_macro
+* @{
+*******************************************************************************/
+#define KBI_MAX_NO              2                  /*!< max number of modules */
+
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+   #define KBI_MAX_PINS_PER_PORT   8                  /*!< max number of pins */
+#elif defined(CPU_NV32M4)
+   #define KBI_MAX_PINS_PER_PORT   32                  /*!< max number of pins */
+#endif
+/*! @} End of kbi_macro                                                    */
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/*! @brief KBI_CALLBACK function declaration                                  */
+typedef void (*KBI_CallbackType)(void);                     
+/*! @} End of kbi_callback                                                    */
+
+
+
+/******************************************************************************
+* KBI pin config struct
+*
+*//*! @addtogroup kbi_pinconfigstruct
+* @{
+*******************************************************************************/
+/*!
+* @brief KBI pin enable and edge select struct.
+*
+*/
+
+typedef struct
+{
+    uint8_t     bEdge   : 1;                                /*!< edge/level select bit */
+    uint8_t     bEn     : 1;                                /*!< pin enable bit */
+    uint8_t     bRsvd   : 6;                                /*!< reserved */
+} KBI_PinConfigType;
+/*! @} End of kbi_pinconfigstruct                                             */
+
+
+/******************************************************************************
+* KBI config struct
+*
+*//*! @addtogroup kbi_configstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief KBI status and control struct.
+ *
+ */
+
+typedef struct
+{
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+    struct
+    {
+        uint8_t     bMode   : 1;                            /*!< KBI detection mode select */
+        uint8_t     bIntEn  : 1;                            /*!< KBI interrupt enable bit */
+        uint8_t     bRsvd   : 6;                            /*!< reserved */
+    } sBits;
+#elif  defined(CPU_NV32M4)
+    struct
+    {
+        uint32_t     bMode   : 1;                            /*!< KBI detection mode select */
+        uint32_t     bIntEn  : 1;                            /*!< KBI interrupt enable bit */
+        uint32_t     bRsvd2  : 2;                           /*!< reserved */
+        uint32_t     bKbspEn : 1;							  /*!<Real KBI_SP register enable*/
+		uint32_t     bRstKbsp: 1;                            /*!<Reset KBI_SP register*/
+        uint32_t     bRsvd26 : 26;                           /*!< reserved */
+    } sBits;
+#endif
+    KBI_PinConfigType   sPin[KBI_MAX_PINS_PER_PORT];
+} KBI_ConfigType, *KBI_ConfigTypePtr;
+/*! @} End of kbi_configstruct                                                */
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+/*!
+ * inline functions
+ */
+/******************************************************************************
+* KBI api list
+*
+*//*! @addtogroup kbi_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief set detect falling edge only.
+*        
+* @param[in]   pKBI          pointer to KBI module.
+* @param[in]   PinMasks      indicate pin numbers.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DetectRisingEdge.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_DetectFallingEdge(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_DetectFallingEdge(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->SC &= ~KBI_SC_KBMOD_MASK;
+    pKBI->ES &= ~(PinMasks);
+}
+
+/*****************************************************************************//*!
+*
+* @brief set detect falling edge only.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin numbers.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DetectFallingEdge.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_DetectRisingEdge(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_DetectRisingEdge(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->SC &= ~KBI_SC_KBMOD_MASK;
+    pKBI->ES |= (PinMasks);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set detect falling edge only.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin number/mask.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DetectFallingEdgeLowLevel.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_DetectRisingEdgeHighLevel(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_DetectRisingEdgeHighLevel(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->SC |= KBI_SC_KBMOD_MASK;
+    pKBI->ES |= (PinMasks);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set detect falling edge only.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin number/mask.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DetectRisingEdgeHighLevel.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_DetectFallingEdgeLowLevel(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_DetectFallingEdgeLowLevel(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->SC |= KBI_SC_KBMOD_MASK;
+    pKBI->ES &= ~(PinMasks);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief enable the pin specified.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin number/mask.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_Disable.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_Enable(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_Enable(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->PE |= (PinMasks);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable the pin specified.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin number/mask.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_Enable.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_Disable(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_Disable(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->PE &= ~(PinMasks);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief enable the corresponding interrupt.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DisableInt.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_EnableInt(KBI_Type *pKBI)
+{
+    pKBI->SC |= KBI_SC_KBIE_MASK;        
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable the corresponding interrupt.
+*        
+* @param[in]  pKBI         pointer to KBI module.
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see KBI_EnableInt.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_DisableInt(KBI_Type *pKBI)
+{
+    pKBI->SC &= ~KBI_SC_KBIE_MASK;        
+}
+
+/*****************************************************************************//*!
+*
+* @brief Get the corresponding status flag bits.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+*          
+* @return uint8_t.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_ClrFlags.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  uint8_t KBI_GetFlags(KBI_Type *pKBI)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  uint32_t KBI_GetFlags(KBI_Type *pKBI)
+#endif
+{
+    return (pKBI->SC & KBI_SC_KBF_MASK);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief clear the corresponding status flag bits.
+*        
+* @param[in]   pKBI         pointer to KBI module
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see KBI_GetFlags.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_ClrFlags(KBI_Type *pKBI)
+{
+    pKBI->SC |= KBI_SC_KBACK_MASK;        
+}
+
+#if defined(CPU_NV32M4)
+/*****************************************************************************//*!
+*
+* @brief Real KBI_SP register enable.
+*        
+* @param[in]   pKBI         pointer to KBI module
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see The real ETMe value of Keyboard source pin to be read.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_SPEnable(KBI_Type *pKBI)
+{
+    pKBI->SC |= KBI_SC_KBSPEN_MASK;        
+}
+
+/*****************************************************************************//*!
+*
+* @brief Get KBI source pin register fields.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+*          
+* @return uint32_t.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_GetSP.
+*
+*****************************************************************************/
+__STATIC_INLINE  uint32_t KBI_GetSP(KBI_Type *pKBI)
+{
+    return (pKBI->SP & KBI_SP_SP_MASK);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief Reset KBI_SP register.
+*        
+* @param[in]   pKBI         pointer to KBI module
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see KBI_RstSP.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_RstSP(KBI_Type *pKBI)
+{
+    pKBI->SC |= KBI_SC_RSTKBSP_MASK;        
+}
+#endif
+
+/*! @} End of kbi_api_list                                                  */
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+void KBI_Init(KBI_Type *pKBI, KBI_ConfigType *pConfig);
+void KBI_SetCallback(KBI_Type *pKBI, KBI_CallbackType pfnCallback);
+
+#ifdef __cplusplus
+}
+#endif
+#endif 
diff --git a/bsp/nv32f100x/lib/inc/pit.h b/bsp/nv32f100x/lib/inc/pit.h
new file mode 100644
index 0000000000..99cbdeb7b3
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/pit.h
@@ -0,0 +1,317 @@
+/******************************************************************************
+* @brief    Periodic Interrupt ETMer (PIT) driver head file. 
+*
+******************************************************************************/
+#ifndef PIT_H_
+#define PIT_H_
+#include"common.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* PIT channel number list
+*
+*//*! @addtogroup pit_channelnumber
+* @{
+*******************************************************************************/
+enum
+{
+    PIT_CHANNEL0 = 0,       /*!< PIT channel 0 */
+    PIT_CHANNEL1            /*!< PIT channel 1 */
+};
+
+/*! @} End of pit_channelnumber                                               */
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/*
+ * Callback type
+ */
+
+/******************************************************************************
+* PIT callback function declaration
+*
+*//*! @addtogroup pit_callback
+* @{
+*******************************************************************************/
+typedef void (*PIT_CallbackType)(void);             /*!< PIT callback type */
+
+/*! @} End of pit_callback                                                    */
+
+/* PIT configuration structure 
+ */  
+/*!
+ * @brief PIT configuration type.
+ *
+ */
+typedef struct
+{   
+    uint8_t bFreeze         : 1;    /*!< 1: stop in debug mode, 0: run in debug mode */
+    uint8_t bModuleDis      : 1;    /*!< 1: PIT module is disable, 0: PIT module is enable */    
+    uint8_t bReserved0      : 1;    /*!< reserved bit */ 
+    uint8_t bReserved1      : 5;    /*!< reserved bit */ 
+    uint8_t bETMerEn        : 1;    /*!< 1: channel ETMer is enable, 0: channel ETMer is disable */ 
+    uint8_t bInterruptEn    : 1;    /*!< 1: channel ETMer interrupt is enable, 0: channel ETMer interrupt is disable */ 
+    uint8_t bChainMode      : 1;    /*!< 1: chain mode is enable, 0: chain mode is disable */ 
+    uint8_t bReserved2      : 5;    /*!< reserved bit */ 
+    uint8_t bFlag           : 1;    /*!< 1: flag is set,and write 1 to clear flag, 0: no flag is set */
+    uint8_t bReserved3      : 7;    /*!< reserved bit */   
+    uint32_t u32LoadValue      ;    /*!< 32-bit channel load value */  
+} PIT_ConfigType, *PIT_ConfigPtr; 
+
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+
+/*!
+ * inline functions
+ */
+
+/******************************************************************************
+* PIT API list
+*
+*//*! @addtogroup pit_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief enable pit module.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_Enable(void)
+{
+
+    PIT->MCR &= ~PIT_MCR_MDIS_MASK; 
+    
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable pit module.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_Disable(void)
+{
+
+    PIT->MCR |= PIT_MCR_MDIS_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief pit ETMers are stopped in debug mode.
+*        
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_SetDebugFreeze(void)
+{
+
+    PIT->MCR |= PIT_MCR_FRZ_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief pit ETMers are running in debug mode.
+*        
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_SetDebugOn(void)
+{
+
+    PIT->MCR &= ~PIT_MCR_FRZ_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief enable pit channel ETMer.
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelEnable(uint8_t u8Channel)
+
+{
+
+    PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_TEN_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable pit channel ETMer.
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelDisable(uint8_t u8Channel)
+{
+
+    PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief enable pit channel ETMer interrupt.
+*        
+* @param[in]  u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelEnableInt(uint8_t u8Channel)
+
+{
+
+    PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_TIE_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable pit channel ETMer interrupt .
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelDisableInt(uint8_t u8Channel)
+
+{
+
+    PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_TIE_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  enable pit channel ETMer chain mode.
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelEnableChain(uint8_t u8Channel)
+{
+    PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_CHN_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  disable pit channel ETMer chain mode.
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelDisableChain(uint8_t u8Channel)
+
+{
+    PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_CHN_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief get pit channel ETMer interrrupt flag.
+*        
+* @param[in]   u8Channel.
+*
+* @return bflag.
+*
+* @ Pass/ Fail criteria: none
+
+*****************************************************************************/
+__STATIC_INLINE uint8_t PIT_ChannelGetFlags(uint8_t u8Channel)
+
+{
+    uint8_t bflag;  
+    
+    bflag = (PIT->CHANNEL[u8Channel].TFLG & PIT_TFLG_TIF_MASK);    
+    
+    return bflag;
+    
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief clear pit channel ETMer interrrupt flag.
+*        
+* @param[in] u8Channel
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelClrFlags(uint8_t u8Channel)
+{
+    PIT->CHANNEL[u8Channel].TFLG |= PIT_TFLG_TIF_MASK;       
+}
+
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void PIT_Init(uint8_t u8Channel_No, PIT_ConfigType *pConfig);
+void PIT_SetLoadVal(uint8_t u8Channel, uint32_t u32loadvalue);
+void PIT_SetCallback(uint8_t u8Channel_No, PIT_CallbackType pfnCallback);
+void PIT_DeInit(void);
+/*! @} End of pit_api_list                                                   */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* PIT_H_ */
diff --git a/bsp/nv32f100x/lib/inc/pmc.h b/bsp/nv32f100x/lib/inc/pmc.h
new file mode 100644
index 0000000000..f47b70b9a4
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/pmc.h
@@ -0,0 +1,373 @@
+/******************************************************************************
+*
+* @brief header file for PMC. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing PMC
+******************************************************************************/
+#ifndef PMC_H_
+#define PMC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+/******************************************************************************
+* PMC system mode definition
+*
+*//*! @addtogroup pmc_sysmode
+* @{
+*******************************************************************************/
+#define PmcModeRun     0                     /*!< run mode */
+#define PmcModeWait    1                     /*!< wait mode */
+#define PmcModeStop4   2                     /*!< stop4 mode */
+#define PmcModeStop3   3                     /*!< stop3 mode */
+/*! @} End of pmc_sysmode                                                     */
+
+/******************************************************************************
+* PMC LVD and LVW voltage definition
+*
+*//*! @addtogroup pmc_voltageselect
+* @{
+*******************************************************************************/
+#define PmcLVDTrip_Low   0                    /*!< LVD low trip point */
+#define PmcLVDTrip_High  1                     /*!< LVD high trip point  */
+
+#define PmcLVWTrip_Low   0                     /*!< LVW low trip point */
+#define PmcLVWTrip_Mid1  1                     /*!< LVW mid1 trip point */
+#define PmcLVWTrip_Mid2  2                     /*!< LVW mid2 trip point */
+#define PmcLVWTrip_High  3                     /*!< LVW high trip point */
+/*! @} End of pmc_voltageselect                                               */
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/******************************************************************************
+* PMC control  struct
+*
+*//*! @addtogroup pmc_ctrlstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief PMC Control Structure Type.
+ *
+ */
+
+typedef union 
+{
+   uint8_t byte;						  /*!< byte field of union type */
+   struct 
+   {     
+       uint8_t bBandgapEn        :1;      /*!< bandgap enable */
+       uint8_t bBandgapDrv       :1;      /*!< bandgap drive select */
+       uint8_t bLvdEn            :1;      /*!< LVD enable */
+       uint8_t bLvdStopEn        :1;      /*!< LVD enable in stop mode */
+       uint8_t bLvdRstEn         :1;      /*!< reset enable when VLD evvent */
+       uint8_t bLvwIrqEn         :1;      /*!< LVW int enable */
+       uint8_t bLvwAck           :1;      /*!< LVW acknowledge */
+       uint8_t bLvwFlag          :1;      /*!< LVW flag */
+   }bits; 								  /*!< bitfield of union type */
+}PMC_Ctrl1Type, *PMC_Ctrl1Ptr;		  /*!< PMC control1 reg structure */
+/*! @} End of pmc_ctrlstruct                                                  */
+
+/******************************************************************************
+* PMC control-- voltage select type.
+*
+*//*! @addtogroup pmc_voltselectstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief PMC control-- voltage select type.
+ *
+ */
+typedef union 
+{
+   uint8_t byte;						   /*!< byte field of union type */
+   struct 
+   {     
+       uint8_t           :4;               /*!< none */  
+       uint8_t bLVWV     :2;               /*!< LVW voltage select */  
+       uint8_t bLVDV     :1;               /*!< LVD voltage select */  
+       uint8_t           :1;               /*!< none */                 
+   }bits;  								   /*!< bitfield of union type */
+}PMC_Ctrl2Type, *PMC_Ctrl2Ptr;		   /*!< PMC control2 reg structure */
+/*! @} End of pmc_voltselectstruct                                            */
+
+/******************************************************************************
+* PMC configrue type.
+*
+*//*! @addtogroup pmc_configstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief PMC configrue type.
+ *
+ */
+
+typedef struct 
+{
+    PMC_Ctrl1Type    sCtrlstatus;          /*!< PMC control and status */  
+    PMC_Ctrl2Type    sDetectVoltSelect;    /*!< LVW and LVW voltage select */  
+}PMC_ConfigType, *PMC_ConfigPtr;		   /*!< PMC configuration structure */
+/*! @} End of pmc_configstruct                                            */  
+
+
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/*!
+ * inline functions
+ */
+/******************************************************************************
+* PMC api list.
+*
+*//*! @addtogroup pmc_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief  enable LVD events during stop mode.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DisableLVDInStopMode.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_EnableLVDInStopMode(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 |= PMC_SPMSC1_LVDSE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable LVD events during stop mode.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_EnableLVDInStopMode.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_DisableLVDInStopMode(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 &= ~PMC_SPMSC1_LVDSE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable LVD events to generate a hardware reset,  note: write once.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DisableLVDRst.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_EnableLVDRst(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 |= PMC_SPMSC1_LVDRE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable LVD events to generate a hardware reset,  note: write once.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_EnableLVDRst.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_DisableLVDRst(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 &= ~PMC_SPMSC1_LVDRE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable low-voltage detect logic,  note: write once.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DisableLVD.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_EnableLVD(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 |= PMC_SPMSC1_LVDE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable low-voltage detect logic,  note: write once
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see PMC_EnableLVD.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_DisableLVD(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 &= ~PMC_SPMSC1_LVDE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the low-voltage detect trip point voltage, note: write once.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+* @param[in]  Trippoint         LVD trip point voltage,0~1.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_SetLVWTripVolt.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_SetLVDTripVolt(PMC_Type *pPMC, uint8_t Trippoint)
+{
+    if(Trippoint)
+        pPMC->SPMSC2 |= PMC_SPMSC2_LVDV_MASK;
+    else
+        pPMC->SPMSC2 &= ~PMC_SPMSC2_LVDV_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the low-voltage warning (LVW) trip point voltage.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+* @param[in]  Trippoint         LVW trip point voltage,0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_SetLVDTripVolt.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_SetLVWTripVolt(PMC_Type *pPMC, uint8_t Trippoint)
+{
+    pPMC->SPMSC2 &= ~PMC_SPMSC2_LVWV_MASK;
+    pPMC->SPMSC2 |= PMC_SPMSC2_LVWV(Trippoint);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Enable hardware interrupt requests for LVWF.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DisableLVWInterrupt.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_EnableLVWInterrupt(PMC_Type *pPMC)
+{
+   pPMC->SPMSC1 |= PMC_SPMSC1_LVWIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Disable hardware interrupt requests for LVWF.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_EnableLVWInterrupt.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_DisableLVWInterrupt(PMC_Type *pPMC)
+{
+   pPMC->SPMSC1 &= ~PMC_SPMSC1_LVWIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  get the lvw warning flag.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return uint8_t lvw warning flag.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_ClrLVWFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t PMC_GetLVWFlag(PMC_Type *pPMC)
+{
+   return (pPMC->SPMSC1 & PMC_SPMSC1_LVWF_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the lvw warning flag.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_GetLVWFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_ClrLVWFlag(PMC_Type *pPMC)
+{
+   pPMC->SPMSC1 |= PMC_SPMSC1_LVWACK_MASK;
+}
+
+/*! @} End of pmc_api_list                                                    */
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+void PMC_Init(PMC_Type *pPMC, PMC_ConfigType *pPMC_Config);
+void PMC_DeInit(PMC_Type *pPMC);
+void PMC_SetMode(PMC_Type *pPMC,uint8_t u8PmcMode);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* PMC_H_ */
diff --git a/bsp/nv32f100x/lib/inc/rtc.h b/bsp/nv32f100x/lib/inc/rtc.h
new file mode 100644
index 0000000000..ac72bec450
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/rtc.h
@@ -0,0 +1,224 @@
+/******************************************************************************
+*
+* @brief    Real-ETMe counter (RTC) driver head file.  
+*
+******************************************************************************/
+#ifndef RTC_H_
+#define RTC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+* RTC control bit definition
+*
+*//*! @addtogroup rtc_controlbit
+* @{
+*******************************************************************************/
+
+#define RTC_OUTPUT_ENABLE           1	/*!< enable RTCO pin  */ 
+#define RTC_INTERRUPT_ENABLE        1	/*!< enable RTC interrupt  */ 
+#define RTC_CLKSRC_EXTERNAL         0	/*!< select external clock as RTC clock source  */
+#define RTC_CLKSRC_1KHZ             1	/*!< select LPO as RTC clock source  */
+#define RTC_CLKSRC_IREF             2	/*!< select internal reference clock as RTC clock source  */
+#define RTC_CLKSRC_BUS              3	/*!< select bus clock as RTC clock source  */
+#define RTC_CLK_PRESCALER_128       1	/*!< presalcer is 1 or 128 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_256       2	/*!< presalcer is 2 or 256 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_512       3	/*!< presalcer is 4 or 512 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_1024      4	/*!< presalcer is 8 or 1024 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_2048      5	/*!< presalcer is 16 or 2048 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_100       6	/*!< presalcer is 32 or 100 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_1000      7	/*!< presalcer is 64 or 1000 according to RTCLKS bits */
+
+
+/*! @} End of rtc_controlbit                                                  */
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/*
+ * Callback type
+ */
+
+/******************************************************************************
+* RTC callback function declaration
+*
+*//*! @addtogroup rtc_callback
+* @{
+*******************************************************************************/
+
+/*!
+ * @brief RTC Callback type.
+ *
+ */
+
+typedef void (*RTC_CallbackType)(void);
+
+/*! @} End of rtc_callback                                                    */
+
+
+/* RTC configuration structure 
+ */  
+/*!
+ * @brief RTC configuration type.
+ *
+ */
+typedef struct
+{   
+    uint16_t bReserved                  : 4;    /*!< reserved */     
+    uint16_t bRTCOut                    : 1;    /*!< 1: RTCO pin is enable, 0: RTCO pin is disable */
+    uint16_t bReserved1                 : 1;    /*!< reserved */ 
+    uint16_t bInterruptEn               : 1;    /*!< 1: RTC interrupt is enable, 0: RTC interrupt is disable */
+    uint16_t bFlag                      : 1;    /*!< 1: RTC flag is set, 0: RTC flag is not set */   
+    uint16_t bClockPresaler             : 3;    /*!< 1: RTC presclaer, from 0x0 to 0x7 */    
+    uint16_t bReserved2                 : 3;    /*!< reserved */ 
+    uint16_t bClockSource               : 2;    /*!< RTC clock source selection from 0x0 to 0x3 */
+    uint16_t u16ModuloValue                ;    /*!< 16-bit rtc modulo value */
+} RTC_ConfigType, *RTC_ConfigPtr; 
+
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/*!
+ * inline functions
+ */
+
+/******************************************************************************
+* RTC API list
+*
+*//*! @addtogroup rtc_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief enable rtc interrupt.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_EnableInt(void)
+{
+    RTC->SC |= RTC_SC_RTIE_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable rtc interrupt.
+*        
+* @param   none
+*
+* @return non
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_DisableInt(void)
+{
+    RTC->SC &= ~RTC_SC_RTIE_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief set rtc modulo value.
+*        
+* @param[in]   u16Mod_Value
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_SetModulo(uint16_t u16Mod_Value)
+{
+ 
+    RTC->MOD = u16Mod_Value;
+}
+
+/*****************************************************************************//*!
+*
+* @brief set rtc clock source and presalcer.
+*        
+* @param[in]   u16Clock_Number clock source number
+* @param[in]   u16Presalcer prescaler value
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_SetClock(uint16_t u16Clock_Number, uint16_t u16Presalcer)
+{
+    uint32_t u32rtc_sc;
+        
+    u32rtc_sc  = RTC->SC; 
+    u32rtc_sc &= ~(RTC_SC_RTCLKS_MASK | RTC_SC_RTCPS_MASK);
+    u32rtc_sc |= RTC_SC_RTCLKS(u16Clock_Number) | RTC_SC_RTCPS(u16Presalcer); 
+    RTC->SC   = u32rtc_sc;
+}
+
+/*****************************************************************************//*!
+*
+* @brief get rtc flag bit.
+*        
+* @param  none 
+*
+* @return bflag.
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t RTC_GetFlags(void)
+{
+  uint8_t bflag;
+  
+  bflag = RTC->SC & RTC_SC_RTIF_MASK; 
+  
+  return bflag;  
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief clear rtc flag bit.
+*        
+* @param  none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_ClrFlags(void)
+{
+    RTC->SC |= RTC_SC_RTIF_MASK; 
+}
+
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void RTC_Init(RTC_ConfigType *pConfig);
+void RTC_SetCallback(RTC_CallbackType pfnCallback);
+void RTC_DeInit(void);
+
+/*! @} End of rtc_api_list                                                   */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* RTC_H_ */
diff --git a/bsp/nv32f100x/lib/inc/sim.h b/bsp/nv32f100x/lib/inc/sim.h
new file mode 100644
index 0000000000..5a6a2ec8d3
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/sim.h
@@ -0,0 +1,2507 @@
+/******************************************************************************
+*
+* @brief header file for SIM utilities. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing SIM
+******************************************************************************/
+
+#ifndef SIM_H_
+#define SIM_H_
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* define SIM device ID types
+*
+*//*! @addtogroup sim_id_types
+* @{
+*******************************************************************************/
+
+typedef enum {
+    ID_TYPE_FAMID,                  /*!< device Family ID */
+    ID_TYPE_SUBFAMID,               /*!< device Subfamily ID */ 
+    ID_TYPE_REVID,                  /*!< device Revision ID */
+    ID_TYPE_PINID                   /*!< device Pin ID (Pin count) */
+} IDType;
+/*! @} End of sim_id_types                                                    					*/
+
+/******************************************************************************
+* Macros
+******************************************************************************/ 
+
+/******************************************************************************
+* Types
+******************************************************************************/
+    
+/* SIM configuration structure 
+ */ 
+ 
+/******************************************************************************
+* define SIM configuration structure
+*
+*//*! @addtogroup sim_config_type
+* @{
+*******************************************************************************/
+
+/*!
+ * @brief SIM configuration structure.
+ *
+ */
+#if defined(CPU_NV32)
+typedef struct{
+    struct{
+        uint32_t bEnableCLKOUT  : 1;        /*!< 1: enable , 0: disable */
+        uint32_t bTXDME         : 1;        /*!< 1: enable TXDME, 0: disable */
+        uint32_t bETMSYNC       : 1;        /*!< 1: enable ETM SYNC, 0: no sync */
+        uint32_t bRXDFE         : 1;        /*!< 1: enable RXD filter, 0: no filter */
+        uint32_t bRXDCE         : 1;        /*!< 1: enable RXD capture, 0: no capture */
+        uint32_t bACIC          : 1;        /*!< 1: ACMP0 to ETM1 channel0 connection, 0: no connection */
+        uint32_t bRTCC          : 1;        /*!< 1: RTC overflow connected to ETM1 channel1, 0: no connection */
+        uint32_t u8ADHWT        : 2;        /*!< ADC h/w trigger source selection */
+        uint32_t bDisableSWD    : 1;        /*!< 1: disable SWD, 0: enable */
+        uint32_t bDisableRESET  : 1;        /*!< 1: disable RESET pin, 0: enable */
+        uint32_t bDisableNMI    : 1;        /*!< 1: disable NMI pin, 0: enable */
+        uint32_t bBusDiv        : 1;        /*!< bus divider BUSDIV value */
+    } sBits;
+    uint8_t     u8Delay;                /*!< delay value */
+    uint8_t     u8BusRef;               /*!< bus reference */
+    uint32_t    u32PinSel;              /*!< pin select reg value */
+    uint32_t    u32SCGC;                /*!< clock gating value register */   
+} SIM_ConfigType, *SIM_ConfigPtr; /*!< sim configuration structure type */
+#elif defined(CPU_NV32M3)
+typedef struct{
+    struct{
+        uint32_t bEnableCLKOUT  : 1;        /*!< 1: enable , 0: disable */
+        uint32_t bTXDME         : 1;        /*!< 1: enable TXDME, 0: disable */
+        uint32_t bETMSYNC       : 1;        /*!< 1: enable ETM SYNC, 0: no sync */
+        uint32_t bRXDCE         : 1;        /*!< 1: enable RXD capture, 0: no capture */
+        uint32_t bRXDFE         : 2;        /*!< 1: enable RXD filter, 0: no filter */
+        uint32_t u8ADHWT        : 3;        /*!< ADC h/w trigger source selection */
+        uint32_t bETMIC         : 2;        /*!< ETM0CH0 input capture source selection */
+        uint32_t bACTRG         : 1;        /*!< ACMP Trigger ETM2 selection*/
+        uint32_t bDisableSWD    : 1;        /*!< 1: disable SWD, 0: enable */
+        uint32_t bDisableRESET  : 1;        /*!< 1: disable RESET pin, 0: enable */
+        uint32_t bDisableNMI    : 1;        /*!< 1: disable NMI pin, 0: enable */
+    } sBits;
+    uint8_t     u8Delay;                /*!< delay value */
+    uint8_t     u8BusRef;               /*!< bus reference */
+    uint32_t    u32PinSel;              /*!< pin select reg value */
+    uint32_t    u32SCGC;                /*!< clock gating value register */ 
+    uint32_t    u32CLKDIV;              /*!< clock divider CLKDIV value */   
+} SIM_ConfigType, *SIM_ConfigPtr; /*!< sim configuration structure type */
+#elif defined(CPU_NV32M4)
+typedef struct{
+    struct{
+        uint32_t bEnableCLKOUT  : 1;        /*!< 1: enable , 0: disable */
+        uint32_t bTXDME         : 1;        /*!< 1: enable TXDME, 0: disable */
+        uint32_t bETMSYNC       : 1;        /*!< 1: enable ETM SYNC, 0: no sync */
+        uint32_t bRXDCE         : 1;        /*!< 1: enable RXD capture, 0: no capture */
+        uint32_t bRXDFE         : 2;        /*!< 1: enable RXD filter, 0: no filter */
+        uint32_t u8ADHWT        : 3;        /*!< ADC h/w trigger source selection */
+        uint32_t bACTRG         : 1;        /*!< ACMP Trigger ETM2 selection*/
+        uint32_t bDisableSWD    : 1;        /*!< 1: disable SWD, 0: enable */
+        uint32_t bDisableRESET  : 1;        /*!< 1: disable RESET pin, 0: enable */
+        uint32_t bDisableNMI    : 1;        /*!< 1: disable NMI pin, 0: enable */
+    } sBits;
+    uint8_t     u8Delay;                /*!< delay value */
+    uint8_t     u8BusRef;               /*!< bus reference */
+    uint32_t    u32PinSel;              /*!< pin select reg value */
+    uint32_t    u32SCGC;                /*!< clock gating value register */ 
+    uint32_t    u32CLKDIV;              /*!< clock divider CLKDIV value */   
+} SIM_ConfigType, *SIM_ConfigPtr; /*!< sim configuration structure type */
+#endif
+/*! @} End of sim_config_type                                                    					*/
+  
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+/******************************************************************************
+* define SIM API list
+*
+*//*! @addtogroup sim_api_list
+* @{
+*******************************************************************************/
+#if defined(CPU_NV32)
+/*****************************************************************************//*!
+*
+* @brief delay ETM2 triggering ADC for u8Delay bus clock output divide. 
+*        
+* @param[in]   u8Delay     delay value of Bus clock output divide.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DelayETM2Trig2ADC(uint8_t u8Delay)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_DELAY_MASK)) | SIM_SOPT_DELAY(u8Delay);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_DisableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableClockOutput(void)
+{
+    SIM->SOPT |= (SIM_SOPT_CLKOE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_EnableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableClockOutput(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_CLKOE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus clock output divide. 
+*        
+* @param[in]  u8Divide     divide (3-bits)
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClockOutputDivide(uint8_t u8Divide)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_BUSREF_MASK)) | SIM_SOPT_BUSREF(u8Divide & 0x07);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 RXD connect with UART0 module  and ETM0 channel 1.. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0RXDConnectETMOCH1(void)
+{
+    SIM->SOPT |= (SIM_SOPT_RXDCE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Modulation(void)
+{
+    SIM->SOPT |= (SIM_SOPT_TXDME_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableUART0Modulation(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_TXDME_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief generate a softare sync trigger to ETM2 module (trigger).
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_GenerateSoftwareTrig2ETM2(void)
+{
+    SIM->SOPT |= (SIM_SOPT_ETMSYNC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 pin from default to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS3_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH1 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH1Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_UART0PS_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap SPI0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_SPI0PS_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap I2C pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2CPin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_IICPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 RX filter. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Filter(void)
+{
+    SIM->SOPT |= (SIM_SOPT_RXDFE_MASK);    
+}
+/******************************************************************************!
+
+* @function name: SIM_DisableUART0Filter
+*
+* @brief disable UART0 RX filter. 
+*        
+* @param         
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableUART0Filter(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_RXDFE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to RTC overflow. 
+*        
+* @param  none        
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByRTC(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ADHWT_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT . 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPIT(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 init trigger with 8-bit programmable delay. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Init(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(2);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 match trigger with 8-bit programmable delay. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Match(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(3);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable RTC capture to ETM1 input channel1. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableRTCCapture(void)
+{
+    SIM->SOPT |= (SIM_SOPT_RTCC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief disable RTC capture to ETM1 input channel1. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableRTCCapture(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_RTCC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable ACMP0 input capture to ETM1 input channel0. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableACMP0InputCapture(void)
+{
+    SIM->SOPT |= (SIM_SOPT_ACIC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief disable ACMP0 input capture to ETM1 input channel0. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableACMP0InputCapture(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ACIC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap RTC pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapRTCPin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_RTCPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus divide BUSDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetBusDivide(uint8_t u8Divide)
+{
+    SIM->BUSDIV = u8Divide;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH1 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH1Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS1_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS0_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH1 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH1Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM1PS1_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM1PS0_MASK;    
+}
+#elif defined(CPU_NV32M3)
+/*****************************************************************************//*!
+*
+* @brief delay ETM2 triggering ADC for u8Delay bus clock output divide. 
+*        
+* @param[in]   u8Delay     delay value of Bus clock output divide.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DelayETM2Trig2ADC(uint8_t u8Delay)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_DELAY_MASK)) | SIM_SOPT_DELAY(u8Delay);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_DisableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableClockOutput(void)
+{
+    SIM->SOPT |= (SIM_SOPT_CLKOE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_EnableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableClockOutput(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_CLKOE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus clock output divide. 
+*        
+* @param[in]  u8Divide     divide (3-bits)
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClockOutputDivide(uint8_t u8Divide)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_BUSREF_MASK)) | SIM_SOPT_BUSREF(u8Divide & 0x07);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 RXD connect with UART0 module  and ETM0 channel 1.. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0RXDConnectETMOCH1(void)
+{
+    SIM->SOPT |= (SIM_SOPT_RXDCE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Modulation(void)
+{
+    SIM->SOPT |= (SIM_SOPT_TXDME_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableUART0Modulation(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_TXDME_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief generate a softare sync trigger to ETM2 module (trigger).
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_GenerateSoftwareTrig2ETM2(void)
+{
+    SIM->SOPT |= (SIM_SOPT_ETMSYNC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 pin from default to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS3_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH1 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH1Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_UART0PS_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap SPI0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_SPI0PS_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap I2C pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2CPin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_IICPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is connected to UART0 module directly. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Filter(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_RXDFE_MASK);   
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is filtered by ACMP0, then injected to UART0. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0FilterByACMP0(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_RXDFE_MASK)) | SIM_SOPT_RXDFE(1);  
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is filtered by ACMP1, then injected to UART0. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0FilterByACMP1(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_RXDFE_MASK)) | SIM_SOPT_RXDFE(2);  
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to RTC overflow. 
+*        
+* @param  none        
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByRTC(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ADHWT_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM0 init trigger . 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPIT(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 init trigger with 8-bit programmable delay. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Init(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(2);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 match trigger with 8-bit programmable delay. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Match(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(3);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT channel0 overflow. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPITCH0Overflow(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(4);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT channel1 overflow. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPITChannel1Overflow(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(5);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ACMP0 out. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByACMP0Out(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(6);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ACMP1 out. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByACMP1Out(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(7);    
+}
+/*****************************************************************************//*!
+*
+* @brief Select ETM0CH0 as ETM0CH0 Input Capture Source. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelETM0CH0AsETM0CH0ICS(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ETMIC_MASK);   
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP0 OUT as ETM0CH0 Input Capture Source. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP0AsETM0CH0ICS(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ETMIC_MASK)) | SIM_SOPT_ETMIC(1);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP1 OUT as ETM0CH0 Input Capture Source. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP1AsETM0CH0ICS(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ETMIC_MASK)) | SIM_SOPT_ETMIC(2);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select RTC overflow as ETM0CH0 Input Capture Source. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelRTCOverflowAsETM0CH0ICS(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ETMIC_MASK)) | SIM_SOPT_ETMIC(3);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP0 output as the trigger0 input of ETM2. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP0AsETM2Trigger0(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ACTRG_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP1 output as the trigger0 input of ETM2. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP1AsETM2Trigger0(void)
+{
+    SIM->SOPT |= (SIM_SOPT_ACTRG_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief set clock3 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock3Divide(void)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV3_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock2 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock2Divide(void)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock1 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock1Divide(uint8_t u8divide)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV1(u8divide);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForPWT(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_PWTCLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForPWT(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_PWTCLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM2(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM2(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM2CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM0(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM0(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM0CLKPS_MASK;    
+}
+#elif defined(CPU_NV32M4)
+/*****************************************************************************//*!
+*
+* @brief delay ETM2 triggering ADC for u8Delay bus clock output divide. 
+*        
+* @param[in]   u8Delay     delay value of Bus clock output divide.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DelayETM2Trig2ADC(uint8_t u8Delay)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_DELAY_MASK)) | SIM_SOPT0_DELAY(u8Delay);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_DisableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableClockOutput(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_CLKOE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_EnableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableClockOutput(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_CLKOE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus clock output divide. 
+*        
+* @param[in]  u8Divide     divide (3-bits)
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClockOutputDivide(uint8_t u8Divide)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_BUSREF_MASK)) | SIM_SOPT0_BUSREF(u8Divide & 0x07);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 RXD connect with UART0 module  and ETM0 channel 1.. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0RXDConnectETMOCH1(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_RXDCE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Modulation(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_TXDME_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableUART0Modulation(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_TXDME_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief generate a softare sync trigger to ETM2 module (trigger).
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_GenerateSoftwareTrig2ETM2(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_ETMSYNC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN3 input signal from UART0RX.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+__STATIC_INLINE void SIM_SetPWTIN3InputFromUART0Rx(void)
+{
+    SIM->SOPT1 = (SIM->SOPT1 & (~SIM_SOPT1_UARTPWTS_MASK)) | SIM_SOPT1_UARTPWTS(0);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN3 input signal from UART1RX.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+__STATIC_INLINE void SIM_SetPWTIN3InputFromUART1Rx(void)
+{
+    SIM->SOPT1 = (SIM->SOPT1 & (~SIM_SOPT1_UARTPWTS_MASK)) | SIM_SOPT1_UARTPWTS(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN3 input signal from UART2RX.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+__STATIC_INLINE void SIM_SetPWTIN3InputFromUART2Rx(void)
+{
+    SIM->SOPT1 = (SIM->SOPT1 & (~SIM_SOPT1_UARTPWTS_MASK)) | SIM_SOPT1_UARTPWTS(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN2 input signal from ACMP0_OUT.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetPWTIN2InputFromACMP0(void)
+{
+    SIM->SOPT1 &= (~SIM_SOPT1_ACPWTS_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN2 input signal from ACMP1_OUT.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetPWTIN2InputFromACMP1(void)
+{
+    SIM->SOPT1 |= SIM_SOPT1_ACPWTS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief enable invertion of the I2C output.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableI2C0OuputInvertion(void)
+{
+    SIM->SOPT1 |= SIM_SOPT1_I2C0OINV_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief disable invertion of the I2C output.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableI2C0OuputInvertion(void)
+{
+    SIM->SOPT1 &= ~SIM_SOPT1_I2C0OINV_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief enable 4-wire I2C.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_Enable4WireI2C0(void)
+{
+    SIM->SOPT1 |= SIM_SOPT1_I2C04WEN_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief  disable 4-wire I2C..
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_Disable4WireI2C0(void)
+{
+    SIM->SOPT1 &= ~SIM_SOPT1_I2C04WEN_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is connected to UART0 module directly. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Filter(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_RXDFE_MASK);   
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is filtered by ACMP0, then injected to UART0. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0FilterByACMP0(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_RXDFE_MASK)) | SIM_SOPT0_RXDFE(1);  
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is filtered by ACMP1, then injected to UART0. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0FilterByACMP1(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_RXDFE_MASK)) | SIM_SOPT0_RXDFE(2);  
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to RTC overflow. 
+*        
+* @param  none        
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByRTC(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_ADHWT_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT . 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPIT(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 init trigger with 8-bit programmable delay. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Init(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(2);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 match trigger with 8-bit programmable delay. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Match(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(3);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT channel0 overflow. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPITCH0Overflow(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(4);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT channel1 overflow. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPITChannel1Overflow(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(5);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ACMP0 out. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByACMP0Out(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(6);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ACMP1 out. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByACMP1Out(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(7);    
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP0 output as the trigger0 input of ETM2. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP0AsETM2Trigger0(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_ACTRG_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP1 output as the trigger0 input of ETM2. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP1AsETM2Trigger0(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_ACTRG_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief enable RTC capture to ETM1 input channel1. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableRTCCapture(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_RTCC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable ACMP0 input capture to ETM1 input channel0. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableACMP0InputCapture(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_ACIC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK0 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK0ForPWT(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_PWTCLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForPWT(void)
+{
+    SIM->PINSEL = (SIM->PINSEL&(~SIM_PINSEL_PWTCLKPS_MASK)) | SIM_PINSEL_PWTCLKPS(1) ;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForPWT(void)
+{
+    SIM->PINSEL = (SIM->PINSEL&(~SIM_PINSEL_PWTCLKPS_MASK)) | SIM_PINSEL_PWTCLKPS(2) ;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK0 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK0ForETM2(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM2CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM2(void)
+{
+    SIM->PINSEL = (SIM->PINSEL & (~SIM_PINSEL_ETM2CLKPS_MASK)) | (((uint32_t)0x1)<<SIM_PINSEL_ETM2CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM2(void)
+{
+    SIM->PINSEL =(SIM->PINSEL & (~SIM_PINSEL_ETM2CLKPS_MASK)) | (((uint32_t)0x2)<<SIM_PINSEL_ETM2CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK0 for ETM1 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK0ForETM1(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM1CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM1 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM1(void)
+{
+    SIM->PINSEL = (SIM->PINSEL & (~SIM_PINSEL_ETM1CLKPS_MASK)) | (((uint32_t)0x1)<<SIM_PINSEL_ETM1CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM1 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM1(void)
+{
+    SIM->PINSEL = (SIM->PINSEL & (~SIM_PINSEL_ETM1CLKPS_MASK)) | (((uint32_t)0x2)<<SIM_PINSEL_ETM1CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK0 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK0ForETM0(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM0CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM0(void)
+{
+    SIM->PINSEL = (SIM->PINSEL &(~SIM_PINSEL_ETM0CLKPS_MASK)) | (((uint32_t)0x1)<<SIM_PINSEL_ETM0CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM0(void)
+{
+    SIM->PINSEL = (SIM->PINSEL &(~SIM_PINSEL_ETM0CLKPS_MASK)) | (((uint32_t)0x2)<<SIM_PINSEL_ETM0CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH1 to pin PTC5 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH1ToPTC5(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM1PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH1 to pin PTE7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH1ToPTE7(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM1PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH0 to pin PTC4 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH0ToPTC4(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM1PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH0 to pin PTH2. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH0ToPTH2(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM1PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH1 to pin PTA1 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH1ToPTA1(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH1 to pin PTB3. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH1ToPTB3(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM0PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH0 to pin PTA0 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH0ToPTA1(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH0 to pin PTB2. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH0ToPTB3(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM0PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART0 to pin PTB0/1 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART0ToPTB_0_1(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_UART0PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART0 to pin PTA2/3. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART0ToPTA_2_3(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_UART0PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap SPI0 to pin PTB2/3/4/5 (default).  
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI0ToPTB_2_3_4_5(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_SPI0PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap SPI0 to pin PTE01/2/3.  
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI0ToPTE_0_12_3(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_SPI0PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap I2C to pin PTA2/3 (default).  
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2CToPTA_2_3(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_I2C0PS_MASK;    
+}   
+/*****************************************************************************//*!
+*
+* @brief remap I2C to pin PTB6/7 (default).  
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2CToPTB_6_7(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_I2C0PS_MASK;    
+} 
+/*****************************************************************************//*!
+*
+* @brief remap RTC to pin PTC4 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapRTCToPTC4(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_RTCPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap RTC to pin PTC5. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapRTCToPTC5(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_RTCPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap MSCAN to pin PTC6/7 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapMSCANToPTC_6_7(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap MSCAN to pin PTH2/7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapMSCANToPTH_2_7(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap PWTIN1 to pin PTB0 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapPWTIN1ToPTB0(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap PWTIN1 to pin PTH7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapPWTIN1ToPTH7(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap PWTIN0 to pin PTD5 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapPWTIN0ToPTD5(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap PWTIN0 to pin PTE2. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapPWTIN0ToPTE2(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART2 to pin PTD6/7 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART2ToPTD_6_7(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_UART2PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART2 to pin PTI0/1. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART2ToPTI_0_1(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_UART2PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART1 to pin PTC6/7 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART1ToPTC_6_7(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_UART1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART1 to pin PTF2/3. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART1ToPTF_2_3(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_UART1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap SPI1 to pin PTD0/1/2/3 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI1ToPTD_0_1_2_3(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_SPI1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap SPI1 to pin PTG4/5/6/7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI1ToPTG_4_5_6_7(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_SPI1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap I2C1 to pin PTE0/1 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2C1ToPTE_0_1(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_I2C1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap I2C1 to pin PTH3/4. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2C1ToPTH_3_4(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_I2C1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH5 to pin PTB5 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH5ToPTB5(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS5_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH5 to pin PTG7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH5ToPTG7(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_ETM2PS5_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH4 to pin PTB4 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH4ToPTB4(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS4_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH4 to pin PTG6. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH4ToPTG6(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_ETM2PS4_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 to pin PTC3 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3ToPTC3(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS3_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 to pin PTD1. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3ToPTD1(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS3_MASK)) | SIM_PINSEL1_ETM2PS3(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 to pin PTG5. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3ToPTG5(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS3_MASK)) | SIM_PINSEL1_ETM2PS3(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 to pin PTC2 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2ToPTC2(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 to pin PTD0. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2ToPTD0(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS2_MASK)) | SIM_PINSEL1_ETM2PS2(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 to pin PTG4. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2ToPTG4(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS2_MASK)) | SIM_PINSEL1_ETM2PS2(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH1 to pin PTC1 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH1ToPTC1(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH1 to pin PTH1. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH1ToPTH1(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS1_MASK)) | SIM_PINSEL1_ETM2PS1(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH1 to pin PTF1. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH1ToPTF1(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS1_MASK)) | SIM_PINSEL1_ETM2PS1(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH0 to pin PTC0 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH0ToPTC0(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH0 to pin PTH0. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH0ToPTH0(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS0_MASK)) | SIM_PINSEL1_ETM2PS0(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH0 to pin PTF0. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH0ToPTF0(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 &(~SIM_PINSEL1_ETM2PS0_MASK)) | SIM_PINSEL1_ETM2PS0(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock3 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock3Divide(void)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV3_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock2 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock2Divide(void)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock1 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock1Divide(uint8_t u8divide)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV1(u8divide);    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus divide BUSDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetBusDivide(uint8_t u8Divide)
+{
+    SIM->CLKDIV = u8Divide;    
+}
+
+#endif
+
+
+/*! @} End of sim_api_list                                                   */
+
+void SIM_Init(SIM_ConfigType *pConfig);
+void SIM_SetClockGating(uint32_t u32PeripheralMask, uint8_t u8GateOn);
+uint32_t SIM_GetStatus(uint32_t u32StatusMask);
+uint8_t SIM_ReadID(IDType sID);
+
+#endif /* SIM_H_ */
+
+
diff --git a/bsp/nv32f100x/lib/inc/spi.h b/bsp/nv32f100x/lib/inc/spi.h
new file mode 100644
index 0000000000..8def944c79
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/spi.h
@@ -0,0 +1,634 @@
+/******************************************************************************
+*
+* @brief header file for SPI module utilities (SPI). 
+*
+*******************************************************************************
+*
+* provide APIs for accessing SPI module (SPI)
+******************************************************************************/
+
+#ifndef SPI_H_
+#define SPI_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+/* maximum number of SPIs */
+#define     MAX_SPI_NO              2
+
+
+
+/******************************************************************************
+* define SPI register default value
+*
+*//*! @addtogroup spi_default_value
+* @{
+*******************************************************************************/
+
+#define SPI_C1_DEFAULT          0x04						/*!< SPI C1 register */
+#define SPI_C2_DEFAULT          0x00						/*!< SPI C2 register */
+#define SPI_BR_DEFAULT          0x00						/*!< SPI BR register */
+#define SPI_S_DEFAULT           0x20						/*!< SPI S register */
+#define SPI_M_DEFAULT           0x00						/*!< SPI M register */
+/*! @} End of spi_default_value                                                    					*/
+
+/******************************************************************************
+* define SPI error status
+*
+*//*! @addtogroup spi_error_list
+* @{
+*******************************************************************************/
+
+#define     SPI_ERR_SUCCESS            0                                /*!< success */
+#define     SPI_ERR_CODE_BASE         ((uint32)SPI0 - 0x40000000L)      /*!< error code base for SPI */
+#define     SPI_ERR_TXBUF_NOT_EMPTY   (SPI_ERR_CODE_BASE+1)             /*!< failure due to SPTEF (empty) not set */
+#define     SPI_ERR_RXBUF_NOT_FULL    (SPI_ERR_CODE_BASE+2)             /*!< failure due to SPRF (full) not set */
+/*! @} End of spi_error_list                                            */
+        
+/******************************************************************************
+* Types
+******************************************************************************/
+
+typedef uint8_t   SPI_WidthType;  /* SPI width type */
+typedef uint32_t  ResultType;     /* SPI routine Result code */
+
+/******************************************************************************
+* define SPI call back funtion
+*
+*//*! @addtogroup spi_callback
+* @{
+*******************************************************************************/
+typedef void (*SPI_CallbackType)(void);  /*!< SPI call back function */
+/*! @} End of spi_callback                                            */
+
+/******************************************************************************
+*
+*//*! @addtogroup spi_setting_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief SPI setting type.
+ *
+ */
+typedef struct
+{
+    uint32_t bIntEn                               : 1; /*!< 1: Interrupt Enable, 0: Interrupt disable */
+    uint32_t bModuleEn                            : 1; /*!< 1: SPI module Enable, 0: SPI module disable */
+    uint32_t bTxIntEn                             : 1; /*!< 1: Tx Interrupt Enable, 0: Tx Interrupt disable */
+    uint32_t bMasterMode                          : 1; /*!< 1: Master mode, 0: Slave mode */
+    uint32_t bClkPolarityLow                      : 1; /*!< 1: Active-low SPI clock, 0: Active-HIgh SPI clock */
+    uint32_t bClkPhase1                           : 1; /*!< Set clock phase */
+    uint32_t bMasterAutoDriveSS                   : 1; /*!< Slave select output enable */
+    uint32_t bShiftLSBFirst                       : 1; /*!< 1: LSB first, 0: MSB first */
+    uint32_t bMatchIntEn                          : 1; /*!< 1: Match interrupt Enable, 0: Match interrupt disable */
+    uint32_t bModeFaultEn                         : 1; /*!< Master mode-fault function enable */
+    uint32_t bBidirectionModeEn                   : 1; /*!< Bidirectional mode output enable */
+    uint32_t bPinAsOuput                          : 1; /*!< enables bidirectional pin configurations */
+    uint32_t bStopInWaitMode                      : 1; /*!< SPI stop in wait mode */
+    uint32_t bRsvd                                : 19;
+} SPI_SettingType;
+/*! @} End of spi_setting_type                                            */
+
+/******************************************************************************
+*
+*//*! @addtogroup spi_config_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief SPI configuration type.
+ *
+ */
+typedef struct 
+{
+    SPI_SettingType     sSettings;              /*!< SPI settings */
+    uint32_t              u32BitRate;             /*!< set baud rate */
+    uint32_t              u32BusClkHz;            /*!< input bus clock */
+} SPI_ConfigType;                              /*!< SPI configuration structure */
+/*! @} End of spi_config_type                                            */
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* inline function
+******************************************************************************/
+/******************************************************************************
+*
+*//*! @addtogroup spi_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief LSB first (shifter direction).
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_SetLSBFirst(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_LSBFE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief MSB first (shifter direction).
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_SetMSBFirst(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_LSBFE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set SPI clock polarity.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   * @param[in]  u8PolLow   set clock polarity, 1 - Active-low SPI clock (idles high).  
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_SetClockPol(SPI_Type *pSPI,uint8_t u8PolLow)
+{
+	if( u8PolLow )
+	{
+		pSPI->C1 |= SPI_C1_CPOL_MASK;	
+	}
+	else
+	{
+		pSPI->C1 &= ~SPI_C1_CPOL_MASK;	
+	}
+}
+/*****************************************************************************//*!
+   *
+   * @brief set SPI clock phase.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   * @param[in]  u8Phase   set clock phase, 1 - First edge on SPSCK occurs at the start of the first cycle of a data transfer. 
+   * 
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_SetClockPhase(SPI_Type *pSPI,uint8_t u8Phase)
+{
+	if( u8Phase )
+	{
+		pSPI->C1 |= SPI_C1_CPHA_MASK;	
+	}
+	else
+	{
+		pSPI->C1 &= ~SPI_C1_CPHA_MASK;	
+	}
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable SPI module.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_Enable(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_SPE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief disable SPI module.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *  
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_Disable(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_SPE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable SPI interrupt.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_IntEnable(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_SPIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief disable SPI interrupt.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_IntDisable(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_SPIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set SPI to master mode.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_SetMasterMode(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_MSTR_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set SPI to slave mode.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_SetSlaveMode(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_MSTR_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI transmit interrupt enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_TxIntEnable(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_SPTIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI transmit interrupt disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_TxIntDisable(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_SPTIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Slave select output enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_SSOutputEnable(SPI_Type *pSPI )
+{
+	pSPI->C1 |= SPI_C1_SSOE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Slave select output disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_SSOutputDisable(SPI_Type *pSPI )
+{
+	pSPI->C1 &= ~SPI_C1_SSOE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI match interrupt enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   * 
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_MatchIntEnable(SPI_Type *pSPI )
+{
+	pSPI->C2 |= SPI_C2_SPMIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI match interrupt disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_MatchIntDisable(SPI_Type *pSPI )
+{
+	pSPI->C2 &= ~SPI_C2_SPMIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Master mode-fault function disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_ModfDisable(SPI_Type *pSPI )
+{
+	pSPI->C2 &= ~SPI_C2_MODFEN_MASK;
+}
+/*****************************************************************************//*!
+
+   *
+   * @brief Master mode-fault function enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_ModfEnable(SPI_Type *pSPI )
+{
+	pSPI->C2 |= SPI_C2_MODFEN_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Bidirectional mode output enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_BidirOutEnable(SPI_Type *pSPI )
+{
+	pSPI->C2 |= SPI_C2_BIDIROE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Bidirectional mode output disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_BidirOutDisable(SPI_Type *pSPI )
+{
+	pSPI->C2 &= ~SPI_C2_BIDIROE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI stop in wait mode
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   * 
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_ClockStopDisable(SPI_Type *pSPI )
+{
+	pSPI->C2 &= ~SPI_C2_SPISWAI_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI stop in wait mode.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *  
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_ClockStopEnable(SPI_Type *pSPI )
+{
+	pSPI->C2 |= SPI_C2_SPISWAI_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enables bidirectional pin configurations.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *   
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_BidirPinEnable(SPI_Type *pSPI)
+{
+	pSPI->C2 |= SPI_C2_SPC0_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enables bidirectional pin configurations.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *   
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_BidirPinDisable(SPI_Type *pSPI)
+{
+	pSPI->C2 &= ~SPI_C2_SPC0_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SPI read buffer full flag.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return  TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_IsSPRF(SPI_Type *pSPI )
+{
+	return(pSPI->S & SPI_S_SPRF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SPI match flag.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return  TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_IsSPMF(SPI_Type *pSPI )
+{
+	return(pSPI->S & SPI_S_SPMF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SPI transmit buffer empty flag.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return  TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_IsSPTEF(SPI_Type *pSPI )
+{
+	return(pSPI->S & SPI_S_SPTEF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check master mode fault flag.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return  TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_IsMODF(SPI_Type *pSPI )
+{
+	return(pSPI->S & SPI_S_MODF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief read SPI data register.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return data register value
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_ReadDataReg(SPI_Type *pSPI )
+{
+	return pSPI->D;
+}
+/*****************************************************************************//*!
+   *
+   * @brief write SPI data register.
+   *        
+   * @param[in]  pSPI   point to SPI module type. 
+   * @param[in]  u8WrBuff   data buffer write to spi data register. 
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_WriteDataReg(SPI_Type *pSPI, uint8_t u8WrBuff )
+{
+	pSPI->D = u8WrBuff;
+}
+/*****************************************************************************//*!
+   *
+   * @brief write SPI match  register.
+   *        
+   * @param[in]  pSPI   point to SPI module type. 
+   * @param[in]  u8WrBuff   the data buffer write to match register. 
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_WriteMatchValue(SPI_Type *pSPI, uint8_t u8WrBuff )
+{
+	pSPI->M = u8WrBuff;
+}
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void SPI_Enable(SPI_Type *pSPI);
+void SPI_Disable(SPI_Type *pSPI);
+void SPI_SetLSBFirst(SPI_Type *pSPI);
+void SPI_SetMSBFirst(SPI_Type *pSPI);
+void SPI_IntEnable(SPI_Type *pSPI);
+void SPI_IntDisable(SPI_Type *pSPI);
+void SPI_SetMasterMode(SPI_Type *pSPI);
+void SPI_SetSlaveMode(SPI_Type *pSPI);
+void SPI_TxIntEnable(SPI_Type *pSPI);
+void SPI_TxIntDisable(SPI_Type *pSPI);
+void SPI_SSOutputEnable(SPI_Type *pSPI );
+void SPI_SSOutputDisable(SPI_Type *pSPI );
+void SPI_MatchIntEnable(SPI_Type *pSPI );
+void SPI_MatchIntDisable(SPI_Type *pSPI );
+void SPI_ModfDisable(SPI_Type *pSPI );
+void SPI_ModfEnable(SPI_Type *pSPI );
+void SPI_BidirOutEnable(SPI_Type *pSPI );
+void SPI_BidirOutDisable(SPI_Type *pSPI );
+void SPI_ClockStopDisable(SPI_Type *pSPI );
+void SPI_ClockStopEnable(SPI_Type *pSPI );
+void SPI_BidirPinEnable(SPI_Type *pSPI );
+void SPI_BidirPinDisable(SPI_Type *pSPI );
+void SPI_SetClockPol(SPI_Type *pSPI,uint8_t u8PolLow);
+void SPI_SetClockPhase(SPI_Type *pSPI,uint8_t u8Phase);
+void SPI_SetBaudRate(SPI_Type *pSPI,uint32_t u32BusClock,uint32_t u32Bps );
+uint8_t SPI_IsSPRF(SPI_Type *pSPI );
+uint8_t SPI_IsSPMF(SPI_Type *pSPI );
+uint8_t SPI_IsSPTEF(SPI_Type *pSPI );
+uint8_t SPI_IsMODF(SPI_Type *pSPI );
+uint8_t SPI_ReadDataReg(SPI_Type *pSPI );
+void SPI_WriteDataReg(SPI_Type *pSPI, uint8_t u8WrBuff );
+void SPI_WriteMatchValue(SPI_Type *pSPI, uint8_t u8WrBuff );
+void SPI_Init(SPI_Type *pSPI, SPI_ConfigType *pConfig);
+void SPI_DeInit(SPI_Type *pSPI);
+ResultType SPI_TransferWait(SPI_Type *pSPI, SPI_WidthType* pRdBuff, SPI_WidthType *pWrBuff,uint32 uiLength);
+void SPI_SetCallback(SPI_Type *pSPI,SPI_CallbackType pfnCallback);
+
+/*! @} End of spi_api_list                                            */
+#ifdef __cplusplus
+}
+#endif
+#endif /* SPI_H_ */
diff --git a/bsp/nv32f100x/lib/inc/uart.h b/bsp/nv32f100x/lib/inc/uart.h
new file mode 100644
index 0000000000..20354933d8
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/uart.h
@@ -0,0 +1,496 @@
+/******************************************************************************
+*
+* @brief provide commond UART utilities. 
+*
+*******************************************************************************/
+#ifndef _UART_H_
+#define _UART_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+#include "common.h"
+#include "wdog.h"
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+#define MAX_UART_NO             3
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/******************************************************************************
+*define uart setting type
+*
+*//*! @addtogroup uart_setting_type
+* @{
+*******************************************************************************/  
+
+/*!
+* @brief UART setting type.
+*
+*/ 
+
+typedef struct
+{
+    uint32_t bEnable      : 1;                /*!< 1: enable, 0: disable */
+    uint32_t resvd        : 31;               /*!< 1: reserved bit field */
+} UART_SettingType;
+/*! @} End of uart_setting_type */
+
+/******************************************************************************
+*define uart config type
+*
+*//*! @addtogroup uart_config_type
+* @{
+******************************************************************************/
+ /*!
+ * @brief UART Configuration structure.
+ *
+ */   
+typedef struct 
+{
+    UART_SettingType    sSettings;              /*!< UART settings */
+    uint32_t    u32SysClkHz;        /*!< system clock */
+    uint32_t    u32Baudrate;        /*!< UART baudrate */
+} UART_ConfigType;
+/*! @} End of uart_config_type  */
+
+/******************************************************************************
+*define uart config baudrate type
+*
+*//*! @addtogroup uart_config_baudrate_type
+* @{
+******************************************************************************/
+ /*!
+ * @brief UART baudrate type structure.
+ *
+ */   
+typedef struct
+{
+    uint32_t    u32SysClkHz;        /*!< system clock */
+    uint32_t    u32Baudrate;        /*!< UART baudrate */
+} UART_ConfigBaudrateType;
+/*! @} End of uart_config_baudrate_type */
+
+/******************************************************************************
+*define uart config mode type list
+*
+*//*! @addtogroup uart_mode_type_list
+* @{
+******************************************************************************/
+typedef enum
+{
+    UART_Mode8Bit,                  /*!< 8 bit mode */
+    UART_Mode9Bit,                  /*!< 9 bit mode */
+    UART_ModeEnableLoopback,        /*!< enable looback mode */
+    UART_ModeDisableLoopback,       /*!< disable loopback mode*/
+    UART_ModeEnableSingleWire,      /*!< enable single wire mode */
+    UART_ModeDisableSingleWire,     /*!< disable single wire mode */
+} UART_ModeType;
+/*! @} End of uart_mode_type_list   */
+
+/******************************************************************************
+*define uart interrupt type list
+*
+*//*! @addtogroup uart_interrupt_type_list
+* @{
+******************************************************************************/
+
+typedef enum
+{
+    UART_TxBuffEmptyInt,            /*!< transmit buffer empty interrupt */
+    UART_TxCompleteInt,             /*!< transmit complete interrupt */
+    UART_RxBuffFullInt,             /*!< receive buffer full interrupt */
+
+    UART_IdleLineInt,               /*!< idle line interrupt */
+
+    UART_RxOverrunInt,              /*!< receive overrun interrupt */
+    UART_NoiseErrorInt,             /*!< noise error interrupt */
+    UART_FramingErrorInt,           /*!< framing error interrupt */
+    UART_ParityErrorInt,            /*!< parity error interrupt */
+} UART_InterruptType;
+/*! @} End of uart_interrupt_type_list  */
+
+/******************************************************************************
+*define uart flag type list
+*
+*//*! @addtogroup uart_flag_type_list
+* @{
+******************************************************************************/
+typedef enum
+{
+    UART_FlagPF = 0,        /*!< Parity error flag */
+    UART_FlagFE,            /*!< Framing error flag */
+    UART_FlagNF,            /*!< Noise flag */
+    UART_FlagOR,            /*!< Receive overrun */
+    UART_FlagIDLE,          /*!< Idle line flag */
+    UART_FlagRDRF,          /*!< Receive data register full flag */
+    UART_FlagTC,            /*!< Transmission complete flag */
+    UART_FlagTDRE,          /*!< Transmit data register flag */
+
+    UART_FlagRAF,           /*!< Receiver active flag */
+    UART_FlagLBKDE,         /*!< LIN break detection enable */
+    UART_FlagBRK13,         /*!< Break character generation length */ 
+    UART_FlagRWUID,         /*!< Receive wake up idle detect */
+    UART_FlagRXINV,         /*!< Receive data inversion */
+    UART_FlagRev1,          /*!< Reserved */
+    UART_FlagRXEDGIF,       /*!< RxD pin active edge interrupt flag */
+    UART_FlagLBKDIF,        /*!< LIN break detect interrupt flag */
+} UART_FlagType;
+/*! @} End of uart_flag_type_list   */
+
+/* callback types */
+typedef void (*UART_CallbackType)(UART_Type *pUART);
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Inline functions
+******************************************************************************/
+
+/******************************************************************************
+* define UART APIs
+*
+*//*! @addtogroup uart_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief read receive buffer
+*        
+* @param[in] pUART       base of UART port
+*
+* @return unsign char received char
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_ReadDataReg(UART_Type *pUART)
+{
+    /* Return the 8-bit data from the receiver */
+    return pUART->D;
+}
+/*****************************************************************************//*!
+*
+* @brief write transmit buffer
+*        
+* @param[in] pUART       base of UART port
+* @param[in] u8Char      char to send
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_WriteDataReg(UART_Type *pUART, uint8_t u8Char)
+{
+    /* Send the character */
+    pUART->D = (uint8_t)u8Char;
+}
+
+/*****************************************************************************//*!
+*
+* @brief check if a character has been received
+*
+* @param[in] pUART  base of UART port
+*
+* @return 0, No character received; no-zero, Character has been received
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_CharPresent(UART_Type *pUART)
+{  
+    return (pUART->S1 & UART_S1_RDRF_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief enable transmit
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableTx(UART_Type *pUART)
+{
+    
+    pUART->C2 |= UART_C2_TE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief disable transmit
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableTx(UART_Type *pUART)
+{    
+    pUART->C2 &= (~UART_C2_TE_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief enable receive
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableRx(UART_Type *pUART)
+{    
+    pUART->C2 |= UART_C2_RE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief disable receive
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableRx(UART_Type *pUART)
+{    
+    pUART->C2 &= (~UART_C2_RE_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief Enable loopback mode
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableLoopback(UART_Type *pUART)
+{
+    pUART->C1 |= UART_C1_LOOPS_MASK;
+    pUART->C1 &= (~UART_C1_RSRC_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief enable single wire mode
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableSingleWire(UART_Type *pUART)
+{
+    pUART->C1 |= UART_C1_LOOPS_MASK;
+    pUART->C1 |= UART_C1_RSRC_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief set 8-bit mode
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_Set8BitMode(UART_Type *pUART)
+{
+    pUART->C1 &= (~UART_C1_M_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief set 9-bit mode
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_Set9BitMode(UART_Type *pUART)
+{
+    pUART->C1 |= UART_C1_M_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief enable transmit buffer empty interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableTxBuffEmptyInt(UART_Type *pUART)
+{
+    pUART->C2 |= UART_C2_TIE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief enable transmit complete interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableTxCompleteInt(UART_Type *pUART)
+{
+    pUART->C2 |= UART_C2_TCIE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief enable receive buffer full interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableRxBuffFullInt(UART_Type *pUART)
+{
+    pUART->C2 |= UART_C2_RIE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief disable transmit buffer empty interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableTxBuffEmptyInt(UART_Type *pUART)
+{
+        pUART->C2 &= (~UART_C2_TIE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief disable transmit complete interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableTxCompleteInt(UART_Type *pUART)
+{
+    pUART->C2 &= (~UART_C2_TCIE_MASK);   
+}
+/*****************************************************************************//*!
+*
+* @brief disable receive buffer full interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableRxBuffFullInt(UART_Type *pUART)
+{
+    pUART->C2 &= (~UART_C2_RIE_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief print out break character
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_PutBreak(UART_Type *pUART)
+{
+    /* Write 1 then write 0 to UART_C2[SBK] bit, will put break character */
+    pUART->C2 |= UART_C2_SBK_MASK; 
+    pUART->C2 &= (~UART_C2_SBK_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief check whether tx is complete,i.e. data has been sent out.
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       
+*               1, Tx complete flag is set
+*               0, Tx complete flag is clear
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_IsTxComplete(UART_Type *pUART)
+{
+    return (pUART->S1 & UART_S1_TC_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief check whether Tx buffer is empty
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       
+*               1, Tx buffer is empty
+*               0, Tx buffer is not empty
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_IsTxBuffEmpty(UART_Type *pUART)
+{
+    return (pUART->S1 & UART_S1_TDRE_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief check whether Rx buffer is full, i.e. receive a character
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       
+*               1, Rx buffer is full
+*               0, Rx buffer is not full
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_IsRxBuffFull(UART_Type *pUART)
+{
+    return (pUART->S1 & UART_S1_RDRF_MASK);
+}
+/*! @} End of uart_api_list */
+
+
+/******************************************************************************
+* Global functions declaration
+******************************************************************************/
+void UART_Init(UART_Type *pUART, UART_ConfigType *pConfig);
+uint8_t UART_GetChar(UART_Type *pUART);
+void UART_PutChar(UART_Type *pUART, uint8_t u8Char);
+void UART_SetBaudrate(UART_Type *pUART, UART_ConfigBaudrateType *pConfig);
+void UART_EnableInterrupt(UART_Type *pUART, UART_InterruptType InterruptType);
+void UART_DisableInterrupt(UART_Type *pUART, UART_InterruptType InterruptType);
+uint16_t UART_GetFlags(UART_Type *pUART);
+uint8_t UART_CheckFlag(UART_Type *pUART, UART_FlagType FlagType);
+void UART_SendWait(UART_Type *pUART, uint8_t *pSendBuff, uint32_t u32Length);
+void UART_ReceiveWait(UART_Type *pUART, uint8_t *pReceiveBuff, uint32_t u32Length);
+void UART_WaitTxComplete(UART_Type *pUART);
+void UART_SetCallback(UART_CallbackType pfnCallback);
+void UART0_Isr(void);
+void UART1_Isr(void);
+void UART2_Isr(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* #ifndef _UART_H_ */
diff --git a/bsp/nv32f100x/lib/inc/wdog.h b/bsp/nv32f100x/lib/inc/wdog.h
new file mode 100644
index 0000000000..75b79ca417
--- /dev/null
+++ b/bsp/nv32f100x/lib/inc/wdog.h
@@ -0,0 +1,203 @@
+
+/******************************************************************************
+* @brief provide commond watch dog utilities. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing watch dog
+******************************************************************************/
+
+#ifndef __WDOG_H__
+#define __WDOG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+#include "sim.h"
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+/* wdog_unlock sequence must be performed within 16 bus clock cycles without
+ * any interrupt 
+ */
+
+   
+/* WDOG clock sources option */
+/******************************************************************************
+* define watchdog clock source selection
+*
+*//*! @addtogroup wdog_clock_sources
+* @{
+*******************************************************************************/
+
+#define WDOG_CLK_BUS                    0   /*!< clock source is bus clock */
+#define WDOG_CLK_INTERNAL_32KHZ         2   /*!< clock source is internal oscillator 32 kHz (ICSIRCLK) */
+#define WDOG_CLK_INTERNAL_1KHZ	        1   /*!< clock source is internal LPO 1 KHz */
+#define WDOG_CLK_EXTERNAL               3   /*!< clock source is external clock */
+/*! @} End of wdog_clock_sources                                                    					*/
+
+/* WDOG clock source selection */
+#define WDOG_CLK  (WDOG_CLK_INTERNAL_1KHZ)
+    
+/* WDOG default values */
+#define WDOG_CS1_DEFAULT_VALUE      0x80
+#define WDOG_CS2_DEFAULT_VALUE      0x01
+#define WDOG_TOVAL_DEFAULT_VALUE    0x0400
+#define WDOG_WIN_DEFAULT_VALUE      0x0000
+     
+/* WDOG utilities */  
+
+/******************************************************************************
+* define watchdog API list
+*
+*//*! @addtogroup wdog_api_list
+* @{
+*******************************************************************************/
+/*! 
+ * @brief watchdog unlock routine.
+ */
+#define WDOG_Unlock()        WDOG->CNT = 0x20C5; WDOG->CNT = 0x28D9        
+//#define WDOG_Unlock()       DisableInterrupts; WDOG->CNT = 0x20C5; WDOG->CNT = 0x28D9; EnableInterrupts        
+/*! @} End of wdog_api_list                                                    					*/
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/******************************************************************************
+* define watchdog configuration structure
+*
+*//*! @addtogroup wdog_config_type
+* @{
+*******************************************************************************/
+
+/*!
+ * @brief watchdog configuration structure.
+ *
+ */
+typedef struct {	
+    struct {
+	uint16_t    bIntEnable      : 1;    /*!< watchdog interrupt enable */
+	uint16_t    bDisable        : 1;    /*!< disable watchdog */
+	uint16_t    bWaitEnable     : 1;    /*!< enable watchdog in wait mode */
+	uint16_t    bStopEnable     : 1;    /*!< enable watchdog in stop mode */
+	uint16_t    bDbgEnable      : 1;    /*!< enable watchdog in debug mode */
+	uint16_t    bWinEnable      : 1;    /*!< enable watchdog window mode */
+	uint16_t    bUpdateEnable   : 1;    /*!< enable update of watchdog control */
+	uint16_t    bClkSrc         : 2;    /*!< watchdog clock source selection */  
+	uint16_t    bPrescaler      : 1;    /*!< prescaler */  
+    }sBits;                             /*!< bitfield structure  */
+    uint16_t    u16ETMeOut;             /*!< watchdog ETMeout value */
+    uint16_t    u16WinETMe;             /*!< watchdog window value */
+} WDOG_ConfigType, *WDOG_ConfigPtr;  /*!< watchdog configuration structure type */
+/*! @} End of wdog_config_type                                                    					*/
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define watchdog API list
+*
+*//*! @addtogroup wdog_api_list
+* @{
+*******************************************************************************/
+
+
+/*****************************************************************************//*!
+*
+* @brief set ETMe out value for WDOG.
+*        
+* @param[in]   u16ETMeOut  ETMeout value to TOVAL register.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*
+*****************************************************************************/
+
+__STATIC_INLINE void WDOG_SetETMeOut(uint16_t u16ETMeOut)
+{
+    WDOG->CNT = 0x20C5; 
+    WDOG->CNT = 0x28D9;
+    WDOG->TOVAL8B.TOVALL  = u16ETMeOut;
+    WDOG->TOVAL8B.TOVALH  = u16ETMeOut >> 8;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief set window value for WDOG.
+*        
+* @param[in]   u16WinETMe  window value to WIN register.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*
+*****************************************************************************/
+
+__STATIC_INLINE void WDOG_SetWindow(uint16_t u16WinETMe)
+{
+    WDOG->CNT = 0x20C5; 
+    WDOG->CNT = 0x28D9;
+    WDOG->WIN8B.WINL  = u16WinETMe;
+    WDOG->WIN8B.WINH  = u16WinETMe >> 8;
+}
+
+/*****************************************************************************//*!
+*
+* @brief check if watchdog reset occurs.
+*        
+* @param    none.
+*
+* @return   TRUE if watchdog reset occurs, FALSE otherwise.
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+__STATIC_INLINE uint8_t WDOG_IsReset(void)
+{
+    if(SIM_GetStatus(SIM_SRSID_WDOG_MASK))
+    {
+        return (TRUE);
+    }
+    return (FALSE);
+}
+
+/*! @} End of wdog_api_list                                                    					*/
+
+
+void WDOG_Init(WDOG_ConfigPtr pConfig);
+void WDOG_DeInit(void);
+void WDOG_Disable(void);
+void WDOG_DisableWDOGEnableUpdate(void);
+void WDOG_Enable(void);
+void WDOG_Feed(void);
+void WDOG_SetETMeOut(uint16_t u16ETMeOut);
+void WDOG_SetWindow(uint16_t u16WinETMe);
+void WDOG_EnableUpdate(void);
+void WDOG_DisableUpdate(void);
+uint8_t WDOG_IsReset(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/********************************************************************/
+#endif /* __WDOG_H__ */
+
diff --git a/bsp/nv32f100x/lib/src/acmp.c b/bsp/nv32f100x/lib/src/acmp.c
new file mode 100644
index 0000000000..5739f767bb
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/acmp.c
@@ -0,0 +1,215 @@
+
+/******************************************************************************
+*
+* @brief providing APIs for configuring ACMP. 
+*
+*******************************************************************************
+*
+* provide APIs for configuring ACMP
+******************************************************************************/
+#include "common.h"
+#include "acmp.h"
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+ACMP_CallbackPtr ACMP_Callback[2] = {(ACMP_CallbackPtr)NULL};
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void ACMP0_Isr(void);
+void ACMP1_Isr(void);
+
+/******************************************************************************
+* ACMP api list.
+*
+*//*! @addtogroup acmp_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize ACMP as per control field.
+*        
+* @param   pACMPx         pointer to an ACMP register base.
+* @param   pConfig        control parameters.  
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see   ACMP_DeInit.  
+*
+*****************************************************************************/
+void ACMP_Init(ACMP_Type *pACMPx, ACMP_ConfigType *pConfig) 
+{
+    if(ACMP0 == pACMPx)
+    {    
+        /* enable clock to ACMP */
+        SIM->SCGC |= SIM_SCGC_ACMP0_MASK;
+ 
+        /* enable ACMP interrupt */
+        if(pConfig->sCtrlStatus.bits.bIntEn)
+            NVIC_EnableIRQ(ACMP0_IRQn);
+    }
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_ACMP1_MASK;
+        if(pConfig->sCtrlStatus.bits.bIntEn)
+            NVIC_EnableIRQ(ACMP1_IRQn);            
+    }
+    /* neg and pos pin are not equal */
+    pACMPx->C0 = pConfig->sPinSelect.byte;
+    ACMP_ConfigDAC(pACMPx, &pConfig->sDacSet );
+    //pACMPx->C1 = pConfig->sDacSet.byte;
+    pACMPx->C2 = pConfig->sPinEnable.byte;
+    pACMPx->CS = pConfig->sCtrlStatus.byte;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief write ACMP register bits.
+*        
+* @param   pACMPx      pointer to an ACMP register base.
+* @param   pDACConfig   pointer to an ACMP DAC control structure.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void ACMP_ConfigDAC(ACMP_Type *pACMPx, ACMP_DACType *pDACConfig) 
+{
+    pACMPx->C1 = pDACConfig->byte;  
+}
+
+/*****************************************************************************//*!
+*
+* @brief deinit ACMP module.
+*        
+* @param   pACMPx      pointer to an ACMP register base.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see   ACMP_Init.  
+*
+*****************************************************************************/
+void ACMP_DeInit(ACMP_Type *pACMPx) 
+{
+    if(ACMP0 == pACMPx)
+    {    
+        if(pACMPx->CS & ACMP_CS_ACIE_MASK)
+            NVIC_DisableIRQ(ACMP0_IRQn);
+    }
+    else
+    {
+        if(pACMPx->CS & ACMP_CS_ACIE_MASK)
+            NVIC_DisableIRQ(ACMP1_IRQn);            
+    }
+    
+    pACMPx->CS = 0;
+    pACMPx->C0 = 0;
+    pACMPx->C1 = 0;
+    pACMPx->C2 = 0;
+    
+    if(ACMP0 == pACMPx)
+    {    
+        SIM->SCGC &= ~SIM_SCGC_ACMP0_MASK;
+    }
+    else
+    {
+        SIM->SCGC &= ~SIM_SCGC_ACMP1_MASK;           
+    } 
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set up ACMP callback routines to be called by interrupt service routine.
+*        
+* @param  pACMPx       pointer to an ACMP register base. 
+* @param   pfnCallback  callback routine.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void ACMP_SetCallback(ACMP_Type *pACMPx, ACMP_CallbackPtr pfnCallback)
+{
+    if(ACMP0 == pACMPx)
+    {
+        ACMP_Callback[0] = pfnCallback;
+    }
+    else
+    {
+        ACMP_Callback[1] = pfnCallback;
+    }
+}
+
+/*! @} End of acmp_api_list                                                  */
+
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP0 interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void ACMP0_Isr(void)
+{
+
+    if(ACMP_Callback[0])
+    {
+        ACMP_Callback[0]();             /* call callback routine */
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP1 interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void ACMP1_Isr(void)
+{
+
+    if(ACMP_Callback[1])
+    {
+        ACMP_Callback[1]();             /* call callback routine */
+    }
+}
+
+
diff --git a/bsp/nv32f100x/lib/src/adc.c b/bsp/nv32f100x/lib/src/adc.c
new file mode 100644
index 0000000000..b9ec2ff151
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/adc.c
@@ -0,0 +1,336 @@
+/******************************************************************************
+* @brief providing APIs for configuring ADC module (ADC). 
+*
+*******************************************************************************
+*
+* provide APIs for configuring ADC module (ADC)
+******************************************************************************/
+#include "common.h"
+#include "adc.h"
+/******************************************************************************
+* Local function
+******************************************************************************/
+ADC_CallbackType ADC_Callback[1] = {NULL};
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* define ADC APIs
+*
+*//*! @addtogroup adc_api_list
+* @{
+*******************************************************************************/
+
+
+/*****************************************************************************//**
+   *
+   * @brief initialize ADC module.
+   *
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  pADC_Config point to ADC configuration structure. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_Init(ADC_Type *pADC, ADC_ConfigTypePtr pADC_Config)
+{
+    if( pADC == ADC)
+    {
+        SIM->SCGC |= SIM_SCGC_ADC_MASK;
+    }
+
+    /* set clock cource for ADC */
+    ADC_SelectClock(pADC,pADC_Config->u8ClockSource);
+
+    /* set clock divide */
+    ADC_SelectClockDivide(pADC,pADC_Config->u8ClockDiv);
+
+    /* set ADC mode */
+    ADC_SetMode(pADC,pADC_Config->u8Mode);
+
+    /* set FIFO level */
+    ADC_SetFifoLevel(pADC,pADC_Config->u8FiFoLevel);
+
+    /* set pin control */
+    pADC->APCTL1 = pADC_Config->u16PinControl;
+
+    if( pADC_Config->sSetting.bCompareEn )
+    {
+        ADC_CompareEnable(pADC);
+    }
+    
+    if( pADC_Config->sSetting.bCompareGreaterEn )
+    {
+        ADC_CompareGreaterFunction(pADC);
+    }
+        
+    if( pADC_Config->sSetting.bContinuousEn )
+    {
+        ADC_ContinuousConversion(pADC);
+    }
+        
+    if( pADC_Config->sSetting.bCompareAndEn ) 
+    {
+        ADC_CompareFifoAnd(pADC);
+    }
+    
+    if( pADC_Config->sSetting.bFiFoScanModeEn )
+    {
+        ADC_FifoScanModeEnable(pADC);
+    }
+    
+    if( pADC_Config->sSetting.bHardwareTriggerEn )
+    {
+        ADC_SetHardwareTrigger(pADC);
+    }
+
+    if( pADC_Config->sSetting.bIntEn )
+    {
+        ADC_IntEnable(pADC);
+        NVIC_EnableIRQ( ADC0_IRQn );
+    } 
+
+    if( pADC_Config->sSetting.bLongSampleEn )
+    {
+        ADC_SetLongSample(pADC);
+    } 
+
+    if( pADC_Config->sSetting.bLowPowerEn )
+    {
+        ADC_SetLowPower(pADC);
+    }
+
+#if !defined(CPU_NV32)
+
+    if( pADC_Config->sSetting.bHTRGMEn )
+    {
+        ADC_HardwareTriggerMultiple(pADC);
+    }
+    else
+    {
+		ADC_HardwareTriggerSingle(pADC);
+    }
+    if( pADC_Config->sSetting.bHTRGMASKEn )
+    {
+        ADC_HardwareTriggerMaskEnable(pADC);
+    }
+    else
+    {
+		ADC_HardwareTriggerMaskDisable(pADC);
+    }
+    if( pADC_Config->sSetting.bHTRGMASKSEL )
+    {
+        ADC_HardwareTriggerMaskAuto(pADC);
+    }
+    else
+    {
+		ADC_HardwareTriggerMaskNonAuto(pADC);
+    }
+#endif
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief disable ADC module.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void ADC_DeInit( ADC_Type *pADC )
+{
+    ADC_SetChannel(pADC,ADC_CHANNEL_DISABLE);
+
+    SIM->SCGC &= ~SIM_SCGC_ADC_MASK;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief start a conversion and get conversion result
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Channel adc channel to conversion. 
+   *
+   * @return ADC conversion result.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+unsigned int ADC_PollRead( ADC_Type *pADC, uint8_t u8Channel )
+{
+		ADC_SetChannel(pADC,u8Channel);
+		while( !ADC_IsCOCOFlag(pADC) );
+		return ADC_ReadResultReg(pADC);
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @brief install ADC call back function.
+   *        
+   * @param[in]	 pADC_CallBack point to address of  adc call back function.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void ADC_SetCallBack(ADC_CallbackType pADC_CallBack)
+{
+    ADC_Callback[0] = pADC_CallBack;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set ADC channel.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Channel adc channel to conversion. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SetChannel( ADC_Type *pADC, uint8_t u8Channel )
+{
+    uint32_t u32temp;    
+    u32temp = pADC->SC1; 
+    u32temp &= ~ADC_SC1_ADCH_MASK;
+    pADC->SC1 = u32temp|ADC_SC1_ADCH(u8Channel);   
+}
+/*****************************************************************************//*!
+   *
+   * @brief Voltage Reference Selection.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Vref adc reference voltage selection. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_VrefSelect( ADC_Type *pADC, uint8_t u8Vref )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC2;
+    u32Temp &= ~ADC_SC2_REFSEL_MASK;
+    pADC->SC2 = u32Temp|ADC_SC2_REFSEL(u8Vref);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief select clock divide
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Div Clock Divide Select. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SelectClockDivide( ADC_Type *pADC, uint8_t u8Div )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC3;
+    u32Temp &= ~ADC_SC3_ADIV_MASK;
+    pADC->SC3 = u32Temp|ADC_SC3_ADIV(u8Div);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set ADC mode.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Mode Conversion Mode Selection. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SetMode( ADC_Type *pADC, uint8_t u8Mode )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC3;
+    u32Temp &= ~ADC_SC3_MODE_MASK;
+    pADC->SC3 = u32Temp|ADC_SC3_MODE(u8Mode);
+}
+/*****************************************************************************//*!
+   *
+   * @brief Input Clock Select.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Clock Input Clock Select. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SelectClock( ADC_Type *pADC, uint8_t u8Clock )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC3;
+    u32Temp &= ~ADC_SC3_ADICLK_MASK;
+    pADC->SC3 = u32Temp|ADC_SC3_ADICLK(u8Clock);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief FIFO Depth enables
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8FifoLevel set FIFO level. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SetFifoLevel( ADC_Type *pADC, uint8_t u8FifoLevel )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC4;
+    u32Temp &= ~ADC_SC4_AFDEP_MASK;
+    pADC->SC4 = u32Temp|ADC_SC4_AFDEP(u8FifoLevel);
+}
+
+/*! @} End of adc_api_list                                               						*/
+
+
+/*****************************************************************************//*!
+   *
+   * @brief ADC interrupt service routine.
+   *        
+   * @param  none. 
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void ADC_Isr(void)
+{ 
+//	printf("input any character to start a new conversion!\n");
+    if( ADC_Callback[0] )
+    {
+        ADC_Callback[0]();
+    }
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/bsp/nv32f100x/lib/src/arm_cm0.c b/bsp/nv32f100x/lib/src/arm_cm0.c
new file mode 100644
index 0000000000..bc42a7c6cb
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/arm_cm0.c
@@ -0,0 +1,77 @@
+/******************************************************************************
+* @brief provide generic high-level routines for ARM Cortex M0/M0+ processors. 
+*
+*******************************************************************************/
+
+#include "common.h"
+
+/***********************************************************************/
+/*
+ * Configures the ARM system control register for STOP (deep sleep) mode
+ * and then executes the WFI instruction to enter the mode.
+ *
+ * Parameters:
+ * none
+ *
+ * Note: Might want to change this later to allow for passing in a parameter
+ *       to optionally set the sleep on exit bit.
+ */
+
+void stop (void)
+{
+	/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;	
+
+	/* WFI instruction will start entry into STOP mode */
+#ifndef KEIL
+        // If not using KEIL's uVision use the standard assembly command
+	asm("WFI");
+#else
+        // If using KEIL's uVision, use the CMSIS intrinsic
+	__wfi();
+#endif
+}
+/***********************************************************************/
+/*
+ * Configures the ARM system control register for WAIT (sleep) mode
+ * and then executes the WFI instruction to enter the mode.
+ *
+ * Parameters:
+ * none
+ *
+ * Note: Might want to change this later to allow for passing in a parameter
+ *       to optionally set the sleep on exit bit.
+ */
+
+void wait (void)
+{
+	/* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep) mode instead
+	 * of deep sleep.
+	 */
+	SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;	
+
+	/* WFI instruction will start entry into WAIT mode */
+#ifndef KEIL
+        // If not using KEIL's uVision use the standard assembly command
+	asm("WFI");
+#else
+        // If using KEIL's uVision, use the CMSIS intrinsic
+    __wfi();
+#endif
+}
+/***********************************************************************/
+/*
+ * Change the value of the vector table offset register to the specified value.
+ *
+ * Parameters:
+ * vtor     new value to write to the VTOR
+ */
+
+void write_vtor (int vtor)
+{
+        /* Write the VTOR with the new value */
+        SCB->VTOR = vtor;	
+}
+
+/***********************************************************************/
+
diff --git a/bsp/nv32f100x/lib/src/crc.c b/bsp/nv32f100x/lib/src/crc.c
new file mode 100644
index 0000000000..7b5766b5b2
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/crc.c
@@ -0,0 +1,256 @@
+/******************************************************************************
+* @brief    Cyclic redundancy check (CRC) source code. 
+*
+******************************************************************************/
+#include "common.h"
+#include "crc.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define CRC APIs
+*
+*//*! @addtogroup crc_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize CRC with poly per control parameters
+*        
+* @param[in]  pConfig point to configuration. 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void CRC_Init(CRC_ConfigType *pConfig)
+{       
+    uint32_t     u32Sc ;
+    
+    u32Sc      = 0;
+    
+    SIM->SCGC |= SIM_SCGC_CRC_MASK;  
+    
+    u32Sc     |= ((pConfig->bWidth & 0x01)<<24);    
+    u32Sc     |= CRC_CTRL_TOTR(pConfig->bTransposeReadType & 0x03); 
+    u32Sc     |= CRC_CTRL_TOT(pConfig->bTransposeWriteType & 0x03);
+    
+    if (pConfig->bFinalXOR)
+    {
+        u32Sc |= CRC_CTRL_FXOR_MASK;        
+    }
+    
+    CRC0->CTRL  = u32Sc;
+
+    if ( pConfig->bWidth )      
+    {
+        CRC0->GPOLY = pConfig->u32PolyData;
+    }
+    else 
+    {
+        CRC0->GPOLY_ACCESS16BIT.GPOLYL = pConfig->u32PolyData;  /*!< only 16-bit write allowed */             
+    }  
+    
+}     
+
+
+/*****************************************************************************//*!
+*
+* @brief crc module 16-bit mode calculation.
+*        
+* @param[in]  seed  
+* @param[in]  msg  poiont to message buffer
+* @param[in]  sizeBytes  size of message
+*
+* @return data_out convertion result
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint32_t CRC_Cal16(uint32_t seed, uint8_t *msg, uint32_t sizeBytes)
+{
+  uint32_t ctrl_reg,data_out,data_in;
+  uint8_t  *pCRCBytes;
+  uint32_t sizeWords;
+  uint32_t i,j;  
+  
+  /* Input seed, Set WaS=1 */
+  ctrl_reg  = CRC0->CTRL;
+  CRC0->CTRL  = ctrl_reg | CRC_CTRL_WAS_MASK;
+  CRC0->ACCESS16BIT.DATAL = seed;
+  
+  /*Input data, Set WaS=0*/
+  CRC0->CTRL  = ctrl_reg & 0xFD000000;
+
+  /*Wait for calculation completion*/
+  sizeWords = sizeBytes>>1;
+  j = 0;
+  for(i=0;i<sizeWords;i++){ 
+      data_in = (msg[j] << 8) | (msg[j+1]);
+      j += 2;
+      CRC0->ACCESS16BIT.DATAL =data_in; 
+  }
+  if (j<sizeBytes)
+  { 
+     pCRCBytes = (uint8_t*)&CRC0->ACCESS8BIT.DATALL;
+     *pCRCBytes++ = msg[j];
+  }
+    data_out=CRC0->ACCESS16BIT.DATAL;
+  
+  return(data_out);
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief crc module 32-bit mode calculation.
+*        
+* @param[in]  seed 
+* @param[in]  msg  poiont to message buffer
+* @param[in]  sizeBytes  size of message
+*
+* @return data_out convertion result 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint32_t CRC_Cal32(uint32_t seed, uint8_t *msg, uint32_t sizeBytes)
+{  
+  uint32_t ctrl_reg,data_out,data_in;
+  uint32_t sizeDwords;
+  uint8_t  *pCRCBytes;
+  uint32_t i,j;
+  
+  /*Input seed, Set WaS=1*/
+  ctrl_reg = CRC0->CTRL;
+  CRC0->CTRL = ctrl_reg | 0x02000000;
+  CRC0->DATA = seed;
+ 
+  /*Input data, Set WaS=0*/
+  CRC0->CTRL = ctrl_reg & 0xFD000000;
+  
+  /*Wait for calculation completion*/
+  sizeDwords = sizeBytes>>2;
+  j = 0;
+  for(i=0;i<sizeDwords;i++)
+  { 
+      data_in = ((msg[j] << 24) | (msg[j+1] << 16) | (msg[j+2] << 8) | msg[j+3]);
+      j += 4;
+      CRC0->DATA = data_in; 
+  }
+  if (j<sizeBytes)
+  {
+    pCRCBytes = (uint8_t*)&CRC0->ACCESS8BIT.DATALL;
+
+#if  defined(BYTE_ENABLES_1_2_4_8)    
+    
+    /*write single byte*/  
+    for(;j<sizeBytes;j++)
+    {     
+       *pCRCBytes++ = msg[j];
+    }
+#elif  defined(BYTE_ENABLES_3_6_C)
+    
+    /*write two bytes*/ 
+    data_in = 0;
+    i = 0;
+    for(;j<sizeBytes;j++)
+    {     
+      data_in = (data_in <<8) | msg[j];
+      i++;
+      if (i==2)
+      {
+        i = 0;
+        CRC0->ACCESS16BIT.DATAL = data_in;
+      }
+    }
+    if (i==1)
+    {
+       CRC0->ACCESS8BIT.DATALL = data_in;                /*!< write last byte */
+    }
+#elif  defined(BYTE_ENABLES_7_E)                         
+    /*!< write three bytes */
+    data_in = 0;
+    i = 0;
+    for(;j<sizeBytes;j++)
+    {     
+      data_in = (data_in <<8) | msg[j];
+      i++;
+      if (i==3)
+      {
+        i = 0;
+        /*write first  char*/
+        CRC0->ACCESS8BIT.DATAHL  = (data_in>>16) & 0xff; /*!< write low byte of high word */
+        /*write last two chars*/
+        CRC0->ACCESS16BIT.DATAL = data_in & 0x00ffff;    /*!< write low word */
+       }
+    }
+    if ( i == 2)
+    {
+       CRC0->ACCESS16BIT.DATAL = (data_in);              /*!< write last 2 bytes */
+    }
+    else if (i == 1)
+    {
+       CRC0->ACCESS8BIT.DATALL = data_in;                /*!< write last byte */      
+    }
+#else                                                    /*!< write low byte only */
+    for(;j<sizeBytes;j++)
+    {     
+       *pCRCBytes = msg[j];
+    }
+#endif            
+  }
+  data_out=CRC0->DATA;
+
+  return(data_out);
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief de-initialize crc module, reset crc register.
+*        
+* @param none 
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void CRC_DeInit(void)
+{  
+   CRC0->CTRL  = 0x3000000; /*!< prepare for write 32-bit seed*/ 
+   CRC0->DATA  = 0xFFFFFFFF;/*!< write 32-bit seed to data register*/ 
+   while(!(CRC0->DATA == 0xFFFFFFFF));
+   CRC0->GPOLY = 0x00001021; 
+   CRC0->CTRL  = 0;         /*!< reset ctrl register*/  
+   SIM->SCGC &= ~SIM_SCGC_CRC_MASK;
+}
+
+/*! @} End of crc_api_list                                                   */
+
+
diff --git a/bsp/nv32f100x/lib/src/eeprom.c b/bsp/nv32f100x/lib/src/eeprom.c
new file mode 100644
index 0000000000..22c0b9196e
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/eeprom.c
@@ -0,0 +1,345 @@
+#include "flash.h"
+#include "eeprom.h"
+#include <string.h>
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+
+/******************************************************************************
+*
+* EEPROM 擦除命令，擦掉eeprom
+*输入参数：地址，函数将会擦除adr所在的512bytes eeprom
+*
+******************************************************************************/
+uint16_t Adress_Js(uint32_t adr)
+{
+    uint16_t err = EEPROM_ERR_SUCCESS;
+
+  
+    if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	return (err);
+	}
+  
+    if(adr >1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+      return(err);
+    }
+    return(err);
+}
+
+/******************************************************************************
+*
+* EEPROM 擦除命令，擦掉eeprom
+*输入参数：地址，函数将会擦除adr所在的512bytes eeprom
+*
+******************************************************************************/
+
+
+uint16_t EEPROM_Erase(uint32_t adr)
+{
+    uint16_t err = EEPROM_ERR_SUCCESS;
+    uint32_t e_adr;
+
+     if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	return (err);
+	}
+  
+    if(adr >1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+    
+      return(err);
+    }
+    
+    e_adr=adr+EEPROM_START_ADR;
+    err = Flash_EraseSector(e_adr);  
+    return(err);
+}
+
+/******************************************************************************
+*
+* EEPROM 读取函数，读取地址所在的eeprom
+*输入参数：地址
+*
+******************************************************************************/
+uint32_t EEPROM_Read(uint32_t adr)
+{
+    uint16_t err = EEPROM_ERR_SUCCESS;
+    uint32_t e_adr;
+    uint32_t data;
+    
+    if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	return (err);
+	}
+  
+    if(adr >1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+      return(err);
+    }
+    
+    e_adr=adr+EEPROM_START_ADR;
+    data = M32(e_adr);
+    return(data);
+    
+}
+/******************************************************************************
+*
+* EEPROM 写函数，写地址所在的eeprom
+*写之前读取出来，判断eeprom是否为空，如果为空，则直接写
+*如果非空，则先把整个512bytes sector读取到sram，修改要写的位置
+*然后再写入到flash，模拟一个eeprom的写过程
+*输入参数：地址
+*
+******************************************************************************/
+uint16_t EEPROM_Write(uint32_t adr, uint32_t Data)
+{
+  
+    uint32_t err = EEPROM_ERR_SUCCESS;
+    uint32_t e_adr;
+    uint32_t r_data;
+    uint16_t i;
+    uint32_t start_adr;
+ //   uint32_t modify_adr;
+    uint32_t EEPROM_DATA[128];
+
+    if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	return (err);
+	}
+  
+    if(adr >1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+      return(err);
+    }
+
+    
+    r_data = EEPROM_Read(adr);
+    
+    e_adr=adr+EEPROM_START_ADR;
+
+    if(r_data== EEPROM_BLANK) //如果要写的位置是空的，则直接写
+    {
+      err= Flash_Program1LongWord(e_adr,Data);
+    }
+   else if((r_data&Data) == Data)//如果要写的位置对应的bit，和要写的数据一致，或者是1，也是可以直接写
+     {
+      err= Flash_Program1LongWord(e_adr,Data);
+    }
+    else if(r_data == Data) //如果要写的数据和现有的数据一致，就不进行任何操作，直接返回
+    {
+      return(err);
+    }
+    else
+    {
+        start_adr = e_adr & EEPROM_SECTOR_MASK; //计算出sector的头地址    
+        
+        for( i=0;i<128;i++ ) //如果要写的位置不为空，则先把flash内容读取出来，放在sram中，修改
+        {
+          EEPROM_DATA[i] = M32(start_adr + 4*i);
+        }
+            
+        EEPROM_DATA[(adr&EEPROM_ARRAY_ADR_MASK)>>2] = Data; //修改SRAM 中的数据
+        
+        err=EEPROM_Erase(adr);
+     
+        err=Flash_Program(start_adr,(uint8_t*)EEPROM_DATA,512);//然后写入flash
+    }
+    return(err);
+    
+}
+
+/******************************************************************************
+*
+*Byte 写函数
+*
+******************************************************************************/
+uint16_t EEPROM_WriteByte(uint32_t adr, uint8_t Data)
+{
+    uint32_t err = EEPROM_ERR_SUCCESS;
+    uint32_t data_mask;
+    uint32_t r_data;
+    uint32_t data_m0;
+    uint32_t data_m1;
+    uint32_t word_adr = adr &0x3fc;
+    uint32_t  b_sit= adr & 0x3;
+    
+
+ //先让高位为FF
+    data_m0 = Data << b_sit*8;   
+    data_mask = 0xFFFFFFFF<<(b_sit+1)*8;    
+//   printf("datam0:=0x%x \n",data_m0);    
+//然后让低位为FF    
+     data_m1 = 0xFFFFFFFF >> (32-b_sit*8);
+     data_m1 = data_m1 | data_m0 | data_mask ;
+     
+//    printf("datam1:=0x%x \n",data_m1);  
+    
+    r_data = EEPROM_Read(word_adr);
+//    printf("r_data:=0x%x \n",r_data);        
+//或上原来的数据    
+    data_m1 = data_m1 & r_data;
+		
+    
+//    printf("data_m1:=0x%x \n",data_m1);     ;           
+    err = EEPROM_Write(word_adr , data_m1);
+    
+    return(err);
+
+}
+
+/******************************************************************************
+*
+*Byte 读函数
+*
+******************************************************************************/
+uint8_t EEPROM_ReadByte(uint32_t adr)
+{
+   uint32_t r_data;
+   uint32_t word_adr = adr &0x3fc;
+   uint32_t b_sit= adr & 0x3;
+   uint8_t  data;
+   
+    r_data = EEPROM_Read(word_adr);
+    data = (r_data>>b_sit*8)& 0xff;
+    return(data);
+   
+   
+}
+
+
+/******************************************************************************
+*
+*写函数，写一个长度为bytesize，到eeprom
+*先把1k的eeprom读取放入sram，然后修改要写的位置，
+*这个函数是还可以再优化的
+*这样更改后，没有考虑2K eeprom 。超过2K 也是完全可以的。
+******************************************************************************/
+uint16_t EERPOM_Writeup4byte(uint32_t adr,uint8_t *pData,uint32_t length)
+{
+	uint8_t buf[512];
+	uint8_t *pbuf;
+	uint32_t e_adr;
+	uint32_t e_sec;
+	uint32_t e_offset;
+	uint32_t a;
+	uint32_t err = EEPROM_ERR_SUCCESS;
+	
+   #ifdef IAR
+    if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	      return (err);
+	   }
+    #endif
+  
+    if((adr + length )>1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+      return(err);
+    }
+    
+	e_adr=adr+EEPROM_START_ADR;
+	e_sec=e_adr & EEPROM_SECTOR_MASK;
+	e_offset=e_adr & 0x1ff;
+
+	
+	while (length>0){
+          //如果起始地址不等于0，或者长度小于512 都进入这个循环
+		if (e_offset||(length<512)){
+			pbuf=buf;
+			a=512-e_offset;
+			a=(length>a?a:length);
+			
+			memcpy(buf,(uint8_t*)e_sec,512);
+			memcpy(&buf[e_offset],pData,a);
+			pData+=a;
+			length-=a;
+			e_offset=0;
+
+		}else{ //如果起始地址等于0且长度大于512 则简单了
+			pbuf=pData;
+			pData+=512;
+			length-=512;
+		}
+		err=Flash_EraseSector(e_sec);
+		err=Flash_Program(e_sec,(uint8_t*)pbuf,512);//然后写入flash
+		e_sec+=0x200;
+	}
+	return err;
+}
+
+
+/*
+uint16_t EERPOM_Writeup4byte(uint32_t adr,uint8_t *pData,uint32_t bytesize)
+{
+    uint32_t err = EEPROM_ERR_SUCCESS;
+    uint32_t e_adr;
+    uint16_t i;
+    uint32_t start_adr;
+    uint32_t EEPROM_DATA[256];
+    uint32_t longword = bytesize >>2;
+    uint32_t *pwData = (uint32_t*)pData ;
+    
+    err=Adress_Js(adr);
+    
+    if(adr+bytesize >1024) //如果写入的地址,加上要写的数据的个数大于1024，则报错
+    {
+      err = EEPROM_ADR_OverFlow;
+      return(err);
+    }
+    
+    e_adr=adr+EEPROM_START_ADR;
+    
+    start_adr = e_adr & EEPROM_SECTOR_MASK; //计算出sector 头地址
+
+    for( i=0;i<256;i++ ) //先把数据读取到sram
+      {
+        EEPROM_DATA[i] = M32(start_adr + 4*i);
+        }
+    for( i=0 ;i<longword ;i++) //然后修改要写的地址
+      {
+        EEPROM_DATA[(adr>>2)+i] = *pwData++;
+      }
+     //先erase掉2个eeprom secoter     
+     err=EEPROM_Erase(0x000);
+     err=EEPROM_Erase(0x200);   
+      
+    err=Flash_Program(start_adr,(uint8_t*)EEPROM_DATA,1024);//然后写入flash
+    
+    return(err);
+}
+*/
+
diff --git a/bsp/nv32f100x/lib/src/etm.c b/bsp/nv32f100x/lib/src/etm.c
new file mode 100644
index 0000000000..6fe474e619
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/etm.c
@@ -0,0 +1,1207 @@
+锘�
+/******************************************************************************
+* @brief providing APIs for configuring ETM. 
+*
+*******************************************************************************
+*
+* provide APIs for configuring ETM
+******************************************************************************/
+#include "common.h"
+#include "ETM.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+ETM_CallbackPtr ETM_Callback[3] = {(ETM_CallbackPtr)NULL};
+
+
+/******************************************************************************
+* ETM api lists
+*
+*//*! @addtogroup ETM_api_list
+* @{
+*******************************************************************************/
+/*******************************************************************************//*!
+*
+* @brief set the ETM moule clock source and prescale.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    ClockSource           ETM clock source.
+* @param[in]    ClockPrescale         prescale factor.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*******************************************************************************//*!
+*
+* @璁剧疆鏃堕挓璧勬簮鍙婂垎棰戠郴鏁�    
+* @杈撳叆     pETM                 鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆     ClockSource          ETM 鏃堕挓璧勬簮
+* @杈撳叆     ClockPrescale        鍒嗛绯绘暟 
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_ClockSet(ETM_Type *pETM, uint8_t u8ClockSource, uint8_t u8ClockPrescale)
+{
+    uint8_t   u8Temp;
+	//pETM鎸囧悜鐨凷C瀵勫瓨鍣ㄤ綆5浣嶆竻0锛屽嵆鏈�夋嫨鏃堕挓锛屾椂閽熻緭鍏ラ噰鍙�1鍒嗛
+    u8Temp  = (pETM->SC & 0xE0);
+	//鏃堕挓閫夋嫨锛屽強棰勫垎棰戝洜瀛愰�夋嫨
+    u8Temp |= (ETM_SC_CLKS(u8ClockSource & 0x3) | ETM_SC_PS(u8ClockPrescale & 0x7));
+	//閰嶇疆璇TM鐨勭姸鎬佷笌鎺у埗瀵勫瓨鍣‥TMx_SC
+    pETM->SC = u8Temp;
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to high ture EPWM mode, clock soure is the 
+*        system clock, MOD, CnV are the initial value.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    PWMModeSelect         select CPWM , EPWM  or combine pwm mode.
+* @param[in]    PWMEdgeSelect         select high true or low true pulse.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/******************************************************************************************
+*
+* @ETM涓璓WM鐨勫垵濮嬪寲鍑芥暟      
+* @杈撳叆        pETM                 鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆        PWMModeSelect        灞呬腑瀵归綈CPWM锛�10锛夈�佽竟娌垮榻怑PWM锛�01锛変互鍙婄骇鑱旀ā寮廝WM锛�11锛�
+* @杈撳叆        PWMEdgeSelect        楂樼湡鑴夊啿锛�01锛夈�佷綆鐪熻剦鍐诧紙10锛�
+*
+* @鏃犺繑鍥�
+*
+******************************************************************************************/
+void ETM_PWMInit(ETM_Type *pETM, uint8_t u8PWMModeSelect, uint8_t u8PWMEdgeSelect)
+{
+    uint8_t   channels, i;
+    
+    ASSERT((ETM0== pETM) || (ETM1== pETM) || (ETM2== pETM));//鏂█妫�娴嬮�氶亾鍚堟硶鎬�
+    
+    /* open the clock gate */  
+	//浣胯兘ETM鐨勬椂閽�
+	if (ETM0 == pETM)
+    {
+        channels = 2;
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+    }
+    else if(ETM1 == pETM)
+    {
+        channels = 2;
+#if !defined(CPU_NV32M3)
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+#endif
+    }        
+    else
+    {
+        channels = 6;
+        SIM->SCGC  |= SIM_SCGC_ETM2_MASK;
+    }
+    
+    pETM->SC  = 0x0;     //鍏抽棴璁℃暟鍣�          /* disable counter */  
+	pETM->MOD = ETM_MOD_INIT; 
+    
+    if(ETM_PWMMODE_CENTERALLIGNED == u8PWMModeSelect) //浣胯兘CPWM   /* enable CPWM */
+    {
+        pETM->SC |= ETM_SC_CPWMS_MASK; 
+    }
+    else if(ETM_PWMMODE_COMBINE == u8PWMModeSelect) // 鎵撳紑绾ц仈PWM妯″紡    /* enable combine pwm mode */
+    {
+        ASSERT(ETM2 == pETM);
+        pETM->MODE    |= ETM_MODE_WPDIS_MASK | ETM_MODE_ETMEN_MASK;
+        pETM->COMBINE = ETM_COMBINE_COMBINE0_MASK | ETM_COMBINE_COMP0_MASK | ETM_COMBINE_SYNCEN0_MASK | ETM_COMBINE_DTEN0_MASK |
+                        ETM_COMBINE_COMBINE1_MASK | ETM_COMBINE_COMP1_MASK | ETM_COMBINE_SYNCEN1_MASK | ETM_COMBINE_DTEN1_MASK |
+                        ETM_COMBINE_COMBINE2_MASK | ETM_COMBINE_COMP2_MASK | ETM_COMBINE_SYNCEN2_MASK | ETM_COMBINE_DTEN2_MASK 
+                        ;     
+        pETM->SC &= ~ETM_SC_CPWMS_MASK; 
+    }
+    if(ETM_PWM_HIGHTRUEPULSE == u8PWMEdgeSelect)
+    {
+        /* Configure ETMers PWM High True Pulses */
+		/* 閰嶇疆閫氶亾瀵勫瓨鍣紝璁剧疆閫氶亾鐘舵�佸強閫氶亾璁℃暟鍊� */
+        for(i=0; i<channels; i++)
+        {
+            pETM->CONTROLS[i].CnSC = ETM_CnSC_MSB_MASK | ETM_CnSC_ELSB_MASK;  
+            pETM->CONTROLS[i].CnV  = ETM_C0V_INIT + i*100; 
+        }
+    }
+    else if(ETM_PWM_LOWTRUEPULSE == u8PWMEdgeSelect)
+    {
+        /* Configure ETMers for PWM Low True Pulses */
+        for(i=0; i<channels; i++) 
+        {
+            pETM->CONTROLS[i].CnSC = ETM_CnSC_MSB_MASK | ETM_CnSC_ELSA_MASK; 
+            pETM->CONTROLS[i].CnV  = ETM_C0V_INIT + i*100 ; 
+        }
+    }  
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to input capture mode, enable interrupt.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               channel number to be configured.
+* @param[in]    CaptureMode           select capture edge: rising, falling or both.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************
+*
+* @杈撳叆鎹曟崏鍒濆鍖栧嚱鏁�
+*        
+* @杈撳叆        pETM                  鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆        Channel               閰嶇疆閫氶亾鍙�
+* @杈撳叆        CaptureMode           閫夋嫨鎹曟崏鏂瑰紡:涓婂崌娌�, 涓嬮檷娌挎垨璺冲彉娌�.
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_InputCaptureInit(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8CaptureMode)
+{ 
+    ASSERT(((ETM0 == pETM) && (u8ETM_Channel < 2))   || 
+           ((ETM1 == pETM) && (u8ETM_Channel < 2))   || 
+           ((ETM2 == pETM) && (u8ETM_Channel < 6))
+           );
+
+    
+    /* open the clock gate */
+	 /* 浣胯兘ETM鐨勬椂閽� */
+	if ((ETM0 == pETM) && (u8ETM_Channel < 2))
+    {
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+        NVIC_EnableIRQ(ETM0_IRQn);
+    }
+    else if((ETM1 == pETM)  && (u8ETM_Channel < 2))
+    {
+#if !defined(CPU_NV32M3)
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+        NVIC_EnableIRQ(ETM1_IRQn);
+#endif
+    }        
+    else 
+    {
+        SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+        NVIC_EnableIRQ(ETM2_IRQn);
+    }
+    
+    pETM->SC  = 0x0;    //鍏抽棴璁℃暟鍣�     /* diable counter */ 
+    pETM->MOD = 0xFFFF;  /* free running */
+    
+    if(ETM_INPUTCAPTURE_RISINGEDGE == u8CaptureMode) //浣胯兘涓柇锛屽湪涓婂崌娌挎崟鎹�       /* enable interrupt, Capture on rising edge */
+    {
+        pETM->CONTROLS[u8ETM_Channel].CnSC = ETM_CnSC_CHIE_MASK | ETM_CnSC_ELSA_MASK;
+    }
+    else if(ETM_INPUTCAPTURE_FALLINGEDGE == u8CaptureMode) //鍦ㄤ笅闄嶆部鎹曟崏      /* Capture on falling edge */
+    {
+        pETM->CONTROLS[u8ETM_Channel].CnSC = ETM_CnSC_CHIE_MASK | ETM_CnSC_ELSB_MASK;
+    }
+    else if(ETM_INPUTCAPTURE_BOTHEDGE == u8CaptureMode) //鍦ㄤ笂鍗囨部鎴栦笅闄嶆部鎹曟崏     /* Capture on rising or falling edge */
+    {
+        pETM->CONTROLS[u8ETM_Channel].CnSC = ETM_CnSC_CHIE_MASK | ETM_CnSC_ELSA_MASK | ETM_CnSC_ELSB_MASK;       
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to Dual Edge Capture mode to measure the
+*        width or the period  of a pulse.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    ChannelPair           ChannelPair number to be configured: 0, 2, 4.
+* @param[in]    CaptureMode           select capture edge: one shot and continuous mode.
+* @param[in]    Channel_N_Edge        channel N detect edge. 
+* @param[in]    Channel_Np1_Edge      channel N+1 detect edge.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @瀵笶TM閰嶇疆鍙岃竟鎹曡幏妯″紡鏉ユ祴閲忎竴涓剦鍐茬殑瀹藉害鎴栧懆鏈�
+*        
+* @杈撳叆        pETM                  鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆        ChannelPair           棰戦亾閰嶅鏁扮殑閰嶇疆涓�: 0, 2, 4.
+* @杈撳叆        CaptureMode           閫夋嫨鍗曞懆鏈熸崟鎹夛紝鍜岃繛缁崟鎹夋柟寮�
+* @杈撳叆        Channel_N_Edge        棰戦亾N杈规部妫�娴� 
+* @杈撳叆        Channel_Np1_Edge      棰戦亾N+1杈规部妫�娴�.
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_DualEdgeCaptureInit(ETM_Type *pETM, uint8_t u8ChannelPair, uint8_t u8CaptureMode, 
+                                 uint8_t u8Channel_N_Edge, uint8_t u8Channel_Np1_Edge)
+{ 
+    ASSERT((ETM2 == pETM)  && (u8ChannelPair < 6) && !(u8ChannelPair & 1) );
+    
+    SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+    if((0 == u8ChannelPair) || (2== u8ChannelPair))
+    {
+                                  //閫氶亾婊ゆ尝      /* channel filter is active */
+    }
+       
+    pETM->SC    = 0x0;         //鍏抽棴璁℃暟鍣�         /* diable counter */ 
+    pETM->MOD   = 0xFFFF;
+    pETM->MODE |= ETM_MODE_ETMEN_MASK;  /* ETMEN = 1 */  
+    /* DECAPEN = 1,  ChannelPair/2 * 8 */
+    pETM->COMBINE |=  ((ETM_COMBINE_DECAPEN0_MASK) << (u8ChannelPair * 4)); 
+    
+    pETM->CONTROLS[u8ChannelPair].CnSC &= ~ETM_CnSC_CHF_MASK;  //娓呴櫎鐩稿叧浣�     /* CH(n)F and CH(n+1)F bits must be cleared first */
+    pETM->CONTROLS[u8ChannelPair + 1].CnSC &= ~ETM_CnSC_CHF_MASK;
+    
+    if(ETM_INPUTCAPTURE_DUALEDGE_ONESHOT == u8CaptureMode)   //鍗曞懆鏈熸ā寮�     /* oneshot mode */
+    {
+        pETM->CONTROLS[u8ChannelPair].CnSC &= ~ETM_CnSC_MSA_MASK;
+        pETM->CONTROLS[u8ChannelPair+1].CnSC &= ~ETM_CnSC_MSA_MASK;
+    }
+    else if(ETM_INPUTCAPTURE_DUALEDGE_CONTINUOUS == u8CaptureMode) //杩炵画妯″紡   /* continuouse mode */
+    {
+        pETM->CONTROLS[u8ChannelPair].CnSC |= ETM_CnSC_MSA_MASK;
+        pETM->CONTROLS[u8ChannelPair+1].CnSC |= ETM_CnSC_MSA_MASK;
+    }
+    
+    pETM->CONTROLS[u8ChannelPair].CnSC |= (u8Channel_N_Edge << 2); //閫夋嫨妫�娴嬭竟娌�  /* select detec edge */
+    pETM->CONTROLS[u8ChannelPair + 1].CnSC |= (u8Channel_Np1_Edge << 2);   
+    
+    pETM->COMBINE |=  (ETM_COMBINE_DECAP0_MASK << (u8ChannelPair * 4)); 
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to input capture mode.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               channel number to be configured.
+* @param[in]    CompareMode           select compare edge: toggle, set and clear.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @杈撳嚭瀵规瘮鍒濆鍖�
+* 
+* @杈撳叆     pETM                   鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆     Channel                蹇呴』瀹屾垚閰嶇疆閫氶亾鍗抽�氶亾鍙�
+* @杈撳叆     CompareMode            閫夋嫨妯″紡锛氱炕杞紙01锛夈�佺疆浣嶏紙11锛夈�佹竻0锛�10锛�
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_OutputCompareInit(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8CompareMode)
+{
+    ASSERT(((ETM0 == pETM) && (u8ETM_Channel < 2))   || 
+           ((ETM1 == pETM) && (u8ETM_Channel < 2))   || 
+           ((ETM2 == pETM) && (u8ETM_Channel < 6))
+           );
+    
+    /* open the clock gate */
+	 /* 浣胯兘ETM鐨勬椂閽� */
+	if(ETM0 == pETM)
+    {
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+    }
+    else if(ETM1 == pETM)
+    {
+#if !defined(CPU_NV32M3)
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+#endif
+    }        
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+    }
+    
+    pETM->SC  = 0x0;                                                 //鍏抽棴璁℃暟鍣�                  /* diable counter */
+    pETM->MOD = ETM_MOD_INIT; 
+    pETM->CONTROLS[u8ETM_Channel].CnSC = (ETM_CnSC_MSA_MASK | (u8CompareMode << 2)); //閫夋嫨妫�娴嬭竟娌�   /* select detec edge */
+    pETM->CONTROLS[u8ETM_Channel].CnV  = ETM_C0V_INIT;
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM2 to start software synchronization.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @杩愮敤ETM2鏉ュ疄鐜拌蒋浠跺悓姝�
+*        
+* @杈撳叆       pETM                   鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_SoftwareSync(ETM_Type *pETM)
+{
+    ASSERT(ETM2 == pETM);
+
+    pETM->SYNCONF   |= ETM_SYNCONF_SYNCMODE_MASK;   // 閫夋嫨澧炲己PWM鍚屾  /* recommend enhanced sync mode */
+    pETM->SYNC      |= ETM_SYNC_SWSYNC_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM to enable hardware synchronization.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    u8TriggerN            select the hardware trigger source.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/********************************************************************
+* @ETM涓厤缃瓻TMx_SYNC 瀵勫瓨鍣ㄦ潵淇濊瘉杞欢鍚屾        
+* 
+* @杈撳叆       pETM                    鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆       u8TriggerN              閫夋嫨纭欢瑙﹀彂璧勬簮
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_HardwareSync(ETM_Type *pETM, uint8_t u8TriggerN)
+{
+    ASSERT(ETM2 == pETM);
+    
+    pETM->SYNCONF   |= ETM_SYNCONF_SYNCMODE_MASK; //閫夋嫨澧炲己PWM鍚屾 /* recommend enhanced sync mode */
+    
+    switch(u8TriggerN)
+    {
+        case ETM_SYNC_TRIGGER_TRIGGER2: 
+                pETM->SYNC |= ETM_SYNC_TRIG2_MASK;
+                break;  
+        case ETM_SYNC_TRIGGER_TRIGGER1: 
+                pETM->SYNC |= ETM_SYNC_TRIG1_MASK;
+                break;   //棣栧厛閰嶇疆ETM0CH0  /* need configure ETM0CH0 first */
+        case ETM_SYNC_TRIGGER_TRIGGER0:
+                pETM->SYNC |= ETM_SYNC_TRIG0_MASK; 
+                break;   //棣栧厛閰嶇疆CMP0  /* need configure CMP0 first */
+        default: 
+                break;
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM to enable hardware synchronization, more then 1 trigger.
+*        
+* @param[in]    pETM               pointer to one of three ETM base register address.
+* @param[in]    u8TriggerMask      select the hardware trigger source. combine TRIG0~TREG2.(x000xxxx~x111xxxx)
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @閫氳繃閰嶇疆ETM淇濊瘉纭欢鍚屾锛屼骇鐢熻Е鍙�
+*        
+* @杈撳叆   pETM              鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆   u8TriggerMask     閫夋嫨纭欢瑙﹀彂璧勬簮. 
+*
+* @鏃犺繑鍥�.
+*
+*********************************************************************************/
+void ETM_HardwareSyncCombine(ETM_Type *pETM, uint8_t u8TriggerMask)
+{
+    ASSERT(ETM2 == pETM);
+    
+    pETM->SYNCONF   |= ETM_SYNCONF_SYNCMODE_MASK;  //閫夋嫨澧炲己PWM鍚屾 /* recommend enhanced sync mode */
+    pETM->SYNC      &= 0x8F;
+    pETM->SYNC      |= (u8TriggerMask & 0x70);
+}
+
+/*********************************************************************************//*!
+*
+* @brief generate ETM2 hardware trigger 2,Note: please call ETM_HardwareSyncCombine first.
+*        
+* @param[in]    pETM               pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @浜х敓ETM2纭欢瑙﹀彂
+*        
+* @杈撳叆        pETM              鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_GenerateTrig2(ETM_Type *pETM)
+{
+    ASSERT(ETM2 == pETM);
+    
+    if(pETM->SYNC & ETM_SYNC_TRIG2_MASK)
+    {
+#if defined(CPU_NV32)
+        SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;
+#elif defined(CPU_NV32M3)
+        SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;
+#elif defined(CPU_NV32M4)
+        SIM->SOPT0  |= SIM_SOPT0_ETMSYNC_MASK;
+#endif
+    }
+}
+
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to start software synchronization.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    PrescalerValue        system clock divide value, 0 to 3.
+* @param[in]    DeadETMeValue         n count clock is inserted, 0 to 63.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM姝诲尯鏃堕棿鎻掑叆璁剧疆.
+*        
+* @杈撳叆         pETM                  鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆         PrescalerValue        绯荤粺鏃堕挓鍒嗛鍊�
+* @杈撳叆         DeadETMeValue         姝诲幓鎻掑叆鏃堕棿鍊硷紝0-63鍙��
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_PWMDeadETMeSet(ETM_Type *pETM, uint8_t u8PrescalerValue, uint8_t u8DeadETMeValue)
+{
+    ASSERT(ETM2 == pETM);
+    
+    pETM->COMBINE |= 0x101010;     //浣胯兘姝诲尯鏃堕棿鎻掑叆    /* enable dead ETMe insertion */
+
+    if(!(pETM->MODE & ETM_MODE_WPDIS_MASK)) //濡傛灉寮�鍚簡鍐欎繚鎶�/* if write protection is enabled */
+    {
+        pETM->MODE |= ETM_MODE_WPDIS_MASK; //绂佺敤鍐欎繚鎶� /* disable the write protection */
+        pETM->DEADETME = (ETM_DEADETME_DTVAL(u8DeadETMeValue & 0x3F) | ETM_DEADETME_DTPS(u8PrescalerValue & 0x3));
+        pETM->MODE &= ~ETM_MODE_WPDIS_MASK;//浣胯兘鍐欎繚鎶� /* enable the write protection */       
+    }
+    else 
+    {
+        //濡傛灉娌℃湁寮�鍚啓淇濇姢     /* if no protection */
+        pETM->DEADETME = (ETM_DEADETME_DTVAL(u8DeadETMeValue & 0x3F) | ETM_DEADETME_DTPS(u8PrescalerValue & 0x3));
+    }
+    pETM->SYNC |= ETM_SYNC_SWSYNC_MASK;    //杞欢鍚屾 /* software sync */
+}    
+
+/*********************************************************************************//*!
+*
+* @brief set output mask.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               pwm channel needed to be masked.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @璁剧疆杈撳嚭鏍囧織浣�
+*        
+* @杈撳叆           pETM                  鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆           Channel               PWM閫氶亾浣嶉渶瑕佽缃爣蹇�
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_OutputMaskSet(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    ASSERT((ETM2 == pETM) && (u8ETM_Channel < 6));
+
+    pETM->OUTMASK |= (1 << u8ETM_Channel);
+    
+    if(pETM->SYNC & ETM_SYNC_SYNCHOM_MASK)           //濡傛灉闇�瑕丳WM鍚屾鏇存柊   /* if PWM sync is needed */
+    {
+        pETM->SYNCONF |= ETM_SYNCONF_SYNCMODE_MASK;   //閫夋嫨澧炲己PWM鍚屾  /* recommend enhanced sync mode */
+        if(pETM->SYNCONF & ETM_SYNCONF_SWOM_MASK)    //濡傛灉闇�瑕佽蒋浠跺悓姝�   /* if software sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_SWSYNC_MASK;
+        }
+        else if(pETM->SYNCONF & ETM_SYNCONF_HWOM_MASK)//濡傛灉闇�瑕佺‖浠跺悓姝� /* if hardware sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_TRIG2_MASK;
+            
+#if defined(CPU_NV32)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;      //纭欢鍚屾   /* hardware sync */ 
+#elif defined(CPU_NV32M3)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;         /* hardware sync */ 
+#elif defined(CPU_NV32M4)
+            SIM->SOPT0  |= SIM_SOPT0_ETMSYNC_MASK;         /* hardware sync */ 
+#endif
+        }
+        else
+        {
+        }
+    }
+    else  /* no need to sync, update on the next rising edge of system clock  */
+    {
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to start software synchronization.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               pwm channel needed to be controlled by software.
+* @param[in]    ChannelValue          the value to be set,  0 or 1.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @閰嶇疆杞欢杈撳嚭鎺у埗SWOCTRL瀵勫瓨鍣ㄧ殑鍚屾鏄惁鐢辫蒋浠惰Е鍙�
+*        
+* @杈撳叆        pETM                  鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆        Channel               PWM娉㈢殑閫氶亾閫夋嫨
+* @杈撳叆        ChannelValue          0鎴�1,0涓嶈Е鍙�;1瑙﹀彂
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_SWOutputControlSet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8ChannelValue)
+{
+    ASSERT((ETM2 == pETM) && (u8ETM_Channel < 6));
+    
+    if(ETM_SWOCTRL_HIGH == u8ChannelValue)
+    {
+        pETM->SWOCTRL |= (0x0101 << u8ETM_Channel);
+    }
+    else if(ETM_SWOCTRL_LOW == u8ChannelValue)
+    {
+        pETM->SWOCTRL |= (1 << u8ETM_Channel);
+        pETM->SWOCTRL &= ~(0x100 << u8ETM_Channel);
+    }
+    if(pETM->SYNCONF & ETM_SYNCONF_SWOC_MASK)               /* if PWM sync is needed */
+    {
+        pETM->SYNCONF |= ETM_SYNCONF_SYNCMODE_MASK;         /* recommend enhanced sync mode */
+        if(pETM->SYNCONF & ETM_SYNCONF_SWSOC_MASK)          /* if software sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_SWSYNC_MASK;             /* software sync */ 
+        }
+        else if(pETM->SYNCONF & ETM_SYNCONF_HWSOC_MASK)     /* if hardware sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_TRIG2_MASK;
+
+#if defined(CPU_NV32)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;             /* hardware sync */ 
+#elif defined(CPU_NV32M3)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;             /* hardware sync */ 
+#elif defined(CPU_NV32M4)
+            SIM->SOPT0  |= SIM_SOPT0_ETMSYNC_MASK;             /* hardware sync */ 
+#endif
+        }
+    }
+    else  /* no need to sync, update on the next rising edge of system clock  */
+    {
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief set PWM polarity.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               pwm channel needed to be controlled by software.
+* @param[in]    ActiveValue           the value to be set,  0 or 1.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************
+*
+* @璁剧疆閫氶亾杈撳嚭鏋佹�х殑鍔熻兘鍑芥暟
+*        
+* @杈撳叆     pETM                 鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆     Channel              PWM娉㈢殑閫氶亾閫夋嫨
+* @杈撳叆     ActiveValue          鏋佹�х殑閫夋嫨锛�0涓洪珮鐢靛钩锛�1涓轰綆鐢靛钩
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_PolaritySet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8ActiveValue)
+{
+    ASSERT((ETM2 == pETM) && (u8ETM_Channel < 6));
+    
+    if(ETM_POLARITY_HIGHACTIVE == u8ActiveValue)
+    {
+        pETM->POL &=  ~(1 << u8ETM_Channel);
+    }
+    else if(ETM_POLARITY_LOWACTIVE == u8ActiveValue)
+    {
+        pETM->POL |=  (1 << u8ETM_Channel);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief set ETM behavior in debug mode.
+*        
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u8DebugMode      debug mode select from 00 to 11.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************
+*
+* @閫夋嫨BDM妯″紡涓嬬殑ETM琛屼负
+*        
+* @杈撳叆   pETM             鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆   u8DebugMode      debug 鐨勬ā寮忎粠00-11涔嬮棿閫夋嫨
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_SetDebugModeBehavior(ETM_Type *pETM, uint8_t u8DebugMode)
+{
+    ASSERT((ETM2 == pETM));
+    pETM->CONF &= ~ETM_CONF_BDMMODE_MASK;
+    pETM->CONF |= ETM_CONF_BDMMODE(u8DebugMode);
+}
+
+/*********************************************************************************//*!
+*
+* @brief Selects the ratio between the number of counter overflows to the number of ETMes the TOF bit is set.
+*        
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u8TOFNUM         TOF numbers before setting TOF bit, 0~31.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM涓璗OF棰戠巼澶у皬鐨勮缃姛鑳藉嚱鏁�
+*        
+* @杈撳叆    pETM              鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆    u8TOFNUM          TOF棰戠巼鏁帮紝澶у皬0鍜�31涔嬮棿
+* 
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM_SetTOFFrequency(ETM_Type *pETM, uint8_t u8TOFNUM)
+{
+    ASSERT((ETM2 == pETM));
+    pETM->CONF &= ~ETM_CONF_NUMTOF_MASK;
+    pETM->CONF |= ETM_CONF_NUMTOF(u8TOFNUM);
+}
+
+/*********************************************************************************//*!
+*
+* @brief swap the output of CH(n) and CH(n+1).
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    ChannelPair           the pair to be swapped, 0,1,2.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************
+*
+* @浜ゆ崲閫氶亾CH锛坣锛夊拰閫氶亾CH锛坣+1锛夌殑杈撳嚭缁撴灉   
+*    
+* @杈撳叆  pETM                   鍏朵腑涓�涓狤TM瀹氭椂鍣ㄧ殑鍩哄潃
+* @杈撳叆  ChannelPair            瑕佽浜ゆ崲鐨勯�氶亾鏁板彿锛屽嵆n鍙负0,1,2,
+*
+*********************************************************************************/
+void ETM_InvertChannel(ETM_Type *pETM, uint8_t u8ChannelPair)
+{
+    ASSERT((ETM2 == pETM)  && u8ChannelPair <= 2);
+
+    pETM->INVCTRL |= 1<<u8ChannelPair;
+    if(pETM->SYNCONF & ETM_SYNCONF_INVC_MASK)     //濡傛灉闇�瑕丳WM鍚屾  /* if PWM sync is needed */
+    {
+        pETM->SYNCONF |= ETM_SYNCONF_SYNCMODE_MASK; //閫夋嫨澧炲己PWM鍚屾 /* recommend enhanced sync mode */
+        if(pETM->SYNCONF & ETM_SYNCONF_SWINVC_MASK)//濡傛灉闇�瑕佽蒋浠跺悓姝� /* if software sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_SWSYNC_MASK; //寮�鍚蒋浠跺悓姝�   /* software sync */ 
+        }
+        else if(pETM->SYNCONF & ETM_SYNCONF_HWINVC_MASK)   //濡傛灉闇�瑕佺‖浠跺悓姝� /* if hardware sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_TRIG2_MASK;
+
+#if defined(CPU_NV32)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;       //纭欢鍚屾      /* hardware sync */ 
+#elif defined(CPU_NV32M3)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;             /* hardware sync */ 
+#elif defined(CPU_NV32M4)
+            SIM->SOPT0  |= SIM_SOPT0_ETMSYNC_MASK;             /* hardware sync */ 
+#endif
+        }
+    }
+    else  
+    {
+    }
+}  
+
+/*****************************************************************************//*!
+*
+* @brief configure the ETM as specified control parameters, CnSC and CnV not 
+*        included.
+*        
+* @param[in]    pETM          pointer to one of three ETM base register address.
+* @param[in]    pConfig     pointer to ETM general parameters.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************//*!
+*
+* @ETM鍒濆鍖栧嚱鏁�
+*        
+* @杈撳叆        pETM           鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆        pConfig        鎸囧悜ETM鐨勪竴浜涘熀鏈弬鏁�
+* @鏃犺繑鍥炲��
+*
+*****************************************************************************/
+void ETM_Init(ETM_Type *pETM, ETM_ConfigType *pConfig)
+{
+    ASSERT((ETM0 == pETM) || (ETM1 == pETM) || (ETM2 == pETM));
+    if(ETM0 == pETM)
+    {
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+    }
+#if !defined(CPU_NV32M3)
+    else if(ETM1 == pETM)
+    {
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+    }
+#endif
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+    }
+        
+    /* diable counter */
+    pETM->SC = 0; 
+ 	pETM->MODE = pConfig->mode;       
+	pETM->MOD = pConfig->modulo;
+	pETM->CNT = pConfig->cnt;
+        
+    if( pETM->MODE & ETM_MODE_ETMEN_MASK  ) 
+    {
+        /* when ETMEN = 1, all other registers can be written */
+		 /* 褰� ETMEN = 1, 鎵�鏈夊瘎瀛樺櫒閮藉彲浠ヨ鍐欏叆 */
+        pETM->COMBINE   = pConfig->combine;      
+        pETM->CNTIN     = pConfig->cntin;      
+        pETM->SYNC      = pConfig->sync;      
+        pETM->OUTINIT   = pConfig->outinit;      
+        pETM->OUTMASK   = pConfig->outmask;      
+        pETM->DEADETME  = pConfig->deadETMe;      
+        pETM->EXTTRIG   = pConfig->exttrig;      
+        pETM->POL       = pConfig->pol;      
+        pETM->FMS       = pConfig->fms;      
+        pETM->FILTER    = pConfig->filter;      
+        pETM->FLTCTRL   = pConfig->fltctrl;    /* fault control */ 
+        pETM->FLTPOL    = pConfig->fltpol;      
+        pETM->CONF      = pConfig->conf;      
+        pETM->SYNCONF   = pConfig->synconf;      
+        pETM->SWOCTRL   = pConfig->swoctrl;      
+        pETM->PWMLOAD   = pConfig->pwmload;      
+    }
+    /* write SC to enable clock */
+    /*閫氳繃鍐欏叆鐘舵�佹帶鍒跺瘎瀛樺櫒SC鏉ヤ娇鑳紼TM鏃堕挓 */
+    pETM->SC = pConfig->sc;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  close the ETM moudle.
+*        
+* @param[in]    pETM          pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************
+*
+*鍏抽棴鐩稿簲鐨凟TM鍔熻兘缁勪欢鍑芥暟     
+*
+*****************************************************************************/
+void ETM_DeInit(ETM_Type *pETM)
+{
+    ASSERT((ETM0 == pETM) || (ETM1 == pETM) || (ETM2 == pETM));
+    pETM->SC = 0;       
+	pETM->MOD = 0;
+	pETM->CNT = 0;
+    if(ETM2 == pETM) 
+    {
+          pETM->MODE = 0x4; 
+          pETM->COMBINE = 0;      
+          pETM->CNTIN = 0;      
+          pETM->SYNC = 0;      
+          pETM->OUTINIT = 0;      
+          pETM->OUTMASK = 0;      
+          pETM->DEADETME = 0;      
+          pETM->EXTTRIG = 0;      
+          pETM->POL = 0;      
+          pETM->FMS = 0;      
+          pETM->FILTER = 0;      
+          pETM->FLTCTRL = 0;  
+          pETM->FLTPOL = 0;      
+          pETM->CONF = 0;      
+          pETM->SYNCONF = 0;      
+          pETM->SWOCTRL = 0;      
+          pETM->PWMLOAD = 0;      
+    }
+    /* close the clock gate */
+	/* 绂佺敤鏃堕挓 */
+	if (ETM0 == pETM)
+    {
+        SIM->SCGC &= ~SIM_SCGC_ETM0_MASK;
+        NVIC_DisableIRQ(ETM0_IRQn);
+    }
+#if !defined(CPU_NV32M3)    
+    else if(ETM1 == pETM)
+    {
+        SIM->SCGC &= ~SIM_SCGC_ETM1_MASK;
+        NVIC_DisableIRQ(ETM1_IRQn);
+    } 
+#endif
+    else if (ETM2 == pETM)
+    {
+        SIM->SCGC &= ~SIM_SCGC_ETM2_MASK;
+        NVIC_DisableIRQ(ETM2_IRQn);
+    }
+}
+    
+/*****************************************************************************//*!
+*
+* @brief configure the ETM  channels, CnSC and CnV are included.
+*        
+* @param[in]    pETM               pointer to one of three ETM base register address.
+* @param[in]    ETM_Channel        ETM channel number.
+* @param[in]    pTETMCH_Params     pointer to ETM channel general parameters.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************//*!
+*
+* @鏈嚱鏁扮敤鏉ラ厤缃瓻TM閫氶亾, 鍖呮嫭閫氶亾鐘舵�佸強鎺у埗瀵勫瓨鍣–nSC鍜岄�氶亾璁℃暟鍊煎瘎瀛樺櫒CnV      
+* @杈撳叆     pETM                 鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆     ETM_Channel          ETM鐨勯�氶亾鍙�
+* @杈撳叆     pTETMCH_Params      鎸囧悜ETM閫氶亾涓�鑸弬鏁扮殑鎸囬拡
+*
+* @鏃犺繑鍥炲��
+*
+*****************************************************************************/
+void ETM_ChannelInit(ETM_Type *pETM, uint8_t u8ETM_Channel, ETM_ChParamsType *pTETMCH_Params)
+{
+    ASSERT((ETM0 == pETM) || (ETM1 == pETM) || (ETM2 == pETM));  
+    
+	if (ETM0 == pETM)
+    {
+        ASSERT(u8ETM_Channel < 2);
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+    }
+ #if !defined(CPU_NV32M3)
+    else if(ETM1 == pETM)
+    {
+        ASSERT(u8ETM_Channel < 2);
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+    }        
+#endif
+    else
+    {
+        ASSERT(u8ETM_Channel < 6);
+        SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+    }
+    
+    pETM->CONTROLS[u8ETM_Channel].CnSC = pTETMCH_Params->u8CnSC;
+    pETM->CONTROLS[u8ETM_Channel].CnV = pTETMCH_Params->u16CnV; 
+    
+    return;
+}
+
+/*****************************************************************************//*!
+*
+* @brief set the ETM channel value register per duty cycle and modulo for combine mode
+*        odd channel no must be provided and even channel value register is not changed.
+*
+* @param[in]    pETM            pointer to one of three ETM base register address.
+* @param[in]    ETM_Channel     odd channel no:1,3,5.
+* @param[in]    dutyCycle       duty cycle in percentage. e.g. 10, means 10%.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************//*!
+*
+* 蹇呴』璁剧疆濂囨暟閫氶亾鏁帮紝涓斿伓鏁伴�氶亾鐨勫�间笉鍙�
+*
+* @杈撳叆        pETM            鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆        ETM_Channel     濂囬�氶亾鏁帮細1銆�3銆�5
+* @杈撳叆        dutyCycle       璁剧疆鍗犵┖姣旓紝鑻utyCycle涓�10,閭ｄ箞鍗犵┖姣斿氨涓�10%
+*
+* @return none.
+*
+*****************************************************************************/
+void  ETM_SetDutyCycleCombine(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8DutyCycle)
+{
+    uint16_t   cnv = pETM->CONTROLS[u8ETM_Channel-1].CnV;
+    uint16_t   modulo = pETM->MOD; 
+    
+    ASSERT((1 == u8ETM_Channel) || (3 == u8ETM_Channel) || (5 == u8ETM_Channel));
+    
+    cnv += (u8DutyCycle * (modulo+1))  / 100;
+    if(cnv > modulo)
+    {
+        cnv = modulo - 1;
+    }
+    pETM->CONTROLS[u8ETM_Channel].CnV = cnv ;    
+    
+    pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK | (1<<u8ETM_Channel);     
+}
+
+/*****************************************************************************//*!
+*
+* @brief configure the ETMx_SYNCONF register including SW and HW Sync selection.
+*
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u32ConfigValue   ETMx_SYNCONF register config value.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************
+*
+* @閰嶇疆瀵勫瓨鍣� ETMx_SYNCONF,鍏朵腑閲岄潰鍖呭惈浜嗚蒋浠惰緭鍑虹殑鎺у埗鏄惁鐢辩‖浠惰Е鍙慔W鎴栨槸鍚︽湁杞欢鍑哄彂SW
+*
+* @杈撳叆     pETM               鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆     u32ConfigValue     ETMx_SYNCONF杩欎釜瀵勫瓨鍣ㄧ殑鍊� 
+*
+* @鏃犺繑鍥�
+*
+*****************************************************************************/
+void  ETM_SyncConfigActivate(ETM_Type *pETM, uint32_t u32ConfigValue)
+{
+    ASSERT((ETM2 == pETM));
+    pETM->SYNCONF |= u32ConfigValue;   
+}
+
+/*****************************************************************************//*!
+
+*
+* @brief configure the ETMx_SYNCONF register including SW and HW Sync selection.
+*
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u32ConfigValue   ETMx_SYNCONF register config value.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************
+*
+* @鎭㈠閰嶇疆瀵勫瓨鍣� ETMx_SYNCONF,鍏朵腑閲岄潰鍖呭惈浜嗚蒋浠惰緭鍑虹殑鎺у埗鏄惁鐢辩‖浠惰Е鍙慔W鎴栨槸鍚︽湁杞欢鍑哄彂SW
+*
+* @杈撳叆     pETM               鎸囧悜涓変釜ETM瀹氭椂鍣ㄥ叾涓竴涓殑鍩哄潃
+* @杈撳叆     u32ConfigValue     ETMx_SYNCONF杩欎釜瀵勫瓨鍣ㄧ殑鍊� 
+*
+* @鏃犺繑鍥�
+*
+*****************************************************************************/
+void  ETM_SyncConfigDeactivate(ETM_Type *pETM, uint32_t u32ConfigValue)
+{
+    ASSERT((ETM2 == pETM));
+    pETM->SYNCONF &= ~u32ConfigValue;   
+}
+
+/*****************************************************************************//*!
+*
+* @brief This function sets the callback function.
+*
+* @param[in]    pETM          pointer to one of three ETM base register address.
+* @param[in]    pfnCallback     functon address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+*****************************************************************************/
+/*****************************************************************************//*!
+*
+* @璁剧疆涓柇鍥炶皟鍑芥暟鍏ュ彛
+*
+* @杈撳叆       pETM            鎸囧悜涓変釜ETM涓叾涓竴涓殑鍩哄潃
+* @杈撳叆       pfnCallback     鍔熻兘鍑芥暟鐨勫湴鍧�
+*
+* @鏃犺繑鍥�.
+*
+*****************************************************************************/
+void  ETM_SetCallback(ETM_Type *pETM, ETM_CallbackPtr pfnCallback)
+{
+   ETM_Callback[((uint32_t)pETM - (uint32_t)ETM0_BASE)>>12] = pfnCallback;
+}
+
+/*! @} End of ETM_api_list                                                    */
+
+
+/*****************************************************************************//*!
+*
+* @brief  ETM0_Isr interrupt service routine.
+*        
+* @param  none.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM0涓柇鏈嶅姟鍑芥暟
+* 
+* @鏃犺緭鍏�
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM0_Isr(void)
+{
+    if(ETM_Callback[0])
+    {
+        ETM_Callback[0]();
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ETM1_Isr interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM1涓柇鏈嶅姟鍑芥暟
+* 
+* @鏃犺緭鍏�
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM1_Isr(void)
+{
+    if(ETM_Callback[1])
+    {
+        ETM_Callback[1]();
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ETM2_Isr interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM2涓柇鏈嶅姟鍑芥暟
+* 
+* @鏃犺緭鍏�
+*
+* @鏃犺繑鍥�
+*
+*********************************************************************************/
+void ETM2_Isr(void)
+{
+    if(ETM_Callback[2])
+    {
+        ETM_Callback[2]();
+    }
+}
+
+
+
diff --git a/bsp/nv32f100x/lib/src/flash.c b/bsp/nv32f100x/lib/src/flash.c
new file mode 100644
index 0000000000..b1b10145b9
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/flash.c
@@ -0,0 +1,351 @@
+/******************************************************************************
+******************************************************************************
+*
+* @file flash.c
+*
+* @brief application entry point which performs application specific tasks. 
+*
+*******************************************************************************
+*
+* provide a demo for how to initialize the NV32, output messages via SCI, 
+* flash operations, etc.
+* NOTE:
+*	printf call may occupy a lot of memory (around 1924 bytes), so please
+*	consider your code size before using printf.
+******************************************************************************
+*
+* provide FLASH driver
+*
+******************************************************************************/
+
+#include "flash.h"
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: Flash_CopyInRAM
+*
+* @brief This section of the code is the one that copies the routine into RAM. 
+* It is following the steps  documented in Technical Note 228
+*        
+* @param  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+#define FLASH_ENABLE_STALLING_FLASH_CONTROLLER
+
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: Flash_Init
+*
+* @brief initialize flash driver
+*        
+* @param  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+uint16_t Flash_Init(void)
+{
+	uint16_t err   = FLASH_ERR_SUCCESS;
+	uint32_t clkDIV = BUS_CLK_HZ/1000000L - 1;
+	uint32_t Tpgs  =(285 *(BUS_CLK_HZ/100))/1000000L;  //update 2016.8.4 by 光脚板のGG
+	uint32_t Tprog =(675*(BUS_CLK_HZ/100))/1000000L;   //by 光脚板のGG
+//        printf("Tpgs= %x \n" , Tpgs);
+//        printf("Tprog= %x \n" , Tprog);   
+        
+	EFMCR=(clkDIV<<24) + 0x00001103; //divide to 1M hz 
+	EFMETM0=(Tpgs<<16)  + 0x00001194;  //0x00281194; //
+	EFMETM1=(Tprog<<16) + 0x000088B8; //
+//        printf("EFMCR= %x \n" , EFMCR); 
+//        printf("EFMETM0= %x \n" , EFMETM0);         
+//        printf("EFMETM1= %x \n" , EFMETM1); 
+  return(err);
+}
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: FlashProgram
+*
+* @brief program flash routine, each program operation supports up to 2 longwords
+* 		 programming
+*        
+* @param  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+uint16_t Flash_Program(uint32_t wNVMTargetAddress, uint8_t *pData, uint16_t sizeBytes)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+	uint16_t w2LongWordCount = sizeBytes>>3;
+	uint8_t  wLeftBytes = (sizeBytes & 0x07);
+	uint16_t wLeftLongWords = wLeftBytes>>2;
+	uint32_t wTargetAddress = wNVMTargetAddress;
+	uint32_t dwData0,dwData1;
+	uint32_t *pdwData = (uint32_t*)pData;
+	int  i;
+ //printf("\n adr : 0x%x ,data = 0x%x\n",w2LongWordCount,wLeftLongWords );
+	// Check address to see if it is aligned to 4 bytes
+	// Global address [1:0] must be 00.
+	if(wNVMTargetAddress & 0x03)
+	{
+		err = FLASH_ERR_INVALID_PARAM;
+		return (err);
+	}
+	// Loop for the two longwords (8 bytes) programming
+	for(i = 0; i < w2LongWordCount; i++)
+	{
+		dwData0 = *pdwData++;
+		dwData1 = *pdwData++;
+		err = Flash_Program2LongWords(wTargetAddress, dwData0, dwData1);
+		if(err)
+		{
+			goto EndP;
+			//break;
+		}
+		wTargetAddress += 8;
+	}
+	// Loop for the single longword (4 bytes) programming
+	for(i = 0; i < wLeftLongWords; i++)
+	{
+		dwData0 = *pdwData++;
+		//printf("\n adr : 0x%x ,data = 0x%x\n",i,dwData0 );
+		err = Flash_Program1LongWord(wTargetAddress, dwData0);
+    //printf("\n adr : 0x%x ,data = 0x%x\n",i,dwData0 );
+		if(err)
+		{			
+			goto EndP;
+			//break;
+		}
+		wTargetAddress += 4;
+	}
+	wLeftBytes = (wLeftBytes-(wLeftLongWords<<2));	// calculate the # of bytes that are not programmed
+	if(!wLeftBytes){
+		return (err);
+	}
+        
+#if     defined(BIG_ENDIAN)                
+	dwData0 = 0;
+	pData = (uint8_t*)pdwData;	// pointer to the left bytes
+	for(i = wLeftBytes; i >0; i--)
+	{
+		dwData0 <<= 8;
+		dwData0 |= *pData++;	// MSB byte first
+	}
+	// Calculate how many bytes need to be filled with 0xFFs
+	// in order to form a single longword for the left bytes of data
+	wLeftBytes = 4 - wLeftBytes;	
+	//  
+	for(i = wLeftBytes; i >0; i--)
+	{
+		dwData0 <<= 8;
+		dwData0 |= 0xFF;	// MSB byte first
+	}
+#else
+	dwData0 = 0xFFFFFFFFL;        
+	pData = (uint8_t*)pdwData+wLeftBytes-1;	// pointer to the left bytes
+	for(i = wLeftBytes; i >0; i--)
+	{
+		dwData0 <<= 8;
+		dwData0 |= *pData--;	// MSB byte first
+	}
+#endif	
+	// Now program the last longword
+	err = Flash_Program1LongWord(wTargetAddress, dwData0);	
+EndP:	
+	return (err);
+}
+
+uint16_t Flash_Program1LongWord(uint32_t wNVMTargetAddress, uint32_t dwData)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+	
+	// Check address to see if it is aligned to 4 bytes
+	// Global address [1:0] must be 00.
+	if(wNVMTargetAddress & 0x03)
+	{
+		err = FLASH_ERR_INVALID_PARAM;
+		return (err);
+	}
+	// Clear error flags
+	EFMCMD = FLASH_CMD_CLEAR;
+	// Write index to specify the command code to be loaded
+	M32(wNVMTargetAddress) = dwData;
+	// Write command code and memory address bits[23:16]	
+        EFM_LaunchCMD(FLASH_CMD_PROGRAM);
+	return (err);
+}
+
+
+uint16_t Flash_Program2LongWords(uint32_t wNVMTargetAddress, uint32_t dwData0, uint32_t dwData1)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+
+	
+	// Check address to see if it is aligned to 4 bytes
+	// Global address [1:0] must be 00.
+	if(wNVMTargetAddress & 0x03)
+	{
+		err = FLASH_ERR_INVALID_PARAM;
+		return (err);
+	}
+	// Clear error flags
+
+	EFMCMD = FLASH_CMD_CLEAR;
+
+//	printf("\n write data  adr : 0x%x ,data = 0x%x\n",dwData0,dwData1 );
+	// Write index to specify the command code to be loaded
+	M32(wNVMTargetAddress) = dwData0;
+	// Write command code and memory address bits[23:16]	
+  EFM_LaunchCMD(FLASH_CMD_PROGRAM);
+	wNVMTargetAddress = wNVMTargetAddress +4;
+	
+	//	printf("\n write data  adr : 0x%x ,data = 0x%x\n",wNVMTargetAddress,dwData1 );
+	// Clear error flags
+		EFMCMD = FLASH_CMD_CLEAR;
+	// Write index to specify the command code to be loaded
+	M32(wNVMTargetAddress) = dwData1;
+	// Write command code and memory address bits[23:16]	
+  EFM_LaunchCMD(FLASH_CMD_PROGRAM);
+//	printf("\n write data  adr : 0x%x ,data = 0x%x\n",wNVMTargetAddress,dwData1 );
+	return (err);
+}
+
+
+
+
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: Flash_EraseSector
+*
+* @brief erase flash sector, each flash sector is of 512 bytes long,
+* global address [1:0] = 00.
+*        
+* @param  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint16_t  Flash_EraseSector(uint32_t wNVMTargetAddress)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+	// Check address to see if it is aligned to 4 bytes
+	// Global address [1:0] must be 00.
+	if(wNVMTargetAddress & 0x03)
+	{
+		err = FLASH_ERR_INVALID_PARAM;
+		return (err);
+	}
+	// Clear error flags
+		EFMCMD = FLASH_CMD_CLEAR;
+	  M32(wNVMTargetAddress) = 0xffffffff;
+	  EFM_LaunchCMD(FLASH_CMD_ERASE_SECTOR);
+	return (err);
+}
+
+uint16_t Flash_VerifyBackdoorKey()
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+//        int i;
+        
+	// Clear error flags
+		EFMCMD = FLASH_CMD_CLEAR;
+	// Write index to specify the command code to be loaded
+	 Custombkd = FLASH_FACTORY_KEY;
+	return (err);
+}
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: NVM_EraseAll
+*
+* @brief erase all block,both flash and EEPROM
+*        
+* @param  
+*	
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint16_t NVM_EraseAll(void)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+		EFMCMD = FLASH_CMD_CLEAR;
+	  EFM_LaunchCMD(FLASH_CMD_ERASE_ALL);
+	// Clear error flags
+    return err;
+}
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: NVM_Unsecure
+*
+* @brief unsecure 
+*        
+* @param  
+*	
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint16_t NVM_Unsecure(void)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+
+    return err;
+}
+
+#ifdef IAR
+void __ramfunc EFM_LaunchCMD(uint32_t EFM_CMD)
+#else
+void EFM_LaunchCMD(uint32_t EFM_CMD)
+#endif
+{
+  DisableInterrupts;
+		if((EFMCMD&EFM_DONE_MASK)== EFM_STATUS_READY)
+		{
+	  EFMCMD = EFM_CMD;
+		}
+	while(1)
+	{
+		if((EFMCMD&EFM_DONE_MASK) == EFM_STATUS_DONE) break;
+	}
+ EnableInterrupts;
+}
diff --git a/bsp/nv32f100x/lib/src/gpio.c b/bsp/nv32f100x/lib/src/gpio.c
new file mode 100644
index 0000000000..5cc10d05a9
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/gpio.c
@@ -0,0 +1,688 @@
+/******************************************************************************
+* @brief providing common gpio API. 
+*
+******************************************************************************/
+#include "gpio.h"
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+*****************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define GPIO APIs
+*
+*//*! @addtogroup gpio_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+* @brief    Initialize the GPIO registers to the default reset values.
+*        
+* @param[in] pGPIO      Pointer to GPIO module, can be GPIOA/GPIOB.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_DeInit(GPIO_Type *pGPIO)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+
+    pGPIO->PCOR = 0x00000000;   /* Port Clear Output Register */
+    pGPIO->PDDR = 0x00000000;   /* Port Data Direction */
+    //pGPIO->PDIR = 0x00000000;   /* Port Data Input Register */
+    pGPIO->PDOR = 0x00000000;   /* Port Data Output Register */
+    pGPIO->PIDR = 0xFFFFFFFF;   /* Port Input Disable Register */
+    pGPIO->PSOR = 0x00000000;   /* Port Set Output Register */
+    pGPIO->PTOR = 0x00000000;   /* Port Toggle Output Register */
+}
+
+/*****************************************************************************//*!
+* @brief    Initialize GPIO pins which are specified by u32PinMask
+*        
+* @param[in] pGPIO      Pointer to GPIO module, can be GPIOA/GPIOB.
+* @param[in] u32PinMask GPIO pin mask need to be set
+* @param[in] sGpioType  pin attribute 
+*
+* @return   none
+*
+* @Note
+*   . High-current drive function is disabled, if the pin is configured as an input
+*   . Internal pullup is disabled if the pin is configured as an output
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_Init(GPIO_Type *pGPIO, uint32_t u32PinMask, GPIO_PinConfigType sGpioType)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+    
+    /* Config GPIO for Input or Output */
+    if ((sGpioType == GPIO_PinOutput) || (sGpioType == GPIO_PinOutput_HighCurrent))
+    {
+        pGPIO->PDDR |= u32PinMask;      /* Enable Port Data Direction Register */
+        pGPIO->PIDR |= u32PinMask;      /* Set Port Input Disable Register */   
+    }
+    else if ((sGpioType == GPIO_PinInput) || (sGpioType == GPIO_PinInput_InternalPullup))
+    {
+        pGPIO->PDDR &= ~u32PinMask;   /* Disable Port Data Direction Register */
+        pGPIO->PIDR &= ~u32PinMask;   /* Clear Port Input Disable Register */
+    }
+    /* Config PORT Pull select for GPIO */
+#if defined(CPU_NV32)
+    switch((uint32_t)pGPIO)
+    {
+        case GPIOA_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEL |= u32PinMask):(PORT->PUEL &= ~u32PinMask);
+            break;
+        case GPIOB_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEH |= u32PinMask):(PORT->PUEH &= ~u32PinMask);
+            break;
+        default:
+            break;
+     }
+#endif
+    
+#if defined(CPU_NV32M3)
+    switch((uint32_t)pGPIO)
+    {
+        case GPIOA_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEL |= u32PinMask):(PORT->PUEL &= ~u32PinMask);
+            break;
+        default:
+            break;
+     }
+#endif
+    
+#if defined(CPU_NV32M4)
+    switch((uint32_t)pGPIO)
+    {
+        case GPIOA_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE0 |= u32PinMask):(PORT->PUE0 &= ~u32PinMask);
+            break;
+        case GPIOB_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE1 |= u32PinMask):(PORT->PUE1 &= ~u32PinMask);
+            break;
+        case GPIOC_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE2 |= u32PinMask):(PORT->PUE2 &= ~u32PinMask);
+            break;
+        default:
+            break;
+     }
+#endif   
+    
+    /* Config PORT GPIO_PinOutput_HighCurrent for GPIO */
+#if defined(CPU_NV32M3)
+    if (u32PinMask & GPIO_PTC5_MASK)
+    {   
+        PORT->HDRVE |= PORT_HDRVE_PTC5_MASK;
+    }   
+    if (u32PinMask & GPIO_PTC1_MASK)
+    {   
+        PORT->HDRVE |= PORT_HDRVE_PTC1_MASK;
+    }   
+    if (u32PinMask & GPIO_PTB5_MASK)
+    {   
+        PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
+    }   
+#endif
+    
+#if defined(CPU_NV32) | defined(CPU_NV32M4)
+    if (pGPIO == GPIOA)
+    {
+        if (u32PinMask & GPIO_PTB4_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTB4_MASK;
+        }   
+        if (u32PinMask & GPIO_PTB5_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
+        }   
+        if (u32PinMask & GPIO_PTD0_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTD0_MASK;
+        }   
+        if (u32PinMask & GPIO_PTD1_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTD1_MASK;
+        }   
+    }
+    if (pGPIO == GPIOB)
+    {
+        if (u32PinMask & GPIO_PTE0_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTE0_MASK;
+        }   
+        if (u32PinMask & GPIO_PTE1_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTE1_MASK;
+        }   
+        if (u32PinMask & GPIO_PTH0_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTH0_MASK;
+        }   
+        if (u32PinMask & GPIO_PTH1_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTH1_MASK;
+        }   
+    }
+
+#endif
+    
+}
+
+
+
+/*****************************************************************************//*!
+* @brief    Toggle the pins which are specified by u32PinMask
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be GPIOA/GPIOB.
+* @param[in] u32PinMask  Specify GPIO pin need to be toggled
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_Toggle(GPIO_Type *pGPIO, uint32_t u32PinMask)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+
+    pGPIO->PTOR = u32PinMask;   /* Toggle the pins specified by u32PinMask */
+}
+
+/*****************************************************************************//*!
+* @brief Read input data from GPIO which is specified by pGPIO
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be GPIOA/GPIOB.
+*
+* @return   GPIO input value unsigned int 32-bit
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint32_t GPIO_Read(GPIO_Type *pGPIO)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+
+    return (pGPIO->PDIR);   /* Read Port Data Input Register */
+  
+}
+
+/*****************************************************************************//*!
+* @brief Read input data from Bit GPIO which is specified by pGPIO
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be GPIOA/GPIOB.
+*
+* @return   Bit GPIO input value 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t GPIO_BitRead(GPIO_PinType GPIO_Pin)
+{
+  uint8_t data;  
+  /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+    
+      
+    /* Config GPIO and pull select*/
+
+      if (GPIO_Pin < GPIO_PTE0)
+      {
+            if(((1<<GPIO_Pin) & GPIOA->PDIR) > 0)       /* Read Bit GPIO input value */
+                data = 0x1;                             /* return value */
+            else 
+                data = 0x0;
+          
+      }
+      
+      else if (GPIO_Pin < GPIO_PTI0)
+      {
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
+        
+            if(((1<<GPIO_Pin) & GPIOB->PDIR) > 0)       /* Read Bit GPIO input value */
+                data = 0x1;                             /* return value */
+            else 
+	       data = 0x0;
+          
+      }
+
+     return data;
+		    
+}
+
+
+/*****************************************************************************//*!
+* @brief    Write output data to GPIO which is specified by pGPIO
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be GPIOA/GPIOB.
+* @param[in] u32Value    value to output
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_Write(GPIO_Type *pGPIO, uint32_t u32Value)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+    
+    pGPIO->PDOR = u32Value;    /* Write Port Ouput Data Register */
+  
+}
+
+/*****************************************************************************//*!
+* @brief    Initialize GPIO single pin which is specified by GPIO_Pin
+*        
+* @param[in] GPIO_Pin        GPIO pin name, can be GPIO_PTA0,1 ...
+* @param[in] GPIO_PinConfig  Config output or input
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_PinInit(GPIO_PinType GPIO_Pin, GPIO_PinConfigType GPIO_PinConfig)
+{
+    /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+      
+    /* Config GPIO and pull select*/
+#if defined(CPU_NV32)
+      if (GPIO_Pin < GPIO_PTE0)
+      {
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEL |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+      else if (GPIO_Pin < GPIO_PTI0)
+      {
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOB->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOB->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEH &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOB->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOB->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEH &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOB->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOB->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEH |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOB->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOB->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEH &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+#endif
+      
+#if defined(CPU_NV32M3)
+      if (GPIO_Pin < GPIO_PTE0)
+      {
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEL |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+#endif
+    
+    
+#if defined(CPU_NV32M4)
+      if (GPIO_Pin < GPIO_PTE0)
+      {
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE0 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE0 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE0 |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE0 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+      else if (GPIO_Pin < GPIO_PTI0)
+      {
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOB->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOB->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE1 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOB->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOB->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE1 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOB->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOB->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE1 |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOB->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOB->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE1 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+      else
+      {
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 64);
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOC->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOC->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE2 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOC->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOC->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE2 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOC->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOC->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE2 |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOC->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOC->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE2 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+#endif
+      
+    /* Config GPIO HDRV */
+    if(GPIO_PinConfig == GPIO_PinOutput_HighCurrent)
+    {
+#if defined(CPU_NV32M3)
+        switch (GPIO_Pin)
+        {
+            case GPIO_PTB5:
+                PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
+                break;
+            case GPIO_PTC1:
+                PORT->HDRVE |= PORT_HDRVE_PTC1_MASK;
+                break;
+            case GPIO_PTC5:
+                PORT->HDRVE |= PORT_HDRVE_PTC5_MASK;
+                break;
+            default:
+                break;
+        }
+#endif
+    
+#if defined(CPU_NV32M4) | defined(CPU_NV32)
+        switch (GPIO_Pin)
+        {
+            case GPIO_PTB4:
+                PORT->HDRVE |= PORT_HDRVE_PTB4_MASK;
+                break;
+            case GPIO_PTB5:
+                PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
+                break;
+            case GPIO_PTD0:
+                PORT->HDRVE |= PORT_HDRVE_PTD0_MASK;
+                break;
+            case GPIO_PTD1:
+                PORT->HDRVE |= PORT_HDRVE_PTD1_MASK;
+                break;
+            case GPIO_PTE0:
+                PORT->HDRVE |= PORT_HDRVE_PTE0_MASK;
+                break;
+            case GPIO_PTE1:
+                PORT->HDRVE |= PORT_HDRVE_PTE1_MASK;
+                break;
+            case GPIO_PTH0:
+                PORT->HDRVE |= PORT_HDRVE_PTH0_MASK;
+                break;
+            case GPIO_PTH1:
+                PORT->HDRVE |= PORT_HDRVE_PTH1_MASK;
+                break;
+            default:
+                break; 
+        }
+#endif
+    }
+}
+
+/*****************************************************************************//*!
+* @brief    Toggle GPIO single pin which is specified by GPIO_Pin
+*        
+* @param[in] GPIO_Pin        GPIO pin name, can be GPIO_PTA0,1 ...
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_PinToggle(GPIO_PinType GPIO_Pin)
+{
+    /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+
+    if (GPIO_Pin < GPIO_PTE0)
+    {
+        /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
+        GPIOA->PTOR = (1<<GPIO_Pin);
+    }
+
+#if (defined(CPU_NV32) | defined(CPU_NV32M4))
+
+    else if (GPIO_Pin < GPIO_PTI0)
+    {
+        /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
+        GPIOB->PTOR = (1<<GPIO_Pin);
+    }
+#endif
+
+#if defined(CPU_NV32M4)  
+    else if(GPIO_Pin < GPIO_PIN_MAX)
+    {
+        /* PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
+        GPIOC->PTOR = (1<<GPIO_Pin);
+    }
+#endif
+}
+
+/*****************************************************************************//*!
+* @brief    Set GPIO single pin which is specified by GPIO_Pin
+*        
+* @param[in] GPIO_Pin        GPIO pin name, can be GPIO_PTA0,1 ...
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_PinSet(GPIO_PinType GPIO_Pin)
+{
+    /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+    
+    if (GPIO_Pin < GPIO_PTE0)
+    {
+        /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
+        GPIOA->PSOR = (1<<GPIO_Pin);
+    }
+
+#if (defined(CPU_NV32) | defined(CPU_NV32M4))
+
+    else if (GPIO_Pin < GPIO_PTI0)
+    {
+        /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
+        GPIOB->PSOR = (1<<GPIO_Pin);
+    }
+#endif
+
+#if defined(CPU_NV32M4) 
+    else if(GPIO_Pin < GPIO_PIN_MAX)
+    {
+        /* PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
+        GPIOC->PSOR = (1<<GPIO_Pin);
+    }
+#endif
+}
+
+/*****************************************************************************//*!
+* @brief    Clear GPIO single pin which is specified by GPIO_Pin
+*        
+* @param[in] GPIO_Pin        GPIO pin name, can be GPIO_PTA0,1 ...
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_PinClear(GPIO_PinType GPIO_Pin)
+{
+    /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+    
+    if (GPIO_Pin < GPIO_PTE0)
+    {
+        /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
+        GPIOA->PCOR = (1<<GPIO_Pin);
+    }
+
+#if (defined(CPU_NV32) | defined(CPU_NV32M4))
+
+    else if (GPIO_Pin < GPIO_PTI0)
+    {
+        /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
+        GPIOB->PCOR = (1<<GPIO_Pin);
+    }
+#endif
+
+#if defined(CPU_NV32M4)
+    else if(GPIO_Pin < GPIO_PIN_MAX)
+    {
+        /* PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
+        GPIOC->PCOR = (1<<GPIO_Pin);
+    }
+#endif
+}
+
+/*! @} End of gpio_api_list */
+
diff --git a/bsp/nv32f100x/lib/src/i2c.c b/bsp/nv32f100x/lib/src/i2c.c
new file mode 100644
index 0000000000..65f7616ef5
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/i2c.c
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* @brief providing APIs for configuring I2C module (I2C). 
+*
+*******************************************************************************
+*
+* provide APIs for configuring I2C module (I2C).
+******************************************************************************/
+#include "common.h"
+#include "i2c.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+static I2C_CallbackType I2C_Callback[2] = {(I2C_CallbackType)NULL};
+/******************************************************************************
+* Local functions
+******************************************************************************/
+void I2C0_Isr( void );
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+
+/******************************************************************************
+* define I2C APIs
+*
+*//*! @addtogroup i2c_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief Initialize I2C module.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+ 	 * @param[in] pI2CConfig point to I2C configure structure.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+void I2C_Init(I2C_Type *pI2Cx,I2C_ConfigPtr pI2CConfig)
+{
+    uint8_t u8Temp;
+
+#if defined(CPU_NV32)
+    SIM->SCGC |= SIM_SCGC_IIC_MASK;
+#elif defined(CPU_NV32M3)
+    SIM->SCGC |= SIM_SCGC_IIC_MASK;
+#elif defined(CPU_NV32M4)
+    if(pI2Cx == I2C0)
+    {
+        SIM->SCGC |= SIM_SCGC_I2C0_MASK;
+    }
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_I2C1_MASK;
+    }
+#endif
+
+	I2C_SetBaudRate(pI2Cx,pI2CConfig->u16F);
+    I2C_SetSlaveAddress(pI2Cx,pI2CConfig->u16OwnA1);
+    pI2Cx->FLT = (uint8_t)pI2CConfig->u16Filt;
+    pI2Cx->RA = (uint8_t)pI2CConfig->u16RangeA & 0xfe;
+    I2C_SetSCLLowETMeout(pI2Cx,pI2CConfig->u16Slt);
+
+    /* configure C2 control register */
+    u8Temp = 0;
+    if( pI2CConfig->sSetting.bGCAEn )
+    {
+        u8Temp |= I2C_C2_GCAEN_MASK;
+    }
+    if( pI2CConfig->sSetting.bAddressExt )
+    {
+        u8Temp |= I2C_C2_ADEXT_MASK;
+    }
+    if( pI2CConfig->sSetting.bRangeAddEn )
+    {
+        u8Temp |= I2C_C2_RMEN_MASK;
+    }
+    pI2Cx->C2 |= u8Temp;
+
+    /* configure SMB rehister */
+    u8Temp = 0;
+    if( pI2CConfig->sSetting.bFackEn )
+    {
+        u8Temp |= I2C_SMB_FACK_MASK;
+    }
+    if( pI2CConfig->sSetting.bSMB_AlertEn )
+    {
+        u8Temp |= I2C_SMB_ALERTEN_MASK;
+    }
+    if( pI2CConfig->sSetting.bSecondAddressEn )
+    {
+        u8Temp |= I2C_SMB_SIICAEN_MASK;
+    }
+    if( pI2CConfig->sSetting.bSHTF2IntEn )
+    {
+        u8Temp |= I2C_SMB_SHTF2IE_MASK;
+    }
+    pI2Cx->SMB = u8Temp;
+    
+    /* configure C1 rehister */
+    u8Temp = 0;
+    if( pI2CConfig->sSetting.bIntEn )
+    {
+        u8Temp |= I2C_C1_IICIE_MASK;
+        if(pI2Cx == I2C0)
+        {
+            NVIC_EnableIRQ(I2C0_IRQn);
+        }
+    #if defined(CPU_NV32M4)     
+        else if(pI2Cx == I2C1)
+        {
+            NVIC_EnableIRQ(I2C1_IRQn);
+        }
+    #endif    
+        else
+        {
+            //
+        }
+    }
+    if( pI2CConfig->sSetting.bWakeUpEn )
+    {
+        u8Temp |= I2C_C1_WUEN_MASK;
+    }
+    if( pI2CConfig->sSetting.bI2CEn )
+    {
+        u8Temp |= I2C_C1_IICEN_MASK;
+    }
+    pI2Cx->C1 = u8Temp;
+
+
+}
+/*****************************************************************************//*!
+   *
+   * @brief send out start signals.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t I2C_Start(I2C_Type *pI2Cx)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+
+    I2C_TxEnable(pI2Cx);
+    pI2Cx->C1 |= I2C_C1_MST_MASK;
+
+    while( (!I2C_IsBusy(pI2Cx)) && ( u32ETMeout < I2C_WAIT_STATUS_ETMEOUT))
+     {
+        u32ETMeout ++;
+     }
+
+     if( u32ETMeout == I2C_WAIT_STATUS_ETMEOUT )
+     {
+        u8ErrorStatus |= I2C_ERROR_START_NO_BUSY_FLAG;
+     }
+
+     return u8ErrorStatus;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief send out stop signals.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t I2C_Stop(I2C_Type *pI2Cx)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+    
+    pI2Cx->C1 &= ~I2C_C1_MST_MASK;
+
+    while( (I2C_IsBusy(pI2Cx) ) && ( u32ETMeout < I2C_WAIT_STATUS_ETMEOUT))
+     {
+        u32ETMeout ++;
+     }
+
+     if( u32ETMeout == I2C_WAIT_STATUS_ETMEOUT )
+     {
+        u8ErrorStatus |= I2C_ERROR_STOP_BUSY_FLAG;
+     }
+
+     return u8ErrorStatus;
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @brief send out repeat start signals.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return error status.
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t I2C_RepeatStart(I2C_Type *pI2Cx)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+    
+    pI2Cx->C1 |= I2C_C1_RSTA_MASK;
+
+    while( (!I2C_IsBusy(I2C0) ) && ( u32ETMeout < I2C_WAIT_STATUS_ETMEOUT))
+     {
+        u32ETMeout ++;
+     }
+
+     if( u32ETMeout == I2C_WAIT_STATUS_ETMEOUT )
+     {
+        u8ErrorStatus |= I2C_ERROR_START_NO_BUSY_FLAG;
+     }
+
+     return u8ErrorStatus;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set slave address.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+void I2C_SetSlaveAddress(I2C_Type *pI2Cx,uint16_t u16SlaveAddress)
+{
+    /* write low 8bit address */
+    pI2Cx->A1 = (uint8_t)u16SlaveAddress;
+
+    /* write high 3bit address if it support 10bit slave address */
+    pI2Cx->C2 &= ~I2C_C2_AD_MASK;
+    pI2Cx->C2 |= (uint8_t)(u16SlaveAddress>>8)&0x03;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief disable IICIF interrupt.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+void I2C_IntDisable(I2C_Type *pI2Cx)
+{
+    pI2Cx->C1 &= ~I2C_C1_IICIE_MASK;
+    if(pI2Cx == I2C0)
+    {
+        NVIC_DisableIRQ(I2C0_IRQn);
+    }
+    #if defined(CPU_NV32M4)
+    else if(pI2Cx == I2C1)
+    {
+        NVIC_DisableIRQ(I2C1_IRQn);
+    }
+    #endif
+    else
+    {
+        
+    }
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable IICIF interrupt.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+void I2C_IntEnable(I2C_Type *pI2Cx)
+{
+    pI2Cx->C1 |= I2C_C1_IICIE_MASK;
+    if(pI2Cx == I2C0)
+    {
+        NVIC_EnableIRQ(I2C0_IRQn);
+    }
+    #if defined(CPU_NV32M4)
+    else if(pI2Cx == I2C1)
+    {
+        NVIC_EnableIRQ(I2C1_IRQn);
+    }
+    #endif
+    else
+    {
+        
+    }
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief SCL low ETMeout value that determines the ETMeout period of SCL low.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+void I2C_SetSCLLowETMeout(I2C_Type *pI2Cx, uint16_t u16ETMeout)
+{
+    pI2Cx->SLTL = (uint8_t)u16ETMeout;
+    pI2Cx->SLTH = (uint8_t)(u16ETMeout>>8);
+}
+/*****************************************************************************//*!
+   *
+   * @brief deinit I2C module.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+void I2C_Deinit(I2C_Type *pI2Cx)
+{
+     pI2Cx->C1 &= ~I2C_C1_IICEN_MASK;
+#if defined(CPU_NV32)
+    SIM->SCGC &= ~SIM_SCGC_IIC_MASK;
+#elif defined(CPU_NV32M3)
+    SIM->SCGC &= ~SIM_SCGC_IIC_MASK;
+#elif defined(CPU_NV32M4)
+    if(pI2Cx == I2C0)
+    {
+        SIM->SCGC &= ~SIM_SCGC_I2C0_MASK;
+    }
+    else
+    {
+        SIM->SCGC &= ~SIM_SCGC_I2C1_MASK;
+    }
+#endif
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief write a byte to I2C module.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   * @param[in] u8WrBuff  data buffer for writing. 
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+uint8_t I2C_WriteOneByte(I2C_Type *pI2Cx, uint8_t u8WrBuff)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+    while (((I2C_GetStatus(pI2Cx)&I2C_S_TCF_MASK) !=  I2C_S_TCF_MASK)
+            && (u32ETMeout<I2C_WAIT_STATUS_ETMEOUT))
+    {
+        u32ETMeout ++;
+    }
+    if (u32ETMeout >= I2C_WAIT_STATUS_ETMEOUT)
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_WAIT_TCF_FLAG; 
+        return u8ErrorStatus;
+    }
+    
+    I2C_TxEnable(pI2Cx);
+    I2C_WriteDataReg(pI2Cx,u8WrBuff);
+
+    u32ETMeout = 0;
+    while (((I2C_GetStatus(pI2Cx)&I2C_S_IICIF_MASK) !=  I2C_S_IICIF_MASK)
+            && (u32ETMeout<I2C_WAIT_STATUS_ETMEOUT))
+    {
+        u32ETMeout ++;
+    }
+    if (u32ETMeout >= I2C_WAIT_STATUS_ETMEOUT)
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_WAIT_IICIF_FLAG; 
+        return u8ErrorStatus;
+    }
+
+    /* clear IICIF flag */
+    I2C_ClearStatus(pI2Cx,I2C_S_IICIF_MASK);
+    if (I2C_GetStatus(pI2Cx) & I2C_S_RXAK_MASK) 
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_GET_ACK;
+    }
+    return u8ErrorStatus;
+}
+/*****************************************************************************//*!
+   *
+   * @brief read a byte from slave I2C.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   * @param[out] pRdBuff point to the data read from slave I2C.
+   * @param[out] u8Ack   send out ack or nack.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+
+uint8_t I2C_ReadOneByte(I2C_Type *pI2Cx, uint8_t *pRdBuff, uint8_t u8Ack)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+    while (((I2C_GetStatus(pI2Cx)&I2C_S_TCF_MASK) !=  I2C_S_TCF_MASK)
+            && (u32ETMeout<I2C_WAIT_STATUS_ETMEOUT))
+    {
+        u32ETMeout ++;
+    }
+    if (u32ETMeout >= I2C_WAIT_STATUS_ETMEOUT)
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_WAIT_TCF_FLAG; 
+        return u8ErrorStatus;
+    }
+    
+    I2C_RxEnable(pI2Cx);
+
+    if( u8Ack )
+    {
+        /* send out nack */
+        I2C_SendNack(pI2Cx);
+       
+    }
+    else
+    {
+         /* send out ack */
+        I2C_SendAck(pI2Cx);
+    }
+    *pRdBuff = I2C_ReadDataReg(pI2Cx);
+
+    u32ETMeout = 0;
+    while (((I2C_GetStatus(pI2Cx)&I2C_S_IICIF_MASK) !=  I2C_S_IICIF_MASK)
+            && (u32ETMeout<I2C_WAIT_STATUS_ETMEOUT))
+    {
+        u32ETMeout ++;
+    }
+    if (u32ETMeout >= I2C_WAIT_STATUS_ETMEOUT)
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_WAIT_IICIF_FLAG; 
+        return u8ErrorStatus;
+    }
+
+    /* clear IICIF flag */
+    I2C_ClearStatus(pI2Cx,I2C_S_IICIF_MASK);
+
+    return u8ErrorStatus;
+}
+/*****************************************************************************//*!
+   *
+   * @brief send data to I2C, and wait to complete transfering.
+   *   
+   * @param[in]  pI2Cx    point to I2C module type.
+   * @param[in]  u16SlaveAddress slave address. 
+   * @param[in]  pWrBuff point the first address of transfering data buffer. 
+   * @param[in]  the length of transfering data.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+
+uint8_t I2C_MasterSendWait(I2C_Type *pI2Cx,uint16_t u16SlaveAddress,uint8_t *pWrBuff,uint32_t u32Length)
+{
+    uint32_t i;
+    uint8_t u8ErrorStatus;
+
+    /* send start signals to bus */
+    u8ErrorStatus = I2C_Start(pI2Cx);
+
+    /* send device address to slave */
+    u8ErrorStatus = I2C_WriteOneByte(pI2Cx,((uint8_t)u16SlaveAddress<<1) | I2C_WRITE);
+
+    /* if no error occur, received the correct ack from slave
+            continue to send data to slave
+        */
+    if( u8ErrorStatus == I2C_ERROR_NULL )
+    {
+        for(i=0;i<u32Length;i++)
+        {
+            u8ErrorStatus = I2C_WriteOneByte(pI2Cx,pWrBuff[i]);
+            if( u8ErrorStatus != I2C_ERROR_NULL )
+            {
+                return u8ErrorStatus;
+            }
+        }
+     }
+
+     /* send stop signals to bus */
+     u8ErrorStatus = I2C_Stop(pI2Cx);
+
+     return u8ErrorStatus;
+            
+}
+/*****************************************************************************//*!
+   *
+   * @brief read data from I2C,and wait to complete transferring.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   * @param[in]  u16SlaveAddress slave address. 
+   * @param[in]  pRdBuff point the first address of reading data buffer. 
+   * @param[in]  the length of transfering data.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+
+uint8_t I2C_MasterReadWait(I2C_Type *pI2Cx,uint16_t u16SlaveAddress,uint8_t *pRdBuff,uint32_t u32Length)
+{
+    uint32_t i;
+    uint8_t u8ErrorStatus;
+
+    /* send start signals to bus */
+    u8ErrorStatus = I2C_Start(pI2Cx);
+
+    /* send device address to slave */
+    u8ErrorStatus = I2C_WriteOneByte(pI2Cx,((uint8_t)u16SlaveAddress<<1) | I2C_READ);
+
+    /* if no error occur, received the correct ack from slave
+            continue to send data to slave
+        */
+    /* dummy read one byte to switch to Rx mode */
+    I2C_ReadOneByte(pI2Cx,&pRdBuff[0],I2C_SEND_ACK);
+    
+    if( u8ErrorStatus == I2C_ERROR_NULL )
+    {
+        for(i=0;i<u32Length-1;i++)
+        {
+            u8ErrorStatus = I2C_ReadOneByte(pI2Cx,&pRdBuff[i],I2C_SEND_ACK);
+            if( u8ErrorStatus != I2C_ERROR_NULL )
+            {
+                return u8ErrorStatus;
+            }
+        }
+        u8ErrorStatus = I2C_ReadOneByte(pI2Cx,&pRdBuff[i],I2C_SEND_NACK);
+     }
+     /* send stop signals to bus */
+     u8ErrorStatus = I2C_Stop(pI2Cx);
+     
+     return u8ErrorStatus;
+            
+}
+/*****************************************************************************//*!
+   *
+   * @brief set call back function for I2C1 module.
+   *        
+   * @param[in] pCallBack point to address of I2C1 call back function.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria:  none.
+*****************************************************************************/
+
+void I2C1_SetCallBack( I2C_CallbackType pCallBack )
+{
+    I2C_Callback[1] = pCallBack;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set call back function for I2C0 module.
+   *        
+   * @param[in] pCallBack point to address of I2C0 call back function.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria:  none.
+*****************************************************************************/
+
+void I2C0_SetCallBack( I2C_CallbackType pCallBack )
+{
+    I2C_Callback[0] = pCallBack;
+}
+/*! @} End of i2c_api_list                                               						*/
+
+
+/*****************************************************************************//*!
+   *
+   * @brief I2C0 interrupt service routine.
+   *        
+   * @param  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+void I2C0_Isr( void )
+{
+    if( I2C_Callback[0] )
+    {
+        I2C_Callback[0]();
+    }
+}
+/*****************************************************************************//*!
+   *
+   * @brief I2C1 interrupt service routine.
+   *        
+   * @param  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+void I2C1_Isr( void )
+{
+    if( I2C_Callback[1] )
+    {
+        I2C_Callback[1]();
+    }
+}
+
+
+
diff --git a/bsp/nv32f100x/lib/src/ics.c b/bsp/nv32f100x/lib/src/ics.c
new file mode 100644
index 0000000000..8e7a791218
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/ics.c
@@ -0,0 +1,1109 @@
+/*************************************************************!     
+ *     技术讨论：QQ群  123763203
+ *     官网    ：www.navota.com
+ *
+ * @file       ics.c
+ * @brief      时钟模块（ICS)函数库
+ * @author     Navota
+ * @date       2017-1-1
+ ****************************************************************/
+#include "common.h"
+#include "ics.h"
+
+/* 复位后ICS和OSC模块寄存器的默认值 */
+#define ICS_C1_DEFAULT  0x04
+#define ICS_C2_DEFAULT  0x20
+#define ICS_C3_DEFAULT  0x54
+#define ICS_C4_DEFAULT  0x00
+#define ICS_S_DEFAULT   0x50
+#define OSC_CR_DEFAULT  0
+
+
+/*****************************************************************************//*!
+   * 
+   * @ 概要  ICS的工作模式由当前的FEI模式切换为FEE模式，对选中的时钟源做1分频
+   *         OSC模块的输出时钟选择振荡器时钟源
+   * 
+   * @ 参数【输入】 pConfig  指向ICS配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   *****************************************************************************/
+void FEI_to_FEE(ICS_ConfigType *pConfig)
+{
+	/*
+	 * 使能OSC模块
+	 */
+	OSC_Init(&pConfig->oscConfig); /*OSC模块初始化 */
+	
+	/* 
+     * 对外部参考时钟进行分频，可将外部时钟分频到31.25k~39.0625k之间
+	 */
+ 
+    ICS_SetClkDivider(pConfig->u32ClkFreq);
+
+        /*将FLL的参考时钟选择为外部时钟*/
+	ICS->C1 =  ICS->C1 & ~ICS_C1_IREFS_MASK;
+         
+        /*等待FLL参考时钟变为外部时钟*/
+
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop 
+};        
+#endif        
+	while(ICS->S & ICS_S_IREFST_MASK);
+	
+        /* 等待FLL时钟成为ICS输出时钟源*/
+	while(!(ICS->S & ICS_S_LOCK_MASK));
+		
+	/*
+     *现在FLL输出时钟变时钟频率等于FLL参考时钟分频结果乘以FLL的倍频系数
+	 * FLL的倍频系数请参考参考手册
+	 */
+#if defined(CPU_NV32)
+  /*对选中的ICS输出时钟源做1分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) == 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	
+	/*
+	 * 完成对选中的时钟源做1分频，系统/总线时钟时频率为设置的目标频率
+	 */
+    /*LOLS清0*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  ICS的工作模式由当前的FEI模式转变成FBI模式，对选中的ICS输出时钟源
+   *         进行2分频
+   *        
+   * @ 参数  pConfig    指向ICS配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FEI_to_FBI(ICS_ConfigType *pConfig)
+{
+
+        /*ICS输出时钟源选择内部参考时钟*/
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(1);   
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+        /*等待内部时钟成为ICS输出时钟源*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif        
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=1);
+			
+	/*
+	 * 现在内部参考时钟为ICS输出时钟源
+	 */
+#if defined(BUS_CLK_EQU_CORE_DIVIDE_BY_2)||defined(CPU_NV32) 
+         /*对选中的ICS输出时钟源做2分频*/       
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+
+#else
+	ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK));     
+#endif        
+	
+     /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  ICS的工作模式由当前的FEI模式转换成FBE模式，对选中的ICS输出时钟源做2分频
+   *         OSC模块的输出时钟选择振荡器时钟源
+   *
+   * @ 参数  pConfig   指向ICS的配置结构体 . 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+
+void FEI_to_FBE(ICS_ConfigType *pConfig)
+{
+	OSC_Init(&pConfig->oscConfig); /*初始化OSC 模块 */
+
+         /*设置FLL的参考时钟为外部时钟*/
+
+    ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(2);   
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+       
+        /*等在参考时钟发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif        
+
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=2);  /*外部时钟成为ICS时钟输出源*/
+        while(ICS->S & ICS_S_IREFST_MASK);  /*FLL参考时钟成为外部时钟*/
+			
+	/* 
+	 * 现在外部时钟成为ICS输出时钟源
+	 */
+#if defined(CPU_NV32)
+        /*对选中的ICS输出时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	/* 
+	 * 现在ICS输出时钟频率为选中的输出时钟源的2分频
+	 */
+        /* LOLS清零 */
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  ICS的工作模式由当前的FEI模式转换成FBE模式，对选中的输出时钟源做2分频 
+   *         OSC输出时钟选择EXTAL引脚的外部时钟源 
+   *
+   * @ 参数 pConfig  指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FEI_to_FBE_OSC(ICS_ConfigType *pConfig)
+{
+    
+	OSC_Init(&pConfig->oscConfig); /* 初始化OSC */
+
+	/* 
+	 * 设置外部参考时钟的分频系数，将参考时钟的分频结果设定在FLL可以锁定的31.25k~39.0625k范围内，
+	 */
+    ICS_SetClkDivider(pConfig->u32ClkFreq);
+    
+        /*改变参考时钟源，将FLL的参考时钟设置为而外部时钟*/
+        ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);/*将FLL的参考时钟设置为而外部时钟*/
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(2);  /*输出时钟源选择外部时钟*/ 
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+        
+        /* 等待参考时钟发生改变*/
+
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=2);/*外部时钟成为ICS时钟输出时钟源*/
+        while(ICS->S & ICS_S_IREFST_MASK);   /*外部时钟成为FLL参考时钟*/
+			
+	/* 
+	 * 现在外部时钟成为FLL参考时钟和ICS输出时钟源
+	 */
+#if defined(CPU_NV32)
+             /*对选中的ICS输出时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	/* 
+	 * 现在ICS的输出时钟频率，为外部参考时钟的2分频
+	 */
+        /*LOLS 清零*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  ICS的工作模式由当前的FEI模式转换FEE模式，对选中的ICS输出时钟源做2分频 
+   *         OSC输出时钟选择EXTAL引脚的外部时钟源
+   *
+   * @ 参数  pConfig    指向配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+
+void FEI_to_FEE_OSC(ICS_ConfigType *pConfig)
+{
+
+	OSC_Init(&pConfig->oscConfig); /* 初始化OSC */
+
+	/* 
+	 * 设置外部参考时钟的分频系数，将参考时钟的分频结果设定在FLL可以锁定的31.25k~39.0625k范围内
+	 */
+    ICS_SetClkDivider(pConfig->u32ClkFreq);
+
+        /* 将FLL的参考时钟设置为外部时钟 */
+        
+    ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);
+
+        /*等待参考时钟变化*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(ICS->S & ICS_S_IREFST_MASK); /*FLL参考时钟变为外部时钟*/
+	
+        /*等待FLL成为ICS输出时钟源 */
+	while(!(ICS->S & ICS_S_LOCK_MASK));
+#if defined(CPU_NV32)	
+       /*对选中的时钟源做2分频*/	
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	/* 
+	 * 现在ICS输出时钟频率，成为要设置的目标频率
+	 */
+
+     /* LOLS清零 */
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FEE模式转换成FEI模式.
+   *        
+   * @ 参数  pConfig  指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FEE_to_FEI(ICS_ConfigType *pConfig)
+{
+       /*选择内部时钟作为FLL的参考时钟*/ 
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	
+        /*等待参考时钟发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(!(ICS->S & ICS_S_IREFST_MASK)); /*FLL参考时钟成为内部时钟*/
+	
+        /*FLL时钟成为ICS输出时钟源 */
+	while(!(ICS->S & ICS_S_LOCK_MASK));
+         /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;
+
+	/* 
+	 * 现在FLL输出成为ICS输出时钟源
+	 */
+#if defined(CPU_NV32)
+        /*对选中的ICS输出时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	/* 
+	 * 现在系统/总线时钟大约为 16MHz
+	 */
+	    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+      OSC_Disable();            /* 禁用 OSC模块 */
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FEE模式转换成FBI模式.
+   *        
+   * @ 参数 pConfig    指向配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FEE_to_FBI(ICS_ConfigType *pConfig)
+{
+        /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;
+	
+  /* 选择内部时钟作为ICS输出时钟源 */
+	/* 选择内部时钟作为FLL参考时钟 */ 
+	/* LP = 0 在bypass模式FLL不会被禁止*/
+        
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(1);   
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+
+        /* 等待参考时钟发生改变 */
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(!(ICS->S & ICS_S_IREFST_MASK));  /*FLL参考时钟成为内部时钟*/
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=1);  /*内部时成为ICS输出时钟源*/
+	
+#if defined(BUS_CLK_EQU_CORE_DIVIDE_BY_2)||defined(CPU_NV32)  
+         /*对所选中的ICS输出时钟源做2分频*/      
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+
+#else
+	ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK));
+       
+#endif    
+        OSC_Disable();            
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  将ICS的工作模式由当前的FEE模式转变成FBE模式
+   *        
+   * @ 参数  pConfig  指向配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+
+void FEE_to_FBE(ICS_ConfigType *pConfig)
+{
+        /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;
+	
+	
+        /* LP = 0 */
+        /*选择外部时钟作为ICS输出时钟源*/
+        /* LP = 0 在bypass模式FLL不会被禁止*/
+
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(2);   
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+
+        /*等待输出时钟源发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=2);
+	
+   /* 现在ICS输出时钟源选择外部时钟源
+	 * 注释: 确保外部时钟频率在20MHz以内
+	 */
+#if defined(CPU_NV32)
+        /*对选择的ICS输出时钟源做2分频*/	 
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBI模式转换成FBE模式
+   *        
+   * @ 参数  pConfig   指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBI_to_FBE(ICS_ConfigType *pConfig)
+{
+	OSC_Init(&pConfig->oscConfig); /*初始化OSC*/
+    
+	/* 选择外部时钟做为FLL的参考时钟 */
+	/*选择外部时钟作为输出时钟源*/
+
+       ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(2);   
+
+
+	/* 等待输出时钟源发生改变 */
+
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=2); /*外部时钟成为ICS输出时钟源*/
+	while((ICS->S & ICS_S_IREFST_MASK));/*外部时钟成为FLL的参考时钟*/
+
+        /* 现在系统时钟源是外部参考时钟
+	 * 注释:确保外部时钟源的频率在20MHz内
+	 */
+#if defined(CPU_NV32)
+         /*对选中的时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+}
+
+/*****************************************************************************//**
+   *
+   * @ 概要 将ICS的工作模式由当前的FBI模式转换成FEE模式
+   *        
+   * @ 参数  pConfig    指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBI_to_FEE(ICS_ConfigType *pConfig)
+{
+	OSC_Init(&pConfig->oscConfig); /*初始化OSC*/
+ 
+	/* 选择外部时钟作为FLL的参考时钟 */
+	/* 选择FLL输出作为做为ICS输出时钟源*/
+
+    ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK));   
+
+        /*等待时钟源改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+
+	while((ICS->S & ICS_S_CLKST_MASK));   /*FLL时钟成为ICS输出时钟源*/
+	while((ICS->S & ICS_S_IREFST_MASK));  /*外部时钟成为FLL参考时钟*/
+	
+     /* 现在系统时钟源为外部时钟
+	 * 注释: 确保外部时钟源的频率在20MHz内
+	 */
+#if defined(CPU_NV32)
+        /*对选中的时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+       /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBI模式转换成FBIP模式 
+   * 
+   * @ 参数  pConfig   输出指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 警告 必须运行在调试接口没有没有接线的状态下
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBI_to_FBILP(ICS_ConfigType *pConfig)
+{
+	/*
+	 * 假设外部晶振时8MHz或者4MHz
+	 */
+	ICS->C2 |= ICS_C2_LP_MASK;	/*进入低功耗模式 */
+}
+
+
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBI模式转变为FEI模式
+   * 
+   * @ 参数 pConfig  指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBI_to_FEI(ICS_ConfigType *pConfig)
+{
+     /* 选择内部时钟为FLL的参考时钟 */
+	/*选择FLL输出作为ICS输出时钟源*/
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK));   
+	
+        /*等待时钟源发生改变*/
+
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while((ICS->S & ICS_S_CLKST_MASK));    /*FLL输出成为ICS输出时钟源*/
+	while(!(ICS->S & ICS_S_IREFST_MASK));  /*FLL的参考时钟选择为外部时钟*/
+
+        
+	/* 
+	 * 现在ICS输出时钟源为FLL输出
+	 */
+#if defined(CPU_NV32)
+         /*对选中的时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+
+        /*LOLS清零 */
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  将ICS的工作模式由当前的FBE模式转换成FBI模式
+   *        
+   * @ 参数  pConfig   指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBE_to_FBI(ICS_ConfigType *pConfig)
+{
+        /*选择内部时钟作为FLL的参考时钟*/
+	/*选择内部时钟作为ICS输出时钟源*/
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(1);   
+	
+        /*等待时钟源发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) != 1);/*内部时钟成为ICS输出时钟源*/
+	while(!(ICS->S & ICS_S_IREFST_MASK)); /*内部时钟成为FLL的参考时钟*/
+	
+	/* 
+	 * 现在ICS输出时钟源为内部时钟
+	 */
+	 
+#if defined(CPU_NV32)
+        /*对选中的时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+        
+    /* 
+     * 禁用OSC模块
+     */
+    OSC_Disable();
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBE模式转换成FEE模式
+   *        
+   * @ 参数 pConfig   指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBE_to_FEE(ICS_ConfigType *pConfig)
+{
+	
+        /*选择FLL输出作为输出时钟源*/
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK));   
+	
+        /*等待ICS输出时钟源发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(ICS->S & ICS_S_CLKST_MASK);
+
+	
+	/* 
+    * 现在ICS输出时钟源为FLL输出
+	 * 注释: 外部时钟频率 <= 20MHz
+	 */
+#if defined(CPU_NV32)
+         /*对选中的ICS输出时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif	
+         /* LOLS清零 */
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBE模式转变成FEI模式
+   *        
+   * @ 参数 pConfig    指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBE_to_FEI(ICS_ConfigType *pConfig)
+{
+    /* 选择内部时钟作为FLL的参考时钟*/
+	/*选择FLL输出做为ICS输出时钟源*/
+
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK));   
+	
+        /*等待时钟源改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while((ICS->S & ICS_S_CLKST_MASK));   /*FLL输出成为ICS输出时钟源*/
+	while(!(ICS->S & ICS_S_IREFST_MASK)); /*内部时钟中成为FLL参考时钟*/
+
+  /* 
+   * 现在FLL输出成为ICS输出时钟源
+   */
+
+#if defined(CPU_NV32)
+
+       /*对选中的时钟源做2分频*/	
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif	
+         /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+        
+    /*
+     *禁用OSC模块
+     */
+    OSC_Disable();
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBE模式转变为FBELP模式
+   *
+   * @ 参数  pConfig   指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBE_to_FBELP(ICS_ConfigType *pConfig)
+{
+	/* enter low power mode */
+        /*进入低功耗模式*/
+ 	ICS->C2 = ICS->C2 | (ICS_C2_LP_MASK); 
+}
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBELP模式转换成FBE模式
+   * 
+   * @ 参数  pConfig     指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBELP_to_FBE(ICS_ConfigType *pConfig)
+{
+	/* enter low power mode */
+        /*禁用低功耗模式*/
+ 	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBILP转换到FBI模式 
+   * 
+   * @ 参数  pConfig  指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBILP_to_FBI(ICS_ConfigType *pConfig)
+{
+	/* enter low power mode */
+        /*禁用低功耗模式*/
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 调整内部内部时钟 (IRC). 
+   * 
+   * @ 参数  u16TrimValue   调整值 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   *****************************************************************************/
+
+void ICS_Trim(uint16_t u16TrimValue)
+{
+   ICS->C3 =  (uint8_t) u16TrimValue;  /*将调整值写入寄存器*/
+   ICS->C4 = (ICS->C4 & ~(ICS_C4_SCFTRIM_MASK)) | ((u16TrimValue>>8) & 0x01);
+   while(!(ICS->S & ICS_S_LOCK_MASK));    
+}
+/*****************************************************************************//*!
+   *
+   * @ 概要 对外部参考时钟进行分频，使得分频结果在FLL可以锁定的31.25k~39.0625k内
+   *
+   * @ 参数 u32ClkFreqKHz    参考时钟频率.
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   *****************************************************************************/
+
+void ICS_SetClkDivider(uint32_t u32ClkFreqKHz)
+{
+    
+    switch(u32ClkFreqKHz)
+    {
+        case 8000L:
+        case 10000L:
+            /* 8MHz or 10MHz*/
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(3);	
+                                                                         /*8MHz分频结果是 8000/256 = 31.25K */ 
+                                                                        /*10MHz分频结果是 8000/256 = 31.25K*/ 
+            break;
+        case 4000L:
+            /* 4MHz */
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(2);	
+                                                                        /*4MHz分频结果是 4000/128 = 31.25K*/
+            break;
+        case 12000L:
+            /* 12MHz */
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(3);	
+                                                                        /*12MHz分频结果是12000/512 = 23.43K*/
+            break;
+        case 16000L:
+            /* 16MHz */
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(4);	
+                                                                        /* 16MHz分频结果是 16000/512 = 31.25K */
+            break;
+        case 20000L:
+            /* 20MHz */
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(4); 
+                                                                        /*20MHz分频结果是 20000/512 = 39.0625K */
+            break;
+        case 32L:
+            /* 32KHz */
+            ICS->C1  &= ~(ICS_C1_RDIV_MASK);
+            break;
+        default:
+            break;
+    }
+}
+/*****************************************************************************//*!
+   *
+   * @ 概要 初始化ICS模块根据定义所需要的总线时钟频率.
+   * 
+   * @ 参数 pConfig  指向配置结构体.  
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+
+
+void ICS_Init(ICS_ConfigType *pConfig)
+{
+  if(pConfig->u8ClkMode == ICS_CLK_MODE_FEE)
+  {    
+        pConfig->oscConfig.bIsCryst = 1;   /* OSC的输出选择选择振动器时钟源 */ 
+        pConfig->oscConfig.bWaitInit = 1;  /* 等待振荡器初始化化完成 */       
+     
+      /*选择FEE模式，OSC输出选择振荡器时钟源*/
+        FEI_to_FEE(pConfig);             
+  }
+  else if (pConfig->u8ClkMode == ICS_CLK_MODE_FEE_OSC)
+  {     
+        pConfig->oscConfig.bIsCryst = 0;     /*OSC输出时钟选择EEXTAL引脚的外部时钟源*/ 
+
+     /*选择FEE工作模式；OSC输出时钟选择EEXTAL引脚的外部时钟源*/
+        FEI_to_FEE_OSC(pConfig);                
+  }
+  else if (pConfig->u8ClkMode == ICS_CLK_MODE_FBE_OSC)
+  {
+        pConfig->oscConfig.bIsCryst = 0;  /* is clock：OSC输出时钟选择EXTAL引脚的外部时钟源 */            
+        /* 选择FBE工作模式；OSC输出时钟选择EXTAL引脚的外部时钟源*/
+        FEI_to_FBE_OSC(pConfig);               
+  } 
+	else if(pConfig->u8ClkMode == ICS_CLK_MODE_FBELP )
+	{
+	pConfig->oscConfig.bIsCryst = 1;        /* OSC的输出时钟选择选择振动器时钟源 */
+        pConfig->oscConfig.bWaitInit = 1;       /*等待振荡器初始化化完成 */		
+
+        /* 选择FBE模式，OSC的输出时钟选择选择振动器时钟源*/
+                    FEI_to_FBE(pConfig);    /*先选择PBE模式*/            
+		    FBE_to_FBELP(pConfig);   /*选择FBELP*/
+		    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+	}
+		else if(pConfig->u8ClkMode == ICS_CLK_MODE_FBILP )
+	{
+       
+            /* OSC输出时钟选择EXTAL引脚的外部时钟源*/            
+		    pConfig->oscConfig.bIsCryst = 0; 
+     
+            /* 选择FBE模式，OSC输出时钟选择EXTAL引脚的外部时钟源*/
+              FEI_to_FBI(pConfig);               
+	      FBI_to_FBILP(pConfig); 
+	      ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+	}
+  else
+  {
+      
+       /*ICS默认工作模式FEI模式*/
+        #if defined(CPU_NV32)
+        if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) == 1)
+        {
+            ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+        }
+        #else
+            ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+        #endif
+  }
+
+}
+/*****************************************************************************//*!
+   *
+   * @ 概要 对ICS模块各寄存器进行复位.
+   * 
+   * @ 无参数   
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_Init
+   *****************************************************************************/
+
+void ICS_DeInit(void)
+{
+    ICS->C1 = ICS_C1_DEFAULT;
+    ICS->C2 = ICS_C2_DEFAULT;
+    ICS->C3 = ICS_C3_DEFAULT;
+    ICS->C4 = ICS_C4_DEFAULT;
+    while(ICS->S != ICS_S_DEFAULT)
+        ;       
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 通过设定的参数初始化XOSC
+   * 
+   * @ 参数  pConfig   指向osc配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   *****************************************************************************/
+void OSC_Init(OSC_ConfigType *pConfig)
+{
+	uint8   cr = 0;
+	/* 
+	 * 
+	 */
+	if(pConfig->bGain) /*高增益振荡器选择*/
+	{
+		/* high gain：选择高增益模式 */
+		cr |= OSC_CR_HGO_MASK ;		
+	}  
+	
+	if(pConfig->bRange)  /*频率范围的选择*/
+	{
+		cr |= OSC_CR_RANGE_MASK; /*选择高频范围 */	
+	}
+
+	if(pConfig->bStopEnable) /*停止模式下的OSC使能*/
+	{
+		cr |= OSC_CR_OSCSTEN_MASK; /*OSC在停止模式下保持使能*/
+	}
+
+	if(pConfig->bIsCryst)     /*OSC输出选择*/
+	{
+		cr |= OSC_CR_OSCOS_MASK; /*选择振荡器时钟*/
+	}
+
+	if(pConfig->bEnable)  /*OSC使能*/
+	{
+		cr |= OSC_CR_OSCEN_MASK;
+	}
+    
+    OSC->CR = cr;   /*数值写入控制寄存器*/
+    
+	if(pConfig->bWaitInit)
+	{
+
+		/* 
+     *等待初始化完成
+		 */
+		while(!(OSC->CR & OSC_CR_OSCINIT_MASK));
+		
+	}
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 重置OSC模块，使其恢复到默认状态.
+   * 
+   * @ 无输参数      
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看   ICS_Init
+   *****************************************************************************/
+
+void OSC_DeInit(void)
+{
+    OSC->CR = OSC_CR_DEFAULT;
+}
+                                                	
+
+
+
+
diff --git a/bsp/nv32f100x/lib/src/kbi.c b/bsp/nv32f100x/lib/src/kbi.c
new file mode 100644
index 0000000000..263e7341c2
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/kbi.c
@@ -0,0 +1,296 @@
+/******************************************************************************
+*
+* @brief providing APIs for configuring KBI. 
+*
+*******************************************************************************
+*
+* provide APIs for configuring KBI
+******************************************************************************/
+#include "common.h"
+#include "kbi.h"
+/******************************************************************************
+* External objects
+******************************************************************************/
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+KBI_CallbackType KBI_Callback[KBI_MAX_NO] = {(KBI_CallbackType)NULL};
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+/******************************************************************************
+* KBI api list
+*
+*//*! @addtogroup kbi_api_list
+* @{
+*******************************************************************************/
+
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize KBI module.
+*        
+* @param[in]  pKBI        pointer to KBI module.
+* @param[in]  pConfig     pointer to KBI configuration structure.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DeInit.
+*
+*****************************************************************************/
+void KBI_Init(KBI_Type *pKBI, KBI_ConfigType *pConfig)
+{
+#if defined(CPU_NV32)
+    uint16_t    i;
+    uint8_t     sc = 0;
+    uint8_t     u8Port;
+    uint8_t     u8PinPos;
+    uint16_t    u16PinMapping[KBI_MAX_NO][8] = 
+    {
+        {
+            0, 1, 2, 3, 8, 9, 10, 11           /* KBI0 pins position in GPIOA register */
+        },
+        {
+            24, 25, 26, 27, 28, 29, 30, 31      /* KBI1 pins position in GPIOA register */
+        }
+    };
+#elif defined(CPU_NV32M3)
+    uint16_t    i;
+    uint8_t     sc = 0;
+    uint8_t     u8Port;
+    uint8_t     u8PinPos;
+    uint16_t    u16PinMapping[KBI_MAX_NO][8] = 
+    {
+        {
+            0, 1, 2, 3, 8, 9, 10, 11           /* KBI0 pins position in GPIOA register */
+        },
+        {
+            20, 21, 16, 17, 18, 19, 12, 13      /* KBI1 pins position in GPIOA register */
+        }
+    };
+#elif defined(CPU_NV32M4)
+     uint32_t    i;
+     uint32_t     sc = 0;
+     uint32_t     u8Port;
+     uint32_t     u8PinPos;
+
+     uint32_t    u16PinMapping[KBI_MAX_NO][KBI_MAX_PINS_PER_PORT] =
+    {
+        {/* KBI0P0~KBI0P31 pins position in GPIOA register */
+            0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31           
+        },
+        {/* KBI1P0~KBI1P31 pins position in GPIOB register */
+			0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31		   
+        }
+    };
+#endif	 
+ 
+    
+    if(KBI0 == pKBI)
+    {
+        SIM->SCGC   |= SIM_SCGC_KBI0_MASK;             /* enable clock to KBI0 */\
+        u8Port      =  0;
+    }
+    else if (KBI1 == pKBI)
+    {        
+        SIM->SCGC   |= SIM_SCGC_KBI1_MASK;             /* enable clock to KBI1 */
+        u8Port      =  1;
+    }
+    
+    /* mask keyboard interrupts first */
+    sc          = pConfig->sBits.bMode;
+    pKBI->SC    = sc;
+
+    /* configure KBI pin polarity and others */
+    for (i = 0; i < KBI_MAX_PINS_PER_PORT; i++)
+    {
+        if(pConfig->sPin[i].bEn)
+        {
+            pKBI->PE    |= (1<<i);                      /* enable this KBI pin */
+            pKBI->ES    = (pKBI->ES & ~(1<<i)) | (pConfig->sPin[i].bEdge << i);     
+            u8PinPos = u16PinMapping[u8Port][i];
+            ASSERT(!(u8PinPos & 0x80));
+		#if defined(CPU_NV32)|| defined(CPU_NV32M3)	
+            FGPIOA->PIDR  &= ~(1<<u8PinPos);              /* enable GPIO input */     
+            FGPIOA->PDDR  &= ~(1<<u8PinPos);              /* configure pin as input */  
+            PORT->PUEL  |= (1<<u8PinPos);                 /* enable pullup for the pin */
+        #elif defined(CPU_NV32M4)
+		   if (u8Port == 0)   /* KBI0 */
+           {
+		   	FGPIOA->PIDR  &= ~(1<<u8PinPos);              /* enable GPIO input */    
+            FGPIOA->PDDR  &= ~(1<<u8PinPos);              /* configure pin as input */ 
+            PORT->PUE0  |= (1<<u8PinPos);                 /*enable pullup for the pin */
+           }
+		   else if (u8Port == 1)   /* KBI1 */
+           {
+		   	FGPIOB->PIDR  &= ~(1<<u8PinPos);              /* enable GPIO input */     
+            FGPIOB->PDDR  &= ~(1<<u8PinPos);              /* configure pin as input */ 
+            PORT->PUE1  |= (1<<u8PinPos);                 /*enable pullup for the pin */
+           }
+		#endif  
+		}
+    }
+    
+    #if defined(CPU_NV32M4)
+    /*Reset KBI_SP register*/
+	sc = pConfig->sBits.bRstKbsp<<KBI_SC_RSTKBSP_SHIFT;
+	pKBI->SC    |= sc;
+	
+    /*Real KBI_SP register enable*/
+	sc = pConfig->sBits.bKbspEn<<KBI_SC_KBSPEN_SHIFT;
+	pKBI->SC    |= sc;
+	#endif
+  
+	/* write to KBACK to clear any false interrupts */
+    pKBI->SC    = sc;
+    
+    /* enable interrupt if needed */
+    if(pConfig->sBits.bIntEn)
+    {
+        pKBI->SC    |=  KBI_SC_KBIE_MASK;
+        
+        if(KBI0 == pKBI)
+        {
+            NVIC_EnableIRQ(KBI0_IRQn);
+        }
+        else
+        {
+            NVIC_EnableIRQ(KBI1_IRQn);            
+        }
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief set up KBI callback routine.
+*        
+* @param[in] pKBI          pointer to KBI module.
+* @param[in] pfnCallback   pointer to callback routine.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void KBI_SetCallback(KBI_Type *pKBI, KBI_CallbackType pfnCallback)
+{
+    if(KBI0 == pKBI)
+    {
+        KBI_Callback[0] = pfnCallback;
+    }
+    else
+    {
+        KBI_Callback[1] = pfnCallback;        
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief deinit the kbi module.
+*        
+* @param[in]  pKBI       pointer to KBI module.
+*         
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_Init.
+*
+*****************************************************************************/
+void KBI_DeInit(KBI_Type *pKBI)
+{
+    if(KBI0 == pKBI)
+    {
+        NVIC_DisableIRQ(KBI0_IRQn);
+    }
+    else
+    {
+        NVIC_DisableIRQ(KBI1_IRQn);        
+    }
+    
+    pKBI->PE = 0;
+    pKBI->SC = 0;
+    pKBI->ES = 0;
+    
+    if(KBI0 == pKBI)
+    {
+        SIM->SCGC   &= ~SIM_SCGC_KBI0_MASK;             /* disable clock to KBI0 */
+    }
+    else
+    {
+        SIM->SCGC   &= ~SIM_SCGC_KBI1_MASK;             /* disable clock to KBI1 */       
+    }
+}
+
+/*! @} End of acmp_api_list                                                  */
+
+/*****************************************************************************//*!
+*
+* @brief button group 0 (KBI0) interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+
+void KBI0_Isr(void)	
+{
+  KBI0->SC |= KBI_SC_KBACK_MASK;                        /* clear interrupt flag */
+
+  if(KBI_Callback[0])
+  {
+      KBI_Callback[0]();
+  }
+}
+
+
+
+/*****************************************************************************//*!
+*
+* @brief button group 0 (KBI0) interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+
+void KBI1_Isr(void)	
+{
+  KBI1->SC |= KBI_SC_KBACK_MASK;                        /* clear interrupt flag */
+ 
+  if(KBI_Callback[1])
+  {
+      KBI_Callback[1]();
+  }
+}
+
diff --git a/bsp/nv32f100x/lib/src/pit.c b/bsp/nv32f100x/lib/src/pit.c
new file mode 100644
index 0000000000..ed3fb2d924
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/pit.c
@@ -0,0 +1,213 @@
+/******************************************************************************
+* @brief    Periodic Interrupt ETMer (PIT) source code. 
+*
+******************************************************************************/
+#include "common.h"
+#include "pit.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+/*!
+ * @brief global variable to store PIT callbacks.
+ *
+ */
+PIT_CallbackType PIT_Callback[2] = {(PIT_CallbackType)NULL}; /*!< PIT initial callback */
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+void PIT_Ch0Isr(void);
+void PIT_Ch1Isr(void);
+
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define PIT APIs
+*
+*//*! @addtogroup pit_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize pit module.
+*        
+* @param[in]   u8Channel_No channel number
+* @param[in]   pConfig point to configuration  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_Init(uint8_t u8Channel_No, PIT_ConfigType *pConfig)
+{  
+    SIM->SCGC |= SIM_SCGC_PIT_MASK;     /*!< enable clock to PIT */
+    
+    if (pConfig->bFreeze)            
+    {                                               
+        PIT_SetDebugFreeze();            
+    } 
+    
+    if (pConfig->bModuleDis == 0) 
+    {                                              
+        PIT_Enable();       /*!< enable pit module */                                                                                
+    }  
+    
+    PIT_SetLoadVal(u8Channel_No, pConfig->u32LoadValue);  
+    
+    if (pConfig->bInterruptEn)            
+    {                                   
+        if (u8Channel_No)
+        {        
+             NVIC_EnableIRQ(PIT_CH1_IRQn);             
+        }
+        else
+        {                  
+            NVIC_EnableIRQ(PIT_CH0_IRQn);
+        }
+        PIT_ChannelEnableInt(u8Channel_No);
+    }                   
+    else                                     
+    {                     
+        NVIC_DisableIRQ(PIT_CH0_IRQn);       
+    }
+
+    if (pConfig->bChainMode)            
+    {                                               
+        PIT_ChannelEnableChain(u8Channel_No);            
+    }
+    
+    if (pConfig->bETMerEn)            
+    {                                               
+        PIT_ChannelEnable(u8Channel_No);            
+    }             
+
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief initialize pit module.
+*        
+* @param[in]   u8Channel_No channel number
+* @param[in]   u32loadvalue load value for pit register  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_SetLoadVal(uint8_t u8Channel, uint32_t u32loadvalue)
+
+{
+    PIT->CHANNEL[u8Channel].LDVAL = u32loadvalue;   
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief pit module set call back.
+*        
+* @param[in] u8Channel_No channel number.   
+* @param[in] pfnCallback point to call back.   
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_SetCallback(uint8_t u8Channel_No, PIT_CallbackType pfnCallback)
+{
+  PIT_Callback[u8Channel_No] = pfnCallback;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief pit module de-initialize, reset pit register
+*        
+* @param none  
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_DeInit(void)
+{
+    NVIC_DisableIRQ(PIT_CH0_IRQn);
+    NVIC_DisableIRQ(PIT_CH1_IRQn);    
+    PIT_SetLoadVal(0,0);
+    PIT_SetLoadVal(1,0);
+    PIT_ChannelDisable(0);
+    PIT_ChannelDisable(1);
+    PIT_ChannelDisableInt(0);
+    PIT_ChannelDisableInt(1);
+    PIT_ChannelDisableChain(0);
+    PIT_ChannelDisableChain(1);    
+    PIT_ChannelClrFlags(0);
+    PIT_ChannelClrFlags(1);    
+    PIT_SetDebugOn();
+    PIT_Disable();
+    SIM->SCGC &= ~SIM_SCGC_PIT_MASK;
+}
+/*! @} End of pit_api_list                                                   */
+
+
+/*****************************************************************************//*!
+*
+* @brief pit module channel 0 isr.
+*        
+* @param none
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_Ch0Isr(void) 
+{   
+   PIT_ChannelClrFlags(0);  
+    
+    if (PIT_Callback[0])
+    {    
+        PIT_Callback[0]();     
+    }
+}
+    
+/*****************************************************************************//*!
+*
+* @brief pit module channel 1 isr.
+*        
+* @param none
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_Ch1Isr(void) 
+{   
+    PIT_ChannelClrFlags(1);
+    if (PIT_Callback[1])
+    {    
+        PIT_Callback[1]();     
+    }
+}    
+
+
diff --git a/bsp/nv32f100x/lib/src/pmc.c b/bsp/nv32f100x/lib/src/pmc.c
new file mode 100644
index 0000000000..2c6a604e83
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/pmc.c
@@ -0,0 +1,113 @@
+
+/******************************************************************************
+* @brief providing APIs for configuring PMC. 
+*
+*******************************************************************************
+*
+* provide APIs for configuring PMC
+******************************************************************************/
+#include "common.h"
+#include "pmc.h"
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+/******************************************************************************
+* Macros
+******************************************************************************/
+/******************************************************************************
+* Types
+******************************************************************************/
+/******************************************************************************
+* Global variables
+******************************************************************************/
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* PMC api list.
+*
+*//*! @addtogroup pmc_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief  configure PMC with given parameters.
+* 
+* @param[in]   pPMC_Config       PMC configuration structure.
+* @param[in]   pPMC             pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DeInit.
+*
+*****************************************************************************/
+void PMC_Init(PMC_Type *pPMC, PMC_ConfigType *pPMC_Config)
+{
+    pPMC->SPMSC1 = pPMC_Config->sCtrlstatus.byte;
+    pPMC->SPMSC2 = pPMC_Config->sDetectVoltSelect.byte;         
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  config the pmc register to the default mode.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_Init.
+*
+*****************************************************************************/
+void PMC_DeInit(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 = 0x1C;
+    pPMC->SPMSC2 = 0;         
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  config the pmc mode among run, wait and stop modes.
+* 
+* @param[in]  u8PmcMode         PMC mode select.
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void PMC_SetMode(PMC_Type *pPMC,uint8_t u8PmcMode)
+{
+    switch(u8PmcMode & 0x3) 
+    {
+        case PmcModeRun:    
+            break;
+        case PmcModeWait:
+            wait();
+            break;
+        case PmcModeStop4:
+            /* enable LVD in stop mode */
+            pPMC->SPMSC1 |= (PMC_SPMSC1_LVDE_MASK | PMC_SPMSC1_LVDSE_MASK);	
+            stop();   
+            break;
+        case PmcModeStop3: 
+            /* disable LVD in stop mode */
+            pPMC->SPMSC1 &= ~(PMC_SPMSC1_LVDE_MASK | PMC_SPMSC1_LVDRE_MASK | PMC_SPMSC1_LVDSE_MASK);	
+            stop();  
+            break;
+        default: 
+            break;
+    }
+ 
+}
+
+/*! @} End of pmc_api_list                                                    */
+
diff --git a/bsp/nv32f100x/lib/src/rtc.c b/bsp/nv32f100x/lib/src/rtc.c
new file mode 100644
index 0000000000..960fbae8a4
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/rtc.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+* @brief    Real-ETMe counter (RTC) driver source code.  
+*
+******************************************************************************/
+#include "common.h"
+#include "rtc.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+/*!
+ * @brief global variable to store RTC callbacks.
+ *
+ */
+RTC_CallbackType RTC_Callback[1] = {(RTC_CallbackType)NULL};    /*!< RTC initial callback */
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+void RTC_Isr(void);
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define RTC APIs
+*
+*//*! @addtogroup rtc_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief inital RTC module
+*        
+* @param[in] pConfig point to configuration  
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void RTC_Init(RTC_ConfigType *pConfig)
+{
+    uint16_t    u16Clocksource, u16Prescler;
+    uint16_t    u16ModVal;
+    
+    u16Clocksource =0;  
+    u16Prescler    =0;
+    u16ModVal      =0;
+
+    SIM->SCGC     |= SIM_SCGC_RTC_MASK; 
+    
+    u16ModVal      = pConfig->u16ModuloValue;
+    RTC_SetModulo(u16ModVal); 
+    
+    if (pConfig->bRTCOut)
+    {
+    
+        RTC->SC= RTC_SC_RTCO_MASK;       
+    } 
+    
+    if (pConfig->bInterruptEn)
+    {
+         NVIC_EnableIRQ(RTC_IRQn);
+         RTC_EnableInt(); 
+    }
+    else      
+    {   
+        NVIC_DisableIRQ(RTC_IRQn);
+    }
+    
+    if (pConfig->bFlag)
+    {   
+        RTC_ClrFlags();         
+    }
+
+    u16Clocksource = pConfig->bClockSource; 
+    u16Prescler    = pConfig->bClockPresaler;
+     
+    RTC_SetClock(u16Clocksource,u16Prescler );
+}
+
+
+
+/*****************************************************************************//*!
+*
+* @brief set call back function for rtc module 
+*        
+* @param[in] pfnCallback point to call back function
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void RTC_SetCallback(RTC_CallbackType pfnCallback)
+{
+  RTC_Callback[0] = pfnCallback;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief de-initialize rtc module , reset rtc register
+*        
+* @param none  
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void RTC_DeInit(void)
+{
+    NVIC_DisableIRQ(RTC_IRQn);    
+    RTC->MOD = 0;
+    while(RTC->MOD);
+    
+    if(RTC_GetFlags())
+    {
+        RTC_ClrFlags();
+    }
+    
+    RTC->SC = 0;
+    while(RTC->SC);
+    SIM->SCGC &= ~SIM_SCGC_RTC_MASK;
+}
+
+/*! @} End of rtc_api_list                                                   */
+
+/*****************************************************************************//*!
+*
+* @brief RTC module interrupt service routine
+*        
+* @param none  
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void RTC_Isr(void) 
+{
+    RTC_ClrFlags();	       
+    if (RTC_Callback[0])
+    {    
+        RTC_Callback[0]();     
+    }
+}
+
+
diff --git a/bsp/nv32f100x/lib/src/sim.c b/bsp/nv32f100x/lib/src/sim.c
new file mode 100644
index 0000000000..1273b7ee74
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/sim.c
@@ -0,0 +1,348 @@
+
+/******************************************************************************
+*
+* @brief providing APIs for system integration module (SIM). 
+*
+*******************************************************************************
+*
+* provide APIs for SIM
+******************************************************************************/
+#include "common.h"
+#include "sim.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define SIM API list
+*
+*//*! @addtogroup sim_api_list
+* @{
+*******************************************************************************/
+#if defined(CPU_NV32)
+/*****************************************************************************//*!
+   *
+   * @brief initialize SIM registers.
+   * 
+   * @param[in]  pConfig    pointer to SIM configuration.  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   * @see SIM_ConfigType
+   *****************************************************************************/
+void SIM_Init(SIM_ConfigType *pConfig)
+{
+    uint32_t    u32Sopt;
+    uint32_t    u32PinSel;
+    uint32_t    u32Scgc;
+    uint32_t    u32BusDiv;
+    /*
+     * intialize the registers to reset default values
+     */
+    u32Sopt     = 0x0010000E;                 /* enable SWD, RESET, and NMI pins */
+    u32PinSel   = 0;
+    u32Scgc     = 0x00003000;           /* enable SWD and FLASH */
+    u32BusDiv   = 0;
+    u32BusDiv = pConfig->sBits.bBusDiv;
+    if(pConfig->sBits.bDisableNMI)
+    {
+        u32Sopt &= ~SIM_SOPT_NMIE_MASK;        
+    }
+    if(pConfig->sBits.bDisableRESET)
+    {
+        u32Sopt &= ~SIM_SOPT_RSTPE_MASK;        
+    }   
+    if(pConfig->sBits.bDisableSWD)
+    {
+        u32Sopt &= ~SIM_SOPT_SWDE_MASK;        
+    } 
+    if(pConfig->sBits.bEnableCLKOUT)
+    {
+        u32Sopt |= SIM_SOPT_CLKOE_MASK;        
+    } 
+    if(pConfig->sBits.bETMSYNC)
+    {
+        u32Sopt |= SIM_SOPT_ETMSYNC_MASK;        
+    }  
+    if(pConfig->sBits.bRXDCE)
+    {
+        u32Sopt |= SIM_SOPT_RXDCE_MASK;        
+    }
+    if(pConfig->sBits.bTXDME)
+    {
+        u32Sopt |= SIM_SOPT_TXDME_MASK;        
+    }
+    if(pConfig->sBits.bACIC)
+    {
+        u32Sopt |= SIM_SOPT_ACIC_MASK;
+    }
+        if(pConfig->sBits.bRTCC)
+    {
+        u32Sopt |= SIM_SOPT_RTCC_MASK;        
+    }
+        if(pConfig->sBits.bRXDFE)
+    {
+        u32Sopt |= SIM_SOPT_RXDFE_MASK;        
+    }
+    u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);        
+    u32Sopt |= ((pConfig->u8Delay) << 24);        
+    u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x03) << 8);
+    u32PinSel = pConfig->u32PinSel;
+    u32Scgc = pConfig->u32SCGC;   
+    
+/* write SIM registers */
+    SIM->SOPT = u32Sopt;
+    SIM->PINSEL = u32PinSel;
+    SIM->SCGC = u32Scgc; 
+    SIM->BUSDIV = u32BusDiv;
+}
+#elif defined(CPU_NV32M3)
+/*****************************************************************************//*!
+   *
+   * @brief initialize SIM registers.
+   * 
+   * @param[in]  pConfig    pointer to SIM configuration.  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   * @see SIM_ConfigType
+   *****************************************************************************/
+
+void SIM_Init(SIM_ConfigType *pConfig)
+{
+    uint32_t    u32Sopt;
+    uint32_t    u32PinSel;
+    uint32_t    u32Scgc;
+    uint32_t    u32ClockDiv;
+    /*
+     * intialize the registers to reset default values
+     */
+    u32Sopt     = 0x0010000E;                 /* enable SWD, RESET, and NMI pins */
+    u32PinSel   = 0;
+    u32Scgc     = 0x00003000;           /* enable SWD and FLASH */
+    u32ClockDiv = 0;
+    u32ClockDiv = pConfig->u32CLKDIV;
+    if(pConfig->sBits.bDisableNMI)
+    {
+        u32Sopt &= ~SIM_SOPT_NMIE_MASK;        
+    }
+    if(pConfig->sBits.bDisableRESET)
+    {
+        u32Sopt &= ~SIM_SOPT_RSTPE_MASK;        
+    }   
+    if(pConfig->sBits.bDisableSWD)
+    {
+        u32Sopt &= ~SIM_SOPT_SWDE_MASK;        
+    } 
+    if(pConfig->sBits.bEnableCLKOUT)
+    {
+        u32Sopt |= SIM_SOPT_CLKOE_MASK;        
+    } 
+    if(pConfig->sBits.bETMSYNC)
+    {
+        u32Sopt |= SIM_SOPT_ETMSYNC_MASK;        
+    }  
+    if(pConfig->sBits.bRXDCE)
+    {
+        u32Sopt |= SIM_SOPT_RXDCE_MASK;        
+    }
+    if(pConfig->sBits.bTXDME)
+    {
+        u32Sopt |= SIM_SOPT_TXDME_MASK;        
+    }
+    if(pConfig->sBits.bACTRG)
+    {
+        u32Sopt |= SIM_SOPT_ACTRG_MASK;
+    }
+    u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);        
+    u32Sopt |= ((pConfig->u8Delay) << 24);        
+    u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x07) << 20);
+    u32Sopt |= ((pConfig->sBits.bRXDFE)&0x03<<8);
+    u32Sopt |= ((pConfig->sBits.bETMIC)&0x03<<6);
+
+    u32PinSel = pConfig->u32PinSel;
+    u32Scgc = pConfig->u32SCGC;    
+/* write SIM registers */
+    SIM->SOPT = u32Sopt;
+    SIM->PINSEL = u32PinSel;
+    SIM->SCGC = u32Scgc;
+    SIM->CLKDIV = u32ClockDiv;
+}
+#elif defined(CPU_NV32M4)
+/*****************************************************************************//*!
+   *
+   * @brief initialize SIM registers.
+   * 
+   * @param[in]  pConfig    pointer to SIM configuration.  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   * @see SIM_ConfigType
+   *****************************************************************************/
+void SIM_Init(SIM_ConfigType *pConfig)
+{
+    uint32_t    u32Sopt;
+    uint32_t    u32PinSel;
+    uint32_t    u32Scgc;
+    uint32_t    u32ClockDiv;
+    /*
+     * intialize the registers to reset default values
+     */
+    u32Sopt     = 0x0E;                 /* enable SWD, RESET, and NMI pins */
+    u32PinSel   = 0;
+    u32Scgc     = 0x00003000;           /* enable SWD and FLASH */
+    u32ClockDiv = 0;
+    u32ClockDiv = pConfig->u32CLKDIV;
+    if(pConfig->sBits.bDisableNMI)
+    {
+        u32Sopt &= ~SIM_SOPT0_NMIE_MASK;        
+    }
+    if(pConfig->sBits.bDisableRESET)
+    {
+        u32Sopt &= ~SIM_SOPT0_RSTPE_MASK;        
+    }   
+    if(pConfig->sBits.bDisableSWD)
+    {
+        u32Sopt &= ~SIM_SOPT0_SWDE_MASK;        
+    } 
+    if(pConfig->sBits.bEnableCLKOUT)
+    {
+        u32Sopt |= SIM_SOPT0_CLKOE_MASK;        
+    } 
+    if(pConfig->sBits.bETMSYNC)
+    {
+        u32Sopt |= SIM_SOPT0_ETMSYNC_MASK;        
+    }  
+    if(pConfig->sBits.bRXDCE)
+    {
+        u32Sopt |= SIM_SOPT0_RXDCE_MASK;        
+    }
+    if(pConfig->sBits.bTXDME)
+    {
+        u32Sopt |= SIM_SOPT0_TXDME_MASK;        
+    }
+    if(pConfig->sBits.bACTRG)
+    {
+        u32Sopt |= SIM_SOPT0_ACTRG_MASK;
+    }
+    u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);        
+    u32Sopt |= ((pConfig->u8Delay) << 24);        
+    u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x07) << 20);
+    u32Sopt |= ((pConfig->sBits.bRXDFE)&0x03<<8);
+    //u32Sopt |= ((pConfig->sBits.bETMIC)&0x03<<6);
+
+    u32PinSel = pConfig->u32PinSel;
+    u32Scgc = pConfig->u32SCGC;    
+/* write SIM registers */
+    SIM->SOPT0 = u32Sopt;
+    SIM->PINSEL = u32PinSel;
+    SIM->SCGC = u32Scgc;
+    SIM->CLKDIV = u32ClockDiv;
+}
+#endif
+
+/*****************************************************************************//*!
+   *
+   * @brief set SIM clock gating registers to enable or disable peripheral clocks.
+   * 
+   * @param[in]  u32PeripheralMask    peripherial bits mask.  
+   * @param[in]  u8GateOn             1: ON, 0: OFF.  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+void SIM_SetClockGating(uint32_t u32PeripheralMask, uint8_t u8GateOn)
+{
+    uint32_t    u32Scgc;
+
+    /*
+     * save original clock gating value
+     */
+    u32Scgc     = SIM->SCGC;
+    
+    if(u8GateOn)
+    {
+        u32Scgc |= u32PeripheralMask;
+    }
+    else
+    {
+        u32Scgc &= ~u32PeripheralMask;        
+    }
+
+    SIM->SCGC = u32Scgc;
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @brief read the corresponding status flags.
+   * 
+   * @param[in]  u32StatusMask    indicates which status to be read. 
+   *
+   * @return status.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+uint32_t SIM_GetStatus(uint32_t u32StatusMask)
+{
+    uint32_t    u32Status;
+
+    u32Status = SIM->SRSID & u32StatusMask;
+    return (u32Status);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief read the corresponding ID.
+   * 
+   * @param[in]  u8ID    type of ID. 
+   *
+   * @return ID
+   *
+   * @ Pass/ Fail criteria: none.
+   * @see   IDType.
+   *****************************************************************************/
+uint8_t SIM_ReadID(IDType sID)
+{
+    uint32_t    u32ID;
+    uint8_t u8IDOffset[4] = 
+    { 
+        28, 24, 20,16
+    };  
+    u32ID = (SIM->SRSID >> u8IDOffset[sID]) & 0x0F;
+    return (u32ID);
+}
+/*! @} End of sim_api_list                                                    */
+
+
+
diff --git a/bsp/nv32f100x/lib/src/spi.c b/bsp/nv32f100x/lib/src/spi.c
new file mode 100644
index 0000000000..a48293f3af
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/spi.c
@@ -0,0 +1,329 @@
+
+/******************************************************************************
+* @brief providing APIs for configuring SPI module (SPI). 
+*
+*******************************************************************************
+*
+* provide APIs for configuring SPI module (SPI).
+******************************************************************************/
+#include "common.h"
+#include "spi.h"
+
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+SPI_CallbackType SPI_Callback[MAX_SPI_NO] = {(SPI_CallbackType)NULL};
+
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+*****************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define SPI APIs
+*
+*//*! @addtogroup spi_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief initialize SPI as per params.
+   *        
+   * @param[in]  pSPI   point to SPI module type.
+   * @param[in]  pConfig point to configuration parameters.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void SPI_Init(SPI_Type *pSPI, SPI_ConfigType *pConfig)
+{
+#if defined(CPU_NV32M3)  
+     /* sanity check */
+    ASSERT((pSPI == SPI0));
+    SIM->SCGC |= SIM_SCGC_SPI0_MASK;
+#else
+    /* sanity check */
+    ASSERT((pSPI == SPI0) ||  (pSPI == SPI1));
+    
+    /* enable SPI clock gating on */
+    if( pSPI == SPI0)
+    {
+        SIM->SCGC |= SIM_SCGC_SPI0_MASK;
+    }
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_SPI1_MASK;     
+    }
+#endif
+    /* configure other control bits */
+    if( pConfig->sSettings.bIntEn)
+    {
+        SPI_IntEnable(pSPI);
+#if defined(CPU_NV32M3)  
+        NVIC_EnableIRQ(SPI0_IRQn);  
+#else
+        if( pSPI == SPI0 )
+        {
+			NVIC_EnableIRQ(SPI0_IRQn);
+        }
+        else
+        {
+			NVIC_EnableIRQ(SPI1_IRQn);
+        }
+#endif
+    }
+
+    if( pConfig->sSettings.bTxIntEn)
+    {
+        SPI_TxIntEnable(pSPI);
+#if defined(CPU_NV32M3)  
+        NVIC_EnableIRQ(SPI0_IRQn);  
+#else
+        if( pSPI == SPI0 )
+        {
+			NVIC_EnableIRQ(SPI0_IRQn);
+        }
+        else
+        {
+			NVIC_EnableIRQ(SPI1_IRQn);
+        }
+#endif
+    }
+    if( pConfig->sSettings.bMasterMode)
+    {
+        SPI_SetMasterMode(pSPI);
+    }
+    else
+    {
+		SPI_SetSlaveMode(pSPI);
+    }
+
+    if( pConfig->sSettings.bClkPolarityLow)
+    {
+    	SPI_SetClockPol(pSPI,1);
+    }
+    if( pConfig->sSettings.bClkPhase1)
+    {
+        SPI_SetClockPhase(pSPI,1);
+    }else
+	{	
+     SPI_SetClockPhase(pSPI,0);
+	}  
+    if( pConfig->sSettings.bShiftLSBFirst)
+    {
+        SPI_SetLSBFirst(pSPI);
+    }
+    if( pConfig->sSettings.bMatchIntEn)
+    {
+        SPI_MatchIntEnable(pSPI);
+    }
+    if( pConfig->sSettings.bModeFaultEn)
+    {
+        SPI_ModfEnable(pSPI);
+    }
+    if( pConfig->sSettings.bMasterAutoDriveSS)
+    {
+        /* set both SSOE and MODFEN bits when auto drive slave SS is enabled */
+        SPI_SSOutputEnable(pSPI);
+        SPI_ModfEnable(pSPI);
+    }    
+ 
+    if( pConfig->sSettings.bPinAsOuput)
+    {
+        SPI_BidirPinEnable(pSPI);
+    }
+
+    if( pConfig->sSettings.bBidirectionModeEn)
+    {
+        SPI_BidirOutEnable(pSPI);
+    }
+    if( pConfig->sSettings.bStopInWaitMode)
+    {
+        SPI_ClockStopEnable(pSPI);
+    }
+    
+    if(pConfig->sSettings.bMasterMode)
+    {
+        SPI_SetBaudRate(pSPI,pConfig->u32BusClkHz,pConfig->u32BitRate);
+    }
+
+	/* enable SPI module */
+    if( pConfig->sSettings.bModuleEn)
+    {
+        SPI_Enable(pSPI);
+    }
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief SPI set band rate.
+   *        
+   * @param[in]  pSPI   point to SPI module type.
+   * @param[in]  u32BusClock   Bus clock.
+   * @param[in]  u32Bps   set spi's baudrate.
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void SPI_SetBaudRate(SPI_Type *pSPI,uint32_t u32BusClock,uint32_t u32Bps)
+{
+	uint32_t u32BitRateDivisor;
+	uint8_t u8Sppr;
+	uint8_t u8Spr;
+    uint8_t u8ReadFlag;
+	u32BitRateDivisor = u32BusClock/u32Bps; /* calculate bit rate divisor */
+       
+    u8ReadFlag = 0;
+    /* find best fit SPPR and SPR */
+    for (u8Spr = 0; u8Spr <= 8; u8Spr++)
+    {
+        for(u8Sppr = 0; u8Sppr <= 7; u8Sppr++)
+        {
+            if((u32BitRateDivisor>>(u8Spr+1))<=(u8Sppr+1))
+            {
+                u8ReadFlag = 1;
+                break;
+            }
+        }
+        if(u8ReadFlag)
+        {
+            break;
+        }
+    }
+    if(u8Sppr >=8)
+    {
+        u8Sppr = 7;
+    }
+    if(u8Spr >8)
+    {
+        u8Spr = 8;
+    }
+    /* set bit rate */
+    pSPI->BR = SPI_BR_SPPR(u8Sppr) | SPI_BR_SPR(u8Spr);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief implement write data to SPI.
+   *        
+   * @param[in]   pSPI  pointer to SPI module type.
+   * @param[in]   pWrBuff -- write data buffer pointer. 
+   * @param[in]   uiLength -- read/write data length.
+   * @param[out]   pRdBuff -- read data buffer pointer. 
+   * 
+   * @return  if <0, means error, 0: success.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ResultType SPI_TransferWait(SPI_Type *pSPI, SPI_WidthType* pRdBuff, SPI_WidthType *pWrBuff,uint32 uiLength)
+{
+    ResultType err = SPI_ERR_SUCCESS;
+    uint32_t  i;
+    
+    if(!uiLength)
+    {
+        return (err);
+    }
+    for(i = 0; i < uiLength; i++)
+    {
+        while(!SPI_IsSPTEF(pSPI));
+        SPI_WriteDataReg(pSPI,pWrBuff[i]);
+        while(!SPI_IsSPRF(pSPI));
+        pRdBuff[i] = SPI_ReadDataReg(pSPI);
+    }
+    return (err);        
+}
+
+
+
+/*****************************************************************************//*!
+   *
+   * @brief Deinitialize SPI to the default state (reset value).
+   *        
+   * @param[in]   pSPI  pointer to SPI module type.
+   *         
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void SPI_DeInit(SPI_Type *pSPI)
+{  
+    int16 i;
+    pSPI->C1 = SPI_C1_DEFAULT;
+    pSPI->C2 = SPI_C2_DEFAULT;
+    pSPI->BR = SPI_BR_DEFAULT;
+    pSPI->M  = SPI_M_DEFAULT;
+    for(i = 0; i<100; i++);                 /* wait for some cycles for the ISR exit */
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief  set up SPI callback routines to be called by interrupt service routine.
+   *        
+   * @param[in]   pSPI  pointer to SPI module type.
+   * @param[in]  pfnCallback  callback routine. 
+   *  
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+void SPI_SetCallback(SPI_Type *pSPI,SPI_CallbackType pfnCallback)
+{
+    uint32_t    u32Port = ((uint32_t)pSPI-(uint32_t)SPI0)>>12;
+    ASSERT(u32Port <2);
+    SPI_Callback[u32Port] = pfnCallback;
+}
+
+/*! @} End of spi_api_list                                               						*/
+
+
+/*****************************************************************************//*!
+   *
+   * @brief SPI0 interrupt service routine.
+   *        
+   * @param   none.
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+
+void SPI0_Isr(void)
+{
+    if( SPI_Callback[0] )
+    {
+		SPI_Callback[0]();
+    }
+}
+#ifndef CPU_NV32M3
+/*****************************************************************************//*!
+   *
+   * @brief SPI1 interrupt service routine.
+   *        
+   * @param   none.
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+void SPI1_Isr(void)
+{
+    if( SPI_Callback[1] )
+    {
+		SPI_Callback[1]();
+    }
+}
+#endif
+
+
diff --git a/bsp/nv32f100x/lib/src/startup_NV32.s b/bsp/nv32f100x/lib/src/startup_NV32.s
new file mode 100644
index 0000000000..269adeedf7
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/startup_NV32.s
@@ -0,0 +1,347 @@
+;/*****************************************************************************
+; * @file:    startup_NV32.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; *           NV32F100
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+                
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp  ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler  ; NMI Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     SVC_Handler  ; SVCall Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     PendSV_Handler  ; PendSV Handler
+                DCD     SysTick_Handler  ; SysTick Handler
+
+                ; External Interrupts
+                DCD     Reserved16_IRQHandler  ; Reserved interrupt 16
+                DCD     Reserved17_IRQHandler  ; Reserved interrupt 17
+                DCD     Reserved18_IRQHandler  ; Reserved interrupt 18
+                DCD     Reserved19_IRQHandler  ; Reserved interrupt 19
+                DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
+                DCD     ETMRH_IRQHandler  ; ETMRH command complete/read collision interrupt
+                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
+                DCD     IRQ_IRQHandler  ; External interrupt
+                DCD     I2C0_IRQHandler  ; I2C0 interrupt
+                DCD     Reserved25_IRQHandler  ; Reserved interrupt 25
+                DCD     SPI0_IRQHandler  ; SPI0 interrupt
+                DCD     SPI1_IRQHandler  ; SPI1 interrupt
+                DCD     UART0_IRQHandler  ; UART0 status/error interrupt
+                DCD     UART1_IRQHandler  ; UART1 status/error interrupt
+                DCD     UART2_IRQHandler  ; UART2 status/error interrupt
+                DCD     ADC0_IRQHandler  ; ADC0 interrupt
+                DCD     ACMP0_IRQHandler  ; ACMP0 interrupt
+                DCD     ETM0_IRQHandler  ; ETM0 Single interrupt vector for all sources
+                DCD     ETM1_IRQHandler  ; ETM1 Single interrupt vector for all sources
+                DCD     ETM2_IRQHandler  ; ETM2 Single interrupt vector for all sources
+                DCD     RTC_IRQHandler  ; RTC overflow
+                DCD     ACMP1_IRQHandler  ; ACMP1 interrupt
+                DCD     PIT_CH0_IRQHandler  ; PIT CH0 overflow
+                DCD     PIT_CH1_IRQHandler  ; PIT CH1 overflow
+                DCD     KBI0_IRQHandler  ; Keyboard interrupt 0
+                DCD     KBI1_IRQHandler  ; Keyboard interrupt 1
+                DCD     Reserved42_IRQHandler  ; Reserved interrupt 42
+                DCD     ICS_IRQHandler  ; MCG interrupt
+                DCD     Watchdog_IRQHandler  ; WDOG Interrupt
+                DCD     Reserved45_IRQHandler  ; Reserved interrupt 45
+                DCD     Reserved46_IRQHandler  ; Reserved interrupt 46
+                DCD     Reserved47_IRQHandler  ; Reserved interrupt 47
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
+;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
+;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
+;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
+;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
+;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
+;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
+;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> EEPROM Protection Register (EEPROT)
+;     <i> The DFPROT register defines which D-Flash sectors are protected against program and erase operations.
+;     <o.7>  DPOPEN
+;       <0=> Enables EEPROM memory protection
+;       <1=> Disables EEPROM memory protection
+;     <o.0..2> DPS
+;       <0=> Flash address range: 0x00_0000 - 0x00_001F; protected size: 32 bytes
+;       <1=> Flash address range: 0x00_0000 - 0x00_003F; protected size: 64 bytes
+;       <2=> Flash address range: 0x00_0000 - 0x00_005F; protected size: 96 bytes
+;       <3=> Flash address range: 0x00_0000 - 0x00_007F; protected size: 128 bytes
+;       <4=> Flash address range: 0x00_0000 - 0x00_009F; protected size: 160 bytes
+;       <5=> Flash address range: 0x00_0000 - 0x00_00BF; protected size: 192 bytes
+;       <6=> Flash address range: 0x00_0000 - 0x00_00DF; protected size: 224 bytes
+;       <7=> Flash address range: 0x00_0000 - 0x00_00FF; protected size: 256 bytes
+EEPROT          EQU     0xFF
+;     </h>
+;     <h> FPROT
+;       <i> P-Flash Protection Register
+;       <o.7> FPOPEN
+;         <0=> FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits FPROT1.1
+;         <1=> FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits
+;       <o.5> FPHDIS
+;         <0=> Protection/Unprotection enabled
+;         <1=> Protection/Unprotection disabled
+;       <o.3..4> FPHS
+;         <0=> Address range: 0x00_7C00-0x00_7FFF; protected size: 1 KB
+;         <1=> Address range: 0x00_7800-0x00_7FFF; protected size: 2 KB
+;         <2=> Address range: 0x00_7000-0x00_7FFF; protected size: 4 KB
+;         <3=> Address range: 0x00_6000-0x00_7FFF; protected size: 8 KB
+;       <o.5> FPLDIS
+;         <0=> Protection/Unprotection enabled
+;         <1=> Protection/Unprotection disabled
+;       <o.3..4> FPLS
+;         <0=> Address range: 0x00_0000-0x00_07FF; protected size: 2 KB
+;         <1=> Address range: 0x00_0000-0x00_0FFF; protected size: 4 KB
+;         <2=> Address range: 0x00_0000-0x00_1FFF; protected size: 8 KB
+;         <3=> Address range: 0x00_0000-0x00_3FFF; protected size: 16 KB
+FPROT         EQU     0xFF
+;     </h>
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;         <i> This bits define the security state of the MCU.
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor key Security Enable
+;         <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC            EQU     0xFE
+;   </h>
+;   <h> Flash Option Register (FOPT)
+FOPT            EQU     0xFE
+;   </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    |.ARM.__at_0x400|, CODE, READONLY
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     0xFF,       0xFF,       0xFF,       0xFF
+                DCB     EEPROT,      FPROT,     FSEC,       FOPT              ;Modified by ARM.  DCB     FPROT,      EEPROT,     FOPT,       FSEC
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  Reserved16_IRQHandler     [WEAK]
+                EXPORT  Reserved17_IRQHandler     [WEAK]
+                EXPORT  Reserved18_IRQHandler     [WEAK]
+                EXPORT  Reserved19_IRQHandler     [WEAK]
+                EXPORT  Reserved20_IRQHandler     [WEAK]
+                EXPORT  ETMRH_IRQHandler     [WEAK]
+                EXPORT  LVD_LVW_IRQHandler     [WEAK]
+                EXPORT  IRQ_IRQHandler     [WEAK]
+                EXPORT  I2C0_IRQHandler     [WEAK]
+                EXPORT  Reserved25_IRQHandler     [WEAK]
+                EXPORT  SPI0_IRQHandler     [WEAK]
+                EXPORT  SPI1_IRQHandler     [WEAK]
+                EXPORT  UART0_IRQHandler     [WEAK]
+                EXPORT  UART1_IRQHandler     [WEAK]
+                EXPORT  UART2_IRQHandler     [WEAK]
+                EXPORT  ADC0_IRQHandler     [WEAK]
+                EXPORT  ACMP0_IRQHandler     [WEAK]
+                EXPORT  ETM0_IRQHandler     [WEAK]
+                EXPORT  ETM1_IRQHandler     [WEAK]
+                EXPORT  ETM2_IRQHandler     [WEAK]
+                EXPORT  RTC_IRQHandler     [WEAK]
+                EXPORT  ACMP1_IRQHandler     [WEAK]
+                EXPORT  PIT_CH0_IRQHandler     [WEAK]
+                EXPORT  PIT_CH1_IRQHandler     [WEAK]
+                EXPORT  KBI0_IRQHandler     [WEAK]
+                EXPORT  KBI1_IRQHandler     [WEAK]
+                EXPORT  Reserved42_IRQHandler     [WEAK]
+                EXPORT  ICS_IRQHandler     [WEAK]
+                EXPORT  Watchdog_IRQHandler     [WEAK]
+                EXPORT  Reserved45_IRQHandler     [WEAK]
+                EXPORT  Reserved46_IRQHandler     [WEAK]
+                EXPORT  Reserved47_IRQHandler     [WEAK]
+                EXPORT  DefaultISR                      [WEAK]
+
+Reserved16_IRQHandler
+Reserved17_IRQHandler
+Reserved18_IRQHandler
+Reserved19_IRQHandler
+Reserved20_IRQHandler
+ETMRH_IRQHandler
+LVD_LVW_IRQHandler
+IRQ_IRQHandler
+I2C0_IRQHandler
+Reserved25_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+ACMP0_IRQHandler
+ETM0_IRQHandler
+ETM1_IRQHandler
+ETM2_IRQHandler
+RTC_IRQHandler
+ACMP1_IRQHandler
+PIT_CH0_IRQHandler
+PIT_CH1_IRQHandler
+KBI0_IRQHandler
+KBI1_IRQHandler
+Reserved42_IRQHandler
+ICS_IRQHandler
+Watchdog_IRQHandler
+Reserved45_IRQHandler
+Reserved46_IRQHandler
+Reserved47_IRQHandler
+DefaultISR
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/bsp/nv32f100x/lib/src/uart.c b/bsp/nv32f100x/lib/src/uart.c
new file mode 100644
index 0000000000..0159628ea0
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/uart.c
@@ -0,0 +1,459 @@
+/******************************************************************************
+* @brief providing common UART API. 
+*
+******************************************************************************/
+#include "uart.h"
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+UART_CallbackType UART_Callback = NULL;
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+*****************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define UART APIs
+*
+*//*! @addtogroup uart_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize the UART, interrupts disabled, and no hardware flow-control.
+*        
+* @param[in] pUART       base of UART port
+* @param[in] pConfig     pointer to UART configuration structure
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void UART_Init(UART_Type *pUART, UART_ConfigType *pConfig)
+{
+    uint16_t u16Sbr;
+    uint8_t u8Temp;
+    uint32_t u32SysClk = pConfig->u32SysClkHz;
+    uint32_t u32Baud = pConfig->u32Baudrate;
+
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+  
+	/* Enable the clock to the selected UART */    
+    if (pUART == UART0)
+	{
+		SIM->SCGC |= SIM_SCGC_UART0_MASK;
+	}
+#if defined(CPU_NV32)  | defined(CPU_NV326)
+	else if (pUART == UART1)
+	{
+        SIM->SCGC |= SIM_SCGC_UART1_MASK;
+	}
+    else
+	{
+        SIM->SCGC |= SIM_SCGC_UART2_MASK;
+	}
+#endif    
+    /* Make sure that the transmitter and receiver are disabled while we 
+     * change settings.
+     */
+    pUART->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
+    
+    /* Configure the UART for 8-bit mode, no parity */
+    pUART->C1 = 0;
+    
+    /* Calculate baud settings */
+    u16Sbr = (((u32SysClk)>>4) + (u32Baud>>1))/u32Baud;
+    
+    /* Save off the current value of the UARTx_BDH except for the SBR field */
+    u8Temp = pUART->BDH & ~(UART_BDH_SBR_MASK);
+    
+    pUART->BDH = u8Temp |  UART_BDH_SBR(u16Sbr >> 8);
+    pUART->BDL = (uint8_t)(u16Sbr & UART_BDL_SBR_MASK);
+
+    /* Enable receiver and transmitter */
+    pUART->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
+}
+
+/*****************************************************************************//*!
+*
+* @brief receive a character.
+*        
+* @param[in] pUART       base of UART port
+*
+* @return unsigned char
+*
+*****************************************************************************/
+uint8_t UART_GetChar(UART_Type *pUART)
+{
+
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+ 
+    /* Wait until character has been received */
+    while (!(pUART->S1 & UART_S1_RDRF_MASK));
+    
+    /* Return the 8-bit data from the receiver */
+    return pUART->D;
+}
+/*****************************************************************************//*!
+*
+* @brief send a character.
+*        
+* @param[in] pUART       base of UART port
+* @param[in] u8Char      char to send
+*
+* @return none
+*
+*****************************************************************************/
+void UART_PutChar(UART_Type *pUART, uint8_t u8Char)
+{    
+    /* Wait until space is available in the FIFO */
+    while (!(pUART->S1 & UART_S1_TDRE_MASK));
+    
+    /* Send the character */
+    pUART->D = (uint8_t)u8Char;
+}
+
+/*****************************************************************************//*!
+*
+* @brief set baudrate.
+*        
+* @param[in] pUART       base of UART port
+* @param[in] pConfig     baudrate config parameters
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_SetBaudrate(UART_Type *pUART, UART_ConfigBaudrateType *pConfig)
+{
+    uint8_t u8Temp;
+    uint16_t u16Sbr;
+    uint32_t u32SysClk    = pConfig->u32SysClkHz;
+    uint32_t u32baud       = pConfig->u32Baudrate;
+ 
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+
+    /* Calculate baud settings */
+    u16Sbr = (((u32SysClk)>>4) + (u32baud>>1))/u32baud;
+
+    /* Save off the current value of the UARTx_BDH except for the SBR field */
+    u8Temp = pUART->BDH & ~(UART_BDH_SBR_MASK);
+    
+    pUART->BDH = u8Temp |  UART_BDH_SBR(u16Sbr >> 8);
+    pUART->BDL = (uint8_t)(u16Sbr & UART_BDL_SBR_MASK);
+
+    /* Enable receiver and transmitter */
+    pUART->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
+
+}
+
+/*****************************************************************************//*!
+*
+* @brief enable interrupt.
+*        
+* @param[in] pUART          base of UART port
+* @param[in] InterruptType  interrupt type
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_EnableInterrupt(UART_Type *pUART, UART_InterruptType InterruptType)
+{
+
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+
+    if (InterruptType == UART_TxBuffEmptyInt)
+    {
+        pUART->C2 |= UART_C2_TIE_MASK;
+    }
+    else if (InterruptType == UART_TxCompleteInt)
+    {
+        pUART->C2 |= UART_C2_TCIE_MASK;
+    }
+    else if (InterruptType == UART_RxBuffFullInt)
+    {
+        pUART->C2 |= UART_C2_RIE_MASK;
+    }
+    else if (InterruptType == UART_IdleLineInt)
+    {
+        pUART->C2 |= UART_C2_ILIE_MASK;
+    }
+    else if (InterruptType == UART_RxOverrunInt)
+    {
+        pUART->C3 |= UART_C3_ORIE_MASK;
+    }
+    else if (InterruptType == UART_NoiseErrorInt)
+    {
+        pUART->C3 |= UART_C3_NEIE_MASK;
+    }
+    else if (InterruptType == UART_FramingErrorInt)
+    {
+        pUART->C3 |= UART_C3_FEIE_MASK;
+    } 
+    else if (InterruptType == UART_ParityErrorInt)
+    {
+        pUART->C3 |= UART_C3_FEIE_MASK;
+    } 
+    else
+    {
+        /* un-supported Interrupt type */
+    }  
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable interrupt.
+*        
+* @param[in] pUART base of UART port
+* @param[in] InterruptType interrupt type
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_DisableInterrupt(UART_Type *pUART, UART_InterruptType InterruptType)
+{
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+
+
+    if (InterruptType == UART_TxBuffEmptyInt)
+    {
+        pUART->C2 &= (~UART_C2_TIE_MASK);
+    }
+    else if (InterruptType == UART_TxCompleteInt)
+    {
+        pUART->C2 &= (~UART_C2_TCIE_MASK);
+    }
+    else if (InterruptType == UART_RxBuffFullInt)
+    {
+        pUART->C2 &= (~UART_C2_RIE_MASK);
+    }
+    else if (InterruptType == UART_IdleLineInt)
+    {
+        pUART->C2 &= (~UART_C2_ILIE_MASK);
+    }
+    else if (InterruptType == UART_RxOverrunInt)
+    {
+        pUART->C3 &= (~UART_C3_ORIE_MASK);
+    }
+    else if (InterruptType == UART_NoiseErrorInt)
+    {
+        pUART->C3 &= (~UART_C3_NEIE_MASK);
+    }
+    else if (InterruptType == UART_FramingErrorInt)
+    {
+        pUART->C3 &= (~UART_C3_FEIE_MASK);
+    } 
+    else if (InterruptType == UART_ParityErrorInt)
+    {
+        pUART->C3 &= (~UART_C3_FEIE_MASK);
+    } 
+    else
+    {
+        /* un-supported interrupt type */
+    }  
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief get flags from 2 UART status registers.
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       16-bit flags
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+uint16_t UART_GetFlags(UART_Type *pUART)
+{
+    uint16_t u16StatusFlags = 0;
+
+    u16StatusFlags = pUART->S2;
+    u16StatusFlags = (u16StatusFlags<<8)| pUART->S1; 
+
+    return u16StatusFlags;
+}
+/*****************************************************************************//*!
+*
+* @brief check whether the specified flag is set.
+*        
+* @param[in] pUART      base of UART port
+* @param[in] FlagType   flag type
+*
+* @return       
+*               1, flag is set
+*               0, flag is clear
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t UART_CheckFlag(UART_Type *pUART, UART_FlagType FlagType)
+{
+    uint16_t u16StatusFlags = 0;
+
+    u16StatusFlags = UART_GetFlags(pUART);
+
+    return (u16StatusFlags & (1<<FlagType));
+}
+
+/*****************************************************************************//*!
+*
+* @brief send a series of charecters using polling mode.
+*        
+* @param[in] pUART      base of UART port
+* @param[in] pSendBuff  pointer of charecters to send
+* @param[in] u32Length  number of charecters
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_SendWait(UART_Type *pUART, uint8_t *pSendBuff, uint32_t u32Length)
+{
+    uint8_t u8TxChar;
+    uint32_t  i;
+    
+    for (i = 0; i < u32Length; i++)
+    {
+        u8TxChar = pSendBuff[i];
+        while (!UART_IsTxBuffEmpty(pUART))
+        {
+            #if defined(ENABLE_WDOG)
+                WDOG_Feed();
+            #endif        
+        }
+        UART_WriteDataReg(pUART, u8TxChar);        
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief receive a series of charecters using polling mode.
+*        
+* @param[in] pUART          base of UART port
+* @param[in] pReceiveBuff   pointer of charecters to receive
+* @param[in] u32Length      number of charecters
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_ReceiveWait(UART_Type *pUART, uint8_t *pReceiveBuff, uint32_t u32Length)
+{
+    uint8_t u8RxChar;
+    uint32_t i;
+    
+    for (i = 0; i < u32Length; i++)
+    {
+        while (!UART_IsRxBuffFull(pUART))
+        {
+            #if defined(ENABLE_WDOG)
+                WDOG_Feed();
+            #endif       
+        }    
+        u8RxChar = UART_ReadDataReg(pUART);
+        pReceiveBuff[i] = u8RxChar;
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief wait tx complete.
+*        
+* @param[in] pUART      base of UART port
+*
+* @return       none
+*
+* @ Pass/ Fail criteria: none*****************************************************************************/
+void UART_WaitTxComplete(UART_Type *pUART)
+{
+    while (!UART_IsTxComplete(pUART));
+}
+
+/*****************************************************************************//*!
+*
+* @brief set up UART callback routines to be called by interrupt service routine.
+*        
+* @param[in]  pUART         pointer to an UART register base 
+* @param[in]  pfnCallback   callback routine
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void UART_SetCallback(UART_CallbackType pfnCallback)
+{
+    //uint8_t    u8Port = ((uint32_t)pUART-(uint32_t)UART0)>>12;
+    UART_Callback = pfnCallback;
+}
+
+
+/*! @} End of uart_api_list */
+
+
+/*****************************************************************************//*!
+*
+* @brief uart0 interrupt service routine.
+*        
+* @param        none
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART0_Isr(void)
+{
+    UART_Callback(UART0);
+}
+
+
+#if defined(CPU_NV32) | defined(CPU_NV326)
+/*****************************************************************************//*!
+*
+* @brief uart1 interrupt service routine.
+*        
+* @param        none
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART1_Isr(void)
+{
+    UART_Callback(UART1);
+}
+/*****************************************************************************//*!
+*
+* @brief uart2 interrupt service routine.
+*        
+* @param        none
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART2_Isr(void)
+{
+    UART_Callback(UART2);
+}
+
+
+#endif
+
+
+
diff --git a/bsp/nv32f100x/lib/src/wdog.c b/bsp/nv32f100x/lib/src/wdog.c
new file mode 100644
index 0000000000..bf17e65037
--- /dev/null
+++ b/bsp/nv32f100x/lib/src/wdog.c
@@ -0,0 +1,324 @@
+
+/******************************************************************************
+*
+* @brief Provide common watchdog module routines. 
+*
+* @history:
+* 	Jun. 25, 2013	modified the watch dog unlock sequence and disable sequence
+******************************************************************************/
+#include "common.h"
+#include "wdog.h"
+ 
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define watchdog API list
+*
+*//*! @addtogroup wdog_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief Watchdog ETMer disable routine.
+*        
+* @param  none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see WDOG_Enable
+*****************************************************************************/
+
+void WDOG_Disable(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;  
+    uint8_t u8Cs2 =  WDOG->CS2;  
+    uint16_t u16TOVAL =  WDOG->TOVAL;  
+    uint16_t u16WIN =  WDOG->WIN;  
+
+    u8Cs1       &= ~WDOG_CS1_EN_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    WDOG_Unlock(); 
+    WDOG->CS2    =  u8Cs2;
+    WDOG->TOVAL  =  u16TOVAL;
+    WDOG->WIN    =  u16WIN;
+    WDOG->CS1    =  u8Cs1;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief Watchdog ETMer disable routine with update enabled.
+*        
+*   Disable watchdog but the watchdog can be enabled and updated later.
+*
+* @param  none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see WDOG_Enable
+*****************************************************************************/
+
+void WDOG_DisableWDOGEnableUpdate(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;  
+    uint8_t u8Cs2 =  WDOG->CS2;  
+    uint16_t u16TOVAL =  WDOG->TOVAL;  
+    uint16_t u16WIN =  WDOG->WIN;  
+
+    u8Cs1       &= ~WDOG_CS1_EN_MASK;
+    u8Cs1       |= WDOG_CS1_UPDATE_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    //WDOG_Unlock(); 
+    WDOG->CS2    =  u8Cs2;
+    WDOG->TOVAL  =  u16TOVAL;
+    WDOG->WIN    =  u16WIN;
+    WDOG->CS1    =  u8Cs1;
+}
+
+/*****************************************************************************//*!
+*
+* @brief Watchdog ETMer enable routine.
+*        
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  WDOG_Disable
+*****************************************************************************/
+
+void WDOG_Enable(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;
+    
+    u8Cs1       |= WDOG_CS1_EN_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    WDOG_Unlock();
+    WDOG->CS1    = u8Cs1;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief initialize watchdog.
+*        
+* @param[in]   pConfig  poiner to watchdog configuration strcture.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* 
+* @warning make sure that WDOG is not initialized after reset or WDOG update is enabled 
+* after reset by calling WDOG_EnableUpdate / WDOG_DisableWDOGEnableUpdate.
+*
+* @see WDOG_EnableUpdate, WDOG_DisableWDOGEnableUpdate
+*
+*****************************************************************************/
+
+void WDOG_Init(WDOG_ConfigPtr pConfig)
+{
+    uint8_t     u8Cs1;
+    uint8_t     u8Cs2;
+    uint16_t    u16Toval;
+    uint16_t    u16Win;
+    
+    u8Cs1       = 0x80;                                   /* default CS1 register value */
+    u8Cs2       = 0;
+    u16Toval    = pConfig->u16ETMeOut;
+    u16Win      = pConfig->u16WinETMe;
+        
+    if(pConfig->sBits.bDisable)
+    {
+        u8Cs1 &= ~WDOG_CS1_EN_MASK;
+    }
+    if(pConfig->sBits.bIntEnable)
+    {
+        u8Cs1 |= WDOG_CS1_INT_MASK;
+    }
+    if(pConfig->sBits.bStopEnable)
+    {
+        u8Cs1 |= WDOG_CS1_STOP_MASK;
+    }
+    if(pConfig->sBits.bDbgEnable)
+    {
+        u8Cs1 |= WDOG_CS1_DBG_MASK;
+    }
+    if(pConfig->sBits.bWaitEnable)
+    {
+        u8Cs1 |= WDOG_CS1_WAIT_MASK;
+    }
+    if(pConfig->sBits.bUpdateEnable)
+    {
+        u8Cs1 |= WDOG_CS1_UPDATE_MASK;
+    }
+    if(pConfig->sBits.bWinEnable)
+    {
+        u8Cs2 |= WDOG_CS2_WIN_MASK;
+    }
+    if(pConfig->sBits.bPrescaler)
+    {
+        u8Cs2 |= WDOG_CS2_PRES_MASK;
+    }
+    u8Cs2   |= (pConfig->sBits.bClkSrc & 0x03);
+    
+    /* write regisers */
+    WDOG_Unlock();              /* unlock watchdog first */
+    WDOG->CS2   = u8Cs2;
+
+    WDOG->TOVAL8B.TOVALL  = u16Toval;
+    WDOG->TOVAL8B.TOVALH  = u16Toval >> 8;
+    
+    WDOG->WIN8B.WINL  = u16Win;
+    WDOG->WIN8B.WINH  = u16Win >> 8;
+    
+    WDOG->CS1   = u8Cs1;                            
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief initialize watchdog to the default state.
+*        
+* @param   none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @warning make sure that WDOG update is enabled after reset by calling WDOG_EnableUpdate.
+* or by calling WDOG_DisableWDOGEnableUpdate.
+*
+* @see WDOG_DisableWDOGEnableUpdate, WDOG_EnableUpdate
+*
+*****************************************************************************/
+
+void WDOG_DeInit(void)
+{
+    WDOG_Unlock();
+    
+    WDOG->CS2    =  WDOG_CS2_DEFAULT_VALUE;
+    WDOG->TOVAL  =  WDOG_TOVAL_DEFAULT_VALUE;
+    WDOG->WIN    =  WDOG_WIN_DEFAULT_VALUE;    
+    WDOG->CS1    =  WDOG_CS1_DEFAULT_VALUE;
+}
+
+/*****************************************************************************//*!
+*
+* @brief feed/refresh watchdog.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+void WDOG_Feed(void)
+{
+    DisableInterrupts;
+    WDOG->CNT = 0x02A6;
+    WDOG->CNT = 0x80B4;
+    EnableInterrupts;
+}
+
+
+
+/*****************************************************************************//*!
+*
+* @brief enable update of WDOG. 
+*        
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @warning  this must be the last step of writing control bits sequence.
+*****************************************************************************/
+
+void WDOG_EnableUpdate(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;  
+    uint8_t u8Cs2 =  WDOG->CS2;  
+    uint16_t u16TOVAL =  WDOG->TOVAL;  
+    uint16_t u16WIN =  WDOG->WIN;  
+
+    u8Cs1 |= WDOG_CS1_UPDATE_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    WDOG_Unlock(); 
+    WDOG->CS2    =  u8Cs2;
+    WDOG->TOVAL  =  u16TOVAL;
+    WDOG->WIN    =  u16WIN;
+    WDOG->CS1    =  u8Cs1;  
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable update of WDOG. 
+*        
+* @param  none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @warning  this must be the last step of writing control bits sequence.
+*****************************************************************************/
+
+void WDOG_DisableUpdate(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;  
+    uint8_t u8Cs2 =  WDOG->CS2;  
+    uint16_t u16TOVAL =  WDOG->TOVAL;  
+    uint16_t u16WIN =  WDOG->WIN;  
+
+    u8Cs1 &= ~WDOG_CS1_UPDATE_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    WDOG_Unlock(); 
+    WDOG->CS2    =  u8Cs2;
+    WDOG->TOVAL  =  u16TOVAL;
+    WDOG->WIN    =  u16WIN;
+    WDOG->CS1    =  u8Cs1;  
+    
+}
+
+
+/********************************************************************/
+
+/*! @} End of wdog_api_list                                                    					*/
+
+
+
+
diff --git a/bsp/nv32f100x/project.uvprojx b/bsp/nv32f100x/project.uvprojx
new file mode 100644
index 0000000000..96d97f3ba2
--- /dev/null
+++ b/bsp/nv32f100x/project.uvprojx
@@ -0,0 +1,711 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>nv32f100x</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060183::V5.06 update 2 (build 183)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>NV32F100FS16E</Device>
+          <Vendor>Navota MCU</Vendor>
+          <PackID>Keil.NV32F100_DFP.1.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x1FFFF800,0x2000) IROM(0x00000000,0x20000) IROM2(0x00400000,0x1400) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFFF800 -FC2000 -FN2 -FF0nv32f100_128 -FS00 -FL020000 -FF1nv32f100_nvr -FS1400000 -FL11400 -FP0($$Device:NV32F100FS16E$Flash\nv32f100_128.FLM) -FP1($$Device:NV32F100FS16E$Flash\nv32f100_nvr.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:NV32F100FS16E$Device\Include\nv32f100.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:NV32F100FS16E$SVD\nv32f100S16.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\output\</OutputDirectory>
+          <OutputName>nv32f100x</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>C:\Users\HF00\Documents\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>1</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>0</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4103</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1ffff800</StartAddress>
+                <Size>0x2000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x400000</StartAddress>
+                <Size>0x1400</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1ffff800</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>1</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NV32, KEIL</Define>
+              <Undefine></Undefine>
+              <IncludePath>app\inc;.;board\inc;lib\inc;..\..\include;..\..\libcpu\arm\cortex-m0;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>0</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc> --keep *.o(.rti_fn.*)   --keep *.o(FSymTab)</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\app\src\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>ledapp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>app\src\ledapp.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\drv_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\drv_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>start.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\start.c</FilePath>
+            </File>
+            <File>
+              <FileName>sysinit.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\sysinit.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Lib</GroupName>
+          <Files>
+            <File>
+              <FileName>acmp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\acmp.c</FilePath>
+            </File>
+            <File>
+              <FileName>adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cm0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\arm_cm0.c</FilePath>
+            </File>
+            <File>
+              <FileName>crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>eeprom.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\eeprom.c</FilePath>
+            </File>
+            <File>
+              <FileName>etm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\etm.c</FilePath>
+            </File>
+            <File>
+              <FileName>flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>ics.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\ics.c</FilePath>
+            </File>
+            <File>
+              <FileName>kbi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\kbi.c</FilePath>
+            </File>
+            <File>
+              <FileName>pit.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\pit.c</FilePath>
+            </File>
+            <File>
+              <FileName>pmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\pmc.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>sim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\sim.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>wdog.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\wdog.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_NV32.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>lib\src\startup_NV32.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORTEX-M0</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\spi\spi_core.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_dev.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\spi\spi_dev.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>portal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\portal.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\symbol.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh_cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_file.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh_file.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/nv32f100x/rtconfig.h b/bsp/nv32f100x/rtconfig.h
new file mode 100644
index 0000000000..0279e205ae
--- /dev/null
+++ b/bsp/nv32f100x/rtconfig.h
@@ -0,0 +1,101 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	   8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	1000
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+//#define RT_DEBUG
+//#define RT_DEBUG_INIT 1
+//#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+/* #define RT_USING_HOOK */
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+/* #define RT_USING_MAILBOX */
+
+/* Using Message Queue */
+/* #define RT_USING_MESSAGEQUEUE */
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+/* #define RT_USING_MEMPOOL */
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+#define RT_USING_TINY_SIZE
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
+#define RT_USING_SERIAL
+#define RT_USING_HOOK
+#define RT_USING_CPU_USAGE
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+#define RT_USING_RTTTERMINAL
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	    "uart0"
+
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+#define RT_FINSHPROMRT_SIZE 16
+/* configure finsh parameters */
+#define FINSH_THREAD_PRIORITY 25
+#define FINSH_THREAD_STACK_SIZE	512
+#define FINSH_HISTORY_LINES	1
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+//#define FINSH_USING_DESCRIPTION
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_ONLY
+
+#define RT_USING_PIN
+#define RT_USING_SPI
+#define RT_DBG_APP
+
+#define RT_USING_UART0
+
+#define RT_USING_USER_MAIN
+
+#endif
diff --git a/bsp/nv32f100x/rtconfig.py b/bsp/nv32f100x/rtconfig.py
new file mode 100644
index 0000000000..6927eee3ab
--- /dev/null
+++ b/bsp/nv32f100x/rtconfig.py
@@ -0,0 +1,126 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM 	= 'gcc'
+    EXEC_PATH 	= 'G:/iot/camera_studio-win32-20160903/camera_studio/tools/arm-2014.05/bin'
+elif CROSS_TOOL == 'keil':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+#BUILD = 'debug'
+BUILD = 'release'
+NV32_TYPE = 'NV32F100X'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE  + ' -DNV32F100X' + ' -DNULL=0'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-nv32.map,-cref,-u,Reset_Handler -T nv32_rom.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-nv32.map --scatter nv32_rom.sct'
+
+    CFLAGS += ' -I./'
+
+    EXEC_PATH += '/ARM/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --debug'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M0'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' -Ol'
+    CFLAGS += ' --use_c++_inline'
+
+    AFLAGS = ''
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M0'
+    AFLAGS += ' --fpu None'
+
+    LFLAGS = ' --config nv32f100x_flash.icf'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny'
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+    LFLAGS += ' --entry __iar_program_start'
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = ''
diff --git a/bsp/nv32f100x/template.uvprojx b/bsp/nv32f100x/template.uvprojx
new file mode 100644
index 0000000000..bab53d35cc
--- /dev/null
+++ b/bsp/nv32f100x/template.uvprojx
@@ -0,0 +1,379 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>nv32f100x</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060183::V5.06 update 2 (build 183)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>NV32F100FS16E</Device>
+          <Vendor>Navota MCU</Vendor>
+          <PackID>Keil.NV32F100_DFP.1.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x1FFFF800,0x2000) IROM(0x00000000,0x20000) IROM2(0x00400000,0x1400) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFFF800 -FC2000 -FN2 -FF0nv32f100_128 -FS00 -FL020000 -FF1nv32f100_nvr -FS1400000 -FL11400 -FP0($$Device:NV32F100FS16E$Flash\nv32f100_128.FLM) -FP1($$Device:NV32F100FS16E$Flash\nv32f100_nvr.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:NV32F100FS16E$Device\Include\nv32f100.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:NV32F100FS16E$SVD\nv32f100S16.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\output\</OutputDirectory>
+          <OutputName>nv32f100x</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>C:\Users\HF00\Documents\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>1</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>0</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4103</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1ffff800</StartAddress>
+                <Size>0x2000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x400000</StartAddress>
+                <Size>0x1400</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1ffff800</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>1</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>0</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--keep *.o(.rti_fn.*)   --keep *.o(FSymTab)</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/qemu-vexpress-a9/.config b/bsp/qemu-vexpress-a9/.config
new file mode 100644
index 0000000000..263636ee81
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/.config
@@ -0,0 +1,159 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+CONFIG_RT_ALIGN_SIZE=4
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_DEBUG=y
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+# CONFIG_RT_DEBUG_INIT is not set
+# CONFIG_RT_DEBUG_THREAD is not set
+CONFIG_RT_USING_HOOK=y
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_USING_HEAP=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_DEFAULT_PASSWORD="rtthread"
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FD_MAX=4
+CONFIG_RT_USING_DFS_ELMFAT=y
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_MAX_LFN=256
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_NET is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# libc
+#
+CONFIG_RT_USING_LIBC=y
+CONFIG_RT_USING_PTHREADS=y
+
+#
+# Network stack
+#
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+
+#
+# language packages
+#
+
+#
+# miscellaneous packages
+#
+CONFIG_PKG_USING_HELLO=y
+CONFIG_PKG_HELLO_PATH="/packages/misc/hello"
+CONFIG_PKG_HELLO_VER="v1.0.0"
+
+#
+# multimedia packages
+#
+
+#
+# security packages
+#
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+CONFIG_RT_USING_UART0=y
+CONFIG_RT_USING_UART1=y
diff --git a/bsp/qemu-vexpress-a9/Kconfig b/bsp/qemu-vexpress-a9/Kconfig
new file mode 100644
index 0000000000..2e1b008775
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/Kconfig
@@ -0,0 +1,20 @@
+mainmenu "RT-Thread Project Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/KConfig"
+source "$PKGS_DIR/KConfig"
+source "$BSP_DIR/drivers/Kconfig"
diff --git a/bsp/qemu-vexpress-a9/README.md b/bsp/qemu-vexpress-a9/README.md
new file mode 100644
index 0000000000..9eb71f3bf2
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/README.md
@@ -0,0 +1,3 @@
+RT-Thread for QEMU/vexpress-a9
+
+The shell of RT-Thread is on serial0. 
diff --git a/bsp/qemu-vexpress-a9/SConscript b/bsp/qemu-vexpress-a9/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/qemu-vexpress-a9/SConstruct b/bsp/qemu-vexpress-a9/SConstruct
new file mode 100644
index 0000000000..61af0ee620
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/SConstruct
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS   = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC   = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX  = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR   = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/qemu-vexpress-a9/applications/SConscript b/bsp/qemu-vexpress-a9/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/qemu-vexpress-a9/applications/main.c b/bsp/qemu-vexpress-a9/applications/main.c
new file mode 100644
index 0000000000..d59513bce8
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/applications/main.c
@@ -0,0 +1,11 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(void)
+{
+    printf("hello rt-thread\n");
+
+    return 0;
+}
+
diff --git a/bsp/qemu-vexpress-a9/cpu/SConscript b/bsp/qemu-vexpress-a9/cpu/SConscript
new file mode 100644
index 0000000000..b45f95cc1a
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/SConscript
@@ -0,0 +1,17 @@
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'iar':
+        src += Glob('*_iar.S')
+elif rtconfig.PLATFORM == 'gcc':
+        src += Glob('*_gcc.S')
+elif rtconfig.PLATFORM == 'armcc':
+        src += Glob('*_rvds.S')
+
+group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/qemu-vexpress-a9/cpu/armv7.h b/bsp/qemu-vexpress-a9/cpu/armv7.h
new file mode 100644
index 0000000000..69c556eb3c
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/armv7.h
@@ -0,0 +1,64 @@
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long sp;
+	unsigned long lr;
+	unsigned long pc;
+	unsigned long cpsr;
+};
+
+struct rt_hw_stack
+{
+	unsigned long cpsr;
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long lr;
+	unsigned long pc;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+#endif
diff --git a/bsp/qemu-vexpress-a9/cpu/context_gcc.S b/bsp/qemu-vexpress-a9/cpu/context_gcc.S
new file mode 100644
index 0000000000..86efcede9f
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/context_gcc.S
@@ -0,0 +1,103 @@
+/*
+ * File      : context.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .text, "ax"
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    cpsid i
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task spsr
+    msr spsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+
+.section .bss.share.isr
+_guest_switch_lvl:
+    .word 0
+
+.section .text.isr, "ax"
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    orrne r4, r4, #0x20     @ it's thumb code
+
+    stmfd sp!, {r4}         @ push cpsr
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
+    msr spsr_cxsf, r4
+    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r0, [ip]
+    str r3, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
diff --git a/bsp/qemu-vexpress-a9/cpu/cp15.h b/bsp/qemu-vexpress-a9/cpu/cp15.h
new file mode 100644
index 0000000000..ebea3f0fe3
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/cp15.h
@@ -0,0 +1,12 @@
+#ifndef __CP15_H__
+#define __CP15_H__
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+
+#endif
diff --git a/bsp/qemu-vexpress-a9/cpu/cp15_gcc.S b/bsp/qemu-vexpress-a9/cpu/cp15_gcc.S
new file mode 100644
index 0000000000..f1ed6492aa
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/cp15_gcc.S
@@ -0,0 +1,140 @@
+/*
+ * File      : cp15_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * http://www.rt-thread.org
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr
diff --git a/bsp/qemu-vexpress-a9/cpu/cpu.c b/bsp/qemu-vexpress-a9/cpu/cpu.c
new file mode 100644
index 0000000000..426da965ad
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/cpu.c
@@ -0,0 +1,37 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+
+/**
+ * @addtogroup ARM CPU
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+	rt_uint32_t level;
+	rt_kprintf("shutdown...\n");
+
+	level = rt_hw_interrupt_disable();
+	while (level)
+	{
+		RT_ASSERT(0);
+	}
+}
+
+/*@}*/
diff --git a/bsp/qemu-vexpress-a9/cpu/gic.c b/bsp/qemu-vexpress-a9/cpu/gic.c
new file mode 100644
index 0000000000..cbef00af22
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/gic.c
@@ -0,0 +1,280 @@
+/*
+ * File      : gic.c, ARM Generic Interrupt Controller
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2014-04-03     Grissiom     many enhancements
+ */
+
+#include <rtthread.h>
+#include <board.h>
+
+#include "gic.h"
+#include "cp15.h"
+
+struct arm_gic
+{
+    rt_uint32_t offset;
+
+    rt_uint32_t dist_hw_base;
+    rt_uint32_t cpu_hw_base;
+};
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+static unsigned int _gic_max_irq;
+
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
+
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_pending(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_active(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
+{
+    rt_uint32_t old_tgt;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+void arm_gic_umask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_dump_type(rt_uint32_t index)
+{
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
+}
+
+void arm_gic_dump(rt_uint32_t index)
+{
+    unsigned int i, k;
+
+    k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+    rt_kprintf("--- hw mask ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n--- hw pending ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
+                                        i * 32));
+    }
+    rt_kprintf("\n--- hw active ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n");
+}
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
+#endif
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
+{
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
+
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
+
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS)
+        _gic_max_irq = ARM_GIC_NR_IRQS;
+
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+
+    GIC_DIST_CTRL(dist_base) = 0x0;
+
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
+
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
+
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
+
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
+
+#if 0
+    /* All interrupts defaults to IGROUP1(IRQ). */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
+#endif
+
+    /* Enable group0 and group1 interrupt forwarding. */
+    GIC_DIST_CTRL(dist_base) = 0x03;
+
+    return 0;
+}
+
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].cpu_hw_base = cpu_base;
+
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
+
+    return 0;
+}
+
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
+{
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
+}
diff --git a/bsp/qemu-vexpress-a9/cpu/gic.h b/bsp/qemu-vexpress-a9/cpu/gic.h
new file mode 100644
index 0000000000..42c061dc1b
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/gic.h
@@ -0,0 +1,32 @@
+/*
+ * File      : gic.h, ARM Generic Interrupt Controller
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+
+#endif
+
diff --git a/bsp/qemu-vexpress-a9/cpu/interrupt.c b/bsp/qemu-vexpress-a9/cpu/interrupt.c
new file mode 100644
index 0000000000..e66f746042
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/interrupt.c
@@ -0,0 +1,113 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "realview.h"
+#include "gic.h"
+
+#define MAX_HANDLERS                NR_IRQS_PBA8
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+/* Those varibles will be accessed in ISR, so we need to share them. */
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+const unsigned int VECTOR_BASE = 0x00;
+extern void rt_cpu_vector_set_base(unsigned int addr);
+extern int system_vectors;
+
+static void rt_hw_vector_init(void)
+{
+    rt_cpu_vector_set_base((unsigned int)&system_vectors);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_uint32_t gic_cpu_base;
+    rt_uint32_t gic_dist_base;
+
+    /* initialize vector table */
+    rt_hw_vector_init();
+
+    /* initialize exceptions table */
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+
+    /* initialize ARM GIC */
+    gic_dist_base = REALVIEW_GIC_DIST_BASE;
+    gic_cpu_base = REALVIEW_GIC_CPU_BASE;
+
+    arm_gic_dist_init(0, gic_dist_base, 0);
+    arm_gic_cpu_init(0, gic_cpu_base);
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    arm_gic_mask(0, vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    arm_gic_umask(0, vector);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
diff --git a/bsp/qemu-vexpress-a9/cpu/interrupt.h b/bsp/qemu-vexpress-a9/cpu/interrupt.h
new file mode 100644
index 0000000000..045246b21d
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/interrupt.h
@@ -0,0 +1,25 @@
+/*
+ * File      : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard      first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_control(int vector, int priority, int route);
+
+void rt_hw_interrupt_init(void);
+
+#endif
diff --git a/bsp/qemu-vexpress-a9/cpu/mmu.c b/bsp/qemu-vexpress-a9/cpu/mmu.c
new file mode 100644
index 0000000000..b2503e4260
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/mmu.c
@@ -0,0 +1,207 @@
+/*
+ * File      : mmu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3<<2)  //cache_on, write_back
+#define CNB            (2<<2)  //cache_on, write_through
+#define NCB            (1<<2)  //cache_off,WR_BUF on
+#define NCNB           (0<<2)  //cache_off,WR_BUF off
+#define AP_RW          (3<<10) //supervisor=RW, user=RW
+#define AP_RO          (2<<10) //supervisor=RW, user=RO
+#define XN             (1<<4)  // eXecute Never
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
+/* Read/Write without cache and write buffer */
+#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_mmu_init(void)
+{
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /* set page table */
+    /* 4G 1:1 memory */
+    rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
+    /* IO memory region */
+    rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+
diff --git a/bsp/qemu-vexpress-a9/cpu/pmu.c b/bsp/qemu-vexpress-a9/cpu/pmu.c
new file mode 100644
index 0000000000..07911a2db7
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/pmu.c
@@ -0,0 +1,12 @@
+#include <rtthread.h>
+#include "pmu.h"
+
+void rt_hw_pmu_dump_feature(void)
+{
+    unsigned long reg;
+
+    reg = rt_hw_pmu_get_control();
+    rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n",
+               reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f);
+    RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f));
+}
diff --git a/bsp/qemu-vexpress-a9/cpu/pmu.h b/bsp/qemu-vexpress-a9/cpu/pmu.h
new file mode 100644
index 0000000000..05c1420dd8
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/pmu.h
@@ -0,0 +1,151 @@
+#ifndef __PMU_H__
+#define __PMU_H__
+
+#include "board.h"
+
+/* Number of counters */
+#define ARM_PMU_CNTER_NR 4
+
+enum rt_hw_pmu_event_type {
+    ARM_PMU_EVENT_PMNC_SW_INCR      = 0x00,
+    ARM_PMU_EVENT_L1_ICACHE_REFILL  = 0x01,
+    ARM_PMU_EVENT_ITLB_REFILL       = 0x02,
+    ARM_PMU_EVENT_L1_DCACHE_REFILL  = 0x03,
+    ARM_PMU_EVENT_L1_DCACHE_ACCESS  = 0x04,
+    ARM_PMU_EVENT_DTLB_REFILL       = 0x05,
+    ARM_PMU_EVENT_MEM_READ          = 0x06,
+    ARM_PMU_EVENT_MEM_WRITE         = 0x07,
+    ARM_PMU_EVENT_INSTR_EXECUTED    = 0x08,
+    ARM_PMU_EVENT_EXC_TAKEN         = 0x09,
+    ARM_PMU_EVENT_EXC_EXECUTED      = 0x0A,
+    ARM_PMU_EVENT_CID_WRITE         = 0x0B,
+};
+
+/* Enable bit */
+#define ARM_PMU_PMCR_E   (0x01 << 0)
+/* Event counter reset */
+#define ARM_PMU_PMCR_P   (0x01 << 1)
+/* Cycle counter reset */
+#define ARM_PMU_PMCR_C   (0x01 << 2)
+/* Cycle counter divider */
+#define ARM_PMU_PMCR_D   (0x01 << 3)
+
+#ifdef __GNUC__
+rt_inline void rt_hw_pmu_enable_cnt(int divide64)
+{
+    unsigned long pmcr;
+    unsigned long pmcntenset;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C;
+    if (divide64)
+        pmcr |= ARM_PMU_PMCR_D;
+    else
+        pmcr &= ~ARM_PMU_PMCR_D;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+
+    /* enable all the counters */
+    pmcntenset = ~0;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset));
+    /* clear overflows(just in case) */
+    asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset));
+}
+
+rt_inline unsigned long rt_hw_pmu_get_control(void)
+{
+    unsigned long pmcr;
+    asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    return pmcr;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_ceid(void)
+{
+    unsigned long reg;
+    /* only PMCEID0 is supported, PMCEID1 is RAZ. */
+    asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg));
+    return reg;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_cnten(void)
+{
+    unsigned long pmcnt;
+    asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt));
+    return pmcnt;
+}
+
+rt_inline void rt_hw_pmu_reset_cycle(void)
+{
+    unsigned long pmcr;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_C;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+    asm volatile ("isb");
+}
+
+rt_inline void rt_hw_pmu_reset_event(void)
+{
+    unsigned long pmcr;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_P;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+    asm volatile ("isb");
+}
+
+rt_inline unsigned long rt_hw_pmu_get_cycle(void)
+{
+    unsigned long cyc;
+    asm volatile ("isb");
+    asm volatile ("mrc  p15, 0, %0, c9, c13, 0" : "=r"(cyc));
+    return cyc;
+}
+
+rt_inline void rt_hw_pmu_select_counter(int idx)
+{
+    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
+
+    asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx));
+    /* Linux add an isb here, don't know why here. */
+    asm volatile ("isb");
+}
+
+rt_inline void rt_hw_pmu_select_event(int idx,
+                                      enum rt_hw_pmu_event_type eve)
+{
+    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
+
+    rt_hw_pmu_select_counter(idx);
+    asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve));
+}
+
+rt_inline unsigned long rt_hw_pmu_read_counter(int idx)
+{
+    unsigned long reg;
+
+    rt_hw_pmu_select_counter(idx);
+    asm volatile ("isb");
+    asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg));
+    return reg;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_ovsr(void)
+{
+    unsigned long reg;
+    asm volatile ("isb");
+    asm ("mrc  p15, 0, %0, c9, c12, 3" : "=r"(reg));
+    return reg;
+}
+
+rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg)
+{
+    asm ("mcr  p15, 0, %0, c9, c12, 3" : : "r"(reg));
+    asm volatile ("isb");
+}
+
+#endif
+
+void rt_hw_pmu_dump_feature(void);
+
+#endif /* end of include guard: __PMU_H__ */
+
diff --git a/bsp/qemu-vexpress-a9/cpu/stack.c b/bsp/qemu-vexpress-a9/cpu/stack.c
new file mode 100644
index 0000000000..4ae1536a20
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/stack.c
@@ -0,0 +1,65 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_uint32_t *stk;
+
+	stk 	 = (rt_uint32_t*)stack_addr;
+	*(stk) 	 = (rt_uint32_t)tentry;			/* entry point */
+	*(--stk) = (rt_uint32_t)texit;			/* lr */
+	*(--stk) = 0;							/* r12 */
+	*(--stk) = 0;							/* r11 */
+	*(--stk) = 0;							/* r10 */
+	*(--stk) = 0;							/* r9 */
+	*(--stk) = 0;							/* r8 */
+	*(--stk) = 0;							/* r7 */
+	*(--stk) = 0;							/* r6 */
+	*(--stk) = 0;							/* r5 */
+	*(--stk) = 0;							/* r4 */
+	*(--stk) = 0;							/* r3 */
+	*(--stk) = 0;							/* r2 */
+	*(--stk) = 0;							/* r1 */
+	*(--stk) = (rt_uint32_t)parameter;		/* r0 : argument */
+
+	/* cpsr */
+	if ((rt_uint32_t)tentry & 0x01)
+		*(--stk) = SVCMODE | 0x20;			/* thumb mode */
+	else
+		*(--stk) = SVCMODE;					/* arm mode   */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/bsp/qemu-vexpress-a9/cpu/start_gcc.S b/bsp/qemu-vexpress-a9/cpu/start_gcc.S
new file mode 100644
index 0000000000..4ab8a4149d
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/start_gcc.S
@@ -0,0 +1,246 @@
+/*
+ * File      : start_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.equ UND_Stack_Size,     0x00000000
+.equ SVC_Stack_Size,     0x00000100
+.equ ABT_Stack_Size,     0x00000000
+.equ RT_FIQ_STACK_PGSZ,  0x00000000
+.equ RT_IRQ_STACK_PGSZ,  0x00000100
+.equ USR_Stack_Size,     0x00000100
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
+
+.section .data.share.isr
+/* stack */
+.globl stack_start
+.globl stack_top
+
+stack_start:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top:
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+
+    /* setup stack */
+    bl      stack_setup
+
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+
+    /* call C++ constructors of global objects                          */
+    ldr     r0, =__ctors_start__
+    ldr     r1, =__ctors_end__
+
+ctor_loop:
+    cmp     r0, r1
+    beq     ctor_end
+    ldr     r2, [r0], #4
+    stmfd   sp!, {r0-r1}
+    mov     lr, pc
+    bx      r2
+    ldmfd   sp!, {r0-r1}
+    b       ctor_loop
+ctor_end:
+
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+    ldr     r0, =stack_top
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_FIQ_STACK_PGSZ
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_IRQ_STACK_PGSZ
+
+    /* come back to SVC mode */
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+    bx      lr
+
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+.section .text.isr, "ax"
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+.globl      rt_current_thread
+
+    .align  5
+.globl vector_irq
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt. If the usr mode guest is
+    @ interrupted, this will just switch to the stack of kernel space.
+    @ save the registers in kernel space won't trigger data abort.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       @ get new task's stack pointer
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl  vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl  vector_undef
+vector_undef:
+    push_svc_reg
+    bl      rt_hw_trap_undef
+    b       .
+
+    .align  5
+    .globl  vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl  vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl  vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .
diff --git a/bsp/qemu-vexpress-a9/cpu/trap.c b/bsp/qemu-vexpress-a9/cpu/trap.c
new file mode 100644
index 0000000000..e3283d7e7e
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/trap.c
@@ -0,0 +1,191 @@
+/*
+ * File      : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "armv7.h"
+
+#include "gic.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    unsigned long ir;
+    unsigned long fullir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    fullir = arm_gic_get_active_irq(0);
+    ir = fullir & GIC_ACK_INTID_MASK;
+
+    if (ir == 1023)
+    {
+        /* Spurious interrupt */
+        return;
+    }
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+    isr_table[ir].counter++;
+#endif
+    if (isr_func)
+    {
+        /* Interrupt for myself. */
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    arm_gic_ack(0, fullir);
+}
+
+void rt_hw_trap_fiq(void)
+{
+    void *param;
+    unsigned long ir;
+    unsigned long fullir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    fullir = arm_gic_get_active_irq(0);
+    ir = fullir & GIC_ACK_INTID_MASK;
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+    param = isr_table[ir].param;
+
+    /* turn to interrupt service routine */
+    isr_func(ir, param);
+
+    /* end of interrupt */
+    arm_gic_ack(0, fullir);
+}
+
diff --git a/bsp/qemu-vexpress-a9/cpu/vector_gcc.S b/bsp/qemu-vexpress-a9/cpu/vector_gcc.S
new file mode 100644
index 0000000000..cbe9bc687b
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/cpu/vector_gcc.S
@@ -0,0 +1,64 @@
+/*
+ * File      : vector_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl    16,0xdeadbeef
diff --git a/bsp/qemu-vexpress-a9/drivers/Kconfig b/bsp/qemu-vexpress-a9/drivers/Kconfig
new file mode 100644
index 0000000000..db0a59d4d1
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/drivers/Kconfig
@@ -0,0 +1,7 @@
+config RT_USING_UART0
+    bool "Enable UART0"
+    default y
+
+config RT_USING_UART1
+    bool "Enable UART1"
+    default y
diff --git a/bsp/qemu-vexpress-a9/drivers/SConscript b/bsp/qemu-vexpress-a9/drivers/SConscript
new file mode 100644
index 0000000000..9987f53e4b
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/drivers/SConscript
@@ -0,0 +1,13 @@
+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/qemu-vexpress-a9/drivers/board.c b/bsp/qemu-vexpress-a9/drivers/board.c
new file mode 100644
index 0000000000..4c63b297d6
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/drivers/board.c
@@ -0,0 +1,91 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-20     Bernard    the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <components.h>
+
+#include "board.h"
+
+#define TIMER_LOAD(hw_base)             __REG32(hw_base + 0x00)
+#define TIMER_VALUE(hw_base)            __REG32(hw_base + 0x04)
+#define TIMER_CTRL(hw_base)             __REG32(hw_base + 0x08)
+#define TIMER_CTRL_ONESHOT              (1 << 0)
+#define TIMER_CTRL_32BIT                (1 << 1)
+#define TIMER_CTRL_DIV1                 (0 << 2)
+#define TIMER_CTRL_DIV16                (1 << 2)
+#define TIMER_CTRL_DIV256               (2 << 2)
+#define TIMER_CTRL_IE                   (1 << 5)        /* Interrupt Enable (versatile only) */
+#define TIMER_CTRL_PERIODIC             (1 << 6)
+#define TIMER_CTRL_ENABLE               (1 << 7)
+
+#define TIMER_INTCLR(hw_base)           __REG32(hw_base + 0x0c)
+#define TIMER_RIS(hw_base)              __REG32(hw_base + 0x10)
+#define TIMER_MIS(hw_base)              __REG32(hw_base + 0x14)
+#define TIMER_BGLOAD(hw_base)           __REG32(hw_base + 0x18)
+
+#define SYS_CTRL                        __REG32(REALVIEW_SCTL_BASE)
+
+#define TIMER_HW_BASE                   REALVIEW_TIMER2_3_BASE
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    rt_tick_increase();
+    /* clear interrupt */
+    TIMER_INTCLR(TIMER_HW_BASE) = 0x01;
+}
+
+int rt_hw_timer_init(void)
+{
+    rt_uint32_t val;
+
+    SYS_CTRL |= REALVIEW_REFCLK;
+
+    /* Setup Timer0 for generating irq */
+    val = TIMER_CTRL(TIMER_HW_BASE);
+    val &= ~TIMER_CTRL_ENABLE;
+    val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
+    TIMER_CTRL(TIMER_HW_BASE) = val;
+
+    TIMER_LOAD(TIMER_HW_BASE) = 1000;
+
+    /* enable timer */
+    TIMER_CTRL(TIMER_HW_BASE) |= TIMER_CTRL_ENABLE;
+
+    rt_hw_interrupt_install(IRQ_PBA8_TIMER2_3, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IRQ_PBA8_TIMER2_3);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+/**
+ * This function will initialize beaglebone board
+ */
+void rt_hw_board_init(void)
+{
+    /* initialzie hardware interrupt */
+    rt_hw_interrupt_init();
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+
+    rt_components_board_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+    rt_thread_idle_sethook(idle_wfi);
+}
diff --git a/bsp/qemu-vexpress-a9/drivers/board.h b/bsp/qemu-vexpress-a9/drivers/board.h
new file mode 100644
index 0000000000..2d3d87fdbb
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/drivers/board.h
@@ -0,0 +1,32 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard    the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <realview.h>
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN      ((void*)&__bss_end)
+#endif
+
+#define HEAP_END        (void*)(0x60000000 + 8 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/qemu-vexpress-a9/drivers/realview.h b/bsp/qemu-vexpress-a9/drivers/realview.h
new file mode 100644
index 0000000000..2e950b1bca
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/drivers/realview.h
@@ -0,0 +1,322 @@
+#ifndef __AM33XX_H__
+#define __AM33XX_H__
+
+#define __REG32(x)  (*((volatile unsigned int *)(x)))
+#define __REG16(x)  (*((volatile unsigned short *)(x)))
+
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_UART0_BASE         0x10009000  /* UART 0 */
+#define REALVIEW_UART1_BASE         0x1000A000  /* UART 1 */
+#define REALVIEW_UART2_BASE         0x1000B000  /* UART 2 */
+#define REALVIEW_UART3_BASE         0x1000C000  /* UART 3 */
+#define REALVIEW_SSP_BASE           0x1000D000  /* Synchronous Serial Port */
+#define REALVIEW_WATCHDOG0_BASE     0x1000F000  /* Watchdog 0 */
+#define REALVIEW_WATCHDOG_BASE      0x10010000  /* watchdog interface */
+#define REALVIEW_TIMER0_1_BASE      0x10011000  /* Timer 0 and 1 */
+#define REALVIEW_TIMER2_3_BASE      0x10012000  /* Timer 2 and 3 */
+#define REALVIEW_GPIO0_BASE         0x10013000  /* GPIO port 0 */
+#define REALVIEW_RTC_BASE           0x10017000  /* Real Time Clock */
+#define REALVIEW_TIMER4_5_BASE      0x10018000  /* Timer 4/5 */
+#define REALVIEW_TIMER6_7_BASE      0x10019000  /* Timer 6/7 */
+#define REALVIEW_SCTL_BASE          0x10001000  /* System Controller */
+#define REALVIEW_CLCD_BASE          0x10020000  /* CLCD */
+#define REALVIEW_ONB_SRAM_BASE      0x10060000  /* On-board SRAM */
+#define REALVIEW_DMC_BASE           0x100E0000  /* DMC configuration */
+#define REALVIEW_SMC_BASE           0x100E1000  /* SMC configuration */
+#define REALVIEW_CAN_BASE           0x100E2000  /* CAN bus */
+#define REALVIEW_GIC_CPU_BASE       0x1E000100  /* Generic interrupt controller CPU interface */
+#define REALVIEW_FLASH0_BASE        0x40000000
+#define REALVIEW_FLASH0_SIZE        SZ_64M
+#define REALVIEW_FLASH1_BASE        0x44000000
+#define REALVIEW_FLASH1_SIZE        SZ_64M
+
+#define VEXPRESS_SRAM_BASE          0x48000000
+
+#define REALVIEW_ETH_BASE           0x4E000000  /* Ethernet */
+#define REALVIEW_USB_BASE           0x4F000000  /* USB */
+#define REALVIEW_GIC_DIST_BASE      0x1E001000  /* Generic interrupt controller distributor */
+#define REALVIEW_LT_BASE            0xC0000000  /* Logic Tile expansion */
+#define REALVIEW_SDRAM6_BASE        0x70000000  /* SDRAM bank 6 256MB */
+#define REALVIEW_SDRAM7_BASE        0x80000000  /* SDRAM bank 7 256MB */
+
+#define REALVIEW_SYS_PLD_CTRL1      0x74
+
+/*
+ * PCI regions
+ */
+#define REALVIEW_PCI_BASE           0x90040000  /* PCI-X Unit base */
+#define REALVIEW_PCI_IO_BASE        0x90050000  /* IO Region on AHB */
+#define REALVIEW_PCI_MEM_BASE       0xA0000000  /* MEM Region on AHB */
+
+#define REALVIEW_PCI_BASE_SIZE      0x10000     /* 16 Kb */
+#define REALVIEW_PCI_IO_SIZE        0x1000      /* 4 Kb */
+#define REALVIEW_PCI_MEM_SIZE       0x20000000  /* 512 MB */
+
+/*
+ * Memory definitions
+ */
+#define REALVIEW_BOOT_ROM_LO          0x30000000    /* DoC Base (64Mb)... */
+#define REALVIEW_BOOT_ROM_HI          0x30000000
+#define REALVIEW_BOOT_ROM_BASE        REALVIEW_BOOT_ROM_HI  /*  Normal position */
+#define REALVIEW_BOOT_ROM_SIZE        SZ_64M
+
+#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
+#define REALVIEW_SSRAM_SIZE           SZ_2M
+
+/*
+ *  SDRAM
+ */
+#define REALVIEW_SDRAM_BASE           0x00000000
+
+/*
+ *  Logic expansion modules
+ *
+ */
+#define IRQ_PBA8_GIC_START          32
+
+/*
+ * PB-A8 on-board gic irq sources
+ */
+#define IRQ_PBA8_WATCHDOG   (IRQ_PBA8_GIC_START + 0)    /* Watchdog timer */
+#define IRQ_PBA8_SOFT       (IRQ_PBA8_GIC_START + 1)    /* Software interrupt */
+#define IRQ_PBA8_TIMER0_1   (IRQ_PBA8_GIC_START + 2)    /* Timer 0/1 (default timer) */
+#define IRQ_PBA8_TIMER2_3   (IRQ_PBA8_GIC_START + 3)    /* Timer 2/3 */
+#define IRQ_PBA8_RTC        (IRQ_PBA8_GIC_START + 4)    /* Timer 2/3 */
+
+#define IRQ_PBA8_UART0      (IRQ_PBA8_GIC_START + 5)    /* UART 0 on development chip */
+#define IRQ_PBA8_UART1      (IRQ_PBA8_GIC_START + 6)    /* UART 1 on development chip */
+#define IRQ_PBA8_UART2      (IRQ_PBA8_GIC_START + 7)    /* UART 2 on development chip */
+#define IRQ_PBA8_UART3      (IRQ_PBA8_GIC_START + 8)    /* UART 3 on development chip */
+
+/* 9 reserved */
+#define IRQ_PBA8_SSP        (IRQ_PBA8_GIC_START + 11)   /* Synchronous Serial Port */
+#define IRQ_PBA8_SCI        (IRQ_PBA8_GIC_START + 16)   /* Smart Card Interface */
+#define IRQ_PBA8_MMCI0A     (IRQ_PBA8_GIC_START + 17)   /* Multimedia Card 0A */
+#define IRQ_PBA8_MMCI0B     (IRQ_PBA8_GIC_START + 18)   /* Multimedia Card 0B */
+#define IRQ_PBA8_AACI       (IRQ_PBA8_GIC_START + 19)   /* Audio Codec */
+#define IRQ_PBA8_KMI0       (IRQ_PBA8_GIC_START + 20)   /* Keyboard/Mouse port 0 */
+#define IRQ_PBA8_KMI1       (IRQ_PBA8_GIC_START + 21)   /* Keyboard/Mouse port 1 */
+#define IRQ_PBA8_CHARLCD    (IRQ_PBA8_GIC_START + 22)   /* Character LCD */
+#define IRQ_PBA8_CLCD       (IRQ_PBA8_GIC_START + 23)   /* CLCD controller */
+#define IRQ_PBA8_DMAC       (IRQ_PBA8_GIC_START + 24)   /* DMA controller */
+#define IRQ_PBA8_PWRFAIL    (IRQ_PBA8_GIC_START + 25)   /* Power failure */
+#define IRQ_PBA8_PISMO      (IRQ_PBA8_GIC_START + 26)   /* PISMO interface */
+#define IRQ_PBA8_DoC        (IRQ_PBA8_GIC_START + 27)   /* Disk on Chip memory controller */
+#define IRQ_PBA8_ETH        (IRQ_PBA8_GIC_START + 28)   /* Ethernet controller */
+#define IRQ_PBA8_USB        (IRQ_PBA8_GIC_START + 29)   /* USB controller */
+#define IRQ_PBA8_TSPEN      (IRQ_PBA8_GIC_START + 30)   /* Touchscreen pen */
+#define IRQ_PBA8_TSKPAD     (IRQ_PBA8_GIC_START + 31)   /* Touchscreen keypad */
+
+#define IRQ_PBA8_PMU        (IRQ_PBA8_GIC_START + 47)   /* Cortex-A8 PMU */
+
+/* ... */
+#define IRQ_PBA8_PCI0       (IRQ_PBA8_GIC_START + 50)
+#define IRQ_PBA8_PCI1       (IRQ_PBA8_GIC_START + 51)
+#define IRQ_PBA8_PCI2       (IRQ_PBA8_GIC_START + 52)
+#define IRQ_PBA8_PCI3       (IRQ_PBA8_GIC_START + 53)
+
+#define IRQ_PBA8_SMC        -1
+#define IRQ_PBA8_SCTL       -1
+
+#define NR_GIC_PBA8     1
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PBA8
+ */
+#define NR_IRQS_PBA8        (IRQ_PBA8_GIC_START + 64)
+
+/* ------------------------------------------------------------------------
+ *  RealView Registers
+ * ------------------------------------------------------------------------
+ *
+ */
+#define REALVIEW_SYS_ID_OFFSET               0x00
+#define REALVIEW_SYS_SW_OFFSET               0x04
+#define REALVIEW_SYS_LED_OFFSET              0x08
+#define REALVIEW_SYS_OSC0_OFFSET             0x0C
+
+#define REALVIEW_SYS_OSC1_OFFSET             0x10
+#define REALVIEW_SYS_OSC2_OFFSET             0x14
+#define REALVIEW_SYS_OSC3_OFFSET             0x18
+#define REALVIEW_SYS_OSC4_OFFSET             0x1C   /* OSC1 for RealView/AB */
+
+#define REALVIEW_SYS_LOCK_OFFSET             0x20
+#define REALVIEW_SYS_100HZ_OFFSET            0x24
+#define REALVIEW_SYS_CFGDATA1_OFFSET         0x28
+#define REALVIEW_SYS_CFGDATA2_OFFSET         0x2C
+#define REALVIEW_SYS_FLAGS_OFFSET            0x30
+#define REALVIEW_SYS_FLAGSSET_OFFSET         0x30
+#define REALVIEW_SYS_FLAGSCLR_OFFSET         0x34
+#define REALVIEW_SYS_NVFLAGS_OFFSET          0x38
+#define REALVIEW_SYS_NVFLAGSSET_OFFSET       0x38
+#define REALVIEW_SYS_NVFLAGSCLR_OFFSET       0x3C
+#define REALVIEW_SYS_RESETCTL_OFFSET         0x40
+#define REALVIEW_SYS_PCICTL_OFFSET           0x44
+#define REALVIEW_SYS_MCI_OFFSET              0x48
+#define REALVIEW_SYS_FLASH_OFFSET            0x4C
+#define REALVIEW_SYS_CLCD_OFFSET             0x50
+#define REALVIEW_SYS_CLCDSER_OFFSET          0x54
+#define REALVIEW_SYS_BOOTCS_OFFSET           0x58
+#define REALVIEW_SYS_24MHz_OFFSET            0x5C
+#define REALVIEW_SYS_MISC_OFFSET             0x60
+#define REALVIEW_SYS_IOSEL_OFFSET            0x70
+#define REALVIEW_SYS_PROCID_OFFSET           0x84
+#define REALVIEW_SYS_TEST_OSC0_OFFSET        0xC0
+#define REALVIEW_SYS_TEST_OSC1_OFFSET        0xC4
+#define REALVIEW_SYS_TEST_OSC2_OFFSET        0xC8
+#define REALVIEW_SYS_TEST_OSC3_OFFSET        0xCC
+#define REALVIEW_SYS_TEST_OSC4_OFFSET        0xD0
+
+#define REALVIEW_SYS_BASE                    0x10000000
+#define REALVIEW_SYS_ID                      (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
+#define REALVIEW_SYS_SW                      (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
+#define REALVIEW_SYS_LED                     (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
+#define REALVIEW_SYS_OSC0                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
+#define REALVIEW_SYS_OSC1                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
+
+#define REALVIEW_SYS_LOCK                    (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
+#define REALVIEW_SYS_100HZ                   (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
+#define REALVIEW_SYS_CFGDATA1                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
+#define REALVIEW_SYS_CFGDATA2                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
+#define REALVIEW_SYS_FLAGS                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
+#define REALVIEW_SYS_FLAGSSET                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
+#define REALVIEW_SYS_FLAGSCLR                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
+#define REALVIEW_SYS_NVFLAGS                 (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
+#define REALVIEW_SYS_NVFLAGSSET              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
+#define REALVIEW_SYS_NVFLAGSCLR              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
+#define REALVIEW_SYS_RESETCTL                (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
+#define REALVIEW_SYS_PCICTL                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
+#define REALVIEW_SYS_MCI                     (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
+#define REALVIEW_SYS_FLASH                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
+#define REALVIEW_SYS_CLCD                    (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
+#define REALVIEW_SYS_CLCDSER                 (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
+#define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
+#define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
+#define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
+#define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
+#define REALVIEW_SYS_PROCID                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
+#define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
+#define REALVIEW_SYS_TEST_OSC1               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
+#define REALVIEW_SYS_TEST_OSC2               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
+#define REALVIEW_SYS_TEST_OSC3               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
+#define REALVIEW_SYS_TEST_OSC4               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
+
+#define REALVIEW_SYS_CTRL_LED         (1 << 0)
+
+/* ------------------------------------------------------------------------
+ *  RealView control registers
+ * ------------------------------------------------------------------------
+ */
+
+/*
+ * REALVIEW_IDFIELD
+ *
+ * 31:24 = manufacturer (0x41 = ARM)
+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
+ * 11:4  = build value
+ * 3:0   = revision number (0x1 = rev B (AHB))
+ */
+
+/*
+ * REALVIEW_SYS_LOCK
+ *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
+ *     SYS_CLD, SYS_BOOTCS
+ */
+#define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
+#define REALVIEW_SYS_LOCKVAL        0xA05F
+#define REALVIEW_SYS_LOCKVAL_MASK   0xFFFF  /* write 0xA05F to enable write access */
+
+/*
+ * REALVIEW_SYS_FLASH
+ */
+#define REALVIEW_FLASHPROG_FLVPPEN  (1 << 0)    /* Enable writing to flash */
+
+/*
+ * REALVIEW_INTREG
+ *     - used to acknowledge and control MMCI and UART interrupts
+ */
+#define REALVIEW_INTREG_WPROT        0x00   /* MMC protection status (no interrupt generated) */
+#define REALVIEW_INTREG_RI0          0x01   /* Ring indicator UART0 is asserted,              */
+#define REALVIEW_INTREG_CARDIN       0x08   /* MMCI card in detect                            */
+/* write 1 to acknowledge and clear               */
+#define REALVIEW_INTREG_RI1          0x02   /* Ring indicator UART1 is asserted,              */
+#define REALVIEW_INTREG_CARDINSERT   0x03   /* Signal insertion of MMC card                   */
+
+/*
+ *  LED settings, bits [7:0]
+ */
+#define REALVIEW_SYS_LED0             (1 << 0)
+#define REALVIEW_SYS_LED1             (1 << 1)
+#define REALVIEW_SYS_LED2             (1 << 2)
+#define REALVIEW_SYS_LED3             (1 << 3)
+#define REALVIEW_SYS_LED4             (1 << 4)
+#define REALVIEW_SYS_LED5             (1 << 5)
+#define REALVIEW_SYS_LED6             (1 << 6)
+#define REALVIEW_SYS_LED7             (1 << 7)
+
+#define ALL_LEDS                  0xFF
+
+#define LED_BANK                  REALVIEW_SYS_LED
+
+/*
+ * Control registers
+ */
+#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
+#define REALVIEW_FLASHPROG_OFFSET   0x4 /* Flash devices */
+#define REALVIEW_INTREG_OFFSET      0x8 /* Interrupt control */
+#define REALVIEW_DECODE_OFFSET      0xC /* Fitted logic modules */
+
+/*
+ *  Clean base - dummy
+ *
+ */
+#define CLEAN_BASE                      REALVIEW_BOOT_ROM_HI
+
+/*
+ * System controller bit assignment
+ */
+#define REALVIEW_REFCLK 0
+#define REALVIEW_TIMCLK 1
+
+#define REALVIEW_TIMER1_EnSel   15
+#define REALVIEW_TIMER2_EnSel   17
+#define REALVIEW_TIMER3_EnSel   19
+#define REALVIEW_TIMER4_EnSel   21
+
+struct rt_hw_register
+{
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+    unsigned long ORIG_r0;
+};
+
+#include <armv7.h>
+
+/* Interrupt Control Interface */
+#define ARM_GIC_CPU_BASE    0x1E000000
+
+/* number of interrupts on board */
+#define ARM_GIC_NR_IRQS     96
+/* only one GIC available */
+#define ARM_GIC_MAX_NR      1
+
+#endif
+
diff --git a/bsp/qemu-vexpress-a9/drivers/serial.c b/bsp/qemu-vexpress-a9/drivers/serial.c
new file mode 100644
index 0000000000..786a26a4ba
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/drivers/serial.c
@@ -0,0 +1,183 @@
+/*
+ *  serial.c UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include "serial.h"
+
+struct hw_uart_device
+{
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+};
+
+#define UART_DR(base)   __REG32(base + 0x00)
+#define UART_FR(base)   __REG32(base + 0x18)
+#define UART_CR(base)   __REG32(base + 0x30)
+#define UART_IMSC(base) __REG32(base + 0x38)
+#define UART_ICR(base)  __REG32(base + 0x44)
+
+#define UARTFR_RXFE     0x10
+#define UARTFR_TXFF     0x20
+#define UARTIMSC_RXIM   0x10
+#define UARTIMSC_TXIM   0x20
+#define UARTICR_RXIC    0x10
+#define UARTICR_TXIC    0x20
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        UART_IMSC(uart->hw_base) &= ~UARTIMSC_RXIM;
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UART_IMSC(uart->hw_base) |= UARTIMSC_RXIM;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while (UART_FR(uart->hw_base) & UARTFR_TXFF);
+    UART_DR(uart->hw_base) = c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    ch = -1;
+    if (!(UART_FR(uart->hw_base) & UARTFR_RXFE))
+    {
+        ch = UART_DR(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+#ifdef RT_USING_UART0
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    REALVIEW_UART0_BASE,
+    IRQ_PBA8_UART0,
+};
+static struct rt_serial_device _serial0;
+#endif
+
+#ifdef RT_USING_UART1
+/* UART1 device driver structure */
+static struct hw_uart_device _uart1_device =
+{
+    REALVIEW_UART1_BASE,
+    IRQ_PBA8_UART1,
+};
+static struct rt_serial_device _serial1;
+#endif
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART0
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
+    /* enable Rx and Tx of UART */
+    UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9);
+#endif
+
+#ifdef RT_USING_UART1
+    uart = &_uart1_device;
+    _serial1.ops = &_uart_ops;
+    _serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+    /* enable Rx and Tx of UART */
+    UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1");
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/qemu-vexpress-a9/drivers/serial.h b/bsp/qemu-vexpress-a9/drivers/serial.h
new file mode 100644
index 0000000000..52e6f07ea3
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/drivers/serial.h
@@ -0,0 +1,39 @@
+/*
+ *  UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+#include <board.h>
+
+int rt_hw_uart_init(void);
+
+#endif
+
+
diff --git a/bsp/qemu-vexpress-a9/link.lds b/bsp/qemu-vexpress-a9/link.lds
new file mode 100644
index 0000000000..4a30d56a22
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/link.lds
@@ -0,0 +1,91 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SECTIONS
+{
+    . = 0x60000000;
+
+    __text_start = .;
+    .text :
+    {
+        *(.vectors)
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    __data_start = .;
+    . = ALIGN(4);
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(4);
+    __bss_start = __data_end;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}
diff --git a/bsp/qemu-vexpress-a9/qemu.bat b/bsp/qemu-vexpress-a9/qemu.bat
new file mode 100644
index 0000000000..33cae43db5
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/qemu.bat
@@ -0,0 +1 @@
+qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial vc -serial vc
diff --git a/bsp/qemu-vexpress-a9/qemu.sh b/bsp/qemu-vexpress-a9/qemu.sh
new file mode 100644
index 0000000000..e9568fa269
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/qemu.sh
@@ -0,0 +1 @@
+qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial vc -serial vc
diff --git a/bsp/qemu-vexpress-a9/rtconfig.h b/bsp/qemu-vexpress-a9/rtconfig.h
new file mode 100644
index 0000000000..80fa9f83c6
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/rtconfig.h
@@ -0,0 +1,134 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_DEBUG
+#define RT_USING_OVERFLOW_CHECK
+/* RT_DEBUG_INIT is not set */
+/* RT_DEBUG_THREAD is not set */
+#define RT_USING_HOOK
+/* RT_USING_TIMER_SOFT is not set */
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_MEMHEAP
+#define RT_USING_HEAP
+#define RT_USING_SMALL_MEM
+/* RT_USING_SLAB is not set */
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+/* RT_USING_MODULE is not set */
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+
+/* C++ features */
+
+/* RT_USING_CPLUSPLUS is not set */
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_STACK_SIZE 4096
+/* FINSH_USING_AUTH is not set */
+#define FINSH_DEFAULT_PASSWORD "rtthread"
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+/* FINSH_USING_MSH_ONLY is not set */
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FD_MAX 4
+#define RT_USING_DFS_ELMFAT
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_MAX_LFN 256
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+/* RT_DFS_ELM_USE_ERASE is not set */
+#define RT_DFS_ELM_REENTRANT
+#define RT_USING_DFS_DEVFS
+/* RT_USING_DFS_NET is not set */
+/* RT_USING_DFS_NFS is not set */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+/* RT_USING_CAN is not set */
+/* RT_USING_HWTIMER is not set */
+/* RT_USING_I2C is not set */
+#define RT_USING_PIN
+/* RT_USING_MTD_NOR is not set */
+/* RT_USING_MTD_NAND is not set */
+/* RT_USING_RTC is not set */
+/* RT_USING_SDIO is not set */
+/* RT_USING_SPI is not set */
+/* RT_USING_WDT is not set */
+/* RT_USING_USB_HOST is not set */
+/* RT_USING_USB_DEVICE is not set */
+
+/* libc */
+
+#define RT_USING_LIBC
+#define RT_USING_PTHREADS
+
+/* Network stack */
+
+/* light weight TCP/IP stack */
+
+/* RT_USING_LWIP is not set */
+
+/* Modbus master and slave stack */
+
+/* RT_USING_MODBUS is not set */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+/* language packages */
+
+/* miscellaneous packages */
+
+#define PKG_USING_HELLO
+
+/* multimedia packages */
+
+/* security packages */
+
+/* system packages */
+
+/* PKG_USING_CMBACKTRACE is not set */
+#define RT_USING_UART0
+#define RT_USING_UART1
+
+#endif
diff --git a/bsp/qemu-vexpress-a9/rtconfig.py b/bsp/qemu-vexpress-a9/rtconfig.py
new file mode 100644
index 0000000000..d11f0aa432
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/rtconfig.py
@@ -0,0 +1,103 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='vexpress-a9'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = 'C:/Keil'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv7-a -marm -msoft-float'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LINK_SCRIPT = 'link.lds'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors'+\
+                      ' -T %s' % LINK_SCRIPT
+
+    CPATH = ''
+    LPATH = ''
+
+    # generate debug info in all cases
+    AFLAGS += ' -gdwarf-2'
+    CFLAGS += ' -g -gdwarf-2'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
+                  SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMP'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' --cpu DARMP'
+
+    CFLAGS = ''
+    AFLAGS = ''
+    LFLAGS = ' --config rtthread.icf'
+
+    EXEC_PATH += '/arm/bin/'
+    RT_USING_MINILIBC = False
+    POST_ACTION = ''
diff --git a/bsp/samd21/README.txt b/bsp/samd21/README.txt
new file mode 100644
index 0000000000..cc705e2d2e
--- /dev/null
+++ b/bsp/samd21/README.txt
@@ -0,0 +1,5 @@
+浣跨敤SAMD21-Xplained-Pro寮�鍙戞澘
+scons:
+  scons
+  scons --target=mdk5
+demo浠ｇ爜婕旂ず浜嗕覆鍙ｃ�佸閮ㄤ腑鏂�丷TC浣庡姛鑰楀敜閱�
diff --git a/bsp/samd21/SAM_D2X_RTT.sct b/bsp/samd21/SAM_D2X_RTT.sct
new file mode 100644
index 0000000000..45489c5687
--- /dev/null
+++ b/bsp/samd21/SAM_D2X_RTT.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/samd21/SConscript b/bsp/samd21/SConscript
new file mode 100644
index 0000000000..744d8d7821
--- /dev/null
+++ b/bsp/samd21/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/samd21/SConstruct b/bsp/samd21/SConstruct
new file mode 100644
index 0000000000..0773dea2fa
--- /dev/null
+++ b/bsp/samd21/SConstruct
@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'SAM_D2X_RTT.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/samd21/applications/SConscript b/bsp/samd21/applications/SConscript
new file mode 100644
index 0000000000..3c69933a88
--- /dev/null
+++ b/bsp/samd21/applications/SConscript
@@ -0,0 +1,14 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Application', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
\ No newline at end of file
diff --git a/bsp/samd21/applications/application.c b/bsp/samd21/applications/application.c
new file mode 100644
index 0000000000..d311cb23fc
--- /dev/null
+++ b/bsp/samd21/applications/application.c
@@ -0,0 +1,119 @@
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "board.h"
+
+#include "port.h"
+#include "extint.h"
+
+#include "sleep_timer.h"
+
+void LED_Init(void)
+{
+    struct port_config config_port_pin;
+
+    port_get_config_defaults(&config_port_pin);
+    config_port_pin.direction  = PORT_PIN_DIR_INPUT;
+    config_port_pin.input_pull = PORT_PIN_PULL_UP;
+    port_pin_set_config(PIN_PA15, &config_port_pin);
+
+    config_port_pin.direction  = PORT_PIN_DIR_OUTPUT;
+    port_pin_set_config(PIN_PB30, &config_port_pin);
+}
+
+void LED_ON(void)
+{
+    port_pin_set_output_level(PIN_PB30, false);
+}
+
+void LED_OFF(void)
+{
+    port_pin_set_output_level(PIN_PB30, true);
+}
+
+void extint_detection_callback(void);
+
+void configure_extint_channel(void)
+{
+//! [setup_1]
+    struct extint_chan_conf config_extint_chan;
+//! [setup_1]
+//! [setup_2]
+    extint_chan_get_config_defaults(&config_extint_chan);
+//! [setup_2]
+
+//! [setup_3]
+    config_extint_chan.gpio_pin           = PIN_PA15A_EIC_EXTINT15;
+    config_extint_chan.gpio_pin_mux       = MUX_PA15A_EIC_EXTINT15;
+    config_extint_chan.gpio_pin_pull      = EXTINT_PULL_UP;
+    config_extint_chan.detection_criteria = EXTINT_DETECT_BOTH;
+//! [setup_3]
+//! [setup_4]
+    extint_chan_set_config(15, &config_extint_chan);
+//! [setup_4]
+}
+
+void configure_extint_callbacks(void)
+{
+//! [setup_5]
+    extint_register_callback(extint_detection_callback, 15, EXTINT_CALLBACK_TYPE_DETECT);
+//! [setup_5]
+//! [setup_6]
+    extint_chan_enable_callback(15, EXTINT_CALLBACK_TYPE_DETECT);
+//! [setup_6]
+}
+
+//! [setup_7]
+void extint_detection_callback(void)
+{
+    bool pin_state = port_pin_get_input_level(PIN_PA15);
+    port_pin_set_output_level(PIN_PB30, pin_state);
+}
+
+static struct rt_semaphore _rx_sem;
+
+static rt_err_t _rx_ind(rt_device_t dev, rt_size_t size)
+{
+    return rt_sem_release(&_rx_sem);
+}
+
+void rt_init_thread_entry(void* parameter)
+{
+    rt_thread_t thread;
+    rt_device_t dev;
+
+    rt_kprintf("SYSTEM running at %uhz\n", SystemCoreClock);
+
+#ifdef RT_USING_FINSH
+    /* init finsh */
+    finsh_system_init();
+    finsh_set_device("uart1");
+#endif
+
+    LED_Init();
+    configure_extint_channel();
+    configure_extint_callbacks();
+
+    sleep_timer_init();
+    // sleep_timer_start(1500);
+
+    while (1)
+    {
+        rt_kprintf("init thread running tick:%u\n", rt_tick_get());
+        rt_thread_delay(2*RT_TICK_PER_SECOND);
+    }
+}
+
+int rt_application_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL,
+                            512, RT_THREAD_PRIORITY_MAX / 3, 20);
+
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+
+    return 0;
+}
+
diff --git a/bsp/samd21/applications/startup.c b/bsp/samd21/applications/startup.c
new file mode 100644
index 0000000000..b8c2c83d0d
--- /dev/null
+++ b/bsp/samd21/applications/startup.c
@@ -0,0 +1,121 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-31     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+/**
+ * @addtogroup STM32
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+#ifdef  DEBUG
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+    rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+    rt_kprintf("       file  %s\r\n", file);
+    rt_kprintf("       line  %d\r\n", line);
+
+    while (1) ;
+}
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init tick */
+    rt_system_tick_init();
+
+    /* init kernel object */
+    rt_system_object_init();
+
+    /* init timer system */
+    rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+    #ifdef __CC_ARM
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)CHIP_SRAM_END);
+    #elif __ICCARM__
+        rt_system_heap_init(__segment_end("HEAP"), (void*)CHIP_SRAM_END);
+    #else
+        /* init memory system */
+        rt_system_heap_init((void*)&__bss_end, (void*)CHIP_SRAM_END);
+    #endif
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/
diff --git a/bsp/samd21/asflib_config/clock_samd20/conf_clocks.h b/bsp/samd21/asflib_config/clock_samd20/conf_clocks.h
new file mode 100644
index 0000000000..5f51a8e926
--- /dev/null
+++ b/bsp/samd21/asflib_config/clock_samd20/conf_clocks.h
@@ -0,0 +1,170 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 Clock configuration
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+#  define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+#  define CONF_CLOCK_FLASH_WAIT_STATES            0
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+#  define CONF_CLOCK_XOSC32K_ENABLE               false
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            true
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       false
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+#  define CONF_CLOCK_DFLL_ENABLE                  false
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
+#  define CONF_CLOCK_DFLL_ON_DEMAND               false
+
+/* DFLL open loop mode configuration */
+#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)
+
+/* DFLL closed loop mode configuration */
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         1465 /* (48000000 / 32768) */
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)
+
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 */
+#  define CONF_CLOCK_GCLK_1_ENABLE                false
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                false
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             32
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 */
+#  define CONF_CLOCK_GCLK_3_ENABLE                false
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 4 */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
+
diff --git a/bsp/samd21/asflib_config/clock_samd21_r21_da_ha1/conf_clocks.h b/bsp/samd21/asflib_config/clock_samd21_r21_da_ha1/conf_clocks.h
new file mode 100644
index 0000000000..70ad8095f8
--- /dev/null
+++ b/bsp/samd21/asflib_config/clock_samd21_r21_da_ha1/conf_clocks.h
@@ -0,0 +1,198 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Clock configuration
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+#  define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+#  define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT     false
+#  define CONF_CLOCK_FLASH_WAIT_STATES            1
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+#  define CONF_CLOCK_XOSC32K_ENABLE               true
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_2048
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  true
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            false
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       true
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+#  define CONF_CLOCK_DFLL_ENABLE                  true
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
+#  define CONF_CLOCK_DFLL_ON_DEMAND               true
+
+/* DFLL open loop mode configuration */
+#  define CONF_CLOCK_DFLL_FINE_VALUE              ((*((uint32_t*)(0x806020 + 8))) & 0x3FF)/*(512)*/
+
+/* DFLL closed loop mode configuration */
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_2
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32768)
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    ((*((uint8_t*)(0x806020 + 7))) >> 2)/*(0x1f / 4)*/
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      ((*((uint32_t*)(0x806020 + 8))) & 0x3FF)/*(0xff / 4)*/
+
+/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
+#  define CONF_CLOCK_DPLL_ENABLE                  false
+#  define CONF_CLOCK_DPLL_ON_DEMAND               true
+#  define CONF_CLOCK_DPLL_RUN_IN_STANDBY          false
+#  define CONF_CLOCK_DPLL_LOCK_BYPASS             false
+#  define CONF_CLOCK_DPLL_WAKE_UP_FAST            false
+#  define CONF_CLOCK_DPLL_LOW_POWER_ENABLE        false
+
+#  define CONF_CLOCK_DPLL_LOCK_TIME               SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
+#  define CONF_CLOCK_DPLL_REFERENCE_CLOCK         SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
+#  define CONF_CLOCK_DPLL_FILTER                  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
+
+#  define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY     32768
+#  define CONF_CLOCK_DPLL_REFERENCE_DIVIDER       1
+#  define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY        48000000
+
+/* DPLL GCLK reference configuration */
+#  define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR  GCLK_GENERATOR_1
+/* DPLL GCLK lock timer configuration */
+#  define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR     GCLK_GENERATOR_1
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_DFLL
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 */
+#  define CONF_CLOCK_GCLK_1_ENABLE                false
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        true
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                true
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        true
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             1
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 */
+#  define CONF_CLOCK_GCLK_3_ENABLE                false
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 4 */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 8 */
+#  define CONF_CLOCK_GCLK_8_ENABLE                false
+#  define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_8_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_8_PRESCALER             1
+#  define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE         false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
+
diff --git a/bsp/samd21/asflib_config/conf_extint.h b/bsp/samd21/asflib_config/conf_extint.h
new file mode 100644
index 0000000000..53fa780ba7
--- /dev/null
+++ b/bsp/samd21/asflib_config/conf_extint.h
@@ -0,0 +1,51 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 External Interrupt Driver Configuration Header
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_EXTINT_H_INCLUDED
+#define CONF_EXTINT_H_INCLUDED
+
+#  define EXTINT_CLOCK_SOURCE      GCLK_GENERATOR_2
+
+#endif
diff --git a/bsp/samd21/board/SConscript b/bsp/samd21/board/SConscript
new file mode 100644
index 0000000000..ea79ebb925
--- /dev/null
+++ b/bsp/samd21/board/SConscript
@@ -0,0 +1,20 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+path = [cwd]
+
+#remove other no use files
+#SrcRemove(src, 'i2c_iomaster.c')
+#SrcRemove(src, 'delay.c')
+
+if rtconfig.DEVICE_SERIES == 'SAMD20':
+	path += [cwd + '/../asflib_config', cwd + '/../asflib_config/clock_samd20']
+elif rtconfig.DEVICE_SERIES == 'SAMD21':
+	path += [cwd + '/../asflib_config', cwd + '/../asflib_config/clock_samd21_r21_da_ha1']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/samd21/board/board.c b/bsp/samd21/board/board.c
new file mode 100644
index 0000000000..282a179281
--- /dev/null
+++ b/bsp/samd21/board/board.c
@@ -0,0 +1,102 @@
+#include "board.h"
+#include <clock.h>
+#include <gclk.h>
+#include <system.h>
+#include <rtthread.h>
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_tick_increase();
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+}
+
+void configure_extosc32k(void);
+void configure_dfll_open_loop(void);
+
+//! [setup]
+//! [config_extosc32k]
+void configure_extosc32k(void)
+{
+//! [config_extosc32k_config]
+	struct system_clock_source_xosc32k_config config_ext32k;
+//! [config_extosc32k_config]
+//! [config_extosc32k_get_defaults]
+	system_clock_source_xosc32k_get_config_defaults(&config_ext32k);
+//! [config_extosc32k_get_defaults]
+
+//! [config_extosc32k_change_defaults]
+	config_ext32k.startup_time = SYSTEM_XOSC32K_STARTUP_4096;
+    config_ext32k.on_demand = false;
+//! [config_extosc32k_change_defaults]
+
+//! [config_extosc32k_set_config]
+	system_clock_source_xosc32k_set_config(&config_ext32k);
+//! [config_extosc32k_set_config]
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+}
+//! [config_extosc32k]
+
+#if (!SAMC21)
+//! [config_dfll]
+void configure_dfll_open_loop(void)
+{
+//! [config_dfll_config]
+	struct system_clock_source_dfll_config config_dfll;
+//! [config_dfll_config]
+//! [config_dfll_get_defaults]
+	system_clock_source_dfll_get_config_defaults(&config_dfll);
+//! [config_dfll_get_defaults]
+	config_dfll.coarse_value    = (*((uint8_t*)(0x806020 + 7))) >> 2;// 0x1f / 4; /* Midpoint */
+	config_dfll.fine_value      = (*((uint32_t*)(0x806020 + 8))) & 0x3FF;//0xff / 4; /* Midpoint */
+//! [config_dfll_set_config]
+	system_clock_source_dfll_set_config(&config_dfll);
+//! [config_dfll_set_config]
+
+//! [enable_dfll_main]
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+	// while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+
+//! [enable_dfll_main]
+	/* Configure flash wait states before switching to high frequency clock */
+//! [set_sys_wait_states]
+	system_flash_set_waitstates(2);
+//! [set_sys_wait_states]
+
+	/* Change system clock to DFLL */
+//! [set_sys_clk_src]
+	struct system_gclk_gen_config config_gclock_gen;
+	system_gclk_gen_get_config_defaults(&config_gclock_gen);
+	config_gclock_gen.source_clock    = SYSTEM_CLOCK_SOURCE_DFLL;
+	config_gclock_gen.division_factor = 1;
+	system_gclk_gen_set_config(GCLK_GENERATOR_0, &config_gclock_gen);
+//! [set_sys_clk_src]
+}
+//! [config_dfll]
+#endif
+
+void rt_board_init(void)
+{
+    extern void uart_init(void);
+
+    // configure_extosc32k();
+
+    // configure_dfll_open_loop();
+	system_init();
+
+	/* initialize systick */
+	SystemCoreClock = system_gclk_gen_get_hz(0);
+	SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+    uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
diff --git a/bsp/samd21/board/board.h b/bsp/samd21/board/board.h
new file mode 100644
index 0000000000..0f964a7b3e
--- /dev/null
+++ b/bsp/samd21/board/board.h
@@ -0,0 +1,36 @@
+/* This is a template file for board configuration created by MCUXpresso Project Generator. Enjoy! */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#include <stdint.h>
+#include "samd21.h"
+#include "system_samd21.h"
+#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
+
+/* The board name */
+#define BOARD_NAME "###-not-specified-###"
+
+#define CHIP_SRAM_END   (0x20000000 + 32*1024)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief initialize debug console to enable printf for this demo/example
+ */
+void rt_board_init(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/bsp/samd21/board/sleep_timer.c b/bsp/samd21/board/sleep_timer.c
new file mode 100644
index 0000000000..a676d5bc85
--- /dev/null
+++ b/bsp/samd21/board/sleep_timer.c
@@ -0,0 +1,126 @@
+// From module: RTC - Real Time Counter in Count Mode (Polled APIs)
+#include <rtc_count.h>
+#include <rtc_count_interrupt.h>
+// #include <rtc_tamper.h>
+#include <power.h>
+#include <port.h>
+
+#include <rtthread.h>
+
+/* RTC module instance */
+static struct rtc_module rtc_instance;
+
+static void _rtc_timer_int_cb(void)
+{
+	port_pin_toggle_output_level(PIN_PB30);
+}
+
+/* Init RTC as ADC sample timer */
+static void _rtc_timer_init(void)
+{
+	struct rtc_count_config conf;
+
+	rtc_count_get_config_defaults(&conf);
+
+	conf.prescaler         = RTC_COUNT_PRESCALER_DIV_1;
+	conf.mode              = RTC_COUNT_MODE_32BIT;
+	conf.clear_on_match    = false;
+	conf.compare_values[0] = 0;
+
+	// struct rtc_count_events evconfig;
+	// evconfig.generate_event_on_compare[0] = true;
+
+	rtc_count_init(&rtc_instance, RTC, &conf);
+	// rtc_count_enable_events(&rtc_instance, &evconfig);
+    // rtc_count_enable(&rtc_instance);
+	rtc_count_set_count(&rtc_instance, 0);
+	rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
+	// rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
+}
+
+static void _rtc_timer_start(uint32_t ms)
+{
+	uint32_t compare = 0;
+
+	compare = (uint32_t)(32.768 * ms);
+
+	// rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
+	rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
+
+	rtc_count_set_count(&rtc_instance, 0);
+	rtc_count_set_compare(&rtc_instance, compare, RTC_COUNT_COMPARE_0);
+	rtc_count_enable(&rtc_instance);
+}
+
+static void sleep_tick_adjust(uint32_t ms)
+{
+	uint32_t diff;
+
+	diff = rt_tick_from_millisecond(ms);
+
+	rt_tick_set(rt_tick_get() + diff);
+	{
+		struct rt_thread *thread;
+
+		/* check time slice */
+		thread = rt_thread_self();
+
+		if (thread->remaining_tick <= diff)
+		{
+			/* change to initialized tick */
+			thread->remaining_tick = thread->init_tick;
+
+			/* yield */
+			rt_thread_yield();
+		}
+		else
+		{
+			thread->remaining_tick -= diff;
+		}
+
+		/* check timer */
+		rt_timer_check();
+	}
+}
+
+static void _sleep_entry(void)
+{
+	rt_tick_t timeout;
+	rt_uint32_t ms;
+	rt_uint32_t count;
+
+	system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY);
+	timeout = rt_timer_next_timeout_tick() - rt_tick_get();
+
+	ms = timeout * (1000 / RT_TICK_PER_SECOND);
+	rt_kprintf("os tick:%u entry sleep:%u tick\r\n", rt_tick_get(), timeout);
+
+	_rtc_timer_start(ms);
+
+	system_sleep();
+
+	rt_enter_critical();
+	count = rtc_count_get_count(&rtc_instance);
+	ms = (count + 32) / 32.768;
+	rtc_count_disable(&rtc_instance);
+	sleep_tick_adjust(ms);
+	timeout = rt_tick_get();
+	rt_exit_critical();
+	rt_kprintf("sleep exited, os tick:%u\n", timeout);
+}
+
+void sleep_timer_init(void)
+{
+	_rtc_timer_init();
+	rt_thread_idle_sethook(_sleep_entry);
+}
+
+void sleep_timer_start(uint32_t ms)
+{
+	_rtc_timer_start(ms);
+}
+
+void sleep_timer_stop(void)
+{
+	rtc_count_disable(&rtc_instance);
+}
diff --git a/bsp/samd21/board/sleep_timer.h b/bsp/samd21/board/sleep_timer.h
new file mode 100644
index 0000000000..1689bc2679
--- /dev/null
+++ b/bsp/samd21/board/sleep_timer.h
@@ -0,0 +1,8 @@
+#ifndef _SLEEP_TIMER_H_
+#define _SLEEP_TIMER_H_
+
+void sleep_timer_init(void);
+
+void sleep_timer_start(uint32_t ms);
+
+#endif
diff --git a/bsp/samd21/board/uart.c b/bsp/samd21/board/uart.c
new file mode 100644
index 0000000000..3d3294cb64
--- /dev/null
+++ b/bsp/samd21/board/uart.c
@@ -0,0 +1,321 @@
+// From module: SERCOM Callback API
+#include <samd21.h>
+#include <sercom.h>
+// #include <sercom_interrupt.h>
+
+// From module: SERCOM USART - Serial Communications (Callback APIs)
+#include <usart.h>
+// #include <usart_interrupt.h>
+
+#include <rtdevice.h>
+
+typedef struct _samd2x_uart_t
+{
+    struct rt_serial_device *serial;
+    struct usart_module *instance;
+    Sercom *com;
+    enum usart_signal_mux_settings mux_setting;
+    uint32_t pinmux_pad0;
+    uint32_t pinmux_pad1;
+    uint32_t pinmux_pad2;
+    uint32_t pinmux_pad3;
+    enum system_interrupt_vector vector;
+} SAMD2x_UART_T;
+
+static struct rt_serial_device _serial3;
+static struct usart_module _uart3_instance;
+static SAMD2x_UART_T _uart3 = {
+    &_serial3,
+    &_uart3_instance,
+    SERCOM3,
+    USART_RX_1_TX_0_XCK_1,
+    PINMUX_PA22C_SERCOM3_PAD0,
+    PINMUX_PA23C_SERCOM3_PAD1,
+    PINMUX_UNUSED,
+    PINMUX_UNUSED,
+    SYSTEM_INTERRUPT_MODULE_SERCOM3
+};
+
+// static struct rt_serial_device _serial2;
+// static struct rt_serial_device _serial3;
+// static struct rt_serial_device _serial4;
+
+static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    SAMD2x_UART_T *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = (SAMD2x_UART_T *)serial->parent.user_data;
+    //! [setup_config]
+	struct usart_config config_usart;
+    //! [setup_config]
+    //! [setup_config_defaults]
+    usart_get_config_defaults(&config_usart);
+    //! [setup_config_defaults]
+    config_usart.baudrate = cfg->baud_rate;
+
+    switch (cfg->data_bits )
+    {
+    case DATA_BITS_8:
+        config_usart.character_size = USART_CHARACTER_SIZE_8BIT;
+        break;
+
+    case DATA_BITS_5:
+        config_usart.character_size = USART_CHARACTER_SIZE_5BIT;
+        break;
+
+    case DATA_BITS_6:
+        config_usart.character_size = USART_CHARACTER_SIZE_6BIT;
+        break;
+
+    case DATA_BITS_7:
+        config_usart.character_size = USART_CHARACTER_SIZE_7BIT;
+        break;
+
+    case DATA_BITS_9:
+        config_usart.character_size = USART_CHARACTER_SIZE_9BIT;
+        break;
+
+    default:
+        config_usart.character_size = USART_CHARACTER_SIZE_8BIT;
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        config_usart.parity = USART_PARITY_NONE;
+        break;
+
+    case PARITY_EVEN:
+        config_usart.parity = USART_PARITY_EVEN;
+        break;
+
+    case PARITY_ODD:
+        config_usart.parity = USART_PARITY_ODD;
+        break;
+
+    default:
+        config_usart.parity = USART_PARITY_NONE;
+        break;
+    }
+
+    config_usart.stopbits = USART_STOPBITS_1;
+    if (cfg->stop_bits != USART_STOPBITS_1)
+    {
+        config_usart.stopbits = USART_STOPBITS_2;
+    }
+
+    config_usart.data_order = USART_DATAORDER_LSB;
+    if (cfg->bit_order != BIT_ORDER_LSB)
+    {
+        config_usart.data_order = USART_DATAORDER_MSB;
+    }
+
+    config_usart.mux_setting = uart->mux_setting;
+    config_usart.pinmux_pad0 = uart->pinmux_pad0;
+    config_usart.pinmux_pad1 = uart->pinmux_pad1;
+    config_usart.pinmux_pad2 = uart->pinmux_pad2;
+    config_usart.pinmux_pad3 = uart->pinmux_pad3;
+    config_usart.receiver_enable = false;
+    config_usart.transmitter_enable = true;
+
+    while (usart_init(uart->instance, uart->com, &config_usart) != STATUS_OK) {
+    }
+
+    usart_enable(uart->instance);
+    /* Wait for the synchronization to complete */
+    _usart_wait_for_sync(uart->instance);
+
+    return RT_EOK;
+}
+
+static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    SAMD2x_UART_T *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (SAMD2x_UART_T *)(serial->parent.user_data);
+
+    switch (cmd)
+    {
+        /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        uart->com->USART.INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+        usart_disable_transceiver(uart->instance, USART_TRANSCEIVER_RX);
+        system_interrupt_disable(uart->vector);
+        /* Wait for the synchronization to complete */
+	    _usart_wait_for_sync(uart->instance);
+        break;
+        /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        /* Enable RX interrupt. */
+        /* Enable the RX Complete Interrupt */
+        uart->com->USART.INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+        usart_enable_transceiver(uart->instance, USART_TRANSCEIVER_RX);
+        system_interrupt_enable(uart->vector);
+        /* Wait for the synchronization to complete */
+	    _usart_wait_for_sync(uart->instance);
+        break;
+
+    default:
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static int _uart_putc(struct rt_serial_device *serial, char c)
+{
+    SAMD2x_UART_T *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    // while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+    // }
+
+    uart = (SAMD2x_UART_T *)(serial->parent.user_data);
+
+	/* Write data to USART module */
+	uart->com->USART.DATA.reg = c;
+
+	while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+		/* Wait until data is sent */
+    }
+
+    return 1;
+}
+
+static int _uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    SAMD2x_UART_T *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (SAMD2x_UART_T *)(serial->parent.user_data);
+
+    /* Check if USART has new data */
+	if (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+		/* Return error code */
+		return -1;
+    }
+
+    ch = uart->com->USART.DATA.reg & 0x1FF;
+
+    return ch;
+}
+
+static struct rt_uart_ops _uart_ops = {
+    _uart_cfg,
+    _uart_ctrl,
+    _uart_putc,
+    _uart_getc
+};
+
+static void uart_int_cb(SAMD2x_UART_T *uart_handle)
+{
+    /* Temporary variables */
+	uint16_t interrupt_status;
+	uint8_t error_code;
+    struct usart_module *module = uart_handle->instance;
+	/* Pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Read and mask interrupt flag register */
+	interrupt_status = usart_hw->INTFLAG.reg;
+	interrupt_status &= usart_hw->INTENSET.reg;
+
+	/* Check if the Receive Complete interrupt has occurred, and that
+	 * there's more data to receive */
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+        /* Read out the status code and mask away all but the 4 LSBs*/
+        error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+#if !SAMD20
+        /* CTS status should not be considered as an error */
+        if(error_code & SERCOM_USART_STATUS_CTS) {
+            error_code &= ~SERCOM_USART_STATUS_CTS;
+        }
+#endif
+#ifdef FEATURE_USART_LIN_MASTER
+        /* TXE status should not be considered as an error */
+        if(error_code & SERCOM_USART_STATUS_TXE) {
+            error_code &= ~SERCOM_USART_STATUS_TXE;
+        }
+#endif
+        /* Check if an error has occurred during the receiving */
+        if (error_code) {
+            /* Check which error occurred */
+            if (error_code & SERCOM_USART_STATUS_FERR) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+            } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+            } else if (error_code & SERCOM_USART_STATUS_PERR) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+            }
+#ifdef FEATURE_USART_LIN_SLAVE
+            else if (error_code & SERCOM_USART_STATUS_ISF) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+            }
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+            else if (error_code & SERCOM_USART_STATUS_COLL) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+            }
+#endif
+        } else {
+            rt_hw_serial_isr(uart_handle->serial, RT_SERIAL_EVENT_RX_IND);
+        }
+	}
+
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+	}
+#endif
+}
+
+void SERCOM3_Handler(void)
+{
+    uart_int_cb(&_uart3);
+}
+
+void uart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    config.bufsz = 512;
+    _serial3.config = config;
+    _serial3.ops = &_uart_ops;
+
+    rt_hw_serial_register(&_serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_uart3);
+}
diff --git a/bsp/samd21/project.uvprojx b/bsp/samd21/project.uvprojx
new file mode 100644
index 0000000000..cb71018e08
--- /dev/null
+++ b/bsp/samd21/project.uvprojx
@@ -0,0 +1,634 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>RT-Thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ATSAMD21J18A</Device>
+          <Vendor>Atmel</Vendor>
+          <PackID>Keil.SAMD21_DFP.1.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ATSAMD21_256 -FS00 -FL040000 -FP0($$Device:ATSAMD21J18A$Flash\ATSAMD21_256.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ATSAMD21J18A$Device\SAMD21\Include\samd21.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ATSAMD21J18A$SVD\SAMD21\ATSAMD21J18A.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>RT-Thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>__SAMD21J18A__, DEBUG, EXTINT_CALLBACK_MODE=true, RTC_COUNT_ASYNC=true, USART_CALLBACK_MODE=false</Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;.;board;asflib_config;asflib_config\clock_samd21_r21_da_ha1;sam_d2x_asflib\CMSIS\Include;sam_d2x_asflib\common\utils;sam_d2x_asflib\common\utils\interrupt;sam_d2x_asflib\common\boards;sam_d2x_asflib\common2\services\delay;sam_d2x_asflib\common2\services\delay\sam0;sam_d2x_asflib\sam0;sam_d2x_asflib\sam0\utils;sam_d2x_asflib\sam0\utils\preprocessor;sam_d2x_asflib\sam0\utils\header_files;sam_d2x_asflib\sam0\utils\cmsis\samd21\include;sam_d2x_asflib\sam0\utils\cmsis\samd21\source;sam_d2x_asflib\sam0\drivers\system;sam_d2x_asflib\sam0\drivers\system\pinmux;sam_d2x_asflib\sam0\drivers\system\power\power_sam_d_r_h;sam_d2x_asflib\sam0\drivers\system\reset\reset_sam_d_r_h;sam_d2x_asflib\sam0\drivers\system\clock;sam_d2x_asflib\sam0\drivers\system\interrupt;sam_d2x_asflib\sam0\drivers\system\interrupt\system_interrupt_samd21;sam_d2x_asflib\sam0\drivers\system\clock\clock_samd21_r21_da_ha1;sam_d2x_asflib\sam0\drivers\sercom;sam_d2x_asflib\sam0\drivers\sercom\usart;sam_d2x_asflib\sam0\drivers\port;sam_d2x_asflib\sam0\drivers\rtc;sam_d2x_asflib\sam0\drivers\extint;sam_d2x_asflib\sam0\drivers\extint\extint_sam_d_r_h;..\..\include;..\..\libcpu\arm\cortex-m0;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Application</GroupName>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\application.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\startup.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Board</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>sleep_timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\sleep_timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>interrupt_sam_nvic.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\common\utils\interrupt\interrupt_sam_nvic.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_samd21.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\utils\cmsis\samd21\source\system_samd21.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_SAMD21.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>sam_d2x_asflib\sam0\utils\cmsis\samd21\source\arm\startup_SAMD21.s</FilePath>
+            </File>
+            <File>
+              <FileName>system.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\system\system.c</FilePath>
+            </File>
+            <File>
+              <FileName>pinmux.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\system\pinmux\pinmux.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_interrupt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\system\interrupt\system_interrupt.c</FilePath>
+            </File>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>gclk.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\gclk.c</FilePath>
+            </File>
+            <File>
+              <FileName>sercom.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\sercom\sercom.c</FilePath>
+            </File>
+            <File>
+              <FileName>usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\sercom\usart\usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>port.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\port\port.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtc_count.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\rtc\rtc_sam_d_r_h\rtc_count.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtc_count_interrupt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\rtc\rtc_sam_d_r_h\rtc_count_interrupt.c</FilePath>
+            </File>
+            <File>
+              <FileName>extint_callback.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\extint\extint_callback.c</FilePath>
+            </File>
+            <File>
+              <FileName>extint.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>sam_d2x_asflib\sam0\drivers\extint\extint_sam_d_r_h\extint.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>src_clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORTEX-M0</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>portal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\portal.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>
diff --git a/bsp/samd21/rtconfig.h b/bsp/samd21/rtconfig.h
new file mode 100644
index 0000000000..1ccf6616a0
--- /dev/null
+++ b/bsp/samd21/rtconfig.h
@@ -0,0 +1,94 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	   6
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	8
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	200
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+//#define RT_DEBUG_INIT 1
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+#define IDLE_THREAD_STACK_SIZE	512
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	100
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+/* #define RT_USING_MAILBOX */
+
+/* Using Message Queue */
+/* #define RT_USING_MESSAGEQUEUE */
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+/* #define RT_USING_MEMPOOL */
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+#define RT_USING_TINY_SIZE
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+//#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
+#define RT_USING_SERIAL
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	    "uart3"
+
+// #define RT_USING_SPI
+
+/* SECTION: finsh, a C-Express shell */
+// #define RT_USING_FINSH
+/* configure finsh parameters */
+#define FINSH_THREAD_PRIORITY 6
+#define FINSH_THREAD_STACK_SIZE	512
+#define FINSH_HISTORY_LINES	1
+/* Using symbol table */
+// #define FINSH_USING_SYMTAB
+// #define FINSH_USING_DESCRIPTION
+
+// #define FINSH_USING_MSH
+// #define FINSH_USING_MSH_ONLY
+
+#endif
diff --git a/bsp/samd21/rtconfig.py b/bsp/samd21/rtconfig.py
new file mode 100644
index 0000000000..edd1d7358d
--- /dev/null
+++ b/bsp/samd21/rtconfig.py
@@ -0,0 +1,88 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+#DEVICE_SERIES = 'SAMD20'
+DEVICE_SERIES = 'SAMD21'
+#DEVICE_TYPE = '__SAMD20G18A__'
+DEVICE_TYPE = '__SAMD21J18A__'
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'C:/Keil'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m0+ -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-MKL15Z128.map,-cref,-u,Reset_Handler -T MKL15Z128_FLASH.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-SAM_D2x.map --strict --scatter SAM_D2X_RTT.sct'
+
+    CFLAGS += ' --c99'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_common_tables.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000..76aadca490
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_const_structs.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000000..217f1d50e2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_math.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000..f06a0713eb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_math.h
@@ -0,0 +1,7538 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvproj
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000..5186cb4838
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0.h
@@ -0,0 +1,711 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0plus.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000..17e43984fc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,822 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm3.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000..e1357c6735
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1650 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm4.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000..bb6be1305d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1802 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm7.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm7.h
new file mode 100644
index 0000000000..e21e9e29fc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2221 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     01. September 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x07)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x07)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[1];
+  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
+  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
+  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
+  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+       uint32_t RESERVED3[93];
+  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
+       uint32_t RESERVED4[15];
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
+       uint32_t RESERVED5[1];
+  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
+       uint32_t RESERVED6[1];
+  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
+  __O  uint32_t DCIMVAU;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
+  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
+  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
+  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
+  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
+  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
+  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
+       uint32_t RESERVED7[6];
+  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
+  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
+  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
+  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
+  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
+       uint32_t RESERVED8[1];
+  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL << SCB_CTR_IMINLINE_Pos)                /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL << SCB_CCSIDR_LINESIZE_Pos)               /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos                0                                             /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (1UL << SCB_CSSELR_LEVEL_Pos)                    /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL << SCB_CSSELR_IND_Pos)                    /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL << SCB_STIR_INTID_Pos)                /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (0x1UL << SCB_ITCMCR_RETEN_Pos)                /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (0x1UL << SCB_ITCMCR_RMW_Pos)                  /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (0x1UL << SCB_ITCMCR_EN_Pos)                   /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL << SCB_DTCMCR_EN_Pos)                     /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL << SCB_AHBPCR_EN_Pos)                     /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL << SCB_CACR_SIWT_Pos)                     /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL << SCB_AHBPCR_CTL_Pos)                    /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL << SCB_ABFSR_ITCM_Pos)                    /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+       uint32_t RESERVED3[981];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)]            = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]            >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  Cache functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_CacheFunctions Cache Functions
+    \brief      Functions that configure Instruction and Data cache.
+    @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) >> SCB_CCSIDR_LINESIZE_Pos     )
+
+
+/** \brief Enable I-Cache
+
+    The function turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    SCB->CCR |=  SCB_CCR_IC_Msk;            // enable I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable I-Cache
+
+    The function turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~SCB_CCR_IC_Msk;            // disable I-Cache
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+    The function invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Enable D-Cache
+
+    The function turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  SCB_CCR_DC_Msk;            // enable D-Cache
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable D-Cache
+
+    The function turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    SCB->CCR &= ~SCB_CCR_DC_Msk;            // disable D-Cache
+
+    do {                                    // clean & invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+    The function invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Clean D-Cache
+
+    The function cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCSW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+    The function cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean & invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmFunc.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000..01089f1333
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmInstr.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000..2e3bb0eabb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300))
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmSimd.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 0000000000..ee58eee56d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc000.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000..5d0219c89f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc000.h
@@ -0,0 +1,842 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc300.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000..b6f6e8b5f2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1630 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/samd21/sam_d2x_asflib/SConscript b/bsp/samd21/sam_d2x_asflib/SConscript
new file mode 100644
index 0000000000..7561fea0fe
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/SConscript
@@ -0,0 +1,92 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+#var defined
+CPPDEFINES = []
+src = []
+path = []
+
+#common lib define
+CPPDEFINES += [rtconfig.DEVICE_TYPE, 'DEBUG']
+
+#CMSIS/Include/ common/ common2/service/delay 
+path += [cwd + '/CMSIS/Include/']
+path += [cwd + '/common/utils/', cwd + '/common/utils/interrupt/']
+path += [cwd + '/common/boards/']
+path += [cwd + '/common2/services/delay/', cwd + '/common2/services/delay/sam0/']
+src += Glob('./common/utils/interrupt/interrupt_sam_nvic.c')
+
+#sam0/ sam0/utils/
+path += [cwd + '/sam0/', cwd + '/sam0/utils/']
+path += [cwd + '/sam0/utils/preprocessor']
+path += [cwd + '/sam0/utils/header_files']
+
+#sam0/utils/cmsis/
+if rtconfig.DEVICE_SERIES == 'SAMD20':
+	#D20
+	path += [cwd + '/sam0/', cwd + '/sam0/utils/cmsis/samd20/include/']
+	path += [cwd + '/sam0/utils/cmsis/samd20/source/']
+	src	+= Glob('./sam0/utils/cmsis/samd20/source/*.c')
+	src += Glob('./sam0/utils/cmsis/samd20/source/arm/*.s')
+elif rtconfig.DEVICE_SERIES == 'SAMD21':
+	#D21
+	path += [cwd + '/sam0/utils/cmsis/samd21/include/']
+	path += [cwd + '/sam0/utils/cmsis/samd21/source/']
+	src	+= Glob('./sam0/utils/cmsis/samd21/source/*.c')
+	src += Glob('./sam0/utils/cmsis/samd21/source/arm/*.s')
+
+#sam0/drivers/system
+path += [cwd + '/sam0/drivers/system/']
+src += Glob('./sam0/drivers/system/system.c')
+path += [cwd + '/sam0/drivers/system/pinmux']
+src += Glob('./sam0/drivers/system/pinmux/*.c')
+path += [cwd + '/sam0/drivers/system/power/power_sam_d_r_h']
+path += [cwd + '/sam0/drivers/system/reset/reset_sam_d_r_h']
+path += [cwd + '/sam0/drivers/system/clock']
+path += [cwd + '/sam0/drivers/system/interrupt/']
+src += Glob('./sam0/drivers/system/interrupt/*.c')
+if rtconfig.DEVICE_SERIES == 'SAMD20':
+	path += [cwd + '/sam0/drivers/system/interrupt/system_interrupt_samd20/']
+elif rtconfig.DEVICE_SERIES == 'SAMD21':
+	path += [cwd + '/sam0/drivers/system/interrupt/system_interrupt_samd21/']
+
+#sam0/drivers/system/clock
+if rtconfig.DEVICE_SERIES == 'SAMD20':
+	path += [cwd + '/sam0/drivers/system/clock/clock_samd20']
+	#path += [cwd + '/sam0/drivers/system/clock/clock_samd20/module_config']
+	src += Glob('./sam0/drivers/system/clock/clock_samd20/*.c')
+elif rtconfig.DEVICE_SERIES == 'SAMD21':
+	#path += [cwd + '/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/module_config']
+	path += [cwd + '/sam0/drivers/system/clock/clock_samd21_r21_da_ha1']
+	src += Glob('./sam0/drivers/system/clock/clock_samd21_r21_da_ha1/*.c')
+
+#sam0/drivers/sercom
+path += [cwd + '/sam0/drivers/sercom', cwd + '/sam0/drivers/sercom/usart']
+src += Glob('./sam0/drivers/sercom/*.c')
+src += Glob('./sam0/drivers/sercom/usart/*.c')
+SrcRemove(src, 'sercom_interrupt.c')
+SrcRemove(src, 'usart_interrupt.c')
+CPPDEFINES += ['USART_CALLBACK_MODE=false']
+
+#sam0/drivers/port
+path += [cwd + '/sam0/drivers/port']
+src += Glob('./sam0/drivers/port/port.c')
+
+#sam0/drivers/rtc
+path += [cwd + '/sam0/drivers/rtc']
+src += Glob('./sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count*.c')
+CPPDEFINES += ['RTC_COUNT_ASYNC=true']
+
+#sam0/drivers/extint
+path += [cwd + '/sam0/drivers/extint', cwd + '/sam0/drivers/extint/extint_sam_d_r_h']
+src += Glob('./sam0/drivers/extint/extint_callback.c')
+src += Glob('./sam0/drivers/extint/extint_sam_d_r_h/extint.c')
+CPPDEFINES += ['EXTINT_CALLBACK_MODE=true']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/board.h b/bsp/samd21/sam_d2x_asflib/common/boards/board.h
new file mode 100644
index 0000000000..0dc09cd1b6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/board.h
@@ -0,0 +1,448 @@
+/**
+ * \file
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board (parameter BOARD).
+ *
+ * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * \defgroup group_common_boards Generic board support
+ *
+ * The generic board support module includes board-specific definitions
+ * and function prototypes, such as the board initialization function.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100                     1  //!< AT32UC3A EVK1100 board.
+#define EVK1101                     2  //!< AT32UC3B EVK1101 board.
+#define UC3C_EK                     3  //!< AT32UC3C UC3C-EK board.
+#define EVK1104                     4  //!< AT32UC3A3 EVK1104 board.
+#define EVK1105                     5  //!< AT32UC3A EVK1105 board.
+#define STK600_RCUC3L0              6  //!< STK600 RCUC3L0 board.
+#define UC3L_EK                     7  //!< AT32UC3L-EK board.
+#define XPLAIN                      8  //!< ATxmega128A1 Xplain board.
+#define STK600_RC064X              10  //!< ATxmega256A3 STK600 board.
+#define STK600_RC100X              11  //!< ATxmega128A1 STK600 board.
+#define UC3_A3_XPLAINED            13  //!< ATUC3A3 UC3-A3 Xplained board.
+#define UC3_L0_XPLAINED            15  //!< ATUC3L0 UC3-L0 Xplained board.
+#define STK600_RCUC3D              16  //!< STK600 RCUC3D board.
+#define STK600_RCUC3C0             17  //!< STK600 RCUC3C board.
+#define XMEGA_B1_XPLAINED          18  //!< ATxmega128B1 Xplained board.
+#define XMEGA_A1_XPLAINED          19  //!< ATxmega128A1 Xplain-A1 board.
+#define XMEGA_A1U_XPLAINED_PRO     20  //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
+#define STK600_RCUC3L4             21  //!< ATUCL4 STK600 board.
+#define UC3_L0_XPLAINED_BC         22  //!< ATUC3L0 UC3-L0 Xplained board controller board.
+#define MEGA1284P_XPLAINED_BC      23  //!< ATmega1284P-Xplained board controller board.
+#define STK600_RC044X              24  //!< STK600 with RC044X routing card board.
+#define STK600_RCUC3B0             25  //!< STK600 RCUC3B0 board.
+#define UC3_L0_QT600               26  //!< QT600 UC3L0 MCU board.
+#define XMEGA_A3BU_XPLAINED        27  //!< ATxmega256A3BU Xplained board.
+#define STK600_RC064X_LCDX         28  //!< XMEGAB3 STK600 RC064X LCDX board.
+#define STK600_RC100X_LCDX         29  //!< XMEGAB1 STK600 RC100X LCDX board.
+#define UC3B_BOARD_CONTROLLER      30  //!< AT32UC3B1 board controller for Atmel boards.
+#define RZ600                      31  //!< AT32UC3A RZ600 MCU board.
+#define SAM3S_EK                   32  //!< SAM3S-EK board.
+#define SAM3U_EK                   33  //!< SAM3U-EK board.
+#define SAM3X_EK                   34  //!< SAM3X-EK board.
+#define SAM3N_EK                   35  //!< SAM3N-EK board.
+#define SAM3S_EK2                  36  //!< SAM3S-EK2 board.
+#define SAM4S_EK                   37  //!< SAM4S-EK board.
+#define STK600_RCUC3A0             38  //!< STK600 RCUC3A0 board.
+#define STK600_MEGA                39  //!< STK600 MEGA board.
+#define MEGA_1284P_XPLAINED        40  //!< ATmega1284P Xplained board.
+#define SAM4S_XPLAINED             41  //!< SAM4S Xplained board.
+#define ATXMEGA128A1_QT600         42  //!< QT600 ATXMEGA128A1 MCU board.
+#define ARDUINO_DUE_X              43  //!< Arduino Due/X board.
+#define STK600_RCUC3L3             44  //!< ATUCL3 STK600 board.
+#define SAM4L_EK                   45  //!< SAM4L-EK board.
+#define STK600_MEGA_RF             46  //!< STK600 MEGA RF EVK board.
+#define XMEGA_C3_XPLAINED          47  //!< ATxmega384C3 Xplained board.
+#define STK600_RC032X              48  //!< STK600 with RC032X routing card board.
+#define SAM4S_EK2                  49  //!< SAM4S-EK2 board.
+#define XMEGA_E5_XPLAINED          50  //!< ATxmega32E5 Xplained board.
+#define SAM4E_EK                   51  //!< SAM4E-EK board.
+#define ATMEGA256RFR2_XPLAINED_PRO 52  //!< ATmega256RFR2 Xplained Pro board.
+#define SAM4S_XPLAINED_PRO         53  //!< SAM4S Xplained Pro board.
+#define SAM4L_XPLAINED_PRO         54  //!< SAM4L Xplained Pro board.
+#define ATMEGA256RFR2_ZIGBIT       55  //!< ATmega256RFR2 zigbit.
+#define XMEGA_RF233_ZIGBIT         56  //!< ATxmega256A3U with AT86RF233 Zigbit.
+#define XMEGA_RF212B_ZIGBIT        57  //!< ATxmega256A3U with AT86RF212B Zigbit.
+#define SAM4S_WPIR_RD              58  //!< SAM4S-WPIR-RD board.
+#define SAMD20_XPLAINED_PRO        59  //!< SAM D20 Xplained Pro board.
+#define SAM4L8_XPLAINED_PRO        60  //!< SAM4L8 Xplained Pro board.
+#define SAM4N_XPLAINED_PRO         61  //!< SAM4N Xplained Pro board.
+#define XMEGA_A3_REB_CBB           62  //!< XMEGA REB Controller Base board.
+#define ATMEGARFX_RCB              63  //!< RFR2 & RFA1 RCB.
+#define SAM4C_EK                   64  //!< SAM4C-EK board.
+#define RCB256RFR2_XPRO            65  //!< RFR2 RCB Xplained Pro board.
+#define SAMG53_XPLAINED_PRO        66  //!< SAMG53 Xplained Pro board.
+#define SAM4CP16BMB                67  //!< SAM4CP16BMB board.
+#define SAM4E_XPLAINED_PRO         68  //!< SAM4E Xplained Pro board.
+#define SAMD21_XPLAINED_PRO        69  //!< SAM D21 Xplained Pro board.
+#define SAMR21_XPLAINED_PRO        70  //!< SAM R21 Xplained Pro board.
+#define SAM4CMP_DB                 71  //!< SAM4CMP demo board.
+#define SAM4CMS_DB                 72  //!< SAM4CMS demo board.
+#define ATPL230AMB                 73  //!< ATPL230AMB board.
+#define SAMD11_XPLAINED_PRO        74  //!< SAM D11 Xplained Pro board.
+#define SAMG55_XPLAINED_PRO        75  //!< SAMG55 Xplained Pro board.
+#define SAML21_XPLAINED_PRO        76  //!< SAM L21 Xplained Pro board.
+#define SAMD10_XPLAINED_MINI       77  //!< SAM D10 Xplained Mini board.
+#define SAMDA1_XPLAINED_PRO        78  //!< SAM DA1 Xplained Pro board.
+#define SAMW25_XPLAINED_PRO        79  //!< SAMW25 Xplained Pro board.
+#define SAMC21_XPLAINED_PRO        80  //!< SAM C21 Xplained Pro board.
+#define SAMV71_XPLAINED_ULTRA      81  //!< SAMV71 Xplained Ultra board.
+#define ATMEGA328P_XPLAINED_MINI   82  //!< ATMEGA328P Xplained MINI board.
+#define ATMEGA328PB_XPLAINED_MINI  83  //!< ATMEGA328PB Xplained MINI board.
+#define SAMB11_XPLAINED_PRO        84  //!< SAM B11 Xplained Pro board.
+#define SAME70_XPLAINED            85  //!< SAME70 Xplained board.
+#define SAML22_XPLAINED_PRO        86  //!< SAM L22 Xplained Pro board.
+#define SAML22_XPLAINED_PRO_B      87  //!< SAM L22 Xplained Pro board.
+#define SAMR21ZLL_EK               88  //!< SAMR21ZLL-EK board.
+#define ATMEGA168PB_XPLAINED_MINI  89  //!< ATMEGA168PB Xplained MINI board.
+#define ATMEGA324PB_XPLAINED_PRO   90  //!< ATMEGA324PB Xplained Pro board.
+#define SAMB11CSP_XPLAINED_PRO     91  //!< SAM B11 CSP Xplained Pro board.
+#define SAMB11ZR_XPLAINED_PRO      92  //!< SAM B11 ZR Xplained Pro board.
+#define SAMR30_XPLAINED_PRO        93  //!< SAM R30 Xplained Pro board.
+#define SAMHA1G16A_XPLAINED_PRO    94  //!< SAM HA1G16A Xplained Pro board.
+#define SIMULATOR_XMEGA_A1         97  //!< Simulator for XMEGA A1 devices.
+#define AVR_SIMULATOR_UC3          98  //!< Simulator for the AVR UC3 device family.
+#define USER_BOARD                 99  //!< User-reserved board (if any).
+#define DUMMY_BOARD               100  //!< Dummy board to support board-independent applications (e.g. bootloader).
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102                      1  //!< AT32UC3B EXT1102 board
+#define MC300                        2  //!< AT32UC3 MC300 board
+#define SENSORS_XPLAINED_INERTIAL_1  3  //!< Xplained inertial sensor board 1
+#define SENSORS_XPLAINED_INERTIAL_2  4  //!< Xplained inertial sensor board 2
+#define SENSORS_XPLAINED_PRESSURE_1  5  //!< Xplained pressure sensor board
+#define SENSORS_XPLAINED_LIGHTPROX_1 6  //!< Xplained light & proximity sensor board
+#define SENSORS_XPLAINED_INERTIAL_A1 7  //!< Xplained inertial sensor board "A"
+#define RZ600_AT86RF231              8  //!< AT86RF231 RF board in RZ600
+#define RZ600_AT86RF230B             9  //!< AT86RF230B RF board in RZ600
+#define RZ600_AT86RF212             10  //!< AT86RF212 RF board in RZ600
+#define SENSORS_XPLAINED_BREADBOARD 11  //!< Xplained sensor development breadboard
+#define SECURITY_XPLAINED           12  //!< Xplained ATSHA204 board
+#define USER_EXT_BOARD              99  //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+#  include "evk1100/evk1100.h"
+#elif BOARD == EVK1101
+#  include "evk1101/evk1101.h"
+#elif BOARD == UC3C_EK
+#  include "uc3c_ek/uc3c_ek.h"
+#elif BOARD == EVK1104
+#  include "evk1104/evk1104.h"
+#elif BOARD == EVK1105
+#  include "evk1105/evk1105.h"
+#elif BOARD == STK600_RCUC3L0
+#  include "stk600/rcuc3l0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+#  include "uc3l_ek/uc3l_ek.h"
+#elif BOARD == STK600_RCUC3L4
+#  include "stk600/rcuc3l4/stk600_rcuc3l4.h"
+#elif BOARD == XPLAIN
+#  include "xplain/xplain.h"
+#elif BOARD == STK600_MEGA
+  /*No header-file to include*/
+#elif BOARD == STK600_MEGA_RF
+#  include "stk600.h"
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
+#  include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
+#elif BOARD == ATMEGA256RFR2_ZIGBIT
+#  include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
+#elif BOARD == STK600_RC032X
+#  include "stk600/rc032x/stk600_rc032x.h"
+#elif BOARD == STK600_RC044X
+#  include "stk600/rc044x/stk600_rc044x.h"
+#elif BOARD == STK600_RC064X
+#  include "stk600/rc064x/stk600_rc064x.h"
+#elif BOARD == STK600_RC100X
+#  include "stk600/rc100x/stk600_rc100x.h"
+#elif BOARD == UC3_A3_XPLAINED
+#  include "uc3_a3_xplained/uc3_a3_xplained.h"
+#elif BOARD == UC3_L0_XPLAINED
+#  include "uc3_l0_xplained/uc3_l0_xplained.h"
+#elif BOARD == STK600_RCUC3B0
+#  include "stk600/rcuc3b0/stk600_rcuc3b0.h"
+#elif BOARD == STK600_RCUC3D
+#  include "stk600/rcuc3d/stk600_rcuc3d.h"
+#elif BOARD == STK600_RCUC3C0
+#  include "stk600/rcuc3c0/stk600_rcuc3c0.h"
+#elif BOARD == SAMG53_XPLAINED_PRO
+#  include "samg53_xplained_pro/samg53_xplained_pro.h"
+#elif BOARD == SAMG55_XPLAINED_PRO
+#  include "samg55_xplained_pro/samg55_xplained_pro.h"
+#elif BOARD == XMEGA_B1_XPLAINED
+#  include "xmega_b1_xplained/xmega_b1_xplained.h"
+#elif BOARD == STK600_RC064X_LCDX
+#  include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
+#elif BOARD == STK600_RC100X_LCDX
+#  include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
+#elif BOARD == XMEGA_A1_XPLAINED
+#  include "xmega_a1_xplained/xmega_a1_xplained.h"
+#elif BOARD == XMEGA_A1U_XPLAINED_PRO
+#  include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
+#elif BOARD == UC3_L0_XPLAINED_BC
+#  include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
+#elif BOARD == SAM3S_EK
+#  include "sam3s_ek/sam3s_ek.h"
+#  include "system_sam3s.h"
+#elif BOARD == SAM3S_EK2
+#  include "sam3s_ek2/sam3s_ek2.h"
+#  include "system_sam3sd8.h"
+#elif BOARD == SAM3U_EK
+#  include "sam3u_ek/sam3u_ek.h"
+#  include "system_sam3u.h"
+#elif BOARD == SAM3X_EK
+#  include "sam3x_ek/sam3x_ek.h"
+#  include "system_sam3x.h"
+#elif BOARD == SAM3N_EK
+#  include "sam3n_ek/sam3n_ek.h"
+#  include "system_sam3n.h"
+#elif BOARD == SAM4S_EK
+#  include "sam4s_ek/sam4s_ek.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_WPIR_RD
+#  include "sam4s_wpir_rd/sam4s_wpir_rd.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_XPLAINED
+#  include "sam4s_xplained/sam4s_xplained.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_EK2
+#  include "sam4s_ek2/sam4s_ek2.h"
+#  include "system_sam4s.h"
+#elif BOARD == MEGA_1284P_XPLAINED
+  /*No header-file to include*/
+#elif BOARD == ARDUINO_DUE_X
+#  include "arduino_due_x/arduino_due_x.h"
+#  include "system_sam3x.h"
+#elif BOARD == SAM4L_EK
+#  include "sam4l_ek/sam4l_ek.h"
+#elif BOARD == SAM4E_EK
+#  include "sam4e_ek/sam4e_ek.h"
+#elif BOARD == SAMD20_XPLAINED_PRO
+#  include "samd20_xplained_pro/samd20_xplained_pro.h"
+#elif BOARD == SAMD21_XPLAINED_PRO
+#  include "samd21_xplained_pro/samd21_xplained_pro.h"
+#elif BOARD == SAMR21_XPLAINED_PRO
+#  include "samr21_xplained_pro/samr21_xplained_pro.h"
+#elif BOARD == SAMR30_XPLAINED_PRO
+#  include "samr30_xplained_pro/samr30_xplained_pro.h"
+#elif BOARD == SAMR21ZLL_EK
+#  include "samr21zll_ek/samr21zll_ek.h"
+#elif BOARD == SAMD11_XPLAINED_PRO
+#  include "samd11_xplained_pro/samd11_xplained_pro.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
+#  include "saml21_xplained_pro/saml21_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO
+#  include "saml22_xplained_pro/saml22_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO_B
+#  include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
+#  include "saml21_xplained_pro_b/saml21_xplained_pro.h"
+#elif BOARD == SAMD10_XPLAINED_MINI
+#  include "samd10_xplained_mini/samd10_xplained_mini.h"
+#elif BOARD == SAMDA1_XPLAINED_PRO
+#  include "samda1_xplained_pro/samda1_xplained_pro.h"
+#elif BOARD == SAMHA1G16A_XPLAINED_PRO
+#  include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
+#elif BOARD == SAMC21_XPLAINED_PRO
+#  include "samc21_xplained_pro/samc21_xplained_pro.h"
+#elif BOARD == SAM4N_XPLAINED_PRO
+#  include "sam4n_xplained_pro/sam4n_xplained_pro.h"
+#elif BOARD == SAMW25_XPLAINED_PRO
+#  include "samw25_xplained_pro/samw25_xplained_pro.h"
+#elif BOARD == SAMV71_XPLAINED_ULTRA
+#  include "samv71_xplained_ultra/samv71_xplained_ultra.h"
+#elif BOARD == MEGA1284P_XPLAINED_BC
+#  include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
+#elif BOARD == UC3_L0_QT600
+#  include "uc3_l0_qt600/uc3_l0_qt600.h"
+#elif BOARD == XMEGA_A3BU_XPLAINED
+#  include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
+#elif BOARD == XMEGA_E5_XPLAINED
+#  include "xmega_e5_xplained/xmega_e5_xplained.h"
+#elif BOARD == UC3B_BOARD_CONTROLLER
+#  include "uc3b_board_controller/uc3b_board_controller.h"
+#elif BOARD == RZ600
+#  include "rz600/rz600.h"
+#elif BOARD == STK600_RCUC3A0
+#  include "stk600/rcuc3a0/stk600_rcuc3a0.h"
+#elif BOARD == ATXMEGA128A1_QT600
+#  include "atxmega128a1_qt600/atxmega128a1_qt600.h"
+#elif BOARD == STK600_RCUC3L3
+#  include "stk600/rcuc3l3/stk600_rcuc3l3.h"
+#elif BOARD == SAM4S_XPLAINED_PRO
+#  include "sam4s_xplained_pro/sam4s_xplained_pro.h"
+#elif BOARD == SAM4L_XPLAINED_PRO
+#  include "sam4l_xplained_pro/sam4l_xplained_pro.h"
+#elif BOARD == SAM4L8_XPLAINED_PRO
+#  include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
+#elif BOARD == SAM4C_EK
+#  include "sam4c_ek/sam4c_ek.h"
+#elif BOARD == SAM4CMP_DB
+#  include "sam4cmp_db/sam4cmp_db.h"
+#elif BOARD == SAM4CMS_DB
+#  include "sam4cms_db/sam4cms_db.h"
+#elif BOARD == SAM4CP16BMB
+#  include "sam4cp16bmb/sam4cp16bmb.h"
+#elif BOARD == ATPL230AMB
+#  include "atpl230amb/atpl230amb.h"
+#elif BOARD == XMEGA_C3_XPLAINED
+#  include "xmega_c3_xplained/xmega_c3_xplained.h"
+#elif BOARD == XMEGA_RF233_ZIGBIT
+#  include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
+#elif BOARD == XMEGA_A3_REB_CBB
+#  include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
+#elif BOARD == ATMEGARFX_RCB
+#  include "atmegarfx_rcb/atmegarfx_rcb.h"
+#elif BOARD == RCB256RFR2_XPRO
+#  include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
+#elif BOARD == XMEGA_RF212B_ZIGBIT
+#  include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
+#elif BOARD == SAM4E_XPLAINED_PRO
+#  include "sam4e_xplained_pro/sam4e_xplained_pro.h"
+#elif BOARD == ATMEGA328P_XPLAINED_MINI
+#  include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
+#elif BOARD == ATMEGA328PB_XPLAINED_MINI
+#  include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
+#elif BOARD == SAMB11_XPLAINED_PRO
+#  include "samb11_xplained_pro/samb11_xplained_pro.h"
+#elif BOARD == SAME70_XPLAINED
+#  include "same70_xplained/same70_xplained.h"
+#elif BOARD == ATMEGA168PB_XPLAINED_MINI
+#  include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
+#elif BOARD == ATMEGA324PB_XPLAINED_PRO
+#  include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
+#elif BOARD == SAMB11CSP_XPLAINED_PRO
+#  include "samb11csp_xplained_pro/samb11csp_xplained_pro.h"
+#elif BOARD == SAMB11ZR_XPLAINED_PRO
+#  include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
+#elif BOARD == SIMULATOR_XMEGA_A1
+#  include "simulator/xmega_a1/simulator_xmega_a1.h"
+#elif BOARD == AVR_SIMULATOR_UC3
+#  include "avr_simulator_uc3/avr_simulator_uc3.h"
+#elif BOARD == USER_BOARD
+  // User-reserved area: #include the header file of your board here (if any).
+#  include "user_board.h"
+#elif BOARD == DUMMY_BOARD
+#  include "dummy/dummy_board.h"
+#else
+#  error No known Atmel board defined
+#endif
+
+#if (defined EXT_BOARD)
+#  if EXT_BOARD == MC300
+#    include "mc300/mc300.h"
+#  elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
+        (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
+        (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+#    include "sensors_xplained/sensors_xplained.h"
+#  elif EXT_BOARD == RZ600_AT86RF231
+#     include "at86rf231/at86rf231.h"
+#  elif EXT_BOARD == RZ600_AT86RF230B
+#    include "at86rf230b/at86rf230b.h"
+#  elif EXT_BOARD == RZ600_AT86RF212
+#    include "at86rf212/at86rf212.h"
+#  elif EXT_BOARD == SECURITY_XPLAINED
+#    include "security_xplained.h"
+#  elif EXT_BOARD == USER_EXT_BOARD
+    // User-reserved area: #include the header file of your extension board here
+    // (if any).
+#  endif
+#endif
+
+
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+
+#endif  // #ifdef __AVR32_ABI_COMPILER__
+#else
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \}
+ */
+
+#endif  // _BOARD_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c b/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c
new file mode 100644
index 0000000000..db2b5a6981
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief SECURITY_XPLAINED extension board adaptation.
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#include "security_xplained.h"
+#include "sha204_physical.h"
+#include "conf_atsha204.h"
+
+
+//! TWI address used at SHA204 library startup
+#define SHA204_I2C_DEFAULT_ADDRESS  (0xCA)
+
+
+/** \brief This function initializes peripherals needed to communicate with
+ *         the I2C security devices (ATSHA204 and ATAES132).
+ */
+void security_board_init(void)
+{
+	sha204p_init();
+}
+
+
+/** \brief This function returns the I2C address of a chosen SHA204 device.
+ *  \param[in] index the selected device on the Security Xplained board
+ *  \return I2C address of chosen device
+ */
+uint8_t sha204_i2c_address(uint8_t index)
+{
+	static uint8_t i2c_addresses[SHA204_DEVICE_COUNT] = {SHA204_I2C_DEFAULT_ADDRESS, 0xCC, 0xCE, 0xF8};
+	return i2c_addresses[index % SHA204_DEVICE_COUNT];
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.h b/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.h
new file mode 100644
index 0000000000..3ba88a1fec
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.h
@@ -0,0 +1,63 @@
+/**
+ * \file
+ *
+ * \brief SECURITY_XPLAINED_BOARD board header file.
+ *
+ * This file contains definitions and services related to the features of the
+ * SECURITY_XPLAINED Xplained board.
+ *
+ * To use the board, define EXT_BOARD=SECURITY_XPLAINED.
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SECURITY_XPLAINED_H_
+#   define SECURITY_XPLAINED_H_
+
+#include <compiler.h>
+
+//! number of ATSHA204 I2C devices on Security Xplained extension board
+#define SHA204_DEVICE_COUNT          (4)
+
+void security_board_init(void);
+uint8_t sha204_i2c_address(uint8_t index);
+
+#endif /* SECURITY_XPLAINED_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.c b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.c
new file mode 100644
index 0000000000..08a69693a6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.c
@@ -0,0 +1,435 @@
+/**
+ * \file
+ *
+ * \brief SENSORS_XPLAINED_BOARD extension board adaptation.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include    "sensors_xplained.h"
+#include    <sysclk.h>
+
+#if UC3
+#   include <eic.h>
+#endif
+
+#if UC3
+#   define PIN_OUTPUT_FLAGS         (GPIO_DIR_OUTPUT | GPIO_INIT_HIGH)
+#   define PIN_INPUT_FLAGS          (GPIO_DIR_INPUT)
+#elif XMEGA
+#   define PIN_OUTPUT_FLAGS         (IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH)
+#   define PIN_INPUT_FLAGS          (IOPORT_DIR_INPUT)
+#endif
+
+#if defined(__AVR32__) || defined(__ICCAVR32__)
+#  if !defined(AVR32_GPIO_IRQ_GROUP)
+#   define AVR32_GPIO_IRQ_GROUP     (AVR32_GPIO_IRQ_0 / 32)
+#  endif
+
+#  if  defined(CONFIG_GPIO_INT_LVL)
+#    define GPIO_INT_LVL            CONFIG_GPIO_INT_LVL
+#  else
+#    define GPIO_INT_LVL            0
+#  endif
+
+#  if !defined(AVR32_EIC_IRQ_GROUP)
+#    if UC3L
+#      define AVR32_EIC_IRQ_GROUP   (AVR32_EIC_IRQ_1 / 32)
+#    else
+#      define AVR32_EIC_IRQ_GROUP   (AVR32_EIC_IRQ_0 / 32)
+#    endif
+#  endif
+
+#  if  defined(CONFIG_EIC_INT_LVL)
+#    define EIC_INT_LVL             CONFIG_EIC_INT_LVL
+#  else
+#    define EIC_INT_LVL             0
+#  endif
+#endif /* (__AVR32__) || (__ICCAVR32__) */
+
+/* Don't include interrupt definitions without a valid board configuration. */
+
+#if defined(SENSORS_XPLAINED_BOARD) && defined(COMMON_SENSOR_PLATFORM)
+
+/*! \internal
+ * \name Sensor Board GPIO interrupt handler callback pointers
+ * @{
+ */
+static SENSOR_IRQ_HANDLER sensor_pin3_handler;
+static volatile void *sensor_pin3_arg;
+
+static SENSOR_IRQ_HANDLER sensor_pin4_handler;
+static volatile void *sensor_pin4_arg;
+
+static SENSOR_IRQ_HANDLER sensor_pin5_handler;
+static volatile void *sensor_pin5_arg;
+/*! @} */
+
+#if UC3
+
+/*! \internal Sensor Board GPIO interrupt handler
+ *
+ * This is the default ISR for the Xplained Sensor board GPIO pins.  If
+ * an external interrupt interface is available, the corresponding
+ * eic_pinX_handler will be used instead.
+ *
+ * \return  Nothing.
+ */
+ISR(gpio_irq_handler, AVR32_GPIO_IRQ_GROUP, GPIO_INT_LVL)
+{
+	if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN3)) {
+		sensor_pin3_handler(sensor_pin3_arg);
+
+		gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN3);
+	} else if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN4)) {
+		sensor_pin4_handler(sensor_pin4_arg);
+
+		gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN4);
+	} else if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN5)) {
+		sensor_pin5_handler(sensor_pin5_arg);
+
+		gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN5);
+	}
+}
+
+#elif XMEGA
+
+/*! \internal Sensor Board GPIO interrupt handler
+ *
+ * This is the default ISR for the Xplained Sensor board GPIO pins.  The
+ * installed handler routine for the particular pin will be called with
+ * the argument specified when the handler was installed..
+ *
+ * \return  Nothing.
+ */
+ISR(SENSOR_BOARD_PORT_vect)
+{
+	PORT_t *const port = &(SENSOR_BOARD_PORT);
+
+	/* Call the interrupt handler (if any). */
+	if (sensor_pin3_handler && (port->IN & PIN2_bm)) {
+		/* Note: header pin 3 = io port pin 2 */
+		sensor_pin3_handler(sensor_pin3_arg);
+	} else if (sensor_pin4_handler && (port->IN & PIN3_bm)) {
+		/* Note: header pin 4 = io port pin 3 */
+		sensor_pin4_handler(sensor_pin4_arg);
+	} else if (sensor_pin5_handler && (port->IN & PIN4_bm)) {
+		/* Note: header pin 5 = io port pin 4 */
+		sensor_pin5_handler(sensor_pin5_arg);
+	}
+
+	/* Clear the port interrupt flag */
+	port->INTFLAGS = PORT_INT0IF_bm;
+}
+#endif
+
+#if defined(SENSOR_PIN3_EIC_LINE)
+
+/*! \internal Sensor Board external interrupt handler - PIN3
+ *
+ * This is the ISR for the Xplained Sensor board GPIO PIN3 for configurations
+ * in which it can generate an external interrupt.
+ *
+ * \return  Nothing.
+ */
+ISR(eic_pin3_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
+{
+	sensor_pin3_handler(sensor_pin3_arg);     /* call handler in driver */
+
+	eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN3_EIC_LINE);
+}
+#endif
+
+#if defined(SENSOR_PIN4_EIC_LINE)
+
+/*! \internal Sensor Board external interrupt handler - PIN4
+ *
+ * This is the ISR for the Xplained Sensor board GPIO PIN4 for configurations
+ * in which it can generate an external interrupt.
+ *
+ * \return  Nothing.
+ */
+ISR(eic_pin4_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
+{
+	sensor_pin4_handler(sensor_pin4_arg);     /* call handler in driver */
+
+	eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN4_EIC_LINE);
+}
+#endif
+
+#if defined(SENSOR_PIN5_EIC_LINE)
+
+/*! \internal Sensor Board external interrupt handler - PIN5
+ *
+ * This is the ISR for the Xplained Sensor board GPIO PIN5 for configurations
+ * in which it can generate an external interrupt.
+ *
+ * \return  Nothing.
+ */
+ISR(eic_pin5_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
+{
+	sensor_pin5_handler(sensor_pin5_arg);     /* call handler in driver */
+
+	eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN5_EIC_LINE);
+}
+#endif
+
+#if UC3
+
+/*! \internal Enable a general purpose I/O pin interrupt.
+ *
+ * This routine enables interrupts on a specified general purpose I/O pin.
+ *
+ * \param gpio_pin      GPIO pin interface to the MCU
+ * \param gpio_irq      IRQ of the interrupt handler
+ */
+static void gpio_irq_connect(uint32_t gpio_pin, uint32_t gpio_irq)
+{
+	irq_register_handler(gpio_irq_handler, gpio_irq, GPIO_INT_LVL);
+	gpio_enable_pin_interrupt(gpio_pin, GPIO_RISING_EDGE);
+}
+
+#endif
+
+#if defined(SYSCLK_EIC)
+
+/*! \brief Enable an EIC interrupt line.
+ *
+ * This routine maps a GPIO pin and peripheral function to a specified EIC line.
+ *
+ * \param eic_line      Line number to enable
+ * \param eic_pin       GPIO module pin
+ * \param eic_func      GPIO module function
+ * \param eic_irq       IRQ of the interrupt handler
+ * \param eic_handler   Interrupt handler to register
+ */
+static void eic_irq_connect(uint32_t eic_line, uint32_t eic_pin,
+		uint32_t eic_func, uint32_t eic_irq, __int_handler eic_handler)
+{
+	eic_options_t const eic_options = {
+		.eic_line   = eic_line,
+		.eic_mode   = EIC_MODE_EDGE_TRIGGERED,
+		.eic_edge   = EIC_EDGE_RISING_EDGE,
+		.eic_level  = EIC_LEVEL_HIGH_LEVEL,
+		.eic_filter = EIC_FILTER_ENABLED,
+		.eic_async  = EIC_ASYNCH_MODE
+	};
+
+	sysclk_enable_pba_module(SYSCLK_EIC);
+
+	gpio_enable_module_pin(eic_pin, eic_func);
+	irq_register_handler(eic_handler, eic_irq, 0);
+
+	eic_init(&AVR32_EIC, &eic_options, 1);
+	eic_enable_line(&AVR32_EIC, eic_line);
+	eic_enable_interrupt_line(&AVR32_EIC, eic_line);
+}
+
+#endif
+
+/*! \brief Install a sensor interrupt handler
+ *
+ * The Sensors Xplained add-on boards route sensor device I/O pins to GPIO
+ * pins for the MCU installed on an Xplained platform board.  Some sensor
+ * devices can be configured to generate interrupts on these pins to indicate
+ * the availability of new sensor data or the occurrence of configurable
+ * events related to sensor data thresholds, for example.
+ *
+ * This routine will enable interrupts on the GPIO pin specified by the
+ * \c gpio_pin parameter and call a user-defined callback \c handler when an
+ * interrupt is detected.  The \c arg parameter is used to pass the address
+ * of user-defined input and output storage for the callback handler.  Calling
+ * the routine with the \c handler parameter set to 0 (the NULL pointer) will
+ * fail with \c false returned to the caller.
+ *
+ * \param   gpio_pin    Board-specific GPIO pin interface to the MCU.
+ * \param   handler     The address of a driver-defined interrupt handler.
+ * \param   arg         An optional address passed to the interrupt handler.
+ *
+ * \return  bool        true if the call succeeds, else false.
+ */
+bool sensor_board_irq_connect(uint32_t gpio_pin,
+		SENSOR_IRQ_HANDLER handler, void *arg)
+{
+	bool status = false;
+
+#if XMEGA
+	PORT_t *sensor_port;
+#endif
+
+	/* Ensure that the caller has specified a function address. */
+
+	if (handler == NULL) {
+		return status;
+	}
+
+	/* Save the interrupt flag state and disable MCU interrupts. */
+
+	irqflags_t const irq_flags = cpu_irq_save();
+
+	cpu_irq_disable();
+
+	/* Initialize an interrupt for a specified I/O pin. */
+
+	if (SENSOR_BOARD_PIN3 == gpio_pin) {
+		sensor_pin3_handler = handler;
+		sensor_pin3_arg     = arg;
+
+#if UC3
+#  if defined(SENSOR_PIN3_EIC_LINE)
+		eic_irq_connect(SENSOR_PIN3_EIC_LINE, SENSOR_PIN3_EIC_PIN,
+				SENSOR_PIN3_EIC_FUNC, SENSOR_PIN3_EIC_IRQ,
+				eic_pin3_handler);
+#  else
+		gpio_irq_connect(gpio_pin, SENSOR_PIN3_IRQ);
+#  endif
+#elif XMEGA
+		sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN3);
+		sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
+		sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN3);
+		/* Some Xplained kits have limited asynchronous sensing on most
+		 * pins, which requires them to be sensing on both edges.
+		 */
+		ioport_set_pin_sense_mode(SENSOR_BOARD_PIN3,
+				IOPORT_SENSE_BOTHEDGES);
+#endif
+		status = true;
+	} else if (SENSOR_BOARD_PIN4 == gpio_pin) {
+		sensor_pin4_handler = handler;
+		sensor_pin4_arg     = arg;
+
+#if UC3
+#  if defined(SENSOR_PIN4_EIC_LINE)
+		eic_irq_connect(SENSOR_PIN4_EIC_LINE, SENSOR_PIN4_EIC_PIN,
+				SENSOR_PIN4_EIC_FUNC, SENSOR_PIN4_EIC_IRQ,
+				eic_pin4_handler);
+#  else
+		gpio_irq_connect(gpio_pin, SENSOR_PIN4_IRQ);
+#  endif
+#elif XMEGA
+		sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN4);
+		sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
+		sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN4);
+		/* Some Xplained kits have limited asynchronous sensing on most
+		 * pins, which requires them to be sensing on both edges.
+		 */
+		ioport_set_pin_sense_mode(SENSOR_BOARD_PIN4,
+				IOPORT_SENSE_BOTHEDGES);
+#endif
+		status = true;
+	} else if (SENSOR_BOARD_PIN5 == gpio_pin) {
+		sensor_pin5_handler = handler;
+		sensor_pin5_arg     = arg;
+
+#if UC3
+#  if defined(SENSOR_PIN5_EIC_LINE)
+		eic_irq_connect(SENSOR_PIN5_EIC_LINE, SENSOR_PIN5_EIC_PIN,
+				SENSOR_PIN5_EIC_FUNC, SENSOR_PIN5_EIC_IRQ,
+				eic_pin5_handler);
+#  else
+		gpio_irq_connect(gpio_pin, SENSOR_PIN5_IRQ);
+#  endif
+#elif XMEGA
+		sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN5);
+		sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
+		sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN5);
+		/* Some Xplained kits have limited asynchronous sensing on most
+		 * pins, which requires them to be sensing on both edges.
+		 */
+		ioport_set_pin_sense_mode(SENSOR_BOARD_PIN5,
+				IOPORT_SENSE_BOTHEDGES);
+#endif
+		status = true;
+	}
+
+	/* Restore the MCU interrupt flag state. */
+
+	cpu_irq_restore(irq_flags);
+
+	return status;
+}
+
+#endif /* defined(SENSORS_XPLAINED_BOARD) && defined(COMMON_SENSOR_PLATFORM) */
+
+/*! \brief Initialize sensor board target resources
+ *
+ * This function should be called to ensure proper initialization
+ * of sensor hardware connected to an Atmel AVR32 or XMEGA platform.
+ *
+ * \return  Nothing.
+ */
+void sensor_board_init(void)
+{
+	/* Configure all defined Xplained Sensor board I/O pins.
+	 *
+	 * \todo
+	 * Determine whether the interrupt event flag (rising edge, falling
+	 * edge, toggle, etc.) should be a statically configurable parameter
+	 * for devices requiring more flexibility in how events are detected.
+	 */
+#if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
+	(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
+	(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
+
+	gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_INPUT_FLAGS);
+	gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
+	gpio_configure_pin(SENSOR_BOARD_PIN5, PIN_INPUT_FLAGS);
+
+#elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
+	gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_OUTPUT_FLAGS);
+	gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
+
+#elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
+	gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_INPUT_FLAGS);
+
+#elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+	gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
+#endif
+
+	/* Global Interrupt Disable */
+	cpu_irq_disable();
+
+	/* Initialize interrupt vector table support. */
+	irq_initialize_vectors();
+
+	/* Global Interrupt Enable */
+	cpu_irq_enable();
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.h b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.h
new file mode 100644
index 0000000000..59f4908d6d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.h
@@ -0,0 +1,468 @@
+/**
+ * \file
+ *
+ * \brief SENSORS_XPLAINED_BOARD board header file.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef _sensors_xplained_h_
+#define _sensors_xplained_h_
+
+/**
+ * \defgroup group_common_boards_sensors_xplained Sensors Xplained Extension Boards
+ *
+ * This file contains definitions and services related to the features of the
+ * SENSORS_XPLAINED_XXX Xplained boards.
+ *
+ * To use these boards, define EXT_BOARD=SENSORS_XPLAINED_XXX, where \c 'XXX'
+ * is a place holder for the specific sensor extension board as defined in
+ * the board.h file.  For example, \ref SENSORS_XPLAINED_INERTIAL_1 selects a
+ * configuration supporting the Atmel Inertial Sensor Board #1.
+ *
+ * When this header file is included in a platform build, the
+ * \ref SENSORS_XPLAINED_BOARD configuration constant will be defined so
+ * that conditionally built pieces of platform functionality can be invoked
+ * to make the sensor board usable to the system.  For example, the
+ * platform board_init() routine can conditionally compile calls to
+ * sensor_board_init().
+ *
+ * \{
+ */
+
+#include "xplained_headers.h"
+#include "conf_board.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @defgroup atavrsb_config Sensors Xplained Extension Board Configuration
+ * @brief
+ * The extension board configuration defines constants identifying the sensors,
+ * bus interface, I/O pin mappings, and sensor device signals from an Atmel
+ * Sensor board (\p ATAVRSBPR1, \p ATAVARSBIN1, \p ATAVARSBIN2, and so on)
+ * to the development platform.
+ *
+ * @sa atavrpb_config
+ * @{
+ */
+
+
+/**
+ * \name Common Sensor Service Configuration Constants
+ *
+ * \brief
+ * This module defines \ref mems_sensor_api configuration constants based
+ * upon a user-specified \b EXT_BOARD value.  The Sensor Service determines
+ * which drivers and bus interface modules to use based upon these definitions.
+ * When \b EXT_BOARD defines a valid Sensors Xplained board constant, a
+ * catch-all constant named SENSORS_XPLAINED_BOARD is defined so that platform,
+ * service, and other code can be conditionally configured without testing for
+ * every particular Sensors Xplained board constant.
+ *
+ * All of the following boards are compatible with the Atmel Xplained MCU
+ * boards provided the required I/O peripheral pin mapping has been added
+ * and a call to the sensor_board_init() routine has been included in the
+ * board_init() routine.
+ *
+ * \par ATAVRSBIN1 Inertial Sensor Board No. 1
+ *
+ *  This sensor board includes an InvenSense 3-axis gyro (ITG-3200), Bosch
+ *  3-axis accelerometer (BMA150), and AKM 3-axis magnetometer (AK8975).
+ *  These sensors are interfaced via a TWI master bus mapped to pins on the
+ *  J1 I/O expansion header on an Xplained development platform.  When the
+ *  EXT_BOARD value is set to \ref SENSORS_XPLAINED_INERTIAL_1, the following
+ *  are defined:
+ *
+ *  - \c CONF_SENSOR_BUS_TWI
+ *  - \c INCLUDE_AK8975
+ *  - \c INCLUDE_BMA150
+ *  - \c INCLUDE_ITG3200
+ *
+ * \par ATAVRSBIN2 Inertial Sensor Board No. 2
+ *
+ *  This sensor board includes an InvenSense 3-axis gyro (IMU-3000), Kionix
+ *  3-axis accelerometer (KXTF9), and Honeywell 3-axis magnetometer (HMC5883).
+ *  These sensors are interfaced via a TWI master bus mapped to pins on the
+ *  J1 I/O expansion header on an Xplained development platform.  When the
+ *  EXT_BOARD value is set to \ref SENSORS_XPLAINED_INERTIAL_2, the following
+ *  are defined:
+ *
+ *  - \c CONF_SENSOR_BUS_TWI
+ *  - \c INCLUDE_HMC5883L
+ *  - \c INCLUDE_IMU3000
+ *  - \c INCLUDE_KXTF9
+ *
+ * \par ATAVRSBPR1 Barometric Pressure Sensor Board No. 1
+ *
+ *  This sensor board includes a Bosch barometric pressure sensor (BMP085).
+ *  This sensor is interfaced via a TWI master bus mapped to pins on the
+ *  J1 I/O expansion header on an Xplained development platform.  When the
+ *  EXT_BOARD value is set to \ref SENSORS_XPLAINED_PRESSURE_1, the following
+ *  are defined:
+ *
+ *  - \c CONF_SENSOR_BUS_TWI
+ *  - \c INCLUDE_BMP085
+ *
+ * \par ATAVRSBLP1 Ambient Light & IR Proximity Sensor Board No. 1
+ *
+ *  This sensor board includes an Osram IR light/proximity sensor (SFH7770).
+ *  This sensor is interfaced via a TWI master bus mapped to pins on the
+ *  J1 I/O expansion header on an Xplained development platform.  When the
+ *  EXT_BOARD value is set to \ref SENSORS_XPLAINED_LIGHTPROX_1, the following
+ *  are defined:
+ *
+ *  - \c CONF_SENSOR_BUS_TWI
+ *  - \c INCLUDE_SFH7770
+ *
+ *  The following list summarizes available sensor service configuration
+ *  constants that are specified by board configurations defined in this
+ *  module.
+ *  @{
+ */
+#define SENSORS_XPLAINED_BOARD
+
+#if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)
+#   define CONF_SENSOR_BUS_TWI
+#   define INCLUDE_AK8975
+#   define INCLUDE_BMA150
+#   define INCLUDE_ITG3200
+#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)
+#   define CONF_SENSOR_BUS_TWI
+#   define INCLUDE_HMC5883L
+#   define INCLUDE_IMU3000
+#   define INCLUDE_KXTF9
+#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
+#   define CONF_SENSOR_BUS_TWI
+#   define INCLUDE_AK8975
+#   define INCLUDE_IMU3000
+#   define INCLUDE_KXTF9
+#elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
+#   define CONF_SENSOR_BUS_TWI
+#   define INCLUDE_BMP085
+#elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
+#   define CONF_SENSOR_BUS_TWI
+#   define INCLUDE_SFH7770
+#elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+#   define CONF_SENSOR_BUS_TWI
+#   define INCLUDE_BMA222
+#else
+#   undef SENSORS_XPLAINED_BOARD
+#   warning "The EXT_BOARD constant does not define a Sensors Xplained board."
+#endif
+// @}
+
+
+/*! \name Xplained Board J1 Connector Pin Mapping
+ *
+ * \internal
+ * These constants map AVR & AVR32 ports to pins on the Xplained board J1
+ * connector where pins on the 10-pin header correspond to the following
+ * functions:
+ *
+ * \code
+
+	      10-pin Header           Function
+	  -------------------------------------------
+	      Pin 1                   SDA
+	      Pin 2                   SCL
+	      Pin 3                   RXD
+	      Pin 4                   TXD
+	      Pin 5                   SS
+	      Pin 6                   MOSI
+	      Pin 7                   MISO
+	      Pin 8                   SCK
+
+\endcode
+ * @{
+ */
+#define SENSOR_BOARD_PIN1           XPLD_HEADER_J1_PIN1
+#define SENSOR_BOARD_PIN2           XPLD_HEADER_J1_PIN2
+#define SENSOR_BOARD_PIN3           XPLD_HEADER_J1_PIN3
+#define SENSOR_BOARD_PIN4           XPLD_HEADER_J1_PIN4
+#define SENSOR_BOARD_PIN5           XPLD_HEADER_J1_PIN5
+#define SENSOR_BOARD_PIN6           XPLD_HEADER_J1_PIN6
+#define SENSOR_BOARD_PIN7           XPLD_HEADER_J1_PIN7
+#define SENSOR_BOARD_PIN8           XPLD_HEADER_J1_PIN8
+
+#if XMEGA
+#   define SENSOR_BOARD_PORT        XPLD_HEADER_J1_PORT
+#   define SENSOR_BOARD_PORT_vect   XPLD_HEADER_J1_INT0_vect
+#endif
+// @}
+
+
+/*! \name Sensor Device Interrupt Routing
+ *
+ * \internal
+ * The following constants map I/O expansion header pins that are used as
+ * sensor event signal inputs to the MCU interrupt controller lines and IRQ
+ * numbers.
+ *
+ * These definitions are provided as a board-level description for the
+ * sensor drivers and are not used directly in sensor service client
+ * applications.
+ * @{
+ */
+#define INVALID_IRQ_NUMBER          ((unsigned int) -1)
+
+#if UC3
+#    define SENSOR_PIN1_IRQ         (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN1 / 8))
+#    define SENSOR_PIN2_IRQ         (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN2 / 8))
+#    define SENSOR_PIN3_IRQ         (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN3 / 8))
+#    define SENSOR_PIN4_IRQ         (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN4 / 8))
+#    define SENSOR_PIN5_IRQ         (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN5 / 8))
+#    define SENSOR_PIN6_IRQ         (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN6 / 8))
+#    define SENSOR_PIN7_IRQ         (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN7 / 8))
+#    define SENSOR_PIN8_IRQ         (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN8 / 8))
+#else
+#    define SENSOR_PIN1_IRQ         (INVALID_IRQ_NUMBER)
+#    define SENSOR_PIN2_IRQ         (INVALID_IRQ_NUMBER)
+#    define SENSOR_PIN3_IRQ         (INVALID_IRQ_NUMBER)
+#    define SENSOR_PIN4_IRQ         (INVALID_IRQ_NUMBER)
+#    define SENSOR_PIN5_IRQ         (INVALID_IRQ_NUMBER)
+#    define SENSOR_PIN6_IRQ         (INVALID_IRQ_NUMBER)
+#    define SENSOR_PIN7_IRQ         (INVALID_IRQ_NUMBER)
+#    define SENSOR_PIN8_IRQ         (INVALID_IRQ_NUMBER)
+#endif
+
+#ifdef XPLD_HEADER_J1_PIN1_EIC_LINE
+#    define SENSOR_PIN1_EIC_LINE    XPLD_HEADER_J1_PIN1_EIC_LINE
+#    define SENSOR_PIN1_EIC_IRQ     XPLD_HEADER_J1_PIN1_EIC_IRQ
+#    define SENSOR_PIN1_EIC_PIN     XPLD_HEADER_J1_PIN1_EIC_PIN
+#    define SENSOR_PIN1_EIC_FUNC    XPLD_HEADER_J1_PIN1_EIC_FUNC
+#endif
+
+#ifdef XPLD_HEADER_J1_PIN2_EIC_LINE
+#    define SENSOR_PIN2_EIC_LINE    XPLD_HEADER_J1_PIN2_EIC_LINE
+#    define SENSOR_PIN2_EIC_IRQ     XPLD_HEADER_J1_PIN2_EIC_IRQ
+#    define SENSOR_PIN2_EIC_PIN     XPLD_HEADER_J1_PIN2_EIC_PIN
+#    define SENSOR_PIN2_EIC_FUNC    XPLD_HEADER_J1_PIN2_EIC_FUNC
+#endif
+
+#ifdef XPLD_HEADER_J1_PIN3_EIC_LINE
+#    define SENSOR_PIN3_EIC_LINE    XPLD_HEADER_J1_PIN3_EIC_LINE
+#    define SENSOR_PIN3_EIC_IRQ     XPLD_HEADER_J1_PIN3_EIC_IRQ
+#    define SENSOR_PIN3_EIC_PIN     XPLD_HEADER_J1_PIN3_EIC_PIN
+#    define SENSOR_PIN3_EIC_FUNC    XPLD_HEADER_J1_PIN3_EIC_FUNC
+#endif
+
+#ifdef XPLD_HEADER_J1_PIN4_EIC_LINE
+#    define SENSOR_PIN4_EIC_LINE    XPLD_HEADER_J1_PIN4_EIC_LINE
+#    define SENSOR_PIN4_EIC_IRQ     XPLD_HEADER_J1_PIN4_EIC_IRQ
+#    define SENSOR_PIN4_EIC_PIN     XPLD_HEADER_J1_PIN4_EIC_PIN
+#    define SENSOR_PIN4_EIC_FUNC    XPLD_HEADER_J1_PIN4_EIC_FUNC
+#endif
+
+#ifdef XPLD_HEADER_J1_PIN5_EIC_LINE
+#    define SENSOR_PIN5_EIC_LINE    XPLD_HEADER_J1_PIN5_EIC_LINE
+#    define SENSOR_PIN5_EIC_IRQ     XPLD_HEADER_J1_PIN5_EIC_IRQ
+#    define SENSOR_PIN5_EIC_PIN     XPLD_HEADER_J1_PIN5_EIC_PIN
+#    define SENSOR_PIN5_EIC_FUNC    XPLD_HEADER_J1_PIN5_EIC_FUNC
+#endif
+
+#ifdef XPLD_HEADER_J1_PIN6_EIC_LINE
+#    define SENSOR_PIN6_EIC_LINE    XPLD_HEADER_J1_PIN6_EIC_LINE
+#    define SENSOR_PIN6_EIC_IRQ     XPLD_HEADER_J1_PIN6_EIC_IRQ
+#    define SENSOR_PIN6_EIC_PIN     XPLD_HEADER_J1_PIN6_EIC_PIN
+#    define SENSOR_PIN6_EIC_FUNC    XPLD_HEADER_J1_PIN6_EIC_FUNC
+#endif
+
+#ifdef XPLD_HEADER_J1_PIN7_EIC_LINE
+#    define SENSOR_PIN7_EIC_LINE    XPLD_HEADER_J1_PIN7_EIC_LINE
+#    define SENSOR_PIN7_EIC_IRQ     XPLD_HEADER_J1_PIN7_EIC_IRQ
+#    define SENSOR_PIN7_EIC_PIN     XPLD_HEADER_J1_PIN7_EIC_PIN
+#    define SENSOR_PIN7_EIC_FUNC    XPLD_HEADER_J1_PIN7_EIC_FUNC
+#endif
+
+#ifdef XPLD_HEADER_J1_PIN8_EIC_LINE
+#    define SENSOR_PIN8_EIC_LINE    XPLD_HEADER_J1_PIN8_EIC_LINE
+#    define SENSOR_PIN8_EIC_IRQ     XPLD_HEADER_J1_PIN8_EIC_IRQ
+#    define SENSOR_PIN8_EIC_PIN     XPLD_HEADER_J1_PIN8_EIC_PIN
+#    define SENSOR_PIN8_EIC_FUNC    XPLD_HEADER_J1_PIN8_EIC_FUNC
+#endif
+// @}
+
+
+/*! \name Sensor Device I/O Pins
+ *
+ * \internal
+ * The following constants specify I/O expansion header pins that are used as
+ * sensor event signal inputs to the MCU and, in some cases, control signal
+ * outputs from the MCU to the sensor device.  For example, the \c BMP085
+ * pressure sensor on the \c ATAVRSBPR1 board provides a pressure sample
+ * End-of-Conversion (EOC) input signal to the MCU and a device "master clear"
+ * and reset signal (XCLR) output from the MCU to the sensor.
+ *
+ * These definitions are provided as a board-level description for the
+ * sensor drivers and are not used directly in sensor service client
+ * applications.
+ * @{
+ */
+#if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)
+#   define ak8975_sigint            (SENSOR_BOARD_PIN3)
+#   define bma150_sigint            (SENSOR_BOARD_PIN4)
+#   define itg3200_sigint           (SENSOR_BOARD_PIN5)
+#   define ak8975_sigout            (INVALID_PIN_NUMBER)
+#   define bma150_sigout            (INVALID_PIN_NUMBER)
+#   define itg3200_sigout           (INVALID_PIN_NUMBER)
+#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)
+#   define hmc5883l_sigint          (SENSOR_BOARD_PIN3)
+#   define kxtf9_sigint             (SENSOR_BOARD_PIN4)
+#   define imu3000_sigint           (SENSOR_BOARD_PIN5)
+#   define hmc5883l_sigout          (INVALID_PIN_NUMBER)
+#   define kxtf9_sigout             (INVALID_PIN_NUMBER)
+#   define imu3000_sigout           (INVALID_PIN_NUMBER)
+#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
+#   define ak8975_sigint            (SENSOR_BOARD_PIN3)
+#   define kxtf9_sigint             (SENSOR_BOARD_PIN4)
+#   define imu3000_sigint           (SENSOR_BOARD_PIN5)
+#   define ak8975_sigout            (INVALID_PIN_NUMBER)
+#   define kxtf9_sigout             (INVALID_PIN_NUMBER)
+#   define imu3000_sigout           (INVALID_PIN_NUMBER)
+#elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
+#   define bmp085_sigint            (SENSOR_BOARD_PIN4)
+#   define bmp085_sigout            (SENSOR_BOARD_PIN3)
+#elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
+#   define sfh7770_sigint           (SENSOR_BOARD_PIN3)
+#   define sfh7770_sigout           (INVALID_PIN_NUMBER)
+#elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+#   define bma222_sigint            (SENSOR_BOARD_PIN4)
+#   define bma222_sigout            (INVALID_PIN_NUMBER)
+#endif
+// @}
+
+
+/*! \name Sensor Physical Orientation
+ *
+ * \internal
+ * The following constants describe the physical orientation of multi-axis
+ * sensor devices, relative to the standardized axes of the sensors API.
+ * This allows for devices to be mounted in different configurations but
+ * provide consistent output to applications in terms of each axis.
+ * For each sensor device, the orientation description consists of a set
+ * of three values in X, Y, Z order, which specify which sensor axis and sign
+ * corresponds to the standard axis positive direction.
+ *
+ * These definitions are provided as a board-level description for the
+ * sensor drivers and are not used directly in sensor service client
+ * applications.
+ * @{
+ */
+#define NON_DIRECTIONAL_DEV         {AXIS_NONE, AXIS_NONE, AXIS_NONE}
+
+#if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)
+#   define ak8975_orientation       {AXIS_X_NEG, AXIS_Y_POS, AXIS_Z_NEG}
+#   define bma150_orientation       {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
+#   define itg3200_orientation      {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
+#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)
+#   define hmc5883l_orientation     {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
+#   define kxtf9_orientation        {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
+#   define imu3000_orientation      {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
+#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
+#   define ak8975_orientation       {AXIS_X_NEG, AXIS_Y_POS, AXIS_Z_NEG}
+#   define kxtf9_orientation        {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
+#   define imu3000_orientation      {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
+#elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
+#   define bmp085_orientation       NON_DIRECTIONAL_DEV
+#elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
+#   define sfh7770_orientation      NON_DIRECTIONAL_DEV
+#elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+#   define bma222_orientation       {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
+#endif
+// @}
+
+/** @} */ // atavrsb_config group
+
+
+//! \brief Sensor Pin Interrupt Handler Callback Type
+
+typedef void (*SENSOR_IRQ_HANDLER)(volatile void *);
+
+
+/*! \brief Initialize sensor board target resources
+ *
+ * This function is called to ensure proper initialization
+ * of sensor hardware connected to an Atmel AVR32 or XMEGA platform.
+ *
+ * \return  Nothing.
+ */
+extern void sensor_board_init(void);
+
+/*! \brief Install a sensor interrupt handler
+ *
+ * The Sensors Xplained add-on boards route sensor device I/O pins to GPIO
+ * pins for the MCU installed on an Xplained platform board.  Some sensor
+ * devices can be configured to generate interrupts on these pins to indicate
+ * the availability of new sensor data or the occurrence of configurable
+ * events related to sensor data thresholds, for example.
+ *
+ * This routine will enable interrupts on the GPIO pin specified by the
+ * \c gpio_pin parameter and call a user-defined callback \c handler when an
+ * interrupt is detected.  The \c arg parameter is used to pass the address
+ * of user-defined input and output storage for the callback handler.  Calling
+ * the routine with the \c handler parameter set to 0 (the NULL pointer) will
+ * fail with \c false returned to the caller.
+ *
+ * \param   gpio_pin    Board-specific GPIO pin interface to the MCU.
+ * \param   handler     The address of a driver-defined interrupt handler.
+ * \param   arg         An optional address passed to the interrupt handler.
+ *
+ * \return  bool        true if the call succeeds, else false.
+ */
+extern bool sensor_board_irq_connect
+	(uint32_t gpio_pin, SENSOR_IRQ_HANDLER handler, void *arg);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \}
+ */
+
+#endif /* _sensors_xplained_h_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/xplained_headers.h b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/xplained_headers.h
new file mode 100644
index 0000000000..8e16645d70
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/xplained_headers.h
@@ -0,0 +1,439 @@
+/**
+ * \file
+ *
+ * \brief Xplained I/O Expansion Header Pin Mapping
+ *
+ * The Atmel Xplained evaluation boards have four 10-pin, 100mil headers that
+ * are used to access spare analog and digital pins on the board
+ * microcontroller.  This file provides a common set of definitions mapping
+ * the Xplained expansion header \c J1, \c J2, \c J3, and \c J4 pins to spare
+ * pins on the board microcontroller.  Software can then use these common
+ * definitions to configure I/O for peripherals and expansion boards connected
+ * to the Xplained header blocks.
+ *
+ * For each board type, the pin definitions are specified for the pins in
+ * each of the four headers.  For UC3 based boards, if a pin can be used as
+ * an external interrupt source, the interrupt and GPIO pin mapping settings
+ * that are needed for initializing the external interrupt controller (EIC)
+ * are also provided.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _xplained_headers_h_
+#define _xplained_headers_h_
+
+#include <board.h>
+#include <gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define INVALID_PIN_NUMBER              ((unsigned int) -1)
+
+
+//! \name Xplained I/O Expansion Header Pin Mapping
+// @{
+#if (BOARD == UC3_A3_XPLAINED)
+#   define XPLD_HEADER_J1_PIN1          (AVR32_PIN_PA25)
+#   define XPLD_HEADER_J1_PIN2          (AVR32_PIN_PA26)
+#   define XPLD_HEADER_J1_PIN3          (AVR32_PIN_PX57)
+#   define XPLD_HEADER_J1_PIN4          (AVR32_PIN_PX58)
+#   define XPLD_HEADER_J1_PIN5          (AVR32_PIN_PB09)
+#   define XPLD_HEADER_J1_PIN6          (AVR32_PIN_PB10)
+#   define XPLD_HEADER_J1_PIN7          (AVR32_PIN_PB08)
+#   define XPLD_HEADER_J1_PIN8          (AVR32_PIN_PB07)
+
+#   define XPLD_HEADER_J2_PIN1          (AVR32_PIN_PA21)
+#   define XPLD_HEADER_J2_PIN2          (AVR32_PIN_PA22)
+#   define XPLD_HEADER_J2_PIN3          (AVR32_PIN_PA23)
+#   define XPLD_HEADER_J2_PIN4          (AVR32_PIN_PA24)
+#   define XPLD_HEADER_J2_PIN5          (AVR32_PIN_PA20)
+#   define XPLD_HEADER_J2_PIN6          (AVR32_PIN_PA19)
+#   define XPLD_HEADER_J2_PIN7          (AVR32_PIN_PA18)
+#   define XPLD_HEADER_J2_PIN8          (AVR32_PIN_PA17)
+
+#   define XPLD_HEADER_J3_PIN1          (AVR32_PIN_PA31)
+#   define XPLD_HEADER_J3_PIN2          (AVR32_PIN_PA30)
+#   define XPLD_HEADER_J3_PIN3          (AVR32_PIN_PA29)
+#   define XPLD_HEADER_J3_PIN4          (AVR32_PIN_PA28)
+#   define XPLD_HEADER_J3_PIN5          (AVR32_PIN_PA27)
+#   define XPLD_HEADER_J3_PIN6          (AVR32_PIN_PB00)
+#   define XPLD_HEADER_J3_PIN7          (AVR32_PIN_PB04)
+#   define XPLD_HEADER_J3_PIN8          (AVR32_PIN_PX19)
+
+#   define XPLD_HEADER_J4_PIN1          (AVR32_PIN_PA15)
+#   define XPLD_HEADER_J4_PIN2          (AVR32_PIN_PA14)
+#   define XPLD_HEADER_J4_PIN3          (AVR32_PIN_PA05)
+#   define XPLD_HEADER_J4_PIN4          (AVR32_PIN_PA06)
+#   define XPLD_HEADER_J4_PIN5          (AVR32_PIN_PA07)
+#   define XPLD_HEADER_J4_PIN6          (AVR32_PIN_PA10)
+#   define XPLD_HEADER_J4_PIN7          (AVR32_PIN_PA11)
+#   define XPLD_HEADER_J4_PIN8          (AVR32_PIN_PA08)
+
+#elif (BOARD == UC3_L0_XPLAINED)
+#   define XPLD_HEADER_J1_PIN1          (AVR32_PIN_PA21)
+#   define XPLD_HEADER_J1_PIN2          (AVR32_PIN_PB05)
+#   define XPLD_HEADER_J1_PIN3          (AVR32_PIN_PB11)
+#   define XPLD_HEADER_J1_PIN4          (AVR32_PIN_PB10)
+#   define XPLD_HEADER_J1_PIN5          (AVR32_PIN_PA08)
+#   define XPLD_HEADER_J1_PIN6          (AVR32_PIN_PB03)
+#   define XPLD_HEADER_J1_PIN7          (AVR32_PIN_PB02)
+#   define XPLD_HEADER_J1_PIN8          (AVR32_PIN_PB01)
+
+#   define XPLD_HEADER_J2_PIN1          (AVR32_PIN_PA14)
+#   define XPLD_HEADER_J2_PIN2          (AVR32_PIN_PA15)
+#   define XPLD_HEADER_J2_PIN3          (AVR32_PIN_PA16)
+#   define XPLD_HEADER_J2_PIN4          (AVR32_PIN_PA18)
+#   define XPLD_HEADER_J2_PIN5          (AVR32_PIN_PB07)
+#   define XPLD_HEADER_J2_PIN6          (AVR32_PIN_PB08)
+#   define XPLD_HEADER_J2_PIN7          (AVR32_PIN_PB06)
+#   define XPLD_HEADER_J2_PIN8          (AVR32_PIN_PA19)
+
+#   define XPLD_HEADER_J3_PIN1          (AVR32_PIN_PA13)
+#   define XPLD_HEADER_J3_PIN2          (AVR32_PIN_PA17)
+#   define XPLD_HEADER_J3_PIN3          (AVR32_PIN_PA20)
+#   define XPLD_HEADER_J3_PIN4          (AVR32_PIN_PA22)
+#   define XPLD_HEADER_J3_PIN5          (AVR32_PIN_PB12)
+#   define XPLD_HEADER_J3_PIN6          (AVR32_PIN_PB09)
+#   define XPLD_HEADER_J3_PIN7          (AVR32_PIN_PB04)
+#   define XPLD_HEADER_J3_PIN8          (AVR32_PIN_PA11)
+
+#   define XPLD_HEADER_J4_PIN1          (AVR32_PIN_PA21)
+#   define XPLD_HEADER_J4_PIN2          (AVR32_PIN_PB05)
+#   define XPLD_HEADER_J4_PIN3          (AVR32_PIN_PB11)
+#   define XPLD_HEADER_J4_PIN4          (AVR32_PIN_PB10)
+#   define XPLD_HEADER_J4_PIN5          (AVR32_PIN_PB00)
+#   define XPLD_HEADER_J4_PIN6          (AVR32_PIN_PB03)
+#   define XPLD_HEADER_J4_PIN7          (AVR32_PIN_PB02)
+#   define XPLD_HEADER_J4_PIN8          (AVR32_PIN_PB01)
+
+#elif (BOARD == XMEGA_A1_XPLAINED)
+#   define XPLD_HEADER_J1_PIN1          IOPORT_CREATE_PIN(PORTF,0)
+#   define XPLD_HEADER_J1_PIN2          IOPORT_CREATE_PIN(PORTF,1)
+#   define XPLD_HEADER_J1_PIN3          IOPORT_CREATE_PIN(PORTF,2)
+#   define XPLD_HEADER_J1_PIN4          IOPORT_CREATE_PIN(PORTF,3)
+#   define XPLD_HEADER_J1_PIN5          IOPORT_CREATE_PIN(PORTF,4)
+#   define XPLD_HEADER_J1_PIN6          IOPORT_CREATE_PIN(PORTF,5)
+#   define XPLD_HEADER_J1_PIN7          IOPORT_CREATE_PIN(PORTF,6)
+#   define XPLD_HEADER_J1_PIN8          IOPORT_CREATE_PIN(PORTF,7)
+
+#   define XPLD_HEADER_J2_PIN1          IOPORT_CREATE_PIN(PORTA,0)
+#   define XPLD_HEADER_J2_PIN2          IOPORT_CREATE_PIN(PORTA,1)
+#   define XPLD_HEADER_J2_PIN3          IOPORT_CREATE_PIN(PORTA,2)
+#   define XPLD_HEADER_J2_PIN4          IOPORT_CREATE_PIN(PORTA,3)
+#   define XPLD_HEADER_J2_PIN5          IOPORT_CREATE_PIN(PORTA,4)
+#   define XPLD_HEADER_J2_PIN6          IOPORT_CREATE_PIN(PORTA,5)
+#   define XPLD_HEADER_J2_PIN7          IOPORT_CREATE_PIN(PORTA,6)
+#   define XPLD_HEADER_J2_PIN8          IOPORT_CREATE_PIN(PORTA,7)
+
+#   define XPLD_HEADER_J3_PIN1          IOPORT_CREATE_PIN(PORTD,0)
+#   define XPLD_HEADER_J3_PIN2          IOPORT_CREATE_PIN(PORTD,1)
+#   define XPLD_HEADER_J3_PIN3          IOPORT_CREATE_PIN(PORTD,2)
+#   define XPLD_HEADER_J3_PIN4          IOPORT_CREATE_PIN(PORTD,3)
+#   define XPLD_HEADER_J3_PIN5          IOPORT_CREATE_PIN(PORTD,4)
+#   define XPLD_HEADER_J3_PIN6          IOPORT_CREATE_PIN(PORTD,5)
+#   define XPLD_HEADER_J3_PIN7          IOPORT_CREATE_PIN(PORTR,0)
+#   define XPLD_HEADER_J3_PIN8          IOPORT_CREATE_PIN(PORTR,1)
+
+#   define XPLD_HEADER_J4_PIN1          IOPORT_CREATE_PIN(PORTC,0)
+#   define XPLD_HEADER_J4_PIN2          IOPORT_CREATE_PIN(PORTC,1)
+#   define XPLD_HEADER_J4_PIN3          IOPORT_CREATE_PIN(PORTC,2)
+#   define XPLD_HEADER_J4_PIN4          IOPORT_CREATE_PIN(PORTC,3)
+#   define XPLD_HEADER_J4_PIN5          IOPORT_CREATE_PIN(PORTC,4)
+#   define XPLD_HEADER_J4_PIN6          IOPORT_CREATE_PIN(PORTC,5)
+#   define XPLD_HEADER_J4_PIN7          IOPORT_CREATE_PIN(PORTC,6)
+#   define XPLD_HEADER_J4_PIN8          IOPORT_CREATE_PIN(PORTC,7)
+
+#elif (BOARD == XMEGA_B1_XPLAINED)
+#   define XPLD_HEADER_J1_PIN1          IOPORT_CREATE_PIN(PORTC,0)
+#   define XPLD_HEADER_J1_PIN2          IOPORT_CREATE_PIN(PORTC,1)
+#   define XPLD_HEADER_J1_PIN3          IOPORT_CREATE_PIN(PORTC,2)
+#   define XPLD_HEADER_J1_PIN4          IOPORT_CREATE_PIN(PORTC,3)
+#   define XPLD_HEADER_J1_PIN5          IOPORT_CREATE_PIN(PORTC,4)
+#   define XPLD_HEADER_J1_PIN6          IOPORT_CREATE_PIN(PORTC,5)
+#   define XPLD_HEADER_J1_PIN7          IOPORT_CREATE_PIN(PORTC,6)
+#   define XPLD_HEADER_J1_PIN8          IOPORT_CREATE_PIN(PORTC,7)
+
+#   define XPLD_HEADER_J2_PIN1          IOPORT_CREATE_PIN(PORTA,0)
+#   define XPLD_HEADER_J2_PIN2          IOPORT_CREATE_PIN(PORTA,1)
+#   define XPLD_HEADER_J2_PIN3          IOPORT_CREATE_PIN(PORTA,2)
+#   define XPLD_HEADER_J2_PIN4          IOPORT_CREATE_PIN(PORTA,3)
+#   define XPLD_HEADER_J2_PIN5          IOPORT_CREATE_PIN(PORTA,4)
+#   define XPLD_HEADER_J2_PIN6          IOPORT_CREATE_PIN(PORTA,5)
+#   define XPLD_HEADER_J2_PIN7          IOPORT_CREATE_PIN(PORTA,6)
+#   define XPLD_HEADER_J2_PIN8          IOPORT_CREATE_PIN(PORTA,7)
+
+#   define XPLD_HEADER_J3_PIN1          IOPORT_CREATE_PIN(PORTB,0)
+#   define XPLD_HEADER_J3_PIN2          IOPORT_CREATE_PIN(PORTB,1)
+#   define XPLD_HEADER_J3_PIN3          IOPORT_CREATE_PIN(PORTB,2)
+#   define XPLD_HEADER_J3_PIN4          IOPORT_CREATE_PIN(PORTB,3)
+#   define XPLD_HEADER_J3_PIN5          IOPORT_CREATE_PIN(PORTB,4)
+#   define XPLD_HEADER_J3_PIN6          IOPORT_CREATE_PIN(PORTB,5)
+#   define XPLD_HEADER_J3_PIN7          IOPORT_CREATE_PIN(PORTB,6)
+#   define XPLD_HEADER_J3_PIN8          IOPORT_CREATE_PIN(PORTB,7)
+
+#   define XPLD_HEADER_J4_PIN1          IOPORT_CREATE_PIN(PORTE,0)
+#   define XPLD_HEADER_J4_PIN2          IOPORT_CREATE_PIN(PORTE,1)
+#   define XPLD_HEADER_J4_PIN3          IOPORT_CREATE_PIN(PORTE,2)
+#   define XPLD_HEADER_J4_PIN4          IOPORT_CREATE_PIN(PORTE,3)
+#   define XPLD_HEADER_J4_PIN5          IOPORT_CREATE_PIN(PORTE,4)
+#   define XPLD_HEADER_J4_PIN6          IOPORT_CREATE_PIN(PORTE,5)
+#   define XPLD_HEADER_J4_PIN7          IOPORT_CREATE_PIN(PORTE,6)
+#   define XPLD_HEADER_J4_PIN8          IOPORT_CREATE_PIN(PORTE,7)
+
+#elif (BOARD == XMEGA_A3BU_XPLAINED)
+#   define XPLD_HEADER_J1_PIN1          IOPORT_CREATE_PIN(PORTC,0)
+#   define XPLD_HEADER_J1_PIN2          IOPORT_CREATE_PIN(PORTC,1)
+#   define XPLD_HEADER_J1_PIN3          IOPORT_CREATE_PIN(PORTC,2)
+#   define XPLD_HEADER_J1_PIN4          IOPORT_CREATE_PIN(PORTC,3)
+#   define XPLD_HEADER_J1_PIN5          IOPORT_CREATE_PIN(PORTC,4)
+#   define XPLD_HEADER_J1_PIN6          IOPORT_CREATE_PIN(PORTC,5)
+#   define XPLD_HEADER_J1_PIN7          IOPORT_CREATE_PIN(PORTC,6)
+#   define XPLD_HEADER_J1_PIN8          IOPORT_CREATE_PIN(PORTC,7)
+
+#   define XPLD_HEADER_J2_PIN1          IOPORT_CREATE_PIN(PORTB,0)
+#   define XPLD_HEADER_J2_PIN2          IOPORT_CREATE_PIN(PORTB,1)
+#   define XPLD_HEADER_J2_PIN3          IOPORT_CREATE_PIN(PORTB,2)
+#   define XPLD_HEADER_J2_PIN4          IOPORT_CREATE_PIN(PORTB,3)
+#   define XPLD_HEADER_J2_PIN5          IOPORT_CREATE_PIN(PORTA,4)
+#   define XPLD_HEADER_J2_PIN6          IOPORT_CREATE_PIN(PORTA,5)
+#   define XPLD_HEADER_J2_PIN7          IOPORT_CREATE_PIN(PORTA,6)
+#   define XPLD_HEADER_J2_PIN8          IOPORT_CREATE_PIN(PORTA,7)
+
+#   define XPLD_HEADER_J3_PIN1          IOPORT_CREATE_PIN(PORTA,0)
+#   define XPLD_HEADER_J3_PIN2          IOPORT_CREATE_PIN(PORTA,1)
+#   define XPLD_HEADER_J3_PIN3          IOPORT_CREATE_PIN(PORTA,2)
+#   define XPLD_HEADER_J3_PIN4          IOPORT_CREATE_PIN(PORTA,3)
+#   define XPLD_HEADER_J3_PIN5          IOPORT_CREATE_PIN(PORTB,4)
+#   define XPLD_HEADER_J3_PIN6          IOPORT_CREATE_PIN(PORTB,5)
+#   define XPLD_HEADER_J3_PIN7          IOPORT_CREATE_PIN(PORTB,6)
+#   define XPLD_HEADER_J3_PIN8          IOPORT_CREATE_PIN(PORTB,7)
+
+#   define XPLD_HEADER_J4_PIN1          IOPORT_CREATE_PIN(PORTE,0)
+#   define XPLD_HEADER_J4_PIN2          IOPORT_CREATE_PIN(PORTE,1)
+#   define XPLD_HEADER_J4_PIN3          IOPORT_CREATE_PIN(PORTE,2)
+#   define XPLD_HEADER_J4_PIN4          IOPORT_CREATE_PIN(PORTE,3)
+#   define XPLD_HEADER_J4_PIN5          IOPORT_CREATE_PIN(PORTD,0)
+#   define XPLD_HEADER_J4_PIN6          IOPORT_CREATE_PIN(PORTD,3)
+#   define XPLD_HEADER_J4_PIN7          IOPORT_CREATE_PIN(PORTD,2)
+#   define XPLD_HEADER_J4_PIN8          IOPORT_CREATE_PIN(PORTD,1)
+
+#else
+#   warning "The BOARD constant does not define a supported Xplained board."
+#   define XPLD_HEADER_J1_PIN1          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J1_PIN2          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J1_PIN3          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J1_PIN4          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J1_PIN5          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J1_PIN6          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J1_PIN7          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J1_PIN8          INVALID_PIN_NUMBER
+
+#   define XPLD_HEADER_J2_PIN1          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J2_PIN2          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J2_PIN3          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J2_PIN4          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J2_PIN5          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J2_PIN6          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J2_PIN7          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J2_PIN8          INVALID_PIN_NUMBER
+
+#   define XPLD_HEADER_J3_PIN1          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J3_PIN2          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J3_PIN3          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J3_PIN4          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J3_PIN5          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J3_PIN6          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J3_PIN7          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J3_PIN8          INVALID_PIN_NUMBER
+
+#   define XPLD_HEADER_J4_PIN1          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J4_PIN2          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J4_PIN3          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J4_PIN4          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J4_PIN5          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J4_PIN6          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J4_PIN7          INVALID_PIN_NUMBER
+#   define XPLD_HEADER_J4_PIN8          INVALID_PIN_NUMBER
+#endif
+// @}
+
+
+//! \name Xplained Expansion Header External Interrupt Controller Pin Mapping
+// @{
+#if (BOARD == UC3_A3_XPLAINED)
+#   define XPLD_HEADER_J2_PIN1_EIC_LINE (AVR32_EIC_INT0)
+#   define XPLD_HEADER_J2_PIN1_EIC_IRQ  (AVR32_EIC_IRQ_0)
+#   define XPLD_HEADER_J2_PIN1_EIC_PIN  (AVR32_EIC_EXTINT_0_PIN)
+#   define XPLD_HEADER_J2_PIN1_EIC_FUNC (AVR32_EIC_EXTINT_0_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN2_EIC_LINE (AVR32_EIC_INT1)
+#   define XPLD_HEADER_J2_PIN2_EIC_IRQ  (AVR32_EIC_IRQ_1)
+#   define XPLD_HEADER_J2_PIN2_EIC_PIN  (AVR32_EIC_EXTINT_1_PIN)
+#   define XPLD_HEADER_J2_PIN2_EIC_FUNC (AVR32_EIC_EXTINT_1_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN3_EIC_LINE (AVR32_EIC_INT2)
+#   define XPLD_HEADER_J2_PIN3_EIC_IRQ  (AVR32_EIC_IRQ_2)
+#   define XPLD_HEADER_J2_PIN3_EIC_PIN  (AVR32_EIC_EXTINT_2_PIN)
+#   define XPLD_HEADER_J2_PIN3_EIC_FUNC (AVR32_EIC_EXTINT_2_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN4_EIC_LINE (AVR32_EIC_INT3)
+#   define XPLD_HEADER_J2_PIN4_EIC_IRQ  (AVR32_EIC_IRQ_3)
+#   define XPLD_HEADER_J2_PIN4_EIC_PIN  (AVR32_EIC_EXTINT_3_PIN)
+#   define XPLD_HEADER_J2_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_3_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN5_EIC_LINE (8) // NMI
+#   define XPLD_HEADER_J2_PIN5_EIC_IRQ  (0) // NMI - special handler required
+#   define XPLD_HEADER_J2_PIN5_EIC_PIN  (AVR32_EIC_EXTINT_8_PIN)
+#   define XPLD_HEADER_J2_PIN5_EIC_FUNC (AVR32_EIC_EXTINT_8_FUNCTION)
+
+#elif (BOARD == UC3_L0_XPLAINED)
+#   define XPLD_HEADER_J1_PIN3_EIC_LINE (AVR32_EIC_INT5)
+#   define XPLD_HEADER_J1_PIN3_EIC_IRQ  (AVR32_EIC_IRQ_5)
+#   define XPLD_HEADER_J1_PIN3_EIC_PIN  (AVR32_EIC_EXTINT_5_1_PIN)
+#   define XPLD_HEADER_J1_PIN3_EIC_FUNC (AVR32_EIC_EXTINT_5_1_FUNCTION)
+
+#   define XPLD_HEADER_J1_PIN4_EIC_LINE (AVR32_EIC_INT4)
+#   define XPLD_HEADER_J1_PIN4_EIC_IRQ  (AVR32_EIC_IRQ_4)
+#   define XPLD_HEADER_J1_PIN4_EIC_PIN  (AVR32_EIC_EXTINT_4_1_PIN)
+#   define XPLD_HEADER_J1_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_4_1_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN2_EIC_LINE (AVR32_EIC_INT3)
+#   define XPLD_HEADER_J2_PIN2_EIC_IRQ  (AVR32_EIC_IRQ_3)
+#   define XPLD_HEADER_J2_PIN2_EIC_PIN  (AVR32_EIC_EXTINT_3_0_PIN)
+#   define XPLD_HEADER_J2_PIN2_EIC_FUNC (AVR32_EIC_EXTINT_3_0_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN3_EIC_LINE (AVR32_EIC_INT4)
+#   define XPLD_HEADER_J2_PIN3_EIC_IRQ  (AVR32_EIC_IRQ_4)
+#   define XPLD_HEADER_J2_PIN3_EIC_PIN  (AVR32_EIC_EXTINT_4_0_PIN)
+#   define XPLD_HEADER_J2_PIN3_EIC_FUNC (AVR32_EIC_EXTINT_4_0_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN4_EIC_LINE (AVR32_EIC_INT5)
+#   define XPLD_HEADER_J2_PIN4_EIC_IRQ  (AVR32_EIC_IRQ_5)
+#   define XPLD_HEADER_J2_PIN4_EIC_PIN  (AVR32_EIC_EXTINT_5_0_PIN)
+#   define XPLD_HEADER_J2_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_5_0_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN5_EIC_LINE (AVR32_EIC_INT1)
+#   define XPLD_HEADER_J2_PIN5_EIC_IRQ  (AVR32_EIC_IRQ_1)
+#   define XPLD_HEADER_J2_PIN5_EIC_PIN  (AVR32_EIC_EXTINT_1_1_PIN)
+#   define XPLD_HEADER_J2_PIN5_EIC_FUNC (AVR32_EIC_EXTINT_1_1_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN6_EIC_LINE (AVR32_EIC_INT2)
+#   define XPLD_HEADER_J2_PIN6_EIC_IRQ  (AVR32_EIC_IRQ_2)
+#   define XPLD_HEADER_J2_PIN6_EIC_PIN  (AVR32_EIC_EXTINT_2_1_PIN)
+#   define XPLD_HEADER_J2_PIN6_EIC_FUNC (AVR32_EIC_EXTINT_2_1_FUNCTION)
+
+#   define XPLD_HEADER_J2_PIN7_EIC_LINE (AVR32_EIC_INT0)
+#   define XPLD_HEADER_J2_PIN7_EIC_IRQ  (AVR32_EIC_IRQ_0)
+#   define XPLD_HEADER_J2_PIN7_EIC_PIN  (AVR32_EIC_EXTINT_0_1_PIN)
+#   define XPLD_HEADER_J2_PIN7_EIC_FUNC (AVR32_EIC_EXTINT_0_1_FUNCTION)
+
+#   define XPLD_HEADER_J3_PIN1_EIC_LINE (AVR32_EIC_INT2)
+#   define XPLD_HEADER_J3_PIN1_EIC_IRQ  (AVR32_EIC_IRQ_2)
+#   define XPLD_HEADER_J3_PIN1_EIC_PIN  (AVR32_EIC_EXTINT_2_0_PIN)
+#   define XPLD_HEADER_J3_PIN1_EIC_FUNC (AVR32_EIC_EXTINT_2_0_FUNCTION)
+
+#   define XPLD_HEADER_J3_PIN6_EIC_LINE (AVR32_EIC_INT3)
+#   define XPLD_HEADER_J3_PIN6_EIC_IRQ  (AVR32_EIC_IRQ_3)
+#   define XPLD_HEADER_J3_PIN6_EIC_PIN  (AVR32_EIC_EXTINT_3_1_PIN)
+#   define XPLD_HEADER_J3_PIN6_EIC_FUNC (AVR32_EIC_EXTINT_3_1_FUNCTION)
+
+#   define XPLD_HEADER_J4_PIN3_EIC_LINE (AVR32_EIC_INT5)
+#   define XPLD_HEADER_J4_PIN3_EIC_IRQ  (AVR32_EIC_IRQ_5)
+#   define XPLD_HEADER_J4_PIN3_EIC_PIN  (AVR32_EIC_EXTINT_5_1_PIN)
+#   define XPLD_HEADER_J4_PIN3_EIC_FUNC (AVR32_EIC_EXTINT_5_1_FUNCTION)
+
+#   define XPLD_HEADER_J4_PIN4_EIC_LINE (AVR32_EIC_INT4)
+#   define XPLD_HEADER_J4_PIN4_EIC_IRQ  (AVR32_EIC_IRQ_4)
+#   define XPLD_HEADER_J4_PIN4_EIC_PIN  (AVR32_EIC_EXTINT_4_1_PIN)
+#   define XPLD_HEADER_J4_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_4_1_FUNCTION)
+
+#elif (BOARD == XMEGA_A1_XPLAINED)
+#   define XPLD_HEADER_J1_PORT          (PORTF)
+#   define XPLD_HEADER_J1_INT0_vect     (PORTF_INT0_vect)
+#   define XPLD_HEADER_J1_INT1_vect     (PORTF_INT1_vect)
+
+#   define XPLD_HEADER_J2_PORT          (PORTA)
+#   define XPLD_HEADER_J2_INT0_vect     (PORTA_INT0_vect)
+#   define XPLD_HEADER_J2_INT1_vect     (PORTA_INT1_vect)
+
+#   define XPLD_HEADER_J3_PORT          (PORTD)
+#   define XPLD_HEADER_J3_INT0_vect     (PORTD_INT0_vect)
+#   define XPLD_HEADER_J3_INT1_vect     (PORTD_INT1_vect)
+
+#   define XPLD_HEADER_J4_PORT          (PORTC)
+#   define XPLD_HEADER_J4_INT0_vect     (PORTC_INT0_vect)
+#   define XPLD_HEADER_J4_INT1_vect     (PORTC_INT1_vect)
+
+#elif (BOARD == XMEGA_B1_XPLAINED)
+#   define XPLD_HEADER_J1_PORT          (PORTC)
+#   define XPLD_HEADER_J1_INT0_vect     (PORTC_INT0_vect)
+#   define XPLD_HEADER_J1_INT1_vect     (PORTC_INT1_vect)
+
+#   define XPLD_HEADER_J2_PORT          (PORTA)
+#   define XPLD_HEADER_J2_INT0_vect     (PORTA_INT0_vect)
+#   define XPLD_HEADER_J2_INT1_vect     (PORTA_INT1_vect)
+
+#   define XPLD_HEADER_J3_PORT          (PORTB)
+#   define XPLD_HEADER_J3_INT0_vect     (PORTB_INT0_vect)
+#   define XPLD_HEADER_J3_INT1_vect     (PORTB_INT1_vect)
+
+#   define XPLD_HEADER_J4_PORT          (PORTE)
+#   define XPLD_HEADER_J4_INT0_vect     (PORTE_INT0_vect)
+#   define XPLD_HEADER_J4_INT1_vect     (PORTE_INT1_vect)
+
+#elif (BOARD == XMEGA_A3BU_XPLAINED)
+#   define XPLD_HEADER_J1_PORT          (PORTC)
+#   define XPLD_HEADER_J1_INT0_vect     (PORTC_INT0_vect)
+#   define XPLD_HEADER_J1_INT1_vect     (PORTC_INT1_vect)
+
+#endif
+// @}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _xplained_headers_h_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h
new file mode 100644
index 0000000000..7b88c97fc2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h
@@ -0,0 +1,14 @@
+/**
+ * \file
+ *
+ * \brief User board configuration template
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_BOARD_H
+#define CONF_BOARD_H
+
+#endif // CONF_BOARD_H
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.gdb b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.gdb
new file mode 100644
index 0000000000..cc98840d25
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.gdb
@@ -0,0 +1 @@
+# This file needs to be customized to your MCU and is intentionally left blank
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.mac b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.mac
new file mode 100644
index 0000000000..cd2c8e03d7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.mac
@@ -0,0 +1,3 @@
+// This file needs to be customized to your MCU and is intentionally left blank /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.gdb b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.gdb
new file mode 100644
index 0000000000..cc98840d25
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.gdb
@@ -0,0 +1 @@
+# This file needs to be customized to your MCU and is intentionally left blank
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.mac b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.mac
new file mode 100644
index 0000000000..cd2c8e03d7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.mac
@@ -0,0 +1,3 @@
+// This file needs to be customized to your MCU and is intentionally left blank /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c
new file mode 100644
index 0000000000..32fba3695e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c
@@ -0,0 +1,21 @@
+/**
+ * \file
+ *
+ * \brief User board initialization template
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <asf.h>
+#include <board.h>
+#include <conf_board.h>
+
+void board_init(void)
+{
+	/* This function is meant to contain board-specific initialization code
+	 * for, e.g., the I/O pins. The initialization can rely on application-
+	 * specific board configuration, found in conf_board.h.
+	 */
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h
new file mode 100644
index 0000000000..39980a7d2e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h
@@ -0,0 +1,40 @@
+/**
+ * \file
+ *
+ * \brief User board definition template
+ *
+ */
+
+ /* This file is intended to contain definitions and configuration details for
+ * features and devices that are available on the board, e.g., frequency and
+ * startup time for an external crystal, external memory devices, LED and USART
+ * pins.
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef USER_BOARD_H
+#define USER_BOARD_H
+
+#include <conf_board.h>
+
+// External oscillator settings.
+// Uncomment and set correct values if external oscillator is used.
+
+// External oscillator frequency
+//#define BOARD_XOSC_HZ          8000000
+
+// External oscillator type.
+//!< External clock signal
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_EXTERNAL
+//!< 32.768 kHz resonator on TOSC
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_32KHZ
+//!< 0.4 to 16 MHz resonator on XTALS
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_XTAL
+
+// External oscillator startup time
+//#define BOARD_XOSC_STARTUP_US  500000
+
+
+#endif // USER_BOARD_H
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/module_config/conf_atsha204.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/module_config/conf_atsha204.h
new file mode 100644
index 0000000000..f1adbce38e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/module_config/conf_atsha204.h
@@ -0,0 +1,68 @@
+/**
+ * \file
+ *
+ * \brief ATSHA204 CryptoAuth driver configuration file
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_ATSHA204_H_INCLUDED
+#define CONF_ATSHA204_H_INCLUDED
+
+#include <board.h>
+
+#if BOARD == XMEGA_A1_XPLAINED
+// Interface configuration for XMEGA-A1 Xplained
+#  define ATSHA204_TWI_PORT         (&TWIC)
+
+#else
+// Interface configuration for other boards
+#  warning ATSHA204 TWI port is not set for your board. Please see conf_atsha204.h.
+#  define ATSHA204_TWI_PORT         (&TWIC)
+#endif // BOARD
+
+// Xplain board independent configuration
+#define ATSHA204_TWI_SPEED      	(400000)
+
+//! TWI address used at SHA204 library startup
+#define SHA204_I2C_DEFAULT_ADDRESS  (0xCA)
+
+#endif /* CONF_ATSHA204_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.c b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.c
new file mode 100644
index 0000000000..24c484b1e7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.c
@@ -0,0 +1,312 @@
+/*
+ * \file
+ *
+ * \brief ATSHA204 file that implements the communication layer for the device
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "sha204_comm.h"                //!< definitions and declarations for the Communication module
+#include "sha204_timer.h"               //!< definitions for timer functions
+#include "sha204_lib_return_codes.h"    //!< declarations of function return codes
+
+uint8_t sha204c_check_crc(uint8_t *response);
+uint8_t sha204c_resync(uint8_t size, uint8_t *response);
+
+/** \brief This function calculates CRC.
+ *
+ * \param[in] length number of bytes in buffer
+ * \param[in] data pointer to data for which CRC should be calculated
+ * \param[out] crc pointer to 16-bit CRC
+ */
+void sha204c_calculate_crc(uint8_t length, uint8_t *data, uint8_t *crc) {
+	uint8_t counter;
+	uint16_t crc_register = 0;
+	uint16_t polynom = 0x8005;
+	uint8_t shift_register;
+	uint8_t data_bit, crc_bit;
+
+	for (counter = 0; counter < length; counter++) {
+	  for (shift_register = 0x01; shift_register > 0x00; shift_register <<= 1) {
+		 data_bit = (data[counter] & shift_register) ? 1 : 0;
+		 crc_bit = crc_register >> 15;
+
+		 // Shift CRC to the left by 1.
+		 crc_register <<= 1;
+
+		 if ((data_bit ^ crc_bit) != 0)
+			crc_register ^= polynom;
+	  }
+	}
+	crc[0] = (uint8_t) (crc_register & 0x00FF);
+	crc[1] = (uint8_t) (crc_register >> 8);
+}
+
+
+/** \brief This function checks the consistency of a response.
+ * \param[in] response pointer to response
+ * \return status of the consistency check
+ */
+uint8_t sha204c_check_crc(uint8_t *response)
+{
+	uint8_t crc[SHA204_CRC_SIZE];
+	uint8_t count = response[SHA204_BUFFER_POS_COUNT];
+
+	count -= SHA204_CRC_SIZE;
+	sha204c_calculate_crc(count, response, crc);
+
+	return (crc[0] == response[count] && crc[1] == response[count + 1])
+		? SHA204_SUCCESS : SHA204_BAD_CRC;
+}
+
+
+/** \brief This function wakes up a SHA204 device
+ *         and receives a response.
+ *  \param[out] response pointer to four-byte response
+ *  \return status of the operation
+ */
+uint8_t sha204c_wakeup(uint8_t *response)
+{
+	uint8_t ret_code = sha204p_wakeup();
+	if (ret_code != SHA204_SUCCESS)
+		return ret_code;
+
+	ret_code = sha204p_receive_response(SHA204_RSP_SIZE_MIN, response);
+	if (ret_code != SHA204_SUCCESS)
+		return ret_code;
+
+	// Verify status response.
+	if (response[SHA204_BUFFER_POS_COUNT] != SHA204_RSP_SIZE_MIN)
+		ret_code = SHA204_INVALID_SIZE;
+	else if (response[SHA204_BUFFER_POS_STATUS] != SHA204_STATUS_BYTE_WAKEUP)
+		ret_code = SHA204_COMM_FAIL;
+	else {
+		if ((response[SHA204_RSP_SIZE_MIN - SHA204_CRC_SIZE] != 0x33)
+					|| (response[SHA204_RSP_SIZE_MIN + 1 - SHA204_CRC_SIZE] != 0x43))
+			ret_code = SHA204_BAD_CRC;
+	}
+	if (ret_code != SHA204_SUCCESS)
+		sha204h_delay_ms(SHA204_COMMAND_EXEC_MAX);
+
+	return ret_code;
+}
+
+
+/** \brief This function re-synchronizes communication.
+ *
+  Be aware that succeeding only after waking up the
+  device could mean that it had gone to sleep and lost
+  its TempKey in the process.\n
+  Re-synchronizing communication is done in a maximum of
+  three steps:
+  <ol>
+    <li>
+      Try to re-synchronize without sending a Wake token.
+      This step is implemented in the Physical layer.
+    </li>
+    <li>
+      If the first step did not succeed send a Wake token.
+    </li>
+    <li>
+      Try to read the Wake response.
+    </li>
+  </ol>
+ *
+ * \param[in] size size of response buffer
+ * \param[out] response pointer to Wake-up response buffer
+ * \return status of the operation
+ */
+uint8_t sha204c_resync(uint8_t size, uint8_t *response)
+{
+	// Try to re-synchronize without sending a Wake token
+	// (step 1 of the re-synchronization process).
+	uint8_t ret_code = sha204p_resync(size, response);
+	if (ret_code == SHA204_SUCCESS)
+		return ret_code;
+
+	// We lost communication. Send a Wake pulse and try
+	// to receive a response (steps 2 and 3 of the
+	// re-synchronization process).
+	(void) sha204p_sleep();
+	ret_code = sha204c_wakeup(response);
+
+	// Translate a return value of success into one
+	// that indicates that the device had to be woken up
+	// and might have lost its TempKey.
+	return (ret_code == SHA204_SUCCESS ? SHA204_RESYNC_WITH_WAKEUP : ret_code);
+}
+
+
+/** \brief This function runs a communication sequence:
+ * Append CRC to tx buffer, send command, delay, and verify response after receiving it.
+ *
+ * The first byte in tx buffer must be the byte count of the packet.
+ * If CRC or count of the response is incorrect, or a command byte got "nacked" (TWI),
+ * this function requests re-sending the response.
+ * If the response contains an error status, this function resends the command.
+ *
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204c_send_and_receive(struct sha204_send_and_receive_parameters *args)
+{
+	uint8_t ret_code = SHA204_FUNC_FAIL;
+	uint8_t ret_code_resync;
+	uint8_t n_retries_send;
+	uint8_t n_retries_receive;
+	uint8_t i;
+	uint8_t status_byte;
+	uint8_t count = args->tx_buffer[SHA204_BUFFER_POS_COUNT];
+	uint8_t count_minus_crc = count - SHA204_CRC_SIZE;
+
+	// Append CRC.
+	sha204c_calculate_crc(count_minus_crc, args->tx_buffer, args->tx_buffer + count_minus_crc);
+
+	// Retry loop for sending a command and receiving a response.
+	n_retries_send = SHA204_RETRY_COUNT + 1;
+
+	while ((n_retries_send-- > 0) && (ret_code != SHA204_SUCCESS)) {
+
+		// Send command.
+		ret_code = sha204p_send_command(count, args->tx_buffer);
+		if (ret_code != SHA204_SUCCESS) {
+			if (sha204c_resync(args->rx_size, args->rx_buffer) == SHA204_RX_NO_RESPONSE)
+				// The device seems to be dead in the water.
+				return ret_code;
+			else
+				continue;
+		}
+
+		// Wait typical command execution time and then start polling for a response.
+		sha204h_delay_ms(args->poll_delay);
+
+		// Retry loop for receiving a response.
+		n_retries_receive = SHA204_RETRY_COUNT + 1;
+		while (n_retries_receive-- > 0) {
+
+			// Reset response buffer.
+			for (i = 0; i < args->rx_size; i++)
+				args->rx_buffer[i] = 0;
+
+			sha204h_start_timeout_timer_ms(args->poll_timeout);
+			do {
+				ret_code = sha204p_receive_response(args->rx_size, args->rx_buffer);
+			} while (!sha204_timer_expired && (ret_code == SHA204_RX_NO_RESPONSE));
+
+			if (ret_code == SHA204_RX_NO_RESPONSE) {
+				// We did not receive a response. Re-synchronize and send command again.
+				if (sha204c_resync(args->rx_size, args->rx_buffer) == SHA204_RX_NO_RESPONSE)
+					// The device seems to be dead in the water.
+					return ret_code;
+				else
+					break;
+			}
+
+			// Check whether we received a valid response.
+			if (ret_code == SHA204_INVALID_SIZE) {
+				// We see 0xFF for the count when communication got out of sync.
+				ret_code_resync = sha204c_resync(args->rx_size, args->rx_buffer);
+				if (ret_code_resync == SHA204_SUCCESS)
+					// We did not have to wake up the device. Try receiving response again.
+					continue;
+				if (ret_code_resync == SHA204_RESYNC_WITH_WAKEUP)
+					// We could re-synchronize, but only after waking up the device.
+					// Re-send command.
+					break;
+				else
+					// We failed to re-synchronize.
+					return ret_code;
+			}
+
+			// We received a response of valid size.
+			// Check the consistency of the response.
+			ret_code = sha204c_check_crc(args->rx_buffer);
+			if (ret_code == SHA204_SUCCESS) {
+				// Received valid response.
+				if (args->rx_buffer[SHA204_BUFFER_POS_COUNT] > SHA204_RSP_SIZE_MIN)
+					// Received non-status response. We are done.
+					return ret_code;
+
+				// Received status response.
+				status_byte = args->rx_buffer[SHA204_BUFFER_POS_STATUS];
+
+				// Translate the three possible device status error codes
+				// into library return codes.
+				if (status_byte == SHA204_STATUS_BYTE_PARSE)
+					return SHA204_PARSE_ERROR;
+				if (status_byte == SHA204_STATUS_BYTE_EXEC)
+					return SHA204_CMD_FAIL;
+				if (status_byte == SHA204_STATUS_BYTE_COMM) {
+					// In case of the device status byte indicating a communication
+					// error this function exits the retry loop for receiving a response
+					// and enters the overall retry loop
+					// (send command / receive response).
+					ret_code = SHA204_STATUS_CRC;
+					break;
+				}
+
+				// Received status response from CheckMAC, DeriveKey, GenDig,
+				// Lock, Nonce, Pause, UpdateExtra, or Write command.
+				return ret_code;
+			}
+
+			else {
+				// Received response with incorrect CRC.
+				ret_code_resync = sha204c_resync(args->rx_size, args->rx_buffer);
+				if (ret_code_resync == SHA204_SUCCESS)
+					// We did not have to wake up the device. Try receiving response again.
+					continue;
+				if (ret_code_resync == SHA204_RESYNC_WITH_WAKEUP)
+					// We could re-synchronize, but only after waking up the device.
+					// Re-send command.
+					break;
+				else
+					// We failed to re-synchronize.
+					return ret_code;
+			} // block end of check response consistency
+
+		} // block end of receive retry loop
+
+	} // block end of send and receive retry loop
+
+	return ret_code;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.h
new file mode 100644
index 0000000000..c1c41f5800
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.h
@@ -0,0 +1,105 @@
+/*
+ * \file
+ *
+ * \brief ATSHA204 header file for the communication layer for the device
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SHA204_COMM_H
+#   define SHA204_COMM_H
+
+#include <compiler.h>               //!< compiler dependent definitions
+
+#include "sha204_physical.h"        //!< declarations that are common to all interface implementations
+
+//! maximum command delay
+#define SHA204_COMMAND_EXEC_MAX      (69)
+
+//! minimum number of bytes in command (from count byte to second CRC byte)
+#define SHA204_CMD_SIZE_MIN          ((uint8_t)  7)
+
+//! maximum size of command packet (CheckMac)
+#define SHA204_CMD_SIZE_MAX          ((uint8_t) 84)
+
+//! number of CRC bytes
+#define SHA204_CRC_SIZE              ((uint8_t)  2)
+
+//! buffer index of status byte in status response
+#define SHA204_BUFFER_POS_STATUS     (1)
+
+//! buffer index of first data byte in data response
+#define SHA204_BUFFER_POS_DATA       (1)
+
+//! status byte after wake-up
+#define SHA204_STATUS_BYTE_WAKEUP    ((uint8_t) 0x11)
+
+//! command parse error
+#define SHA204_STATUS_BYTE_PARSE     ((uint8_t) 0x03)
+
+//! command execution error
+#define SHA204_STATUS_BYTE_EXEC      ((uint8_t) 0x0F)
+
+//! communication error
+#define SHA204_STATUS_BYTE_COMM      ((uint8_t) 0xFF)
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204c_send_and_receive function.
+ */
+struct sha204_send_and_receive_parameters {
+	uint8_t *tx_buffer;         //!< pointer to send buffer
+	uint8_t rx_size;            //!< size of receive buffer
+	uint8_t *rx_buffer;         //!< pointer to receive buffer
+	uint8_t poll_delay;         //!< how long to wait before polling for response-ready
+	uint8_t poll_timeout;       //!< how long to poll before timing out
+};
+
+/**
+ * \defgroup sha204_communication_group SHA204 Service - hardware independent communication functions
+ * @{
+ */
+void sha204c_calculate_crc(uint8_t length, uint8_t *data, uint8_t *crc);
+uint8_t sha204c_wakeup(uint8_t *response);
+uint8_t sha204c_send_and_receive(struct sha204_send_and_receive_parameters *args);
+//! @}
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.c b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.c
new file mode 100644
index 0000000000..e2137bcd4f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.c
@@ -0,0 +1,755 @@
+/*
+ * \file
+ *
+ * \brief ATSHA204 file that implements the command marshaling layer for the device
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <string.h>                    // needed for memcpy()
+
+#include "sha204_lib_return_codes.h"   // declarations of function return codes
+#include "sha204_command_marshaling.h"    // definitions and declarations for the Command module
+
+/** \brief This function checks the parameters for sha204m_execute().
+ *
+ * \param[in, out] args pointer to parameter structure
+ * \return status of the operation
+ */
+static uint8_t sha204m_check_parameters(struct sha204_command_parameters *args)
+{
+#ifdef SHA204_CHECK_PARAMETERS
+
+	uint8_t len = args->data_len_1 + args->data_len_2 + args->data_len_3 + SHA204_CMD_SIZE_MIN;
+	if (!args->tx_buffer || args->tx_size < len || args->rx_size < SHA204_RSP_SIZE_MIN || !args->rx_buffer)
+		return SHA204_BAD_PARAM;
+
+	if ((args->data_len_1 > 0 && !args->data_1) || (args->data_len_2 > 0 && !args->data_2) || (args->data_len_3 > 0 && !args->data_3))
+		return SHA204_BAD_PARAM;
+
+	// Check parameters depending on op-code.
+	switch (args->op_code) {
+	case SHA204_CHECKMAC:
+		if (
+				// no null pointers allowed
+				!args->data_1 || !args->data_2
+				// No reserved bits should be set.
+				|| (args->param_1 | CHECKMAC_MODE_MASK) != CHECKMAC_MODE_MASK
+				// key_id > 15 not allowed
+				|| args->param_2 > SHA204_KEY_ID_MAX
+			)
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_DERIVE_KEY:
+		if (((args->param_1 & ~DERIVE_KEY_RANDOM_FLAG) != 0)
+					 || (args->param_2 > SHA204_KEY_ID_MAX))
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_DEVREV:
+		break;
+
+	case SHA204_GENDIG:
+		if ((args->param_1 != GENDIG_ZONE_OTP) && (args->param_1 != GENDIG_ZONE_DATA))
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_HMAC:
+		if ((args->param_1 & ~HMAC_MODE_MASK) != 0)
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_LOCK:
+		if (((args->param_1 & ~LOCK_ZONE_MASK) != 0)
+					|| ((args->param_1 & LOCK_ZONE_NO_CRC) && (args->param_2 != 0)))
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_MAC:
+		if (((args->param_1 & ~MAC_MODE_MASK) != 0)
+					|| (((args->param_1 & MAC_MODE_BLOCK2_TEMPKEY) == 0) && !args->data_1))
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_NONCE:
+		if (!args->data_1
+				|| (args->param_1 > NONCE_MODE_PASSTHROUGH)
+				|| (args->param_1 == NONCE_MODE_INVALID)
+			)
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_PAUSE:
+		break;
+
+	case SHA204_RANDOM:
+		if (args->param_1 > RANDOM_NO_SEED_UPDATE)
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_READ:
+		if (((args->param_1 & ~READ_ZONE_MASK) != 0)
+					|| ((args->param_1 & READ_ZONE_MODE_32_BYTES) && (args->param_1 == SHA204_ZONE_OTP)))
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_UPDATE_EXTRA:
+		if (args->param_1 > UPDATE_CONFIG_BYTE_86)
+			return SHA204_BAD_PARAM;
+		break;
+
+	case SHA204_WRITE:
+		if (!args->data_1 || ((args->param_1 & ~WRITE_ZONE_MASK) != 0))
+			return SHA204_BAD_PARAM;
+		break;
+
+	default:
+		// unknown op-code
+		return SHA204_BAD_PARAM;
+	}
+
+	return SHA204_SUCCESS;
+
+#else
+	return SHA204_SUCCESS;
+#endif
+}
+
+
+/** \brief This function creates a command packet, sends it, and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_execute(struct sha204_command_parameters *args)
+{
+	uint8_t *p_buffer;
+	uint8_t len;
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer
+	};
+
+	uint8_t ret_code = sha204m_check_parameters(args);
+	if (ret_code != SHA204_SUCCESS)
+		return ret_code;
+
+	// Supply delays and response size.
+	switch (args->op_code) {
+	case SHA204_CHECKMAC:
+		comm_parameters.poll_delay = CHECKMAC_DELAY;
+		comm_parameters.poll_timeout = CHECKMAC_EXEC_MAX - CHECKMAC_DELAY;
+		comm_parameters.rx_size = CHECKMAC_RSP_SIZE;
+		break;
+
+	case SHA204_DERIVE_KEY:
+		comm_parameters.poll_delay = DERIVE_KEY_DELAY;
+		comm_parameters.poll_timeout = DERIVE_KEY_EXEC_MAX - DERIVE_KEY_DELAY;
+		comm_parameters.rx_size = DERIVE_KEY_RSP_SIZE;
+		break;
+
+	case SHA204_DEVREV:
+		comm_parameters.poll_delay = DEVREV_DELAY;
+		comm_parameters.poll_timeout = DEVREV_EXEC_MAX - DEVREV_DELAY;
+		comm_parameters.rx_size = DEVREV_RSP_SIZE;
+		break;
+
+	case SHA204_GENDIG:
+		comm_parameters.poll_delay = GENDIG_DELAY;
+		comm_parameters.poll_timeout = GENDIG_EXEC_MAX - GENDIG_DELAY;
+		comm_parameters.rx_size = GENDIG_RSP_SIZE;
+		break;
+
+	case SHA204_HMAC:
+		comm_parameters.poll_delay = HMAC_DELAY;
+		comm_parameters.poll_timeout = HMAC_EXEC_MAX - HMAC_DELAY;
+		comm_parameters.rx_size = HMAC_RSP_SIZE;
+		break;
+
+	case SHA204_LOCK:
+		comm_parameters.poll_delay = LOCK_DELAY;
+		comm_parameters.poll_timeout = LOCK_EXEC_MAX - LOCK_DELAY;
+		comm_parameters.rx_size = LOCK_RSP_SIZE;
+		break;
+
+	case SHA204_MAC:
+		comm_parameters.poll_delay = MAC_DELAY;
+		comm_parameters.poll_timeout = MAC_EXEC_MAX - MAC_DELAY;
+		comm_parameters.rx_size = MAC_RSP_SIZE;
+		break;
+
+	case SHA204_NONCE:
+		comm_parameters.poll_delay = NONCE_DELAY;
+		comm_parameters.poll_timeout = NONCE_EXEC_MAX - NONCE_DELAY;
+		comm_parameters.rx_size = args->param_1 == NONCE_MODE_PASSTHROUGH
+							? NONCE_RSP_SIZE_SHORT : NONCE_RSP_SIZE_LONG;
+		break;
+
+	case SHA204_PAUSE:
+		comm_parameters.poll_delay = PAUSE_DELAY;
+		comm_parameters.poll_timeout = PAUSE_EXEC_MAX - PAUSE_DELAY;
+		comm_parameters.rx_size = PAUSE_RSP_SIZE;
+		break;
+
+	case SHA204_RANDOM:
+		comm_parameters.poll_delay = RANDOM_DELAY;
+		comm_parameters.poll_timeout = RANDOM_EXEC_MAX - RANDOM_DELAY;
+		comm_parameters.rx_size = RANDOM_RSP_SIZE;
+		break;
+
+	case SHA204_READ:
+		comm_parameters.poll_delay = READ_DELAY;
+		comm_parameters.poll_timeout = READ_EXEC_MAX - READ_DELAY;
+		comm_parameters.rx_size = (args->param_1 & SHA204_ZONE_COUNT_FLAG)
+							? READ_32_RSP_SIZE : READ_4_RSP_SIZE;
+		break;
+
+	case SHA204_UPDATE_EXTRA:
+		comm_parameters.poll_delay = UPDATE_DELAY;
+		comm_parameters.poll_timeout = UPDATE_EXEC_MAX - UPDATE_DELAY;
+		comm_parameters.rx_size = UPDATE_RSP_SIZE;
+		break;
+
+	case SHA204_WRITE:
+		comm_parameters.poll_delay = WRITE_DELAY;
+		comm_parameters.poll_timeout = WRITE_EXEC_MAX - WRITE_DELAY;
+		comm_parameters.rx_size = WRITE_RSP_SIZE;
+		break;
+
+	default:
+		comm_parameters.poll_delay = 0;
+		comm_parameters.poll_timeout = SHA204_COMMAND_EXEC_MAX;
+		comm_parameters.rx_size = args->rx_size;
+	}
+
+	// Assemble command.
+	len = args->data_len_1 + args->data_len_2 + args->data_len_3 + SHA204_CMD_SIZE_MIN;
+	p_buffer = args->tx_buffer;
+	*p_buffer++ = len;
+	*p_buffer++ = args->op_code;
+	*p_buffer++ = args->param_1;
+	*p_buffer++ = args->param_2 & 0xFF;
+	*p_buffer++ = args->param_2 >> 8;
+
+	if (args->data_len_1 > 0) {
+		memcpy(p_buffer, args->data_1, args->data_len_1);
+		p_buffer += args->data_len_1;
+	}
+	if (args->data_len_2 > 0) {
+		memcpy(p_buffer, args->data_2, args->data_len_2);
+		p_buffer += args->data_len_2;
+	}
+	if (args->data_len_3 > 0) {
+		memcpy(p_buffer, args->data_3, args->data_len_3);
+		p_buffer += args->data_len_3;
+	}
+
+	sha204c_calculate_crc(len - SHA204_CRC_SIZE, args->tx_buffer, p_buffer);
+
+	// Send command and receive response.
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a CheckMAC command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_check_mac(struct sha204_check_mac_parameters *args)
+{
+	if (		// no null pointers allowed
+				!args->tx_buffer || !args->rx_buffer || !args->client_response || !args->other_data
+				// No reserved bits should be set.
+				|| (args->mode | CHECKMAC_MODE_MASK) != CHECKMAC_MODE_MASK
+				// key_id > 15 not allowed
+				|| args->key_id > SHA204_KEY_ID_MAX)
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_COUNT_IDX] = CHECKMAC_COUNT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_CHECKMAC;
+	args->tx_buffer[CHECKMAC_MODE_IDX] = args->mode & CHECKMAC_MODE_MASK;
+	args->tx_buffer[CHECKMAC_KEYID_IDX]= args->key_id;
+	args->tx_buffer[CHECKMAC_KEYID_IDX + 1] = 0;
+	if (args->client_challenge == NULL)
+		memset(&args->tx_buffer[CHECKMAC_CLIENT_CHALLENGE_IDX], 0, CHECKMAC_CLIENT_CHALLENGE_SIZE);
+	else
+		memcpy(&args->tx_buffer[CHECKMAC_CLIENT_CHALLENGE_IDX], args->client_challenge, CHECKMAC_CLIENT_CHALLENGE_SIZE);
+
+	memcpy(&args->tx_buffer[CHECKMAC_CLIENT_RESPONSE_IDX], args->client_response, CHECKMAC_CLIENT_RESPONSE_SIZE);
+	memcpy(&args->tx_buffer[CHECKMAC_DATA_IDX], args->other_data, CHECKMAC_OTHER_DATA_SIZE);
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = CHECKMAC_RSP_SIZE,
+		.poll_delay = CHECKMAC_DELAY,
+		.poll_timeout = CHECKMAC_EXEC_MAX - CHECKMAC_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a DeriveKey command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_derive_key(struct sha204_derive_key_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer || ((args->use_random & ~DERIVE_KEY_RANDOM_FLAG) != 0)
+				 || (args->target_key > SHA204_KEY_ID_MAX))
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_DERIVE_KEY;
+	args->tx_buffer[DERIVE_KEY_RANDOM_IDX] = args->use_random;
+	args->tx_buffer[DERIVE_KEY_TARGETKEY_IDX] = args->target_key;
+	args->tx_buffer[DERIVE_KEY_TARGETKEY_IDX + 1] = 0;
+	if (args->mac != NULL)
+	{
+		memcpy(&args->tx_buffer[DERIVE_KEY_MAC_IDX], args->mac, DERIVE_KEY_MAC_SIZE);
+		args->tx_buffer[SHA204_COUNT_IDX] = DERIVE_KEY_COUNT_LARGE;
+	}
+	else
+		args->tx_buffer[SHA204_COUNT_IDX] = DERIVE_KEY_COUNT_SMALL;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = DERIVE_KEY_RSP_SIZE,
+		.poll_delay = DERIVE_KEY_DELAY,
+		.poll_timeout = DERIVE_KEY_EXEC_MAX - DERIVE_KEY_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a DevRev command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_dev_rev(struct sha204_dev_rev_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer)
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_COUNT_IDX] = DEVREV_COUNT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_DEVREV;
+
+	// Parameters are 0.
+	args->tx_buffer[DEVREV_PARAM1_IDX] =
+	args->tx_buffer[DEVREV_PARAM2_IDX] =
+	args->tx_buffer[DEVREV_PARAM2_IDX + 1] = 0;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = DEVREV_RSP_SIZE,
+		.poll_delay = DEVREV_DELAY,
+		.poll_timeout = DEVREV_EXEC_MAX - DEVREV_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a GenDig command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_gen_dig(struct sha204_gen_dig_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer
+				|| ((args->zone != GENDIG_ZONE_OTP) && (args->zone != GENDIG_ZONE_DATA)))
+		return SHA204_BAD_PARAM;
+
+	if (((args->zone == GENDIG_ZONE_OTP) && (args->key_id > SHA204_OTP_BLOCK_MAX))
+				|| ((args->zone == GENDIG_ZONE_DATA) && (args->key_id > SHA204_KEY_ID_MAX)))
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_GENDIG;
+	args->tx_buffer[GENDIG_ZONE_IDX] = args->zone;
+	args->tx_buffer[GENDIG_KEYID_IDX] = args->key_id;
+	args->tx_buffer[GENDIG_KEYID_IDX + 1] = 0;
+	if (args->other_data != NULL)
+	{
+		memcpy(&args->tx_buffer[GENDIG_DATA_IDX], args->other_data, GENDIG_OTHER_DATA_SIZE);
+		args->tx_buffer[SHA204_COUNT_IDX] = GENDIG_COUNT_DATA;
+	}
+	else
+		args->tx_buffer[SHA204_COUNT_IDX] = GENDIG_COUNT;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = GENDIG_RSP_SIZE,
+		.poll_delay = GENDIG_DELAY,
+		.poll_timeout = GENDIG_EXEC_MAX - GENDIG_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends an HMAC command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_hmac(struct sha204_hmac_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer || ((args->mode & ~HMAC_MODE_MASK) != 0))
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_COUNT_IDX] = HMAC_COUNT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_HMAC;
+	args->tx_buffer[HMAC_MODE_IDX] = args->mode;
+
+	// Although valid key identifiers are only
+	// from 0 to 15, all 16 bits are used in the HMAC message.
+	args->tx_buffer[HMAC_KEYID_IDX] = args->key_id & 0xFF;
+	args->tx_buffer[HMAC_KEYID_IDX + 1] = args->key_id >> 8;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = HMAC_RSP_SIZE,
+		.poll_delay = HMAC_DELAY,
+		.poll_timeout = HMAC_EXEC_MAX - HMAC_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a Lock command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_lock(struct sha204_lock_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer || ((args->zone & ~LOCK_ZONE_MASK) != 0)
+				|| ((args->zone & LOCK_ZONE_NO_CRC) && (args->summary != 0)))
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_COUNT_IDX] = LOCK_COUNT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_LOCK;
+	args->tx_buffer[LOCK_ZONE_IDX] = args->zone & LOCK_ZONE_MASK;
+	args->tx_buffer[LOCK_SUMMARY_IDX]= args->summary & 0xFF;
+	args->tx_buffer[LOCK_SUMMARY_IDX + 1]= args->summary >> 8;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = LOCK_RSP_SIZE,
+		.poll_delay = LOCK_DELAY,
+		.poll_timeout = LOCK_EXEC_MAX - LOCK_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a MAC command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_mac(struct sha204_mac_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer || ((args->mode & ~MAC_MODE_MASK) != 0)
+				|| (((args->mode & MAC_MODE_BLOCK2_TEMPKEY) == 0) && !args->challenge))
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_COUNT_IDX] = MAC_COUNT_SHORT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_MAC;
+	args->tx_buffer[MAC_MODE_IDX] = args->mode;
+	args->tx_buffer[MAC_KEYID_IDX] = args->key_id & 0xFF;
+	args->tx_buffer[MAC_KEYID_IDX + 1] = args->key_id >> 8;
+	if ((args->mode & MAC_MODE_BLOCK2_TEMPKEY) == 0)
+	{
+		memcpy(&args->tx_buffer[MAC_CHALLENGE_IDX], args->challenge, MAC_CHALLENGE_SIZE);
+		args->tx_buffer[SHA204_COUNT_IDX] = MAC_COUNT_LONG;
+	}
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = MAC_RSP_SIZE,
+		.poll_delay = MAC_DELAY,
+		.poll_timeout = MAC_EXEC_MAX - MAC_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a Nonce command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_nonce(struct sha204_nonce_parameters *args)
+{
+	uint8_t rx_size;
+
+	if (!args->tx_buffer || !args->rx_buffer || !args->num_in
+				|| (args->mode > NONCE_MODE_PASSTHROUGH) || (args->mode == NONCE_MODE_INVALID))
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_NONCE;
+	args->tx_buffer[NONCE_MODE_IDX] = args->mode;
+
+	// 2. parameter is 0.
+	args->tx_buffer[NONCE_PARAM2_IDX] =
+	args->tx_buffer[NONCE_PARAM2_IDX + 1] = 0;
+
+	if (args->mode != NONCE_MODE_PASSTHROUGH)
+	{
+		memcpy(&args->tx_buffer[NONCE_INPUT_IDX], args->num_in, NONCE_NUMIN_SIZE);
+		args->tx_buffer[SHA204_COUNT_IDX] = NONCE_COUNT_SHORT;
+		rx_size = NONCE_RSP_SIZE_LONG;
+	}
+	else
+	{
+		memcpy(&args->tx_buffer[NONCE_INPUT_IDX], args->num_in, NONCE_NUMIN_SIZE_PASSTHROUGH);
+		args->tx_buffer[SHA204_COUNT_IDX] = NONCE_COUNT_LONG;
+		rx_size = NONCE_RSP_SIZE_SHORT;
+	}
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = rx_size,
+		.poll_delay = NONCE_DELAY,
+		.poll_timeout = NONCE_EXEC_MAX - NONCE_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a Pause command to SWI devices and receives a response from the selected device.
+ *         All others pause.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_pause(struct sha204_pause_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer)
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_COUNT_IDX] = PAUSE_COUNT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_PAUSE;
+	args->tx_buffer[PAUSE_SELECT_IDX] = args->selector;
+
+	// 2. parameter is 0.
+	args->tx_buffer[PAUSE_PARAM2_IDX] =
+	args->tx_buffer[PAUSE_PARAM2_IDX + 1] = 0;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = PAUSE_RSP_SIZE,
+		.poll_delay = PAUSE_DELAY,
+		.poll_timeout = PAUSE_EXEC_MAX - PAUSE_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a Random command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_random(struct sha204_random_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer || (args->mode > RANDOM_NO_SEED_UPDATE))
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_COUNT_IDX] = RANDOM_COUNT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_RANDOM;
+	args->tx_buffer[RANDOM_MODE_IDX] = args->mode & RANDOM_SEED_UPDATE;
+
+	// 2. parameter is 0.
+	args->tx_buffer[RANDOM_PARAM2_IDX] =
+	args->tx_buffer[RANDOM_PARAM2_IDX + 1] = 0;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = RANDOM_RSP_SIZE,
+		.poll_delay = RANDOM_DELAY,
+		.poll_timeout = RANDOM_EXEC_MAX - RANDOM_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends a Read command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_read(struct sha204_read_parameters *args)
+{
+	uint8_t rx_size;
+	uint16_t address;
+
+	if (!args->tx_buffer || !args->rx_buffer || ((args->zone & ~READ_ZONE_MASK) != 0)
+				|| ((args->zone & READ_ZONE_MODE_32_BYTES) && (args->zone == SHA204_ZONE_OTP)))
+		return SHA204_BAD_PARAM;
+
+	// If we would just mask address bits, we would
+	// read from an address that was not intended.
+	address = args->address >> 2;
+	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_CONFIG) {
+		if (address > SHA204_ADDRESS_MASK_CONFIG)
+			return SHA204_BAD_PARAM;
+	}		
+	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_OTP) {
+		if (address > SHA204_ADDRESS_MASK_OTP)
+			// If we would just mask this bit, we would
+			// read from an address that was not intended.
+			return SHA204_BAD_PARAM;
+	}		
+	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_DATA) {
+		if (address > SHA204_ADDRESS_MASK)
+			// If we would just mask this bit, we would
+			// read from an address that was not intended.
+			return SHA204_BAD_PARAM;
+	}
+
+	args->tx_buffer[SHA204_COUNT_IDX] = READ_COUNT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_READ;
+	args->tx_buffer[READ_ZONE_IDX] = args->zone;
+	args->tx_buffer[READ_ADDR_IDX] = (uint8_t) address;
+	args->tx_buffer[READ_ADDR_IDX + 1] = 0;
+
+	rx_size = (args->zone & SHA204_ZONE_COUNT_FLAG) ? READ_32_RSP_SIZE : READ_4_RSP_SIZE;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = rx_size,
+		.poll_delay = READ_DELAY,
+		.poll_timeout = READ_EXEC_MAX - READ_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/** \brief This function sends an UpdateExtra command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_update_extra(struct sha204_update_extra_parameters *args)
+{
+	if (!args->tx_buffer || !args->rx_buffer || (args->mode > UPDATE_CONFIG_BYTE_86))
+		return SHA204_BAD_PARAM;
+
+	args->tx_buffer[SHA204_COUNT_IDX] = UPDATE_COUNT;
+	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_UPDATE_EXTRA;
+	args->tx_buffer[UPDATE_MODE_IDX] = args->mode;
+	args->tx_buffer[UPDATE_VALUE_IDX] = args->new_value;
+	args->tx_buffer[UPDATE_VALUE_IDX + 1] = 0;
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = UPDATE_RSP_SIZE,
+		.poll_delay = UPDATE_DELAY,
+		.poll_timeout = UPDATE_EXEC_MAX - UPDATE_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
+
+
+/**\brief This function sends a Write command to the device and receives its response.
+ * \param[in, out]  args pointer to parameter structure
+ * \return status of the operation
+ */
+uint8_t sha204m_write(struct sha204_write_parameters *args)
+{
+	uint8_t *p_command;
+	uint8_t count;
+	uint16_t address;
+
+	if (!args->tx_buffer || !args->rx_buffer || !args->new_value || ((args->zone & ~WRITE_ZONE_MASK) != 0))
+		return SHA204_BAD_PARAM;
+
+	// If we would just mask address bits, we would
+	// read from an address that was not intended.
+	address = args->address >> 2;
+	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_CONFIG) {
+		if (address > SHA204_ADDRESS_MASK_CONFIG)
+			return SHA204_BAD_PARAM;
+	}		
+	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_OTP) {
+		if (address > SHA204_ADDRESS_MASK_OTP)
+			// If we would just mask this bit, we would
+			// read from an address that was not intended.
+			return SHA204_BAD_PARAM;
+	}		
+	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_DATA) {
+		if (address > SHA204_ADDRESS_MASK)
+			// If we would just mask this bit, we would
+			// read from an address that was not intended.
+			return SHA204_BAD_PARAM;
+	}
+
+	p_command = &args->tx_buffer[SHA204_OPCODE_IDX];
+	*p_command++ = SHA204_WRITE;
+	*p_command++ = args->zone;
+	*p_command++ = (uint8_t) address;
+	*p_command++ = 0;
+
+	count = (args->zone & SHA204_ZONE_COUNT_FLAG) ? SHA204_ZONE_ACCESS_32 : SHA204_ZONE_ACCESS_4;
+	memcpy(p_command, args->new_value, count);
+	p_command += count;
+
+	if (args->mac != NULL)
+	{
+		memcpy(p_command, args->mac, WRITE_MAC_SIZE);
+		p_command += WRITE_MAC_SIZE;
+	}
+
+	// Supply count.
+	args->tx_buffer[SHA204_COUNT_IDX] = (uint8_t) (p_command - &args->tx_buffer[0] + SHA204_CRC_SIZE);
+
+	struct sha204_send_and_receive_parameters comm_parameters = {
+		.tx_buffer = args->tx_buffer,
+		.rx_buffer = args->rx_buffer,
+		.rx_size = WRITE_RSP_SIZE,
+		.poll_delay = WRITE_DELAY,
+		.poll_timeout = WRITE_EXEC_MAX - WRITE_DELAY
+	};
+	return sha204c_send_and_receive(&comm_parameters);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.h
new file mode 100644
index 0000000000..ed5bcc631b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.h
@@ -0,0 +1,539 @@
+/*
+ * \file
+ *
+ * \brief ATSHA204 header file for the command marshaling layer for the device
+ *
+   <table>
+     <caption>Command Packet Structure</caption>
+     <tr>
+       <th width=25%>Byte #</th> <th width=25%>Name</th> <th>Meaning</th>
+     </tr>
+     <tr>
+       <td>0</td>
+       <td>Count</td>
+       <td>Number of bytes in the packet, includes the count byte, body and the checksum</td>
+     </tr>
+     <tr>
+       <td>1</td>
+       <td>Ordinal</td>
+       <td>Command Opcode (Ordinal)</td>
+     </tr>
+     <tr>
+       <td>2 to n</td>
+       <td>Parameters</td>
+       <td>Parameters for specific command</td>
+     </tr>
+     <tr>
+       <td>n+1 to n+2</td>
+       <td>Checksum</td>
+       <td>Checksum of the command packet</td>
+     </tr>
+   </table>
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SHA204_COMMAND_MARSHALING_H
+#   define SHA204_COMMAND_MARSHALING_H
+
+#include "sha204_comm.h"
+
+/** \todo Create doxygen groups. */
+
+//////////////////////////////////////////////////////////////////////
+// command op-code definitions
+#define SHA204_CHECKMAC                 ((uint8_t) 0x28)       //!< CheckMac command op-code
+#define SHA204_DERIVE_KEY               ((uint8_t) 0x1C)       //!< DeriveKey command op-code
+#define SHA204_DEVREV                   ((uint8_t) 0x30)       //!< DevRev command op-code
+#define SHA204_GENDIG                   ((uint8_t) 0x15)       //!< GenDig command op-code
+#define SHA204_HMAC                     ((uint8_t) 0x11)       //!< HMAC command op-code
+#define SHA204_LOCK                     ((uint8_t) 0x17)       //!< Lock command op-code
+#define SHA204_MAC                      ((uint8_t) 0x08)       //!< MAC command op-code
+#define SHA204_NONCE                    ((uint8_t) 0x16)       //!< Nonce command op-code
+#define SHA204_PAUSE                    ((uint8_t) 0x01)       //!< Pause command op-code
+#define SHA204_RANDOM                   ((uint8_t) 0x1B)       //!< Random command op-code
+#define SHA204_READ                     ((uint8_t) 0x02)       //!< Read command op-code
+#define SHA204_UPDATE_EXTRA             ((uint8_t) 0x20)       //!< UpdateExtra command op-code
+#define SHA204_WRITE                    ((uint8_t) 0x12)       //!< Write command op-code
+
+
+//////////////////////////////////////////////////////////////////////
+// packet size definitions
+#define SHA204_RSP_SIZE_VAL             ((uint8_t)  7)         //!< size of response packet containing four bytes of data
+
+//////////////////////////////////////////////////////////////////////
+// parameter range definitions
+#define SHA204_KEY_ID_MAX               ((uint8_t) 15)         //!< maximum value for key id
+#define SHA204_OTP_BLOCK_MAX            ((uint8_t)  1)         //!< maximum value for OTP block
+
+//////////////////////////////////////////////////////////////////////
+// definitions for command packet indexes common to all commands
+#define SHA204_COUNT_IDX                ( 0)                   //!< command packet index for count
+#define SHA204_OPCODE_IDX               ( 1)                   //!< command packet index for op-code
+#define SHA204_PARAM1_IDX               ( 2)                   //!< command packet index for first parameter
+#define SHA204_PARAM2_IDX               ( 3)                   //!< command packet index for second parameter
+#define SHA204_DATA_IDX                 ( 5)                   //!< command packet index for second parameter
+
+//////////////////////////////////////////////////////////////////////
+// zone definitions
+#define SHA204_ZONE_CONFIG              ((uint8_t)  0x00)      //!< Configuration zone
+#define SHA204_ZONE_OTP                 ((uint8_t)  0x01)      //!< OTP (One Time Programming) zone
+#define SHA204_ZONE_DATA                ((uint8_t)  0x02)      //!< Data zone
+#define SHA204_ZONE_MASK                ((uint8_t)  0x03)      //!< Zone mask
+#define SHA204_ZONE_COUNT_FLAG          ((uint8_t)  0x80)      //!< Zone bit 7 set: Access 32 bytes, otherwise 4 bytes.
+#define SHA204_ZONE_ACCESS_4            ((uint8_t)     4)      //!< Read or write 4 bytes.
+#define SHA204_ZONE_ACCESS_32           ((uint8_t)    32)      //!< Read or write 32 bytes.
+#define SHA204_ADDRESS_MASK_CONFIG      (         0x001F)      //!< Address bits 5 to 7 are 0 for Configuration zone.
+#define SHA204_ADDRESS_MASK_OTP         (         0x000F)      //!< Address bits 4 to 7 are 0 for OTP zone.
+#define SHA204_ADDRESS_MASK             (         0x007F)    //!< Address bit 7 to 15 are always 0.
+
+//////////////////////////////////////////////////////////////////////
+// CheckMAC command definitions
+#define CHECKMAC_MODE_IDX               SHA204_PARAM1_IDX      //!< CheckMAC command index for mode
+#define CHECKMAC_KEYID_IDX              SHA204_PARAM2_IDX      //!< CheckMAC command index for key identifier
+#define CHECKMAC_CLIENT_CHALLENGE_IDX   SHA204_DATA_IDX        //!< CheckMAC command index for client challenge
+#define CHECKMAC_CLIENT_RESPONSE_IDX    (37)                   //!< CheckMAC command index for client response
+#define CHECKMAC_DATA_IDX               (69)                   //!< CheckMAC command index for other data
+#define CHECKMAC_COUNT                  (84)                   //!< CheckMAC command packet size
+#define CHECKMAC_MODE_MASK              ((uint8_t) 0x27)       //!< CheckMAC mode bits 3, 4, 6, and 7 are 0.
+#define CHECKMAC_CLIENT_CHALLENGE_SIZE  (32)                   //!< CheckMAC size of client challenge
+#define CHECKMAC_CLIENT_RESPONSE_SIZE   (32)                   //!< CheckMAC size of client response
+#define CHECKMAC_OTHER_DATA_SIZE        (13)                   //!< CheckMAC size of "other data"
+#define CHECKMAC_CLIENT_COMMAND_SIZE    ( 4)                   //!< CheckMAC size of client command header size inside "other data"
+
+//////////////////////////////////////////////////////////////////////
+// DeriveKey command definitions
+#define DERIVE_KEY_RANDOM_IDX           SHA204_PARAM1_IDX      //!< DeriveKey command index for random bit
+#define DERIVE_KEY_TARGETKEY_IDX        SHA204_PARAM2_IDX      //!< DeriveKey command index for target slot
+#define DERIVE_KEY_MAC_IDX              SHA204_DATA_IDX        //!< DeriveKey command index for optional MAC
+#define DERIVE_KEY_COUNT_SMALL          SHA204_CMD_SIZE_MIN    //!< DeriveKey command packet size without MAC
+#define DERIVE_KEY_COUNT_LARGE          (39)                   //!< DeriveKey command packet size with MAC
+#define DERIVE_KEY_RANDOM_FLAG          ((uint8_t) 4)          //!< DeriveKey 1. parameter
+#define DERIVE_KEY_MAC_SIZE             (32)                   //!< DeriveKey MAC size
+
+//////////////////////////////////////////////////////////////////////
+// DevRev command definitions
+#define DEVREV_PARAM1_IDX               SHA204_PARAM1_IDX      //!< DevRev command index for 1. parameter (ignored)
+#define DEVREV_PARAM2_IDX               SHA204_PARAM2_IDX      //!< DevRev command index for 2. parameter (ignored)
+#define DEVREV_COUNT                    SHA204_CMD_SIZE_MIN    //!< DevRev command packet size
+
+//////////////////////////////////////////////////////////////////////
+// GenDig command definitions
+#define GENDIG_ZONE_IDX                 SHA204_PARAM1_IDX      //!< GenDig command index for zone
+#define GENDIG_KEYID_IDX                SHA204_PARAM2_IDX      //!< GenDig command index for key id
+#define GENDIG_DATA_IDX                 SHA204_DATA_IDX        //!< GenDig command index for optional data
+#define GENDIG_COUNT                    SHA204_CMD_SIZE_MIN    //!< GenDig command packet size without "other data"
+#define GENDIG_COUNT_DATA               (11)                   //!< GenDig command packet size with "other data"
+#define GENDIG_OTHER_DATA_SIZE          (4)                    //!< GenDig size of "other data"
+#define GENDIG_ZONE_OTP                 ((uint8_t) 1)          //!< GenDig zone id OTP
+#define GENDIG_ZONE_DATA                ((uint8_t) 2)          //!< GenDig zone id data
+
+//////////////////////////////////////////////////////////////////////
+// HMAC command definitions
+#define HMAC_MODE_IDX                   SHA204_PARAM1_IDX      //!< HMAC command index for mode
+#define HMAC_KEYID_IDX                  SHA204_PARAM2_IDX      //!< HMAC command index for key id
+#define HMAC_COUNT                      SHA204_CMD_SIZE_MIN    //!< HMAC command packet size
+#define HMAC_MODE_MASK                  ((uint8_t) 0x74)       //!< HMAC mode bits 0, 1, 3, and 7 are 0.
+
+//////////////////////////////////////////////////////////////////////
+// Lock command definitions
+#define LOCK_ZONE_IDX                   SHA204_PARAM1_IDX      //!< Lock command index for zone
+#define LOCK_SUMMARY_IDX                SHA204_PARAM2_IDX      //!< Lock command index for summary
+#define LOCK_COUNT                      SHA204_CMD_SIZE_MIN    //!< Lock command packet size
+#define LOCK_ZONE_NO_CONFIG             ((uint8_t) 0x01)       //!< Lock zone is OTP or Data
+#define LOCK_ZONE_NO_CRC                ((uint8_t) 0x80)       //!< Lock command: Ignore summary.
+#define LOCK_ZONE_MASK                  (0x81)                 //!< Lock parameter 1 bits 2 to 6 are 0.
+
+//////////////////////////////////////////////////////////////////////
+// Mac command definitions
+#define MAC_MODE_IDX                    SHA204_PARAM1_IDX      //!< MAC command index for mode
+#define MAC_KEYID_IDX                   SHA204_PARAM2_IDX      //!< MAC command index for key id
+#define MAC_CHALLENGE_IDX               SHA204_DATA_IDX        //!< MAC command index for optional challenge
+#define MAC_COUNT_SHORT                 SHA204_CMD_SIZE_MIN    //!< MAC command packet size without challenge
+#define MAC_COUNT_LONG                  (39)                   //!< MAC command packet size with challenge
+#define MAC_MODE_BLOCK2_TEMPKEY         ((uint8_t) 0x01)       //!< MAC mode bit   0: second SHA block from TempKey
+#define MAC_MODE_BLOCK1_TEMPKEY         ((uint8_t) 0x02)       //!< MAC mode bit   1: first SHA block from TempKey
+#define MAC_MODE_SOURCE_FLAG_MATCH      ((uint8_t) 0x04)       //!< MAC mode bit   2: match TempKey.SourceFlag
+#define MAC_MODE_PASSTHROUGH            ((uint8_t) 0x07)       //!< MAC mode bit 0-2: pass-through mode
+#define MAC_MODE_INCLUDE_OTP_88         ((uint8_t) 0x10)       //!< MAC mode bit   4: include first 88 OTP bits
+#define MAC_MODE_INCLUDE_OTP_64         ((uint8_t) 0x20)       //!< MAC mode bit   5: include first 64 OTP bits
+#define MAC_MODE_INCLUDE_SN             ((uint8_t) 0x50)       //!< MAC mode bit   6: include serial number
+#define MAC_CHALLENGE_SIZE              (32)                   //!< MAC size of challenge
+#define MAC_MODE_MASK                   ((uint8_t) 0x77)       //!< MAC mode bits 3 and 7 are 0.
+
+
+//////////////////////////////////////////////////////////////////////
+// Nonce command definitions
+#define NONCE_MODE_IDX                  SHA204_PARAM1_IDX      //!< Nonce command index for mode
+#define NONCE_PARAM2_IDX                SHA204_PARAM2_IDX      //!< Nonce command index for 2. parameter
+#define NONCE_INPUT_IDX                 SHA204_DATA_IDX        //!< Nonce command index for input data
+#define NONCE_COUNT_SHORT               (27)                   //!< Nonce command packet size for 20 bytes of data
+#define NONCE_COUNT_LONG                (39)                   //!< Nonce command packet size for 32 bytes of data
+#define NONCE_MODE_MASK                 ((uint8_t) 3)          //!< Nonce mode bits 2 to 7 are 0.
+#define NONCE_MODE_SEED_UPDATE          ((uint8_t) 0x00)       //!< Nonce mode: update seed
+#define NONCE_MODE_NO_SEED_UPDATE       ((uint8_t) 0x01)       //!< Nonce mode: do not update seed
+#define NONCE_MODE_INVALID              ((uint8_t) 0x02)       //!< Nonce mode 2 is invalid.
+#define NONCE_MODE_PASSTHROUGH          ((uint8_t) 0x03)       //!< Nonce mode: pass-through
+#define NONCE_NUMIN_SIZE                (20)                   //!< Nonce data length
+#define NONCE_NUMIN_SIZE_PASSTHROUGH    (32)                   //!< Nonce data length in pass-through mode (mode = 3)
+
+//////////////////////////////////////////////////////////////////////
+// Pause command definitions
+#define PAUSE_SELECT_IDX                SHA204_PARAM1_IDX      //!< Pause command index for Selector
+#define PAUSE_PARAM2_IDX                SHA204_PARAM2_IDX      //!< Pause command index for 2. parameter
+#define PAUSE_COUNT                     SHA204_CMD_SIZE_MIN    //!< Pause command packet size
+
+//////////////////////////////////////////////////////////////////////
+// Random command definitions
+#define RANDOM_MODE_IDX                 SHA204_PARAM1_IDX      //!< Random command index for mode
+#define RANDOM_PARAM2_IDX               SHA204_PARAM2_IDX      //!< Random command index for 2. parameter
+#define RANDOM_COUNT                    SHA204_CMD_SIZE_MIN    //!< Random command packet size
+#define RANDOM_SEED_UPDATE              ((uint8_t) 0x00)       //!< Random mode for automatic seed update
+#define RANDOM_NO_SEED_UPDATE           ((uint8_t) 0x01)       //!< Random mode for no seed update
+
+//////////////////////////////////////////////////////////////////////
+// Read command definitions
+#define READ_ZONE_IDX                   SHA204_PARAM1_IDX      //!< Read command index for zone
+#define READ_ADDR_IDX                   SHA204_PARAM2_IDX      //!< Read command index for address
+#define READ_COUNT                      SHA204_CMD_SIZE_MIN    //!< Read command packet size
+#define READ_ZONE_MASK                  ((uint8_t) 0x83)       //!< Read zone bits 2 to 6 are 0.
+#define READ_ZONE_MODE_32_BYTES         ((uint8_t) 0x80)       //!< Read mode: 32 bytes
+
+//////////////////////////////////////////////////////////////////////
+// UpdateExtra command definitions
+#define UPDATE_MODE_IDX                  SHA204_PARAM1_IDX     //!< UpdateExtra command index for mode
+#define UPDATE_VALUE_IDX                 SHA204_PARAM2_IDX     //!< UpdateExtra command index for new value
+#define UPDATE_COUNT                     SHA204_CMD_SIZE_MIN   //!< UpdateExtra command packet size
+#define UPDATE_CONFIG_BYTE_86            ((uint8_t) 0x01)      //!< UpdateExtra mode: update Config byte 86
+
+//////////////////////////////////////////////////////////////////////
+// Write command definitions
+#define WRITE_ZONE_IDX                  SHA204_PARAM1_IDX      //!< Write command index for zone
+#define WRITE_ADDR_IDX                  SHA204_PARAM2_IDX      //!< Write command index for address
+#define WRITE_VALUE_IDX                 SHA204_DATA_IDX        //!< Write command index for data
+#define WRITE_MAC_VS_IDX                ( 9)                   //!< Write command index for MAC following short data
+#define WRITE_MAC_VL_IDX                (37)                   //!< Write command index for MAC following long data
+#define WRITE_COUNT_SHORT               (11)                   //!< Write command packet size with short data and no MAC
+#define WRITE_COUNT_LONG                (39)                   //!< Write command packet size with long data and no MAC
+#define WRITE_COUNT_SHORT_MAC           (43)                   //!< Write command packet size with short data and MAC
+#define WRITE_COUNT_LONG_MAC            (71)                   //!< Write command packet size with long data and MAC
+#define WRITE_MAC_SIZE                  (32)                   //!< Write MAC size
+#define WRITE_ZONE_MASK                 ((uint8_t) 0xC1)       //!< Write zone bits 2 to 5 are 0.
+#define WRITE_ZONE_WITH_MAC             ((uint8_t) 0x40)       //!< Write zone bit 6: write encrypted with MAC
+
+//////////////////////////////////////////////////////////////////////
+// Response size definitions
+#define CHECKMAC_RSP_SIZE               SHA204_RSP_SIZE_MIN    //!< response size of DeriveKey command
+#define DERIVE_KEY_RSP_SIZE             SHA204_RSP_SIZE_MIN    //!< response size of DeriveKey command
+#define DEVREV_RSP_SIZE                 SHA204_RSP_SIZE_VAL    //!< response size of DevRev command returns 4 bytes
+#define GENDIG_RSP_SIZE                 SHA204_RSP_SIZE_MIN    //!< response size of GenDig command
+#define HMAC_RSP_SIZE                   SHA204_RSP_SIZE_MAX    //!< response size of HMAC command
+#define LOCK_RSP_SIZE                   SHA204_RSP_SIZE_MIN    //!< response size of Lock command
+#define MAC_RSP_SIZE                    SHA204_RSP_SIZE_MAX    //!< response size of MAC command
+#define NONCE_RSP_SIZE_SHORT            SHA204_RSP_SIZE_MIN    //!< response size of Nonce command with mode[0:1] = 3
+#define NONCE_RSP_SIZE_LONG             SHA204_RSP_SIZE_MAX    //!< response size of Nonce command
+#define PAUSE_RSP_SIZE                  SHA204_RSP_SIZE_MIN    //!< response size of Pause command
+#define RANDOM_RSP_SIZE                 SHA204_RSP_SIZE_MAX    //!< response size of Random command
+#define READ_4_RSP_SIZE                 SHA204_RSP_SIZE_VAL    //!< response size of Read command when reading 4 bytes
+#define READ_32_RSP_SIZE                SHA204_RSP_SIZE_MAX    //!< response size of Read command when reading 32 bytes
+#define UPDATE_RSP_SIZE                 SHA204_RSP_SIZE_MIN    //!< response size of UpdateExtra command
+#define WRITE_RSP_SIZE                  SHA204_RSP_SIZE_MIN    //!< response size of Write command
+
+//////////////////////////////////////////////////////////////////////
+// command timing definitions for typical execution times (ms)
+//! CheckMAC typical command delay
+#define CHECKMAC_DELAY                  (12)
+
+//! DeriveKey typical command delay
+#define DERIVE_KEY_DELAY                (14)
+
+//! DevRev typical command delay
+#define DEVREV_DELAY                    ( 1)  // 0.4 rounded up
+
+//! GenDig typical command delay
+#define GENDIG_DELAY                    (11)
+
+//! HMAC typical command delay
+#define HMAC_DELAY                      (27)
+
+//! Lock typical command delay
+#define LOCK_DELAY                      ( 5)
+
+//! MAC typical command delay
+#define MAC_DELAY                       (12)
+
+//! Nonce typical command delay
+#define NONCE_DELAY                     (22)
+
+//! Pause typical command delay
+#define PAUSE_DELAY                     ( 1)  // 0.4 rounded up
+
+//! Random typical command delay
+#define RANDOM_DELAY                    (11)
+
+//! Read typical command delay
+#define READ_DELAY                      ( 1)  // 0.4 rounded up
+
+//! UpdateExtra typical command delay
+#define UPDATE_DELAY                    ( 8)
+
+//! Write typical command delay
+#define WRITE_DELAY                     ( 4)
+
+//////////////////////////////////////////////////////////////////////
+// command timing definitions for maximum execution times (ms)
+//! CheckMAC maximum execution time
+#define CHECKMAC_EXEC_MAX                (38)
+
+//! DeriveKey maximum execution time
+#define DERIVE_KEY_EXEC_MAX              (62)
+
+//! DevRev maximum execution time
+#define DEVREV_EXEC_MAX                  ( 2)
+
+//! GenDig maximum execution time
+#define GENDIG_EXEC_MAX                  (43)
+
+//! HMAC maximum execution time
+#define HMAC_EXEC_MAX                    (69)
+
+//! Lock maximum execution time
+#define LOCK_EXEC_MAX                    (24)
+
+//! MAC maximum execution time
+#define MAC_EXEC_MAX                     (35)
+
+//! Nonce maximum execution time
+#define NONCE_EXEC_MAX                   (60)
+
+//! Pause maximum execution time
+#define PAUSE_EXEC_MAX                   ( 2)
+
+//! Random maximum execution time
+#define RANDOM_EXEC_MAX                  (50)
+
+//! Read maximum execution time
+#define READ_EXEC_MAX                    ( 4)
+
+//! UpdateExtra maximum execution time
+#define UPDATE_EXEC_MAX                  (12)
+
+//! Write maximum execution time
+#define WRITE_EXEC_MAX                   (42)
+
+//////////////////////////////////////////////////////////////////////
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_check_mac function.
+ */
+struct sha204_check_mac_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t mode;              //!< what to include in the MAC calculation
+   uint8_t key_id;            //!< what key to use for the MAC calculation
+   uint8_t *client_challenge; //!< pointer to challenge that host had sent to client
+   uint8_t *client_response;  //!< pointer to challenge response received from client 
+   uint8_t *other_data;       //!< pointer to 13 bytes of data that were used by client to calculate MAC
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_derive_key function.
+ */
+struct sha204_derive_key_parameters {
+   uint8_t *tx_buffer;   	//!< pointer to send buffer
+   uint8_t *rx_buffer;   	//!< pointer to receive buffer
+   uint8_t use_random;   	//!< true if source for TempKey was random number
+   uint8_t target_key;   	//!< slot where derived key should be stored
+   uint8_t *mac;	     	   //!< pointer to MAC for this command
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_dev_rev function.
+ */
+struct sha204_dev_rev_parameters {
+   uint8_t *tx_buffer;   	//!< pointer to send buffer
+   uint8_t *rx_buffer;		//!< pointer to receive buffer
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_gen_dig function.
+ */
+struct sha204_gen_dig_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t zone;              //!< what zone (config, OTP, or data) to use in the digest calculation
+   uint8_t key_id;            //!< what key or OTP block to use for the digest calculation
+   uint8_t *other_data;       //!< pointer to four bytes of data to use for the digest calculation, only needed when key is CheckMac only key 
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_hmac function.
+ */
+struct sha204_hmac_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t mode;              //!< what to include in the HMAC calculation
+   uint16_t key_id;           //!< what key to use for the HMAC calculation
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_lock function.
+ */
+struct sha204_lock_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t zone;              //!< what zone (config, OTP, or data) to lock
+   uint16_t summary;          //!< CRC over the zone to be locked
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_mac function.
+ */
+struct sha204_mac_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t mode;              //!< what to include in the MAC calculation
+   uint16_t key_id;           //!< what key to use for the MAC calculation
+   uint8_t *challenge;        //!< pointer to 32 bytes of challenge data to be sent to client
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_nonce function.
+ */
+struct sha204_nonce_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t mode;              //!< what TempKey should be loaded with
+   uint8_t *num_in;           //!< pointer to 20 bytes of input or 32 bytes of pass-through data
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_pause function.
+ */
+struct sha204_pause_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t selector;          //!< which device not to set into Idle mode (single-wire interface only)
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_random function.
+ */
+struct sha204_random_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t mode;              //!< true if existing EEPROM seed should be used
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_read function.
+ */
+struct sha204_read_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t zone;              //!< what zone (config, OTP, or data) to read from and how many bytes (4 or 32)
+   uint16_t address;          //!< what address to read from
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_update_extra function.
+ */
+struct sha204_update_extra_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t mode;              //!< config byte address = 84 + mode (0 or 1)
+   uint8_t new_value;         //!< value to write
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_write function.
+ */
+struct sha204_write_parameters {
+   uint8_t *tx_buffer;        //!< pointer to send buffer
+   uint8_t *rx_buffer;        //!< pointer to receive buffer
+   uint8_t zone;              //!< what zone (config, OTP, or data) to write to, how many bytes (4 or 32), and whether data are encrypted
+   uint16_t address;          //!< what address to write to
+   uint8_t *new_value;        //!< pointer to 4 or 32 bytes of data to be written
+   uint8_t *mac;              //!< pointer to MAC of this command (null if zone is unlocked) 
+};
+
+/** 
+ * \brief This structure contains the parameters for the \ref sha204m_execute function.
+ */
+struct sha204_command_parameters {
+	uint8_t op_code;      //!< command code
+	uint8_t param_1;      //!< parameter 1
+	uint16_t param_2;     //!< parameter 2
+	uint8_t data_len_1;   //!< length of data field 1
+	uint8_t data_len_2;   //!< length of data field 2
+	uint8_t data_len_3;   //!< length of data field 3
+	uint8_t *data_1;      //!< pointer to data field 1
+	uint8_t *data_2;      //!< pointer to data field 2
+	uint8_t *data_3;      //!< pointer to data field 3
+	uint8_t *tx_buffer;   //!< pointer to send buffer
+	uint8_t *rx_buffer;   //!< pointer to receive buffer
+	uint8_t tx_size;      //!< size of supplied send buffer
+	uint8_t rx_size;      //!< size of supplied receive buffer
+};
+	
+/**
+ * \defgroup sha204_command_marshaling_group SHA204 Service - command marshaling functions
+ *
+ * @{
+ */
+uint8_t sha204m_check_mac(struct sha204_check_mac_parameters *args);
+uint8_t sha204m_derive_key(struct sha204_derive_key_parameters *args);
+uint8_t sha204m_dev_rev(struct sha204_dev_rev_parameters *args);
+uint8_t sha204m_gen_dig(struct sha204_gen_dig_parameters *args);
+uint8_t sha204m_hmac(struct sha204_hmac_parameters *args);
+uint8_t sha204m_lock(struct sha204_lock_parameters *args);
+uint8_t sha204m_mac(struct sha204_mac_parameters *args);
+uint8_t sha204m_nonce(struct sha204_nonce_parameters *args);
+uint8_t sha204m_pause(struct sha204_pause_parameters *args);
+uint8_t sha204m_random(struct sha204_random_parameters *args);
+uint8_t sha204m_read(struct sha204_read_parameters *args);
+uint8_t sha204m_update_extra(struct sha204_update_extra_parameters *args);
+uint8_t sha204m_write(struct sha204_write_parameters *args);
+uint8_t sha204m_execute(struct sha204_command_parameters *args);
+//! @}
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_config.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_config.h
new file mode 100644
index 0000000000..14a7a6deac
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_config.h
@@ -0,0 +1,63 @@
+/*
+ * \file
+ *
+ *  \brief  Definitions for Configurable Values of the ATSHA204 Library
+ *
+ *  This file contains configurations for the ATSHA204 modules.
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SHA204_CONFIG_H
+#   define SHA204_CONFIG_H
+
+/** \brief number of command / response retries
+ *
+ * If communication is lost, re-synchronization includes waiting for the
+ * longest possible execution time of a command.
+ * This adds a #SHA204_COMMAND_EXEC_MAX delay to every retry.
+ * Every increment of the number of retries increases the time
+ * the library is spending in the retry loop by #SHA204_COMMAND_EXEC_MAX.
+ */
+#define SHA204_RETRY_COUNT             (1)
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_i2c.c b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_i2c.c
new file mode 100644
index 0000000000..10057ef8a6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_i2c.c
@@ -0,0 +1,300 @@
+/*
+ * \file
+ *
+ * \brief ATSHA204 file that implements the I2C layer for the device
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "conf_twim.h"
+#include "conf_atsha204.h"
+#include "twi_master.h"
+#include "sha204_physical.h"            // declarations that are common to all interface implementations
+#include "sha204_lib_return_codes.h"    // declarations of function return codes
+#include "sha204_timer.h"               // definitions for delay functions
+
+/** 
+ * \brief This enumeration lists all packet types sent to a SHA204 device.
+ *
+ * The following byte stream is sent to a SHA204 TWI device:
+ *    {I2C start} {I2C address} {word address} [{data}] {I2C stop}.
+ * Data are only sent after a word address of value #SHA204_I2C_PACKET_FUNCTION_NORMAL.
+ */
+enum i2c_word_address {
+	SHA204_I2C_PACKET_FUNCTION_RESET,  //!< Reset device.
+	SHA204_I2C_PACKET_FUNCTION_SLEEP,  //!< Put device into Sleep mode.
+	SHA204_I2C_PACKET_FUNCTION_IDLE,   //!< Put device into Idle mode.
+	SHA204_I2C_PACKET_FUNCTION_NORMAL  //!< Write / evaluate data that follow this word address byte.
+};
+
+
+//! I2C address can be changed by calling #sha204p_set_device_id.
+static uint8_t device_address = SHA204_I2C_DEFAULT_ADDRESS >> 1;
+
+
+/** \brief This function initializes peripherals (timer and communication).
+ */
+void sha204p_init(void)
+{
+	// Initialize timer.
+	sha204h_timer_init();
+
+	// Initialize interrupt vectors.
+	irq_initialize_vectors();
+
+	// Enable interrupts.
+	cpu_irq_enable();
+}
+
+
+/** 
+ * \brief This I2C function sets the I2C address.
+ *         Communication functions will use this address.
+ *
+ *  \param[in] id I2C address
+ */
+void sha204p_set_device_id(uint8_t id)
+{
+	device_address = id >> 1;
+}
+
+
+/** 
+ * \brief This I2C function generates a Wake-up pulse and delays.
+ * \return status of the operation
+ */
+uint8_t sha204p_wakeup(void)
+{
+	twi_package_t twi_package;
+	twi_options_t twi_options = {.speed = 133333};
+   
+	// Set SDA low for 60 us. Speed is therefore: f = 1 / 0.00006 / 8 = 133,333.
+	// Generating the Stop condition adds 20 us for this particular implementation / target,
+	// but a longer wake pulse is okay.
+	twi_master_disable(ATSHA204_TWI_PORT);
+	int twi_master_setup_status = twi_master_setup(ATSHA204_TWI_PORT, &twi_options);
+	if (twi_master_setup_status != STATUS_OK)
+		return SHA204_COMM_FAIL;
+
+	twi_package.chip = 0;
+	twi_package.addr_length = 0;
+	twi_package.length = 0;
+	twi_package.buffer = NULL;
+
+	// This call will return a nack error.
+	(void) twi_master_write(ATSHA204_TWI_PORT, &twi_package);
+
+	sha204h_delay_ms(SHA204_WAKEUP_DELAY);
+	
+	// Set I2C speed back to communication speed.
+	twi_master_enable(ATSHA204_TWI_PORT);
+	twi_options.speed = ATSHA204_TWI_SPEED;
+	return (uint8_t) twi_master_setup(ATSHA204_TWI_PORT, &twi_options);
+}
+
+
+/** 
+ * \brief This function sends a I2C packet enclosed by a I2C start and stop to a SHA204 device.
+ *
+ *         This function combines a I2C packet send sequence that is common to all packet types.
+ *         Only if word_address is \ref SHA204_I2C_PACKET_FUNCTION_NORMAL, count and buffer parameters are
+ *         expected to be non-zero.
+ * \param[in] word_address packet function code listed in #i2c_word_address
+ * \param[in] count number of bytes in data buffer
+ * \param[in] buffer pointer to data buffer
+ * \return status of the operation
+ */
+static uint8_t sha204p_send(uint8_t word_address, uint8_t count, uint8_t *buffer)
+{
+	twi_package_t twi_package = {
+		.chip = device_address,
+		.addr_length = 1,
+		.length = count,
+		.buffer = (void *) buffer,
+		.addr[0] = word_address
+	};
+	return (twi_master_write(ATSHA204_TWI_PORT, &twi_package) ? SHA204_COMM_FAIL : SHA204_SUCCESS);
+}
+
+
+/** 
+ * \brief This I2C function sends a command to the device.
+ * \param[in] count number of bytes to send
+ * \param[in] command pointer to command buffer
+ * \return status of the operation
+ */
+uint8_t sha204p_send_command(uint8_t count, uint8_t *command)
+{
+	return sha204p_send(SHA204_I2C_PACKET_FUNCTION_NORMAL, count, command);
+}
+
+
+/** 
+ * \brief This I2C function puts the SHA204 device into idle state.
+ * \return status of the operation
+ */
+uint8_t sha204p_idle(void)
+{
+	return sha204p_send(SHA204_I2C_PACKET_FUNCTION_IDLE, 0, NULL);
+}
+
+
+/** 
+ * \brief This I2C function puts the SHA204 device into low-power state.
+ * \return status of the operation
+ */
+uint8_t sha204p_sleep(void)
+{
+	return sha204p_send(SHA204_I2C_PACKET_FUNCTION_SLEEP, 0, NULL);
+}
+
+
+/** 
+ * \brief This I2C function resets the I/O buffer of the SHA204 device.
+ * \return status of the operation
+ */
+uint8_t sha204p_reset_io(void)
+{
+	return sha204p_send(SHA204_I2C_PACKET_FUNCTION_RESET, 0, NULL);
+}
+
+
+/** 
+ * \brief This I2C function receives a response from the SHA204 device.
+ *
+ * \param[in] size size of receive buffer
+ * \param[out] response pointer to receive buffer
+ * \return status of the operation
+ */
+uint8_t sha204p_receive_response(uint8_t size, uint8_t *response)
+{
+    // Read count.
+	twi_package_t twi_package = {
+		.chip = device_address,
+		.addr_length = 0,
+		.length = 1,
+		.buffer = (void *) response
+	};
+	status_code_t i2c_status = twi_master_read(ATSHA204_TWI_PORT, &twi_package);
+	if (i2c_status != STATUS_OK)
+	    return (i2c_status == ERR_TIMEOUT ? SHA204_TIMEOUT : SHA204_RX_NO_RESPONSE);
+
+	uint8_t count = response[SHA204_BUFFER_POS_COUNT];
+	if ((count < SHA204_RSP_SIZE_MIN) || (count > SHA204_RSP_SIZE_MAX))
+		return SHA204_INVALID_SIZE;
+	   
+	// Read packet remainder.
+    twi_package.length = (count > size) ? size : count;
+    twi_package.length--;
+    twi_package.buffer = response + 1;
+    return (twi_master_read(ATSHA204_TWI_PORT, &twi_package) ? SHA204_COMM_FAIL : SHA204_SUCCESS);
+}
+
+
+/** 
+ * \brief This I2C function resynchronizes communication.
+ *
+ * Parameters are not used for I2C.\n
+ * Re-synchronizing communication is done in a maximum of three steps
+ * listed below. This function implements the first step. Since
+ * steps 2 and 3 (sending a Wake-up token and reading the response)
+ * are the same for I2C and SWI, they are
+ * implemented in the communication layer (\ref sha204c_resync).
+ * See the excerpt from the SHA204 data sheet below.
+  <ol>
+     <li>
+       To ensure an IO channel reset, the system should send
+       the standard I2C software reset sequence, as follows:
+       <ul>
+         <li>a Start condition</li>
+         <li>nine cycles of SCL, with SDA held high</li>
+         <li>another Start condition</li>
+         <li>a Stop condition</li>
+       </ul>
+       It should then be possible to send a read sequence and
+       if synchronization has completed properly the ATSHA204 will
+       acknowledge the device address. The chip may return data or
+       may leave the bus floating (which the system will interpret
+       as a data value of 0xFF) during the data periods.\n
+       If the chip does acknowledge the device address, the system
+       should reset the internal address counter to force the
+       ATSHA204 to ignore any partial input command that may have
+       been sent. This can be accomplished by sending a write
+       sequence to word address 0x00 (Reset), followed by a
+       Stop condition.
+     </li>
+     <li>
+       If the chip does NOT respond to the device address with an ACK,
+       then it may be asleep. In this case, the system should send a
+       complete Wake token and wait t_whi after the rising edge. The
+       system may then send another read sequence and if synchronization
+       has completed the chip will acknowledge the device address.
+     </li>
+     <li>
+       If the chip still does not respond to the device address with
+       an acknowledge, then it may be busy executing a command. The
+       system should wait the longest TEXEC and then send the
+       read sequence, which will be acknowledged by the chip.
+     </li>
+  </ol>
+ * \param[in] size size of response buffer
+ * \param[out] response pointer to response buffer
+ * \return status of the operation
+ */
+uint8_t sha204p_resync(uint8_t size, uint8_t *response)
+{
+	// Generate Start, nine clocks, Stop.
+	// (Adding a Repeat Start before the Stop would additionally
+	// prevent erroneously writing a byte, but a Stop right after a
+	// Start is not "legal" for I2C and the SHA204 will not write
+	// anything without a successful CRC check.)
+	twi_package_t twi_package = {
+		.chip = (uint8_t) 0xFF,
+		.addr_length = 1,
+		.length = 0,
+		.buffer = (void *) response,
+		.addr[0] = 0
+	};
+	(void) twi_master_read(ATSHA204_TWI_PORT, &twi_package);
+
+	return sha204p_reset_io();
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_lib_return_codes.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_lib_return_codes.h
new file mode 100644
index 0000000000..aba98e6728
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_lib_return_codes.h
@@ -0,0 +1,68 @@
+/*
+ * \file
+ *
+ * \brief ATSHA204 library return codes
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SHA204_LIB_RETURN_CODES_H
+#   define SHA204_LIB_RETURN_CODES_H
+
+#include <compiler.h>               //!< compiler dependent definitions
+
+#define SHA204_SUCCESS              ((uint8_t)  0x00) //!< Function succeeded.
+#define SHA204_PARSE_ERROR          ((uint8_t)  0xD2) //!< response status byte indicates parsing error
+#define SHA204_CMD_FAIL             ((uint8_t)  0xD3) //!< response status byte indicates command execution error
+#define SHA204_STATUS_CRC           ((uint8_t)  0xD4) //!< response status byte indicates CRC error
+#define SHA204_FUNC_FAIL            ((uint8_t)  0xE0) //!< Function could not execute due to incorrect condition / state.
+#define SHA204_BAD_PARAM            ((uint8_t)  0xE2) //!< bad argument (out of range, null pointer, etc.)
+#define SHA204_INVALID_SIZE         ((uint8_t)  0xE4) //!< Count value is out of range or greater than buffer size.
+#define SHA204_BAD_CRC              ((uint8_t)  0xE5) //!< incorrect CRC received
+#define SHA204_RX_FAIL              ((uint8_t)  0xE6) //!< Timed out while waiting for response. Number of bytes received is > 0.
+#define SHA204_RX_NO_RESPONSE       ((uint8_t)  0xE7) //!< Not an error while the Command layer is polling for a command response.
+#define SHA204_RESYNC_WITH_WAKEUP   ((uint8_t)  0xE8) //!< re-synchronization succeeded, but only after generating a Wake-up
+
+#define SHA204_COMM_FAIL            ((uint8_t)  0xF0) //!< Communication with device failed. Same as in hardware dependent modules.
+#define SHA204_TIMEOUT              ((uint8_t)  0xF1) //!< Timed out while waiting for response. Number of bytes received is 0.
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_physical.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_physical.h
new file mode 100644
index 0000000000..660ffdf8ad
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_physical.h
@@ -0,0 +1,77 @@
+/*
+ * \file
+ *
+ * \brief ATSHA204 header file for the I2C layer for the device
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SHA204_PHYSICAL_H
+#   define SHA204_PHYSICAL_H
+
+#include "sha204_config.h"                           //!< configuration values
+
+#define SHA204_RSP_SIZE_MIN          ((uint8_t)  4)  //!< minimum number of bytes in response
+#define SHA204_RSP_SIZE_MAX          ((uint8_t) 35)  //!< maximum size of response packet
+
+#define SHA204_BUFFER_POS_COUNT      (0)             //!< buffer index of count byte in command or response
+#define SHA204_BUFFER_POS_DATA       (1)             //!< buffer index of data in response
+
+//! delay between Wakeup pulse and communication in ms
+#define SHA204_WAKEUP_DELAY          (3)
+/**
+ * \defgroup sha204_communication_physical_group SHA204 Service - hardware dependent communication functions
+ *
+ * @{
+ */
+void    sha204p_init(void);
+void    sha204p_set_device_id(uint8_t id);
+uint8_t sha204p_send_command(uint8_t count, uint8_t *command);
+uint8_t sha204p_receive_response(uint8_t size, uint8_t *response);
+uint8_t sha204p_wakeup(void);
+uint8_t sha204p_idle(void);
+uint8_t sha204p_sleep(void);
+uint8_t sha204p_reset_io(void);
+uint8_t sha204p_resync(uint8_t size, uint8_t *response);
+//! @}
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/common_nvm.h b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/common_nvm.h
new file mode 100644
index 0000000000..b5007a87f2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/common_nvm.h
@@ -0,0 +1,332 @@
+/**
+ * \file
+ *
+ * \brief Non volatile memories management
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef COMMON_NVM_H_INCLUDED
+#define COMMON_NVM_H_INCLUDED
+
+#include "compiler.h"
+#include "conf_board.h"
+#include "parts.h"
+#include "status_codes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
+#include "at45dbx.h"
+#endif
+
+/* ! \name Non volatile memory types */
+/* ! @{ */
+typedef enum {
+	INT_FLASH     /* !< Internal Flash */
+
+#if (XMEGA || UC3 || SAM4S)
+	, INT_USERPAGE  /* !< Userpage/User signature */
+#endif
+
+#if XMEGA
+	, INT_EEPROM    /* !< Internal EEPROM */
+#endif
+
+#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
+	, AT45DBX        /* !< External AT45DBX dataflash */
+#endif
+} mem_type_t;
+/* ! @} */
+
+#if SAM
+#       ifndef IFLASH_PAGE_SIZE
+#               define IFLASH_PAGE_SIZE IFLASH0_PAGE_SIZE
+#       endif
+
+#       ifndef IFLASH_ADDR
+#               define IFLASH_ADDR IFLASH0_ADDR
+#       endif
+#endif
+
+/**
+ * \defgroup nvm_group NVM service
+ *
+ * See \ref common_nvm_quickstart.
+ *
+ * This is the common API for non volatile memories. Additional features are
+ * available
+ * in the documentation of the specific modules.
+ *
+ */
+
+/**
+ * \brief Initialize the non volatile memory specified.
+ *
+ * \param mem Type of non volatile memory to initialize
+ */
+status_code_t nvm_init(mem_type_t mem);
+
+/**
+ * \brief Read single byte of data.
+ *
+ * \param mem Type of non volatile memory to read
+ * \param address Address to read
+ * \param data Pointer to where to store the read data
+ */
+status_code_t nvm_read_char(mem_type_t mem, uint32_t address, uint8_t *data);
+
+/**
+ * \brief Write single byte of data.
+ *
+ * \note For SAM4S internal flash, the page existed in the address must be erased first
+ *  before written, and the minimum write unit is a page,thus when writing a single
+ *  byte, a whole page that contains the data is writen.
+ *
+ * \param mem Type of non volatile memory to write
+ * \param address Address to write
+ * \param data Data to be written
+ */
+status_code_t nvm_write_char(mem_type_t mem, uint32_t address, uint8_t data);
+
+/**
+ * \brief Read \a len number of bytes from address \a address in non volatile
+ * memory \a mem and store it in the buffer \a buffer
+ *
+ * \param mem Type of non volatile memory to read
+ * \param address Address to read
+ * \param buffer Pointer to destination buffer
+ * \param len Number of bytes to read
+ */
+status_code_t nvm_read(mem_type_t mem, uint32_t address, void *buffer,
+		uint32_t len);
+
+/**
+ * \brief Write \a len number of bytes at address \a address in non volatile
+ * memory \a mem from the buffer \a buffer
+ *
+ * \note For SAM4S internal flash, the page existed in the address must be erased
+ *  first before written.
+ *
+ * \param mem Type of non volatile memory to write
+ * \param address Address to write
+ * \param buffer Pointer to source buffer
+ * \param len Number of bytes to write
+ */
+status_code_t nvm_write(mem_type_t mem, uint32_t address, void *buffer,
+		uint32_t len);
+
+/**
+ * \brief Erase a page in the non volatile memory.
+ *
+ * The function is only available for internal flash and/or userpage signature.
+ *
+ * \note For SAM4S internal flash erase, the minimum erase unit is 8 pages.
+ *
+ * \param mem Type of non volatile memory to erase
+ * \param page_number Page number to erase
+ */
+status_code_t nvm_page_erase(mem_type_t mem, uint32_t page_number);
+
+/**
+ * \brief Get the size of whole non volatile memory specified.
+ *
+ * \param mem Type of non volatile memory
+ * \param size Pointer to where to store the size
+ */
+status_code_t nvm_get_size(mem_type_t mem, uint32_t *size);
+
+/**
+ * \brief Get the size of a page in the non volatile memory specified.
+ *
+ * \param mem Type of non volatile memory
+ * \param size Pointer to where to store the size
+ */
+status_code_t nvm_get_page_size(mem_type_t mem, uint32_t *size);
+
+/**
+ * \brief Get the page number from the byte address \a address.
+ *
+ * \param mem Type of non volatile memory
+ * \param address Byte address of the non volatile memory
+ * \param num Pointer to where to store the page number
+ */
+status_code_t nvm_get_pagenumber(mem_type_t mem, uint32_t address,
+		uint32_t *num);
+
+/**
+ * \brief Enable security bit which blocks external read and write access
+ * to the device.
+ *
+ */
+status_code_t nvm_set_security_bit(void);
+
+/**
+ * \page common_nvm_quickstart Quick Start quide for common NVM driver
+ *
+ * This is the quick start quide for the \ref nvm_group "Common NVM driver",
+ * with step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section nvm_basic_use_case Basic use case
+ * In this basic use case, NVM driver is configured for Internal Flash
+ *
+ * \section nvm_basic_use_case_setup Setup steps
+ *
+ * \subsection nvm_basic_use_case_setup_code Example code
+ * Add to you application C-file:
+ * \code
+	if(nvm_init(INT_FLASH) == STATUS_OK)
+	  do_something();
+\endcode
+ *
+ * \subsection nvm_basic_use_case_setup_flow Workflow
+ * -# Ensure that board_init() has configured selected I/Os for TWI function
+ * when using external AT45DBX dataflash
+ * -# Ensure that \ref conf_nvm.h is present for the driver.
+ *   - \note This file is only for the driver and should not be included by the
+ * user.
+ * -# Call nvm_init \code nvm_init(INT_FLASH); \endcode
+ * and optionally check its return code
+ *
+ * \section nvm_basic_use_case_usage Usage steps
+ * \subsection nvm_basic_use_case_usage_code_writing Example code: Writing to
+ * non volatile memory
+ * Use in the application C-file:
+ * \code
+	   uint8_t buffer[] = {0xAA, 0xBB, 0xCC, 0xDD, 0xEE};
+
+	   if(nvm_write(INT_FLASH, test_address, (void *)buffer, sizeof(buffer)) ==
+	 STATUS_OK)
+	     do_something();
+\endcode
+ *
+ * \subsection nvm_basic_use_case_usage_flow Workflow
+ * -# Prepare the data you want to send to the non volatile memory
+ *   \code uint8_t buffer[] = {0xAA, 0xBB, 0xCC, 0xDD, 0xEE}; \endcode
+ * -# Call nvm_write \code nvm_write(INT_FLASH, test_address, (void *)buffer,
+	 sizeof(buffer)) \endcode
+ * and optionally check its return value for STATUS_OK.
+ *
+ * \subsection nvm_basic_use_case_usage_code_reading Example code: Reading from
+ * non volatile memory
+ * Use in application C-file:
+ * \code
+	   uint8_t data_read[8];
+
+	   if(nvm_read(INT_FLASH, test_address, (void *)data_read, sizeof(data_read))
+	 == STATUS_OK) {
+	     //Check read content
+	     if(data_read[0] == 0xAA)
+	       do_something();
+	   }
+\endcode
+ *
+ * \subsection nvm_basic_use_case_usage_flow Workflow
+ * -# Prepare a data buffer that will read data from non volatile memory
+ *   \code uint8_t data_read[8]; \endcode
+ * -# Call nvm_read \code nvm_read(INT_FLASH, test_address, (void *)data_read,
+	 sizeof(data_read)); \endcode
+ * and optionally check its return value for STATUS_OK.
+ * The data read from the non volatile memory are in data_read.
+ *
+ * \subsection nvm_basic_use_case_usage_code_erasing Example code: Erasing a
+ * page of non volatile memory
+ * Use in the application C-file:
+ * \code
+	if(nvm_page_erase(INT_FLASH, test_page) == STATUS_OK)
+	  do_something();
+\endcode
+ *
+ * \subsection nvm_basic_use_case_usage_flow Workflow
+ * -# Call nvm_page_erase \code nvm_page_erase(INT_FLASH, test_page) \endcode
+ * and optionally check its return value for STATUS_OK.
+ *
+ * \subsection nvm_basic_use_case_usage_code_config Example code: Reading
+ *configuration of non volatile memory
+ * Use in application C-file:
+ * \code
+	   uint8_t mem_size, page_size, page_num;
+
+	   nvm_get_size(INT_FLASH, &mem_size);
+	   nvm_get_page_size(INT_FLASH, &page_size);
+	   nvm_get_pagenumber(INT_FLASH, test_address, &page_num);
+\endcode
+ *
+ * \subsection nvm_basic_use_case_usage_flow Workflow
+ * -# Prepare a buffer to store configuration of non volatile memory
+ *   \code uint8_t mem_size, page_size, page_num; \endcode
+ * -# Call nvm_get_size \code nvm_get_size(INT_FLASH, &mem_size); \endcode
+ * and optionally check its return value for STATUS_OK.
+ * The memory size of the non volatile memory is in mem_size.
+ * -# Call nvm_get_page_size \code nvm_get_page_size(INT_FLASH, &page_size);
+\endcode
+ * and optionally check its return value for STATUS_OK.
+ * The page size of the non volatile memory is in page_size.
+ * -# Call nvm_get_pagenumber \code nvm_get_page_number(INT_FLASH, test_address,
+	 &page_num); \endcode
+ * and optionally check its return value for STATUS_OK.
+ * The page number of given address in the non volatile memory is in page_num.
+ *
+ * \subsection nvm_basic_use_case_usage_code_locking Example code: Enabling
+ * security bit
+ * Use in the application C-file:
+ * \code
+	if(nvm_set_security_bit() == STATUS_OK)
+	  do_something();
+\endcode
+ *
+ * \subsection nvm_basic_use_case_usage_flow Workflow
+ * -# Call nvm_set_security_bit \code nvm_set_security_bit() \endcode
+ * and optionally check its return value for STATUS_OK.
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* COMMON_NVM_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/module_config/conf_nvm.h b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/module_config/conf_nvm.h
new file mode 100644
index 0000000000..14947660c5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/module_config/conf_nvm.h
@@ -0,0 +1,50 @@
+/**
+ * \file
+ *
+ * \brief Non volatile memories management for SAM devices
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_NVM_H_INCLUDED
+#define CONF_NVM_H_INCLUDED
+
+#endif /* CONF_NVM_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/sam_nvm.c b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/sam_nvm.c
new file mode 100644
index 0000000000..cf23c7fee7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/sam_nvm.c
@@ -0,0 +1,394 @@
+/**
+ * \file
+ *
+ * \brief Non volatile memories management for SAM devices
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "common_nvm.h"
+#include "conf_board.h"
+#include "flash_efc.h"
+#include "string.h"
+
+status_code_t nvm_init(mem_type_t mem)
+{
+	switch (mem) {
+	case INT_FLASH:
+#if SAM4S
+	case INT_USERPAGE:
+#endif
+		break;
+
+#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
+	case AT45DBX:
+		/* Initialize dataflash */
+		at45dbx_init();
+		/* Perform memory check */
+		if (!at45dbx_mem_check()) {
+			return ERR_NO_MEMORY;
+		}
+		break;
+#endif
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_read_char(mem_type_t mem, uint32_t address, uint8_t *data)
+{
+	switch (mem) {
+	case INT_FLASH:
+		*data = *((uint8_t *)(address));
+		break;
+
+#if SAM4S
+	case INT_USERPAGE:
+	{
+		/*! This function creates a buffer of IFLASH_PAGE_SIZE to
+		 * read the data from starting of user signature */
+		uint32_t buffer[IFLASH_PAGE_SIZE];
+		uint32_t offset = address - IFLASH_ADDR;
+		if (offset < 0) {
+			return ERR_INVALID_ARG;
+		}
+
+		flash_read_user_signature(buffer, offset);
+		*data = buffer[offset];
+		break;
+	}
+#endif
+
+#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
+	case AT45DBX:
+		if (!at45dbx_read_byte_open(address)) {
+			return ERR_BAD_ADDRESS;
+		}
+
+		*data = at45dbx_read_byte();
+		at45dbx_read_close();
+		break;
+#endif
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_write_char(mem_type_t mem, uint32_t address, uint8_t data)
+{
+	switch (mem) {
+	case INT_FLASH:
+#if SAM4S
+
+		if (flash_write(address, (const void *)&data, 1,
+				false)) {
+			return ERR_INVALID_ARG;
+		}
+
+#else
+		if (flash_write(address, (const void *)&data, 1, true)) {
+			return ERR_INVALID_ARG;
+		}
+
+#endif
+		break;
+
+#if SAM4S
+	case INT_USERPAGE:
+		if (flash_write_user_signature((const void *)&data,	1)) {
+			return ERR_INVALID_ARG;
+		}
+		break;
+#endif
+
+#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
+	case AT45DBX:
+		if (!at45dbx_write_byte_open(address)) {
+			return ERR_BAD_ADDRESS;
+		}
+
+		at45dbx_write_byte(data);
+		at45dbx_write_close();
+		break;
+#endif
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_read(mem_type_t mem, uint32_t address, void *buffer,
+		uint32_t len)
+{
+	switch (mem) {
+	case INT_FLASH:
+		memcpy(buffer, (const void *)address, len);
+		break;
+
+#if SAM4S
+	case INT_USERPAGE:
+	{
+		/*! This function creates a buffer of IFLASH_PAGE_SIZE to
+		 * read the data from starting of user signature */
+		uint32_t temp_buff[IFLASH_PAGE_SIZE], *buff = buffer;
+
+		/* Read from the starting of user signature */
+		if (flash_read_user_signature(temp_buff, len)) {
+			return ERR_INVALID_ARG;
+		}
+
+		/* Calculate offset and copy required number of bytes */
+		for (uint16_t i = 0; i < len; i++) {
+			*buff = temp_buff[address - IFLASH_ADDR + i];
+			buff++;
+		}
+		break;
+	}
+#endif
+
+#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
+	case AT45DBX:
+	{
+		if (len == AT45DBX_SECTOR_SIZE) {
+			uint32_t sector = address / AT45DBX_SECTOR_SIZE;
+			if (!at45dbx_read_sector_open(sector)) {
+				return ERR_BAD_ADDRESS;
+			}
+
+			at45dbx_read_sector_to_ram(buffer);
+			at45dbx_read_close();
+		} else {
+			if (!at45dbx_read_byte_open(address)) {
+				return ERR_BAD_ADDRESS;
+			}
+			uint8_t *buf = (uint8_t *)buffer;
+			while (len--) {
+				*buf++ = at45dbx_read_byte();
+			}
+			at45dbx_read_close();
+		}
+		
+	}
+	break;
+#endif
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_write(mem_type_t mem, uint32_t address, void *buffer,
+		uint32_t len)
+{
+	switch (mem) {
+	case INT_FLASH:
+#if SAM4S
+
+		if (flash_write(address, (const void *)buffer, len, false)) {
+			return ERR_INVALID_ARG;
+		}
+
+#else
+		if (flash_write(address, (const void *)buffer, len, true)) {
+			return ERR_INVALID_ARG;
+		}
+
+#endif
+		break;
+
+#if SAM4S
+	case INT_USERPAGE:
+		if (flash_write_user_signature((const void *)buffer, len)) {
+			return ERR_INVALID_ARG;
+		}
+		break;
+#endif
+
+#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
+	case AT45DBX:
+	{
+		if (len == AT45DBX_SECTOR_SIZE) {
+			uint32_t sector = address / AT45DBX_SECTOR_SIZE;
+			if (!at45dbx_write_sector_open(sector)) {
+				return ERR_BAD_ADDRESS;
+			}
+
+			at45dbx_write_sector_from_ram((const void *)buffer);
+			at45dbx_write_close();
+		} else {
+			if (!at45dbx_write_byte_open(address)) {
+				return ERR_BAD_ADDRESS;
+			}
+			uint8_t *buf = (uint8_t *)buffer;
+			while (len--) {
+				at45dbx_write_byte(*buf++);
+			}
+			at45dbx_write_close();
+		}	
+	}
+	break;
+#endif
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_page_erase(mem_type_t mem, uint32_t page_number)
+{
+	switch (mem) {
+	case INT_FLASH:
+	{
+#if SAM4S
+		/*! Page erase function erases minimum 8 pages in Flash */
+		if (flash_erase_page((uint32_t)(page_number * IFLASH_PAGE_SIZE),
+				IFLASH_ERASE_PAGES_8)) {
+			return ERR_INVALID_ARG;
+		}
+
+#else
+		uint32_t buffer[IFLASH_PAGE_SIZE], byte_address;
+		for (uint16_t i = 0; i < IFLASH_PAGE_SIZE; i++) {
+			buffer[i] = 0xFFFFFFFF;
+		}
+		byte_address = page_number * IFLASH_PAGE_SIZE;
+
+		/* Erase and write FFs to a page as there is no function for
+		 * erase */
+		if (!flash_write(byte_address, (const void *)buffer,
+				IFLASH_PAGE_SIZE, true)) {
+			return ERR_INVALID_ARG;
+		}
+
+#endif
+		break;
+	}
+
+#if SAM4S
+	case INT_USERPAGE:
+		flash_erase_user_signature();
+		break;
+#endif
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_get_size(mem_type_t mem, uint32_t *size)
+{
+	switch (mem) {
+	case INT_FLASH:
+		*size = (uint32_t)IFLASH_SIZE;
+		break;
+
+#if SAM4S
+	case INT_USERPAGE:
+		*size = (uint32_t)IFLASH_PAGE_SIZE;
+		break;
+#endif
+
+#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
+	case AT45DBX:
+		*size = (uint32_t)AT45DBX_MEM_SIZE;
+		break;
+#endif
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_get_page_size(mem_type_t mem, uint32_t *size)
+{
+	switch (mem) {
+	case INT_FLASH:
+#if SAM4S
+	case INT_USERPAGE:
+#endif
+		*size = (uint32_t)IFLASH_PAGE_SIZE;
+		break;
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_get_pagenumber(mem_type_t mem, uint32_t address,
+		uint32_t *num)
+{
+	switch (mem) {
+	case INT_FLASH:
+		*num = (uint32_t)(address / IFLASH_PAGE_SIZE);
+		break;
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+status_code_t nvm_set_security_bit(void)
+{
+	if (!flash_enable_security_bit()) {
+		return ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.c
new file mode 100644
index 0000000000..5b41fc76ed
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.c
@@ -0,0 +1,1353 @@
+/**
+ * \file
+ *
+ * \brief ADP service implementation
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+
+#include "adp.h"
+#include "adp_interface.h"
+#include "status_codes.h"
+#include <string.h>
+
+/** ID of last received message */
+static uint8_t last_received_message_id = 0xff;
+/** true if valid message has been received */
+static bool packet_received = false;
+/** Number of bytes received */
+static uint16_t bytes_received;
+/** Judge previous received data */
+static uint8_t prev_data = 0;
+/** The length of received data */
+static uint16_t length_received;
+/** Current state */
+static enum rx_state_e rx_state;
+
+uint16_t adp_add_send_byte(uint8_t* buffer, uint8_t index, uint8_t* data, uint16_t length)
+{
+	for(uint16_t i = 0; i < length; i++) {
+		if (*(data + i) == ADP_TOKEN){
+			*(buffer + index) = ADP_TOKEN;
+			index++;
+		}
+		*(buffer + index) = *(data + i);
+		index++;
+	}
+
+	return index;
+}
+
+/**
+* \internal Handle incoming data byte
+*
+* \param[in] data New data byte to handle
+*
+* \return
+* \retval true Given data byte is part of message data
+* \retval false Given data byte is not part of message data
+*/
+static bool adp_add_receive_byte(uint8_t data)
+{
+	static uint8_t message_id;
+
+	if ((rx_state == RX_STATE_GOT_SYMBOL) && (data != ADP_TOKEN)) {
+		/* Abort packet reception, new packet incoming */
+		rx_state = RX_STATE_WAIT_LENGTH_LSB;
+	}
+
+	switch (rx_state) {
+		case RX_STATE_IDLE:
+			packet_received = false;
+			last_received_message_id = 0xFF;
+			/* We are waiting for a new packet. */
+			if (data != ADP_TOKEN) {
+				return false;
+			}
+			/* Got start symbol, wait for message ID */
+			rx_state = RX_STATE_WAIT_MSG_ID;
+			return false;
+
+		case RX_STATE_WAIT_MSG_ID:
+			if (data == ADP_TOKEN) {
+				/* Restart. Don't change state. Wait for new message ID */
+				return false;
+			}
+			message_id = data;
+			rx_state = RX_STATE_WAIT_LENGTH_LSB;
+			return false;
+
+		case RX_STATE_WAIT_LENGTH_LSB:
+			if (data == ADP_TOKEN) {
+				if (prev_data != ADP_TOKEN) {
+					prev_data = ADP_TOKEN;
+					return false;
+				}
+			}
+			length_received = data;
+			rx_state = RX_STATE_WAIT_LENGTH_MSB;
+			prev_data = 0;
+			return false;
+
+		case RX_STATE_WAIT_LENGTH_MSB:
+			if (data == ADP_TOKEN) {
+				if (prev_data != ADP_TOKEN) {
+					prev_data = ADP_TOKEN;
+					return false;
+				}
+			}
+			length_received += (uint16_t)data << 8;
+			prev_data = 0;
+			/* Got valid length, do we expect data? */
+			if (length_received == 0) {
+				/* No data here, wait for next packet */
+				rx_state = RX_STATE_IDLE;
+				packet_received = true;
+				last_received_message_id = message_id;
+				return false;
+			}
+
+			/* Wait for packet data */
+			bytes_received = 0;
+			rx_state = RX_STATE_GET_DATA;
+			return false;
+
+		case RX_STATE_GET_DATA:
+		case RX_STATE_GOT_SYMBOL:
+			if ((data == ADP_TOKEN) && (rx_state == RX_STATE_GET_DATA)) {
+				rx_state = RX_STATE_GOT_SYMBOL;
+				return false;
+			}
+			/* Add new data to rx buffer */
+			bytes_received++;
+			/* Are we done yet? */
+			if (length_received == bytes_received) {
+				/* Yes we are! */
+				packet_received = true;
+				rx_state = RX_STATE_IDLE;
+				last_received_message_id = message_id;
+				return true;
+			}
+			/* Not done yet.. keep on receiving */
+			rx_state = RX_STATE_GET_DATA;
+			return true;
+	}
+	return false;
+}
+
+static bool adp_is_received(void)
+{
+	if (bytes_received == 0) {
+		return false;
+	}
+	return packet_received;
+}
+
+static uint8_t adp_packet_received_get_id(void)
+{
+	return last_received_message_id;
+}
+
+static bool adp_protocol_add_byte(uint8_t rx_id, uint8_t* rx_buf, uint8_t length, uint8_t* protocol_buf)
+{
+	uint8_t i;
+
+	for (i = 0; i < length; i++)
+	{
+		if (adp_add_receive_byte(*(rx_buf + i)) == true) {
+			/* This is a data byte */
+			protocol_buf[bytes_received - 1] = *(rx_buf + i);
+		}
+		if (adp_is_received() & (adp_packet_received_get_id() == rx_id)) {
+			return true;
+		}
+	}
+	return false;
+}
+
+static bool adp_check_for_response(uint8_t rx_id, uint8_t* protocol_buf, uint8_t length)
+{
+	uint8_t retry;
+	bool status = false;
+	uint8_t rx_buf[ADP_MAX_PACKET_DATA_SIZE] = {0,};
+
+	retry = 50;
+	length = length + ADP_LENGTH_PACKET_HEADER;
+	packet_received = false;
+	while((adp_is_received() == false) & (retry-- > 0)) {	
+		if(adp_interface_read_response(rx_buf, length) == STATUS_OK) {
+			status = adp_protocol_add_byte(rx_id, rx_buf, length, protocol_buf);
+			if(status == true) {
+				break;
+			}
+		}
+	}
+	
+	return status;
+}
+
+static void adp_wait_for_response(uint8_t rx_id, uint8_t* protocol_buf, uint8_t length)
+{
+	uint8_t rx_buf[ADP_MAX_PACKET_DATA_SIZE] = {0,};
+
+	packet_received = false;
+	length = length + ADP_LENGTH_PACKET_HEADER;
+	while((adp_is_received() == false)) {
+		if(adp_interface_read_response(rx_buf, length) == STATUS_OK) {
+			adp_protocol_add_byte(rx_id, rx_buf, length, protocol_buf);
+		}
+	}
+}
+
+/**
+* \brief Initialization of the ADP service
+*
+* \return None
+*/
+void adp_init(void)
+{
+	adp_interface_init();
+}
+
+/**
+* \brief Send handshake to PC and check for response
+*
+* \param[in]  protocol_version  ADP version used in this implementation
+* \param[out] status            Status returned by PC
+*
+* \return PC returned valid response to out handshake
+* \retval true  If we got valid response
+* \retval false If we didn't receive a valid handshake response
+*/
+static bool adp_request_handshake(uint8_t protocol_version, uint8_t options, uint8_t* protocol_buf)
+{
+	uint16_t data_length = MSQ_REQ_HANDSHAKE_LEN + ADP_LENGTH_PACKET_HEADER;
+	uint8_t key[8] = ADP_HANDSHAKE_KEY;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	struct adp_msg_request_handshake msg_request_handshake;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_REQ_HANDSHAKE;
+	msg_format.data_length = MSQ_REQ_HANDSHAKE_LEN;
+	
+	msg_request_handshake.protocol_version = protocol_version;
+	msg_request_handshake.options = options;
+	memcpy(&msg_request_handshake.key, key, 8);
+	memcpy((uint8_t*)&msg_format.data, &msg_request_handshake, sizeof(msg_request_handshake));
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	return adp_check_for_response(MSG_RES_HANDSHAKE, protocol_buf, 1);
+}
+
+
+/**
+* \brief Send handshake to PC until we get a valid response
+*
+* \warning Blocking function
+*
+* \return Handshake status. See /ref something
+*/
+enum adp_handshake_status adp_wait_for_handshake(void)
+{
+	uint8_t handshake_status;
+
+	/* Keep sending handshake until we get something back */
+	while (adp_request_handshake(ADP_VERSION, ADP_HANDSHAKE_OPTIONS_GPIO, &handshake_status) == false) {
+	}
+
+	/* Return status */
+	return ((enum adp_handshake_status)handshake_status);
+}
+
+
+/**
+* \brief Request status from PC
+*
+* Sends a MSG_REQ_STATUS and waits for response
+*
+* \return PC Status. See /ref something
+*/
+enum adp_status_code adp_request_status(void)
+{
+	uint16_t data_length = MSG_REQ_STATUS_LEN + ADP_LENGTH_PACKET_HEADER;
+	uint16_t status;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_REQ_STATUS;
+	msg_format.data_length = MSG_REQ_STATUS_LEN;
+
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	/* Wait for response from PC */
+	adp_wait_for_response(MSG_RES_STATUS, (uint8_t*)&status, 2);
+	return ((enum adp_status_code)status);
+}
+
+
+/**
+* \brief Send MSG_CONF_INFO message and wait for response
+*
+* \param[in] title       Application title
+* \param[in] description Application description
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_configure_info(const char* title, const char* description)
+{
+	uint16_t title_len;
+	uint16_t description_len;
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	
+	struct adp_msg_format msg_format;
+
+	/* Add null-termination to length */
+	title_len = strlen(title) + 1;
+	description_len = strlen(description) + 1;
+	/* Make sure the strings are not too long */
+	Assert(title_len + description_len <= ADP_MAX_PACKET_DATA_SIZE);	
+	
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_INFO;
+	msg_format.data_length = title_len + description_len;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)description, description_len);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Send MSG_CONF_STREAM and wait for response
+*
+* \param[in] config Configuration struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_configure_stream(struct adp_msg_configure_stream *const config, const char* label)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t label_len;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+	/* Add null-termination to length */
+	label_len = strlen(label) + 1;
+	/* Make sure the strings are not too long */
+	Assert(label_len <= ADP_MAX_PACKET_DATA_SIZE);
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_STREAM;
+	msg_format.data_length = MSG_CONF_STREAM_LEN + label_len;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->type, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->state, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+
+/**
+* \brief Send MSG_CONF_TOGGLE_STREAM and wait for response
+*
+* \param[in] stream_id ID of stream to toggle
+* \param[in] state     New state for given stream
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_toggle_stream(struct adp_msg_toggle_stream *const config)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_TOGGLE_STREAM;
+	msg_format.data_length = MSG_CONF_TOGGLE_STREAM_LEN;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->state, 1);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+
+/**
+* \brief Send MSG_CONF_GRAPH and wait for response
+*
+* \param[in] config Graph configuration struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_configure_graph(struct adp_msg_configure_graph *const config, \
+						const char* graph_label, const char* x_label)
+{
+	uint8_t ack;
+	uint16_t graph_label_len, x_label_len;
+
+	/* Add 0-termination to label string length */
+	graph_label_len = strlen(graph_label) + 1;
+	x_label_len = strlen(x_label) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(MSG_CONF_GRAPH_LEN + graph_label_len + x_label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_GRAPH;
+	msg_format.data_length = MSG_CONF_GRAPH_LEN + graph_label_len + x_label_len;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)graph_label, graph_label_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_min, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_max, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)x_label, x_label_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_numerator, MSG_CONF_GRAPH_LEN - 10);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+
+/**
+* \brief Send MSG_CONF_TERMINAL and wait for response
+*
+* \param[in] config Terminal configuration struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_configure_terminal(struct adp_msg_conf_terminal *const config, const char* label)
+{
+	uint8_t ack;
+	uint16_t label_len;
+
+	/* Add 0-termination to label string length */
+	label_len = strlen(label) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(MSG_CONF_TERMINAL_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_TERMINAL;
+	msg_format.data_length = MSG_CONF_TERMINAL_LEN + label_len;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->terminal_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->width, MSG_CONF_TERMINAL_LEN - 1);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Send MSG_CONF_ADD_TO_TERMINAL and wait for response
+*
+* \param[in] config Stream-to-terminal configuration struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_stream_to_terminal(struct adp_msg_add_stream_to_terminal *const config, const char* tag_text)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t tag_text_len;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	/* Add 0-termination to label string length */
+	tag_text_len = strlen(tag_text) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(MSG_CONF_ADD_TO_TERMINAL_LEN + tag_text_len <= ADP_MAX_PACKET_DATA_SIZE);
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_ADD_TO_TERMINAL;
+	msg_format.data_length = MSG_CONF_ADD_TO_TERMINAL_LEN + tag_text_len;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->terminal_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->text_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_text, tag_text_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->tag_text_color, 3);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+
+/**
+* \brief Send MSG_CONF_AXIS and wait for response
+*
+* \param[in] config Axis configuration struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_axis_to_graph(struct adp_msg_conf_axis *const config, const char* label)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint16_t label_len;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	/* Add 0-termination to label string length */
+	label_len = strlen(label) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(MSG_CONF_AXIS_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_AXIS;
+	msg_format.data_length = MSG_CONF_AXIS_LEN + label_len;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_min, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_max, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_numerator, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_denominator, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+
+/**
+* \brief Send MSG_CONF_ADD_STREAM_TO_AXIS and wait for response
+*
+* \param[in] config Axis configuration struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_stream_to_axis(struct adp_msg_add_stream_to_axis *const config)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_ADD_STREAM_TO_AXIS;
+	msg_format.data_length = MSG_CONF_ADD_STREAM_TO_AXIS_LEN;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->sample_rate_numerator, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->sample_rate_denominator, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_scale_numerator, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_scale_denominator, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_offset, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_thickness, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color, 3);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+
+/**
+* \brief Send MSG_CONF_CURSOR_TO_GRAPH and wait for response
+*
+* \param[in] config Cursor configuration struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_cursor_to_graph(struct adp_msg_add_cursor_to_graph *const config, const char* label)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint16_t label_len;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	/* Add 0-termination to label string length */
+	label_len = strlen(label) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(MSG_CONF_CURSOR_TO_GRAPH_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_CURSOR_TO_GRAPH;
+	msg_format.data_length = MSG_CONF_CURSOR_TO_GRAPH_LEN;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->thickness, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_numerator, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_denominator, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_offset, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_style, 1);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Send MSG_CONF_CURSOR_TO_GRAPH and wait for response
+*
+* \param[in] config         Cursor configuration struct
+* \param[in] tag_high_state Tag text to display when GPIO pin is high.
+* \param[in] tag_low_state  Tag text to display when GPIO pin is low.
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_gpio_to_graph(struct adp_msg_conf_gpio_to_graph *const config, \
+					const char* tag_high_state, const char* tag_low_state)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint16_t label_len, tag_high_state_len, tag_low_state_len;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	/* Add 0-termination to label string length */
+	tag_high_state_len = strlen(tag_high_state) + 1;
+	tag_low_state_len = strlen(tag_low_state) + 1;
+	label_len = tag_high_state_len + tag_low_state_len;
+
+	/* Make sure label isn't too big */
+	Assert(MSG_CONF_GPIO_TO_GRAPH_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_GPIO_TO_GRAPH;
+	msg_format.data_length = MSG_CONF_GPIO_TO_GRAPH_LEN + label_len;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->gpio_number, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_high_state, tag_high_state_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_low_state, tag_low_state_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_thickness, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color_high_state, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color_low_state, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_style, 1);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a dashboard
+*
+* \param[in] config    Pointer to dashboard configuration data struct
+* \param[in] label     Dashboard label (0-terminated string)
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_dashboard(struct adp_msg_conf_dashboard *const config, const char* label)
+{
+	uint8_t ack;
+	uint16_t label_len;
+
+	/* Add 0-termination to label string length */
+	label_len = strlen(label) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(MSG_CONF_DASHBOARD_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD;
+	msg_format.data_length = MSG_CONF_DASHBOARD_LEN + label_len;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index,(uint8_t*)&config->dashboard_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->height, 2);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+static uint16_t adp_add_dashboard_element_common_send_byte(uint8_t* add_buf, uint16_t index, \
+									struct adp_msg_conf_dashboard_element_common *const config)
+{
+	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->dashboard_id, 2);
+	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->element_id, 2);
+	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->z_index, 1);
+	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->x, 2);
+	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->y, 2);
+	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->width, 2);
+	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->height, 2);
+	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->element_type, 1);
+	
+	return index;
+}
+
+/**
+* \brief Add a label to dashboard
+*
+* \param[in] config    Pointer to dashboard label struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_label_to_dashboard(struct adp_msg_conf_dashboard_element_label *const config, const char* label)
+{
+	uint8_t ack;
+	uint16_t label_len;
+
+	/* Add 0-termination to label string length */
+	label_len = strlen(label) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(ADP_ELEMENT_TYPE_LABEL_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_LABEL_LEN + label_len;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+											(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->attribute, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->horisontal_alignment, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->vertical_alignment, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_transparency, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->foreground_transparency, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->foreground_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a button to dashboard
+*
+* \param[in] config    Pointer to dashboard button struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_button_to_dashboard(struct adp_msg_conf_dashboard_element_button *const config, const char* label)
+{
+	uint8_t ack;
+	uint16_t label_len;
+
+	/* Add 0-termination to label string length */
+	label_len = strlen(label) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(ADP_ELEMENT_TYPE_BUTTON_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_BUTTON_LEN + label_len;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+										(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a slider to dashboard
+*
+* \param[in] config    Pointer to dashboard slider struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_slider_to_dashboard(struct adp_msg_conf_dashboard_element_slider *const config)
+{	
+		uint8_t ack;
+		uint16_t data_length;
+		uint16_t index = 0;
+		uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+		
+		struct adp_msg_format msg_format;
+		
+		msg_format.protocol_token = ADP_TOKEN;
+		msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+		msg_format.data_length = ADP_ELEMENT_TYPE_SLIDER_LEN;
+		index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+												(struct adp_msg_conf_dashboard_element_common *)config);
+		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
+		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
+		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
+		data_length = ADP_LENGTH_PACKET_HEADER + index;
+		
+		/* Send the protocol packet data */
+		adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+		
+		/* Wait for response and return status */
+		adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+		return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a progress bar to dashboard
+*
+* \param[in] config    Pointer to dashboard progress bar struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_progress_to_dashboard(struct adp_msg_conf_dashboard_element_progress *const config)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_PROGRESS_LEN;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+											(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a signal to dashboard
+*
+* \param[in] config    Pointer to dashboard signal struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_signal_to_dashboard(struct adp_msg_conf_dashboard_element_signal *const config)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_SIGNAL_LEN;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+											(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->on_transparency, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->on_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->off_transparency, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->off_color, 3);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a segment display to dashboard
+*
+* \param[in] config    Pointer to dashboard segment struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_segment_to_dashboard(struct adp_msg_conf_dashboard_element_segment *const config)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_SEGMENT_LEN;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+											(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->segment_count, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->base, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a graph to dashboard
+*
+* \param[in] config    Pointer to dashboard graph struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_graph_to_dashboard(struct adp_msg_conf_dashboard_element_graph *const config, const char* title)
+{
+	uint8_t ack;
+	uint16_t title_len;
+
+	/* Add 0-termination to label string length */
+	title_len = strlen(title) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(ADP_ELEMENT_TYPE_GRAPH_LEN + title_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_GRAPH_LEN + title_len;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+										(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->title_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_background_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->plot_count, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_min, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_max, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_min, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_max, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+	
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add data fields to dashboard
+*
+* \param[in] config    Pointer to dashboard text struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_text_to_dashboard(struct adp_msg_conf_dashboard_element_text *const config)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_TEXT_LEN;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+											(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum, 4);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->value, 4);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a radio to dashboard
+*
+* \param[in] config    Pointer to dashboard radio struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_radio_to_dashboard(struct adp_msg_conf_dashboard_element_radio *const config, const char* text)
+{
+	uint8_t ack;
+	uint16_t text_len;
+
+	/* Add 0-termination to label string length */
+	text_len = strlen(text) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(ADP_ELEMENT_TYPE_RADIO_LEN + text_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_RADIO_LEN + text_len;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+											(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->number_items, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->orientation, 1);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)text, text_len);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Add a pie to dashboard
+*
+* \param[in] config    Pointer to dashboard pie struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_pie_to_dashboard(struct adp_msg_conf_dashboard_element_pie *const config, const char* title)
+{
+	uint8_t ack;
+	uint16_t title_len;
+
+	/* Add 0-termination to label string length */
+	title_len = strlen(title) + 1;
+
+	/* Make sure label isn't too big */
+	Assert(ADP_ELEMENT_TYPE_PIE_LEN + title_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+	msg_format.data_length = ADP_ELEMENT_TYPE_PIE_LEN + title_len;
+	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+											(struct adp_msg_conf_dashboard_element_common *)config);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->title_color, 3);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->number_slices, 1);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+/**
+* \brief Connect a stream to dashboard element
+*
+* \param[in] config    Pointer to stream element configuration struct
+*
+* \return Status from PC
+* \retval true   Message received and accepted
+* \retval false  Message received but not accepted
+*/
+bool adp_add_stream_to_element(struct adp_conf_add_stream_to_element *const config)
+{
+	uint8_t ack;
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_CONF_ADD_STREAM_TO_ELEMENT;
+	msg_format.data_length = MSG_CONF_ADD_STREAM_TO_ELEMENT_LEN;
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->dashboard_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->element_id, 2);
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+	/* Wait for response and return status */
+	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+	return (ack == ADP_ACK_OK);
+}
+
+bool adp_transceive_stream(struct adp_msg_data_stream *const stream_data, uint8_t *protocol_buf)
+{
+	uint8_t stream_num;	
+	uint16_t data_length;
+	uint16_t index = 0;
+	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+	
+	struct adp_msg_format msg_format;
+	
+	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&stream_data->number_of_streams, 1);
+	/* find packet size */
+	for (stream_num = 0; stream_num < stream_data->number_of_streams; stream_num++) {
+		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
+						(uint8_t*)&stream_data->stream[stream_num].stream_id, 2);
+		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
+						(uint8_t*)&stream_data->stream[stream_num].data_size, 1);
+		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
+						stream_data->stream[stream_num].data, \
+						stream_data->stream[stream_num].data_size);
+	}
+	
+	msg_format.protocol_token = ADP_TOKEN;
+	msg_format.protocol_msg_id = MSG_DATA_STREAM;
+	msg_format.data_length = index;
+	data_length = ADP_LENGTH_PACKET_HEADER + index;
+	
+	/* Send the protocol packet data */
+	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+	
+	return adp_protocol_add_byte(MSG_RES_DATA, rx_buf, data_length, protocol_buf);
+}
+
+
+/**
+* \brief Send and read data on one single stream
+*
+* \param[in] stream_id ID of stream
+* \param[in] data      Pointer to data to send
+* \param[in] data_size Size of data to send
+*
+* \return None
+*/
+bool adp_transceive_single_stream(uint16_t stream_id, uint8_t* data, uint8_t data_size, uint8_t* protocol_buf)
+{
+	struct adp_msg_data_stream data_stream;
+	volatile uint8_t status;
+
+	data_stream.number_of_streams = 1;
+	data_stream.stream[0].stream_id = stream_id;
+	data_stream.stream[0].data_size = data_size;
+	data_stream.stream[0].data = data;
+	status = adp_transceive_stream(&data_stream, protocol_buf);
+	
+	return status;
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.h b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.h
new file mode 100644
index 0000000000..4e8656ca6d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.h
@@ -0,0 +1,943 @@
+/**
+ * \file
+ *
+ * \brief ADP service implementation
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef ADP_H_INCLUDED
+#define ADP_H_INCLUDED
+
+#include <compiler.h>
+
+/** Version of ADP implemented here */
+#define ADP_VERSION                 1
+
+/** Start token for ADP data */
+#define ADP_TOKEN                   0xFF
+
+/** Maximum number of streams from PC to target */
+#define ADP_MAX_INCOMMING_STREAMS   5
+/** Maximum number of streams from target to PC */
+#define ADP_MAX_OUTGOING_STREAMS    5
+
+/** Maximum number of bytes target can request from PC in one request */
+#define ADP_MAX_BYTE_REQUEST        20
+
+/** Length of ADP packet header: Token, Message ID, Data Length */
+#define ADP_LENGTH_PACKET_HEADER    4
+
+/** Maximum number of bytes in data part of ADP packet */
+#define ADP_MAX_PACKET_DATA_SIZE    254
+
+/** Maximum number of all bytes in ADP packet */
+#define  ADP_MAX_PACKET_LENGTH (ADP_LENGTH_PACKET_HEADER + ADP_MAX_PACKET_DATA_SIZE)
+
+/** Key used to identify proper handshake message */
+#define ADP_HANDSHAKE_KEY {0x58, 0x99, 0xAB, 0xC9, 0x0F, 0xE2, 0xF7, 0xAA}
+
+/** ADP RGB color definitions. Other RGB values can be used as well */
+#define ADP_COLOR_WHITE   0xFF, 0xFF, 0xFF
+#define ADP_COLOR_BLACK   0x00, 0x00, 0x00
+#define ADP_COLOR_SILVER  0xC0, 0xC0, 0xC0
+#define ADP_COLOR_GRAY    0x80, 0x80, 0x80
+#define ADP_COLOR_MAROON  0x80, 0x00, 0x00
+#define ADP_COLOR_RED     0xFF, 0x00, 0x00
+#define ADP_COLOR_PURPLE  0x80, 0x00, 0x80
+#define ADP_COLOR_FUCHSIA 0xFF, 0x00, 0xFF
+#define ADP_COLOR_GREEN   0x00, 0x80, 0x00
+#define ADP_COLOR_LIME    0x00, 0xFF, 0x00
+#define ADP_COLOR_OLIVE   0x80, 0x80, 0x00
+#define ADP_COLOR_YELLOW  0xFF, 0xFF, 0x00
+#define ADP_COLOR_NAVY    0x00, 0x00, 0x80
+#define ADP_COLOR_BLUE    0x00, 0x00, 0xFF
+#define ADP_COLOR_TEAL    0x00, 0x80, 0x80
+#define ADP_COLOR_AQUA    0x00, 0xFF, 0xFF
+#define ADP_COLOR_ORANGE  0xFF, 0xA5, 0x00
+
+/** States in receive state machine */
+enum rx_state_e {
+	/** We are idle, waiting for a new packet */
+	RX_STATE_IDLE,
+	/** Start symbol received, waiting for Message ID */
+	RX_STATE_WAIT_MSG_ID,
+	/** Message ID received, waiting for data length */
+	RX_STATE_WAIT_LENGTH_LSB,
+	/** Message ID received, waiting for data length */
+	RX_STATE_WAIT_LENGTH_MSB,
+	/** Length received; we are receiving packet data */
+	RX_STATE_GET_DATA,
+	/** Start symbol received */
+	RX_STATE_GOT_SYMBOL,
+};
+
+/** Max length of labels */
+ #define ADP_CONF_MAX_LABEL 20
+
+static inline void adp_set_color(uint8_t* struct_member, uint8_t c_red, uint8_t c_green, uint8_t c_blue)
+{
+	struct_member[0] = c_red;
+	struct_member[1] = c_green;
+	struct_member[2] = c_blue;
+}
+
+
+#define adp_set_string(struct_member, string)                  \
+		Assert(sizeof(struct_member));                         \
+		strncpy(struct_member, string, sizeof(struct_member)); \
+		struct_member[sizeof(struct_member)-1] = '\0';
+
+/* MESSAGE FORMAT */
+SHORTENUM struct adp_msg_format {
+	/* Start token for ADP data */
+	uint8_t protocol_token;
+	/* Describes what data is sent */
+	uint8_t protocol_msg_id;
+	/* Length of data packet */
+	uint16_t data_length;
+	/* Data packet for the message */
+	uint8_t data[ADP_MAX_PACKET_DATA_SIZE];
+};
+
+
+/* MSG_REQ_HANDSHAKE */
+#define MSG_REQ_HANDSHAKE 0x00
+#define MSQ_REQ_HANDSHAKE_LEN 10
+enum adp_handshake_options {
+	/* Use GPIO */
+	ADP_HANDSHAKE_OPTIONS_GPIO,
+	/* Lock configuration */
+	ADP_HANDSHAKE_OPTIONS_LOCK,
+};
+SHORTENUM struct adp_msg_request_handshake {
+	/* Version of protocol on target */
+	uint8_t protocol_version;
+	/* Is GPIO in use in this app?
+	 * Can user change configuration on PC side? 
+	 */
+	uint8_t options;
+	/* Token used to verify ADP protocol */
+	uint8_t key[8];
+};
+
+/* MSG_RES_HANDSHAKE */
+#define MSG_RES_HANDSHAKE 0x10
+enum adp_handshake_status {
+	/* Handshake accepted */
+	ADP_HANDSHAKE_ACCEPTED,
+	/* Handshake rejected. Invalid protocol version */
+	ADP_HANDSHAKE_REJECTED_PROTOCOL,
+	/* Handshake rejected. Other reason */
+	ADP_HANDSHAKE_REJECTED_OTHER,
+};
+SHORTENUM struct adp_msg_response_handshake {
+	enum adp_handshake_status status;
+};
+
+enum adp_handshake_status adp_wait_for_handshake(void);
+
+/* MSG_REQ_STATUS */
+#define MSG_REQ_STATUS 0x02
+#define MSG_REQ_STATUS_LEN 0
+/* This message has no data */
+
+/* MSG_RES_STATUS */
+#define MSG_RES_STATUS 0x12
+enum adp_status_code {
+	/* Invalid packet received */
+	ADP_STATUS_INVALID_PACKET,
+	/* Invalid configuration data received */
+	ADP_STATUS_INVALID_CONFIGURATION,
+	/* Data ready to be transmitted to target */
+	ADP_STATUS_DATA_READY,
+	/* Invalid stream request (req_data) */
+	ADP_STATUS_INVALID_REQUEST,
+	/* No data available on stream (req_data) */
+	ADP_STATUS_NO_DATA,
+	/* Request target software reset */
+	ADP_STATUS_RESET,
+};
+SHORTENUM struct adp_msg_response_status {
+	enum adp_status_code status;
+};
+
+enum adp_status_code adp_request_status(void);
+
+/* MSG_RES_DATA */
+#define MSG_RES_DATA 0x14
+#define MSG_RES_DATA_MAX_LEN (ADP_MAX_BYTE_REQUEST + 4)
+SHORTENUM struct adp_msg_response_data {
+	/* ID of stream */
+	uint8_t stream_id;
+	/* Number of bytes in packet. 
+	 * If the target has requested data from an unknown stream, or if stream 
+	 * has no data to send, this field should be set to 0 and the appropriate 
+	 * status flag should be set.
+	 */
+	uint8_t bytes_sent;
+	/* The data */		
+	uint8_t data[ADP_MAX_BYTE_REQUEST];
+};
+
+void adp_request_data(uint8_t stream_id, uint8_t bytes_to_send, struct adp_msg_response_data *response);
+
+#define MSG_RES_PACKET_DATA_MAX_LEN (ADP_MAX_BYTE_REQUEST + 2)
+SHORTENUM struct adp_msg_packet_data {
+	uint16_t stream_id;
+	uint8_t bytes_sent;
+	uint8_t data[ADP_MAX_BYTE_REQUEST];
+};
+bool adp_receive_packet_data(uint8_t *receive_buf);
+
+/* MSG_CONF_STREAM */
+enum adp_stream_type {
+	ADP_STREAM_EVENT,
+	ADP_STREAM_STRING,
+	ADP_STREAM_UINT_8,
+	ADP_STREAM_INT_8,
+	ADP_STREAM_UINT_16,
+	ADP_STREAM_INT_16,
+	ADP_STREAM_UINT_32,
+	ADP_STREAM_INT_32,
+	ADP_STREAM_XY_8,
+	ADP_STREAM_XY_16,
+	ADP_STREAM_XY_32,
+	ADP_STREAM_BOOL,
+	ADP_STREAM_FLOAT,
+};
+
+enum adp_stream_state {
+	ADP_STREAM_OFF,
+	ADP_STREAM_ON,
+};
+
+enum adp_stream_mode {
+	/* Incoming (normal) */
+	ADP_STREAM_IN,
+	/* Incoming (single value) */
+	ADP_STREAM_IN_SINGLE,
+	/* Outgoing */
+	ADP_STREAM_OUT,
+};
+
+#define MSG_CONF_ACK       0x30
+#define ADP_ACK_NOT_OK     0
+#define ADP_ACK_OK         1
+
+#define MSG_CONF_INFO      0x28
+#define MSG_CONF_INFO_LEN
+bool adp_configure_info(const char* title, const char* description);
+
+#define MSG_CONF_STREAM     0x20
+#define MSG_CONF_STREAM_LEN 5
+SHORTENUM struct adp_msg_configure_stream {
+	/* ID of stream */
+	uint16_t stream_id;
+	/* Stream type */
+	enum adp_stream_type type;
+	/* Stream mode/direction */
+	enum adp_stream_mode mode;
+	/* Stream state */
+	enum adp_stream_state state;
+};
+
+static inline void adp_configure_stream_get_defaults(struct adp_msg_configure_stream *const config)
+{
+	Assert(config);
+	config->stream_id = 0;
+	config->type = ADP_STREAM_UINT_8;
+	config->mode = ADP_STREAM_OUT;
+	config->state = ADP_STREAM_ON;
+}
+
+bool adp_configure_stream(struct adp_msg_configure_stream *const config, const char* label);
+
+/* MSG_CONF_TOGGLE_STREAM */
+#define MSG_CONF_TOGGLE_STREAM   0x21
+#define MSG_CONF_TOGGLE_STREAM_LEN 3
+SHORTENUM struct adp_msg_toggle_stream {
+	uint16_t               stream_id;
+	enum adp_stream_state  state;
+};
+bool adp_toggle_stream(struct adp_msg_toggle_stream *const config);
+
+/* MSG_CONF_GRAPH */
+#define MSG_CONF_GRAPH           0x22
+#define MSG_CONF_GRAPH_LEN       23
+
+enum adp_graph_scale_mode {
+	ADP_GRAPH_SCALE_OFF,
+	ADP_GRAPH_SCALE_AUTO
+};
+
+enum adp_graph_scroll_mode {
+	/* No scrolling */
+	ADP_GRAPH_SCROLL_OFF,
+	/* Stepping */
+	ADP_GRAPH_SCROLL_STEP,
+	/* Scroll */
+	ADP_GRAPH_SCROLL_SCROLL,
+	/* Circular/sweep */
+	ADP_GRAPH_SCROLL_CIRCULAR
+};
+
+SHORTENUM struct adp_msg_configure_graph {
+	/* ID of new graph */
+	uint8_t graph_id;
+	/* Range Xmin value */
+	uint32_t x_min;
+	/* Range Xmax value */
+	uint32_t x_max;
+	/* Xscale numerator */
+	uint32_t x_scale_numerator;
+	/* X range scale value. Set to 0 to enable auto range */
+	uint32_t x_scale_denominator;
+	/* Vertical scaling */
+	enum adp_graph_scale_mode scale_mode;
+	/* RGB background color */
+	uint8_t background_color[3];
+	/* Horizontal scrolling */
+	enum adp_graph_scroll_mode scroll_mode;
+};
+
+static inline void adp_configure_graph_get_defaults(struct adp_msg_configure_graph *const config)
+{
+	Assert(config);
+	config->graph_id = 0;
+	config->x_min = 0;
+	config->x_max = 0;
+	config->x_scale_numerator = 0;
+	config->x_scale_denominator = 0;
+	config->scale_mode = ADP_GRAPH_SCALE_OFF;
+	adp_set_color(config->background_color, ADP_COLOR_WHITE);
+	config->scroll_mode = ADP_GRAPH_SCROLL_SCROLL;
+}
+
+bool adp_configure_graph(struct adp_msg_configure_graph *const config, \
+						const char* graph_label, const char* x_label);
+
+/* MSG_CONF_AXIS */
+#define MSG_CONF_AXIS       0x29
+#define MSG_CONF_AXIS_LEN   24
+SHORTENUM struct adp_msg_conf_axis {
+	/* ID of new axis */
+	uint16_t axis_id;
+	/* ID of graph */
+	uint16_t graph_id;
+	/* Range Ymin value */
+	int32_t y_min;
+	/* Range Ymax value */
+	int32_t y_max;
+	/* X range scale value.	Set to 0 to enable auto range */
+	uint32_t x_scale_numerator;
+	/* X range scale value.	Set to 0 to enable auto range */
+	uint32_t x_scale_denominator;
+	/* Mode */
+	uint8_t mode;                                         // TODO
+	/* RGB color */
+	uint8_t color[3];
+};
+
+static inline void adp_add_axis_to_graph_get_defaults(struct adp_msg_conf_axis *const config)
+{
+	Assert(config);
+	config->axis_id = 0;
+	config->graph_id = 0;
+	config->y_min = 0;
+	config->y_max = 0;
+	config->x_scale_numerator = 0;
+	config->x_scale_denominator = 0;
+	config->mode = 0;
+	adp_set_color(config->color, ADP_COLOR_BLACK);
+}
+
+bool adp_add_axis_to_graph(struct adp_msg_conf_axis *const config, const char* label);
+
+/* MSG_CONF_ADD_STREAM_TO_GRAPH */
+#define MSG_CONF_ADD_STREAM_TO_AXIS       0x23
+#define MSG_CONF_ADD_STREAM_TO_AXIS_LEN   32
+
+#define ADP_AXIS_LINE_bm    0x01
+#define ADP_AXIS_POINTS_bm  0x02
+
+SHORTENUM struct adp_msg_add_stream_to_axis {
+	/* ID of graph */
+	uint16_t graph_id;
+	/* ID of new axis */
+	uint16_t axis_id;
+	/* ID of stream */
+	uint16_t stream_id;
+	/* Sample rate of stream, set to 0 if NA */
+	uint32_t sample_rate_numerator;
+	/* Sample rate of stream, set to 0 if NA */
+	uint32_t sample_rate_denominator;
+	/* Range Ymin value */
+	uint32_t y_scale_numerator;
+	/* Range Ymax value */
+	uint32_t y_scale_denominator;
+	/* Offset of values */
+	uint32_t y_offset;
+	/* Adjust the transparency */
+	uint8_t transparency;
+	/* For graphs:  bit 0 = line on/off
+	 *              bit 1 = points on/off
+	 * For text:    bit 0 = flag
+	 *              bit 1 = text
+	 */
+	uint8_t mode;                           // TODO
+	/* Thickness of line */
+	uint8_t line_thickness;
+	/* RGB color of line */
+	uint8_t line_color[3];
+};
+
+static inline void adp_add_stream_to_axis_get_defaults(struct adp_msg_add_stream_to_axis *const config)
+{
+	Assert(config);
+	config->graph_id = 0;
+	config->axis_id = 0;
+	config->stream_id = 0;
+	config->sample_rate_numerator = 0;
+	config->sample_rate_denominator = 0;
+	config->y_scale_numerator = 0;
+	config->y_scale_denominator = 0;
+	config->y_offset = 0;
+	config->transparency = 0;
+	config->mode = ADP_AXIS_LINE_bm;
+	config->line_thickness = 1;
+	adp_set_color(config->line_color, ADP_COLOR_BLACK);
+}
+
+bool adp_add_stream_to_axis(struct adp_msg_add_stream_to_axis *const config);
+
+/* MSG_CONF_CURSOR_TO_GRAPH */
+#define MSG_CONF_CURSOR_TO_GRAPH     0x24
+#define MSG_CONF_CURSOR_TO_GRAPH_LEN 35
+SHORTENUM struct adp_msg_add_cursor_to_graph {
+	/* ID of streama */
+	uint16_t stream_id;
+	/* ID of graph */
+	uint16_t graph_id;
+	/* ID of axis */
+	uint16_t axis_id;
+	/* Thickness of line */
+	uint8_t thickness;
+	/* RGB color of cursor */
+	uint8_t color[3];
+	/* Starting point of cursor */
+	uint32_t initial_value;
+	/* Minimum allowed value */
+	uint32_t minimum_value;
+	/* Maximum */
+	uint32_t maximum_value;
+	/* Numerator of scaling value */
+	uint32_t scale_numerator;
+	/* Denominator of scaling value */
+	uint32_t scale_denominator;
+	/* Offset of value */
+	uint32_t scale_offset;
+	/* The style of line: Solid, dashed, dotted.. */
+	uint8_t line_style;          // TODO
+};
+
+static inline void adp_add_cursor_to_graph_get_defaults(struct adp_msg_add_cursor_to_graph *const config)
+{
+	Assert(config);
+	config->stream_id = 0;
+	config->graph_id = 0;
+	config->axis_id = 0;
+	config->thickness = 1;
+	adp_set_color(config->color, ADP_COLOR_WHITE);
+	config->initial_value = 0;
+	config->minimum_value = 0;
+	config->maximum_value = 0;
+	config->scale_numerator = 0;
+	config->scale_denominator = 0;
+	config->scale_offset = 0;
+	config->line_style = 0;
+}
+
+bool adp_add_cursor_to_graph(struct adp_msg_add_cursor_to_graph *const config, const char* label);
+
+/* MSG_CONF_GPIO_TO_GRAPH */
+#define MSG_CONF_GPIO_TO_GRAPH       0x25
+#define MSG_CONF_GPIO_TO_GRAPH_LEN   15
+SHORTENUM struct adp_msg_conf_gpio_to_graph {
+	/* ID of graph */
+	uint16_t graph_id;
+	/* GPIO number to add to graph. Bit 0: GPIO0. bit 1: GPIO1 etc. */
+	uint8_t gpio_number;
+	/* Used to group graphs and cursors to the same scale */
+	uint8_t group_id;
+	/* Adjust the transparency */
+	uint8_t transparency;
+	/* Mode */
+	uint16_t mode;                                    // TODO
+	/* Thickness of line */
+	uint8_t line_thickness;
+	/* RGB color of line when GPIO pin is high */
+	uint8_t line_color_high_state[3];
+	/* RGB color of line when GPIO pin is low */
+	uint8_t line_color_low_state[3];
+	/* The style of line */
+	uint8_t line_style;
+};
+
+static inline void adp_gpio_to_graph_get_defaults(struct adp_msg_conf_gpio_to_graph *const config)
+{
+	Assert(config);
+	config->graph_id = 0;
+	config->gpio_number = 0;
+	config->group_id = 0;
+	config->transparency = 0;
+	config->mode = 0;
+	config->line_thickness = 1;
+	adp_set_color(config->line_color_high_state, ADP_COLOR_WHITE);
+	adp_set_color(config->line_color_low_state, ADP_COLOR_WHITE);
+	config->line_style = 0;
+}
+
+bool adp_add_gpio_to_graph(struct adp_msg_conf_gpio_to_graph *const config, \
+						const char* tag_high_state, const char* tag_low_state);
+
+/* MSG_CONF_TERMINAL */
+#define MSG_CONF_TERMINAL        0x26
+#define MSG_CONF_TERMINAL_LEN    10
+SHORTENUM struct adp_msg_conf_terminal {
+	/* ID of terminal */
+	uint16_t terminal_id;
+	/* Number of characters wide */
+	uint8_t width;
+	/* Number of characters high */
+	uint8_t height;
+	/* RGB background color */
+	uint8_t background_color[3];
+	/* RGB background color */
+	uint8_t foreground_color[3];
+};
+
+static inline void adp_configure_terminal_get_defaults(struct adp_msg_conf_terminal *const config)
+{
+	Assert(config);
+	config->terminal_id = 0;
+	config->width = 80;
+	config->height = 25;
+	adp_set_color(config->background_color, ADP_COLOR_WHITE);
+	adp_set_color(config->foreground_color, ADP_COLOR_BLACK);
+}
+
+bool adp_configure_terminal(struct adp_msg_conf_terminal *const config, const char* label);
+
+/* MSG_CONF_ADD_TO_TERMINAL */
+#define MSG_CONF_ADD_TO_TERMINAL       0x27
+#define MSG_CONF_ADD_TO_TERMINAL_LEN   11
+SHORTENUM struct adp_msg_add_stream_to_terminal {
+	/* ID of Terminal */
+	uint16_t terminal_id;
+	/* ID of stream */
+	uint16_t stream_id;
+	/* 0bx x x N T S F F
+	 * N = implicit newline in incoming text
+	 * T = enable tag
+	 * S = timestamped
+	 * F = format (Hex, decimal, binary, ascii)
+	 */
+	uint8_t mode;                                    // TODO
+	/* RGB color of the text stream received */
+	uint8_t text_color[3];
+	/* RGB color of the tag text */
+	uint8_t tag_text_color[3];
+};
+
+static inline void adp_add_stream_to_terminal_get_defaults(struct adp_msg_add_stream_to_terminal *const config)
+{
+	Assert(config);
+	config->terminal_id = 0;
+	config->stream_id = 0;
+	config->mode = 0;
+	adp_set_color(config->text_color, ADP_COLOR_BLACK);
+	adp_set_color(config->tag_text_color, ADP_COLOR_BLACK);
+}
+
+bool adp_add_stream_to_terminal(struct adp_msg_add_stream_to_terminal *const config, const char* tag_text);
+
+/* MSG_CONF_DASHBOARD */
+#define MSG_CONF_DASHBOARD       0x2A
+#define MSG_CONF_DASHBOARD_LEN   7
+SHORTENUM struct adp_msg_conf_dashboard {
+	uint16_t dashboard_id;
+	uint8_t color[3];
+	uint16_t height;
+};
+
+static inline void adp_conf_dashboard_get_defaults(struct adp_msg_conf_dashboard *const config)
+{
+	Assert(config);
+	config->dashboard_id = 0;
+	adp_set_color(config->color, ADP_COLOR_BLACK);
+	config->height = 100;
+}
+
+bool adp_add_dashboard(struct adp_msg_conf_dashboard *const config, const char* label);
+
+/* MSG_CONF_DASHBOARD_ELEMENT */
+#define MSG_CONF_DASHBOARD_ELEMENT 0x2B
+
+enum adp_dashboard_element_type {
+	ADP_ELEMENT_TYPE_LABEL,
+	ADP_ELEMENT_TYPE_BUTTON,
+	ADP_ELEMENT_TYPE_SLIDER,
+	ADP_ELEMENT_TYPE_PROGRESS,
+	ADP_ELEMENT_TYPE_SIGNAL,
+	ADP_ELEMENT_TYPE_SEGMENT,
+	ADP_ELEMENT_TYPE_GRAPH,
+	ADP_ELEMENT_TYPE_TEXT,
+	ADP_ELEMENT_TYPE_RADIO,
+	ADP_ELEMENT_TYPE_PIE,
+};
+
+#define MSG_CONF_DASHBOARD_COMMON_LEN    14
+#define ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS \
+	uint16_t  dashboard_id; \
+	uint16_t  element_id;   \
+	uint8_t   z_index;      \
+	uint16_t  x;            \
+	uint16_t  y;            \
+	uint16_t  width;        \
+	uint16_t  height;       \
+	enum adp_dashboard_element_type element_type 
+
+SHORTENUM struct adp_msg_conf_dashboard_element_common {
+	/* Dashboard ID */
+	uint16_t  dashboard_id;
+	/* Unique ID of element */
+	uint16_t  element_id;
+	/* Order index */
+	uint8_t   z_index;
+	/* X-coordinate of element location. 0 is leftmost position on dashboard */
+	uint16_t  x;
+	/* Y-coordinate of element location. 0 is topmost position on dashboard */
+	uint16_t  y;
+	/* Width of element */
+	uint16_t  width;
+	/* Height of element */
+	uint16_t  height;
+	/* See each element type below */
+	enum adp_dashboard_element_type element_type;
+};
+
+static inline void adp_conf_dashboard_element_get_defaults(struct adp_msg_conf_dashboard_element_common *const config)
+{
+	Assert(config);
+	config->dashboard_id = 0;
+	config->element_id = 0;
+	config->z_index = 0;
+	config->x = 0;
+	config->y = 0;
+	config->width = 0;
+	config->height = 0;
+}
+
+enum adp_label_attribute_alignment {
+	BOLD_OFF_ITALIC_OFF,
+	BOLD_ON_ITALIC_OFF,
+	BOLD_OFF_ITALIC_ON,
+	BOLD_ON_ITALIC_ON,
+};
+
+enum adp_label_horisontal_alignment {
+	HORISONTAL_ALIGNMENT_LEFT,
+	HORISONTAL_ALIGNMENT_CENTER,
+	HORISONTAL_ALIGNMENT_RIGHT,
+};
+
+enum adp_label_vertical_alignment {
+	VERTICAL_ALIGNMENT_TOP,
+	VERTICAL_ALIGNMENT_CENTER,
+	VERTICAL_ALIGNMENT_BOTTOM,
+};
+
+#define ADP_ELEMENT_TYPE_LABEL_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 12)
+SHORTENUM struct adp_msg_conf_dashboard_element_label {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint8_t                             font_size;
+	uint8_t                             attribute;                               // TODO
+	enum adp_label_horisontal_alignment horisontal_alignment;
+	enum adp_label_vertical_alignment   vertical_alignment;
+	uint8_t                             background_transparency;
+	uint8_t                             background_color[3];
+	uint8_t                             foreground_transparency;
+	uint8_t                             foreground_color[3];
+};
+
+static inline void adp_conf_dashboard_label_get_defaults(struct adp_msg_conf_dashboard_element_label *const config)
+{
+	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+	config->element_type = ADP_ELEMENT_TYPE_LABEL;
+	config->font_size = 10;
+	config->attribute = 0;
+	config->horisontal_alignment = HORISONTAL_ALIGNMENT_LEFT;
+	config->vertical_alignment = VERTICAL_ALIGNMENT_CENTER;
+	config->background_transparency = 0;
+	adp_set_color(config->background_color, ADP_COLOR_BLACK);
+	config->foreground_transparency = 0;
+	adp_set_color(config->foreground_color, ADP_COLOR_BLACK);
+}
+
+bool adp_add_label_to_dashboard(struct adp_msg_conf_dashboard_element_label *const config, const char* label);
+
+#define ADP_ELEMENT_TYPE_BUTTON_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 1)
+
+SHORTENUM struct adp_msg_conf_dashboard_element_button {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint8_t font_size;
+};
+
+static inline void adp_conf_dashboard_button_get_defaults(struct adp_msg_conf_dashboard_element_button *const config)
+{
+	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+	config->element_type = ADP_ELEMENT_TYPE_BUTTON;
+	config->font_size = 10;
+}
+
+bool adp_add_button_to_dashboard(struct adp_msg_conf_dashboard_element_button *const config, const char* label);
+
+#define ADP_ELEMENT_TYPE_SLIDER_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 12)
+SHORTENUM struct adp_msg_conf_dashboard_element_slider {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint32_t minimum_value;
+	uint32_t maximum_value;
+	uint32_t initial_value;
+};
+
+static inline void adp_conf_dashboard_slider_get_defaults(struct adp_msg_conf_dashboard_element_slider *const config)
+{
+	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+	config->element_type = ADP_ELEMENT_TYPE_SLIDER;
+	config->minimum_value = 0;
+	config->maximum_value = 100;
+	config->initial_value = 0;
+}
+
+bool adp_add_slider_to_dashboard(struct adp_msg_conf_dashboard_element_slider *const config);
+
+#define ADP_ELEMENT_TYPE_SIGNAL_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 8)
+SHORTENUM struct adp_msg_conf_dashboard_element_signal {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint8_t on_transparency;
+	uint8_t on_color[3];
+	uint8_t off_transparency;
+	uint8_t off_color[3];
+};
+
+static inline void adp_conf_dashboard_signal_get_defaults(struct adp_msg_conf_dashboard_element_signal *const config)
+{
+	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+	config->element_type = ADP_ELEMENT_TYPE_SIGNAL;
+	config->on_transparency = 0;
+	adp_set_color(config->on_color, ADP_COLOR_WHITE);
+	config->off_transparency = 0;
+	adp_set_color(config->off_color, ADP_COLOR_BLACK);
+}
+
+bool adp_add_signal_to_dashboard(struct adp_msg_conf_dashboard_element_signal *const config);
+
+#define ADP_ELEMENT_TYPE_PROGRESS_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 15)
+SHORTENUM struct adp_msg_conf_dashboard_element_progress {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint32_t minimum_value;
+	uint32_t maximum_value;
+	uint32_t initial_value;
+	uint8_t color[3];
+};
+
+static inline void adp_conf_dashboard_progress_get_defaults(struct adp_msg_conf_dashboard_element_progress *const config)
+{
+	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+	config->element_type = ADP_ELEMENT_TYPE_PROGRESS;
+	config->minimum_value = 0;
+	config->maximum_value = 100;
+	config->initial_value = 0;
+	adp_set_color(config->color, ADP_COLOR_BLACK);
+}
+
+bool adp_add_progress_to_dashboard(struct adp_msg_conf_dashboard_element_progress *const config);
+
+#define ADP_ELEMENT_TYPE_SEGMENT_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 6)
+SHORTENUM struct adp_msg_conf_dashboard_element_segment {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	/* Values: 1 ~ 20 */
+	uint8_t segment_count;
+	/* Values: 2 ~ 16*/
+	uint8_t base;
+	uint8_t transparency;
+	uint8_t color[3];
+};
+
+static inline void adp_conf_dashboard_segment_get_defaults(struct adp_msg_conf_dashboard_element_segment *const config)
+{
+	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+	config->element_type = ADP_ELEMENT_TYPE_SEGMENT;
+	config->segment_count = 1;
+	config->base = 10;
+	config->transparency = 0;
+	adp_set_color(config->color, ADP_COLOR_BLACK);
+}
+
+bool adp_add_segment_to_dashboard(struct adp_msg_conf_dashboard_element_segment *const config);
+
+/* MSG_CONF_ADD_GRAPH_TO_ELEMENT */
+#define  ADP_ELEMENT_TYPE_GRAPH_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 27)
+typedef union {
+	struct {
+		uint8_t mouse:1;
+		uint8_t fit_graph:1;
+		uint8_t :6;
+	} bit;
+	uint8_t reg;
+} mode_type;
+
+SHORTENUM struct adp_msg_conf_dashboard_element_graph {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint8_t title_color[3];
+	uint8_t background_color[3];
+	uint8_t graph_background_color[3];
+	uint8_t plot_count;
+	float x_min;
+	float x_max;
+	float y_min;
+	float y_max;
+	mode_type mode;
+};
+
+static inline void adp_conf_dashboard_graph_get_defaults(struct adp_msg_conf_dashboard_element_graph *const config)
+{
+	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+	config->element_type = ADP_ELEMENT_TYPE_GRAPH;
+	adp_set_color(config->title_color, ADP_COLOR_WHITE);
+	adp_set_color(config->background_color, ADP_COLOR_BLACK);
+	adp_set_color(config->graph_background_color, ADP_COLOR_BLACK);
+	config->plot_count = 1;
+	config->x_min = 0;
+	config->x_max = 10;
+	config->y_min = 0;
+	config->y_max = 5;
+	config->mode.bit.fit_graph = 1;
+	config->mode.bit.mouse = 0;
+}
+
+bool adp_add_graph_to_dashboard(struct adp_msg_conf_dashboard_element_graph *const config, const char* title);
+
+
+/* MSG_CONF_ADD_TEXT_TO_ELEMENT */
+#define  ADP_ELEMENT_TYPE_TEXT_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 12)
+SHORTENUM struct adp_msg_conf_dashboard_element_text {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint8_t minimum[4];
+	uint8_t maximum[4];
+	uint8_t value[4];
+};
+
+bool adp_add_text_to_dashboard(struct adp_msg_conf_dashboard_element_text *const config);
+
+/* MSG_CONF_ADD_RADIO_TO_ELEMENT */
+#define  ADP_ELEMENT_TYPE_RADIO_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 3)
+
+enum adp_radio_orientation {
+	HORIZONTAL,
+	VERTICAL,
+};
+
+SHORTENUM struct adp_msg_conf_dashboard_element_radio {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint8_t font_size;
+	uint8_t number_items;
+	enum adp_radio_orientation orientation;
+};
+bool adp_add_radio_to_dashboard(struct adp_msg_conf_dashboard_element_radio *const config, const char* text);
+
+/* MSG_CONF_ADD_PIE_TO_ELEMENT */
+#define  ADP_ELEMENT_TYPE_PIE_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 7)
+
+SHORTENUM struct adp_msg_conf_dashboard_element_pie {
+	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+	uint8_t background_color[3];
+	uint8_t title_color[3];
+	uint8_t number_slices;
+};
+bool adp_add_pie_to_dashboard(struct adp_msg_conf_dashboard_element_pie *const config, const char* title);
+
+/* MSG_CONF_ADD_STREAM_TO_ELEMENT */
+#define MSG_CONF_ADD_STREAM_TO_ELEMENT       0x2C
+#define MSG_CONF_ADD_STREAM_TO_ELEMENT_LEN   6
+
+SHORTENUM struct adp_conf_add_stream_to_element {
+	uint16_t dashboard_id;
+	uint16_t element_id;
+	uint16_t stream_id;
+};
+
+bool adp_add_stream_to_element(struct adp_conf_add_stream_to_element *const config);
+
+/* MSG_DATA_STREAM */
+#define MSG_DATA_STREAM 0x40
+SHORTENUM struct adp_msg_data_stream_data {
+	uint16_t stream_id;
+	uint8_t data_size;
+	uint8_t *data;
+};
+
+SHORTENUM struct adp_msg_data_stream {
+	uint8_t number_of_streams;
+	struct adp_msg_data_stream_data stream[ADP_MAX_OUTGOING_STREAMS];
+};
+
+bool adp_send_stream(struct adp_msg_data_stream *const stream_data, uint8_t* receive_buf);
+bool adp_send_single_stream(uint8_t stream_id, uint8_t* data, uint8_t data_size, uint8_t* receive_buf);
+bool adp_transceive_stream(struct adp_msg_data_stream *const stream_data, uint8_t *receive_buf);
+bool adp_transceive_single_stream(uint16_t stream_id, uint8_t* data, uint8_t data_size, uint8_t* receive_buf);
+
+/* Init SPI/TWI interface used. And some other misc init */
+void adp_init(void);
+uint16_t adp_add_send_byte(uint8_t* buffer, uint8_t index, uint8_t* data, uint16_t length);
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/adp_interface.h b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp_interface.h
new file mode 100644
index 0000000000..91ab6ed27c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp_interface.h
@@ -0,0 +1,55 @@
+/**
+ * \file
+ *
+ * \brief ADP interface header file
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef ADP_INTERFACE_H_INCLUDED
+#define ADP_INTERFACE_H_INCLUDED
+
+/* Prototypes of communication functions used to setup, send and receive data */
+enum status_code adp_interface_init(void);
+void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf);
+enum status_code adp_interface_read_response(uint8_t* rx_buf, uint16_t length);
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_spi.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_spi.c
new file mode 100644
index 0000000000..1eaab719ab
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_spi.c
@@ -0,0 +1,150 @@
+/**
+ * \file
+ *
+ * \brief ADP SPI interface implementation
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <asf.h>
+#include "adp_interface.h"
+
+//! \name Embedded debugger SPI interface definitions
+//@{
+#define EDBG_SPI_MODULE           SPI
+//@}
+
+#define SPI_CHIP_SEL  SPI_NPCS3_PA5_GPIO
+
+#define SPI_DEVICE_ID         3
+#define SPI_BAUDRATE          1500000
+
+struct spi_device SPI_DEVICE = {
+	/** Board specific select id */
+	.id = SPI_DEVICE_ID
+};
+
+/**
+* \brief Send SPI start condition
+*
+*/
+static void adp_interface_send_start(void)
+{
+	spi_select_device(EDBG_SPI_MODULE, &SPI_DEVICE);
+}
+
+/**
+* \brief Send SPI stop condition
+*
+*/
+static void adp_interface_send_stop(void)
+{
+	spi_deselect_device(EDBG_SPI_MODULE, &SPI_DEVICE);
+}
+
+/**
+* \brief Sends and reads data byte on SPI
+*
+* \param[in]  data     Data byte to send
+* \param[in]  tx_data  SPI character to transmit
+* \param[out] rx_data  Pointer to store the received SPI character
+*/
+static void adp_interface_transceive(uint8_t *tx_data, uint8_t *rx_data, uint16_t length)
+{
+	spi_transceive_packet(EDBG_SPI_MODULE, tx_data, rx_data, length);
+}
+
+/**
+* \brief Initialize EDBG SPI communication for SAM
+*
+*/
+enum status_code adp_interface_init(void)
+{
+	sysclk_init();
+
+	/* Configure the SPI interface */
+	spi_master_init(EDBG_SPI_MODULE);
+	spi_master_setup_device(EDBG_SPI_MODULE, &SPI_DEVICE, SPI_MODE_0,
+			SPI_BAUDRATE, 0);
+	spi_enable(EDBG_SPI_MODULE);
+
+	return STATUS_OK;
+}
+
+/**
+* \brief Sends and reads protocol packet data byte on SPI
+*
+* \param[in]  tx_buf  Pointer to send the protocol packet data
+* \param[in]  length  The length of the send protocol packet data
+* \param[out] rx_buf  Pointer to store the received SPI character
+*/
+void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf)
+{
+	/* Send SPI start condition */
+	adp_interface_send_start();
+
+	adp_interface_transceive(tx_buf, rx_buf, length);
+	
+	/* Send SPI end condition */
+	adp_interface_send_stop();
+}
+
+/**
+* \brief Read response on SPI from PC
+*
+* return Status
+* \param[in]  rx_buf  Pointer to receive the data
+* \param[in]  length  The length of the read data
+* \param[out] rx_buf  Pointer to store the received SPI character
+*/
+enum status_code adp_interface_read_response(uint8_t* rx_buf, uint16_t length)
+{
+	enum status_code status;
+
+	/* Send SPI start condition */
+	adp_interface_send_start();	
+	status = spi_read_packet(EDBG_SPI_MODULE, rx_buf, length);
+	/* Send SPI end condition */
+	adp_interface_send_stop();
+
+	return status;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_twi.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_twi.c
new file mode 100644
index 0000000000..f29b018215
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_twi.c
@@ -0,0 +1,127 @@
+/**
+ * \file
+ *
+ * \brief ADP service implementation
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <compiler.h>
+#include <asf.h>
+#include "adp_interface.h"
+
+//! \name Embedded debugger TWI interface definitions
+//@{
+#define EDBG_TWI_MODULE           TWI0
+//@}
+
+#define TWI_EDBG_SLAVE_ADDR 0x28
+#define TIMEOUT 1000
+
+/**
+* \brief Initialize EDBG TWI interface for SAM4S
+*
+*/
+enum status_code adp_interface_init(void)
+{
+	sysclk_init();
+
+	/* Configure the TWI interface */
+	twi_master_options_t opt = {
+		.speed = 100000,
+		.chip  = TWI_EDBG_SLAVE_ADDR
+	};
+	return twi_master_setup(EDBG_TWI_MODULE, &opt);
+}
+
+/**
+* \brief Send data on TWI
+*
+* \param[in] data   Pointer to data to send
+* \param[in] length Number of bytes to send
+*/
+static enum status_code adp_interface_send(uint8_t* tx_buf, uint16_t length)
+{
+	twi_package_t packet_write = {
+		.chip         = TWI_EDBG_SLAVE_ADDR, /* TWI slave bus address */
+		.buffer       = tx_buf,        /* transfer data source buffer */
+		.length       = length               /* transfer data size (bytes) */
+	};
+	return twi_master_write(EDBG_TWI_MODULE, &packet_write);
+}
+
+/**
+* \brief Read data on TWI
+*
+* \param[out] data   Pointer to place received data
+* \param[in]  length Number of bytes to receive
+*/
+enum status_code adp_interface_read_response(uint8_t *data,	uint16_t length)
+{
+	enum status_code status = ERR_IO_ERROR;
+	uint8_t data_len = 0;
+	
+	twi_package_t packet_read = {
+		.chip         = TWI_EDBG_SLAVE_ADDR, // TWI slave bus address
+		.buffer       = &data_len,                // transfer data destination buffer
+		.length       = 1               // transfer data size (bytes)
+	};
+	twi_master_read(EDBG_TWI_MODULE, &packet_read);
+	
+	if(data_len != 0){
+		packet_read.length = data_len;
+		packet_read.buffer = data;
+		status = twi_master_read(EDBG_TWI_MODULE, &packet_read);	
+	}
+
+	return status;
+}
+
+/**
+* \brief Sends and reads protocol packet data byte on I2C
+*
+* \param[in]  tx_buf  Pointer to send the protocol packet data
+* \param[in]  length  The length of the send protocol packet data
+* \param[out] rx_buf  Pointer to store the received I2C character
+*/
+void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf)
+{
+	adp_interface_send(tx_buf, length);
+	adp_interface_read_response(rx_buf, length);
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_spi.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_spi.c
new file mode 100644
index 0000000000..f23ab10742
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_spi.c
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief ADP service implementation
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#include <asf.h>
+#include "adp_interface.h"
+
+struct spi_module edbg_spi;
+struct spi_slave_inst slave;
+
+/**
+* \brief Send SPI start condition
+*
+*/
+static void adp_interface_send_start(void)
+{
+	spi_select_slave(&edbg_spi, &slave, true);
+}
+
+/**
+* \brief Send SPI stop condition
+*
+*/
+static void adp_interface_send_stop(void)
+{
+	spi_select_slave(&edbg_spi, &slave, false);
+}
+
+/**
+* \brief Sends and reads data byte on SPI
+*
+* \param[in]  data     Data byte to send
+* \param[in]  tx_data  SPI character to transmit
+* \param[out] rx_data  Pointer to store the received SPI character
+*/
+static void adp_interface_transceive(uint8_t *tx_data, uint8_t *rx_data, uint16_t length)
+{
+	spi_transceive_buffer_wait(&edbg_spi, tx_data, rx_data, length);
+}
+
+/**
+* \brief Initialize EDBG SPI communication for SAM0
+*
+*/
+enum status_code adp_interface_init(void)
+{
+	enum status_code return_value;
+
+	system_init();
+
+	struct spi_slave_inst_config slave_dev_config;
+
+	struct spi_config config;
+
+	spi_slave_inst_get_config_defaults(&slave_dev_config);
+	slave_dev_config.ss_pin = (EDBG_SPI_SERCOM_PINMUX_PAD1 >> 16) & 0xFF;
+	spi_attach_slave(&slave, &slave_dev_config);
+
+	spi_get_config_defaults(&config);
+	config.mode_specific.master.baudrate = 1000000;
+	config.mux_setting = EDBG_SPI_SERCOM_MUX_SETTING;
+	config.pinmux_pad0 = EDBG_SPI_SERCOM_PINMUX_PAD0;
+	config.pinmux_pad1 = PINMUX_UNUSED;
+	config.pinmux_pad2 = EDBG_SPI_SERCOM_PINMUX_PAD2;
+	config.pinmux_pad3 = EDBG_SPI_SERCOM_PINMUX_PAD3;
+
+	return_value = spi_init(&edbg_spi, EDBG_SPI_MODULE, &config);
+
+	spi_enable(&edbg_spi);
+
+	return return_value;
+}
+
+/**
+* \brief Sends and reads protocol packet data byte on SPI
+*
+* \param[in]  tx_buf  Pointer to send the protocol packet data
+* \param[in]  length  The length of the send protocol packet data
+* \param[out] rx_buf  Pointer to store the received SPI character
+*/
+void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf)
+{
+	/* Send SPI start condition */
+	adp_interface_send_start();
+
+	adp_interface_transceive(tx_buf, rx_buf, length);
+	
+	/* Send SPI end condition */
+	adp_interface_send_stop();
+}
+
+/**
+* \brief Read response on SPI from PC
+*
+* return Status
+* \param[in]  rx_buf  Pointer to receive the data
+* \param[in]  length  The length of the read data
+* \param[out] rx_buf  Pointer to store the received SPI character
+*/
+enum status_code adp_interface_read_response(uint8_t* rx_buf, uint16_t length)
+{
+	bool status;
+
+	/* Send SPI start condition */
+	adp_interface_send_start();	
+	status = spi_read_buffer_wait(&edbg_spi, rx_buf, length, 0xFF);
+	/* Send SPI end condition */
+	adp_interface_send_stop();
+
+	return status;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_twi.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_twi.c
new file mode 100644
index 0000000000..18d5202cdf
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_twi.c
@@ -0,0 +1,133 @@
+/**
+ * \file
+ *
+ * \brief ADP service implementation
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#include <asf.h>
+#include <adp_interface.h>
+
+#define EDBG_TWI EDBG_I2C_MODULE
+#define TWI_EDBG_SLAVE_ADDR 0x28
+#define TIMEOUT 1000
+
+struct i2c_master_module i2c_master_instance;
+
+/**
+* \brief Initialize EDBG I2C communication for SAM0
+*
+*/
+enum status_code adp_interface_init(void)
+{
+	enum status_code return_value;
+
+	system_init();
+
+	struct i2c_master_config config_i2c_master;
+	i2c_master_get_config_defaults(&config_i2c_master);
+	config_i2c_master.buffer_timeout = 10000;
+	return_value = i2c_master_init(&i2c_master_instance, EDBG_TWI, &config_i2c_master);
+	i2c_master_enable(&i2c_master_instance);
+	return return_value;
+}
+
+static enum status_code adp_interface_send(uint8_t* tx_buf, uint16_t length)
+{
+	enum status_code status;
+	
+	struct i2c_master_packet packet = {
+		.address = TWI_EDBG_SLAVE_ADDR,
+		.data_length = length,
+		.data = tx_buf,
+	};
+	/* Send data to PC */
+	status = i2c_master_write_packet_wait(&i2c_master_instance, &packet);
+	
+	return status;
+}
+
+/**
+* \brief Read response on I2C from PC
+*
+* return Status
+* \param[in]  rx_buf  Pointer to receive the data
+* \param[in]  length  The length of the read data
+* \param[out] rx_buf  Pointer to store the received SPI character
+*/
+enum status_code adp_interface_read_response(uint8_t* rx_buf, uint16_t length)
+{
+	enum status_code status = STATUS_ERR_IO;
+	uint8_t data_len = 0;
+
+	struct i2c_master_packet packet = {
+		.address = TWI_EDBG_SLAVE_ADDR,
+		.data_length = 1,
+		.data = &data_len,
+	};
+	i2c_master_read_packet_wait(&i2c_master_instance, &packet);
+	
+	if (data_len != 0)
+	{
+		packet.data_length = data_len;
+		packet.data = rx_buf;
+		status = i2c_master_read_packet_wait(&i2c_master_instance, &packet);
+	}
+	
+	return status;
+}
+
+/**
+* \brief Sends and reads protocol packet data byte on I2C
+*
+* \param[in]  tx_buf  Pointer to send the protocol packet data
+* \param[in]  length  The length of the send protocol packet data
+* \param[out] rx_buf  Pointer to store the received I2C character
+*/
+void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf)
+{	
+	adp_interface_send(tx_buf, length);
+	adp_interface_read_response(rx_buf, length);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.c b/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.c
new file mode 100644
index 0000000000..9d06e0d86e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.c
@@ -0,0 +1,492 @@
+/**
+ * \file
+ *
+ * \brief Calendar service.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "compiler.h"
+#include "calendar.h"
+#include <stdio.h>
+
+//! Unix epoch year
+#define EPOCH_YEAR 1970
+
+//! Number of seconds in a day
+#define SECS_PER_DAY 86400UL
+
+//! Number of seconds in an hour
+#define SECS_PER_HOUR 3600UL
+
+//! Number of seconds in a minute
+#define SECS_PER_MINUTE 60UL
+
+//! Number of days in a specified month. Index 1 for leap year, else 0.
+const uint8_t month[2][12] = {
+	{ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 },
+	{ 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }
+};
+
+/**
+ * \internal
+ * \brief Check if a year is a leap year
+ *
+ * Returns true or false depending if the input year is a leap year or not.
+ *
+ * \param year the year in format YYYY to check for leap year or not
+ *
+ * \retval true  if the year is a leap year
+ * \retval false if the year is not a leap year
+ */
+static bool calendar_leapyear(uint16_t year)
+{
+	if(!((year) % 4) && (((year) % 100) || !((year) % 400))) {
+		return true;
+	} else {
+		return false;
+	}
+}
+
+/**
+ * \internal
+ * \brief Find number of days in a year
+ *
+ * Returns the number of days in a year, depending if the input is leap year
+ * or not.
+ *
+ * \param year the year in format YYYY to check number of days
+ *
+ * \retval 366 if the year is a leap year
+ * \retval 365 if the year is not a leap year
+ */
+static uint16_t calendar_yearsize(uint16_t year)
+{
+	if (calendar_leapyear(year)) {
+		return 366;
+	} else {
+		return 365;
+	}
+}
+
+/**
+ * \internal
+ * \brief Add a year to a date
+ *
+ * Adds one year to specified date as long as the current year is before 2105.
+ *
+ * \param *date the date to add a year to
+ *
+ */
+static void calendar_add_year_to_date(struct calendar_date *date)
+{
+	if (date->year < 2105) {
+		date->year++;
+	}
+}
+
+/**
+ * \internal
+ * \brief Add a month to a date
+ *
+ * Adds one month to specified date. If month is december, increment year.
+ *
+ * \param *date the date to add a month to
+ *
+ */
+static void calendar_add_month_to_date(struct calendar_date *date)
+{
+	uint8_t months = date->month;
+	months++;
+	if (months == 12){
+		months = 0;
+		calendar_add_year_to_date(date);
+	}
+	date->month = months;
+}
+
+/**
+ * \internal
+ * \brief Add a day to a date
+ *
+ * Adds one day to specified date. If day is the last of the month, increment
+ * month.
+ *
+ * \param *date the date to add a day to
+ *
+ */
+static void calendar_add_day_to_date(struct calendar_date *date)
+{
+	uint8_t dates = date->date;
+	uint8_t months = date->month;
+	uint8_t year = date->year;
+
+	dates++;
+	if (dates == month[calendar_leapyear(year)][months]) {
+		dates = 0;
+		calendar_add_month_to_date(date);
+	}
+	date->dayofweek++;
+	if (date->dayofweek == 7) {
+		date->dayofweek = 0;
+	}
+	date->date = dates;
+}
+
+/**
+ * \internal
+ * \brief Add an hour to a date
+ *
+ * Adds one hour to specified date. If hour is 23, increment day.
+ *
+ * \param *date the date to add an hour to
+ *
+ */
+static void calendar_add_hour_to_date(struct calendar_date *date)
+{
+	int8_t hour = date->hour;
+	hour++;
+	if (hour == 24){
+		hour = 0;
+		calendar_add_day_to_date(date);
+	}
+	date->hour = hour;
+}
+
+/**
+ * \internal
+ * \brief Add a minute to a date
+ *
+ * Adds one minute to specified date. If minute is 59, increment hour.
+ *
+ * \param *date the date to add a minute to
+ *
+ */
+static void calendar_add_minute_to_date(struct calendar_date *date)
+{
+	uint8_t minute = date->minute;
+	minute++;
+	if (minute == 60){
+		minute = 0;
+		calendar_add_hour_to_date(date);
+	}
+	date->minute = minute;
+}
+
+/**
+ * \brief Check if a date is valid
+ *
+ * Checks that number of seconds, minutes and hours is a valid value.
+ * Checks that number of days does not exceed number of days in current month.
+ * Checks that number of months is a valid value, and checks that year is
+ * between 1970 (epoch year) and 2106 (overflow year).
+ *
+ * \param *date the date to check if valid
+ *
+ */
+bool calendar_is_date_valid(struct calendar_date *date)
+{
+	// Make sure time is valid
+	if ((date->second >= 60) || (date->minute >= 60) || (date->hour >= 24)) {
+		return false;
+	}
+
+	// Make sure month and date is valid
+	if ((date->month >= 12) || (date->date >=31)) {
+		return false;
+	}
+
+	// Make sure days in month are not more than it should be
+	if (date->date >= month[calendar_leapyear(date->year)][date->month]) {
+		return false;
+	}
+
+	// Make sure year is not earlier than 1970 and before 2106
+	if ((date->year < EPOCH_YEAR) || (date->year >= 2106)) {
+		return false;
+	} else {
+		return true;
+	}
+}
+
+/**
+ * \brief Convert a UNIX timestamp to a date
+ *
+ * Finds the corresponding date and time for a UNIX timestamp.
+ *
+ * \param timestamp  UNIX timestamp
+ * \param date_out   Date to store result
+ *
+ */
+void calendar_timestamp_to_date(uint32_t timestamp,
+		struct calendar_date *date_out)
+{
+	uint32_t day_number;
+	uint32_t day_clock;
+
+	date_out->year = EPOCH_YEAR;
+	date_out->month = 0;
+
+	day_clock = timestamp % SECS_PER_DAY;
+	day_number = timestamp / SECS_PER_DAY;
+
+	date_out->second = day_clock % SECS_PER_MINUTE;
+	date_out->minute = (day_clock % SECS_PER_HOUR) / SECS_PER_MINUTE;
+	date_out->hour = day_clock / SECS_PER_HOUR;
+	date_out->dayofweek = (day_number + 4) % 7;
+
+	while (day_number >= calendar_yearsize(date_out->year)) {
+		day_number -= calendar_yearsize(date_out->year);
+		date_out->year++;
+	}
+
+	while (day_number >=
+			month[calendar_leapyear(date_out->year)][date_out->month]) {
+		day_number -= month[calendar_leapyear(date_out->year)][date_out->month];
+		date_out->month++;
+	}
+	date_out->date = day_number;
+}
+
+/**
+ * \brief Convert a UNIX timestamp to a date in a given time zone.
+ *
+ * The provided UNIX timestamp is converted to the corresponding time in the
+ * provided time zone.
+ *
+ * \param timestamp  UNIX timestamp
+ * \param hour       Hour offset from UTC (UTC-12 to UTC+14)
+ * \param min        Minute offset from UTC (0, 15, 30, 45)
+ * \param date_out   Date to store result
+ *
+ */
+void calendar_timestamp_to_date_tz(uint32_t timestamp, int8_t hour,
+		uint8_t min, struct calendar_date *date_out)
+{
+	// Multiply timezone offset by seconds, and add to timestamp
+	if (hour >= 0) {
+		calendar_timestamp_to_date((timestamp + (SECS_PER_HOUR * hour) +
+				(SECS_PER_MINUTE * min)), date_out);
+	} else {
+		calendar_timestamp_to_date((timestamp + (SECS_PER_HOUR * hour) -
+				(SECS_PER_MINUTE * min)), date_out);
+	}
+}
+
+/**
+ * \brief Convert a date to a UNIX timestamp.
+ *
+ * \note
+ * If date is invalid, timestamp 0 will be returned.
+ *
+ * \param date  Date
+ *
+ * \return The corresponding UNIX timestamp
+ * \retval 0 if date is not valid
+ */
+uint32_t calendar_date_to_timestamp(struct calendar_date *date)
+{
+
+	// Make sure date is valid
+	if (!calendar_is_date_valid(date))
+		return 0;
+
+	uint32_t timestamp = 0;
+	uint8_t date_month;
+	uint16_t date_year;
+
+	date_month = date->month;
+	date_year = date->year;
+
+	// Add number of seconds elapsed in current month
+	timestamp += (date->date * SECS_PER_DAY) + (date->hour * SECS_PER_HOUR) +
+			(date->minute * SECS_PER_MINUTE) + date->second;
+
+	while (date_month != 0) {
+		date_month--;
+		// Add number of seconds in months of current year
+		timestamp += month[calendar_leapyear(date_year)][date_month]
+				* SECS_PER_DAY;
+	}
+	while (date_year > EPOCH_YEAR) {
+		date_year--;
+		// Add number of seconds in all years since epoch year
+		timestamp += calendar_yearsize(date_year) * SECS_PER_DAY;
+	}
+
+	return timestamp;
+}
+
+/**
+ * \brief This function converts a date in a given time zone to a UNIX
+ * timestamp
+ * \note
+ * If date is invalid, timestamp 0 will be returned.
+ *
+ * \param date   Date
+ * \param hour   Hour offset from UTC (UTC-12 to UTC+14)
+ * \param min    Minute offset from UTC (0, 15, 30, 45)
+ *
+ * \return The corresponding UNIX timestamp
+ * \retval 0 if date is not valid
+ */
+uint32_t calendar_date_to_timestamp_tz(struct calendar_date *date, int8_t hour,
+		uint8_t min)
+{
+	uint32_t timestamp = calendar_date_to_timestamp(date);
+	if (timestamp == 0) {
+		return 0;
+	} else {
+		// Subtract the seconds of offset in time zone offset from timestamp
+		if (hour >= 0) {
+			return (timestamp - (SECS_PER_HOUR * hour + SECS_PER_MINUTE *
+					min));
+		} else {
+			return (timestamp - (SECS_PER_HOUR * hour - SECS_PER_MINUTE *
+					min));
+		}
+	}
+}
+
+/**
+ * \brief This function calculates the time difference between to dates.
+ *
+ * The time difference is provided as number of years, months, days, hours,
+ * minutes and seconds between the dates. If end date is before start date,
+ * the dates are switched.
+ *
+ * \param date_end         The end date
+ * \param date_start       The start date
+ * \param date_out         The time between the dates
+ *
+ */
+void calendar_time_between_dates(struct calendar_date *date_end,
+		struct calendar_date *date_start, struct calendar_date *date_out)
+{
+	uint32_t timestamp_start;
+	uint32_t timestamp_end;
+	struct calendar_date *temp;
+
+	timestamp_start = calendar_date_to_timestamp(date_start);
+	timestamp_end = calendar_date_to_timestamp(date_end);
+
+	// Switch dates if date_end is before date_start
+	if (timestamp_end < timestamp_start) {
+		temp = date_end;
+		date_end = date_start;
+		date_start = temp;
+	}
+
+	// Calculate number of years
+	date_out->year = date_end->year - date_start->year;
+
+	// Check if months wrap around new year
+	if (date_end->month - date_start->month < 0 ) {
+		date_end->month += 12;
+		if (date_out->year != 0) {
+			date_out->year--;
+		}
+	}
+	// Calculate number of months
+	date_out->month = date_end->month - date_start->month;
+
+	// Check if dates wrap around month
+	if(date_end->date - date_start->date < 0) {
+		// Add number of days in last month to get number of days correct
+		date_end->date +=
+			month[calendar_leapyear(date_end->year)][date_end->month-1];
+		if (date_out->month != 0) {
+			date_out->month--;
+		}
+	}
+	// Calculate number of days
+	date_out->date = date_end->date - date_start->date;
+
+	// Check if hours wrap around midnight
+	if (date_end->hour - date_start->hour < 0) {
+		date_end->hour += 24;
+		if (date_out->date != 0) {
+			date_out->date--;
+		}
+	}
+	// Calculate number of hours
+	date_out->hour = date_end->hour - date_start->hour;
+
+	// Check if minutes wrap around hour
+	if (date_end->minute - date_start->minute < 0) {
+		date_end->minute += 60;
+		if (date_out->hour != 0) {
+			date_out->hour--;
+		}
+	}
+	// Calculate number of minutes
+	date_out->minute = date_end->minute - date_start->minute;
+
+	// Check if seconds wrap around minute
+	if (date_end->second - date_start->second < 0) {
+		date_end->second += 60;
+		if (date_out->minute != 0) {
+			date_out->minute--;
+		}
+	}
+	// Calculate number of seconds
+	date_out->second = date_end->second - date_start->second;
+
+}
+
+/**
+ * \brief Increments a date with one second.
+ *
+ * This function will add one second to specified date. If second is 59,
+ * it will increment minute.
+ *
+ * \param date The date to add a second to
+ *
+ */
+void calendar_add_second_to_date(struct calendar_date *date)
+{
+	// Check if input date is valid
+	Assert(calendar_is_date_valid(date));
+
+	if (++date->second == 60) {
+		date->second = 0;
+		calendar_add_minute_to_date(date);
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.h b/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.h
new file mode 100644
index 0000000000..d825434fd9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.h
@@ -0,0 +1,205 @@
+/**
+ * \file
+ *
+ * \brief Calendar.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _CALENDAR_H_INCLUDED_
+#define _CALENDAR_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+/**
+*
+* \defgroup calendar_group Calendar service
+ *
+ * See \ref calendar_quickstart.
+ *
+ * This is the common API for a calendar service.
+ * It provides functionality to convert UNIX timestamps to dates and back. It
+ * also provides functionality for calculating the difference between dates and
+ * converting timestamps to dates with different time zones and back.
+ * \note
+ * This module is a pure software module, and does not interface
+ * hardware calendar peripherals (e.g. the AST on UC3L)
+ *
+ * @{
+ */
+
+//! Calendar structure to hold a date
+struct calendar_date {
+	uint8_t second;        //!< 0-59
+	uint8_t minute;        //!< 0-59
+	uint8_t hour;          //!< 0-23
+	uint8_t date;          //!< 0-30 \note First day of month is 0, not 1.
+	uint8_t month;         //!< 0 January - 11 December
+	uint16_t year;         //!< 1970-2105
+	uint8_t dayofweek;     //!< 0 Sunday  - 6 Saturday
+};
+
+bool calendar_is_date_valid(struct calendar_date *date);
+
+void calendar_timestamp_to_date(uint32_t timestamp, struct calendar_date
+		*date_out);
+
+void calendar_timestamp_to_date_tz(uint32_t timestamp, int8_t hour,
+		uint8_t min, struct calendar_date *date_out);
+
+uint32_t calendar_date_to_timestamp(struct calendar_date *date);
+
+uint32_t calendar_date_to_timestamp_tz(struct calendar_date *date, int8_t hour,
+		uint8_t min);
+
+void calendar_time_between_dates(struct calendar_date *date_end,
+		struct calendar_date *date_start, struct calendar_date *date_out);
+
+void calendar_add_second_to_date(struct calendar_date *date);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page calendar_quickstart Quick start guide for Calendar service
+ *
+ * This is the quick start guide for the \ref calendar_group, with
+ * step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section calendar_basic_use_case Basic use case
+ * \section calendar_use_cases Calendar use cases
+ * - \ref calendar_basic_use_case
+ * - \subpage calendar_use_case_1
+ *
+ * \section calendar_basic_use_case Basic use case - Calculate timestamp
+ *
+ * The use case will let the user calculate the corresponding timestamp to a
+ * date
+ *
+ * \section calendar_basic_use_case_setup Setup steps
+ *
+ * \subsection calendar_basic_use_case_setup_prereq Prerequisites
+ * For the code of this use case to work, the following must
+ * be added to the project:
+ * -# A date struct with a date:
+ * \code
+	struct calendar_date date = {
+	    .second = 12,
+	    .minute = 1,
+	    .hour = 22,
+	    .date = 8,
+	    .month = 2,
+	    .year = 1985
+	};
+\endcode
+ *
+ * \subsection calendar_basic_use_case_setup_code Example code
+ * No setup code is needed, the service is ready for use as-is.
+ *
+ * \section calendar_basic_use_case_usage Usage steps
+ *
+ * \subsection calendar_basic_use_case_usage_code Example code
+ * Add to, e.g. the main loop in the application C-file:
+ * \code uint32_t timestamp = calendar_date_to_timestamp(&date); \endcode
+ *
+ * \subsection calendar_basic_use_case_usage_flow Workflow
+ * -# Convert date to timestamp:
+ *   - \code uint32_t timestamp = calendar_date_to_timestamp(&date); \endcode
+ */
+
+/**
+ * \page calendar_use_case_1 Calculate time between dates
+ *
+ * The use case will let the user calculate the time between two dates, by
+ * first calculating the dates from two timestamps.
+ *
+ * \section calendar_use_case_1_setup Setup steps
+ *
+ * \subsection calendar_use_case_1_setup_prereq Prerequisites
+ * For the code of this use case to work, the following must
+ * be added to the project:
+ * -# Three date structs:
+ * \code
+	struct calendar_date result;
+	struct calendar_date end_date;
+	struct calendar_date start_date;
+\endcode
+ * -# Two timestamps:
+ * \code
+	uint32_t end_timestamp = 1309174659;
+	uint32_t start_timestamp = 123456789;
+\endcode
+ *
+ * \subsection calendar_use_case_1_setup_code Example code
+ * No setup code is needed, the service is ready for use as-is.
+ *
+ * \section calendar_use_case_1_usage Usage steps
+ *
+ * \subsection calendar_use_case_1_usage_code Example code
+ * Add to, e.g. the main loop in the application C-file:
+ * \code
+	calendar_timestamp_to_date(end_timestamp, &end_date);
+	calendar_timestamp_to_date(start_timestamp, &start_date);
+	calendar_time_between_dates(&end_date, &start_date, &result);
+\endcode
+ *
+ * \subsection calendar_use_case_1_usage_flow Workflow
+ * -# Convert the end timestamp to date:
+ *   - \code calendar_timestamp_to_date(end_timestamp, &end_date); \endcode
+ * -# Convert the start timestamp to date:
+ *   - \code calendar_timestamp_to_date(start_timestamp, &start_date); \endcode
+ * -# Calculate the time between the two dates:
+ *   - \code calendar_time_between_dates(&end_date, &start_date, &result);
+\endcode
+ */
+
+#endif /* _CALENDAR_H_INCLUDED_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/dfll.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/dfll.h
new file mode 100644
index 0000000000..ca5bb97ade
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/dfll.h
@@ -0,0 +1,402 @@
+/**
+ * \file
+ *
+ * \brief DFLL management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CLK_DFLL_H_INCLUDED
+#define CLK_DFLL_H_INCLUDED
+
+#include <parts.h>
+#include "conf_clock.h"
+
+#if UC3L
+# include "uc3l/dfll.h"
+#elif SAM4L
+# include "sam4l/dfll.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \ingroup clk_group
+ * \defgroup dfll_group DFLL Management
+ *
+ * A Digital Frequency Locked Loop can be used to generate a highly
+ * accurate frequency from a slower-running reference clock, in much the
+ * same way as a PLL. DFLLs typically have shorter startup times and
+ * less jitter. They can also be used in open-loop mode to generate a
+ * less accurate frequency without the use of a reference clock.
+ *
+ * There may be significant variations between platforms in the support
+ * for certain features.
+ *
+ * \par Example: Setting up DFLL0 with default parameters and dithering enabled
+ *
+ * The following example shows how to configure and enable DFLL0 in
+ * closed-loop mode using the default parameters specified through
+ * configuration symbols.
+ * \code
+	dfll_enable_config_defaults(0); \endcode
+ *
+ * To configure and enable DFLL0 in closed-loop mode using the default
+ * parameters and to enable specific feature like dithering for better accuracy,
+ * you can use this initialization process.
+ * \code
+	struct dfll_config dfllcfg;
+
+	dfll_enable_source(CONFIG_DFLL0_SOURCE);
+	dfll_config_defaults(&dfllcfg, 0);
+	dfll_config_enable_dithering(&dfllcfg);
+	dfll_enable(&dfllcfg, 0);
+	dfll_wait_for_accurate_lock(0); \endcode
+ *
+ * When the last function call returns, DFLL0 is running at a frequency
+ * which matches the default configuration as accurately as possible.
+ * Any additional alterations to the default configuration can be added
+ * at the same place as the call to dfll_config_enable_dithering(), but
+ * note that the DFLL will never achieve "accurate" lock if dithering is
+ * disabled.
+ *
+ * @{
+ */
+
+//! \name Chip-specific DFLL characteristics
+//@{
+/**
+ * \def NR_DFLLS
+ * \brief Number of on-chip DFLLs.
+ */
+/**
+ * \def DFLL_MIN_HZ
+ * \brief Minimum frequency that the DFLL can generate.
+ */
+/**
+ * \def DFLL_MAX_HZ
+ * \brief Maximum frequency that the DFLL can generate.
+ */
+//@}
+
+/**
+ * \typedef dfll_refclk_t
+ * \brief Type used for identifying a reference clock source for the DFLL.
+ */
+
+//! \name DFLL Configuration
+//@{
+
+/**
+ * \struct dfll_config
+ * \brief Hardware-specific representation of DFLL configuration.
+ *
+ * This structure contains one or more device-specific values
+ * representing the current DFLL configuration. The contents of this
+ * structure is typically different from platform to platform, and the
+ * user should not access any fields except through the DFLL
+ * configuration API.
+ */
+
+/**
+ * \fn void dfll_config_init_open_loop_mode(struct dfll_config *cfg)
+ * \brief Configure the DFLL configuration \a cfg for open-loop mode.
+ *
+ * \param cfg The DFLL configuration to be initialized.
+ */
+/**
+ * \fn void dfll_config_init_closed_loop_mode(struct dfll_config *cfg,
+ *              dfll_refclk_t refclk, uint16_t div, uint16_t mul)
+ * \brief Configure the DFLL configuration \a cfg for closed-loop mode.
+ *
+ * \param cfg The DFLL configuration to be initialized.
+ * \param refclk The reference clock source.
+ * \param div Reference clock divider.
+ * \param mul Multiplier (integer part only).
+ */
+/**
+ * \def dfll_config_defaults(cfg, dfll_id)
+ * \brief Initialize DFLL configuration using default parameters.
+ *
+ * After this function returns, \a cfg will contain a configuration
+ * which will make the DFLL run at (CONFIG_DFLLx_MUL / CONFIG_DFLLx_DIV)
+ * times the frequency of CONFIG_DFLLx_SOURCE. The default configuration
+ * will always use closed-loop mode with no fractional multiplier.
+ *
+ * \param cfg The DFLL configuration to be initialized.
+ * \param dfll_id Use defaults for this DFLL.
+ */
+/**
+ * \def dfll_get_default_rate(dfll_id)
+ * \brief Return the default rate in Hz of \a dfll_id.
+ */
+
+/**
+ * \fn void dfll_config_set_fractional_multiplier(struct dfll_config *cfg,
+ *              uint16_t mul_i, uint16_t mul_f)
+ * \brief Set a fractional multiplier.
+ *
+ * This function has no effect in open-loop mode, and is only available
+ * on devices which support fractional multipliers.
+ *
+ * The fractional part of the multiplier is assumed to be 16 bits. The
+ * low-level driver will make sure to shift this value to match the
+ * hardware if necessary.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ * \param mul_i Integer part of multiplier.
+ * \param mul_f Fractional part of multiplier.
+ */
+/**
+ * \fn void dfll_config_enable_dithering(struct dfll_config *cfg)
+ * \brief Enable dithering for more accurate frequency generation.
+ *
+ * The fine LSB input to the VCO is dithered to achieve fractional
+ * approximation to the correct multiplication ratio.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ */
+/**
+ * \fn void dfll_config_disable_dithering(struct dfll_config *cfg)
+ * \brief Disable dithering.
+ *
+ * \see dfll_config_enable_dithering()
+ *
+ * \param cfg The DFLL configuration to be modified.
+ */
+/**
+ * \fn void dfll_config_set_initial_tuning(struct dfll_config *cfg,
+ *              uint16_t coarse, uint16_t fine)
+ * \brief Set initial VCO tuning.
+ *
+ * In open loop mode, this will determine the frequency of the output.
+ *
+ * In closed loop mode, this will provide an initial estimate of the VCO
+ * tuning. While the DFLL will automatically adjust these values to
+ * match the desired output frequency, careful selection of initial
+ * values might reduce the time to achieve coarse and fine lock.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ * \param coarse Coarse tuning of the frequency generator.
+ * \param fine Fine tuning of the frequency generator.
+ */
+/**
+ * \fn void dfll_config_set_max_step(struct dfll_config *cfg,
+ *              uint16_t coarse, uint16_t fine)
+ * \brief Set the maximum VCO tuning step size.
+ *
+ * This function has no effect in open-loop mode.
+ *
+ * By default, both of these values are set to 50% of their respective
+ * maximums.  It is not recommended to set the values any higher than
+ * this, but setting them lower might reduce the frequency overshoot at
+ * the expense of longer time to achieve coarse and/or fine lock.
+ *
+ * \param cfg The DFLL configuration to be modified
+ * \param coarse The maximum step size of the coarse VCO tuning.
+ * \param fine The maximum step size of the fine VCO tuning.
+ */
+/**
+ * \fn void dfll_config_enable_ssg(struct dfll_config *cfg,
+ *              uint16_t amplitude, uint16_t step_size)
+ * \brief Enable Spread Spectrum Generator.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ * \param amplitude The amplitude of the spread spectrum.
+ * \param step_size The step size of the spread spectrum.
+ */
+/**
+ * \fn void dfll_config_disable_ssg(struct dfll_config *cfg)
+ * \brief Disable Spread Spectrum Generator.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ */
+//@}
+
+//! \name Interaction with the DFLL hardware
+//@{
+/**
+ * \fn void dfll_enable_open_loop(const struct dfll_config *cfg,
+ *              unsigned int dfll_id)
+ * \brief Activate the configuration \a cfg and enable DFLL \a dfll_id
+ * in open-loop mode.
+ *
+ * \pre The configuration in \a cfg must represent an open-loop
+ * configuration.
+ *
+ * \param cfg The configuration to be activated.
+ * \param dfll_id The ID of the DFLL to be enabled.
+ */
+/**
+ * \fn void dfll_enable_closed_loop(const struct dfll_config *cfg,
+ *              unsigned int dfll_id)
+ * \brief Activate the configuration \a cfg and enable DFLL \a dfll_id
+ * in closed-loop mode.
+ *
+ * \pre The configuration in \a cfg must represent a closed-loop
+ * configuration.
+ *
+ * \param cfg The configuration to be activated.
+ * \param dfll_id The ID of the DFLL to be enabled.
+ */
+/**
+ * \fn void dfll_disable_open_loop(unsigned int dfll_id)
+ * \brief Disable the DFLL identified by \a dfll_id.
+ *
+ * \pre The DFLL must have been enabled in open loop mode.
+ *
+ * \param dfll_id The ID of the DFLL to be disabled.
+ */
+/**
+ * \fn void dfll_disable_closed_loop(unsigned int dfll_id)
+ * \brief Disable the DFLL identified by \a dfll_id.
+ *
+ * \pre The DFLL must have been enabled in closed loop mode.
+ *
+ * \param dfll_id The ID of the DFLL to be disabled.
+ */
+/**
+ * \fn bool dfll_is_coarse_locked(unsigned int dfll_id)
+ * \brief Determine whether or not a DFLL has achieved coarse lock.
+ *
+ * \param dfll_id The ID of the DFLL to check.
+ *
+ * \retval true The DFLL has determined the final value of the coarse
+ * VCO tuning value.
+ * \retval false The DFLL has not yet determined the coarse VCO tuning
+ * value, or has not been enabled.
+ */
+/**
+ * \fn bool dfll_is_fine_locked(unsigned int dfll_id)
+ * \brief Determine whether or not a DFLL has achieved fine lock.
+ *
+ * \param dfll_id The ID of the DFLL to check.
+ *
+ * \retval true The DFLL has determined the final value of the fine VCO
+ * tuning value.
+ * \retval false The DFLL has not yet determined the fine VCO tuning
+ * value, or has not been enabled.
+ */
+/**
+ * \fn bool dfll_is_accurate_locked(unsigned int dfll_id)
+ * \brief Determine whether or not a DFLL has achieved accurate lock.
+ *
+ * \param dfll_id The ID of the DFLL to check.
+ *
+ * \retval true The DFLL has determined the final dithering duty cycle.
+ * \retval false The DFLL has not yet determined the dithering duty
+ * cycle, or has not been enabled with dithering enabled.
+ */
+/**
+ * \fn void dfll_enable_source(enum dfll_refclk_t src)
+ * \brief Enable the source of the dfll.
+ * The source is enabled, if the source is not already running.
+ *
+ * \param dfll_source src The ID of the DFLL source to enable.
+ */
+/**
+ * \fn void dfll_enable_config_defaults(unsigned int dfll_id)
+ * \brief Enable the dfll with the default configuration.
+ * DFLL is enabled, if the DFLL is not already locked.
+ *
+ * \param dfll_id The ID of the DFLL to enable.
+ */
+
+/**
+ * \brief Wait for the DFLL identified by \a dfll_id to achieve coarse
+ * lock.
+ *
+ * \param dfll_id The ID of the DFLL to wait for.
+ *
+ * \retval STATUS_OK The DFLL has achieved coarse lock.
+ * \retval ERR_TIMEOUT Timed out waiting for lock.
+ */
+static inline int dfll_wait_for_coarse_lock(unsigned int dfll_id)
+{
+	/* TODO: Add timeout mechanism */
+	while (!dfll_is_coarse_locked(dfll_id)) {
+		/* Do nothing */
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Wait for the DFLL identified by \a dfll_id to achieve fine
+ * lock.
+ *
+ * \param dfll_id The ID of the DFLL to wait for.
+ *
+ * \retval STATUS_OK The DFLL has achieved fine lock.
+ * \retval ERR_TIMEOUT Timed out waiting for lock.
+ */
+static inline int dfll_wait_for_fine_lock(unsigned int dfll_id)
+{
+	/* TODO: Add timeout mechanism */
+	while (!dfll_is_fine_locked(dfll_id)) {
+		/* Do nothing */
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Wait for the DFLL identified by \a dfll_id to achieve accurate
+ * lock.
+ *
+ * \param dfll_id The ID of the DFLL to wait for.
+ *
+ * \retval STATUS_OK The DFLL has achieved accurate lock.
+ * \retval ERR_TIMEOUT Timed out waiting for lock.
+ */
+static inline int dfll_wait_for_accurate_lock(unsigned int dfll_id)
+{
+	/* TODO: Add timeout mechanism */
+	while (!dfll_is_accurate_locked(dfll_id)) {
+		/* Do nothing */
+	}
+
+	return 0;
+}
+
+//@}
+//! @}
+
+#endif /* CLK_DFLL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/genclk.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/genclk.h
new file mode 100644
index 0000000000..503a50a2f9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/genclk.h
@@ -0,0 +1,199 @@
+/**
+ * \file
+ *
+ * \brief Generic clock management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CLK_GENCLK_H_INCLUDED
+#define CLK_GENCLK_H_INCLUDED
+
+#include "parts.h"
+
+#if SAM3S
+# include "sam3s/genclk.h"
+#elif SAM3U
+# include "sam3u/genclk.h"
+#elif SAM3N
+# include "sam3n/genclk.h"
+#elif SAM3XA
+# include "sam3x/genclk.h"
+#elif SAM4S
+# include "sam4s/genclk.h"
+#elif SAM4L
+# include "sam4l/genclk.h"
+#elif SAM4E
+# include "sam4e/genclk.h"
+#elif SAM4N
+# include "sam4n/genclk.h"
+#elif SAM4C
+# include "sam4c/genclk.h"
+#elif SAM4CM
+# include "sam4cm/genclk.h"
+#elif SAM4CP
+# include "sam4cp/genclk.h"
+#elif SAMG
+# include "samg/genclk.h"
+#elif SAMV71
+# include "samv71/genclk.h"
+#elif SAMV70
+# include "samv70/genclk.h"
+#elif SAME70
+# include "same70/genclk.h"
+#elif SAMS70
+# include "sams70/genclk.h"
+#elif (UC3A0 || UC3A1)
+# include "uc3a0_a1/genclk.h"
+#elif UC3A3
+# include "uc3a3_a4/genclk.h"
+#elif UC3B
+# include "uc3b0_b1/genclk.h"
+#elif UC3C
+# include "uc3c/genclk.h"
+#elif UC3D
+# include "uc3d/genclk.h"
+#elif UC3L
+# include "uc3l/genclk.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \ingroup clk_group
+ * \defgroup genclk_group Generic Clock Management
+ *
+ * Generic clocks are configurable clocks which run outside the system
+ * clock domain. They are often connected to peripherals which have an
+ * asynchronous component running independently of the bus clock, e.g.
+ * USB controllers, low-power timers and RTCs, etc.
+ *
+ * Note that not all platforms have support for generic clocks; on such
+ * platforms, this API will not be available.
+ *
+ * @{
+ */
+
+/**
+ * \def GENCLK_DIV_MAX
+ * \brief Maximum divider supported by the generic clock implementation
+ */
+/**
+ * \enum genclk_source
+ * \brief Generic clock source ID
+ *
+ * Each generic clock may be generated from a different clock source.
+ * These are the available alternatives provided by the chip.
+ */
+
+//! \name Generic clock configuration
+//@{
+/**
+ * \struct genclk_config
+ * \brief Hardware representation of a set of generic clock parameters
+ */
+/**
+ * \fn void genclk_config_defaults(struct genclk_config *cfg,
+ *              unsigned int id)
+ * \brief Initialize \a cfg to the default configuration for the clock
+ * identified by \a id.
+ */
+/**
+ * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)
+ * \brief Read the currently active configuration of the clock
+ * identified by \a id into \a cfg.
+ */
+/**
+ * \fn void genclk_config_write(const struct genclk_config *cfg,
+ *              unsigned int id)
+ * \brief Activate the configuration \a cfg on the clock identified by
+ * \a id.
+ */
+/**
+ * \fn void genclk_config_set_source(struct genclk_config *cfg,
+ *              enum genclk_source src)
+ * \brief Select a new source clock \a src in configuration \a cfg.
+ */
+/**
+ * \fn void genclk_config_set_divider(struct genclk_config *cfg,
+ *              unsigned int divider)
+ * \brief Set a new \a divider in configuration \a cfg.
+ */
+/**
+ * \fn void genclk_enable_source(enum genclk_source src)
+ * \brief Enable the source clock \a src used by a generic clock.
+ */
+ //@}
+
+//! \name Enabling and disabling Generic Clocks
+//@{
+/**
+ * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)
+ * \brief Activate the configuration \a cfg on the clock identified by
+ * \a id and enable it.
+ */
+/**
+ * \fn void genclk_disable(unsigned int id)
+ * \brief Disable the generic clock identified by \a id.
+ */
+//@}
+
+/**
+ * \brief Enable the configuration defined by \a src and \a divider
+ * for the generic clock identified by \a id.
+ *
+ * \param id      The ID of the generic clock.
+ * \param src     The source clock of the generic clock.
+ * \param divider The divider used to generate the generic clock.
+ */
+static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)
+{
+	struct genclk_config gcfg;
+
+	genclk_config_defaults(&gcfg, id);
+	genclk_enable_source(src);
+	genclk_config_set_source(&gcfg, src);
+	genclk_config_set_divider(&gcfg, divider);
+	genclk_enable(&gcfg, id);
+}
+
+//! @}
+
+#endif /* CLK_GENCLK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/osc.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/osc.h
new file mode 100644
index 0000000000..e67f01f502
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/osc.h
@@ -0,0 +1,185 @@
+/**
+ * \file
+ *
+ * \brief Oscillator management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef OSC_H_INCLUDED
+#define OSC_H_INCLUDED
+
+#include "parts.h"
+#include "conf_clock.h"
+
+#if SAM3S
+# include "sam3s/osc.h"
+#elif SAM3XA
+# include "sam3x/osc.h"
+#elif SAM3U
+# include "sam3u/osc.h"
+#elif SAM3N
+# include "sam3n/osc.h"
+#elif SAM4S
+# include "sam4s/osc.h"
+#elif SAM4E
+# include "sam4e/osc.h"
+#elif SAM4C
+# include "sam4c/osc.h"
+#elif SAM4CM
+# include "sam4cm/osc.h"
+#elif SAM4CP
+# include "sam4cp/osc.h"
+#elif SAM4L
+# include "sam4l/osc.h"
+#elif SAM4N
+# include "sam4n/osc.h"
+#elif SAMG
+# include "samg/osc.h"
+#elif SAMV71
+# include "samv71/osc.h"
+#elif SAMV70
+# include "samv70/osc.h"
+#elif SAME70
+# include "same70/osc.h"
+#elif SAMS70
+# include "sams70/osc.h"
+#elif (UC3A0 || UC3A1)
+# include "uc3a0_a1/osc.h"
+#elif UC3A3
+# include "uc3a3_a4/osc.h"
+#elif UC3B
+# include "uc3b0_b1/osc.h"
+#elif UC3C
+# include "uc3c/osc.h"
+#elif UC3D
+# include "uc3d/osc.h"
+#elif UC3L
+# include "uc3l/osc.h"
+#elif XMEGA
+# include "xmega/osc.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \ingroup clk_group
+ * \defgroup osc_group Oscillator Management
+ *
+ * This group contains functions and definitions related to configuring
+ * and enabling/disabling on-chip oscillators. Internal RC-oscillators,
+ * external crystal oscillators and external clock generators are
+ * supported by this module. What all of these have in common is that
+ * they swing at a fixed, nominal frequency which is normally not
+ * adjustable.
+ *
+ * \par Example: Enabling an oscillator
+ *
+ * The following example demonstrates how to enable the external
+ * oscillator on XMEGA A and wait for it to be ready to use. The
+ * oscillator identifiers are platform-specific, so while the same
+ * procedure is used on all platforms, the parameter to osc_enable()
+ * will be different from device to device.
+ * \code
+	osc_enable(OSC_ID_XOSC);
+	osc_wait_ready(OSC_ID_XOSC); \endcode
+ *
+ * \section osc_group_board Board-specific Definitions
+ * If external oscillators are used, the board code must provide the
+ * following definitions for each of those:
+ *   - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.
+ *   - \b BOARD_<osc name>_STARTUP_US: The startup time of the
+ *     oscillator in microseconds.
+ *   - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.
+ *     whether it's a crystal or external clock, and sometimes what kind
+ *     of crystal it is. The meaning of this value is platform-specific.
+ *
+ * @{
+ */
+
+//! \name Oscillator Management
+//@{
+/**
+ * \fn void osc_enable(uint8_t id)
+ * \brief Enable oscillator \a id
+ *
+ * The startup time and mode value is automatically determined based on
+ * definitions in the board code.
+ */
+/**
+ * \fn void osc_disable(uint8_t id)
+ * \brief Disable oscillator \a id
+ */
+/**
+ * \fn osc_is_ready(uint8_t id)
+ * \brief Determine whether oscillator \a id is ready.
+ * \retval true Oscillator \a id is running and ready to use as a clock
+ * source.
+ * \retval false Oscillator \a id is not running.
+ */
+/**
+ * \fn uint32_t osc_get_rate(uint8_t id)
+ * \brief Return the frequency of oscillator \a id in Hz
+ */
+
+#ifndef __ASSEMBLY__
+
+/**
+ * \brief Wait until the oscillator identified by \a id is ready
+ *
+ * This function will busy-wait for the oscillator identified by \a id
+ * to become stable and ready to use as a clock source.
+ *
+ * \param id A number identifying the oscillator to wait for.
+ */
+static inline void osc_wait_ready(uint8_t id)
+{
+	while (!osc_is_ready(id)) {
+		/* Do nothing */
+	}
+}
+
+#endif /* __ASSEMBLY__ */
+
+//@}
+
+//! @}
+
+#endif /* OSC_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/pll.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/pll.h
new file mode 100644
index 0000000000..23e930c00a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/pll.h
@@ -0,0 +1,341 @@
+/**
+ * \file
+ *
+ * \brief PLL management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CLK_PLL_H_INCLUDED
+#define CLK_PLL_H_INCLUDED
+
+#include "parts.h"
+#include "conf_clock.h"
+
+#if SAM3S
+# include "sam3s/pll.h"
+#elif SAM3XA
+# include "sam3x/pll.h"
+#elif SAM3U
+# include "sam3u/pll.h"
+#elif SAM3N
+# include "sam3n/pll.h"
+#elif SAM4S
+# include "sam4s/pll.h"
+#elif SAM4E
+# include "sam4e/pll.h"
+#elif SAM4C
+# include "sam4c/pll.h"
+#elif SAM4CM
+# include "sam4cm/pll.h"
+#elif SAM4CP
+# include "sam4cp/pll.h"
+#elif SAM4L
+# include "sam4l/pll.h"
+#elif SAM4N
+# include "sam4n/pll.h"
+#elif SAMG
+# include "samg/pll.h"
+#elif SAMV71
+# include "samv71/pll.h"
+#elif SAMV70
+# include "samv70/pll.h"
+#elif SAME70
+# include "same70/pll.h"
+#elif SAMS70
+# include "sams70/pll.h"
+#elif (UC3A0 || UC3A1)
+# include "uc3a0_a1/pll.h"
+#elif UC3A3
+# include "uc3a3_a4/pll.h"
+#elif UC3B
+# include "uc3b0_b1/pll.h"
+#elif UC3C
+# include "uc3c/pll.h"
+#elif UC3D
+# include "uc3d/pll.h"
+#elif (UC3L0128 || UC3L0256 || UC3L3_L4)
+# include "uc3l/pll.h"
+#elif XMEGA
+# include "xmega/pll.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \ingroup clk_group
+ * \defgroup pll_group PLL Management
+ *
+ * This group contains functions and definitions related to configuring
+ * and enabling/disabling on-chip PLLs. A PLL will take an input signal
+ * (the \em source), optionally divide the frequency by a configurable
+ * \em divider, and then multiply the frequency by a configurable \em
+ * multiplier.
+ *
+ * Some devices don't support input dividers; specifying any other
+ * divisor than 1 on these devices will result in an assertion failure.
+ * Other devices may have various restrictions to the frequency range of
+ * the input and output signals.
+ *
+ * \par Example: Setting up PLL0 with default parameters
+ *
+ * The following example shows how to configure and enable PLL0 using
+ * the default parameters specified using the configuration symbols
+ * listed above.
+ * \code
+	pll_enable_config_defaults(0); \endcode
+ *
+ * To configure, enable PLL0 using the default parameters and to disable
+ * a specific feature like Wide Bandwidth Mode (a UC3A3-specific
+ * PLL option.), you can use this initialization process.
+ * \code
+	struct pll_config pllcfg;
+	if (pll_is_locked(pll_id)) {
+		return; // Pll already running
+	}
+	pll_enable_source(CONFIG_PLL0_SOURCE);
+	pll_config_defaults(&pllcfg, 0);
+	pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
+	pll_enable(&pllcfg, 0);
+	pll_wait_for_lock(0); \endcode
+ *
+ * When the last function call returns, PLL0 is ready to be used as the
+ * main system clock source.
+ *
+ * \section pll_group_config Configuration Symbols
+ *
+ * Each PLL has a set of default parameters determined by the following
+ * configuration symbols in the application's configuration file:
+ *   - \b CONFIG_PLLn_SOURCE: The default clock source connected to the
+ *     input of PLL \a n. Must be one of the values defined by the
+ *     #pll_source enum.
+ *   - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL
+ *     \a n.
+ *   - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.
+ *
+ * These configuration symbols determine the result of calling
+ * pll_config_defaults() and pll_get_default_rate().
+ *
+ * @{
+ */
+
+//! \name Chip-specific PLL characteristics
+//@{
+/**
+ * \def PLL_MAX_STARTUP_CYCLES
+ * \brief Maximum PLL startup time in number of slow clock cycles
+ */
+/**
+ * \def NR_PLLS
+ * \brief Number of on-chip PLLs
+ */
+
+/**
+ * \def PLL_MIN_HZ
+ * \brief Minimum frequency that the PLL can generate
+ */
+/**
+ * \def PLL_MAX_HZ
+ * \brief Maximum frequency that the PLL can generate
+ */
+/**
+ * \def PLL_NR_OPTIONS
+ * \brief Number of PLL option bits
+ */
+//@}
+
+/**
+ * \enum pll_source
+ * \brief PLL clock source
+ */
+
+//! \name PLL configuration
+//@{
+
+/**
+ * \struct pll_config
+ * \brief Hardware-specific representation of PLL configuration.
+ *
+ * This structure contains one or more device-specific values
+ * representing the current PLL configuration. The contents of this
+ * structure is typically different from platform to platform, and the
+ * user should not access any fields except through the PLL
+ * configuration API.
+ */
+
+/**
+ * \fn void pll_config_init(struct pll_config *cfg,
+ *              enum pll_source src, unsigned int div, unsigned int mul)
+ * \brief Initialize PLL configuration from standard parameters.
+ *
+ * \note This function may be defined inline because it is assumed to be
+ * called very few times, and usually with constant parameters. Inlining
+ * it will in such cases reduce the code size significantly.
+ *
+ * \param cfg The PLL configuration to be initialized.
+ * \param src The oscillator to be used as input to the PLL.
+ * \param div PLL input divider.
+ * \param mul PLL loop divider (i.e. multiplier).
+ *
+ * \return A configuration which will make the PLL run at
+ * (\a mul / \a div) times the frequency of \a src
+ */
+/**
+ * \def pll_config_defaults(cfg, pll_id)
+ * \brief Initialize PLL configuration using default parameters.
+ *
+ * After this function returns, \a cfg will contain a configuration
+ * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)
+ * times the frequency of CONFIG_PLLx_SOURCE.
+ *
+ * \param cfg The PLL configuration to be initialized.
+ * \param pll_id Use defaults for this PLL.
+ */
+/**
+ * \def pll_get_default_rate(pll_id)
+ * \brief Get the default rate in Hz of \a pll_id
+ */
+/**
+ * \fn void pll_config_set_option(struct pll_config *cfg,
+ *              unsigned int option)
+ * \brief Set the PLL option bit \a option in the configuration \a cfg.
+ *
+ * \param cfg The PLL configuration to be changed.
+ * \param option The PLL option bit to be set.
+ */
+/**
+ * \fn void pll_config_clear_option(struct pll_config *cfg,
+ *              unsigned int option)
+ * \brief Clear the PLL option bit \a option in the configuration \a cfg.
+ *
+ * \param cfg The PLL configuration to be changed.
+ * \param option The PLL option bit to be cleared.
+ */
+/**
+ * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)
+ * \brief Read the currently active configuration of \a pll_id.
+ *
+ * \param cfg The configuration object into which to store the currently
+ * active configuration.
+ * \param pll_id The ID of the PLL to be accessed.
+ */
+/**
+ * \fn void pll_config_write(const struct pll_config *cfg,
+ *              unsigned int pll_id)
+ * \brief Activate the configuration \a cfg on \a pll_id
+ *
+ * \param cfg The configuration object representing the PLL
+ * configuration to be activated.
+ * \param pll_id The ID of the PLL to be updated.
+ */
+
+//@}
+
+//! \name Interaction with the PLL hardware
+//@{
+/**
+ * \fn void pll_enable(const struct pll_config *cfg,
+ *              unsigned int pll_id)
+ * \brief Activate the configuration \a cfg and enable PLL \a pll_id.
+ *
+ * \param cfg The PLL configuration to be activated.
+ * \param pll_id The ID of the PLL to be enabled.
+ */
+/**
+ * \fn void pll_disable(unsigned int pll_id)
+ * \brief Disable the PLL identified by \a pll_id.
+ *
+ * After this function is called, the PLL identified by \a pll_id will
+ * be disabled. The PLL configuration stored in hardware may be affected
+ * by this, so if the caller needs to restore the same configuration
+ * later, it should either do a pll_config_read() before disabling the
+ * PLL, or remember the last configuration written to the PLL.
+ *
+ * \param pll_id The ID of the PLL to be disabled.
+ */
+/**
+ * \fn bool pll_is_locked(unsigned int pll_id)
+ * \brief Determine whether the PLL is locked or not.
+ *
+ * \param pll_id The ID of the PLL to check.
+ *
+ * \retval true The PLL is locked and ready to use as a clock source
+ * \retval false The PLL is not yet locked, or has not been enabled.
+ */
+/**
+ * \fn void pll_enable_source(enum pll_source src)
+ * \brief Enable the source of the pll.
+ * The source is enabled, if the source is not already running.
+ *
+ * \param src The ID of the PLL source to enable.
+ */
+/**
+ * \fn void pll_enable_config_defaults(unsigned int pll_id)
+ * \brief Enable the pll with the default configuration.
+ * PLL is enabled, if the PLL is not already locked.
+ *
+ * \param pll_id The ID of the PLL to enable.
+ */
+
+/**
+ * \brief Wait for PLL \a pll_id to become locked
+ *
+ * \todo Use a timeout to avoid waiting forever and hanging the system
+ *
+ * \param pll_id The ID of the PLL to wait for.
+ *
+ * \retval STATUS_OK The PLL is now locked.
+ * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
+ */
+static inline int pll_wait_for_lock(unsigned int pll_id)
+{
+	Assert(pll_id < NR_PLLS);
+
+	while (!pll_is_locked(pll_id)) {
+		/* Do nothing */
+	}
+
+	return 0;
+}
+
+//@}
+//! @}
+
+#endif /* CLK_PLL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/sysclk.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/sysclk.h
new file mode 100644
index 0000000000..86e4bf7a24
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/sysclk.h
@@ -0,0 +1,194 @@
+/**
+ * \file
+ *
+ * \brief System clock management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSCLK_H_INCLUDED
+#define SYSCLK_H_INCLUDED
+
+#include "parts.h"
+#include "conf_clock.h"
+
+#if SAM3S
+# include "sam3s/sysclk.h"
+#elif SAM3U
+# include "sam3u/sysclk.h"
+#elif SAM3N
+# include "sam3n/sysclk.h"
+#elif SAM3XA
+# include "sam3x/sysclk.h"
+#elif SAM4S
+# include "sam4s/sysclk.h"
+#elif SAM4E
+# include "sam4e/sysclk.h"
+#elif SAM4C
+# include "sam4c/sysclk.h"
+#elif SAM4CM
+# include "sam4cm/sysclk.h"
+#elif SAM4CP
+# include "sam4cp/sysclk.h"
+#elif SAM4L
+# include "sam4l/sysclk.h"
+#elif SAM4N
+# include "sam4n/sysclk.h"
+#elif SAMG
+# include "samg/sysclk.h"
+#elif SAMV71
+# include "samv71/sysclk.h"
+#elif SAMV70
+# include "samv70/sysclk.h"
+#elif SAME70
+# include "same70/sysclk.h"
+#elif SAMS70
+# include "sams70/sysclk.h"
+#elif (UC3A0 || UC3A1)
+# include "uc3a0_a1/sysclk.h"
+#elif UC3A3
+# include "uc3a3_a4/sysclk.h"
+#elif UC3B
+# include "uc3b0_b1/sysclk.h"
+#elif UC3C
+# include "uc3c/sysclk.h"
+#elif UC3D
+# include "uc3d/sysclk.h"
+#elif UC3L
+# include "uc3l/sysclk.h"
+#elif XMEGA
+# include "xmega/sysclk.h"
+#elif MEGA
+# include "mega/sysclk.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \defgroup clk_group Clock Management
+ */
+
+/**
+ * \ingroup clk_group
+ * \defgroup sysclk_group System Clock Management
+ *
+ * See \ref sysclk_quickstart.
+ *
+ * The <em>sysclk</em> API covers the <em>system clock</em> and all
+ * clocks derived from it. The system clock is a chip-internal clock on
+ * which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral
+ * clocks, are based. The system clock is typically generated from one
+ * of a variety of sources, which may include crystal and RC oscillators
+ * as well as PLLs.  The clocks derived from the system clock are
+ * sometimes also known as <em>synchronous clocks</em>, since they
+ * always run synchronously with respect to each other, as opposed to
+ * <em>generic clocks</em> which may run from different oscillators or
+ * PLLs.
+ *
+ * Most applications should simply call sysclk_init() to initialize
+ * everything related to the system clock and its source (oscillator,
+ * PLL or DFLL), and leave it at that. More advanced applications, and
+ * platform-specific drivers, may require additional services from the
+ * clock system, some of which may be platform-specific.
+ *
+ * \section sysclk_group_platform Platform Dependencies
+ *
+ * The sysclk API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms with the same
+ * parameters and functionality. These functions may be called freely by
+ * portable applications, drivers and services:
+ *   - sysclk_init()
+ *   - sysclk_set_source()
+ *   - sysclk_get_main_hz()
+ *   - sysclk_get_cpu_hz()
+ *   - sysclk_get_peripheral_bus_hz()
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behavior. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - sysclk_enable_peripheral_clock()
+ *   - sysclk_disable_peripheral_clock()
+ *   - sysclk_enable_module()
+ *   - sysclk_disable_module()
+ *   - sysclk_module_is_enabled()
+ *   - sysclk_set_prescalers()
+ *
+ * All other functions should be considered platform-specific.
+ * Enabling/disabling clocks to specific peripherals as well as
+ * determining the speed of these clocks should be done by calling
+ * functions provided by the driver for that peripheral.
+ *
+ * @{
+ */
+
+//! \name System Clock Initialization
+//@{
+/**
+ * \fn void sysclk_init(void)
+ * \brief Initialize the synchronous clock system.
+ *
+ * This function will initialize the system clock and its source. This
+ * includes:
+ *   - Mask all synchronous clocks except for any clocks which are
+ *     essential for normal operation (for example internal memory
+ *     clocks).
+ *   - Set up the system clock prescalers as specified by the
+ *     application's configuration file.
+ *   - Enable the clock source specified by the application's
+ *     configuration file (oscillator or PLL) and wait for it to become
+ *     stable.
+ *   - Set the main system clock source to the clock specified by the
+ *     application's configuration file.
+ *
+ * Since all non-essential peripheral clocks are initially disabled, it
+ * is the responsibility of the peripheral driver to re-enable any
+ * clocks that are needed for normal operation.
+ */
+//@}
+
+//! @}
+
+#endif /* SYSCLK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/cpu/reset_cause.h b/bsp/samd21/sam_d2x_asflib/common/services/cpu/reset_cause.h
new file mode 100644
index 0000000000..9d91bfb621
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/cpu/reset_cause.h
@@ -0,0 +1,399 @@
+/**
+ * \file
+ *
+ * \brief CPU reset cause functions
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef COMMON_DRIVERS_CPU_RESET_CAUSE_H
+#define COMMON_DRIVERS_CPU_RESET_CAUSE_H
+
+#include <parts.h>
+#include <stdbool.h>
+
+#if XMEGA
+# include "xmega_reset_cause.h"
+#elif UC3
+# include "avr32_reset_cause.h"
+#elif SAM4L
+# include "sam4l_reset_cause.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \defgroup reset_cause_group CPU reset cause
+ *
+ * See \ref reset_cause_quickstart
+ *
+ * This is a generic interface for getting and clearing the chip reset causes.
+ *
+ * \section dependencies Dependencies
+ *
+ * The reset cause interface does not depend on any other modules, as it only
+ * accesses a few registers in the device core.
+ *
+ * On the other hand, the software reset call might depend on \ref sysclk_group
+ * to enable the clock to the debug system, for devices doing software reset
+ * through the on-chip debug system. This applies only to the 32-bit AVR
+ * devices.
+ *
+ * \section Quick start guide
+ * See \ref reset_cause_quickstart
+ *
+ * @{
+ */
+
+/*
+ * Sanity check of reset causes, define undefined reset causes to 0. Hence they
+ * will always return false when queried.
+ */
+#ifndef CHIP_RESET_CAUSE_BOD_CPU
+/**
+ * \brief Brown-out detected on CPU power domain reset cause not available on
+ * this chip.
+ */
+# define CHIP_RESET_CAUSE_BOD_CPU       0
+#endif
+#ifndef CHIP_RESET_CAUSE_BOD_IO
+/**
+ * \brief Brown-out detected on I/O power domain reset cause not available on
+ * this chip.
+ */
+# define CHIP_RESET_CAUSE_BOD_IO        0
+#endif
+#ifndef CHIP_RESET_CAUSE_CPU_ERROR
+//! CPU error reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_CPU_ERROR     0
+#endif
+#ifndef CHIP_RESET_CAUSE_EXTRST
+//! External reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_EXTRST        0
+#endif
+#ifndef CHIP_RESET_CAUSE_JTAG
+//! JTAG reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_JTAG          0
+#endif
+#ifndef CHIP_RESET_CAUSE_OCD
+//! On-chip debug system reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_OCD           0
+#endif
+#ifndef CHIP_RESET_CAUSE_POR
+//! Power-on-reset reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_POR           0
+#endif
+#ifndef CHIP_RESET_CAUSE_POR_IO
+//! Power-on-reset on I/O power domain reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_POR_IO           0
+#endif
+#ifndef CHIP_RESET_CAUSE_SLEEP
+//! Wake from Shutdown sleep mode reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_SLEEP         0
+#endif
+#ifndef CHIP_RESET_CAUSE_SOFT
+//! Software reset reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_SOFT          0
+#endif
+#ifndef CHIP_RESET_CAUSE_SPIKE
+//! Spike detected reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_SPIKE         0
+#endif
+#ifndef CHIP_RESET_CAUSE_WDT
+//! Watchdog timeout reset cause not available on this chip.
+# define CHIP_RESET_CAUSE_WDT           0
+#endif
+
+/**
+ * \brief List of reset causes in bit-mask format
+ */
+enum reset_cause {
+	/** \brief Brown-out detected on CPU power domain reset cause */
+	RESET_CAUSE_BOD_CPU     = CHIP_RESET_CAUSE_BOD_CPU,
+	/** \brief Brown-out detected on I/O power domain reset cause */
+	RESET_CAUSE_BOD_IO      = CHIP_RESET_CAUSE_BOD_IO,
+	/** \brief CPU error reset cause */
+	RESET_CAUSE_CPU_ERROR   = CHIP_RESET_CAUSE_CPU_ERROR,
+	/** \brief External reset cause */
+	RESET_CAUSE_EXTRST      = CHIP_RESET_CAUSE_EXTRST,
+	/** \brief JTAG reset cause */
+	RESET_CAUSE_JTAG        = CHIP_RESET_CAUSE_JTAG,
+	/** \brief On-chip debug system reset cause */
+	RESET_CAUSE_OCD         = CHIP_RESET_CAUSE_OCD,
+	/** \brief Power-on-reset reset cause */
+	RESET_CAUSE_POR         = CHIP_RESET_CAUSE_POR,
+	/** \brief Power-on-reset reset cause */
+	RESET_CAUSE_POR_IO         = CHIP_RESET_CAUSE_POR_IO,
+	/** \brief Wake from Shutdown sleep mode reset cause */
+	RESET_CAUSE_SLEEP       = CHIP_RESET_CAUSE_SLEEP,
+	/** \brief Software reset reset cause */
+	RESET_CAUSE_SOFT        = CHIP_RESET_CAUSE_SOFT,
+	/** \brief Spike detected reset cause */
+	RESET_CAUSE_SPIKE       = CHIP_RESET_CAUSE_SPIKE,
+	/** \brief Watchdog timeout reset cause */
+	RESET_CAUSE_WDT         = CHIP_RESET_CAUSE_WDT,
+};
+
+//! \name Management
+//@{
+
+/**
+ * \fn void reset_do_soft_reset(void)
+ * \brief Perform a software reset of the device
+ *
+ * \note This function will never return.
+ * \note This function does not disable interrupts, this is up to the caller to
+ *       handle.
+ */
+/**
+ * \fn reset_cause_t reset_cause_get_causes(void)
+ * \brief Get all reset causes
+ *
+ * This function will return a value containing the currently triggered reset
+ * cause(s).
+ *
+ * \return Bit-mask with each active reset cause set to 1.
+ */
+/**
+ * \fn reset_cause_clear_causes(reset_cause_t causes)
+ * \brief Clear a bit-mask of reset causes
+ *
+ * This function will clear the provided reset causes in the reset cause
+ * register.
+ *
+ * \param causes bit-mask of reset causes to clear
+ */
+
+//@}
+
+//! \name Specific reset cause helper functions
+//@{
+
+/**
+ * \brief Check if chip reset was caused by a CPU power brown-out detection
+ *
+ * \return True if reset was caused by a CPU power brown-out detection
+ */
+static inline bool reset_cause_is_cpu_brown_out_detected(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_BOD_CPU);
+}
+
+/**
+ * \brief Check if chip reset was caused by an I/O power brown-out detection
+ *
+ * \return True if reset was caused by an I/O power brown-out detection
+ */
+static inline bool reset_cause_is_io_brown_out_detected(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_BOD_IO);
+}
+
+/**
+ * \brief Check if chip reset was caused by a brown-out detection on any
+ * power domain.
+ *
+ * \return True if reset was caused by a power brown-out detection
+ */
+static inline bool reset_cause_is_brown_out_detected(void)
+{
+	return (reset_cause_is_cpu_brown_out_detected() ||
+			reset_cause_is_io_brown_out_detected());
+}
+
+/**
+ * \brief Check if chip reset was caused by a CPU error, illegal access
+ *
+ * \return True if reset was caused by a CPU error, illegal access
+ */
+static inline bool reset_cause_is_cpu_error(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_CPU_ERROR);
+}
+
+/**
+ * \brief Check if chip reset was caused by an external reset
+ *
+ * \return True if reset was caused by an external reset
+ */
+static inline bool reset_cause_is_external_reset(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_EXTRST);
+}
+
+/**
+ * \brief Check if chip reset was caused by a JTAG reset
+ *
+ * \return True if reset was caused by a JTAG reset
+ */
+static inline bool reset_cause_is_jtag(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_JTAG);
+}
+
+/**
+ * \brief Check if chip reset was caused by the on-chip debug system
+ *
+ * \return True if reset was caused by the on-chip debug system
+ */
+static inline bool reset_cause_is_ocd(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_OCD);
+}
+
+/**
+ * \brief Check if chip reset was caused by a power-on-reset
+ *
+ * \return True if reset was caused by a power-on-reset
+ */
+static inline bool reset_cause_is_power_on_reset(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_POR);
+}
+
+/**
+ * \brief Check if chip reset was caused by an I/O power-on-reset
+ *
+ * \return True if reset was caused by a power-on-reset
+ */
+static inline bool reset_cause_is_io_power_on_reset(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_POR_IO);
+}
+
+/**
+ * \brief Check if chip reset was caused by a wake up from shutdown sleep mode
+ *
+ * \return True if reset was caused by a wake up from shutdown sleep mode
+ */
+static inline bool reset_cause_is_wake_from_shutdown_sleep(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_SLEEP);
+}
+
+/**
+ * \brief Check if chip reset was caused by a software reset
+ *
+ * \return True if reset was caused by a software reset
+ */
+static inline bool reset_cause_is_software_reset(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_SOFT);
+}
+
+/**
+ * \brief Check if chip reset was caused by a power spike detection
+ *
+ * \return True if reset was caused by a spike detection
+ */
+static inline bool reset_cause_is_spike_detected(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_SPIKE);
+}
+
+/**
+ * \brief Check if chip reset was caused by a watchdog timeout
+ *
+ * \return True if reset was caused by a watchdog timeout
+ */
+static inline bool reset_cause_is_watchdog(void)
+{
+	return (reset_cause_get_causes() & RESET_CAUSE_WDT);
+}
+
+//@}
+
+//! @}
+
+/**
+ * \page reset_cause_quickstart Quick start guide for reset cause service
+ *
+ * This is the quick start guide for the \ref reset_cause_group
+ * "Reset Cause service", with step-by-step instructions on how to configure
+ * and use the driver in a selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section reset_cause_basic_use_case Basic use case
+ * In this basic use case, the reset cause service is used for checking if the
+ * last reset was a watchdog reset.
+ *
+ * \section reset_cause_basic_use_case_setup Setup steps
+ *
+ * \subsection reset_cause_basic_use_case_setup_code Example code
+ * Add to application C-file:
+ * \code
+	 if (reset_cause_is_watchdog()) {
+		// Do action due to last reset being a watchdog reset
+		reset_cause_clear_causes(RESET_CAUSE_WDT);
+	 }
+\endcode
+ *
+ * \subsection reset_cause_basic_use_case_setup_flow Workflow
+ * -# Check for watchdog reset flag:
+ *   - \code if (reset_cause_is_watchdog()) { \endcode
+ *   - \attention Please consult the specific device datasheet on which reset
+ *   causes that are supported.
+ * -# Insert your own code taking action here. E.g.: Increase a watchdog reset
+ * counter.
+ * -# Reset flag if the flag was set to make sure it's not falsely
+ * detected in another reset:
+ *   - \code reset_cause_clear_causes(RESET_CAUSE_WDT); \endcode
+ *
+ * \section reset_cause_use_cases Advanced use cases
+ * For more advanced use of the Reset Cause service, see the following use cases:
+ * - \subpage reset_cause_use_case_1 : Software controlled reset
+ */
+
+/**
+ * \page reset_cause_use_case_1 Use case #1
+ * In this use case, the reset cause service is used to perform a software
+ * controlled reset.
+ *
+ * \section reset_cause_use_case_1_setup Setup steps
+ *
+ * \subsection reset_cause_use_case_1_setup_flow Workflow
+ * -# Call soft reset. This call will not return.
+ *   - \code reset_do_soft_reset(); \endcode
+ */
+
+#endif /* COMMON_DRIVERS_CPU_RESET_CAUSE_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.c b/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.c
new file mode 100644
index 0000000000..e962c06d93
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.c
@@ -0,0 +1,171 @@
+/**
+ * \file
+ *
+ * \brief 32-bit CRC implementation.
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "crc32.h"
+#include <status_codes.h>
+
+
+/**
+ * Convenience typedef for words.
+ *
+ * \note This type has an architecture dependent size, and is used to optimize
+ * the CRC algorithm with regards to the number of databus accesses.
+ */
+typedef unsigned int word_t;
+
+/** Polynomial for 32-bit CRC in IEEE 802.3. */
+#define CRC32_POLYNOMIAL     0xEDB88320UL
+
+/** Convenience macro for inverting the CRC. */
+#define COMPLEMENT_CRC(c)    ((c) ^ 0xffffffffUL)
+
+/** Convenience macro for size of a word. */
+#define WORD_SIZE            (sizeof(word_t))
+
+/** Bitmask for word-aligning an address. */
+#define WORD_ALIGNMENT_MASK  ~((uintptr_t)WORD_SIZE - 1)
+
+
+/**
+ * \internal
+ * \brief Recalculate 32-bit CRC for bytes within a word
+ *
+ * \param[in] data Data to recalculate for.
+ * \param[in] crc Initial/current CRC value.
+ * \param[in] bytes Number of data bytes in word.
+ *
+ * \return New CRC value.
+ *
+ * \attention This implementation assumes a little-endian architecture.
+ */
+static inline crc32_t _crc32_recalculate_bytes_helper(word_t data,
+		crc32_t crc, uint_fast8_t bytes)
+{
+	uint_fast8_t bit;
+
+	crc ^= data;
+
+	for (bit = 8 * bytes; bit > 0; bit--) {
+		if (crc & 1) {
+			crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
+		} else {
+			crc >>= 1;
+		}
+	}
+
+	return crc;
+}
+
+/**
+ * \brief Recalculate 32-bit CRC for another block
+ *
+ * This function recalculates the CRC according to the polynomial
+ * \ref CRC32_POLYNOMIAL for the specified data block and initial CRC value.
+ *
+ * To reduce the number of databus accesses and thus speed up the calculation,
+ * the algorithm is tuned to work with words as much as possible.
+ *
+ * \param[in] data Address of data.
+ * \param[in] length Length of data.
+ * \param[in,out] crc Address of variable containing current CRC, and to store
+ * recalculated CRC in.
+ *
+ * \return Status of calculation.
+ * \retval STATUS_OK if calculation succeeded.
+ * \retval <other> if calculation failed or could not be started.
+ *
+ * \note To calculate the CRC of multiple blocks, use \ref crc32_calculate()
+ * first, then this function for the following blocks.
+ *
+ * \attention This implementation assumes a little-endian architecture.
+ */
+enum status_code crc32_recalculate(const void *data, size_t length, crc32_t *crc)
+{
+	const word_t *word_ptr =
+			(word_t *)((uintptr_t)data & WORD_ALIGNMENT_MASK);
+	size_t temp_length;
+	crc32_t temp_crc = COMPLEMENT_CRC(*crc);
+	word_t word;
+
+	// Calculate for initial bytes to get word-aligned
+	if (length < WORD_SIZE) {
+		temp_length = length;
+	} else {
+		temp_length = ~WORD_ALIGNMENT_MASK & (WORD_SIZE - (uintptr_t)data);
+	}
+
+	if (temp_length) {
+		length -= temp_length;
+
+		word = *(word_ptr++);
+		word >>= 8 * (WORD_SIZE - temp_length);
+		temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, temp_length);
+	}
+
+	// Calculate for whole words, if any
+	temp_length = length & WORD_ALIGNMENT_MASK;
+
+	if (temp_length) {
+		length -= temp_length;
+		temp_length /= WORD_SIZE;
+
+		while (temp_length--) {
+			word = *(word_ptr++);
+			temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, WORD_SIZE);
+		}
+	}
+
+	// Calculate for tailing bytes
+	if (length) {
+		word = *word_ptr;
+		word &= 0xffffffffUL >> (8 * (WORD_SIZE - length));
+		temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, length);
+	}
+
+	*crc = COMPLEMENT_CRC(temp_crc);
+
+	return STATUS_OK;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.h b/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.h
new file mode 100644
index 0000000000..e0994c3cf2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.h
@@ -0,0 +1,138 @@
+/**
+ * \file
+ *
+ * \brief 32-bit CRC header.
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CRC32_H
+#define CRC32_H
+
+
+#include <compiler.h>
+
+
+/**
+ * \defgroup common_services_crc32 CRC-32 calculation service
+ *
+ * See \ref common_services_crc32_quickstart.
+ *
+ * This service enables the user to calculate 32-bit CRC using the polynomial
+ * defined in the IEEE 802.3 standard, with support for multiple data blocks
+ * of arbitrary sizes, and any alignment in memory.
+ *
+ * @{
+ */
+
+
+//! Type to contain 32-bit CRC.
+typedef uint32_t crc32_t;
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum status_code crc32_recalculate(const void *data, size_t length, crc32_t *crc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \brief Calculate 32-bit CRC for initial block
+ *
+ * This function calculates the CRC for the specified data block, which may be
+ * first of an arbitrary number of blocks.
+ *
+ * The actual calculation is done in \ref crc32_recalculate(), while this
+ * function just sets up the initial CRC value.
+ *
+ * \param[in] data Address of data.
+ * \param[in] length Length of data.
+ * \param[out] crc Address of variable to store the calculated CRC in.
+ *
+ * \return Status of calculation.
+ * \retval STATUS_OK if calculation succeeded.
+ * \retval <other> if calculation failed somehow.
+ *
+ * \note To calculate the CRC of multiple blocks, use this function first, then
+ * \ref crc32_recalculate() for the following blocks.
+ */
+static inline enum status_code crc32_calculate(const void *data, size_t length,
+		crc32_t *crc)
+{
+	*crc = 0;
+
+	return crc32_recalculate(data, length, crc);
+}
+
+/** @} */
+
+/**
+ * \page common_services_crc32_quickstart Quick Start Guide for CRC-32
+ *
+ * To use this service, the user must supply a \ref crc32_t "container" variable
+ * for the CRC and call \ref crc32_calculate() with the parameters for the first
+ * block in the dataset. For subsequent blocks, \ref crc32_recalculate() must be
+ * used.
+ *
+ * \note The user may also initialize the container with a known CRC value and
+ * use that as the "seed" for \ref crc32_recalculate().
+ *
+ *
+ * \section common_services_crc32_quickstart_code Example Code
+ *
+\code
+	uint8_t block1[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
+	uint8_t block2[6] = {0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
+
+	crc32_t my_crc;
+
+	crc32_calculate(block1, sizeof(block1), &my_crc);
+	crc32_recalculate(block2, sizeof(block2), &my_crc);
+\endcode
+ *
+ */
+
+#endif // CRC32_H
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/delay/delay.h b/bsp/samd21/sam_d2x_asflib/common/services/delay/delay.h
new file mode 100644
index 0000000000..cab97f5e81
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/delay/delay.h
@@ -0,0 +1,139 @@
+/**
+ * \file
+ *
+ * \brief Common Delay Service
+ *
+ * Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _DELAY_H_
+#define _DELAY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sysclk.h>
+
+#if UC3
+#   include <cycle_counter.h>
+#elif XMEGA
+#   include "xmega/cycle_counter.h"
+#elif MEGA
+#   include "mega/cycle_counter.h"
+#elif SAM
+#   include "sam/cycle_counter.h"
+#endif
+
+/**
+ * @defgroup group_common_services_delay Busy-Wait Delay Routines
+ *
+ * This module provides simple loop-based delay routines for those
+ * applications requiring a brief wait during execution. Common API
+ * for UC3, XMEGA, and AVR MEGA.
+ *
+ * @{
+ */
+
+/**
+ * @def F_CPU
+ * @brief MCU Clock Frequency (Hertz)
+ *
+ * @deprecated
+ * The \ref F_CPU configuration constant is used for compatibility with the
+ * \ref group_common_services_delay routines. The common loop-based delay
+ * routines are designed to use the \ref clk_group modules while anticipating
+ * support for legacy applications assuming a statically defined clock
+ * frequency. Applications using a statically configured MCU clock frequency
+ * can define \ref F_CPU (Hertz), in which case the common delay routines will
+ * use this value rather than calling sysclk_get_cpu_hz() to get the current
+ * MCU clock frequency.
+ */
+#ifndef F_CPU
+#       define F_CPU sysclk_get_cpu_hz()
+#endif
+
+/**
+ * @def delay_init
+ *
+ * @brief Initialize the delay driver.
+ * @param fcpu_hz CPU frequency in Hz
+ *
+ * @deprecated
+ * This function is provided for compatibility with ASF applications that
+ * may not have been updated to configure the system clock via the common
+ * clock service; e.g. sysclk_init() and a configuration header file are
+ * used to configure clocks.
+ *
+ * The functions in this module call \ref sysclk_get_cpu_hz() function to
+ * obtain the system clock frequency.
+ */
+#define delay_init(fcpu_hz)
+
+/**
+ * @def delay_s
+ * @brief Delay in seconds.
+ * @param delay Delay in seconds
+ */
+#define delay_s(delay)      ((delay) ? cpu_delay_ms(1000 * delay, F_CPU) : cpu_delay_us(1, F_CPU))
+
+/**
+ * @def delay_ms
+ * @brief Delay in milliseconds.
+ * @param delay Delay in milliseconds
+ */
+#define delay_ms(delay)     ((delay) ? cpu_delay_ms(delay, F_CPU) : cpu_delay_us(1, F_CPU))
+
+/**
+ * @def delay_us
+ * @brief Delay in microseconds.
+ * @param delay Delay in microseconds
+ */
+#define delay_us(delay)     ((delay) ? cpu_delay_us(delay, F_CPU) : cpu_delay_us(1, F_CPU))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _DELAY_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.c b/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.c
new file mode 100644
index 0000000000..96669ef6b8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.c
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "cycle_counter.h"
+
+// Delay loop is put to SRAM so that FWS will not affect delay time
+OPTIMIZE_HIGH
+RAMFUNC
+void portable_delay_cycles(unsigned long n)
+{
+	UNUSED(n);
+
+	__asm (
+		"loop: DMB	\n"
+		"SUBS R0, R0, #1  \n"
+		"BNE.N loop         "
+	);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.h b/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.h
new file mode 100644
index 0000000000..4ac1c6b583
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.h
@@ -0,0 +1,126 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _cycle_counter_h_
+#define _cycle_counter_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include <compiler.h>
+
+/**
+ * @name Convenience functions for busy-wait delay loops
+ *
+ * @def delay_cycles
+ * @brief Delay program execution for a specified number of CPU cycles.
+ * @param n number of CPU cycles to wait
+ *
+ * @def cpu_delay_ms
+ * @brief Delay program execution for a specified number of milliseconds.
+ * @param delay number of milliseconds to wait
+ * @param f_cpu CPU frequency in Hertz
+ *
+ * @def cpu_delay_us
+ * @brief Delay program execution for a specified number of microseconds.
+ * @param delay number of microseconds to wait
+ * @param f_cpu CPU frequency in Hertz
+ *
+ * @def cpu_ms_2_cy
+ * @brief Convert milli-seconds into CPU cycles.
+ * @param ms number of milliseconds
+ * @param f_cpu CPU frequency in Hertz
+ * @return the converted number of CPU cycles
+ *
+ * @def cpu_us_2_cy
+ * @brief Convert micro-seconds into CPU cycles.
+ * @param ms number of microseconds
+ * @param f_cpu CPU frequency in Hertz
+ * @return the converted number of CPU cycles
+ *
+ * @{
+ */
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ *
+ * \note The function runs in internal RAM so that flash wait states
+ *       will not affect the delay time.
+ *
+ * \param n Number of cycles
+ */
+void portable_delay_cycles(unsigned long n);
+
+/* Cortex-M7 is faster than Cortex-M3/M4/M0+ */
+#ifdef __CM7_REV
+
+#  define cpu_ms_2_cy(ms, f_cpu)  \
+	(((uint64_t)(ms) * (f_cpu) + (uint64_t)(5.932e3 - 1ul)) / (uint64_t)5.932e3)
+#  define cpu_us_2_cy(us, f_cpu)  \
+	(((uint64_t)(us) * (f_cpu) + (uint64_t)(5.932e6 - 1ul)) / (uint64_t)5.932e6)
+
+#else
+
+#  define cpu_ms_2_cy(ms, f_cpu)  \
+	(((uint64_t)(ms) * (f_cpu) + (uint64_t)(14e3 - 1ul)) / (uint64_t)14e3)
+#  define cpu_us_2_cy(us, f_cpu)  \
+	(((uint64_t)(us) * (f_cpu) + (uint64_t)(14e6 - 1ul)) / (uint64_t)14e6)
+
+#endif
+
+#define delay_cycles               portable_delay_cycles
+
+#define cpu_delay_ms(delay, f_cpu) delay_cycles(cpu_ms_2_cy(delay, f_cpu))
+#define cpu_delay_us(delay, f_cpu) delay_cycles(cpu_us_2_cy(delay, f_cpu))
+//! @}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _cycle_counter_h_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.c b/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.c
new file mode 100644
index 0000000000..1b251bf4c2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.c
@@ -0,0 +1,82 @@
+/**
+ * \file
+ *
+ * \brief This file controls the software FIFO management.
+ *
+ * These functions manages FIFOs thanks to simple a API. The FIFO can
+ * be 100% full thanks to a double-index range implementation. For example,
+ * a FIFO of 4 elements can be implemented: the FIFO can really hold up to 4
+ * elements.
+ * This is particularly well suited for any kind of application needing a lot of
+ * small FIFO.
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "fifo.h"
+
+int fifo_init(fifo_desc_t *fifo_desc, void *buffer, uint8_t size)
+{
+	// Check the size parameter. It must be not null...
+	Assert (size);
+
+	// ... must be a 2-power ...
+	Assert (!(size & (size - 1)));
+
+	// ... and must fit in a uint8_t. Since the read and write indexes are using a
+	// double-index range implementation, the max FIFO size is thus 128 items.
+	Assert (size <= 128);
+
+	// Fifo starts empty.
+	fifo_desc->read_index  = 0;
+	fifo_desc->write_index = 0;
+
+	// Save the size parameter.
+	fifo_desc->size = size;
+
+	// Create a mask to speed up the FIFO management (index swapping).
+	fifo_desc->mask = (2 * (uint16_t)size) - 1;
+
+	// Save the buffer pointer.
+	fifo_desc->buffer.u8ptr = buffer;
+
+	return FIFO_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.h b/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.h
new file mode 100644
index 0000000000..7d57ad1297
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.h
@@ -0,0 +1,668 @@
+/**
+ * \file
+ *
+ * \brief This file controls the software FIFO management.
+ *
+ * These functions manages FIFOs thanks to simple a API. The FIFO can
+ * be 100% full thanks to a double-index range implementation. For example,
+ * a FIFO of 4 elements can be implemented: the FIFO can really hold up to 4
+ * elements.
+ * This is particularly well suited for any kind of application needing a lot of
+ * small FIFO.
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _FIFO_H_
+#define _FIFO_H_
+
+#include "compiler.h"
+
+/**
+ * \defgroup fifo_group First-In-First-Out Buffer (FIFO)
+ *
+ * See \ref fifo_quickstart.
+ *
+ * These functions manages FIFOs thanks to simple a API. The FIFO can
+ * be 100% full thanks to a double-index range implementation. For example,
+ * a FIFO of 4 elements can be implemented: the FIFO can really hold up to 4
+ * elements. This is particularly well suited for any kind of application
+ * needing a lot of small FIFO. The maximum fifo size is 128 items (uint8,
+ * uint16 or uint32). Note that the driver, thanks to its conception, does
+ * not use interrupt protection.
+ *
+ * @{
+ */
+
+//! Error codes used by FIFO driver.
+enum {
+	FIFO_OK = 0,          //!< Normal operation.
+	FIFO_ERROR_OVERFLOW,  //!< Attempt to push something in a FIFO that is full.
+	FIFO_ERROR_UNDERFLOW, //!< Attempt to pull something from a FIFO that is empty
+	FIFO_ERROR,           //!< Error condition during FIFO initialization
+};
+
+//! FIFO descriptor used by FIFO driver.
+struct fifo_desc {
+	union
+	{
+		uint32_t *u32ptr; //!< Pointer to unsigned-32 bits location
+		uint16_t *u16ptr; //!< Pointer to unsigned-16 bits location
+		uint8_t  *u8ptr;  //!< Pointer to unsigned-8 bits location
+	}  buffer;
+	volatile uint8_t read_index;  //!< Read index
+	volatile uint8_t write_index; //!< Write index
+	uint8_t size;                 //!< Size of the FIFO (unit is in number of 'element')
+	uint8_t mask;                 //!< Mask used to speed up FIFO operation (wrapping)
+};
+
+typedef struct fifo_desc fifo_desc_t;
+
+/**
+ *  \brief Initializes a new software FIFO for a certain 'size'.
+ *
+ *  \pre Both fifo descriptor and buffer must be allocated by the caller before.
+ *
+ *  \param fifo_desc  Pointer on the FIFO descriptor.
+ *  \param buffer     Pointer on the FIFO buffer.
+ *  \param size       Size of the buffer (unit is in number of 'elements').
+ *                    It must be a 2-power and <= to 128.
+ *
+ *  \return Status
+ *    \retval FIFO_OK when no error occurred.
+ *    \retval FIFO_ERROR when the size is not a 2-power.
+ */
+int fifo_init(fifo_desc_t *fifo_desc, void *buffer, uint8_t size);
+
+/**
+ *  \brief Returns the number of elements in the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \return The number of used elements.
+ */
+static inline uint8_t fifo_get_used_size(fifo_desc_t *fifo_desc)
+{
+	return ((fifo_desc->write_index - fifo_desc->read_index) & fifo_desc->mask);
+}
+
+/**
+ *  \brief Returns the remaining free spaces of the FIFO (in number of elements).
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \return The number of free elements.
+ */
+static inline uint8_t fifo_get_free_size(fifo_desc_t *fifo_desc)
+{
+	return fifo_desc->size - fifo_get_used_size(fifo_desc);
+}
+
+/**
+ *  \brief Tests if a FIFO is empty.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \return Status
+ *    \retval true when the FIFO is empty.
+ *    \retval false when the FIFO is not empty.
+ */
+static inline bool fifo_is_empty(fifo_desc_t *fifo_desc)
+{
+	return (fifo_desc->write_index == fifo_desc->read_index);
+}
+
+/**
+ *  \brief Tests if a FIFO is full.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \return Status
+ *    \retval true when the FIFO is full.
+ *    \retval false when the FIFO is not full.
+ */
+static inline bool fifo_is_full(fifo_desc_t *fifo_desc)
+{
+	return (fifo_get_used_size(fifo_desc) == fifo_desc->size);
+}
+
+/**
+ *  \brief Puts a new 8-bits element into the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ */
+static inline void fifo_push_uint8_nocheck(fifo_desc_t *fifo_desc, uint32_t item)
+{
+	uint8_t write_index;
+
+	write_index = fifo_desc->write_index;
+	fifo_desc->buffer.u8ptr[write_index & (fifo_desc->mask >> 1)] = item;
+	write_index = (write_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->write_index = write_index;
+}
+
+/**
+ *  \brief Puts a new 8-bits element into the FIFO and
+ *         checks for a possible overflow.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ *
+ *  \return Status
+ *    \retval FIFO_OK when no error occurred.
+ *    \retval FIFO_ERROR_UNDERFLOW when the FIFO was empty.
+ */
+static inline int fifo_push_uint8(fifo_desc_t *fifo_desc, uint32_t item)
+{
+	uint8_t write_index;
+
+	if (fifo_is_full(fifo_desc)) {
+		return FIFO_ERROR_OVERFLOW;
+	}
+
+	write_index = fifo_desc->write_index;
+	fifo_desc->buffer.u8ptr[write_index & (fifo_desc->mask >> 1)] = item;
+	write_index = (write_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->write_index = write_index;
+
+	return FIFO_OK;
+}
+
+/**
+ *  \brief Puts a new 16-bits element into the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ */
+static inline void fifo_push_uint16_nocheck(fifo_desc_t *fifo_desc, uint32_t item)
+{
+	uint8_t write_index;
+
+	write_index = fifo_desc->write_index;
+	fifo_desc->buffer.u16ptr[write_index & (fifo_desc->mask >> 1)] = item;
+	write_index = (write_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->write_index = write_index;
+}
+
+/**
+ *  \brief Puts a new 16-bits element into the FIFO and
+ *         checks for a possible overflow.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ *
+ *  \return Status
+ *    \retval FIFO_OK when no error occurred.
+ *    \retval FIFO_ERROR_UNDERFLOW when the FIFO was empty.
+ */
+static inline int fifo_push_uint16(fifo_desc_t *fifo_desc, uint32_t item)
+{
+	uint8_t write_index;
+
+	if (fifo_is_full(fifo_desc)) {
+		return FIFO_ERROR_OVERFLOW;
+	}
+
+	write_index = fifo_desc->write_index;
+	fifo_desc->buffer.u16ptr[write_index & (fifo_desc->mask >> 1)] = item;
+	write_index = (write_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->write_index = write_index;
+
+	return FIFO_OK;
+}
+
+/**
+ *  \brief Puts a new 32-bits element into the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ */
+static inline void fifo_push_uint32_nocheck(fifo_desc_t *fifo_desc, uint32_t item)
+{
+	uint8_t write_index;
+
+	write_index = fifo_desc->write_index;
+	fifo_desc->buffer.u32ptr[write_index & (fifo_desc->mask >> 1)] = item;
+	write_index = (write_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->write_index = write_index;
+}
+
+/**
+ *  \brief Puts a new 32-bits element into the FIFO and
+ *         checks for a possible overflow.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ *
+ *  \return Status
+ *    \retval FIFO_OK when no error occurred.
+ *    \retval FIFO_ERROR_UNDERFLOW when the FIFO was empty.
+ */
+static inline int fifo_push_uint32(fifo_desc_t *fifo_desc, uint32_t item)
+{
+	uint8_t write_index;
+
+	if (fifo_is_full(fifo_desc)) {
+		return FIFO_ERROR_OVERFLOW;
+	}
+
+	write_index = fifo_desc->write_index;
+	fifo_desc->buffer.u32ptr[write_index & (fifo_desc->mask >> 1)] = item;
+	write_index = (write_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->write_index = write_index;
+
+	return FIFO_OK;
+}
+
+/**
+ *  \brief Gets a 8-bits element from the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \return extracted element.
+ */
+static inline uint8_t fifo_pull_uint8_nocheck(fifo_desc_t *fifo_desc)
+{
+	uint8_t read_index;
+	uint8_t item;
+
+	read_index = fifo_desc->read_index;
+	item = fifo_desc->buffer.u8ptr[read_index & (fifo_desc->mask >> 1)];
+	read_index = (read_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->read_index = read_index;
+
+	return item;
+}
+
+/**
+ *  \brief Gets a 8-bits element from the FIFO and
+ *         checks for a possible underflow.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ *
+ *  \return Status
+ *    \retval FIFO_OK when no error occurred.
+ *    \retval FIFO_ERROR_UNDERFLOW when the FIFO was empty.
+ */
+static inline int fifo_pull_uint8(fifo_desc_t *fifo_desc, uint8_t *item)
+{
+	uint8_t read_index;
+
+	if (fifo_is_empty(fifo_desc)) {
+		return FIFO_ERROR_UNDERFLOW;
+	}
+
+	read_index = fifo_desc->read_index;
+	*item = fifo_desc->buffer.u8ptr[read_index & (fifo_desc->mask >> 1)];
+	read_index = (read_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->read_index = read_index;
+
+	return FIFO_OK;
+}
+
+/**
+ *  \brief Gets a 16-bits element from the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \return extracted element.
+ */
+static inline uint16_t fifo_pull_uint16_nocheck(fifo_desc_t *fifo_desc)
+{
+	uint8_t read_index;
+	uint16_t item;
+
+	read_index = fifo_desc->read_index;
+	item = fifo_desc->buffer.u16ptr[read_index & (fifo_desc->mask >> 1)];
+	read_index = (read_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->read_index = read_index;
+
+	return item;
+}
+
+/**
+ *  \brief Gets a 16-bits element from the FIFO and
+ *         checks for a possible underflow.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ *
+ *  \return Status
+ *    \retval FIFO_OK when no error occurred.
+ *    \retval FIFO_ERROR_UNDERFLOW when the FIFO was empty.
+ */
+static inline int fifo_pull_uint16(fifo_desc_t *fifo_desc, uint16_t *item)
+{
+	uint8_t read_index;
+
+	if (fifo_is_empty(fifo_desc)) {
+		return FIFO_ERROR_UNDERFLOW;
+	}
+
+	read_index = fifo_desc->read_index;
+	*item = fifo_desc->buffer.u16ptr[read_index & (fifo_desc->mask >> 1)];
+	read_index = (read_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->read_index = read_index;
+
+	return FIFO_OK;
+}
+
+/**
+ *  \brief Gets a 32-bits element from the FIFO
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \return extracted element.
+ */
+static inline uint32_t fifo_pull_uint32_nocheck(fifo_desc_t *fifo_desc)
+{
+	uint8_t read_index;
+	uint32_t item;
+
+	read_index = fifo_desc->read_index;
+	item = fifo_desc->buffer.u32ptr[read_index & (fifo_desc->mask >> 1)];
+	read_index = (read_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->read_index = read_index;
+
+	return item;
+}
+
+/**
+ *  \brief Gets a 32-bits element from the FIFO and
+ *         checks for a possible underflow.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *  \param item       extracted element.
+ *
+ *  \return Status
+ *    \retval FIFO_OK when no error occurred.
+ *    \retval FIFO_ERROR_UNDERFLOW when the FIFO was empty.
+ */
+static inline int fifo_pull_uint32(fifo_desc_t *fifo_desc, uint32_t *item)
+{
+	uint8_t read_index;
+
+	if (fifo_is_empty(fifo_desc)) {
+		return FIFO_ERROR_UNDERFLOW;
+	}
+
+	read_index = fifo_desc->read_index;
+	*item = fifo_desc->buffer.u32ptr[read_index & (fifo_desc->mask >> 1)];
+	read_index = (read_index + 1) & fifo_desc->mask;
+
+	// Must be the last thing to do.
+	barrier();
+	fifo_desc->read_index = read_index;
+
+	return FIFO_OK;
+}
+
+/**
+ *  \brief Gets a 32-bits element from the FIFO but does
+ *         not remove it from the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \retval item      extracted element.
+ */
+static inline uint32_t fifo_peek_uint32(fifo_desc_t *fifo_desc)
+{
+	return fifo_desc->buffer.u32ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
+}
+
+/**
+ *  \brief Gets a 16-bits element from the FIFO but does
+ *         not remove it from the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \retval item      extracted element.
+ */
+static inline uint16_t fifo_peek_uint16(fifo_desc_t *fifo_desc)
+{
+	return fifo_desc->buffer.u16ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
+}
+
+/**
+ *  \brief Gets a 8-bits element from the FIFO but does
+ *         not remove it from the FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ *
+ *  \retval item      extracted element.
+ */
+static inline uint8_t fifo_peek_uint8(fifo_desc_t *fifo_desc)
+{
+	return fifo_desc->buffer.u8ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
+}
+
+/**
+ *  \brief Flushes a software FIFO.
+ *
+ *  \param fifo_desc  The FIFO descriptor.
+ */
+static inline void fifo_flush(fifo_desc_t *fifo_desc)
+{
+	// Fifo starts empty.
+	fifo_desc->read_index = fifo_desc->write_index = 0;
+}
+
+/**
+ * @}
+ */
+
+ /**
+ * \page fifo_quickstart Quick start guide for First-In-First-Out Buffer (FIFO)
+ *
+ * This is the quick start guide for the \ref fifo_group, with
+ * step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section fifo_use_cases FIFO use cases
+ * - \ref fifo_basic_use_case
+ * - \subpage fifo_use_case_1
+ *
+ * \section fifo_basic_use_case Basic use case - Push and pull
+ * In this use case, an element will be pushed to the FIFO, and the same
+ * element will be pulled from it.
+ *
+ * \section fifo_basic_use_case_setup Setup steps
+ *
+ * \subsection fifo_basic_use_case_setup_code Example code
+ * The following must be added to the project:
+ * \code
+	#define FIFO_BUFFER_LENGTH  4
+	#define PUSH_VALUE          0x12345678
+	union buffer_element {
+	   uint8_t  byte;
+	   uint16_t halfword;
+	   uint32_t word;
+	};
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+	union buffer_element fifo_buffer[FIFO_BUFFER_LENGTH];
+	fifo_desc_t fifo_desc;
+	fifo_init(&fifo_desc, fifo_buffer, FIFO_BUFFER_LENGTH); 
+\endcode
+ *
+ * \subsection fifo_basic_use_case_setup_flow Workflow
+ * -# Create a FIFO buffer of FIFO_BUFFER_LENGTH elements, capable
+ * of holding a byte, halfword or word:
+ *   - \code union buffer_element fifo_buffer[FIFO_BUFFER_LENGTH]; \endcode
+ * -# Create a FIFO buffer descriptor that contains information about the
+ * location of the FIFO buffer, its size and where to read from or write to
+ * upon the next buffer pull or push:
+ *   - \code fifo_desc_t fifo_desc; \endcode
+ * -# Initialize the FIFO:
+ *   - \code fifo_init(&fifo_desc, fifo_buffer, FIFO_BUFFER_LENGTH); \endcode
+ *
+ * \section fifo_basic_use_case_usage Usage steps
+ *
+ * \subsection fifo_basic_use_case_usage_code Example code
+ * Add to application C-file:
+ * \code
+	uint8_t status;
+	uint8_t pull_value;
+	status = fifo_push_uint8(&fifo_desc, PUSH_VALUE & 0xff);
+	status = fifo_pull_uint8(&fifo_desc, &pull_value);
+\endcode
+ *
+ * \subsection fifo_basic_use_case_usage_flow Workflow
+ * -# Create a variable to hold the return status from the FIFO:
+ *   - \code uint8_t status; \endcode
+ * -# Create a variable to hold the pulled value from the FIFO:
+ *   - \code uint8_t pull_value; \endcode
+ * -# Put a new 8-bit element into the FIFO:
+ *   - \code status = fifo_push_uint8(&fifo_desc, PUSH_VALUE & 0xff); \endcode
+ * \note The status variable will contain \ref FIFO_OK if no error occurred.
+ * -# Get the 8-bit element from the FIFO:
+ *   - \code status = fifo_pull_uint8(&fifo_desc, &pull_value); \endcode
+ * \note The status variable will contain \ref FIFO_OK if no error occurred.
+ */
+
+/**
+ * \page fifo_use_case_1 Push and flush
+ *
+ * In this use case, two elements will be pushed to the FIFO, and the FIFO
+ * will be flushed.
+ *
+ * \section fifo_use_case_1_setup Setup steps
+ *
+ * \subsection fifo_use_case_1_setup_code Example code
+ * The following must be added to the project:
+ * \code
+	#define FIFO_BUFFER_LENGTH  4
+	#define PUSH_VALUE          0x12345678
+	union buffer_element {
+	   uint8_t  byte;
+	   uint16_t halfword;
+	   uint32_t word;
+	};
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+	union buffer_element fifo_buffer[FIFO_BUFFER_LENGTH];
+	fifo_desc_t fifo_desc;
+	fifo_init(&fifo_desc, fifo_buffer, FIFO_BUFFER_LENGTH); 
+\endcode
+ *
+ * \subsection fifo_use_case_1_setup_flow Workflow
+ * -# Create a FIFO buffer of FIFO_BUFFER_LENGTH elements, capable
+ * of holding a byte, halfword or word:
+ *   - \code union buffer_element fifo_buffer[FIFO_BUFFER_LENGTH]; \endcode
+ * -# Create a FIFO buffer descriptor that containing information about the
+ * location of the FIFO buffer, its size and where to read from or write to
+ * upon the next buffer pull or push:
+ *   - \code fifo_desc_t fifo_desc; \endcode
+ * -# Initialize the FIFO:
+ *   - \code fifo_init(&fifo_desc, fifo_buffer, FIFO_BUFFER_LENGTH); \endcode
+ * \section fifo_use_case_1_usage Usage steps
+ *
+ * \subsection fifo_use_case_1_usage_code Example code
+ * Add to application C-file:
+ * \code
+	uint8_t status;
+	bool fifo_empty;
+	status = fifo_push_uint16(&fifo_desc, PUSH_VALUE & 0xffff);
+	status = fifo_push_uint16(&fifo_desc, PUSH_VALUE & 0xffff);
+	fifo_flush(&fifo_desc);
+	fifo_empty = fifo_is_empty(&fifo_desc);
+\endcode
+ *
+ * \subsection fifo_use_case_1_usage_flow Workflow
+ * -# Create a variable to hold the return status from the FIFO:
+ *   - \code uint8_t status; \endcode
+ * -# Create a variable to hold the pulled value from the FIFO:
+ *   - \code uint16_t pull_value; \endcode
+ * -# Put two new 16-bit element into the FIFO:
+ *   - \code status = fifo_push_uint16(&fifo_desc, PUSH_VALUE & 0xffff); \endcode
+ *   - \code status = fifo_push_uint16(&fifo_desc, PUSH_VALUE & 0xffff); \endcode
+ * \note The status variable will contain \ref FIFO_OK if no error occurred.
+ * -# Flush the FIFO:
+ *   - \code fifo_flush(&fifo_desc); \endcode
+ * -# Check that the FIFO is empty after flushing:
+ *   - \code fifo_empty = fifo_is_empty(&fifo_desc); \endcode
+ * \note The fifo_empty variable will be true if the FIFO is empty.
+ */
+
+#endif  // _FIFO_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/gpio/gpio.h b/bsp/samd21/sam_d2x_asflib/common/services/gpio/gpio.h
new file mode 100644
index 0000000000..e062690d8d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/gpio/gpio.h
@@ -0,0 +1,86 @@
+/**
+ * \file
+ *
+ * \brief Common GPIO API.
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include <parts.h>
+
+#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+# include "sam_gpio/sam_gpio.h"
+#elif XMEGA
+# include "xmega_gpio/xmega_gpio.h"
+#elif MEGA || MEGA_RF
+# include "mega_gpio/mega_gpio.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \defgroup gpio_group General Purpose Input/Output
+ *
+ * This is the common API for GPIO. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section io_group_platform Platform Dependencies
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - gpio_pin_is_low()
+ *   - gpio_pin_is_high()
+ *   - gpio_set_pin_high()
+ *   - gpio_set_pin_group_high()
+ *   - gpio_set_pin_low()
+ *   - gpio_set_pin_group_low()
+ *   - gpio_toggle_pin()
+ *   - gpio_toggle_pin_group()
+ *   - gpio_configure_pin()
+ *   - gpio_configure_group()
+ */
+
+#endif  /* _GPIO_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/gpio/sam_gpio/sam_gpio.h b/bsp/samd21/sam_d2x_asflib/common/services/gpio/sam_gpio/sam_gpio.h
new file mode 100644
index 0000000000..cb5e974f63
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/gpio/sam_gpio/sam_gpio.h
@@ -0,0 +1,83 @@
+/**
+ * \file
+ *
+ * \brief GPIO service for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAM_GPIO_H_INCLUDED
+#define SAM_GPIO_H_INCLUDED
+
+#include "compiler.h"
+#include "pio.h"
+
+#define gpio_pin_is_low(io_id) \
+	(pio_get_pin_value(io_id) ? 0 : 1)
+
+#define gpio_pin_is_high(io_id) \
+	(pio_get_pin_value(io_id) ? 1 : 0)
+
+#define gpio_set_pin_high(io_id) \
+	pio_set_pin_high(io_id)
+
+#define gpio_set_pin_low(io_id) \
+	pio_set_pin_low(io_id)
+
+#define gpio_toggle_pin(io_id) \
+	pio_toggle_pin(io_id)
+
+#define gpio_configure_pin(io_id,io_flags) \
+	pio_configure_pin(io_id,io_flags)
+
+#define gpio_configure_group(port_id,port_mask,io_flags) \
+	pio_configure_pin_group(port_id,port_mask,io_flags)
+
+#define gpio_set_pin_group_high(port_id,mask) \
+	pio_set_pin_group_high(port_id,mask)
+
+#define gpio_set_pin_group_low(port_id,mask) \
+	pio_set_pin_group_low(port_id,mask)
+
+#define gpio_toggle_pin_group(port_id,mask) \
+	pio_toggle_pin_group(port_id,mask)
+
+#endif /* SAM_GPIO_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/hugemem/generic/hugemem.h b/bsp/samd21/sam_d2x_asflib/common/services/hugemem/generic/hugemem.h
new file mode 100644
index 0000000000..d7aa125a95
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/hugemem/generic/hugemem.h
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Generic implementation of huge data memory access
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GENERIC_HUGEMEM_H_INCLUDED
+#define GENERIC_HUGEMEM_H_INCLUDED
+
+#include <stdint.h>
+#include <string.h>
+
+/**
+ * \weakgroup hugemem_group
+ * @{
+ */
+
+/**
+ * \internal
+ * \defgroup hugemem_generic_group Generic hugemem implementation.
+ *
+ * These functions are needed for code compatibility between 8- and 32-bit AVR,
+ * as well as a different application configurations on 8-bit AVR, i.e., if huge
+ * data memory is optional.
+ */
+
+typedef void * hugemem_ptr_t;
+
+#define HUGEMEM_NULL    NULL
+
+static inline uint8_t hugemem_read8(const hugemem_ptr_t from)
+{
+	return *(uint8_t *)from;
+}
+
+static inline uint16_t hugemem_read16(const hugemem_ptr_t from)
+{
+	return *(uint16_t *)from;
+}
+
+static inline uint32_t hugemem_read32(const hugemem_ptr_t from)
+{
+	return *(uint32_t *)from;
+}
+
+static inline void hugemem_read_block(void *to, const hugemem_ptr_t from,
+		size_t size)
+{
+	memcpy(to, from, size);
+}
+
+static inline void hugemem_write8(hugemem_ptr_t to, uint8_t val)
+{
+	*(uint8_t *)to = val;
+}
+
+static inline void hugemem_write16(hugemem_ptr_t to, uint16_t val)
+{
+	*(uint16_t *)to = val;
+}
+
+
+static inline void hugemem_write32(hugemem_ptr_t to, uint32_t val)
+{
+	*(uint32_t *)to = val;
+}
+
+static inline void hugemem_write_block(hugemem_ptr_t to, const void *from,
+		size_t size)
+{
+	memcpy(to, from, size);
+}
+
+//@}
+
+#endif /* GENERIC_HUGEMEM_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/hugemem/hugemem.h b/bsp/samd21/sam_d2x_asflib/common/services/hugemem/hugemem.h
new file mode 100644
index 0000000000..f8395022f9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/hugemem/hugemem.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Huge data memory space access
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef HUGEMEM_H_INCLUDED
+#define HUGEMEM_H_INCLUDED
+
+#include <stdint.h>
+#include <stddef.h>
+
+#if defined(__AVR32__) || defined(__ICCAVR32__)
+# include <generic/hugemem.h>
+#elif defined(__AVR__) || defined (__ICCAVR__)
+# include <avr8/hugemem.h>
+#else
+# error Unknown architecture passed to hugemem interface.
+# error Expected __AVR32__ or __AVR__.
+#endif
+
+/**
+ * \defgroup hugemem_group Data in Huge Data Memory Space
+ *
+ * Due to shortcomings of the GCC compiler for 8-bit AVR, custom functions are
+ * needed for access to data beyond the 64 kB boundary, i.e., addresses that
+ * are larger than 16-bit.
+ *
+ * The definition of huge memory space can differ between architectures, so the
+ * implementation is architecture specific.
+ *
+ * This module supplies functions for copying a number of bytes between huge
+ * and 64 kB data memory space, and is needed solely for code compatibility
+ * across compilers.
+ *
+ * @{
+ */
+
+/**
+ * \typedef hugemem_ptr_t
+ *
+ * \brief Type to use for pointers to huge memory.
+ */
+
+/**
+ * \def HUGEMEM_NULL
+ *
+ * \brief Hugemem null pointer, similar to NULL, but works across different
+ * platforms.
+ */
+
+/**
+ * \fn uint_fast8_t hugemem_read8(const hugemem_ptr_t from)
+ *
+ * \brief Read 8-bit value stored at huge memory address \a from.
+ */
+
+/**
+ * \fn uint_fast16_t hugemem_read16(const hugemem_ptr_t from)
+ *
+ * \brief Read 16-bit value stored at huge memory address \a from.
+ */
+
+/**
+ * \fn void hugemem_read_block(void *to, const hugemem_ptr_t from, size_t size)
+ *
+ * \brief Read \a size bytes from huge memory address \a from into buffer at
+ * address \a to.
+ */
+
+/**
+ * \fn uint_fast32_t hugemem_read32(const hugemem_ptr_t from)
+ *
+ * \brief Read 32-bit value stored at huge memory address \a from.
+ */
+
+/**
+ * \fn void hugemem_write8(hugemem_ptr_t to, uint_fast8_t val)
+ *
+ * \brief Write 8-bit value \a val to huge memory address \a to.
+ */
+
+/**
+ * \fn void hugemem_write16(hugemem_ptr_t to, uint_fast16_t val)
+ *
+ * \brief Write 16-bit value \a val to huge memory address \a to.
+ */
+
+/**
+ * \fn void hugemem_write32(hugemem_ptr_t to, uint_fast32_t val)
+ *
+ * \brief Write 32-bit value \a val to huge memory address \a to.
+ */
+
+/**
+ * \fn void hugemem_write_block(hugemem_ptr_t to, const void *from, size_t size)
+ *
+ * \brief Write \a size bytes from buffer at address \a from to huge memory
+ * address \a to.
+ */
+
+//@}
+
+#endif /* HUGEMEM_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/ioport/ioport.h b/bsp/samd21/sam_d2x_asflib/common/services/ioport/ioport.h
new file mode 100644
index 0000000000..ed8db27ccc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/ioport/ioport.h
@@ -0,0 +1,548 @@
+/**
+ * \file
+ *
+ * \brief Common IOPORT service main header file for AVR, UC3 and ARM
+ *        architectures.
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef IOPORT_H
+#define IOPORT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <parts.h>
+#include <compiler.h>
+
+/**
+ * \defgroup ioport_group Common IOPORT API
+ *
+ * See \ref ioport_quickstart.
+ *
+ * This is common IOPORT service for GPIO pin configuration and control in a
+ * standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices.
+ *
+ * Port pin control code is optimized for each platform, and should produce
+ * both compact and fast execution times when used with constant values.
+ *
+ * \section dependencies Dependencies
+ * This driver depends on the following modules:
+ * - \ref sysclk_group for clock speed and functions.
+ * @{
+ */
+
+/**
+ * \def IOPORT_CREATE_PIN(port, pin)
+ * \brief Create IOPORT pin number
+ *
+ * Create a IOPORT pin number for use with the IOPORT functions.
+ *
+ * \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen
+ *             architecture)
+ * \param pin IOPORT zero-based index of the I/O pin
+ */
+
+/** \brief IOPORT pin directions */
+enum ioport_direction {
+	IOPORT_DIR_INPUT,  /*!< IOPORT input direction */
+	IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */
+};
+
+/** \brief IOPORT levels */
+enum ioport_value {
+	IOPORT_PIN_LEVEL_LOW,  /*!< IOPORT pin value low */
+	IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */
+};
+
+#if MEGA_RF
+/** \brief IOPORT edge sense modes */
+enum ioport_sense {
+	IOPORT_SENSE_LEVEL,     /*!< IOPORT sense low level  */
+	IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+	IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
+	IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
+};
+#elif SAM && !SAM4L
+/** \brief IOPORT edge sense modes */
+enum ioport_sense {
+	IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+	IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
+	IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
+	IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level  */
+	IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level  */
+};
+#elif XMEGA
+enum ioport_sense {
+	IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+	IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
+	IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
+	IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */
+};
+#else
+enum ioport_sense {
+	IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+	IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
+	IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
+};
+#endif
+
+
+#if XMEGA
+# include "xmega/ioport.h"
+# if defined(IOPORT_XMEGA_COMPAT)
+#  include "xmega/ioport_compat.h"
+# endif
+#elif MEGA
+#  include "mega/ioport.h"
+#elif UC3
+# include "uc3/ioport.h"
+#elif SAM
+# if SAM4L
+#  include "sam/ioport_gpio.h"
+# elif (SAMD20 | SAMD21 | SAML21)
+#  include "sam0/ioport.h"
+# else
+#  include "sam/ioport_pio.h"
+# endif
+#endif
+
+/**
+ * \brief Initializes the IOPORT service, ready for use.
+ *
+ * This function must be called before using any other functions in the IOPORT
+ * service.
+ */
+static inline void ioport_init(void)
+{
+	arch_ioport_init();
+}
+
+/**
+ * \brief Enable an IOPORT pin, based on a pin created with \ref
+ * IOPORT_CREATE_PIN().
+ *
+ * \param pin  IOPORT pin to enable
+ */
+static inline void ioport_enable_pin(ioport_pin_t pin)
+{
+	arch_ioport_enable_pin(pin);
+}
+
+/**
+ * \brief Enable multiple pins in a single IOPORT port.
+ *
+ * \param port IOPORT port to enable
+ * \param mask Mask of pins within the port to enable
+ */
+static inline void ioport_enable_port(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_enable_port(port, mask);
+}
+
+/**
+ * \brief Disable IOPORT pin, based on a pin created with \ref
+ *        IOPORT_CREATE_PIN().
+ *
+ * \param pin IOPORT pin to disable
+ */
+static inline void ioport_disable_pin(ioport_pin_t pin)
+{
+	arch_ioport_disable_pin(pin);
+}
+
+/**
+ * \brief Disable multiple pins in a single IOPORT port.
+ *
+ * \param port IOPORT port to disable
+ * \param mask Pin mask of pins to disable
+ */
+static inline void ioport_disable_port(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_disable_port(port, mask);
+}
+
+/**
+ * \brief Set multiple pin modes in a single IOPORT port, such as pull-up,
+ * pull-down, etc. configuration.
+ *
+ * \param port IOPORT port to configure
+ * \param mask Pin mask of pins to configure
+ * \param mode Mode masks to configure for the specified pins (\ref
+ * ioport_modes)
+ */
+static inline void ioport_set_port_mode(ioport_port_t port,
+		ioport_port_mask_t mask, ioport_mode_t mode)
+{
+	arch_ioport_set_port_mode(port, mask, mode);
+}
+
+/**
+ * \brief Set pin mode for one single IOPORT pin.
+ *
+ * \param pin IOPORT pin to configure
+ * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)
+ */
+static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode)
+{
+	arch_ioport_set_pin_mode(pin, mode);
+}
+
+/**
+ * \brief Reset multiple pin modes in a specified IOPORT port to defaults.
+ *
+ * \param port IOPORT port to configure
+ * \param mask Mask of pins whose mode configuration is to be reset
+ */
+static inline void ioport_reset_port_mode(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_set_port_mode(port, mask, 0);
+}
+
+/**
+ * \brief Reset pin mode configuration for a single IOPORT pin
+ *
+ * \param pin IOPORT pin to configure
+ */
+static inline void ioport_reset_pin_mode(ioport_pin_t pin)
+{
+	arch_ioport_set_pin_mode(pin, 0);
+}
+
+/**
+ * \brief Set I/O direction for a group of pins in a single IOPORT.
+ *
+ * \param port IOPORT port to configure
+ * \param mask Pin mask of pins to configure
+ * \param dir Direction to set for the specified pins (\ref ioport_direction)
+ */
+static inline void ioport_set_port_dir(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_direction dir)
+{
+	arch_ioport_set_port_dir(port, mask, dir);
+}
+
+/**
+ * \brief Set direction for a single IOPORT pin.
+ *
+ * \param pin IOPORT pin to configure
+ * \param dir Direction to set for the specified pin (\ref ioport_direction)
+ */
+static inline void ioport_set_pin_dir(ioport_pin_t pin,
+		enum ioport_direction dir)
+{
+	arch_ioport_set_pin_dir(pin, dir);
+}
+
+/**
+ * \brief Set an IOPORT pin to a specified logical value.
+ *
+ * \param pin IOPORT pin to configure
+ * \param level Logical value of the pin
+ */
+static inline void ioport_set_pin_level(ioport_pin_t pin, bool level)
+{
+	arch_ioport_set_pin_level(pin, level);
+}
+
+/**
+ * \brief Set a group of IOPORT pins in a single port to a specified logical
+ * value.
+ *
+ * \param port IOPORT port to write to
+ * \param mask Pin mask of pins to modify
+ * \param level Level of the pins to be modified
+ */
+static inline void ioport_set_port_level(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_value level)
+{
+	arch_ioport_set_port_level(port, mask, level);
+}
+
+/**
+ * \brief Get current value of an IOPORT pin, which has been configured as an
+ * input.
+ *
+ * \param pin IOPORT pin to read
+ * \return Current logical value of the specified pin
+ */
+static inline bool ioport_get_pin_level(ioport_pin_t pin)
+{
+	return arch_ioport_get_pin_level(pin);
+}
+
+/**
+ * \brief Get current value of several IOPORT pins in a single port, which have
+ * been configured as an inputs.
+ *
+ * \param port IOPORT port to read
+ * \param mask Pin mask of pins to read
+ * \return Logical levels of the specified pins from the read port, returned as
+ * a mask.
+ */
+static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port,
+		ioport_port_mask_t mask)
+{
+	return arch_ioport_get_port_level(port, mask);
+}
+
+/**
+ * \brief Toggle the value of an IOPORT pin, which has previously configured as
+ * an output.
+ *
+ * \param pin IOPORT pin to toggle
+ */
+static inline void ioport_toggle_pin_level(ioport_pin_t pin)
+{
+	arch_ioport_toggle_pin_level(pin);
+}
+
+/**
+ * \brief Toggle the values of several IOPORT pins located in a single port.
+ *
+ * \param port IOPORT port to modify
+ * \param mask Pin mask of pins to toggle
+ */
+static inline void ioport_toggle_port_level(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_toggle_port_level(port, mask);
+}
+
+/**
+ * \brief Set the pin sense mode of a single IOPORT pin.
+ *
+ * \param pin IOPORT pin to configure
+ * \param pin_sense Edge to sense for the pin (\ref ioport_sense)
+ */
+static inline void ioport_set_pin_sense_mode(ioport_pin_t pin,
+		enum ioport_sense pin_sense)
+{
+	arch_ioport_set_pin_sense_mode(pin, pin_sense);
+}
+
+/**
+ * \brief Set the pin sense mode of a multiple IOPORT pins on a single port.
+ *
+ * \param port IOPORT port to configure
+ * \param mask Bitmask if pins whose edge sense is to be configured
+ * \param pin_sense Edge to sense for the pins (\ref ioport_sense)
+ */
+static inline void ioport_set_port_sense_mode(ioport_port_t port,
+		ioport_port_mask_t mask,
+		enum ioport_sense pin_sense)
+{
+	arch_ioport_set_port_sense_mode(port, mask, pin_sense);
+}
+
+/**
+ * \brief Convert a pin ID into a its port ID.
+ *
+ * \param pin IOPORT pin ID to convert
+ * \retval Port ID for the given pin ID
+ */
+static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin)
+{
+	return arch_ioport_pin_to_port_id(pin);
+}
+
+/**
+ * \brief Convert a pin ID into a bitmask mask for the given pin on its port.
+ *
+ * \param pin IOPORT pin ID to convert
+ * \retval Bitmask with a bit set that corresponds to the given pin ID in its port
+ */
+static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)
+{
+	return arch_ioport_pin_to_mask(pin);
+}
+
+/** @} */
+
+/**
+ * \page ioport_quickstart Quick start guide for the common IOPORT service
+ *
+ * This is the quick start guide for the \ref ioport_group, with
+ * step-by-step instructions on how to configure and use the service in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section ioport_quickstart_basic Basic use case
+ * In this use case we will configure one IO pin for button input and one for
+ * LED control. Then it will read the button state and output it on the LED.
+ *
+ * \section ioport_quickstart_basic_setup Setup steps
+ *
+ * \subsection ioport_quickstart_basic_setup_code Example code
+ * \code
+	 #define MY_LED    IOPORT_CREATE_PIN(PORTA, 5)
+	 #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
+
+	 ioport_init();
+
+	 ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT);
+	 ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT);
+	 ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP);
+\endcode
+ *
+ * \subsection ioport_quickstart_basic_setup_flow Workflow
+ * -# It's useful to give the GPIOs symbolic names and this can be done with
+ *    the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a
+ *    button.
+ *   - \code
+	#define MY_LED    IOPORT_CREATE_PIN(PORTA, 5)
+	#define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
+\endcode
+ *   - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names
+ *           differ between architectures:
+ *     - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions
+ *              PORTA, PORTB ...
+ *     - UC3: Most convenient to pick up the device header file pin definition
+ *            and us it directly. E.g.: AVR32_PIN_PB06
+ *     - SAM: Most convenient to pick up the device header file pin definition
+ *            and us it directly. E.g.: PIO_PA5_IDX<br>
+ *            \ref IOPORT_CREATE_PIN can also be used with port definitions
+ *            PIOA, PIOB ...
+ * -# Initialize the ioport service. This typically enables the IO module if
+ *    needed.
+ *   - \code ioport_init(); \endcode
+ * -# Set the LED GPIO as output:
+ *   - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode
+ * -# Set the button GPIO as input:
+ *   - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode
+ * -# Enable pull-up for the button GPIO:
+ *   - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode
+ *
+ * \section ioport_quickstart_basic_usage Usage steps
+ *
+ * \subsection ioport_quickstart_basic_usage_code Example code
+ * \code
+	 bool value;
+
+	 value = ioport_get_pin_level(MY_BUTTON);
+	 ioport_set_pin_level(MY_LED, value);
+\endcode
+ *
+ * \subsection ioport_quickstart_basic_usage_flow Workflow
+ * -# Define a boolean variable for state storage:
+ *   - \code bool value; \endcode
+ * -# Read out the button level into variable value:
+ *   - \code value = ioport_get_pin_level(MY_BUTTON); \endcode
+ * -# Set the LED to read out value from the button:
+ *   - \code ioport_set_pin_level(MY_LED, value); \endcode
+ *
+ * \section ioport_quickstart_advanced Advanced use cases
+ * - \subpage ioport_quickstart_use_case_1 : Port access
+ */
+
+/**
+ * \page ioport_quickstart_use_case_1 Advanced use case doing port access
+ *
+ * In this case we will read out the pins from one whole port and write the
+ * read value to another port.
+ *
+ * \section ioport_quickstart_use_case_1_setup Setup steps
+ *
+ * \subsection ioport_quickstart_use_case_1_setup_code Example code
+ * \code
+	 #define IN_PORT  IOPORT_PORTA
+	 #define OUT_PORT IOPORT_PORTB
+	 #define MASK     0x00000060
+
+	 ioport_init();
+
+	 ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT);
+	 ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT);
+\endcode
+ *
+ * \subsection ioport_quickstart_basic_setup_flow Workflow
+ * -# It's useful to give the ports symbolic names:
+ *   - \code
+	#define IN_PORT  IOPORT_PORTA
+	#define OUT_PORT IOPORT_PORTB
+\endcode
+ *   - \note The port names differ between architectures:
+ *     - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA,
+ *              IOPORT_PORTB ...
+ *     - UC3: Use the index value of the different IO blocks: 0, 1 ...
+ *     - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB
+ *            ...
+ * -# Also useful to define a mask for the bits to work with:
+ *     - \code #define MASK     0x00000060 \endcode
+ * -# Initialize the ioport service. This typically enables the IO module if
+ *    needed.
+ *   - \code ioport_init(); \endcode
+ * -# Set one of the ports as input:
+ *   - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode
+ * -# Set the other port as output:
+ *   - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode
+ *
+ * \section ioport_quickstart_basic_usage Usage steps
+ *
+ * \subsection ioport_quickstart_basic_usage_code Example code
+ * \code
+	 ioport_port_mask_t value;
+
+	 value = ioport_get_port_level(IN_PORT, MASK);
+	 ioport_set_port_level(OUT_PORT, MASK, value);
+\endcode
+ *
+ * \subsection ioport_quickstart_basic_usage_flow Workflow
+ * -# Define a variable for port date storage:
+ *   - \code ioport_port_mask_t value; \endcode
+ * -# Read out from one port:
+ *   - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode
+ * -# Put the read data out on the other port:
+ *   - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IOPORT_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_gpio.h b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_gpio.h
new file mode 100644
index 0000000000..6f3cbd7f7b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_gpio.h
@@ -0,0 +1,307 @@
+/**
+ * \file
+ *
+ * \brief SAM architecture specific IOPORT service implementation header file.
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef IOPORT_SAM_H
+#define IOPORT_SAM_H
+
+#include <sysclk.h>
+
+#define IOPORT_CREATE_PIN(port, pin) ((port) * 32 + (pin))
+
+// Aliases
+#define IOPORT_GPIOA     0
+#define IOPORT_GPIOB     1
+#define IOPORT_GPIOC     2
+#define IOPORT_GPIOD     3
+#define IOPORT_GPIOE     4
+#define IOPORT_GPIOF     5
+
+/**
+ * \weakgroup ioport_group
+ * \section ioport_modes IOPORT Modes
+ *
+ * For details on these please see the device datasheet.
+ *
+ * @{
+ */
+
+/** \name IOPORT Mode bit definitions */
+/** @{ */
+#define IOPORT_MODE_MUX_MASK            (7 << 0) /*!< MUX bits mask */
+#define IOPORT_MODE_MUX_BIT0            (1 << 0) /*!< MUX BIT0 mask */
+#define IOPORT_MODE_MUX_BIT1            (1 << 1) /*!< MUX BIT1 mask */
+#define IOPORT_MODE_MUX_A               (0 << 0) /*!< MUX function A */
+#define IOPORT_MODE_MUX_B               (1 << 0) /*!< MUX function B */
+#define IOPORT_MODE_MUX_C               (2 << 0) /*!< MUX function C */
+#define IOPORT_MODE_MUX_D               (3 << 0) /*!< MUX function D */
+
+#define IOPORT_MODE_MUX_BIT2            (1 << 2) /*!< MUX BIT2 mask */
+#define IOPORT_MODE_MUX_E               (4 << 0) /*!< MUX function E */
+#define IOPORT_MODE_MUX_F               (5 << 0) /*!< MUX function F */
+#define IOPORT_MODE_MUX_G               (6 << 0) /*!< MUX function G */
+#define IOPORT_MODE_MUX_H               (7 << 0) /*!< MUX function H */
+
+#define IOPORT_MODE_PULLUP              (1 << 3) /*!< Pull-up */
+#define IOPORT_MODE_PULLDOWN            (1 << 4) /*!< Pull-down */
+#define IOPORT_MODE_GLITCH_FILTER       (1 << 6) /*!< Glitch filter */
+#define IOPORT_MODE_DRIVE_STRENGTH      (1 << 7) /*!< Extra drive strength */
+/** @} */
+
+/** @} */
+
+typedef uint32_t ioport_mode_t;
+typedef uint32_t ioport_pin_t;
+typedef uint32_t ioport_port_t;
+typedef uint32_t ioport_port_mask_t;
+
+__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)
+{
+	return pin >> 5;
+}
+
+__always_inline static volatile GpioPort *arch_ioport_port_to_base(
+		ioport_port_t port)
+{
+	return (volatile GpioPort *)(GPIO_ADDR
+		+ port * sizeof(GpioPort));
+}
+
+__always_inline static volatile GpioPort *arch_ioport_pin_to_base(ioport_pin_t pin)
+{
+	return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
+}
+
+__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)
+{
+	return 1U << (pin & 0x1F);
+}
+
+__always_inline static void arch_ioport_init(void)
+{
+	sysclk_enable_peripheral_clock(GPIO);
+}
+
+__always_inline static void arch_ioport_enable_port(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_port_to_base(port)->GPIO_GPERS = mask;
+}
+
+__always_inline static void arch_ioport_disable_port(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_port_to_base(port)->GPIO_GPERC = mask;
+}
+
+__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin)
+{
+	arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin));
+}
+
+__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin)
+{
+	arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin));
+}
+
+__always_inline static void arch_ioport_set_port_mode(ioport_port_t port,
+		ioport_port_mask_t mask, ioport_mode_t mode)
+{
+	volatile GpioPort *base = arch_ioport_port_to_base(port);
+
+	if (mode & IOPORT_MODE_PULLUP) {
+		base->GPIO_PUERS = mask;
+	} else {
+		base->GPIO_PUERC = mask;
+	}
+
+#ifdef IOPORT_MODE_PULLDOWN
+	if (mode & IOPORT_MODE_PULLDOWN) {
+		base->GPIO_PDERS = mask;
+	} else {
+		base->GPIO_PDERC = mask;
+	}
+#endif
+
+	if (mode & IOPORT_MODE_GLITCH_FILTER) {
+		base->GPIO_GFERS = mask;
+	} else {
+		base->GPIO_GFERC = mask;
+	}
+
+#ifdef IOPORT_MODE_DRIVE_STRENGTH
+	if (mode & IOPORT_MODE_DRIVE_STRENGTH) {
+		base->GPIO_ODCR0S = mask;
+	} else {
+		base->GPIO_ODCR0C = mask;
+	}
+#endif
+
+	if (mode & IOPORT_MODE_MUX_BIT0) {
+		base->GPIO_PMR0S = mask;
+	} else {
+		base->GPIO_PMR0C = mask;
+	}
+
+	if (mode & IOPORT_MODE_MUX_BIT1) {
+		base->GPIO_PMR1S = mask;
+	} else {
+		base->GPIO_PMR1C = mask;
+	}
+
+#ifdef IOPORT_MODE_MUX_BIT2
+	if (mode & IOPORT_MODE_MUX_BIT2) {
+		base->GPIO_PMR2S = mask;
+	} else {
+		base->GPIO_PMR2C = mask;
+	}
+#endif
+}
+
+__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,
+		ioport_mode_t mode)
+{
+	arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin), mode);
+}
+
+__always_inline static void arch_ioport_set_port_dir(ioport_port_t port,
+		ioport_port_mask_t mask, unsigned char group_direction)
+{
+	if (group_direction == IOPORT_DIR_OUTPUT) {
+		arch_ioport_port_to_base(port)->GPIO_ODERS = mask;
+		// Always disable the Schmitt trigger for output pins.
+		arch_ioport_port_to_base(port)->GPIO_STERC = mask;
+	} else if (group_direction == IOPORT_DIR_INPUT) {
+		arch_ioport_port_to_base(port)->GPIO_ODERC = mask;
+		// Always enable the Schmitt trigger for input pins.
+		arch_ioport_port_to_base(port)->GPIO_STERS = mask;
+	}
+}
+
+__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,
+		enum ioport_direction dir)
+{
+	if (dir == IOPORT_DIR_OUTPUT) {
+		arch_ioport_pin_to_base(pin)->GPIO_ODERS = arch_ioport_pin_to_mask(pin);
+		// Always disable the Schmitt trigger for output pins.
+		arch_ioport_pin_to_base(pin)->GPIO_STERC = arch_ioport_pin_to_mask(pin);
+	} else if (dir == IOPORT_DIR_INPUT) {
+		arch_ioport_pin_to_base(pin)->GPIO_ODERC = arch_ioport_pin_to_mask(pin);
+		// Always enable the Schmitt trigger for input pins.
+		arch_ioport_pin_to_base(pin)->GPIO_STERS = arch_ioport_pin_to_mask(pin);
+	}
+}
+
+__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin,
+		bool level)
+{
+	if (level) {
+		arch_ioport_pin_to_base(pin)->GPIO_OVRS = arch_ioport_pin_to_mask(pin);
+	} else {
+		arch_ioport_pin_to_base(pin)->GPIO_OVRC = arch_ioport_pin_to_mask(pin);
+	}
+}
+
+__always_inline static void arch_ioport_set_port_level(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_value level)
+{
+	volatile GpioPort *base = arch_ioport_port_to_base(port);
+	if (level){
+		base->GPIO_OVRS = mask;
+	} else{
+		base->GPIO_OVRC = mask;
+	}
+}
+
+__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)
+{
+	return arch_ioport_pin_to_base(pin)->GPIO_PVR & arch_ioport_pin_to_mask(pin);
+}
+
+__always_inline static ioport_port_mask_t arch_ioport_get_port_level(
+		ioport_port_t port, ioport_port_mask_t mask)
+{
+	return arch_ioport_port_to_base(port)->GPIO_PVR & mask;
+}
+
+__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)
+{
+	arch_ioport_pin_to_base(pin)->GPIO_OVRT = arch_ioport_pin_to_mask(pin);
+}
+
+__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_port_to_base(port)->GPIO_OVRT = mask;
+}
+
+__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_sense pin_sense)
+{
+	volatile GpioPort *base = arch_ioport_port_to_base(port);
+
+	if (pin_sense & 0x01) {
+		base->GPIO_IMR0S = mask;
+	} else {
+		base->GPIO_IMR0C = mask;
+	}
+
+	if (pin_sense & 0x02) {
+		base->GPIO_IMR1S = mask;
+	} else {
+		base->GPIO_IMR1C = mask;
+	}
+}
+
+__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,
+		enum ioport_sense pin_sense)
+{
+	arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin), pin_sense);
+}
+
+#endif /* IOPORT_SAM_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_pio.h b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_pio.h
new file mode 100644
index 0000000000..f3005991df
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_pio.h
@@ -0,0 +1,383 @@
+/**
+ * \file
+ *
+ * \brief SAM architecture specific IOPORT service implementation header file.
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef IOPORT_SAM_H
+#define IOPORT_SAM_H
+
+#include <sysclk.h>
+
+#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 32 + (pin))
+#define IOPORT_BASE_ADDRESS (uintptr_t)PIOA
+#define IOPORT_PIO_OFFSET   ((uintptr_t)PIOB - (uintptr_t)PIOA)
+
+#define IOPORT_PIOA     0
+#define IOPORT_PIOB     1
+#define IOPORT_PIOC     2
+#define IOPORT_PIOD     3
+#define IOPORT_PIOE     4
+#define IOPORT_PIOF     5
+
+/**
+ * \weakgroup ioport_group
+ * \section ioport_modes IOPORT Modes
+ *
+ * For details on these please see the SAM Manual.
+ *
+ * @{
+ */
+
+/** \name IOPORT Mode bit definitions */
+/** @{ */
+#define IOPORT_MODE_MUX_MASK            (0x7 << 0) /*!< MUX bits mask */
+#define IOPORT_MODE_MUX_BIT0            (  1 << 0) /*!< MUX BIT0 mask */
+
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70
+#define IOPORT_MODE_MUX_BIT1            (  1 << 1) /*!< MUX BIT1 mask */
+#endif
+
+#define IOPORT_MODE_MUX_A               (  0 << 0) /*!< MUX function A */
+#define IOPORT_MODE_MUX_B               (  1 << 0) /*!< MUX function B */
+
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70
+#define IOPORT_MODE_MUX_C               (  2 << 0) /*!< MUX function C */
+#define IOPORT_MODE_MUX_D               (  3 << 0) /*!< MUX function D */
+#endif
+
+#define IOPORT_MODE_PULLUP              (  1 << 3) /*!< Pull-up */
+
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70
+#define IOPORT_MODE_PULLDOWN            (  1 << 4) /*!< Pull-down */
+#endif
+
+#define IOPORT_MODE_OPEN_DRAIN          (  1 << 5) /*!< Open drain */
+
+#define IOPORT_MODE_GLITCH_FILTER       (  1 << 6) /*!< Glitch filter */
+#define IOPORT_MODE_DEBOUNCE            (  1 << 7) /*!< Input debounce */
+/** @} */
+
+/** @} */
+
+typedef uint32_t ioport_mode_t;
+typedef uint32_t ioport_pin_t;
+typedef uint32_t ioport_port_t;
+typedef uint32_t ioport_port_mask_t;
+
+__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)
+{
+	return pin >> 5;
+}
+
+__always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port)
+{
+#if (SAM4C || SAM4CM || SAM4CP)
+	if (port == IOPORT_PIOC) {
+		return (Pio *)(uintptr_t)PIOC;
+#  ifdef ID_PIOD
+	} else if (port == IOPORT_PIOD) {
+		return (Pio *)(uintptr_t)PIOD;
+#  endif
+	} else {
+		return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +
+		       (IOPORT_PIO_OFFSET * port));
+	}
+#else
+	return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +
+	       (IOPORT_PIO_OFFSET * port));
+#endif
+}
+
+__always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin)
+{
+	return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
+}
+
+__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)
+{
+	return 1U << (pin & 0x1F);
+}
+
+__always_inline static void arch_ioport_init(void)
+{
+#ifdef ID_PIOA
+	sysclk_enable_peripheral_clock(ID_PIOA);
+#endif
+#ifdef ID_PIOB
+	sysclk_enable_peripheral_clock(ID_PIOB);
+#endif
+#ifdef ID_PIOC
+	sysclk_enable_peripheral_clock(ID_PIOC);
+#endif
+#ifdef ID_PIOD
+	sysclk_enable_peripheral_clock(ID_PIOD);
+#endif
+#ifdef ID_PIOE
+	sysclk_enable_peripheral_clock(ID_PIOE);
+#endif
+#ifdef ID_PIOF
+	sysclk_enable_peripheral_clock(ID_PIOF);
+#endif
+}
+
+__always_inline static void arch_ioport_enable_port(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_port_to_base(port)->PIO_PER = mask;
+}
+
+__always_inline static void arch_ioport_disable_port(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_port_to_base(port)->PIO_PDR = mask;
+}
+
+__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin)
+{
+	arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin));
+}
+
+__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin)
+{
+	arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin));
+}
+
+__always_inline static void arch_ioport_set_port_mode(ioport_port_t port,
+		ioport_port_mask_t mask, ioport_mode_t mode)
+{
+	Pio *base = arch_ioport_port_to_base(port);
+
+	if (mode & IOPORT_MODE_PULLUP) {
+		base->PIO_PUER = mask;
+	} else {
+		base->PIO_PUDR = mask;
+	}
+
+#if defined(IOPORT_MODE_PULLDOWN)
+	if (mode & IOPORT_MODE_PULLDOWN) {
+		base->PIO_PPDER = mask;
+	} else {
+		base->PIO_PPDDR = mask;
+	}
+#endif
+
+	if (mode & IOPORT_MODE_OPEN_DRAIN) {
+		base->PIO_MDER = mask;
+	} else {
+		base->PIO_MDDR = mask;
+	}
+
+	if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) {
+		base->PIO_IFER = mask;
+	} else {
+		base->PIO_IFDR = mask;
+	}
+
+	if (mode & IOPORT_MODE_DEBOUNCE) {
+#if SAM3U || SAM3XA
+		base->PIO_DIFSR = mask;
+#else
+		base->PIO_IFSCER = mask;
+#endif
+	} else {
+#if SAM3U || SAM3XA
+		base->PIO_SCIFSR = mask;
+#else
+		base->PIO_IFSCDR = mask;
+#endif
+	}
+
+#if !defined(IOPORT_MODE_MUX_BIT1)
+	if (mode & IOPORT_MODE_MUX_BIT0) {
+		base->PIO_ABSR |= mask;
+	} else {
+		base->PIO_ABSR &= ~mask;
+	}
+#else
+	if (mode & IOPORT_MODE_MUX_BIT0) {
+		base->PIO_ABCDSR[0] |= mask;
+	} else {
+		base->PIO_ABCDSR[0] &= ~mask;
+	}
+
+	if (mode & IOPORT_MODE_MUX_BIT1) {
+		base->PIO_ABCDSR[1] |= mask;
+	} else {
+		base->PIO_ABCDSR[1] &= ~mask;
+	}
+#endif
+}
+
+__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,
+		ioport_mode_t mode)
+{
+	arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin), mode);
+}
+
+__always_inline static void arch_ioport_set_port_dir(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_direction group_direction)
+{
+	Pio *base = arch_ioport_port_to_base(port);
+
+	if (group_direction == IOPORT_DIR_OUTPUT) {
+		base->PIO_OER = mask;
+	} else if (group_direction == IOPORT_DIR_INPUT) {
+		base->PIO_ODR = mask;
+	}
+
+	base->PIO_OWER = mask;
+}
+
+__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,
+		enum ioport_direction dir)
+{
+	Pio *base = arch_ioport_pin_to_base(pin);
+
+	if (dir == IOPORT_DIR_OUTPUT) {
+		base->PIO_OER = arch_ioport_pin_to_mask(pin);
+	} else if (dir == IOPORT_DIR_INPUT) {
+		base->PIO_ODR = arch_ioport_pin_to_mask(pin);
+	}
+
+	base->PIO_OWER = arch_ioport_pin_to_mask(pin);
+}
+
+__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin,
+		bool level)
+{
+	Pio *base = arch_ioport_pin_to_base(pin);
+
+	if (level) {
+		base->PIO_SODR = arch_ioport_pin_to_mask(pin);
+	} else {
+		base->PIO_CODR = arch_ioport_pin_to_mask(pin);
+	}
+}
+
+__always_inline static void arch_ioport_set_port_level(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_value level)
+{
+	Pio *base = arch_ioport_port_to_base(port);
+
+	if (level){
+		base->PIO_SODR = mask;
+	} else {
+		base->PIO_CODR = mask;
+	}
+}
+
+__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)
+{
+	return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin);
+}
+
+__always_inline static ioport_port_mask_t arch_ioport_get_port_level(
+		ioport_port_t port, ioport_port_mask_t mask)
+{
+	return arch_ioport_port_to_base(port)->PIO_PDSR & mask;
+}
+
+__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)
+{
+	Pio *port = arch_ioport_pin_to_base(pin);
+	ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin);
+
+	if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) {
+		port->PIO_CODR = mask;
+	} else {
+		port->PIO_SODR = mask;
+	}
+}
+
+__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_port_to_base(port)->PIO_ODSR ^= mask;
+}
+
+__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_sense pin_sense)
+{
+	Pio *base = arch_ioport_port_to_base(port);
+	/*   AIMMR    ELSR    FRLHSR
+	 *       0       X         X    IOPORT_SENSE_BOTHEDGES (Default)
+	 *       1       0         0    IOPORT_SENSE_FALLING
+	 *       1       0         1    IOPORT_SENSE_RISING
+	 *       1       1         0    IOPORT_SENSE_LEVEL_LOW
+	 *       1       1         1    IOPORT_SENSE_LEVEL_HIGH
+	 */
+	switch(pin_sense) {
+	case IOPORT_SENSE_LEVEL_LOW:
+		base->PIO_LSR = mask;
+		base->PIO_FELLSR = mask;
+		break;
+	case IOPORT_SENSE_LEVEL_HIGH:
+		base->PIO_LSR = mask;
+		base->PIO_REHLSR = mask;
+		break;
+	case IOPORT_SENSE_FALLING:
+		base->PIO_ESR = mask;
+		base->PIO_FELLSR = mask;
+		break;
+	case IOPORT_SENSE_RISING:
+		base->PIO_ESR = mask;
+		base->PIO_REHLSR = mask;
+		break;
+	default:
+		base->PIO_AIMDR = mask;
+		return;
+	}
+	base->PIO_AIMER = mask;
+}
+
+__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,
+		enum ioport_sense pin_sense)
+{
+	arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin), pin_sense);
+}
+
+#endif /* IOPORT_SAM_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam0/ioport.h b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam0/ioport.h
new file mode 100644
index 0000000000..07d44ad7d4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam0/ioport.h
@@ -0,0 +1,305 @@
+/**
+ * \file
+ *
+ * \brief SAM architecture specific IOPORT service implementation header file.
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef IOPORT_SAM0_H
+#define IOPORT_SAM0_H
+
+#include <compiler.h>
+
+#define IOPORT_CREATE_PIN(port, pin) ((port) * 32 + (pin))
+
+// Aliases
+#if (PORT_GROUPS > 0)
+#  define IOPORT_PORTA     0
+#endif
+#if (PORT_GROUPS > 1)
+#  define IOPORT_PORTB     1
+#endif
+#if (PORT_GROUPS > 2)
+#  define IOPORT_PORTC     2
+#endif
+#if (PORT_GROUPS > 3)
+#  define IOPORT_PORTD     3
+#endif
+
+/**
+ * \weakgroup ioport_group
+ * \section ioport_modes IOPORT Modes
+ *
+ * For details on these please see the device datasheet.
+ *
+ * @{
+ */
+
+/** \name IOPORT Mode bit definitions */
+/** @{ */
+#define IOPORT_MODE_MUX_MASK            (0xF << 0) /*!< MUX bits mask */
+#define IOPORT_MODE_MUX_BIT0            (1 << 0) /*!< MUX BIT0 mask */
+#define IOPORT_MODE_MUX_BIT1            (1 << 1) /*!< MUX BIT1 mask */
+#define IOPORT_MODE_MUX_BIT2            (1 << 2) /*!< MUX BIT2 mask */
+#define IOPORT_MODE_MUX_BIT3            (1 << 3) /*!< MUX BIT3 mask */
+#define IOPORT_MODE_MUX_A               (0 << 0) /*!< MUX function A */
+#define IOPORT_MODE_MUX_B               (1 << 0) /*!< MUX function B */
+#define IOPORT_MODE_MUX_C               (2 << 0) /*!< MUX function C */
+#define IOPORT_MODE_MUX_D               (3 << 0) /*!< MUX function D */
+#define IOPORT_MODE_MUX_E               (4 << 0) /*!< MUX function E */
+#define IOPORT_MODE_MUX_F               (5 << 0) /*!< MUX function F */
+#define IOPORT_MODE_MUX_G               (6 << 0) /*!< MUX function G */
+#define IOPORT_MODE_MUX_H               (7 << 0) /*!< MUX function H */
+
+#define IOPORT_MODE_PULLUP              (1 << 4) /*!< Pull-up */
+#define IOPORT_MODE_PULLDOWN            (1 << 5) /*!< Pull-down */
+#define IOPORT_MODE_OPEN_DRAIN          (1 << 6) /*!< Open Drain */
+#define IOPORT_MODE_DRIVE_STRENGTH      (1 << 7) /*!< Extra drive strength */
+/** @} */
+
+/** @} */
+
+typedef uint32_t ioport_mode_t;
+typedef uint32_t ioport_pin_t;
+typedef uint32_t ioport_port_t;
+typedef uint32_t ioport_port_mask_t;
+
+inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)
+{
+	return pin >> 5;
+}
+
+inline static PortGroup *arch_ioport_port_to_base(
+		ioport_port_t port)
+{
+	return &PORT->Group[port];
+}
+
+inline static PortGroup *arch_ioport_pin_to_base(ioport_pin_t pin)
+{
+	return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
+}
+
+inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)
+{
+	return 1U << (pin & 0x1F);
+}
+
+inline static void arch_ioport_init(void)
+{
+	/* No implementation for SAM0 */
+}
+
+
+inline static void arch_ioport_enable_port(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	volatile PortGroup *base = arch_ioport_port_to_base(port);
+
+	for (uint32_t i = 0; i < 32; i++) {
+		if (mask & (1 << i)) {
+			base->PINCFG[i].reg &= ~PORT_PINCFG_PMUXEN;
+		}
+	}
+}
+
+inline static void arch_ioport_disable_port(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	volatile PortGroup *base = arch_ioport_port_to_base(port);
+
+	for (uint32_t i = 0; i < 32; i++) {
+		if (mask & (1 << i)) {
+			base->PINCFG[i].reg |= PORT_PINCFG_PMUXEN;
+		}
+	}
+}
+
+inline static void arch_ioport_enable_pin(ioport_pin_t pin)
+{
+	arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin));
+}
+
+inline static void arch_ioport_disable_pin(ioport_pin_t pin)
+{
+	arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin));
+}
+
+inline static void arch_ioport_set_port_mode(ioport_port_t port,
+		ioport_port_mask_t mask, ioport_mode_t mode)
+{
+	PortGroup *base = arch_ioport_port_to_base(port);
+
+	uint32_t config_mask = 0;
+	uint32_t config_mux  = 0;
+
+	config_mask |= PORT_WRCONFIG_INEN;
+
+	if ((mode & IOPORT_MODE_PULLDOWN) || (mode & IOPORT_MODE_PULLUP)) {
+		config_mask |= PORT_WRCONFIG_PULLEN;
+	}
+
+#ifdef PORT_WRCONFIG_ODRAIN
+	if (mode & IOPORT_MODE_OPEN_DRAIN) {
+		config_mask |= PORT_WRCONFIG_ODRAIN;
+	}
+#endif
+
+	if (mode & IOPORT_MODE_DRIVE_STRENGTH) {
+		config_mask |= PORT_WRCONFIG_DRVSTR;
+	}
+
+	config_mux = (mode & IOPORT_MODE_MUX_MASK) << PORT_WRCONFIG_PMUX_Pos;
+
+	uint32_t lower_pin_mask = (mask & 0xFFFF);
+	uint32_t upper_pin_mask = (mask >> 16);
+
+	base->WRCONFIG.reg =
+			(lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			config_mask | config_mux |
+			PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+
+	base->WRCONFIG.reg =
+			(upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			config_mask | config_mux |
+			PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+			PORT_WRCONFIG_HWSEL;
+
+	if (mode & IOPORT_MODE_PULLDOWN) {
+		base->OUTCLR.reg = mask;
+	}
+	else if (mode & IOPORT_MODE_PULLUP) {
+		base->OUTSET.reg = mask;
+	}
+}
+
+inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,
+		ioport_mode_t mode)
+{
+	arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin), mode);
+}
+
+inline static void arch_ioport_set_port_dir(ioport_port_t port,
+		ioport_port_mask_t mask, unsigned char dir)
+{
+	if (dir == IOPORT_DIR_OUTPUT) {
+		arch_ioport_port_to_base(port)->DIRSET.reg = mask;
+	} else if (dir == IOPORT_DIR_INPUT) {
+		arch_ioport_port_to_base(port)->DIRCLR.reg = mask;
+	}
+}
+
+inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,
+		enum ioport_direction dir)
+{
+	PortGroup *base = arch_ioport_pin_to_base(pin);
+
+	if (dir == IOPORT_DIR_OUTPUT) {
+		base->DIRSET.reg = arch_ioport_pin_to_mask(pin);
+	} else if (dir == IOPORT_DIR_INPUT) {
+		base->DIRCLR.reg = arch_ioport_pin_to_mask(pin);
+	}
+
+	base->PINCFG[pin].reg |= PORT_PINCFG_INEN;
+}
+
+inline static void arch_ioport_set_pin_level(ioport_pin_t pin,
+		bool level)
+{
+	if (level) {
+		arch_ioport_pin_to_base(pin)->OUTSET.reg = arch_ioport_pin_to_mask(pin);
+	} else {
+		arch_ioport_pin_to_base(pin)->OUTCLR.reg = arch_ioport_pin_to_mask(pin);
+	}
+}
+
+inline static void arch_ioport_set_port_level(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_value level)
+{
+	volatile PortGroup *base = arch_ioport_port_to_base(port);
+
+	if (level){
+		base->OUTSET.reg = mask;
+	} else {
+		base->OUTCLR.reg = mask;
+	}
+}
+
+inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)
+{
+	return arch_ioport_pin_to_base(pin)->IN.reg & arch_ioport_pin_to_mask(pin);
+}
+
+inline static ioport_port_mask_t arch_ioport_get_port_level(
+		ioport_port_t port, ioport_port_mask_t mask)
+{
+	return arch_ioport_port_to_base(port)->IN.reg & mask;
+}
+
+inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)
+{
+	arch_ioport_pin_to_base(pin)->OUTTGL.reg = arch_ioport_pin_to_mask(pin);
+}
+
+inline static void arch_ioport_toggle_port_level(ioport_port_t port,
+		ioport_port_mask_t mask)
+{
+	arch_ioport_port_to_base(port)->OUTTGL.reg = mask;
+}
+
+inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,
+		ioport_port_mask_t mask, enum ioport_sense pin_sense)
+{
+	// TODO
+	Assert(false);
+}
+
+inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,
+		enum ioport_sense pin_sense)
+{
+	arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
+			arch_ioport_pin_to_mask(pin), pin_sense);
+}
+
+#endif /* IOPORT_SAM0_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/flip_protocol.h b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/flip_protocol.h
new file mode 100644
index 0000000000..64a49b985d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/flip_protocol.h
@@ -0,0 +1,253 @@
+/**
+ * \file
+ *
+ * \brief FLIP protocol definitions.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _FLIP_PROTOCOL_H_
+#define _FLIP_PROTOCOL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup flip_protocol Atmel FLIP Protocol definitions
+ *
+ * To perform firmware upgrade, Atmel has developed an application called "FLIP"
+ * This software is a flexible application which lets you program and
+ * configure Atmel's microcontroller devices in their final environment
+ * without needing any dedicated hardware.
+ * @{
+ */
+
+//! \defgroup FLIP Protocol versions
+//@{
+#define  FLIP_PROTOCOL_VERSION_2     2 // Used by UC3 parts and Xmega parts
+#define  FLIP_PROTOCOL_VERSION_1     1 // Used by Mega
+#define  FLIP_PROTOCOL_VERSION_0     0 // Used by C51 parts
+//@}
+
+
+/**
+ * \defgroup flip_pv1 Definitions for FLIP Protocol version 1
+ *
+ * Note: Used by Mega parts.
+ *
+ * @{
+ */
+
+COMPILER_PACK_SET(1)
+/**
+ * \brief FLIP message structure
+ */
+typedef struct {
+	uint8_t cmd_id;
+	uint8_t arg[5];
+} flip_msg_v1_t;
+COMPILER_PACK_RESET()
+
+//! Size of buffer used by FLIP to receive or send data
+#define  FLIP_V1_BUF_TRANS_SIZE  1024
+
+//! \name FLIP commands
+//@{
+#define  FLIP_V1_CMD_PROG_START            0x01
+#define  FLIP_V1_CMD_READ                  0x03
+#define  FLIP_V1_CMD_WRITE                 0x04
+#define  FLIP_V1_CMD_READ_ID               0x05
+#define  FLIP_V1_CMD_CHANGE_BASE_ADDR      0x06
+
+//! \name FLIP_V1_CMD_PROG_START first argument
+//@{
+#define FLIP_V1_CMD_PROG_START_ARG_FLASH   0x00
+#define FLIP_V1_CMD_PROG_START_ARG_EEPROM  0x01
+#define FLIP_V1_CMD_PROG_START_ARG_CUSTOM  0x08
+//@}
+
+//! \name FLIP_V1_CMD_READ first argument
+//@{
+#define FLIP_V1_CMD_READ_ARG_FLASH      0x00
+#define FLIP_V1_CMD_READ_ARG_FLASHCHECK 0x01
+#define FLIP_V1_CMD_READ_ARG_EEPROM     0x02
+#define FLIP_V1_CMD_READ_ARG_CUSTOM     0x03
+//@}
+
+//! \name FLIP_V1_CMD_WRITE first argument
+//@{
+#define FLIP_V1_CMD_WRITE_ARG_ERASE     0x00
+#define FLIP_V1_CMD_WRITE_ARG_RST       0x03
+//! \name FLIP_V1_CMD_WRITE_ARG_ERASE following argument
+//@{
+#define FLIP_V1_CMD_WRITE_ARG_ERASE_CHIP 0xFF
+//@}
+//! \name FLIP_V1_CMD_WRITE_ARG_RST following arguments
+//@{
+#define FLIP_V1_CMD_WRITE_ARG_RST_HW    0x00
+#define FLIP_V1_CMD_WRITE_ARG_RST_SF    0x01
+//@}
+//@}
+
+//! \name FLIP_V1_CMD_READ_ID first argument
+//@{
+#define FLIP_V1_CMD_READ_ID_ARG_BOOTLOADER 0x00
+#define FLIP_V1_CMD_READ_ID_ARG_SIGNATURE  0x01
+//! \name FLIP_V1_CMD_READ_ID_ARG_SIGNATURE following arguments
+//@{
+#define FLIP_V1_CMD_READ_ID_SIGNATURE_ARG_MANUF              0x30
+#define FLIP_V1_CMD_READ_ID_SIGNATURE_ARG_FAMILY             0x31
+#define FLIP_V1_CMD_READ_ID_SIGNATURE_ARG_PRODUCT            0x60
+#define FLIP_V1_CMD_READ_ID_SIGNATURE_ARG_REVISION           0x61
+//@}
+//@}
+
+//! \name FLIP_V1_CMD_CHANGE_BASE_ADDR first argument
+//@{
+#define FLIP_V1_CMD_CHANGE_BASE_ADDR_ARG0   0x03
+#define FLIP_V1_CMD_CHANGE_BASE_ADDR_ARG1   0x00
+//@}
+
+//@}
+//@}
+
+
+/**
+ * \defgroup flip_pv2 Definitions for Atmel FLIP Protocol version 2
+ *
+ * Note: Used by uc3 and Xmega parts
+ *
+ * @{
+ */
+
+COMPILER_PACK_SET(1)
+/**
+ * \brief FLIP message structure
+ */
+typedef struct {
+	uint8_t group;
+	uint8_t cmd_id;
+	uint8_t arg[4];
+} flip_msg_v2_t;
+COMPILER_PACK_RESET()
+
+//! Size of buffer used by FLIP to receive or send data
+//! Note:  Write uses 2K and Read uses 1KB
+#define  FLIP_V2_BUF_TRANS_SIZE  (2*1024)
+
+//! \name Command Groups
+//@{
+#define FLIP_V2_CMD_GRP_DNLOAD                0x01
+#define FLIP_V2_CMD_GRP_UPLOAD                0x03
+#define FLIP_V2_CMD_GRP_EXEC                  0x04
+#define FLIP_V2_CMD_GRP_SELECT                0x06
+//@}
+
+//! \name FLIP_V2_CMD_GRP_DNLOAD first argument
+//@{
+#define FLIP_V2_CMD_PROGRAM_START             0x00
+//@}
+
+
+//! \name FLIP_V2_CMD_GRP_UPLOAD first argument
+//@{
+#define FLIP_V2_CMD_READ_MEMORY               0x00
+#define FLIP_V2_CMD_BLANK_CHECK               0x01
+//@}
+
+//! \name FLIP_V2_CMD_GRP_EXEC first argument
+//@{
+#define FLIP_V2_CMD_ERASE                     0x00
+#define FLIP_V2_CMD_START_APPLI               0x03
+//! \name FLIP_V2_CMD_ERASE following argument
+//@{
+#define FLIP_V2_CMD_ERASE_ARG_CHIP            0xFF
+//@}
+//! \name FLIP_V2_CMD_START_APPLI following arguments
+//@{
+#define FLIP_V2_CMD_START_APPLI_ARG_RESET     0x00
+#define FLIP_V2_CMD_START_APPLI_ARG_NO_RESET  0x01
+//@}
+//@}
+
+//! \name FLIP_V2_CMD_GRP_SELECT first argument
+//@{
+#define FLIP_V2_CMD_SELECT_MEMORY             0x03
+//! \name FLIP_V2_CMD_SELECT_MEMORY following arguments
+//@{
+#define FLIP_V2_CMD_SELECT_MEMORY_ARG_UNIT    0x00
+#define FLIP_V2_CMD_SELECT_MEMORY_ARG_PAGE    0x01
+//@}
+//! \name FLIP_V2_CMD_SELECT_MEMORY_ARG_UNIT following arguments
+//! Memory units field
+//@{
+#define FLIP_V2_CMD_SELECT_MEM_FLASH          0x00
+#define FLIP_V2_CMD_SELECT_MEM_EEPROM         0x01
+#define FLIP_V2_CMD_SELECT_MEM_SECURITY       0x02
+#define FLIP_V2_CMD_SELECT_MEM_CONFIGURATION  0x03
+#define FLIP_V2_CMD_SELECT_MEM_BOOTLOADER     0x04
+#define FLIP_V2_CMD_SELECT_MEM_SIGNATURE      0x05
+#define FLIP_V2_CMD_SELECT_MEM_USER           0x06
+#define FLIP_V2_CMD_SELECT_MEM_INT_RAM        0x07
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS0    0x08
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS1    0x09
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS2    0x0A
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS3    0x0B
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS4    0x0C
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS5    0x0D
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS6    0x0E
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS7    0x0F
+#define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_DF     0x10
+#define FLIP_V2_CMD_SELECT_MEM_COUNT          0x11	// Number of memory units
+//@}
+//@}
+
+//@}
+
+//@}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _FLIP_PROTOCOL_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/isp.h b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/isp.h
new file mode 100644
index 0000000000..fe035029ea
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/isp.h
@@ -0,0 +1,229 @@
+/**
+ * \file
+ *
+ * \brief In System Programming API
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _ISP_H_
+#define _ISP_H_
+
+#include "conf_isp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup isp In System Programming API
+ *
+ * @{
+ */
+
+/**
+ * \name Main In System Programming functions
+ * @{
+ */
+
+/**
+ * \brief Initializes the ISP interface
+ *
+ * Example, load the JTAG ID in signature memory
+ */
+void isp_init(void);
+
+/**
+ * \brief Gives the security state of the chip
+ *
+ * \return \c 1 if chip is secured, otherwise \c 0.
+ */
+bool isp_is_security(void);
+
+/**
+ * \brief Change the boot process configuration
+ * to enable/disable the ISP mode for the next startup.
+ *
+ * \param force  Enable the ISP mode for the next startup if true
+ */
+void isp_force_boot_isp(bool force);
+
+/**
+ * \brief Erase the application flash area and eventually the eeprom
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+bool isp_erase_chip(void);
+
+/**
+ * \brief Erase a part of the application flash area
+ * This function must be called again as long as it returns 0.
+ *
+ * \return \c 1 if the whole application flash area is erased, otherwise it is
+ * not finished.
+ *
+ * This function has been created to split a long erase so that
+ * the ISP application is able to answer external pending requests.
+ */
+
+bool isp_erase_chip_split(void);
+
+/**
+ * \brief Resets the device to start the user application
+ *
+ * The ISP mode must be disabled before (See isp_force_boot_isp(false))
+ * to allow the boot process to jump to the user application.
+ *
+ * \note: this function is usually implemented by using a watchdog reset
+ * or a software reset to restart the CPU.
+ */
+void isp_start_appli(void);
+//! @}
+
+
+//! Data type for holding flash memory addresses
+#ifdef ISP_SMALL_MEMORY_SIZE
+	typedef uint16_t isp_addr_t;
+#else
+	typedef uint32_t isp_addr_t;
+#endif
+
+//! Memory API definition
+typedef struct {
+	//! Size of the memory (unit Byte)
+	uint32_t size;
+	//! Function to read memory
+	void (*fnct_read) (void *dst, isp_addr_t src, uint16_t nbytes);
+	//! Function to write memory
+	void (*fnct_write) (isp_addr_t dst, const void *src, uint16_t nbytes);
+} isp_mem_t;
+
+/**
+ * \name Memory units index values
+ * Used to access at a memory through \ref isp_memories list.
+ * @{
+ */
+#define ISP_MEM_FLASH                        0x00
+#define ISP_MEM_EEPROM                       0x01
+#define ISP_MEM_SECURITY                     0x02
+#define ISP_MEM_CONFIGURATION                0x03
+#define ISP_MEM_BOOTLOADER                   0x04
+#define ISP_MEM_SIGNATURE                    0x05
+#define ISP_MEM_USER                         0x06
+#define ISP_MEM_INT_RAM                      0x07
+#define ISP_MEM_EXT_MEM_CS0                  0x08
+#define ISP_MEM_EXT_MEM_CS1                  0x09
+#define ISP_MEM_EXT_MEM_CS2                  0x0A
+#define ISP_MEM_EXT_MEM_CS3                  0x0B
+#define ISP_MEM_EXT_MEM_CS4                  0x0C
+#define ISP_MEM_EXT_MEM_CS5                  0x0D
+#define ISP_MEM_EXT_MEM_CS6                  0x0E
+#define ISP_MEM_EXT_MEM_CS7                  0x0F
+#define ISP_MEM_EXT_MEM_DF                   0x10
+#define ISP_MEM_COUNT                        0x11 // Number of memory units
+//! @}
+
+//! Memories list structure
+typedef union {
+	isp_mem_t const *mem[ISP_MEM_COUNT];
+	struct {
+		isp_mem_t const *flash;
+		isp_mem_t const *eeprom;
+		isp_mem_t const *security;
+		isp_mem_t const *conf;
+		isp_mem_t const *bootloader;
+		isp_mem_t const *signature;
+		isp_mem_t const *user;
+		isp_mem_t const *int_ram;
+		isp_mem_t const *ext_mem_cs0;
+		isp_mem_t const *ext_mem_cs1;
+		isp_mem_t const *ext_mem_cs2;
+		isp_mem_t const *ext_mem_cs3;
+		isp_mem_t const *ext_mem_cs4;
+		isp_mem_t const *ext_mem_cs5;
+		isp_mem_t const *ext_mem_cs6;
+		isp_mem_t const *ext_mem_cs7;
+		isp_mem_t const *ext_mem_df;
+	}list;
+} isp_mems_t;
+
+//! Memories list declaration
+extern const isp_mems_t isp_memories;
+
+COMPILER_PACK_SET(1) // alignment requested to simulate a memory
+
+//! Memory signature structure to store JTAG ID
+typedef union {
+	uint8_t mem[4];
+	struct {
+		uint8_t manufacture;
+		uint8_t product_number_msb;
+		uint8_t product_number_lsb;
+		uint8_t product_revision;
+	};
+} isp_mem_signature_t;
+
+
+/**
+ * Memory bootloader structure
+ *
+ * In the FLIP protocol, this structure is used to store medium
+ * and minor bootloader versions:
+ * - Example, Version 0x00 give 1.0.0 on batchisp log
+ * - Example, Version 0x03 give 1.0.3 on batchisp log
+ * - Example, Version 0x25 give 1.2.5 on batchisp log
+ * - id1 & id2 are not used and must always be 0.
+ */
+typedef struct {
+	uint8_t version;
+	uint8_t id1;
+	uint8_t id2;
+} isp_mem_bootloader_t;
+
+COMPILER_PACK_RESET()
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _ISP_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/module_config/conf_isp.h b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/module_config/conf_isp.h
new file mode 100644
index 0000000000..cad66a3871
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/module_config/conf_isp.h
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief ISP configuration file template.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _CONF_ISP_H_
+#define _CONF_ISP_H_
+
+// Bootloader Versions
+// Example: Version 0x00 gives 1.0.0 on batchisp log
+// Example: Version 0x03 gives 1.0.3 on batchisp log
+// Example: Version 0x25 gives 1.2.5 on batchisp log
+//
+// Note: a specific UC3 rule is defined:
+// - 1.0.X for USB bootloaders that follow the AVR32784 application note
+// specification
+// - 1.1.X for USB bootloaders that follow the AVR32806 application note
+// specification
+//
+#define BOOTLOADER_VERSION   0x00  // 1.0.0
+
+// If all memories (flash,eeprom,...) do not exceed 64KB.
+// then the ISP interface can be optimized to save CODE.
+#define ISP_SMALL_MEMORY_SIZE
+
+// Definition of hardware condition to enter in ISP mode on AVR Xmega devices
+#define ISP_PORT_DIR      PORTX_DIR
+#define ISP_PORT_PINCTRL  PORTX_PIN5CTRL
+#define ISP_PORT_IN       PORTX_IN
+#define ISP_PORT_PIN      0 to 7
+
+#endif // _CONF_ISP_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam0_usart/usart_serial.h b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam0_usart/usart_serial.h
new file mode 100644
index 0000000000..acd235cf96
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam0_usart/usart_serial.h
@@ -0,0 +1,151 @@
+/**
+ * \file
+ *
+ * \brief USART Serial wrapper service for the SAM D/L/C/R devices.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _USART_SERIAL_H_
+#define _USART_SERIAL_H_
+
+#include "compiler.h"
+#include "status_codes.h"
+#include "usart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \name Serial Management Configuration */
+
+typedef Sercom * usart_inst_t;
+
+//struct usart_module usart;
+
+/*! \brief Initializes the Usart in serial mode.
+ *
+ * \param[in,out] module  Software instance of the USART to initialize.
+ * \param[in]     hw      Base address of the hardware USART.
+ * \param[in]     config  Configuration settings for the USART.
+ *
+ * \retval true if the initialization was successful
+ * \retval false if initialization failed (error in baud rate calculation)
+ */
+static inline bool usart_serial_init(
+		struct usart_module *const module,
+		usart_inst_t const hw,
+		const struct usart_config *const config)
+{
+	if (usart_init(module, hw, config) == STATUS_OK) {
+		return true;
+	}
+	else {
+		return false;
+	}
+}
+
+/** \brief Sends a character with the USART.
+ *
+ * \param[in,out] module  Software instance of the USART.
+ * \param[in]     c       Character to write.
+ *
+ * \return Status code
+ */
+static inline enum status_code usart_serial_putchar(
+		struct usart_module *const module,
+		uint8_t c)
+{
+	while(STATUS_OK !=usart_write_wait(module, c));
+
+	return STATUS_OK;
+}
+
+/** \brief Waits until a character is received, and returns it.
+ *
+ * \param[in,out] module  Software instance of the USART.
+ * \param[out]    c       Destination for the read character.
+ */
+static inline void usart_serial_getchar(
+		struct usart_module *const module,
+		uint8_t *c)
+{
+	uint16_t temp = 0;
+
+	while(STATUS_OK != usart_read_wait(module, &temp));
+
+	*c = temp;
+}
+
+/**
+ * \brief Send a sequence of bytes to USART device
+ *
+ * \param[in,out] module   Software instance of the USART.
+ * \param[in]     tx_data  Data buffer to read the data to write from.
+ * \param[in]     length   Length of data to write.
+ */
+static inline enum status_code usart_serial_write_packet(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length)
+{
+	return usart_write_buffer_wait(module, tx_data, length);
+}
+
+/**
+ * \brief Receive a sequence of bytes from USART device
+ *
+ * \param[in,out] module   Software instance of the USART.
+ * \param[out]    rx_data  Data buffer to store the read data into.
+ * \param[in]     length   Length of data to read.
+ */
+static inline enum status_code usart_serial_read_packet(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	return usart_read_buffer_wait(module, rx_data, length);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _USART_SERIAL_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/module_config/conf_uart_serial.h b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/module_config/conf_uart_serial.h
new file mode 100644
index 0000000000..ce1dba582a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/module_config/conf_uart_serial.h
@@ -0,0 +1,71 @@
+/**
+ * \file
+ *
+ * \brief Serial USART service configuration.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_USART_SERIAL_H
+#define CONF_USART_SERIAL_H
+
+/* A reference setting for UART */
+/** UART Interface */
+//#define CONF_UART            CONSOLE_UART
+/** Baudrate setting */
+//#define CONF_UART_BAUDRATE   115200
+/** Parity setting */
+//#define CONF_UART_PARITY     UART_MR_PAR_NO
+
+
+/* A reference setting for USART */
+/** USART Interface */
+//#define CONF_UART              USART1
+/** Baudrate setting */
+//#define CONF_UART_BAUDRATE     115200
+/** Character length setting */
+//#define CONF_UART_CHAR_LENGTH  US_MR_CHRL_8_BIT
+/** Parity setting */
+//#define CONF_UART_PARITY       US_MR_PAR_NO
+/** Stop bits setting */
+//#define CONF_UART_STOP_BITS    US_MR_NBSTOP_1_BIT
+
+#endif/* CONF_USART_SERIAL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/uart_serial.h b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/uart_serial.h
new file mode 100644
index 0000000000..b6fece28ff
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/uart_serial.h
@@ -0,0 +1,689 @@
+/**
+ * \file
+ *
+ * \brief Uart Serial for SAM.
+ *
+ * Copyright (c) 2011-2017 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _UART_SERIAL_H_
+#define _UART_SERIAL_H_
+
+#include "compiler.h"
+#include "sysclk.h"
+#if (SAMG55)
+#include "flexcom.h"
+#endif
+#if ((!SAM4L) && (!SAMG55))
+#include "uart.h"
+#endif
+#include "usart.h"
+
+/** 
+ * \name Serial Management Configuration
+ */
+//! @{
+#include "conf_uart_serial.h"
+
+//! @}
+
+/** Input parameters when initializing RS232 and similar modes. */
+typedef struct uart_rs232_options {
+	/** Set baud rate of the USART (unused in slave modes). */
+	uint32_t baudrate;
+
+	/** Number of bits to transmit as a character (5-bit to 9-bit). */
+	uint32_t charlength;
+
+	/**
+	 * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc,
+	 * USART_PMODE_ODD_gc.
+	 */
+	uint32_t paritytype;
+
+	/** 1, 1.5 or 2 stop bits. */
+	uint32_t stopbits;
+
+} usart_rs232_options_t;
+
+typedef usart_rs232_options_t usart_serial_options_t;
+
+typedef Usart *usart_if;
+
+/** 
+ * \brief Initializes the Usart in master mode.
+ *
+ * \param p_usart  Base address of the USART instance.
+ * \param opt      Options needed to set up RS232 communication (see
+ * \ref usart_options_t).
+ */
+static inline void usart_serial_init(usart_if p_usart,
+		usart_serial_options_t *opt)
+{
+#if ((!SAM4L) && (!SAMG55))
+	sam_uart_opt_t uart_settings;
+	uart_settings.ul_mck = sysclk_get_peripheral_hz();
+	uart_settings.ul_baudrate = opt->baudrate;
+	uart_settings.ul_mode = opt->paritytype;
+#endif
+
+	sam_usart_opt_t usart_settings;
+	usart_settings.baudrate = opt->baudrate;
+	usart_settings.char_length = opt->charlength;
+	usart_settings.parity_type = opt->paritytype;
+	usart_settings.stop_bits= opt->stopbits;
+	usart_settings.channel_mode= US_MR_CHMODE_NORMAL;
+	
+#ifdef UART
+	if (UART == (Uart*)p_usart) {
+		sysclk_enable_peripheral_clock(ID_UART);
+		/* Configure UART */
+		uart_init((Uart*)p_usart, &uart_settings);
+	}
+#else
+# ifdef UART0
+	if (UART0 == (Uart*)p_usart) {
+		sysclk_enable_peripheral_clock(ID_UART0);
+		/* Configure UART */
+		uart_init((Uart*)p_usart, &uart_settings);
+	}
+# endif
+# ifdef UART1
+	if (UART1 == (Uart*)p_usart) {
+		sysclk_enable_peripheral_clock(ID_UART1);
+		/* Configure UART */
+		uart_init((Uart*)p_usart, &uart_settings);
+	}
+# endif
+# ifdef UART2
+	if (UART2 == (Uart*)p_usart) {
+		sysclk_enable_peripheral_clock(ID_UART2);
+		/* Configure UART */
+		uart_init((Uart*)p_usart, &uart_settings);
+	}
+# endif
+# ifdef UART3
+	if (UART3 == (Uart*)p_usart) {
+		sysclk_enable_peripheral_clock(ID_UART3);
+		/* Configure UART */
+		uart_init((Uart*)p_usart, &uart_settings);
+	}
+# endif
+# ifdef UART4
+	if (UART4 == (Uart*)p_usart) {
+		sysclk_enable_peripheral_clock(ID_UART4);
+		/* Configure UART */
+		uart_init((Uart*)p_usart, &uart_settings);
+	}
+# endif
+#endif /* ifdef UART */
+
+
+#ifdef USART
+	if (USART == p_usart) {
+#if (!SAM4L)
+		sysclk_enable_peripheral_clock(ID_USART);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+#else
+# ifdef USART0
+	if (USART0 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+		flexcom_enable(FLEXCOM0);
+		flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART);
+#else
+		sysclk_enable_peripheral_clock(ID_USART0);
+#endif
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+# endif
+# ifdef USART1
+	if (USART1 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+		flexcom_enable(FLEXCOM1);
+		flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART);
+#else
+		sysclk_enable_peripheral_clock(ID_USART1);
+#endif
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+# endif
+# ifdef USART2
+	if (USART2 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+		flexcom_enable(FLEXCOM2);
+		flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART);
+#else
+		sysclk_enable_peripheral_clock(ID_USART2);
+#endif
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+# endif
+# ifdef USART3
+	if (USART3 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+		flexcom_enable(FLEXCOM3);
+		flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART);
+#else
+		sysclk_enable_peripheral_clock(ID_USART3);
+#endif
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+# endif
+# ifdef USART4
+	if (USART4 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+		flexcom_enable(FLEXCOM4);
+		flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART);
+#else
+		sysclk_enable_peripheral_clock(ID_USART4);
+#endif
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+# endif
+# ifdef USART5
+	if (USART5 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+		flexcom_enable(FLEXCOM5);
+		flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART);
+#else
+		sysclk_enable_peripheral_clock(ID_USART5);
+#endif
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+# endif
+# ifdef USART6
+	if (USART6 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+		flexcom_enable(FLEXCOM6);
+		flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART);
+#else
+		sysclk_enable_peripheral_clock(ID_USART6);
+#endif
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+# endif
+# ifdef USART7
+	if (USART7 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+		flexcom_enable(FLEXCOM7);
+		flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART);
+#else
+		sysclk_enable_peripheral_clock(ID_USART7);
+#endif
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+		sysclk_enable_peripheral_clock(p_usart);
+		/* Configure USART */
+		usart_init_rs232(p_usart, &usart_settings,
+				sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+		/* Enable the receiver and transmitter. */
+		usart_enable_tx(p_usart);
+		usart_enable_rx(p_usart);
+	}
+# endif
+
+#endif /* ifdef USART */
+
+}
+
+/**
+ * \brief Sends a character with the USART.
+ *
+ * \param p_usart   Base address of the USART instance.
+ * \param c       Character to write.
+ *
+ * \return Status.
+ *   \retval 1  The character was written.
+ *   \retval 0  The function timed out before the USART transmitter became
+ * ready to send.
+ */
+static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c)
+{
+#ifdef UART
+	if (UART == (Uart*)p_usart) {
+		while (uart_write((Uart*)p_usart, c)!=0);
+		return 1;
+	}
+#else
+# ifdef UART0
+	if (UART0 == (Uart*)p_usart) {
+		while (uart_write((Uart*)p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef UART1
+	if (UART1 == (Uart*)p_usart) {
+		while (uart_write((Uart*)p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef UART2
+	if (UART2 == (Uart*)p_usart) {
+		while (uart_write((Uart*)p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef UART3
+	if (UART3 == (Uart*)p_usart) {
+		while (uart_write((Uart*)p_usart, c)!=0);
+		return 1;
+	}
+# endif
+#endif /* ifdef UART */
+
+
+#ifdef USART
+	if (USART == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+#else
+# ifdef USART0
+	if (USART0 == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef USART1
+	if (USART1 == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef USART2
+	if (USART2 == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef USART3
+	if (USART3 == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef USART4
+	if (USART4 == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef USART5
+	if (USART5 == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef USART6
+	if (USART6 == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+# endif
+# ifdef USART7
+	if (USART7 == p_usart) {
+		while (usart_write(p_usart, c)!=0);
+		return 1;
+	}
+# endif
+#endif /* ifdef USART */
+
+	return 0;
+}
+/**
+ * \brief Waits until a character is received, and returns it.
+ *
+ * \param p_usart   Base address of the USART instance.
+ * \param data   Data to read
+ *
+ */
+static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data)
+{
+	uint32_t val = 0;
+
+	/* Avoid Cppcheck Warning */
+	UNUSED(val);
+
+#ifdef UART
+	if (UART == (Uart*)p_usart) {
+		while (uart_read((Uart*)p_usart, data));
+	}
+#else
+# ifdef UART0
+	if (UART0 == (Uart*)p_usart) {
+		while (uart_read((Uart*)p_usart, data));
+	}
+# endif
+# ifdef UART1
+	if (UART1 == (Uart*)p_usart) {
+		while (uart_read((Uart*)p_usart, data));
+	}
+# endif
+# ifdef UART2
+	if (UART2 == (Uart*)p_usart) {
+		while (uart_read((Uart*)p_usart, data));
+	}
+# endif
+# ifdef UART3
+	if (UART3 == (Uart*)p_usart) {
+		while (uart_read((Uart*)p_usart, data));
+	}
+# endif
+#endif /* ifdef UART */
+
+
+#ifdef USART
+	if (USART == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+#else
+# ifdef USART0
+	if (USART0 == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+# endif
+# ifdef USART1
+	if (USART1 == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+# endif
+# ifdef USART2
+	if (USART2 == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+# endif
+# ifdef USART3
+	if (USART3 == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+# endif
+# ifdef USART4
+	if (USART4 == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+# endif
+# ifdef USART5
+	if (USART5 == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+# endif
+# ifdef USART6
+	if (USART6 == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+# endif
+# ifdef USART7
+	if (USART7 == p_usart) {
+		while (usart_read(p_usart, &val));
+		*data = (uint8_t)(val & 0xFF);
+	}
+# endif
+#endif /* ifdef USART */
+
+}
+
+/**
+ * \brief Check if Received data is ready.
+ *
+ * \param p_usart   Base address of the USART instance.
+ *
+ * \retval 1 One data has been received.
+ * \retval 0 No data has been received.
+ */
+static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart)
+{
+#ifdef UART
+	if (UART == (Uart*)p_usart) {
+		return uart_is_rx_ready((Uart*)p_usart);
+	}
+#else
+# ifdef UART0
+	if (UART0 == (Uart*)p_usart) {
+		return uart_is_rx_ready((Uart*)p_usart);
+	}
+# endif
+# ifdef UART1
+	if (UART1 == (Uart*)p_usart) {
+		return uart_is_rx_ready((Uart*)p_usart);
+	}
+# endif
+# ifdef UART2
+	if (UART2 == (Uart*)p_usart) {
+		return uart_is_rx_ready((Uart*)p_usart);
+	}
+# endif
+# ifdef UART3
+	if (UART3 == (Uart*)p_usart) {
+		return uart_is_rx_ready((Uart*)p_usart);
+	}
+# endif
+#endif /* ifdef UART */
+
+
+#ifdef USART
+	if (USART == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+#else
+# ifdef USART0
+	if (USART0 == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+# endif
+# ifdef USART1
+	if (USART1 == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+# endif
+# ifdef USART2
+	if (USART2 == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+# endif
+# ifdef USART3
+	if (USART3 == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+# endif
+# ifdef USART4
+	if (USART4 == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+# endif
+# ifdef USART5
+	if (USART5 == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+# endif
+# ifdef USART6
+	if (USART6 == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+# endif
+# ifdef USART7
+	if (USART7 == p_usart) {
+		return usart_is_rx_ready(p_usart);
+	}
+# endif
+#endif /* ifdef USART */
+
+	return 0;
+}
+
+/**
+ * \brief Send a sequence of bytes to a USART device
+ *
+ * \param usart Base address of the USART instance.
+ * \param data   data buffer to write
+ * \param len    Length of data
+ *
+ */
+status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
+		size_t len);
+
+/**
+ * \brief Receive a sequence of bytes to a USART device
+ *
+ * \param usart Base address of the USART instance.
+ * \param data   data buffer to write
+ * \param len    Length of data
+ *
+ */
+status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data,
+		size_t len);
+
+#endif  /* _UART_SERIAL_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/serial.h b/bsp/samd21/sam_d2x_asflib/common/services/serial/serial.h
new file mode 100644
index 0000000000..df0ae236b6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/serial.h
@@ -0,0 +1,279 @@
+/**
+ * \file
+ *
+ * \brief Serial Mode management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SERIAL_H_INCLUDED
+#define SERIAL_H_INCLUDED
+
+#include <parts.h>
+#include "status_codes.h"
+
+/**
+ * \typedef usart_if
+ *
+ * This type can be used independently to refer to USART module for the
+ * architecture used. It refers to the correct type definition for the
+ * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3.
+ */
+
+#if XMEGA
+# include "xmega_usart/usart_serial.h"
+#elif MEGA_RF
+# include "megarf_usart/usart_serial.h"
+#elif UC3
+# include "uc3_usart/usart_serial.h"
+#elif (SAMB)
+#include "samb_uart/uart_serial.h"
+#elif (SAM0)
+#include "sam0_usart/usart_serial.h"
+#elif SAM
+# include "sam_uart/uart_serial.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup serial_group Serial Interface (Serial)
+ *
+ * See \ref serial_quickstart.
+ *
+ * This is the common API for serial interface. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section serial_group_platform Platform Dependencies
+ *
+ * The serial API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - usart_serial_init()
+ *   - usart_serial_putchar()
+ *   - usart_serial_getchar()
+ *   - usart_serial_write_packet()
+ *   - usart_serial_read_packet()
+ *
+ *
+ * @{
+ */
+ 
+//! @}
+
+/**
+ * \page serial_quickstart Quick start guide for Serial Interface service
+ *
+ * This is the quick start guide for the \ref serial_group "Serial Interface module", with
+ * step-by-step instructions on how to configure and use the serial in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section serial_use_cases Serial use cases
+ * - \ref serial_basic_use_case
+ * - \subpage serial_use_case_1
+ *
+ * \section serial_basic_use_case Basic use case - transmit a character
+ * In this use case, the serial module is configured for:
+ * - Using USARTD0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case waits for a received character on the configured USART and
+ * echoes the character back to the same USART.
+ *
+ * \section serial_basic_use_case_setup Setup steps
+ *
+ * \subsection serial_basic_use_case_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclk)"
+ *
+ * \subsection serial_basic_use_case_setup_code Example code
+ * The following configuration must be added to the project (typically to a 
+ * conf_uart_serial.h file, but it can also be added to your main application file.)
+ *
+ * \note The following takes SAM3X configuration for example, other devices have similar
+ * configuration, but their parameters may be different, refer to corresponding header files.
+ *
+ * \code
+	#define USART_SERIAL                     &USARTD0
+	#define USART_SERIAL_BAUDRATE            9600
+	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
+	#define USART_SERIAL_PARITY              US_MR_PAR_NO
+	#define USART_SERIAL_STOP_BIT            false
+\endcode
+ *
+ * A variable for the received byte must be added:
+ * \code uint8_t received_byte; \endcode
+ *
+ * Add to application initialization:
+ * \code
+	    sysclk_init();
+
+	    static usart_serial_options_t usart_options = {
+	       .baudrate = USART_SERIAL_BAUDRATE,
+	       .charlength = USART_SERIAL_CHAR_LENGTH,
+	       .paritytype = USART_SERIAL_PARITY,
+	       .stopbits = USART_SERIAL_STOP_BIT
+	    };
+
+	    usart_serial_init(USART_SERIAL, &usart_options);
+\endcode
+ *
+ * \subsection serial_basic_use_case_setup_flow Workflow
+ * -# Initialize system clock:
+ *   - \code sysclk_init(); \endcode
+ * -# Create serial USART options struct:
+ *   - \code
+	static usart_serial_options_t usart_options = {
+	   .baudrate = USART_SERIAL_BAUDRATE,
+	   .charlength = USART_SERIAL_CHAR_LENGTH,
+	   .paritytype = USART_SERIAL_PARITY,
+	   .stopbits = USART_SERIAL_STOP_BIT
+	};
+\endcode
+ * -# Initialize the serial service:
+ *   - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode
+ *
+ * \section serial_basic_use_case_usage Usage steps
+ *
+ * \subsection serial_basic_use_case_usage_code Example code
+ * Add to application C-file:
+ * \code
+	usart_serial_getchar(USART_SERIAL, &received_byte);
+	usart_serial_putchar(USART_SERIAL, received_byte);
+\endcode
+ *
+ * \subsection serial_basic_use_case_usage_flow Workflow
+ * -# Wait for reception of a character:
+ *   - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode
+ * -# Echo the character back:
+ *   - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode
+ */
+
+/**
+ * \page serial_use_case_1 Advanced use case - Send a packet of serial data
+ *
+ * In this use case, the USART module is configured for:
+ * - Using USARTD0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case sends a string of text through the USART.
+ *
+ * \section serial_use_case_1_setup Setup steps
+ *
+ * \subsection serial_use_case_1_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclk)"
+ *
+ * \subsection serial_use_case_1_setup_code Example code
+ * The following configuration must be added to the project (typically to a 
+ * conf_uart_serial.h file, but it can also be added to your main application file.):
+ *
+ * \note The following takes SAM3X configuration for example, other devices have similar
+ * configuration, but their parameters may be different, refer to corresponding header files.
+ *
+ * \code
+	#define USART_SERIAL                     &USARTD0
+	#define USART_SERIAL_BAUDRATE            9600
+	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
+	#define USART_SERIAL_PARITY              US_MR_PAR_NO
+	#define USART_SERIAL_STOP_BIT            false
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+	    sysclk_init();
+
+	    static usart_serial_options_t usart_options = {
+	       .baudrate = USART_SERIAL_BAUDRATE,
+	       .charlength = USART_SERIAL_CHAR_LENGTH,
+	       .paritytype = USART_SERIAL_PARITY,
+	       .stopbits = USART_SERIAL_STOP_BIT
+	    };
+
+	    usart_serial_init(USART_SERIAL, &usart_options);
+\endcode
+ *
+ * \subsection serial_use_case_1_setup_flow Workflow
+ * -# Initialize system clock:
+ *   - \code sysclk_init(); \endcode
+ * -# Create USART options struct:
+ *   - \code
+	static usart_serial_options_t usart_options = {
+	   .baudrate = USART_SERIAL_BAUDRATE,
+	   .charlength = USART_SERIAL_CHAR_LENGTH,
+	   .paritytype = USART_SERIAL_PARITY,
+	   .stopbits = USART_SERIAL_STOP_BIT
+	};
+\endcode
+ * -# Initialize in RS232 mode:
+ *   - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode
+ *
+ * \section serial_use_case_1_usage Usage steps
+ *
+ * \subsection serial_use_case_1_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+	usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));
+\endcode
+ *
+ * \subsection serial_use_case_1_usage_flow Workflow
+ * -# Write a string of text to the USART:
+ *   - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode
+ */
+
+#endif /* SERIAL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/usart_serial.c b/bsp/samd21/sam_d2x_asflib/common/services/serial/usart_serial.c
new file mode 100644
index 0000000000..c67c256327
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/usart_serial.c
@@ -0,0 +1,87 @@
+/**
+ *
+ * \file
+ *
+ * \brief USART Serial driver functions.
+ *
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "serial.h"
+
+/**
+ * \brief Send a sequence of bytes to USART device
+ *
+ * \param usart  Base address of the USART instance.
+ * \param data   Data buffer to read
+ * \param len    Length of data
+ *
+ */
+status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
+		size_t len)
+{
+	while (len) {
+		usart_serial_putchar(usart, *data);
+		len--;
+		data++;
+	}
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Receive a sequence of bytes from USART device
+ *
+ * \param usart  Base address of the USART instance.
+ * \param data   Data buffer to write
+ * \param len    Length of data
+ *
+ */
+status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data,
+		size_t len)
+{
+	while (len) {
+		usart_serial_getchar(usart, data);
+		len--;
+		data++;
+	}
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h
new file mode 100644
index 0000000000..0f6efbc456
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h
@@ -0,0 +1,52 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific sleep manager configuration
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_SLEEPMGR_H
+#define CONF_SLEEPMGR_H
+
+// Sleep manager options
+#define CONFIG_SLEEPMGR_ENABLE
+
+#endif /* CONF_SLEEPMGR_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.c b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.c
new file mode 100644
index 0000000000..8531f56163
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.c
@@ -0,0 +1,54 @@
+/**
+ * \file
+ *
+ * \brief SAM3/SAM4 Sleep manager implementation.
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <sleepmgr.h>
+
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
+
+uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES];
+
+#endif /* CONFIG_SLEEPMGR_ENABLE */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.h
new file mode 100644
index 0000000000..a39bfd32fb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.h
@@ -0,0 +1,121 @@
+/**
+ * \file
+ *
+ * \brief SAM3/SAM4 Sleep manager implementation.
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAM_SLEEPMGR_INCLUDED
+#define SAM_SLEEPMGR_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <conf_sleepmgr.h>
+#include <sleep.h>
+#include <interrupt.h>
+
+/**
+ * \weakgroup sleepmgr_group
+ * @{
+ */
+enum sleepmgr_mode {
+	//! Active mode.
+	SLEEPMGR_ACTIVE = 0,
+	/*! WFE sleep mode.
+	 *  Potential Wake Up sources:
+	 *  fast startup events (USB, RTC, RTT, WKUPs),
+	 *  interrupt, and events. */
+	SLEEPMGR_SLEEP_WFE,
+	/*! WFI sleep mode.
+	 * Potential Wake Up sources: fast startup events and interrupt. */
+	SLEEPMGR_SLEEP_WFI,
+	/*! Wait mode, wakeup fast (in 3ms).
+	 *  XTAL is not disabled when sleep.
+	 *  Potential Wake Up sources: fast startup events */
+	SLEEPMGR_WAIT_FAST,
+	/*! Wait mode.
+	 *  Potential Wake Up sources: fast startup events */
+	SLEEPMGR_WAIT,
+#if (!(SAMG51 || SAMG53 || SAMG54))
+	//! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC.
+	SLEEPMGR_BACKUP,
+#endif
+	SLEEPMGR_NR_OF_MODES,
+};
+
+/**
+ * \internal
+ * \name Internal arrays
+ * @{
+ */
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
+//! Sleep mode lock counters
+extern uint8_t sleepmgr_locks[];
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+//! @}
+
+
+static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode)
+{
+	Assert(sleep_mode != SLEEPMGR_ACTIVE);
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	cpu_irq_disable();
+
+	// Atomically enable the global interrupts and enter the sleep mode.
+	pmc_sleep(sleep_mode);
+#else
+	UNUSED(sleep_mode);
+	cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+
+}
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAM_SLEEPMGR_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h
new file mode 100644
index 0000000000..2ccd8b3f7f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h
@@ -0,0 +1,52 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific sleep manager configuration
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_SLEEPMGR_INCLUDED
+#define CONF_SLEEPMGR_INCLUDED
+
+// Sleep manager options
+#define CONFIG_SLEEPMGR_ENABLE
+
+#endif /* CONF_SLEEPMGR_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.c b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.c
new file mode 100644
index 0000000000..4da613c849
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.c
@@ -0,0 +1,53 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific sleep manager configuration
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <compiler.h>
+#include <sleepmgr.h>
+
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
+
+uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES];
+
+#endif /* CONFIG_SLEEPMGR_ENABLE */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.h
new file mode 100644
index 0000000000..8cb94ddb5b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.h
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific sleep manager configuration
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAM_SLEEPMGR_INCLUDED
+#define SAM_SLEEPMGR_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <conf_sleepmgr.h>
+#include <interrupt.h>
+#include "system.h"
+
+/**
+ * \weakgroup sleepmgr_group
+ * @{
+ */
+
+enum sleepmgr_mode {
+	/** Active mode. */
+	SLEEPMGR_ACTIVE = 0,
+
+	/**
+	 *  Idle 0 mode.
+	 *  Potential Wake Up sources: Synchronous(APB, AHB), asynchronous.
+	 */
+	SLEEPMGR_IDLE_0,
+
+	/**
+	 *  Idle 1 mode.
+	 *  Potential Wake Up sources: Synchronous (APB), asynchronous
+	 */
+	SLEEPMGR_IDLE_1,
+
+	/**
+	 *  Idle 2 mode.
+	 *  Potential Wake Up sources: Asynchronous
+	 */
+	SLEEPMGR_IDLE_2,
+
+	/**
+	 * Standby mode.
+	 * Potential Wake Up sources: Asynchronous
+	 */
+	SLEEPMGR_STANDBY,
+
+	SLEEPMGR_NR_OF_MODES,
+};
+
+/**
+ * \internal
+ * \name Internal arrays
+ * @{
+ */
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
+/** Sleep mode lock counters */
+extern uint8_t sleepmgr_locks[];
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+/** @} */
+
+static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode)
+{
+	Assert(sleep_mode != SLEEPMGR_ACTIVE);
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	cpu_irq_disable();
+
+	/* Enter the sleep mode. */
+	system_set_sleepmode((enum system_sleepmode)(sleep_mode - 1));
+	cpu_irq_enable();
+	system_sleep();
+#else
+	UNUSED(sleep_mode);
+	cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAM_SLEEPMGR_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sleepmgr.h
new file mode 100644
index 0000000000..ae38de1361
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sleepmgr.h
@@ -0,0 +1,273 @@
+/**
+ * \file
+ *
+ * \brief Sleep manager
+ *
+ * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SLEEPMGR_H
+#define SLEEPMGR_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70)
+# include "sam/sleepmgr.h"
+#elif XMEGA
+# include "xmega/sleepmgr.h"
+#elif UC3
+# include "uc3/sleepmgr.h"
+#elif SAM4L
+# include "sam4l/sleepmgr.h"
+#elif MEGA
+# include "mega/sleepmgr.h"
+#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11 || SAMDA1)
+# include "samd/sleepmgr.h"
+#elif (SAML21 || SAML22 || SAMR30)
+# include "saml/sleepmgr.h"
+#elif (SAMC21)
+# include "samc/sleepmgr.h"
+#else
+# error Unsupported device.
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup sleepmgr_group Sleep manager
+ *
+ * The sleep manager is a service for ensuring that the device is not put to
+ * sleep in deeper sleep modes than the system (e.g., peripheral drivers,
+ * services or the application) allows at any given time.
+ *
+ * It is based on the use of lock counting for the individual sleep modes, and
+ * will put the device to sleep in the shallowest sleep mode that has a non-zero
+ * lock count. The drivers/services/application can change these counts by use
+ * of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode.
+ * Refer to \ref sleepmgr_mode for a list of the sleep modes available for
+ * locking, and the device datasheet for information on their effect.
+ *
+ * The application must supply the file \ref conf_sleepmgr.h.
+ *
+ * For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE
+ * must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not
+ * defined, the functions are replaced with dummy functions and no RAM is used.
+ *
+ * @{
+ */
+
+/**
+ * \def CONFIG_SLEEPMGR_ENABLE
+ * \brief Configuration symbol for enabling the sleep manager
+ *
+ * If this symbol is not defined, the functions of this service are replaced
+ * with dummy functions. This is useful for reducing code size and execution
+ * time if the sleep manager is not needed in the application.
+ *
+ * This symbol may be defined in \ref conf_sleepmgr.h.
+ */
+#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE)
+#  define CONFIG_SLEEPMGR_ENABLE
+#endif
+
+/**
+ * \enum sleepmgr_mode
+ * \brief Sleep mode locks
+ *
+ * Identifiers for the different sleep mode locks.
+ */
+
+/**
+ * \brief Initialize the lock counts
+ *
+ * Sets all lock counts to 0, except the very last one, which is set to 1. This
+ * is done to simplify the algorithm for finding the deepest allowable sleep
+ * mode in \ref sleepmgr_enter_sleep.
+ */
+static inline void sleepmgr_init(void)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	uint8_t i;
+
+	for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) {
+		sleepmgr_locks[i] = 0;
+	}
+	sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1;
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+ * \brief Increase lock count for a sleep mode
+ *
+ * Increases the lock count for \a mode to ensure that the sleep manager does
+ * not put the device to sleep in the deeper sleep modes.
+ *
+ * \param mode Sleep mode to lock.
+ */
+static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	irqflags_t flags;
+
+	if(sleepmgr_locks[mode] >= 0xff) {
+		while (true) {
+			// Warning: maximum value of sleepmgr_locks buffer is no more than 255.
+			// Check APP or change the data type to uint16_t.
+		}
+	}
+
+	// Enter a critical section
+	flags = cpu_irq_save();
+
+	++sleepmgr_locks[mode];
+
+	// Leave the critical section
+	cpu_irq_restore(flags);
+#else
+	UNUSED(mode);
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+ * \brief Decrease lock count for a sleep mode
+ *
+ * Decreases the lock count for \a mode. If the lock count reaches 0, the sleep
+ * manager can put the device to sleep in the deeper sleep modes.
+ *
+ * \param mode Sleep mode to unlock.
+ */
+static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	irqflags_t flags;
+
+	if(sleepmgr_locks[mode] == 0) {
+		while (true) {
+			// Warning: minimum value of sleepmgr_locks buffer is no less than 0.
+			// Check APP.
+		}
+	}
+
+	// Enter a critical section
+	flags = cpu_irq_save();
+
+	--sleepmgr_locks[mode];
+
+	// Leave the critical section
+	cpu_irq_restore(flags);
+#else
+	UNUSED(mode);
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+ /**
+ * \brief Retrieves the deepest allowable sleep mode
+ *
+ * Searches through the sleep mode lock counts, starting at the shallowest sleep
+ * mode, until the first non-zero lock count is found. The deepest allowable
+ * sleep mode is then returned.
+ */
+static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void)
+{
+	enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE;
+
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	uint8_t *lock_ptr = sleepmgr_locks;
+
+	// Find first non-zero lock count, starting with the shallowest modes.
+	while (!(*lock_ptr)) {
+		lock_ptr++;
+		sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1);
+	}
+
+	// Catch the case where one too many sleepmgr_unlock_mode() call has been
+	// performed on the deepest sleep mode.
+	Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES);
+
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+
+	return sleep_mode;
+}
+
+/**
+ * \fn sleepmgr_enter_sleep
+ * \brief Go to sleep in the deepest allowed mode
+ *
+ * Searches through the sleep mode lock counts, starting at the shallowest sleep
+ * mode, until the first non-zero lock count is found. The device is then put to
+ * sleep in the sleep mode that corresponds to the lock.
+ *
+ * \note This function enables interrupts before going to sleep, and will leave
+ * them enabled upon return. This also applies if sleep is skipped due to ACTIVE
+ * mode being locked.
+ */
+
+static inline void sleepmgr_enter_sleep(void)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	enum sleepmgr_mode sleep_mode;
+
+	cpu_irq_disable();
+
+	// Find the deepest allowable sleep mode
+	sleep_mode = sleepmgr_get_sleep_mode();
+	// Return right away if first mode (ACTIVE) is locked.
+	if (sleep_mode==SLEEPMGR_ACTIVE) {
+		cpu_irq_enable();
+		return;
+	}
+	// Enter the deepest allowable sleep mode with interrupts enabled
+	sleepmgr_sleep(sleep_mode);
+#else
+	cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SLEEPMGR_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/module_config/conf_spi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/module_config/conf_spi_master.h
new file mode 100644
index 0000000000..e98fe69f9c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/module_config/conf_spi_master.h
@@ -0,0 +1,67 @@
+/**
+ * \file
+ *
+ * \brief Spi Master configuration.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_SPI_MASTER_H_INCLUDED
+#define CONF_SPI_MASTER_H_INCLUDED
+
+/* Possibility to change low-level configurations here */
+
+//! Default Config Spi Master Delay BCS
+#define CONFIG_SPI_MASTER_DELAY_BCS            0
+
+//! Default Config Spi Master Bits per Transfer Definition
+#define CONFIG_SPI_MASTER_BITS_PER_TRANSFER    8
+
+//! Default Config Spi Master Delay BCT
+#define CONFIG_SPI_MASTER_DELAY_BCT            0
+
+//! Default Config Spi Master Delay BS
+#define CONFIG_SPI_MASTER_DELAY_BS             0
+
+//! Default Config Spi Master Dummy Field
+#define CONFIG_SPI_MASTER_DUMMY                0xFF
+
+#endif /* CONF_SPI_MASTER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.c b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.c
new file mode 100644
index 0000000000..562a7dc7e7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.c
@@ -0,0 +1,296 @@
+/**
+ * \file
+ *
+ * \brief SPI master common service for SAM.
+ *
+ * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "spi_master.h"
+#if SAMG55
+#include "flexcom.h"
+#include "conf_board.h"
+#endif
+
+/**
+ * \brief Max number when the chip selects are connected to a 4- to 16-bit decoder.
+ */
+#define MAX_NUM_WITH_DECODER 0x10
+
+/**
+ * \brief Max number when the chip selects are directly connected to peripheral device.
+ */
+#define MAX_NUM_WITHOUT_DECODER 0x04
+
+/**
+ * \brief Max number when the chip selects are directly connected to peripheral device.
+ */
+#define NONE_CHIP_SELECT_ID 0x0f
+
+/**
+ * \brief The default chip select id.
+ */
+#define DEFAULT_CHIP_ID 0
+
+/** \brief Initialize the SPI in master mode.
+ *
+ * \param p_spi  Base address of the SPI instance.
+ *
+ */
+void spi_master_init(Spi *p_spi)
+{
+#if SAMG55
+	flexcom_enable(BOARD_FLEXCOM_SPI);
+	flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
+#else
+	spi_enable_clock(p_spi);
+#endif
+	spi_reset(p_spi);
+	spi_set_master_mode(p_spi);
+	spi_disable_mode_fault_detect(p_spi);
+	spi_disable_loopback(p_spi);
+	spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
+	spi_set_fixed_peripheral_select(p_spi);
+	spi_disable_peripheral_select_decode(p_spi);
+	spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
+}
+
+/**
+ * \brief Set up an SPI device.
+ *
+ * The returned device descriptor structure must be passed to the driver
+ * whenever that device should be used as current slave device.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param device    Pointer to SPI device struct that should be initialized.
+ * \param flags     SPI configuration flags. Common flags for all
+ *                  implementations are the SPI modes SPI_MODE_0 ...
+ *                  SPI_MODE_3.
+ * \param baud_rate Baud rate for communication with slave device in Hz.
+ * \param sel_id    Board specific select id.
+ */
+void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
+		spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
+{
+#if (SAM4L)
+    int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_pba_hz());
+#else
+	int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_peripheral_hz());
+#endif
+	/* avoid Cppcheck Warning */
+	UNUSED(sel_id);
+	if (-1 == baud_div) {
+		Assert(0 == "Failed to find baudrate divider");
+	}
+	spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
+			CONFIG_SPI_MASTER_DELAY_BCT);
+	spi_set_bits_per_transfer(p_spi, device->id,
+			CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
+	spi_set_baudrate_div(p_spi, device->id, baud_div);
+	spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
+	spi_set_clock_polarity(p_spi, device->id, flags >> 1);
+	spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
+}
+
+/**
+ * \brief Select the given device on the SPI bus.
+ *
+ * Set device specific setting and call board chip select.
+ *
+ * \param p_spi   Base address of the SPI instance.
+ * \param device  SPI device.
+ *
+ */
+void spi_select_device(Spi *p_spi, struct spi_device *device)
+{
+	if (spi_get_peripheral_select_decode_setting(p_spi)) {
+		if (device->id < MAX_NUM_WITH_DECODER) {
+			spi_set_peripheral_chip_select_value(p_spi, device->id);
+		}
+	} else {
+		if (device->id < MAX_NUM_WITHOUT_DECODER) {
+			spi_set_peripheral_chip_select_value(p_spi, (~(1 << device->id)));
+		}
+	}
+}
+
+/**
+ * \brief Deselect the given device on the SPI bus.
+ *
+ * Call board chip deselect.
+ *
+ * \param p_spi   Base address of the SPI instance.
+ * \param device  SPI device.
+ *
+ * \pre SPI device must be selected with spi_select_device() first.
+ */
+void spi_deselect_device(Spi *p_spi, struct spi_device *device)
+{
+	/* avoid Cppcheck Warning */
+	UNUSED(device);
+	while (!spi_is_tx_empty(p_spi)) {
+	}
+
+	// Assert all lines; no peripheral is selected.
+	spi_set_peripheral_chip_select_value(p_spi, NONE_CHIP_SELECT_ID);
+
+	// Last transfer, so de-assert the current NPCS if CSAAT is set.
+	spi_set_lastxfer(p_spi);
+
+}
+
+/**
+ * \brief Send a sequence of bytes to an SPI device.
+ *
+ * Received bytes on the SPI bus are discarded.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param data      Data buffer to write.
+ * \param len       Length of data to be written.
+ *
+ * \pre SPI device must be selected with spi_select_device() first.
+ */
+status_code_t spi_write_packet(Spi *p_spi, const uint8_t *data,
+		size_t len)
+{
+	uint32_t timeout = SPI_TIMEOUT;
+	uint32_t i = 0;
+	uint8_t val;
+
+	while (len) {
+		timeout = SPI_TIMEOUT;
+		while (!spi_is_tx_ready(p_spi)) {
+			if (!timeout--) {
+				return ERR_TIMEOUT;
+			}
+		}
+		val = data[i];
+		spi_write_single(p_spi, val);
+		i++;
+		len--;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a sequence of bytes from an SPI device.
+ *
+ * All bytes sent out on SPI bus are sent as value 0.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param data      Data buffer to read.
+ * \param len       Length of data to be read.
+ *
+ * \pre SPI device must be selected with spi_select_device() first.
+ */
+status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len)
+{
+	uint32_t timeout = SPI_TIMEOUT;
+	uint8_t val;
+	uint32_t i = 0;
+
+	while (len) {
+		timeout = SPI_TIMEOUT;
+		while (!spi_is_tx_ready(p_spi)) {
+			if (!timeout--) {
+				return ERR_TIMEOUT;
+			}
+		}
+		spi_write_single(p_spi, CONFIG_SPI_MASTER_DUMMY);
+
+		timeout = SPI_TIMEOUT;
+		while (!spi_is_rx_ready(p_spi)) {
+			if (!timeout--) {
+				return ERR_TIMEOUT;
+			}
+		}
+		spi_read_single(p_spi, &val);
+
+		data[i] = val;
+		i++;
+		len--;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Send and receive a sequence of bytes from an SPI device.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param tx_data   Data buffer to send.
+ * \param rx_data   Data buffer to read.
+ * \param len       Length of data to be read.
+ *
+ * \pre SPI device must be selected with spi_select_device() first.
+ */
+status_code_t spi_transceive_packet(Spi *p_spi, uint8_t *tx_data, uint8_t *rx_data, size_t len)
+{
+	uint32_t timeout = SPI_TIMEOUT;
+	uint8_t val;
+	uint32_t i = 0;
+
+	while (len) {
+		timeout = SPI_TIMEOUT;
+		while (!spi_is_tx_ready(p_spi)) {
+			if (!timeout--) {
+				return ERR_TIMEOUT;
+			}
+		}
+		spi_write_single(p_spi, tx_data[i]);
+
+		timeout = SPI_TIMEOUT;
+		while (!spi_is_rx_ready(p_spi)) {
+			if (!timeout--) {
+				return ERR_TIMEOUT;
+			}
+		}
+		spi_read_single(p_spi, &val);
+
+		rx_data[i] = val;
+		i++;
+		len--;
+	}
+
+	return STATUS_OK;
+}
+//! @}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.h
new file mode 100644
index 0000000000..a5fd655763
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.h
@@ -0,0 +1,252 @@
+/**
+ * \file
+ *
+ * \brief SPI master common service for SAM.
+ *
+ * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SPI_MASTER_H_
+#define _SPI_MASTER_H_
+
+#include "compiler.h"
+#include "sysclk.h"
+#include "status_codes.h"
+#include "spi.h"
+
+/*! \name SPI Master Management Configuration */
+//! @{
+#include "conf_spi_master.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+//! Default Configuration of SPI Master Delay BCS
+#ifndef CONFIG_SPI_MASTER_DELAY_BCS
+#define CONFIG_SPI_MASTER_DELAY_BCS          0
+#endif
+
+//! Default Configuration of SPI Master Bits per Transfer Definition
+#ifndef CONFIG_SPI_MASTER_BITS_PER_TRANSFER
+#define CONFIG_SPI_MASTER_BITS_PER_TRANSFER  SPI_CSR_BITS_8_BIT
+#endif
+
+//! Default Configuration of SPI Master Delay BCT
+#ifndef CONFIG_SPI_MASTER_DELAY_BCT
+#define CONFIG_SPI_MASTER_DELAY_BCT          0
+#endif
+
+//! Default Configuration of SPI Master Delay BS
+#ifndef CONFIG_SPI_MASTER_DELAY_BS
+#define CONFIG_SPI_MASTER_DELAY_BS           0
+#endif
+
+//! Default Configuration of SPI Master Dummy Field
+#ifndef CONFIG_SPI_MASTER_DUMMY
+#define CONFIG_SPI_MASTER_DUMMY              0xFF
+#endif
+//! @}
+
+/**
+ * \brief Clock phase.
+ */
+#define SPI_CPHA  (1 << 0)
+
+/**
+ * \brief Clock polarity.
+ */
+#define SPI_CPOL  (1 << 1)
+
+/**
+ * \brief SPI mode 0.
+ */
+#define SPI_MODE_0  0
+/**
+ * \brief SPI mode 1.
+ */
+#define SPI_MODE_1  (SPI_CPHA)
+/**
+ * \brief SPI mode 2.
+ */
+#define SPI_MODE_2  (SPI_CPOL)
+/**
+ * \brief SPI mode 3.
+ */
+#define SPI_MODE_3  (SPI_CPOL | SPI_CPHA)
+
+#ifndef SPI_TYPE_DEFS
+#define SPI_TYPE_DEFS
+//! SPI Flags Definition
+typedef uint8_t spi_flags_t;
+
+//! Board SPI Select Id Definition
+typedef uint32_t board_spi_select_id_t;
+#endif
+
+//! \brief Polled SPI device definition.
+struct spi_device {
+	//! Board specific select id
+	board_spi_select_id_t id;
+};
+
+/** \brief Initialize the SPI in master mode.
+ *
+ * \param p_spi Base address of the SPI instance.
+ *
+ */
+extern void spi_master_init(Spi *p_spi);
+
+/**
+ * \brief Set up an SPI device.
+ *
+ * The returned device descriptor structure must be passed to the driver
+ * whenever that device should be used as current slave device.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param device    Pointer to SPI device struct that should be initialized.
+ * \param flags     SPI configuration flags. Common flags for all
+ *                  implementations are the SPI modes SPI_MODE_0 ...
+ *                  SPI_MODE_3.
+ * \param baud_rate Baud rate for communication with slave device in Hz.
+ * \param sel_id    Board specific select id.
+ */
+extern void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
+		spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id);
+
+/**
+ * \brief Select the given device on the SPI bus.
+ *
+ * Set device specific setting and call board chip select.
+ *
+ * \param p_spi  Base address of the SPI instance.
+ * \param device SPI device.
+ *
+ */
+extern void spi_select_device(Spi *p_spi, struct spi_device *device);
+
+/**
+ * \brief Deselect the given device on the SPI bus.
+ *
+ * Call board chip deselect.
+ *
+ * \param p_spi  Base address of the SPI instance.
+ * \param device SPI device.
+ *
+ * \pre SPI device must be selected with spi_select_device() first.
+ */
+extern void spi_deselect_device(Spi *p_spi, struct spi_device *device);
+
+
+/** \brief Write one byte to an SPI device.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param data      Data to write.
+ *
+ */
+static inline void spi_write_single(Spi *p_spi, uint8_t data)
+{
+	spi_put(p_spi, (uint16_t)data);
+}
+
+/**
+ * \brief Send a sequence of bytes to an SPI device.
+ *
+ * Received bytes on the SPI bus are discarded.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param data      Data buffer to write.
+ * \param len       Length of data to be written.
+ *
+ * \pre SPI device must be selected with spi_select_device() first.
+ */
+extern status_code_t spi_write_packet(Spi *p_spi,
+		const uint8_t *data, size_t len);
+
+/** \brief Receive one byte from an SPI device.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param data      Data to read.
+ *
+ */
+static inline void spi_read_single(Spi *p_spi, uint8_t *data)
+{
+	*data = (uint8_t)spi_get(p_spi);
+}
+
+/**
+ * \brief Receive a sequence of bytes from an SPI device.
+ *
+ * All bytes sent out on SPI bus are sent as value 0xff.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param data      Data buffer to read.
+ * \param len       Length of data to be read.
+ *
+ * \pre SPI device must be selected with spi_select_device() first.
+ */
+extern status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len);
+
+/**
+ * \brief Send and receive a sequence of bytes from an SPI device.
+ *
+ * \param p_spi     Base address of the SPI instance.
+ * \param tx_data   Data buffer to send.
+ * \param rx_data   Data buffer to read.
+ * \param len       Length of data to be read.
+ *
+ * \pre SPI device must be selected with spi_select_device() first.
+ */
+extern status_code_t spi_transceive_packet(Spi *p_spi, uint8_t *tx_data, uint8_t *rx_data, size_t len);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif // _SPI_MASTER_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/module_config/conf_usart_spi.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/module_config/conf_usart_spi.h
new file mode 100644
index 0000000000..565d665db9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/module_config/conf_usart_spi.h
@@ -0,0 +1,50 @@
+/**
+ * \file
+ *
+ * \brief USART SPI Configuration.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_USART_SPI_H_INCLUDED
+#define CONF_USART_SPI_H_INCLUDED
+
+#endif /* CONF_USART_SPI_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.c b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.c
new file mode 100644
index 0000000000..7dcaf76689
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.c
@@ -0,0 +1,344 @@
+/**
+ * \file
+ *
+ * \brief SAM USART in SPI mode driver functions.
+ *
+ * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "usart_spi.h"
+#include "sysclk.h"
+#if SAMG55
+#include "flexcom.h"
+#include "conf_board.h"
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/*! \brief Enable the USART system clock in SPI master mode.
+ *
+ * \param p_usart Pointer to Base address of the USART instance.
+ *
+ */
+void usart_spi_init(Usart *p_usart)
+{
+#if (!SAMG55)
+
+	uint8_t uc_id;
+
+#ifdef USART0
+	if (p_usart == USART0) {
+		uc_id = ID_USART0;
+	}
+#endif
+
+#ifdef USART1
+	else if(p_usart == USART1) {
+		uc_id = ID_USART1;
+	}
+#endif
+
+#ifdef USART2
+	else if(p_usart == USART2) {
+		uc_id = ID_USART2;
+	}
+#endif
+
+#ifdef USART3
+	else if(p_usart == USART3) {
+		uc_id = ID_USART3;
+	}
+#endif
+
+#endif
+
+#if SAM4L
+	sysclk_enable_peripheral_clock(p_usart);
+#elif SAMG55
+	flexcom_enable(BOARD_FLEXCOM_USART);
+	flexcom_set_opmode(BOARD_FLEXCOM_USART, FLEXCOM_USART);
+#else
+	sysclk_enable_peripheral_clock(uc_id);
+#endif
+}
+
+/**
+ * \brief Set up a USART in SPI master mode device.
+ *
+ * The returned device descriptor structure must be passed to the driver
+ * whenever that device should be used as current slave device.
+ *
+ * \param p_usart   Base address of the USART instance.
+ * \param device    Pointer to usart device struct that should be initialized.
+ * \param flags     USART configuration flags. Common flags for all
+ *                  implementations are the usart modes, which should be SPI_MODE_0,
+ *                  SPI_MODE_1, SPI_MODE_2, SPI_MODE_3.
+ * \param baud_rate Baud rate for communication with slave device in Hz.
+ * \param sel_id    Board specific select id.
+ */
+void usart_spi_setup_device(Usart *p_usart, struct usart_spi_device *device, 
+     spi_flags_t flags, unsigned long baud_rate,
+     board_spi_select_id_t sel_id)
+{
+	usart_spi_opt_t opt;
+
+	/* avoid Cppcheck Warning */
+	UNUSED(device);
+	UNUSED(sel_id);
+
+	/* Basic usart SPI configuration. */
+	opt.baudrate = baud_rate;
+	opt.char_length = US_MR_CHRL_8_BIT;
+	opt.spi_mode = flags;
+	opt.channel_mode = US_MR_CHMODE_NORMAL;
+	
+	/* Initialize the USART module as SPI master. */
+#if (SAM4L)
+	usart_init_spi_master(p_usart, &opt, sysclk_get_pba_hz());
+#else
+	usart_init_spi_master(p_usart, &opt, sysclk_get_peripheral_hz());
+#endif
+
+	usart_enable_rx(p_usart);
+	usart_enable_tx(p_usart);
+}
+
+/*! \brief Write one byte to an SPI device using USART in SPI mode.
+ *
+ * \param p_usart Base address of the USART instance.
+ * \param data    The data to be sent out. 
+ *
+ */
+void usart_spi_write_single(Usart *p_usart, uint8_t data)
+{
+	usart_putchar(p_usart, data);
+}
+
+/**
+ * \brief Send a sequence of bytes to an SPI device using USART in SPI mode.
+ *
+ * Received bytes on the USART in SPI mode are discarded.
+ *
+ * \param p_usart Base address of the USART instance.
+ * \param data    Data buffer to write.
+ * \param len     Length of data.
+ *
+ * \return 0 if the USART in SPI master mode sends packet successfully.
+ *
+ * \pre USART device must be selected with usart_spi_select_device() first.
+ */
+uint32_t usart_spi_write_packet(Usart *p_usart, const uint8_t *data, size_t len)
+{
+	uint32_t dummy_data;
+	size_t i=0;
+	while(len) {
+		usart_putchar(p_usart, *(data+i));
+		usart_getchar(p_usart, &dummy_data);
+		len--;
+		i++;
+	}
+	return 0;
+}
+
+/*! \brief Receive one byte from an SPI device using USART in SPI mode.
+ *
+ * \param p_usart Base address of the USART instance.
+ * \param data    Pointer to the data byte where to store the received data.
+ *
+ * \pre USART device must be selected with usart_spi_select_device() first.
+ */
+void usart_spi_read_single(Usart *p_usart, uint8_t *data)
+{
+	uint32_t temp_data = 0;
+	/* Dummy write one data to slave in order to read data. */
+	usart_putchar(p_usart, CONFIG_USART_SPI_DUMMY);
+
+	usart_getchar(p_usart, &temp_data);
+	*data = (uint8_t)temp_data;
+}
+
+/**
+ * \brief Receive a sequence of bytes from a USART in SPI mode device.
+ *
+ * All bytes sent out on usart bus are sent as value 0.
+ *
+ * \param p_usart Base address of the usart instance.
+ * \param data    Data buffer to put read data.
+ * \param len     Length of data.
+ *
+ * \return 0 if the USART in SPI master mode reads packet successfully.
+ *
+ * \pre USART device must be selected with usart_spi_select_device() first.
+ */
+uint32_t usart_spi_read_packet(Usart *p_usart, uint8_t *data, size_t len)
+{
+	uint32_t val;
+	uint32_t i = 0;
+
+	while(len) {
+		/* Dummy write one data to slave in order to read data. */
+		usart_putchar(p_usart, CONFIG_USART_SPI_DUMMY);
+		usart_getchar(p_usart, &val);
+
+		data[i] = (uint8_t)(val & 0xFF);
+		i++;
+		len--;
+	}
+	
+	return 0;
+}
+
+/**
+ * \brief Select the given device on the SPI bus.
+ *
+ * \param p_usart  Base address of the USART instance.
+ * \param device   SPI device.
+ *
+ */
+void usart_spi_select_device(Usart *p_usart, struct usart_spi_device *device)
+{
+	/* avoid Cppcheck Warning */
+	UNUSED(device);
+	
+	usart_spi_force_chip_select(p_usart);
+}
+
+/**
+ * \brief De-select the given device on the SPI bus.
+ *
+ * \param p_usart Base address of the USART instance.
+ * \param device  SPI device.
+ */
+void usart_spi_deselect_device(Usart *p_usart, struct usart_spi_device *device)
+{
+	/* avoid Cppcheck Warning */
+	UNUSED(device);
+	
+	usart_spi_release_chip_select(p_usart);
+}
+
+/*! \brief Check whether there are data in Transmit Holding Register or
+ *         Transmit Shift Register in SPI master mode.
+ *
+ * \param p_usart Base address of the USART instance.
+ *
+ * \retval 1      The two registers are empty.
+ * \retval 0      One of the two registers contains data.
+ */
+uint32_t usart_spi_is_tx_empty(Usart *p_usart)
+{
+	return usart_is_tx_empty(p_usart);
+}
+
+/*! \brief Check whether the USART in SPI master mode contains a received character.
+ *
+ * \param p_usart Base address of the USART instance.
+ *
+ * \retval 1      Some data have been received.
+ * \retval 0      No data has been received.
+ */
+uint32_t usart_spi_is_rx_ready(Usart *p_usart)
+{
+	return usart_is_rx_ready(p_usart);
+}
+
+/*! \brief Check if the USART Transmit Holding Register is empty or not in SPI mode.
+ *
+ * \param p_usart Base address of the USART instance.
+ *
+ * \retval 1      There is no data in the Transmit Holding Register.
+ * \retval 0      There are data in the Transmit Holding Register.
+ */
+uint32_t usart_spi_is_tx_ready(Usart *p_usart)
+{
+	return usart_is_tx_ready(p_usart);
+}
+
+/*! \brief Check if both receive buffers are full.
+ *
+ * \param p_usart Base address of the USART instance.
+ *
+ * \retval 1      Receive buffers are full.
+ * \retval 0      Receive buffers are not full.
+ */
+uint32_t usart_spi_is_rx_full(Usart *p_usart)
+{
+#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
+	return usart_is_rx_buf_full(p_usart);
+#endif
+}
+
+/*! \brief Enable the USART for the specified USART in SPI mode.
+ *
+ * \param p_usart Base address of the USART instance.
+ */
+void usart_spi_enable(Usart *p_usart)
+{
+	usart_enable_tx(p_usart);
+	usart_enable_rx(p_usart);
+}
+
+/*! \brief Disable the USART for the specified USART in SPI mode.
+ *
+ * Ensure that nothing is transferred while setting up buffers.
+ *
+ * \param p_usart Base address of the USART instance.
+ *
+ */
+void usart_spi_disable(Usart *p_usart)
+{
+	usart_disable_tx(p_usart);
+	usart_disable_rx(p_usart);
+}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.h
new file mode 100644
index 0000000000..026c4e302a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.h
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief SAM USART in SPI mode driver functions.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _USART_SPI_H_
+#define _USART_SPI_H_
+
+#include "compiler.h"
+#include "usart.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/*! \name USART in SPI mode Management Configuration.
+ */
+//! @{
+#include "conf_usart_spi.h"
+
+//! Default Configuration of SPI Master Dummy Field
+#ifndef CONFIG_USART_SPI_DUMMY
+	#define CONFIG_USART_SPI_DUMMY              0xFF
+#endif
+//! @}
+
+#ifndef SPI_TYPE_DEFS
+#define SPI_TYPE_DEFS
+//! SPI Flags Definition
+typedef uint8_t spi_flags_t;
+
+//! Board SPI Select Id Definition
+typedef uint32_t board_spi_select_id_t;
+#endif
+
+typedef uint8_t port_pin_t; 
+
+//! \brief Polled SPI device definition.
+struct usart_spi_device {
+	/* Board specific select id. */
+	port_pin_t	id;
+};
+
+void usart_spi_init(Usart *p_usart);
+void usart_spi_setup_device(Usart *p_usart, struct usart_spi_device *device,
+     spi_flags_t flags, unsigned long baud_rate, board_spi_select_id_t sel_id);
+void usart_spi_write_single(Usart *p_usart, uint8_t data);
+uint32_t usart_spi_write_packet(Usart *p_usart, const uint8_t *data, size_t len);
+void usart_spi_read_single(Usart *p_usart, uint8_t *data);
+uint32_t usart_spi_read_packet(Usart *p_usart, uint8_t *data, size_t len);
+void usart_spi_select_device(Usart *p_usart, struct usart_spi_device *device);
+void usart_spi_deselect_device(Usart *p_usart, struct usart_spi_device *device);
+uint32_t usart_spi_is_tx_empty(Usart *p_usart);
+uint32_t usart_spi_is_rx_ready(Usart *p_usart);
+uint32_t usart_spi_is_tx_ready(Usart *p_usart);
+uint32_t usart_spi_is_rx_full(Usart *p_usart);
+void usart_spi_enable(Usart *p_usart);
+void usart_spi_disable(Usart *p_usart);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif  /* _USART_SPI_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/spi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/spi_master.h
new file mode 100644
index 0000000000..e92f4ca5ac
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/spi_master.h
@@ -0,0 +1,273 @@
+/**
+ * \file
+ *
+ * \brief SPI Master Mode management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SPI_MASTER_H_INCLUDED
+#define SPI_MASTER_H_INCLUDED
+
+#include <parts.h>
+
+#if XMEGA
+# include "xmega_spi/spi_master.h"
+#elif MEGA_RF
+# include "megarf_spi/spi_master.h"
+#elif UC3
+# include "uc3_spi/spi_master.h"
+#elif SAM
+# include "sam_spi/spi_master.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup spi_group Serial Peripheral Interface (SPI)
+ *
+ * This is the common API for SPI interface. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section spi_group_platform Platform Dependencies
+ *
+ * The SPI API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behavior. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - spi_master_init()
+ *   - spi_master_setup_device()
+ *   - spi_select_device()
+ *   - spi_deselect_device()
+ *   - spi_write_single()
+ *   - spi_write_packet()
+ *   - spi_read_single()
+ *   - spi_read_packet()
+ *   - spi_is_tx_empty()
+ *   - spi_is_tx_ready()
+ *   - spi_is_rx_full()
+ *   - spi_is_rx_ready()
+ *   - spi_enable()
+ *   - spi_disable()
+ *   - spi_is_enabled()
+ *
+ * \section spi_master_quickstart_section Quick Start Guide
+ * See \ref common_spi_master_quickstart
+ * @{
+ */
+
+//! @}
+
+/**
+ * \page common_spi_master_quickstart Quick Start Guide for the SPI Master Driver
+ *
+ * This is the quick start guide for the \ref spi_group "SPI Driver", with
+ * step-by-step instructions on how to configure and use the driver for a
+ * specific use case.
+ *
+ * The use case contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * The steps for setting up the SPI master for XMEGA and UC3 use exactly the
+ * same approach, but note that there are different names on the peripherals. So
+ * to use this Quick Start for UC3 please make sure that all the peripheral
+ * names are updated according to the UC3 datasheet.
+ * - \subpage spi_master_xmega
+ *
+ */
+/**
+ * \page spi_master_xmega Basic setup for SPI master on XMEGA devices
+ *
+ * \section spi_master_xmega_basic Basic setup for XMEGA devices
+ * The SPI module will be set up as master:
+ *  - SPI on PORTD
+ *  - 1MHz SPI clock speed
+ *  - Slave Chip Select connected on PORTD pin 1
+ *  - SPI mode 0 (data on rising clock edge)
+ *
+ * \section   spi_master_xmega_basic_setup Setup steps
+ * \subsection spi_master_xmega_basic_setup_code Example code
+ * Add to application C-file (e.g. main.c):
+ * \code
+	   void spi_init_pins(void)
+	   {
+	       ioport_configure_port_pin(&PORTD, PIN1_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+
+	       ioport_configure_port_pin(&PORTD, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT);
+	       ioport_configure_port_pin(&PORTD, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+	       ioport_configure_port_pin(&PORTD, PIN6_bm, IOPORT_DIR_INPUT);
+	       ioport_configure_port_pin(&PORTD, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+	   }
+
+	   void spi_init_module(void)
+	   {
+	      struct spi_device spi_device_conf = {
+	          .id = IOPORT_CREATE_PIN(PORTD, 1)
+	      };
+
+	      spi_master_init(&SPID);
+	      spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0);
+	      spi_enable(&SPID);
+	   }
+\endcode
+ *
+ * \subsection spi_master_xmega_basic_setup Workflow
+ * -# Ensure that \ref conf_spi_master.h is present for the driver.
+ *  - \note This file is only for the driver and should not be included by the
+ * user. In this example the file can be left empty.
+ * -# Initialize the pins used by the SPI interface (this initialization is for
+ * the ATxmega32A4U device).
+ *  -# Set the pin used for slave select as output high:
+ *    \code
+	ioport_configure_port_pin(&PORTD, PIN1_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+\endcode
+ *  -# Enable pull-up on own chip select (SS):
+ *    \code
+	ioport_configure_port_pin(&PORTD, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT);
+\endcode
+ *    \attention If this pin is pulled low the SPI module will go into slave mode.
+ *  -# Set MOSI and SCL as output high, and set MISO as input:
+ *    \code
+	ioport_configure_port_pin(&PORTD, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+	ioport_configure_port_pin(&PORTD, PIN6_bm, IOPORT_DIR_INPUT);
+	ioport_configure_port_pin(&PORTD, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+\endcode
+ * -# Define the SPI device configuration struct to describe which pin the
+ * slave select (slave chip select) is connected to, in this case the slave
+ * select pin has been connected to PORTD pin 1 (PD1):
+ *  - \code
+	struct spi_device spi_device_conf = {
+	    .id = IOPORT_CREATE_PIN(PORTD, 1)
+	};
+\endcode
+ * -# Initialize the SPI module, in this case SPI on PORTD has been chosen:
+ *  - \code
+	spi_master_init(&SPID);
+\endcode
+ * -# Setup the SPI master module for a specific device:
+ *  - \code
+	spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0);
+\endcode
+ *  - \note The last argument, which is zero in this case, can be ignored and is
+ *  only included for compatibility purposes.
+ * -# Then enable the SPI:
+ *  - \code
+	spi_enable(&SPID);
+\endcode
+ *
+ * \section spi_master_xmega_basic_usage Usage steps
+ * \subsection spi_master_xmega_basic_usage_code Example code
+ * Add to, e.g., the main loop in the application C-file:
+ * \code
+	   uint8_t data_buffer[1] = {0xAA};
+
+	   struct spi_device spi_device_conf = {
+	       .id = IOPORT_CREATE_PIN(PORTD, 1)
+	   };
+
+	   spi_select_device(&SPID, &spi_device_conf);
+
+	   spi_write_packet(&SPID, data_buffer, 1);
+	   spi_read_packet(&SPID, data_buffer, 1);
+
+	   spi_deselect_device(&SPID, &spi_device_conf);
+\endcode
+ *
+ * \subsection spi_master_xmega_basic_usage_flow Workflow
+ * -# Create a buffer for data to be sent/received on the SPI bus, in this case
+ * a single byte buffer is used. The buffer can be of arbitrary size as long as
+ * there is space left in SRAM:
+ *  - \code
+	uint8_t data_buffer[1] = {0xAA};
+\endcode
+ * -# Define the SPI device configuration struct to describe which pin the
+ * slave select (slave chip select) is connected to, in this case the slave
+ * select pin has been connected to PORTD pin 1 (PD1):
+ *  - \code
+	struct spi_device spi_device_conf = {
+	    .id = IOPORT_CREATE_PIN(PORTD, 1)
+	};
+\endcode
+ *  - \note As this struct is the same for both the initializing part and the usage
+ * part it could be a good idea to make the struct global, and hence accessible
+ * for both the initializing part and usage part. Another solution could be to
+ * create the struct in the main function and pass the address of the struct to
+ * the spi_init_module() function, e.g.:
+ *  \code
+	   void spi_init_module(struct spi_device *spi_device_conf)
+	   {
+	       ...
+
+	       spi_master_setup_device(&SPID, spi_device_conf, SPI_MODE_0, 1000000, 0);
+
+	       ...
+	   }
+\endcode
+ * -# Write data to the SPI slave device, in this case write one byte from the
+ * data_buffer:
+ *  - \code
+	spi_write_packet(&SPID, data_buffer, 1);
+\endcode
+ * -# Read data from the SPI slave device, in this case read one byte and put it
+ * into the data_buffer:
+ *  - \code
+	spi_read_packet(&SPID, data_buffer, 1);
+\endcode
+ *  - \attention As the SPI works as a shift register so that data is shifted in at
+ * the same time as data is shifted out a read operation will mean that a dummy
+ * byte \ref CONFIG_SPI_MASTER_DUMMY is written to the SPI bus. \ref CONFIG_SPI_MASTER_DUMMY
+ * defaults to 0xFF, but can be changed by defining it inside the \ref conf_spi_master.h
+ * file.
+ * -# When read and write operations is done de-select the slave:
+ *  - \code
+	spi_deselect_device(&SPID, &spi_device_conf);
+\endcode
+ *
+ */
+
+#endif /* SPI_MASTER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/usart_spi.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/usart_spi.h
new file mode 100644
index 0000000000..92b407ff5c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/usart_spi.h
@@ -0,0 +1,104 @@
+/**
+ * \file
+ *
+ * \brief USART in SPI mode driver functions.
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef USART_SPI_H_INCLUDED
+#define USART_SPI_H_INCLUDED
+
+#include <parts.h>
+
+#if XMEGA
+# include "xmega_usart_spi/usart_spi.h"
+#elif MEGA_RF
+# include "megarf_usart_spi/usart_spi.h"
+#elif UC3
+# include "uc3_usart_spi/usart_spi.h"
+#elif SAM
+# include "sam_usart_spi/usart_spi.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup usart_spi_group USART in SPI (Serial Peripheral Interface) mode
+ *
+ * This is the common API for USART in SPI mode. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section spi_group_platform Platform Dependencies
+ *
+ * The spi API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - usart_spi_init()
+ *   - usart_spi_setup_device()
+ *   - usart_spi_select_device()
+ *   - usart_spi_deselect_device()
+ *   - usart_spi_write_single()
+ *   - usart_spi_write_packet()
+ *   - usart_spi_read_single()
+ *   - usart_spi_read_packet()
+ *   - usart_spi_is_tx_empty()
+ *   - usart_spi_is_tx_ready()
+ *   - usart_spi_is_rx_full()
+ *   - usart_spi_is_rx_ready()
+ *   - usart_spi_enable()
+ *   - usart_spi_disable()
+ *   - usart_spi_is_enabled()
+ *
+ *
+ * @{
+ */
+
+//! @}
+
+#endif /* USART_SPI_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.c b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.c
new file mode 100644
index 0000000000..9b3b52b703
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.c
@@ -0,0 +1,644 @@
+/*****************************************************************************
+ *
+ * \file
+ *
+ * \brief Abstraction layer for memory interfaces.
+ *
+ * This module contains the interfaces:
+ *   - MEM <-> USB;
+ *   - MEM <-> RAM;
+ *   - MEM <-> MEM.
+ *
+ * This module may be configured and expanded to support the following features:
+ *   - write-protected globals;
+ *   - password-protected data;
+ *   - specific features;
+ *   - etc.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+//_____ I N C L U D E S ____________________________________________________
+
+#include "compiler.h"
+#include "preprocessor.h"
+#ifdef FREERTOS_USED
+#include "FreeRTOS.h"
+#include "semphr.h"
+#endif
+#include "ctrl_access.h"
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+#ifdef FREERTOS_USED
+
+/*! \name LUN Access Protection Macros
+ */
+//! @{
+
+/*! \brief Locks accesses to LUNs.
+ *
+ * \return \c true if the access was successfully locked, else \c false.
+ */
+#define Ctrl_access_lock()    ctrl_access_lock()
+
+/*! \brief Unlocks accesses to LUNs.
+ */
+#define Ctrl_access_unlock()  xSemaphoreGive(ctrl_access_semphr)
+
+//! @}
+
+//! Handle to the semaphore protecting accesses to LUNs.
+static xSemaphoreHandle ctrl_access_semphr = NULL;
+
+#else
+
+/*! \name LUN Access Protection Macros
+ */
+//! @{
+
+/*! \brief Locks accesses to LUNs.
+ *
+ * \return \c true if the access was successfully locked, else \c false.
+ */
+#define Ctrl_access_lock()    true
+
+/*! \brief Unlocks accesses to LUNs.
+ */
+#define Ctrl_access_unlock()
+
+//! @}
+
+#endif  // FREERTOS_USED
+
+
+#if MAX_LUN
+
+/*! \brief Initializes an entry of the LUN descriptor table.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return LUN descriptor table entry initializer.
+ */
+#if ACCESS_USB == true && ACCESS_MEM_TO_RAM == true
+#define Lun_desc_entry(lun) \
+  {\
+    TPASTE3(Lun_, lun, _test_unit_ready),\
+    TPASTE3(Lun_, lun, _read_capacity),\
+    TPASTE3(Lun_, lun, _unload),\
+    TPASTE3(Lun_, lun, _wr_protect),\
+    TPASTE3(Lun_, lun, _removal),\
+    TPASTE3(Lun_, lun, _usb_read_10),\
+    TPASTE3(Lun_, lun, _usb_write_10),\
+    TPASTE3(Lun_, lun, _mem_2_ram),\
+    TPASTE3(Lun_, lun, _ram_2_mem),\
+    TPASTE3(LUN_, lun, _NAME)\
+  }
+#elif ACCESS_USB == true
+#define Lun_desc_entry(lun) \
+  {\
+    TPASTE3(Lun_, lun, _test_unit_ready),\
+    TPASTE3(Lun_, lun, _read_capacity),\
+    TPASTE3(Lun_, lun, _unload),\
+    TPASTE3(Lun_, lun, _wr_protect),\
+    TPASTE3(Lun_, lun, _removal),\
+    TPASTE3(Lun_, lun, _usb_read_10),\
+    TPASTE3(Lun_, lun, _usb_write_10),\
+    TPASTE3(LUN_, lun, _NAME)\
+  }
+#elif ACCESS_MEM_TO_RAM == true
+#define Lun_desc_entry(lun) \
+  {\
+    TPASTE3(Lun_, lun, _test_unit_ready),\
+    TPASTE3(Lun_, lun, _read_capacity),\
+    TPASTE3(Lun_, lun, _unload),\
+    TPASTE3(Lun_, lun, _wr_protect),\
+    TPASTE3(Lun_, lun, _removal),\
+    TPASTE3(Lun_, lun, _mem_2_ram),\
+    TPASTE3(Lun_, lun, _ram_2_mem),\
+    TPASTE3(LUN_, lun, _NAME)\
+  }
+#else
+#define Lun_desc_entry(lun) \
+  {\
+    TPASTE3(Lun_, lun, _test_unit_ready),\
+    TPASTE3(Lun_, lun, _read_capacity),\
+    TPASTE3(Lun_, lun, _unload),\
+    TPASTE3(Lun_, lun, _wr_protect),\
+    TPASTE3(Lun_, lun, _removal),\
+    TPASTE3(LUN_, lun, _NAME)\
+  }
+#endif
+
+//! LUN descriptor table.
+static const struct
+{
+  Ctrl_status (*test_unit_ready)(void);
+  Ctrl_status (*read_capacity)(U32 *);
+  bool (*unload)(bool);
+  bool (*wr_protect)(void);
+  bool (*removal)(void);
+#if ACCESS_USB == true
+  Ctrl_status (*usb_read_10)(U32, U16);
+  Ctrl_status (*usb_write_10)(U32, U16);
+#endif
+#if ACCESS_MEM_TO_RAM == true
+  Ctrl_status (*mem_2_ram)(U32, void *);
+  Ctrl_status (*ram_2_mem)(U32, const void *);
+#endif
+  const char *name;
+} lun_desc[MAX_LUN] =
+{
+#if LUN_0 == ENABLE
+# ifndef Lun_0_unload
+#  define Lun_0_unload NULL
+# endif
+  Lun_desc_entry(0),
+#endif
+#if LUN_1 == ENABLE
+# ifndef Lun_1_unload
+#  define Lun_1_unload NULL
+# endif
+  Lun_desc_entry(1),
+#endif
+#if LUN_2 == ENABLE
+# ifndef Lun_2_unload
+#  define Lun_2_unload NULL
+# endif
+  Lun_desc_entry(2),
+#endif
+#if LUN_3 == ENABLE
+# ifndef Lun_3_unload
+#  define Lun_3_unload NULL
+# endif
+  Lun_desc_entry(3),
+#endif
+#if LUN_4 == ENABLE
+# ifndef Lun_4_unload
+#  define Lun_4_unload NULL
+# endif
+  Lun_desc_entry(4),
+#endif
+#if LUN_5 == ENABLE
+# ifndef Lun_5_unload
+#  define Lun_5_unload NULL
+# endif
+  Lun_desc_entry(5),
+#endif
+#if LUN_6 == ENABLE
+# ifndef Lun_6_unload
+#  define Lun_6_unload NULL
+# endif
+  Lun_desc_entry(6),
+#endif
+#if LUN_7 == ENABLE
+# ifndef Lun_7_unload
+#  define Lun_7_unload NULL
+# endif
+  Lun_desc_entry(7)
+#endif
+};
+
+#endif
+
+
+#if GLOBAL_WR_PROTECT == true
+bool g_wr_protect;
+#endif
+
+
+/*! \name Control Interface
+ */
+//! @{
+
+
+#ifdef FREERTOS_USED
+
+bool ctrl_access_init(void)
+{
+  // If the handle to the protecting semaphore is not valid,
+  if (!ctrl_access_semphr)
+  {
+    // try to create the semaphore.
+    vSemaphoreCreateBinary(ctrl_access_semphr);
+
+    // If the semaphore could not be created, there is no backup solution.
+    if (!ctrl_access_semphr) return false;
+  }
+
+  return true;
+}
+
+
+/*! \brief Locks accesses to LUNs.
+ *
+ * \return \c true if the access was successfully locked, else \c false.
+ */
+static bool ctrl_access_lock(void)
+{
+  // If the semaphore could not be created, there is no backup solution.
+  if (!ctrl_access_semphr) return false;
+
+  // Wait for the semaphore.
+  while (!xSemaphoreTake(ctrl_access_semphr, portMAX_DELAY));
+
+  return true;
+}
+
+#endif  // FREERTOS_USED
+
+
+U8 get_nb_lun(void)
+{
+#if MEM_USB == ENABLE
+#  ifndef Lun_usb_get_lun
+#    define Lun_usb_get_lun()  host_get_lun()
+#  endif
+  U8 nb_lun;
+
+  if (!Ctrl_access_lock()) return MAX_LUN;
+
+  nb_lun = MAX_LUN + Lun_usb_get_lun();
+
+  Ctrl_access_unlock();
+
+  return nb_lun;
+#else
+  return MAX_LUN;
+#endif
+}
+
+
+U8 get_cur_lun(void)
+{
+  return LUN_ID_0;
+}
+
+
+Ctrl_status mem_test_unit_ready(U8 lun)
+{
+  Ctrl_status status;
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  status =
+#if MAX_LUN
+         (lun < MAX_LUN) ? lun_desc[lun].test_unit_ready() :
+#endif
+#if LUN_USB == ENABLE
+                             Lun_usb_test_unit_ready(lun - LUN_ID_USB);
+#else
+                             CTRL_FAIL;
+#endif
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector)
+{
+  Ctrl_status status;
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  status =
+#if MAX_LUN
+         (lun < MAX_LUN) ? lun_desc[lun].read_capacity(u32_nb_sector) :
+#endif
+#if LUN_USB == ENABLE
+                             Lun_usb_read_capacity(lun - LUN_ID_USB, u32_nb_sector);
+#else
+                             CTRL_FAIL;
+#endif
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+U8 mem_sector_size(U8 lun)
+{
+  U8 sector_size;
+
+  if (!Ctrl_access_lock()) return 0;
+
+  sector_size =
+#if MAX_LUN
+              (lun < MAX_LUN) ? 1 :
+#endif
+#if LUN_USB == ENABLE
+                                  Lun_usb_read_sector_size(lun - LUN_ID_USB);
+#else
+                                  0;
+#endif
+
+  Ctrl_access_unlock();
+
+  return sector_size;
+}
+
+
+bool mem_unload(U8 lun, bool unload)
+{
+  bool unloaded;
+#if !MAX_LUN || !defined(Lun_usb_unload)
+  UNUSED(lun);
+#endif
+
+  if (!Ctrl_access_lock()) return false;
+
+  unloaded =
+#if MAX_LUN
+          (lun < MAX_LUN) ?
+              (lun_desc[lun].unload ?
+                  lun_desc[lun].unload(unload) : !unload) :
+#endif
+#if LUN_USB == ENABLE
+# if defined(Lun_usb_unload)
+              Lun_usb_unload(lun - LUN_ID_USB, unload);
+# else
+              !unload; /* Can not unload: load success, unload fail */
+# endif
+#else
+              false; /* No mem, unload/load fail */
+#endif
+
+  Ctrl_access_unlock();
+
+  return unloaded;
+}
+
+bool mem_wr_protect(U8 lun)
+{
+  bool wr_protect;
+
+  if (!Ctrl_access_lock()) return true;
+
+  wr_protect =
+#if MAX_LUN
+             (lun < MAX_LUN) ? lun_desc[lun].wr_protect() :
+#endif
+#if LUN_USB == ENABLE
+                                 Lun_usb_wr_protect(lun - LUN_ID_USB);
+#else
+                                 true;
+#endif
+
+  Ctrl_access_unlock();
+
+  return wr_protect;
+}
+
+
+bool mem_removal(U8 lun)
+{
+  bool removal;
+#if MAX_LUN==0
+  UNUSED(lun);
+#endif
+
+  if (!Ctrl_access_lock()) return true;
+
+  removal =
+#if MAX_LUN
+          (lun < MAX_LUN) ? lun_desc[lun].removal() :
+#endif
+#if LUN_USB == ENABLE
+                              Lun_usb_removal();
+#else
+                              true;
+#endif
+
+  Ctrl_access_unlock();
+
+  return removal;
+}
+
+
+const char *mem_name(U8 lun)
+{
+#if MAX_LUN==0
+  UNUSED(lun);
+#endif
+  return
+#if MAX_LUN
+       (lun < MAX_LUN) ? lun_desc[lun].name :
+#endif
+#if LUN_USB == ENABLE
+                           LUN_USB_NAME;
+#else
+                           NULL;
+#endif
+}
+
+
+//! @}
+
+
+#if ACCESS_USB == true
+
+/*! \name MEM <-> USB Interface
+ */
+//! @{
+
+
+Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector)
+{
+  Ctrl_status status;
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  memory_start_read_action(nb_sector);
+  status =
+#if MAX_LUN
+           (lun < MAX_LUN) ? lun_desc[lun].usb_read_10(addr, nb_sector) :
+#endif
+                             CTRL_FAIL;
+  memory_stop_read_action();
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector)
+{
+  Ctrl_status status;
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  memory_start_write_action(nb_sector);
+  status =
+#if MAX_LUN
+           (lun < MAX_LUN) ? lun_desc[lun].usb_write_10(addr, nb_sector) :
+#endif
+                             CTRL_FAIL;
+  memory_stop_write_action();
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+//! @}
+
+#endif  // ACCESS_USB == true
+
+
+#if ACCESS_MEM_TO_RAM == true
+
+/*! \name MEM <-> RAM Interface
+ */
+//! @{
+
+
+Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram)
+{
+  Ctrl_status status;
+#if MAX_LUN==0
+  UNUSED(lun);
+#endif
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  memory_start_read_action(1);
+  status =
+#if MAX_LUN
+           (lun < MAX_LUN) ? lun_desc[lun].mem_2_ram(addr, ram) :
+#endif
+#if LUN_USB == ENABLE
+                             Lun_usb_mem_2_ram(addr, ram);
+#else
+                             CTRL_FAIL;
+#endif
+  memory_stop_read_action();
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram)
+{
+  Ctrl_status status;
+#if MAX_LUN==0
+  UNUSED(lun);
+#endif
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  memory_start_write_action(1);
+  status =
+#if MAX_LUN
+           (lun < MAX_LUN) ? lun_desc[lun].ram_2_mem(addr, ram) :
+#endif
+#if LUN_USB == ENABLE
+                             Lun_usb_ram_2_mem(addr, ram);
+#else
+                             CTRL_FAIL;
+#endif
+  memory_stop_write_action();
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+//! @}
+
+#endif  // ACCESS_MEM_TO_RAM == true
+
+
+#if ACCESS_STREAM == true
+
+/*! \name Streaming MEM <-> MEM Interface
+ */
+//! @{
+
+
+  #if ACCESS_MEM_TO_MEM == true
+
+#include "fat.h"
+
+Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector)
+{
+  COMPILER_ALIGNED(4)
+  static U8 sector_buf[FS_512B];
+  Ctrl_status status = CTRL_GOOD;
+
+  while (nb_sector--)
+  {
+    if ((status = memory_2_ram(src_lun, src_addr++, sector_buf)) != CTRL_GOOD) break;
+    if ((status = ram_2_memory(dest_lun, dest_addr++, sector_buf)) != CTRL_GOOD) break;
+  }
+
+  return status;
+}
+
+  #endif  // ACCESS_MEM_TO_MEM == true
+
+
+Ctrl_status stream_state(U8 id)
+{
+  UNUSED(id);
+  return CTRL_GOOD;
+}
+
+
+U16 stream_stop(U8 id)
+{
+  UNUSED(id);
+  return 0;
+}
+
+
+//! @}
+
+#endif  // ACCESS_STREAM == true
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.h b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.h
new file mode 100644
index 0000000000..af6c8ceb96
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.h
@@ -0,0 +1,402 @@
+/*****************************************************************************
+ *
+ * \file
+ *
+ * \brief Abstraction layer for memory interfaces.
+ *
+ * This module contains the interfaces:
+ *   - MEM <-> USB;
+ *   - MEM <-> RAM;
+ *   - MEM <-> MEM.
+ *
+ * This module may be configured and expanded to support the following features:
+ *   - write-protected globals;
+ *   - password-protected data;
+ *   - specific features;
+ *   - etc.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef _CTRL_ACCESS_H_
+#define _CTRL_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup group_common_services_storage_ctrl_access Memory Control Access
+ *
+ * Common abstraction layer for memory interfaces. It provides interfaces between:
+ * Memory and USB, Memory and RAM, Memory and Memory. Common API for XMEGA and UC3.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+#include "conf_access.h"
+
+#ifndef SECTOR_SIZE
+#define SECTOR_SIZE  512
+#endif
+
+//! Status returned by CTRL_ACCESS interfaces.
+typedef enum
+{
+  CTRL_GOOD       = PASS,     //!< Success, memory ready.
+  CTRL_FAIL       = FAIL,     //!< An error occurred.
+  CTRL_NO_PRESENT = FAIL + 1, //!< Memory unplugged.
+  CTRL_BUSY       = FAIL + 2  //!< Memory not initialized or changed.
+} Ctrl_status;
+
+
+// FYI: Each Logical Unit Number (LUN) corresponds to a memory.
+
+// Check LUN defines.
+#ifndef LUN_0
+  #error LUN_0 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_1
+  #error LUN_1 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_2
+  #error LUN_2 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_3
+  #error LUN_3 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_4
+  #error LUN_4 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_5
+  #error LUN_5 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_6
+  #error LUN_6 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_7
+  #error LUN_7 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_USB
+  #error LUN_USB must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+
+/*! \name LUN IDs
+ */
+//! @{
+#define LUN_ID_0        (0)                 //!< First static LUN.
+#define LUN_ID_1        (LUN_ID_0 + LUN_0)
+#define LUN_ID_2        (LUN_ID_1 + LUN_1)
+#define LUN_ID_3        (LUN_ID_2 + LUN_2)
+#define LUN_ID_4        (LUN_ID_3 + LUN_3)
+#define LUN_ID_5        (LUN_ID_4 + LUN_4)
+#define LUN_ID_6        (LUN_ID_5 + LUN_5)
+#define LUN_ID_7        (LUN_ID_6 + LUN_6)
+#define MAX_LUN         (LUN_ID_7 + LUN_7)  //!< Number of static LUNs.
+#define LUN_ID_USB      (MAX_LUN)           //!< First dynamic LUN (USB host mass storage).
+//! @}
+
+
+// Include LUN header files.
+#if LUN_0 == ENABLE
+  #include LUN_0_INCLUDE
+#endif
+#if LUN_1 == ENABLE
+  #include LUN_1_INCLUDE
+#endif
+#if LUN_2 == ENABLE
+  #include LUN_2_INCLUDE
+#endif
+#if LUN_3 == ENABLE
+  #include LUN_3_INCLUDE
+#endif
+#if LUN_4 == ENABLE
+  #include LUN_4_INCLUDE
+#endif
+#if LUN_5 == ENABLE
+  #include LUN_5_INCLUDE
+#endif
+#if LUN_6 == ENABLE
+  #include LUN_6_INCLUDE
+#endif
+#if LUN_7 == ENABLE
+  #include LUN_7_INCLUDE
+#endif
+#if LUN_USB == ENABLE
+  #include LUN_USB_INCLUDE
+#endif
+
+
+// Check the configuration of write protection in conf_access.h.
+#ifndef GLOBAL_WR_PROTECT
+  #error GLOBAL_WR_PROTECT must be defined as true or false in conf_access.h
+#endif
+
+
+#if GLOBAL_WR_PROTECT == true
+
+//! Write protect.
+extern bool g_wr_protect;
+
+#endif
+
+
+/*! \name Control Interface
+ */
+//! @{
+
+#ifdef FREERTOS_USED
+
+/*! \brief Initializes the LUN access locker.
+ *
+ * \return \c true if the locker was successfully initialized, else \c false.
+ */
+extern bool ctrl_access_init(void);
+
+#endif  // FREERTOS_USED
+
+/*! \brief Returns the number of LUNs.
+ *
+ * \return Number of LUNs in the system.
+ */
+extern U8 get_nb_lun(void);
+
+/*! \brief Returns the current LUN.
+ *
+ * \return Current LUN.
+ *
+ * \todo Implement.
+ */
+extern U8 get_cur_lun(void);
+
+/*! \brief Tests the memory state and initializes the memory if required.
+ *
+ * The TEST UNIT READY SCSI primary command allows an application client to poll
+ * a LUN until it is ready without having to allocate memory for returned data.
+ *
+ * This command may be used to check the media status of LUNs with removable
+ * media.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return Status.
+ */
+extern Ctrl_status mem_test_unit_ready(U8 lun);
+
+/*! \brief Returns the address of the last valid sector (512 bytes) in the
+ *         memory.
+ *
+ * \param lun           Logical Unit Number.
+ * \param u32_nb_sector Pointer to the address of the last valid sector.
+ *
+ * \return Status.
+ */
+extern Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector);
+
+/*! \brief Returns the size of the physical sector.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return Sector size (unit: 512 bytes).
+ */
+extern U8 mem_sector_size(U8 lun);
+
+/*! \brief Unload/load the medium.
+ *
+ * \param lun Logical Unit Number.
+ * \param unload \c true to unload the medium, \c false to load the medium.
+ *
+ * \return \c true if unload/load success, else \c false.
+ */
+extern bool mem_unload(U8 lun, bool unload);
+
+/*! \brief Returns the write-protection state of the memory.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return \c true if the memory is write-protected, else \c false.
+ *
+ * \note Only used by removable memories with hardware-specific write
+ *       protection.
+ */
+extern bool mem_wr_protect(U8 lun);
+
+/*! \brief Tells whether the memory is removable.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return \c true if the memory is removable, else \c false.
+ */
+extern bool mem_removal(U8 lun);
+
+/*! \brief Returns a pointer to the LUN name.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return Pointer to the LUN name string.
+ */
+extern const char *mem_name(U8 lun);
+
+//! @}
+
+
+#if ACCESS_USB == true
+
+/*! \name MEM <-> USB Interface
+ */
+//! @{
+
+/*! \brief Transfers data from the memory to USB.
+ *
+ * \param lun       Logical Unit Number.
+ * \param addr      Address of first memory sector to read.
+ * \param nb_sector Number of sectors to transfer.
+ *
+ * \return Status.
+ */
+extern Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector);
+
+/*! \brief Transfers data from USB to the memory.
+ *
+ * \param lun       Logical Unit Number.
+ * \param addr      Address of first memory sector to write.
+ * \param nb_sector Number of sectors to transfer.
+ *
+ * \return Status.
+ */
+extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector);
+
+//! @}
+
+#endif  // ACCESS_USB == true
+
+
+#if ACCESS_MEM_TO_RAM == true
+
+/*! \name MEM <-> RAM Interface
+ */
+//! @{
+
+/*! \brief Copies 1 data sector from the memory to RAM.
+ *
+ * \param lun   Logical Unit Number.
+ * \param addr  Address of first memory sector to read.
+ * \param ram   Pointer to RAM buffer to write.
+ *
+ * \return Status.
+ */
+extern Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram);
+
+/*! \brief Copies 1 data sector from RAM to the memory.
+ *
+ * \param lun   Logical Unit Number.
+ * \param addr  Address of first memory sector to write.
+ * \param ram   Pointer to RAM buffer to read.
+ *
+ * \return Status.
+ */
+extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram);
+
+//! @}
+
+#endif  // ACCESS_MEM_TO_RAM == true
+
+
+#if ACCESS_STREAM == true
+
+/*! \name Streaming MEM <-> MEM Interface
+ */
+//! @{
+
+//! Erroneous streaming data transfer ID.
+#define ID_STREAM_ERR         0xFF
+
+  #if ACCESS_MEM_TO_MEM == true
+
+/*! \brief Copies data from one memory to another.
+ *
+ * \param src_lun   Source Logical Unit Number.
+ * \param src_addr  Source address of first memory sector to read.
+ * \param dest_lun  Destination Logical Unit Number.
+ * \param dest_addr Destination address of first memory sector to write.
+ * \param nb_sector Number of sectors to copy.
+ *
+ * \return Status.
+ */
+extern Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector);
+
+  #endif  // ACCESS_MEM_TO_MEM == true
+
+/*! \brief Returns the state of a streaming data transfer.
+ *
+ * \param id  Transfer ID.
+ *
+ * \return Status.
+ *
+ * \todo Implement.
+ */
+extern Ctrl_status stream_state(U8 id);
+
+/*! \brief Stops a streaming data transfer.
+ *
+ * \param id  Transfer ID.
+ *
+ * \return Number of remaining sectors.
+ *
+ * \todo Implement.
+ */
+extern U16 stream_stop(U8 id);
+
+//! @}
+
+#endif  // ACCESS_STREAM == true
+
+/**
+ * \}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _CTRL_ACCESS_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/module_config/conf_access.h b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/module_config/conf_access.h
new file mode 100644
index 0000000000..25e376c84a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/module_config/conf_access.h
@@ -0,0 +1,282 @@
+/*****************************************************************************
+ *
+ * \file
+ *
+ * \brief Memory access control configuration file.
+ *
+ * This file contains the possible external configuration of the memory access
+ * control.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+ //! Configuration of ctrl_access which is an abstraction layer for memory interfaces (common/services/storage/ctrl_access)
+
+#ifndef _CONF_ACCESS_H_
+#define _CONF_ACCESS_H_
+
+#include "compiler.h"
+#include "board.h"
+
+
+/*! \name Activation of Logical Unit Numbers
+ */
+//! @{
+#ifdef VIRTUAL_MEMORY_ENABLE
+#define LUN_0                ENABLE   //!< Enable On-Chip Virtual Memory.
+#else
+#define LUN_0                DISABLE  //!< Disable On-Chip Virtual Memory.
+#endif
+
+#ifdef AT45DBX_ENABLE
+#define LUN_1                ENABLE   //!< Enable AT45DBX Data Flash.
+#else
+#define LUN_1                DISABLE  //!< Disable AT45DBX Data Flash.
+#endif
+
+//! New setting for SD/MMC stack in common folder
+#ifdef SD_MMC_ENABLE
+#define LUN_2                ENABLE   //!< Enable common SD/MMC stack
+#define LUN_3                ENABLE
+#else
+#define LUN_2                DISABLE  //!< Disable common SD/MMC stack
+#define LUN_3                DISABLE
+#endif
+
+//! Old setting for SD/MMC stack in AVR folder
+#ifdef SD_MMC_SPI_ENABLE
+#define LUN_4                ENABLE   //!< Enable SD/MMC Card over SPI or SPI.
+#else
+#define LUN_4                DISABLE  //!< Disable SD/MMC Card over SPI or SPI.
+#endif
+
+//! Old setting for SD/MMC stack in AVR folder
+#ifdef SD_MMC_MCI_ENABLE
+#define LUN_5                ENABLE   //!< Enable SD/MMC Card over MCI or MCI.
+#else
+#define LUN_5                DISABLE  //!< Disable SD/MMC Card over MCI or MCI.
+#endif
+
+#define LUN_6                DISABLE
+#define LUN_7                DISABLE
+
+#ifdef USB_MASS_STORAGE_ENABLE
+#define LUN_USB              ENABLE   //!< Enable Host Mass-Storage Memory.
+#else
+#define LUN_USB              DISABLE  //!< Disable Host Mass-Storage Memory.
+#endif
+
+//! @}
+
+/*! \name LUN 0 Definitions
+ */
+//! @{
+#define VIRTUAL_MEM                             LUN_0
+#define LUN_ID_VIRTUAL_MEM                      LUN_ID_0
+#define LUN_0_INCLUDE                           "virtual_mem.h"
+#define Lun_0_test_unit_ready                   virtual_test_unit_ready
+#define Lun_0_read_capacity                     virtual_read_capacity
+#define Lun_0_unload                            NULL /* Can not be unloaded */
+#define Lun_0_wr_protect                        virtual_wr_protect
+#define Lun_0_removal                           virtual_removal
+#define Lun_0_usb_read_10                       virtual_usb_read_10
+#define Lun_0_usb_write_10                      virtual_usb_write_10
+#define Lun_0_mem_2_ram                         virtual_mem_2_ram
+#define Lun_0_ram_2_mem                         virtual_ram_2_mem
+#define LUN_0_NAME                              "\"On-Chip Virtual Memory\""
+//! @}
+
+/*! \name LUN 1 Definitions
+ */
+//! @{
+#define AT45DBX_MEM                             LUN_1
+#define LUN_ID_AT45DBX_MEM                      LUN_ID_1
+#define LUN_1_INCLUDE                           "at45dbx_mem.h"
+#define Lun_1_test_unit_ready                   at45dbx_test_unit_ready
+#define Lun_1_read_capacity                     at45dbx_read_capacity
+#define Lun_1_unload                            NULL /* Can not be unloaded */
+#define Lun_1_wr_protect                        at45dbx_wr_protect
+#define Lun_1_removal                           at45dbx_removal
+#define Lun_1_usb_read_10                       at45dbx_usb_read_10
+#define Lun_1_usb_write_10                      at45dbx_usb_write_10
+#define Lun_1_mem_2_ram                         at45dbx_df_2_ram
+#define Lun_1_ram_2_mem                         at45dbx_ram_2_df
+#define LUN_1_NAME                              "\"AT45DBX Data Flash\""
+//! @}
+
+/*! \name LUN 2 Definitions
+ */
+//! @{
+#define SD_MMC_0_MEM                            LUN_2
+#define LUN_ID_SD_MMC_0_MEM                     LUN_ID_2
+#define LUN_2_INCLUDE                           "sd_mmc_mem.h"
+#define Lun_2_test_unit_ready                   sd_mmc_test_unit_ready_0
+#define Lun_2_read_capacity                     sd_mmc_read_capacity_0
+#define Lun_2_unload                            sd_mmc_unload_0
+#define Lun_2_wr_protect                        sd_mmc_wr_protect_0
+#define Lun_2_removal                           sd_mmc_removal_0
+#define Lun_2_usb_read_10                       sd_mmc_usb_read_10_0
+#define Lun_2_usb_write_10                      sd_mmc_usb_write_10_0
+#define Lun_2_mem_2_ram                         sd_mmc_mem_2_ram_0
+#define Lun_2_ram_2_mem                         sd_mmc_ram_2_mem_0
+#define LUN_2_NAME                              "\"SD/MMC Card Slot 0\""
+//! @}
+
+/*! \name LUN 3 Definitions
+ */
+//! @{
+#define SD_MMC_1_MEM                            LUN_3
+#define LUN_ID_SD_MMC_1_MEM                     LUN_ID_3
+#define LUN_3_INCLUDE                           "sd_mmc_mem.h"
+#define Lun_3_test_unit_ready                   sd_mmc_test_unit_ready_1
+#define Lun_3_read_capacity                     sd_mmc_read_capacity_1
+#define Lun_3_unload                            sd_mmc_unload_1
+#define Lun_3_wr_protect                        sd_mmc_wr_protect_1
+#define Lun_3_removal                           sd_mmc_removal_1
+#define Lun_3_usb_read_10                       sd_mmc_usb_read_10_1
+#define Lun_3_usb_write_10                      sd_mmc_usb_write_10_1
+#define Lun_3_mem_2_ram                         sd_mmc_mem_2_ram_1
+#define Lun_3_ram_2_mem                         sd_mmc_ram_2_mem_1
+#define LUN_3_NAME                              "\"SD/MMC Card Slot 1\""
+//! @}
+
+/*! \name LUN 4 Definitions
+ */
+//! @{
+#define SD_MMC_SPI_MEM                          LUN_4
+#define LUN_ID_SD_MMC_SPI_MEM                   LUN_ID_4
+#define LUN_4_INCLUDE                           "sd_mmc_spi_mem.h"
+#define Lun_4_test_unit_ready                   sd_mmc_spi_test_unit_ready
+#define Lun_4_read_capacity                     sd_mmc_spi_read_capacity
+#define Lun_4_unload                            NULL
+#define Lun_4_wr_protect                        sd_mmc_spi_wr_protect
+#define Lun_4_removal                           sd_mmc_spi_removal
+#define Lun_4_usb_read_10                       sd_mmc_spi_usb_read_10
+#define Lun_4_usb_write_10                      sd_mmc_spi_usb_write_10
+#define Lun_4_mem_2_ram                         sd_mmc_spi_mem_2_ram
+#define Lun_4_ram_2_mem                         sd_mmc_spi_ram_2_mem
+#define LUN_4_NAME                              "\"SD/MMC Card over SPI\""
+//! @}
+
+/*! \name LUN 5 Definitions
+ */
+//! @{
+#define SD_MMC_MCI_0_MEM                        LUN_5
+#define LUN_ID_SD_MMC_MCI_0_MEM                 LUN_ID_5
+#define LUN_5_INCLUDE                           "sd_mmc_mci_mem.h"
+#define Lun_5_test_unit_ready                   sd_mmc_mci_test_unit_ready_0
+#define Lun_5_read_capacity                     sd_mmc_mci_read_capacity_0
+#define Lun_5_unload                            NULL
+#define Lun_5_wr_protect                        sd_mmc_mci_wr_protect_0
+#define Lun_5_removal                           sd_mmc_mci_removal_0
+#define Lun_5_usb_read_10                       sd_mmc_mci_usb_read_10_0
+#define Lun_5_usb_write_10                      sd_mmc_mci_usb_write_10_0
+#define Lun_5_mem_2_ram                         sd_mmc_mci_mem_2_ram_0
+#define Lun_5_ram_2_mem                         sd_mmc_mci_ram_2_mem_0
+#define LUN_5_NAME                              "\"SD/MMC Card over MCI Slot 0\""
+//! @}
+
+/*! \name USB LUNs Definitions
+ */
+//! @{
+#define MEM_USB                                 LUN_USB
+#define LUN_ID_MEM_USB                          LUN_ID_USB
+#define LUN_USB_INCLUDE                         "uhi_msc_mem.h"
+#define Lun_usb_get_lun()                       uhi_msc_mem_get_lun()
+#define Lun_usb_test_unit_ready(lun)            uhi_msc_mem_test_unit_ready(lun)
+#define Lun_usb_read_capacity(lun, nb_sect)     uhi_msc_mem_read_capacity(lun, nb_sect)
+#define Lun_usb_read_sector_size(lun)           uhi_msc_mem_read_sector_size(lun)
+#define Lun_usb_unload                          NULL
+#define Lun_usb_wr_protect(lun)                 uhi_msc_mem_wr_protect(lun)
+#define Lun_usb_removal()                       uhi_msc_mem_removal()
+#define Lun_usb_mem_2_ram(addr, ram)            uhi_msc_mem_read_10_ram(addr, ram)
+#define Lun_usb_ram_2_mem(addr, ram)            uhi_msc_mem_write_10_ram(addr, ram)
+#define LUN_USB_NAME                            "\"Host Mass-Storage Memory\""
+//! @}
+
+/*! \name Actions Associated with Memory Accesses
+ *
+ * Write here the action to associate with each memory access.
+ *
+ * \warning Be careful not to waste time in order not to disturb the functions.
+ */
+//! @{
+#define memory_start_read_action(nb_sectors)
+#define memory_stop_read_action()
+#define memory_start_write_action(nb_sectors)
+#define memory_stop_write_action()
+//! @}
+
+/*! \name Activation of Interface Features
+ */
+//! @{
+#ifdef ACCESS_USB_ENABLED
+#define ACCESS_USB           true  //!< MEM <-> USB interface.
+#else
+#define ACCESS_USB           false //!< MEM <-> USB interface.
+#endif
+
+#ifdef ACCESS_MEM_TO_RAM_ENABLED
+#define ACCESS_MEM_TO_RAM    true  //!< MEM <-> RAM interface.
+#else
+#define ACCESS_MEM_TO_RAM    false //!< MEM <-> RAM interface.
+#endif
+
+#define ACCESS_STREAM        false //!< Streaming MEM <-> MEM interface.
+#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode.
+#define ACCESS_MEM_TO_MEM    false //!< MEM <-> MEM interface.
+#define ACCESS_CODEC         false //!< Codec interface.
+//! @}
+
+/*! \name Specific Options for Access Control
+ */
+//! @{
+#define GLOBAL_WR_PROTECT    false //!< Management of a global write protection.
+//! @}
+
+/*! \name Sector size option for different storage media.
+ */
+//! @{
+#define SECTOR_SIZE  512
+//! @}
+
+#endif  // _CONF_ACCESS_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.c b/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.c
new file mode 100644
index 0000000000..680bf780b4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.c
@@ -0,0 +1,329 @@
+/**
+ * \file
+ *
+ * \brief Hamming ECC software implementation.
+ *
+ * This file contains a software Hamming ECC implementation.
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "ecc-sw.h"
+
+/**
+ *  Count and return the number of bits set to '1' in the given byte.
+ *
+ *  \param byte  Byte to count.
+ */
+static uint32_t count_bits_in_byte(uint8_t byte)
+{
+	uint32_t count = 0;
+
+	while (byte > 0) {
+		if (byte & 1) {
+			count++;
+		}
+		byte >>= 1;
+	}
+
+	return count;
+}
+
+/**
+ *  Count and return the number of bits set to '1' in the given hamming code.
+ *
+ *  \param code  Hamming code.
+ */
+static uint32_t count_bits_in_code256(uint8_t *code)
+{
+	return count_bits_in_byte(code[0]) + count_bits_in_byte(code[1]) +
+			count_bits_in_byte(code[2]);
+}
+
+/**
+ *  Calculates the 22-bit hamming code for a 256-bytes block of data.
+ *
+ *  \param data  Data buffer to calculate code for.
+ *  \param code  Pointer to a buffer where the code should be stored.
+ */
+static void compute256(const uint8_t *data, uint8_t *code)
+{
+	uint32_t i;
+	uint8_t column_sum = 0;
+	uint8_t even_line_code = 0;
+	uint8_t odd_line_code = 0;
+	uint8_t even_column_code = 0;
+	uint8_t odd_column_code = 0;
+
+	/* 
+	 * Xor all bytes together to get the column sum.
+	 * At the same time, calculate the even and odd line codes.
+	 */
+	for (i = 0; i < 256; i++) {
+		column_sum ^= data[i];
+
+		/* 
+		 * If the xor sum of the byte is 0, then this byte has no incidence on
+		 * the computed code. So check if the sum is 1.
+		 */
+		if ((count_bits_in_byte(data[i]) & 1) == 1) {
+			/*
+			 * Parity groups are formed by forcing a particular index bit to 0
+			 * (even) or 1 (odd).
+			 * Example on one byte:
+			 *
+			 * bits (dec)  7   6   5   4   3   2   1   0
+			 *      (bin) 111 110 101 100 011 010 001 000
+			 *                            '---'---'---'----------.
+			 *                                                   |
+			 * groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4     |
+			 *        P2' ooooooo eeeeeee ooooooo eeeeeee P2     |
+			 *        P1' ooo eee ooo eee ooo eee ooo eee P1     |
+			 *                                                   |
+			 * We can see that:                                  |
+			 *  - P4  -> bit 2 of index is 0 --------------------'
+			 *  - P4' -> bit 2 of index is 1.
+			 *  - P2  -> bit 1 of index if 0.
+			 *  - etc...
+			 * We deduce that a bit position has an impact on all even Px if
+			 * the log2(x)nth bit of its index is 0
+			 *     ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)
+			 * and on all odd Px' if the log2(x)nth bit of its index is 1
+			 *     ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)
+			 *
+			 * As such, we calculate all the possible Px and Px' values at the
+			 * same time in two variables, even_line_code and odd_line_code, such as
+			 *     even_line_code bits: P128  P64  P32  P16  P8  P4  P2  P1
+			 *     odd_line_code  bits: P128' P64' P32' P16' P8' P4' P2' P1'
+			 */
+			even_line_code ^= (255 - i);
+			odd_line_code ^= i;
+		}
+	}
+
+	/*
+	 * At this point, we have the line parities, and the column sum. First, We
+	 * must calculate the parity group values on the column sum.
+	 */
+	for (i = 0; i < 8; i++) {
+		if (column_sum & 1) {
+			even_column_code ^= (7 - i);
+			odd_column_code ^= i;
+		}
+		column_sum >>= 1;
+	}
+
+	/*
+	 * Now, we must interleave the parity values, to obtain the following layout:
+	 * Code[0] = Line1
+	 * Code[1] = Line2
+	 * Code[2] = Column
+	 * Line = Px' Px P(x-1)- P(x-1) ...
+	 * Column = P4' P4 P2' P2 P1' P1 PadBit PadBit
+	 */
+	code[0] = 0;
+	code[1] = 0;
+	code[2] = 0;
+
+	for (i = 0; i < 4; i++) {
+		code[0] <<= 2;
+		code[1] <<= 2;
+		code[2] <<= 2;
+
+		/* Line 1 */
+		if ((odd_line_code & 0x80) != 0) {
+			code[0] |= 2;
+		}
+
+		if ((even_line_code & 0x80) != 0) {
+			code[0] |= 1;
+		}
+		/* Line 2 */
+		if ((odd_line_code & 0x08) != 0) {
+			code[1] |= 2;
+		}
+
+		if ((even_line_code & 0x08) != 0) {
+			code[1] |= 1;
+		}
+		/* Column */
+		if ((odd_column_code & 0x04) != 0) {
+			code[2] |= 2;
+		}
+
+		if ((even_column_code & 0x04) != 0) {
+			code[2] |= 1;
+		}
+
+		odd_line_code <<= 1;
+		even_line_code <<= 1;
+		odd_column_code <<= 1;
+		even_column_code <<= 1;
+	}
+
+	/* Invert codes (linux compatibility) */
+	code[0] = (~(uint32_t) code[0]);
+	code[1] = (~(uint32_t) code[1]);
+	code[2] = (~(uint32_t) code[2]);
+
+}
+
+/**
+ *  Verifies and corrects a 256-bytes block of data using the given 22-bits
+ *  hamming code.
+ *
+ *  \param puc_data  Pointer to data buffer to check.
+ *  \param puc_original_code  Pointer to hamming code to use for verifying the data.
+ *
+ *  \return 0 if there is no error, otherwise returns a HAMMING_ERROR code.
+ */
+static uint32_t verify256(uint8_t *puc_data, const uint8_t *puc_original_code)
+{
+	/* Calculate new code */
+	uint8_t computed_code[3];
+	uint8_t correction_code[3];
+
+	compute256(puc_data, computed_code);
+
+	/* Xor both codes together */
+	correction_code[0] = computed_code[0] ^ puc_original_code[0];
+	correction_code[1] = computed_code[1] ^ puc_original_code[1];
+	correction_code[2] = computed_code[2] ^ puc_original_code[2];
+
+
+	/* If all bytes are 0, there is no error */
+	if ((correction_code[0] == 0) && (correction_code[1] == 0)
+			&& (correction_code[2] == 0)) {
+		return 0;
+	}
+
+	/* If there is a single bit error, there are 11 bits set to 1 */
+	if (count_bits_in_code256(correction_code) == 11) {
+		/* Get byte and bit indexes */
+		uint8_t byte;
+		uint8_t bit;
+
+		byte = correction_code[0] & 0x80;
+		byte |= ((correction_code[0] << 1) & 0x40);
+		byte |= ((correction_code[0] << 2) & 0x20);
+		byte |= ((correction_code[0] << 3) & 0x10);
+
+		byte |= ((correction_code[1] >> 4) & 0x08);
+		byte |= ((correction_code[1] >> 3) & 0x04);
+		byte |= ((correction_code[1] >> 2) & 0x02);
+		byte |= ((correction_code[1] >> 1) & 0x01);
+
+		bit = (correction_code[2] >> 5) & 0x04;
+		bit |= ((correction_code[2] >> 4) & 0x02);
+		bit |= ((correction_code[2] >> 3) & 0x01);
+
+		/* Correct bit */
+		puc_data[byte] ^= (1 << bit);
+
+		return HAMMING_ERROR_SINGLE_BIT;
+	}
+
+	/* Check if ECC has been corrupted */
+	if (count_bits_in_code256(correction_code) == 1) {
+		return HAMMING_ERROR_ECC;
+	}
+	/* Otherwise, this is a multi-bit error */
+	else {
+		return HAMMING_ERROR_MULTIPLE_BITS;
+	}
+}
+
+/**
+ *  Computes 3-bytes hamming codes for a data block whose size is multiple of
+ *  256 bytes. Each 256 bytes block gets its own code.
+ *
+ *  \param puc_data Pointer to data to compute code for.
+ *  \param dw_size  Data size in bytes.
+ *  \param puc_code Pointer to codes buffer.
+ */
+void hamming_compute_256x(const uint8_t *puc_data, uint32_t dw_size,
+		uint8_t *puc_code)
+{
+	while (dw_size > 0) {
+		compute256(puc_data, puc_code);
+
+		puc_data += 256;
+		puc_code += 3;
+		dw_size -= 256;
+	}
+}
+
+/**
+ *  Verify 3-bytes hamming codes for a data block whose size is multiple of
+ *  256 bytes. Each 256-bytes block is verified with its own code.
+ *
+ *  \param puc_data Pointer to data buffer to verify.
+ *  \param dw_size  Size of the data in bytes.
+ *  \param puc_code Pointer to original codes.
+ *
+ *  \return 0 if the data is correct, HAMMING_ERROR_SINGLE_BIT if one or more
+ *  block(s) have had a single bit corrected, or either HAMMING_ERROR_ECC
+ *  or HAMMING_ERROR_MULTIPLE_BITS.
+ */
+uint32_t hamming_verify_256x(uint8_t *puc_data, uint32_t dw_size,
+		const uint8_t *puc_code)
+{
+	uint32_t error;
+	uint32_t result = 0;
+
+	while (dw_size > 0) {
+		error = verify256(puc_data, puc_code);
+
+		if (error == HAMMING_ERROR_SINGLE_BIT) {
+			result = HAMMING_ERROR_SINGLE_BIT;
+		} else {
+			if (error) {
+				return error;
+			}
+		}
+
+		puc_data += 256;
+		puc_code += 3;
+		dw_size -= 256;
+	}
+
+	return result;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.h b/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.h
new file mode 100644
index 0000000000..fed7e947a5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.h
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Hamming ECC software implementation.
+ *
+ * This file contains a software Hamming ECC implementation.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef ECC_SW_H_INCLUDED
+#define ECC_SW_H_INCLUDED
+
+#include "compiler.h"
+
+/**
+ *  These are the possible errors when trying to verify a block of data encoded
+ *  using a Hamming code:
+ *
+ *  \section Errors
+ *   - HAMMING_ERROR_SINGLE_BIT
+ *   - HAMMING_ERROR_ECC
+ *   - HAMMING_ERROR_MULTIPLE_BITS
+ */
+
+/*  A single bit was incorrect but has been recovered. */
+#define HAMMING_ERROR_SINGLE_BIT         1
+
+/* The original code has been corrupted. */
+#define HAMMING_ERROR_ECC               2
+
+/* Multiple bits are incorrect in the data and they cannot be corrected. */
+#define HAMMING_ERROR_MULTIPLE_BITS      3
+
+
+void hamming_compute_256x(const uint8_t *puc_data, uint32_t dw_size,
+		uint8_t *puc_code);
+uint32_t hamming_verify_256x(uint8_t *puc_data, uint32_t dw_size,
+		const uint8_t *puc_code);
+
+#endif /* ECC_SW_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_master.h
new file mode 100644
index 0000000000..c51d800941
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_master.h
@@ -0,0 +1,107 @@
+/**
+ * \file
+ *
+ * \brief TWI Master driver for SAM.
+ *
+ * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _TWI_MASTER_H_
+#define _TWI_MASTER_H_
+
+#include "twi.h"
+#include "sysclk.h"
+
+typedef Twi *twi_master_t;
+typedef twi_options_t twi_master_options_t;
+typedef twi_packet_t twi_package_t;
+
+static inline uint32_t twi_master_setup(twi_master_t p_twi,
+		twi_master_options_t *p_opt)
+{
+	p_opt->master_clk = sysclk_get_peripheral_hz();
+	p_opt->smbus      = 0;
+#if SAMG55
+	if (p_twi == TWI0) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM0);
+	} else if (p_twi == TWI1) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM1);
+	} else if (p_twi == TWI2) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM2);
+	} else if (p_twi == TWI3) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM3);
+	} else if (p_twi == TWI4) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM4);
+	} else if (p_twi == TWI5) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM5);
+	} else if (p_twi == TWI6) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM6);
+#ifdef _SAMG55_FLEXCOM7_INSTANCE_
+	} else if (p_twi == TWI7) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM7);
+#endif /* _SAMG55_FLEXCOM7_INSTANCE_*/
+	} else {
+		// Do Nothing
+	}
+#else
+#if (!(SAMG51 || SAMG53 || SAMG54))
+	if (p_twi == TWI0) {
+		sysclk_enable_peripheral_clock(ID_TWI0);
+	} else
+#endif
+	if (p_twi == TWI1) {
+		sysclk_enable_peripheral_clock(ID_TWI1);
+#if (SAM4N || SAMG)
+	} else if (p_twi == TWI2) {
+		sysclk_enable_peripheral_clock(ID_TWI2);
+#endif
+	} else {
+		// Do Nothing
+	}
+#endif
+
+	return (twi_master_init(p_twi, p_opt));
+}
+
+#define twi_master_enable(p_twi)   twi_enable_master_mode(p_twi)
+#define twi_master_disable(p_twi)  twi_disable_master_mode(p_twi)
+
+#endif // _TWI_MASTER_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_slave.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_slave.h
new file mode 100644
index 0000000000..fcd714ee45
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_slave.h
@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief TWI Slave driver for SAM.
+ *
+ * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _TWI_SLAVE_H_
+#define _TWI_SLAVE_H_
+
+#include "twi.h"
+#include "sysclk.h"
+
+typedef Twi *twi_slave_t;
+
+static inline void twi_slave_setup(twi_slave_t p_twi, uint32_t dw_device_addr)
+{
+#if SAMG55
+	if (p_twi == TWI0) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM0);
+	} else if (p_twi == TWI1) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM1);
+	} else if (p_twi == TWI2) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM2);
+	} else if (p_twi == TWI3) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM3);
+	} else if (p_twi == TWI4) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM4);
+	} else if (p_twi == TWI5) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM5);
+	} else if (p_twi == TWI6) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM6);
+#ifdef _SAMG55_FLEXCOM7_INSTANCE_
+	} else if (p_twi == TWI7) {
+		sysclk_enable_peripheral_clock(ID_FLEXCOM7);
+#endif /* _SAMG55_FLEXCOM7_INSTANCE_*/
+	} else {
+		// Do Nothing
+	}
+#else
+#if (!(SAMG51 || SAMG53 || SAMG54))
+	if (p_twi == TWI0) {
+		sysclk_enable_peripheral_clock(ID_TWI0);
+	} else
+#endif
+	if (p_twi == TWI1) {
+		sysclk_enable_peripheral_clock(ID_TWI1);
+#if (SAM4N || SAMG)
+	} else if (p_twi == TWI2) {
+		sysclk_enable_peripheral_clock(ID_TWI2);
+#endif
+	} else {
+		// Do Nothing
+	}
+#endif
+
+	twi_slave_init(p_twi, dw_device_addr);
+}
+
+#define twi_slave_enable(p_twi)  twi_enable_slave_mode(p_twi)
+
+#define twi_slave_disable(p_twi)  twi_disable_slave_mode(p_twi)
+
+#endif // _TWI_SLAVE_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_master.h
new file mode 100644
index 0000000000..8af74cb4bf
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_master.h
@@ -0,0 +1,102 @@
+/**
+ * \file
+ *
+ * \brief TWIHS Master driver for SAM.
+ *
+ * Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _TWIHS_MASTER_H_
+#define _TWIHS_MASTER_H_
+
+#include "twihs.h"
+#include "sysclk.h"
+
+typedef Twihs *twihs_master_t;
+typedef twihs_options_t twihs_master_options_t;
+typedef twihs_packet_t twihs_package_t;
+
+static inline uint32_t twihs_master_setup(twihs_master_t p_twihs,
+		twihs_master_options_t *p_opt)
+{
+	p_opt->master_clk = sysclk_get_peripheral_hz();
+	p_opt->smbus      = 0;
+
+#if (SAMV70 || SAMV71 || SAME70 || SAMS70)
+	if (p_twihs == TWIHS0) {
+		sysclk_enable_peripheral_clock(ID_TWIHS0);
+	} else if (p_twihs == TWIHS1) {
+		sysclk_enable_peripheral_clock(ID_TWIHS1);
+	} else if (p_twihs == TWIHS2) {
+		sysclk_enable_peripheral_clock(ID_TWIHS2);
+	} else {
+		// Do Nothing
+	}
+#else
+	if (p_twihs == TWI0) {
+		sysclk_enable_peripheral_clock(ID_TWI0);
+#if SAMG55		
+	} else if (p_twihs == TWI1) {
+		sysclk_enable_peripheral_clock(ID_TWI1);
+	} else if (p_twihs == TWI2) {
+		sysclk_enable_peripheral_clock(ID_TWI2);
+	} else if (p_twihs == TWI3) {
+		sysclk_enable_peripheral_clock(ID_TWI3);
+	} else if (p_twihs == TWI4) {
+		sysclk_enable_peripheral_clock(ID_TWI4);
+	} else if (p_twihs == TWI5) {
+		sysclk_enable_peripheral_clock(ID_TWI5);
+	} else if (p_twihs == TWI6) {
+		sysclk_enable_peripheral_clock(ID_TWI6);
+	} else if (p_twihs == TWI7) {
+		sysclk_enable_peripheral_clock(ID_TWI7);
+#endif		
+	} else {
+		// Do Nothing
+	}
+#endif
+	return (twihs_master_init(p_twihs, p_opt));
+}
+
+#define twihs_master_enable(p_twihs)   twihs_enable_master_mode(p_twihs)
+#define twihs_master_disable(p_twihs)  twihs_disable_master_mode(p_twihs)
+
+#endif // _TWIHS_MASTER_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_slave.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_slave.h
new file mode 100644
index 0000000000..a39431a801
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_slave.h
@@ -0,0 +1,97 @@
+/**
+ * \file
+ *
+ * \brief TWIHS Slave driver for SAM.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TWIHS_SLAVE_H_INCLUDED
+#define TWIHS_SLAVE_H_INCLUDED
+
+#include "twihs.h"
+#include "sysclk.h"
+
+typedef Twihs *twihs_slave_t;
+
+static inline void twihs_slave_setup(twihs_slave_t p_twihs, uint32_t dw_device_addr)
+{
+#if (SAMV70 || SAMV71 || SAME70 || SAMS70)
+	if (p_twihs == TWIHS0) {
+		sysclk_enable_peripheral_clock(ID_TWIHS0);
+	} else if (p_twihs == TWIHS1) {
+		sysclk_enable_peripheral_clock(ID_TWIHS1);
+	} else if (p_twihs == TWIHS2) {
+		sysclk_enable_peripheral_clock(ID_TWIHS2);
+	} else {
+		// Do Nothing
+	}
+#else
+	if (p_twihs == TWI0) {
+		sysclk_enable_peripheral_clock(ID_TWI0);
+#if SAMG55		
+	} else if (p_twihs == TWI1) {
+		sysclk_enable_peripheral_clock(ID_TWI1);
+	} else if (p_twihs == TWI2) {
+		sysclk_enable_peripheral_clock(ID_TWI2);
+	} else if (p_twihs == TWI3) {
+		sysclk_enable_peripheral_clock(ID_TWI3);
+	} else if (p_twihs == TWI4) {
+		sysclk_enable_peripheral_clock(ID_TWI4);
+	} else if (p_twihs == TWI5) {
+		sysclk_enable_peripheral_clock(ID_TWI5);
+	} else if (p_twihs == TWI6) {
+		sysclk_enable_peripheral_clock(ID_TWI6);
+	} else if (p_twihs == TWI7) {
+		sysclk_enable_peripheral_clock(ID_TWI7);
+#endif		
+	} else {
+		// Do Nothing
+	}
+#endif
+	twihs_slave_init(p_twihs, dw_device_addr);
+}
+
+#define twihs_slave_enable(p_twihs)  twihs_enable_slave_mode(p_twihs)
+
+#define twihs_slave_disable(p_twihs)  twihs_disable_slave_mode(p_twihs)
+
+#endif /* TWIHS_SLAVE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twim/twi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twim/twi_master.h
new file mode 100644
index 0000000000..a3570de6c2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twim/twi_master.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+ *
+ * \file
+ *
+ * \brief TWI Master driver for SAM.
+ *
+ * This file defines a useful set of functions for the TWIM interface on SAM
+ * devices.
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef _TWI_MASTER_H_
+#define _TWI_MASTER_H_
+
+#include "compiler.h"
+#include "sysclk.h"
+#include "status_codes.h"
+#include "twim.h"
+
+typedef twi_options_t twi_master_options_t;
+
+static inline uint32_t twi_master_setup(Twim *twi, twi_master_options_t *opt)
+{
+	opt->twim_clk = sysclk_get_pba_hz();
+	/* Initialize the TWIM Module */
+	twim_set_callback(twi, 0, twim_default_callback, 1);
+	return twi_master_init(twi, (twi_master_options_t *)opt);
+}
+
+#endif  // _TWI_MASTER_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_master.h
new file mode 100644
index 0000000000..183af48923
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_master.h
@@ -0,0 +1,234 @@
+/**
+ * \file
+ *
+ * \brief TWI Master Mode management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef TWI_MASTER_H_INCLUDED
+#define TWI_MASTER_H_INCLUDED
+
+#include <compiler.h>
+
+#if (SAM4L)
+# include "sam_twim/twi_master.h"
+#elif (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)
+# include "sam_twi/twi_master.h"
+#elif XMEGA
+# include "xmega_twi/twi_master.h"
+#elif MEGA_RF
+# include "megarf_twi/twi_master.h"
+#elif UC3
+# if (defined AVR32_TWI)
+# include "uc3_twi/twi_master.h"
+# else
+# include "uc3_twim/twi_master.h"
+# endif
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup twi_group Two Wire-interface(TWI)
+ *
+ * This is the common API for TWIs. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * See \ref twi_quickstart.
+ *
+ * \section twi_group_platform Platform Dependencies
+ *
+ * The TWI API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - Master TWI Module initialization
+ *   \code status_code_t twi_master_setup(*twi_module_pointer, twi_master_options_t *opt) \endcode
+ *   - Enables TWI Module
+ *   \code void twi_master_enable(*twi_module_pointer) \endcode
+ *   - Disables TWI Module
+ *   \code void twi_master_disable(*twi_module_pointer) \endcode
+ *   - Read data from a slave device
+ *   \code status_code_t twi_master_read(*twi_module_pointer, twi_package_t *package) \endcode
+ *   - Write data from to a slave device
+ *   \code status_code_t twi_master_write(*twi_module_pointer, twi_package_t *package) \endcode
+ *
+ * @{
+ */
+
+/**
+ * \typedef twi_master_t
+ * This type can be used independently to refer to TWI master module for the
+ * architecture used. It refers to the correct type definition for the
+ * architecture, ie. TWI_t* for XMEGA or avr32_twim_t* for UC3
+ */
+
+//! @}
+
+
+/**
+ * \page twi_quickstart Quickstart guide for Common service TWI
+ *
+ * This is the quickstart guide for the \ref twi_group "Common service TWI",
+ * with step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section twi_basic_use_case Basic use case
+ * In the most basic use case, the TWI module is configured for
+ * - Master operation
+ * - addressing one slave device of the bus at address 0x50
+ * - TWI clock of 50kHz
+ * - polled read/write handling
+ *
+ * \section twi_basic_use_case_setup Setup steps
+ * \subsection twi_basic_use_case_setup_code Example code
+ * Add to your application C-file:
+ * \code
+	  void twi_init(void)
+	  {
+	    twi_master_options_t opt = {
+	        .speed = 50000,
+	        .chip  = 0x50
+	    };
+
+	    twi_master_setup(&TWIM0, &opt);
+	  }
+\endcode
+ *
+ * \subsection twi_basic_use_case_setup_flow Workflow
+ * -# Ensure that board_init() has configured selected I/Os for TWI function.
+ * -# Ensure that \ref conf_twim.h is present for the driver.
+ *   - \note This file is only for the driver and should not be included by the
+ * user.
+ * -# Define and initialize config structs for TWI module in your TWI initialization
+ * function:
+ *   - \code
+	twi_master_options_t opt = {
+	  .speed = 50000,
+	  .chip  = 0x50
+	}; \endcode
+ *   - field \ref speed sets the baudrate of the TWI bus
+ *   - field \ref chip sets the address of the slave device you want to communicate with
+ * -# Call twi_master_setup and optionally check its return code
+ *   - \note The config structs can be reused for other TWI modules
+ * after this step. Simply reconfigure and write to others modules.
+ *
+ * \section twi_basic_use_case_usage Usage steps
+ * \subsection twi_basic_use_case_usage_code_writing Example code : Writing to a slave device
+ * Use in application C-file:
+ * \code
+	  const uint8_t test_pattern[] = {0x55,0xA5,0x5A,0x77,0x99};
+
+	  twi_package_t packet_write = {
+	    .addr         = EEPROM_MEM_ADDR,      // TWI slave memory address data
+	    .addr_length  = sizeof (uint16_t),    // TWI slave memory address data size
+	    .chip         = EEPROM_BUS_ADDR,      // TWI slave bus address
+	    .buffer       = (void *)test_pattern, // transfer data source buffer
+	    .length       = sizeof(test_pattern)  // transfer data size (bytes)
+	  };
+
+	  while (twi_master_write(&TWIM0, &packet_write) != TWI_SUCCESS);
+\endcode
+ *
+ * \subsection twi_basic_use_case_usage_flow Workflow
+ * -# Prepare the data you want to send to the slave device:
+ *   - \code const uint8_t test_pattern[] = {0x55,0xA5,0x5A,0x77,0x99}; \endcode
+ * -# Prepare a twi_package_t structure
+ *   \code twi_package_t packet_write; \endcode
+ * Fill all the fields of the structure :
+ *  - addr is the address in the slave device
+ *  - addr_length is the size of the address in the slave (support for large TWI memory devices)
+ *  - chip sets the 7 bit address of the slave device you want to communicate with
+ *  - buffer is a pointer on the data to write to slave
+ *  - length is the number of data to write
+ *
+ * -# Finally, call twi_master_write \code twi_master_write(&TWIM0, &packet_write); \endcode
+ * and optionally check its return value for TWI_SUCCESS.
+ * \subsection twi_basic_use_case_usage_code_reading Example code : Reading from a slave device
+ * Use in application C-file:
+ * \code
+	   uint8_t data_received[10];
+
+	   twi_package_t packet_read = {
+	     .addr         = EEPROM_MEM_ADDR,      // TWI slave memory address data
+	     .addr_length  = sizeof (uint16_t),    // TWI slave memory address data size
+	     .chip         = EEPROM_BUS_ADDR,      // TWI slave bus address
+	     .buffer       = data_received,        // transfer data destination buffer
+	     .length       = 10                    // transfer data size (bytes)
+	   };
+	   // Perform a multi-byte read access then check the result.
+	   if(twi_master_read(&TWIM0, &packet_read) == TWI_SUCCESS){
+	     //Check read content
+	     if(data_received[0]==0x55)
+	       do_something();
+	   }
+\endcode
+ *
+ * \subsection twi_basic_use_case_usage_flow Workflow
+ * -# Prepare a data buffer that will receive the data from the slave device:
+ *   \code uint8_t data_received[10]; \endcode
+ * -# Prepare a twi_package_t structure
+ *   \code twi_package_t packet_read; \endcode
+ * Fill all the fields of the structure :
+ *  - addr is the address in the slave device
+ *  - addr_length is the size of the address in the slave (support for large TWI memory devices)
+ *  - chip sets the 7 bit address of the slave device you want to communicate with
+ *  - buffer is a pointer on the data buffer that will receive the data from the slave device
+ *  - length is the number of data to read
+ *
+ * -# Finally, call twi_master_read \code twi_master_read(&TWIM0, &packet_read); \endcode
+ * and optionally check its return value for TWI_SUCCESS.
+ * the data read from the device are now in data_received.
+ */
+
+
+#endif /* TWI_MASTER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_slave.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_slave.h
new file mode 100644
index 0000000000..497316b40a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_slave.h
@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief TWI Slave Mode management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef TWI_SLAVE_H_INCLUDED
+#define TWI_SLAVE_H_INCLUDED
+
+#include <parts.h>
+#include <compiler.h>
+
+#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP)
+# include "sam_twi/twi_slave.h"
+#elif XMEGA
+# include "xmega_twi/twi_slave.h"
+#elif MEGA_RF
+# include "megarf_twi/twi_slave.h"
+#elif (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
+#if (defined AVR32_TWI)
+#error Not supported.
+#endif
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup twi_group Two Wire-interface(TWI)
+ *
+ * This is the common API for TWIs. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section twi_group_platform Platform Dependencies
+ *
+ * The twi API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - twi_slave_setup()
+ *   - twi_slave_enable()
+ *   - twi_slave_disable()
+ *   - twi_slave_read()
+ *   - twi_slave_write()
+ *
+ * @{
+ */
+
+/**
+ * \typedef twi_slave_t
+ * This type can be used independently to refer to TWI slave module for the
+ * architecture used. It refers to the correct type definition for the
+ * architecture, ie. TWI_t* for XMEGA or avr32_twi_t* for UC3
+ */
+
+//! @}
+
+#endif /* TWI_SLAVE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_master.h
new file mode 100644
index 0000000000..a620f3db20
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_master.h
@@ -0,0 +1,221 @@
+/**
+ * \file
+ *
+ * \brief TWIHS Master Mode management
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef TWIHS_MASTER_H_INCLUDED
+#define TWIHS_MASTER_H_INCLUDED
+
+#include <parts.h>
+#include <compiler.h>
+
+#if (SAMG || SAMV70 || SAMV71 || SAME70 || SAMS70)
+# include "sam_twihs/twihs_master.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup twihs_group Two Wire-interface High Speed(TWIHS)
+ *
+ * This is the common API for TWIHS. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * See \ref twihs_quickstart.
+ *
+ * \section twihs_group_platform Platform Dependencies
+ *
+ * The TWIHS API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - Master TWIHS Module initialization
+ *   \code status_code_t twihs_master_setup(*twihs_module_pointer, twihs_master_options_t *opt) \endcode
+ *   - Enables TWIHS Module
+ *   \code void twihs_master_enable(*twihs_module_pointer) \endcode
+ *   - Disables TWIHS Module
+ *   \code void twihs_master_disable(*twihs_module_pointer) \endcode
+ *   - Read data from a slave device
+ *   \code status_code_t twihs_master_read(*twihs_module_pointer, twihs_package_t *package) \endcode
+ *   - Write data from to a slave device
+ *   \code status_code_t twihs_master_write(*twihs_module_pointer, twihs_package_t *package) \endcode
+ *
+ * @{
+ */
+
+/**
+ * \typedef twihs_master_t
+ * This type can be used independently to refer to TWIHS master module for the
+ * architecture used. It refers to the correct type definition for the
+ * architecture.
+ */
+
+//! @}
+
+/**
+ * \page twihs_quickstart Quickstart guide for Common service TWIHS
+ *
+ * This is the quickstart guide for the \ref twihs_group "Common service TWIHS",
+ * with step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section twihs_basic_use_case Basic use case
+ * In the most basic use case, the TWIHS module is configured for
+ * - Master operation
+ * - addressing one slave device of the bus at address 0x50
+ * - TWIHS clock of 400kHz
+ * - polled read/write handling
+ *
+ * \section twihs_basic_use_case_setup Setup steps
+ * \subsection twihs_basic_use_case_setup_code Example code
+ * Add to your application C-file, for example in SAM series chip:
+ * \code
+	  void twihs_init(void)
+	  {
+	    twihs_master_options_t opt = {
+	        .speed = 400000,
+	        .chip  = 0x50
+	    };
+
+	    twihs_master_setup(&TWIM0, &opt);
+	  }
+\endcode
+ *
+ * \subsection twihs_basic_use_case_setup_flow Workflow
+ * -# Ensure that board_init() has configured selected I/Os for TWIHS function.
+ * -# Ensure that \ref conf_twim.h is present for the driver.
+ *   - \note This file is only for the driver and should not be included by the
+ * user.
+ * -# Define and initialize config structs for TWIHS module in your TWIHS initialization
+ * function, for example in SAM series chip:
+ *   - \code
+	twihs_master_options_t opt = {
+	  .speed = 400000,
+	  .chip  = 0x50
+	}; \endcode
+ *   - field \ref speed sets the baudrate of the TWIHS bus
+ *   - field \ref chip sets the address of the slave device you want to communicate with
+ * -# Call twihs_master_setup and optionally check its return code
+ *   - \note The config structs can be reused for other TWIHS modules
+ * after this step. Simply reconfigure and write to others modules.
+ *
+ * \section twihs_basic_use_case_usage Usage steps
+ * \subsection twihs_basic_use_case_usage_code_writing Example code : Writing to a slave device
+ * Use in application C-file, for example in SAM series chip:
+ * \code
+	  const uint8_t test_pattern[] = {0x55,0xA5,0x5A,0x77,0x99};
+
+	  twihs_package_t packet_write = {
+	    .addr         = EEPROM_MEM_ADDR,      // TWIHS slave memory address data
+	    .addr_length  = sizeof (uint16_t),    // TWIHS slave memory address data size
+	    .chip         = EEPROM_BUS_ADDR,      // TWIHS slave bus address
+	    .buffer       = (void *)test_pattern, // transfer data source buffer
+	    .length       = sizeof(test_pattern)  // transfer data size (bytes)
+	  };
+
+	  while (twihs_master_write(&TWIM0, &packet_write) != TWI_SUCCESS);
+\endcode
+ *
+ * \subsection twihs_basic_use_case_usage_flow Workflow
+ * -# Prepare the data you want to send to the slave device:
+ *   - \code const uint8_t test_pattern[] = {0x55,0xA5,0x5A,0x77,0x99}; \endcode
+ * -# Prepare a twihs_package_t structure
+ *   \code twihs_package_t packet_write; \endcode
+ * Fill all the fields of the structure :
+ *  - addr is the address in the slave device
+ *  - addr_length is the size of the address in the slave (support for large TWI memory devices)
+ *  - chip sets the 7 bit address of the slave device you want to communicate with
+ *  - buffer is a pointer on the data to write to slave
+ *  - length is the number of data to write
+ *
+ * -# Finally, call twihs_master_write \code twihs_master_write(&TWIM0, &packet_write); \endcode
+ * and optionally check its return value for TWI_SUCCESS.
+ * \subsection twihs_basic_use_case_usage_code_reading Example code : Reading from a slave device
+ * Use in application C-file, for example in SAM series chip:
+ * \code
+	   uint8_t data_received[10];
+
+	   twihs_package_t packet_read = {
+	     .addr         = EEPROM_MEM_ADDR,      // TWIHS slave memory address data
+	     .addr_length  = sizeof (uint16_t),    // TWIHS slave memory address data size
+	     .chip         = EEPROM_BUS_ADDR,      // TWIHS slave bus address
+	     .buffer       = data_received,        // transfer data destination buffer
+	     .length       = 10                    // transfer data size (bytes)
+	   };
+	   // Perform a multi-byte read access then check the result.
+	   if(twihs_master_read(&TWIM0, &packet_read) == TWI_SUCCESS){
+	     //Check read content
+	     if(data_received[0]==0x55)
+	       do_something();
+	   }
+\endcode
+ *
+ * \subsection twihs_basic_use_case_usage_flow Workflow
+ * -# Prepare a data buffer that will receive the data from the slave device:
+ *   \code uint8_t data_received[10]; \endcode
+ * -# Prepare a twihs_package_t structure
+ *   \code twihs_package_t packet_read; \endcode
+ * Fill all the fields of the structure :
+ *  - addr is the address in the slave device
+ *  - addr_length is the size of the address in the slave (support for large TWI memory devices)
+ *  - chip sets the 7 bit address of the slave device you want to communicate with
+ *  - buffer is a pointer on the data buffer that will receive the data from the slave device
+ *  - length is the number of data to read
+ *
+ * -# Finally, call twihs_master_read \code twihs_master_read(&TWIM0, &packet_read); \endcode
+ * and optionally check its return value for TWI_SUCCESS.
+ * the data read from the device are now in data_received.
+ */
+
+#endif /* TWI_MASTER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_slave.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_slave.h
new file mode 100644
index 0000000000..4c768d03dc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_slave.h
@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief TWIHS Slave Mode management
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef TWIHS_SLAVE_H_INCLUDED
+#define TWIHS_SLAVE_H_INCLUDED
+
+#include <parts.h>
+#include <compiler.h>
+
+#if (SAMG || SAMV70 || SAMV71 || SAME70 || SAMS70)
+# include "sam_twihs/twihs_slave.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup twihs_group Two Wire-interface High Speed(TWIHS)
+ *
+ * This is the common API for TWIHS. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section twihs_group_platform Platform Dependencies
+ *
+ * The twihs API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - twihs_slave_setup()
+ *   - twihs_slave_enable()
+ *   - twihs_slave_disable()
+ *   - twihs_slave_read()
+ *   - twihs_slave_write()
+ *
+ * @{
+ */
+
+/**
+ * \typedef twihs_slave_t
+ * This type can be used independently to refer to TWIHS slave module for the
+ * architecture used.
+ */
+
+//! @}
+
+#endif /* TWIHS_SLAVE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt.h b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt.h
new file mode 100644
index 0000000000..a88c6f0c59
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt.h
@@ -0,0 +1,142 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for 8- and 32-bit AVR
+ *
+ * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef UTILS_INTERRUPT_H
+#define UTILS_INTERRUPT_H
+
+#include <parts.h>
+
+#if XMEGA || MEGA
+#  include "interrupt/interrupt_avr8.h"
+#elif UC3
+#  include "interrupt/interrupt_avr32.h"
+#elif SAM || SAMB
+#  include "interrupt/interrupt_sam_nvic.h"
+#else
+#  error Unsupported device.
+#endif
+
+/**
+ * \defgroup interrupt_group Global interrupt management
+ *
+ * This is a driver for global enabling and disabling of interrupts.
+ *
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * \def CONFIG_INTERRUPT_FORCE_INTC
+ * \brief Force usage of the ASF INTC driver
+ *
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
+ * This is useful to ensure compatibility across compilers and shall be used only when required
+ * by the application needs.
+ */
+#  define CONFIG_INTERRUPT_FORCE_INTC
+#endif
+
+//! \name Global interrupt flags
+//@{
+/**
+ * \typedef irqflags_t
+ * \brief Type used for holding state of interrupt flag
+ */
+
+/**
+ * \def cpu_irq_enable
+ * \brief Enable interrupts globally
+ */
+
+/**
+ * \def cpu_irq_disable
+ * \brief Disable interrupts globally
+ */
+
+/**
+ * \fn irqflags_t cpu_irq_save(void)
+ * \brief Get and clear the global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_restore.
+ *
+ * \return Current state of interrupt flags.
+ *
+ * \note This function leaves interrupts disabled.
+ */
+
+/**
+ * \fn void cpu_irq_restore(irqflags_t flags)
+ * \brief Restore global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_save.
+ *
+ * \param flags State to set interrupt flag to.
+ */
+
+/**
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
+ * \brief Check if interrupts are globally enabled in supplied flags
+ *
+ * \param flags Currents state of interrupt flags.
+ *
+ * \return True if interrupts are enabled.
+ */
+
+/**
+ * \def cpu_irq_is_enabled
+ * \brief Check if interrupts are globally enabled
+ *
+ * \return True if interrupts are enabled.
+ */
+//@}
+
+//! @}
+
+/**
+ * \ingroup interrupt_group
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
+ */
+
+#endif /* UTILS_INTERRUPT_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr32.h b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr32.h
new file mode 100644
index 0000000000..66f2fa2c2f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr32.h
@@ -0,0 +1,351 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for 32-bit AVR
+ *
+ * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <preprocessor/tpaste.h>
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+//! Pointer to interrupt handler.
+#if (defined __GNUC__)
+typedef void (*__int_handler)(void);
+#elif (defined __ICCAVR32__)
+typedef void (__interrupt *__int_handler)(void);
+#endif
+
+/**
+ * \name Interrupt Service Routine definition and registration
+ *
+ * @{
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+
+/**
+ * \brief Macro to declare an interrupt service routine
+ *
+ * With GCC, this macro only causes the function to be defined as an interrupt
+ * service routine, i.e., it does not add any initialization code. A valid
+ * function name is required for use with \ref irq_register_handler.
+ *
+ * With IAR, this macro defines the function as an interrupt service routine and
+ * causes the compiler to add initialization code for the interrupt controller
+ * (INTC). The interrupt group and level, as well as a valid function name are
+ * therefore required.\n
+ * \note If \ref CONFIG_INTERRUPT_FORCE_INTC is defined, only a valid function
+ * name is required for use with \ref irq_register_handler. The initialization
+ * code will be handled by the interrupt controller itself.
+ *
+ * Usage:
+ * \code
+	ISR(foo_irq_handler, AVR32_xxx_IRQ_GROUP, n)
+	{
+	     // Function definition
+	     ...
+	}
+\endcode
+ *
+ * \param func Name for the function, needed by \ref irq_register_handler.
+ * \param int_grp Interrupt group to define service routine for.
+ * \param int_lvl Priority level to set for the interrupt group, in the range
+ * \c 0 to \c 3.
+ *
+ * \note The interrupt groups can be found in the device header files for the
+ * IAR toolchain (avr32/io\<part\>.h).
+ *
+ * \todo Update to use IRQ numbers when these are made available in the
+ * device header files of both IAR and GCC.
+ */
+#  define ISR(func, int_grp, int_lvl)    \
+	__attribute__((__interrupt__)) static void func (void)
+
+#elif defined(__ICCAVR32__) && defined(CONFIG_INTERRUPT_FORCE_INTC)
+#  define ISR(func, int_grp, int_lvl) \
+		__interrupt static void func (void)
+
+#elif defined(__ICCAVR32__)
+#  define ISR0(...) _Pragma(#__VA_ARGS__)
+#  define ISR(func, int_grp, int_lvl)                                          \
+		ISR0(handler=int_grp, int_lvl)                                 \
+		__interrupt static void func (void)
+#endif
+
+#if defined(__GNUC__) || defined(__DOXYGEN__) || defined(CONFIG_INTERRUPT_FORCE_INTC)
+#  include <intc.h>
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * With GCC, this macro adds code for initialization of the interrupt vectors
+ * with the driver for the interrupt controller (INTC).
+ *
+ * With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro
+ * adds no code, since initialization of the INTC is handled by the compiler.
+ * \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the
+ * INTC driver, replacing the compiler built-in interrupt handler.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+#  define irq_initialize_vectors()    INTC_init_interrupts()
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * With GCC, this macro adds code for registering an interrupt handler with the
+ * driver for the interrupt controller (INTC).
+ *
+ * With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro
+ * adds no code, since initialization of the INTC is handled by the compiler.
+ * \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the
+ * INTC driver, replacing the compiler built-in interrupt handler.
+ *
+ * \param func Name of handler function to register for interrupt.
+ * \param int_num Number of the interrupt line to register function for.
+ * \param int_lvl Priority level to set for the interrupt's group, in the range
+ * \c 0 to \c 3.
+ *
+ * Usage:
+ * \code
+	irq_initialize_vectors();
+	irq_register_handler(foo_irq_handler, AVR32_xxx_IRQ, n);
+\endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The interrupt line number can be found in the device header files for
+ * the GCC toolchain (avr32/\<part\>.h).
+ */
+#  define irq_register_handler(func, int_num, int_lvl)                         \
+	INTC_register_interrupt(func, int_num,                                 \
+			TPASTE2(AVR32_INTC_INT, int_lvl))
+
+#elif defined(__ICCAVR32__)
+#  define irq_initialize_vectors()                        do{ } while(0)
+#  define irq_register_handler(func, int_num, int_lvl)    do{ } while(0)
+#endif
+
+//@}
+
+#if (defined __GNUC__)
+#  define cpu_irq_enable()                             \
+	do {                                           \
+		barrier();                             \
+		__builtin_csrf(AVR32_SR_GM_OFFSET);    \
+	} while (0)
+#  define cpu_irq_disable()                            \
+	do {                                           \
+		__builtin_ssrf(AVR32_SR_GM_OFFSET);    \
+		barrier();                             \
+	} while (0)
+#elif (defined __ICCAVR32__)
+#  if (defined CONFIG_INTERRUPT_FORCE_INTC)
+#    define cpu_irq_enable()                                 \
+	do {                                                 \
+		barrier();                                   \
+		__clear_status_flag(AVR32_SR_GM_OFFSET);     \
+	} while(0)
+#    define cpu_irq_disable()                                \
+	do {                                                 \
+		__set_status_flag(AVR32_SR_GM_OFFSET);       \
+		barrier();                                   \
+	} while (0)
+#  else
+#    define cpu_irq_enable()     __enable_interrupt()
+#    define cpu_irq_disable()    __disable_interrupt()
+#  endif
+#endif
+
+typedef uint32_t irqflags_t;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+	volatile irqflags_t flags;
+
+	flags = sysreg_read(AVR32_SR);
+	cpu_irq_disable();
+
+	return flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+	return !(flags & AVR32_SR_GM_MASK);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+	barrier();
+
+   /* Restore the global IRQ mask status flag if it was previously set */
+   if ( cpu_irq_is_enabled_flags(flags) ) {
+      cpu_irq_enable();
+   }
+
+	barrier();
+}
+
+#define cpu_irq_is_enabled()    cpu_irq_is_enabled_flags(sysreg_read(AVR32_SR))
+
+//! \name Global interrupt levels
+//@{
+
+/**
+ * \brief Check if interrupt level is enabled in supplied flags
+ *
+ * \param flags State of interrupt flags.
+ * \param level Bit position for interrupt level.
+ *
+ * \return True if interrupt level is enabled.
+ */
+static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
+		uint32_t level)
+{
+	return !(flags & (1 << level));
+}
+
+/**
+ * \brief Check if interrupt level is enabled
+ *
+ * \param level Interrupt level (0 to 3).
+ *
+ * \return True if interrupt level \a level is enabled.
+ *
+ * \note The interrupt level must be known at compile time.
+ */
+#define cpu_irq_level_is_enabled(level)                                  \
+	cpu_irq_level_is_enabled_flags(sysreg_read(AVR32_SR),             \
+			TPASTE3(AVR32_SR_I, level, M_OFFSET))
+
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+/**
+ * \brief Enable interrupt level
+ *
+ * \param level Interrupt level to enable (0 to 3).
+ *
+ * \note The interrupt level must be known at compile time.
+ */
+#  define cpu_irq_enable_level(level)                                    \
+	do {                                                             \
+		barrier();                                               \
+		__builtin_csrf(TPASTE3(AVR32_SR_I, level, M_OFFSET));    \
+	} while (0)
+
+/**
+ * \brief Disable interrupt level
+ *
+ * \param level Interrupt level to disable (0 to 3).
+ *
+ * \note The interrupt level must be known at compile time.
+ */
+#  define cpu_irq_disable_level(level)                                   \
+	do {                                                             \
+		__builtin_ssrf(TPASTE3(AVR32_SR_I, level, M_OFFSET));    \
+		barrier();                                               \
+	} while (0)
+
+#elif (defined __ICCAVR32__)
+#  define cpu_irq_enable_level(level)                                          \
+	do {                                                                   \
+		barrier();                                                     \
+		__clear_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET));     \
+	} while(0)
+#  define cpu_irq_disable_level(level)                                         \
+	do {                                                                   \
+		__set_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET));       \
+		barrier();                                                     \
+	} while (0)
+#endif
+
+//@}
+
+//@}
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt()            cpu_irq_enable()
+#define Disable_global_interrupt()           cpu_irq_disable()
+#define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
+
+#define Enable_interrupt_level(level)        cpu_irq_enable_level(level)
+#define Disable_interrupt_level(level)       cpu_irq_disable_level(level)
+#define Is_interrupt_level_enabled(level)    cpu_irq_level_is_enabled(level)
+
+/**
+ * \name Interrupt protection of code sections
+ * \note Use \ref cpu_irq_save and \ref cpu_irq_restore instead of these macros.
+ * @{
+ */
+
+/**
+ * \brief Start section with code protected against interrupts
+ */
+#define AVR32_ENTER_CRITICAL_REGION()                                          \
+	{                                                                      \
+		bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
+		Disable_global_interrupt();
+
+/**
+ * \brief End section with code protected against interrupts
+ *
+ * \note This macro must always be used in conjunction with
+ * \ref AVR32_ENTER_CRITICAL_REGION so that interrupts are enabled again.
+ */
+#define AVR32_LEAVE_CRITICAL_REGION()                                          \
+		if (global_interrupt_enabled) Enable_global_interrupt();       \
+	}
+
+//@}
+
+//@}
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr8.h b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr8.h
new file mode 100644
index 0000000000..1e6928c285
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr8.h
@@ -0,0 +1,148 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for 8-bit AVR
+ *
+ * Copyright (C) 2010-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <parts.h>
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+#ifdef ISR_CUSTOM_H
+#  include ISR_CUSTOM_H
+#else
+
+/**
+ * \def ISR
+ * \brief Define service routine for specified interrupt vector
+ *
+ * Usage:
+ * \code
+	ISR(FOO_vect)
+	{
+	    ...
+	}
+\endcode
+ *
+ * \param vect Interrupt vector name as found in the device header files.
+ */
+#if defined(__DOXYGEN__)
+#  define ISR(vect)
+#elif defined(__GNUC__)
+#  include <avr/interrupt.h>
+#elif defined(__ICCAVR__)
+#  define __ISR(x) _Pragma(#x)
+#  define ISR(vect) __ISR(vector=vect) __interrupt void handler_##vect(void)
+#endif
+#endif // ISR_CUSTOM_H
+
+#if XMEGA
+/**
+ * \brief Initialize interrupt vectors
+ * Enables all interrupt levels, with vectors located in the application section
+ * and fixed priority scheduling.
+ */
+#define irq_initialize_vectors() \
+	PMIC.CTRL = PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
+#elif MEGA_RF
+#define irq_initialize_vectors()
+#endif
+
+#ifdef __GNUC__
+#  define cpu_irq_enable()     sei()
+#  define cpu_irq_disable()    cli()
+#else
+#  define cpu_irq_enable()     __enable_interrupt()
+#  define cpu_irq_disable()    __disable_interrupt()
+#endif
+
+typedef uint8_t irqflags_t;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+	volatile irqflags_t flags = SREG;
+	cpu_irq_disable();
+	return flags;
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+	barrier();
+	SREG = flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+#if XMEGA
+#  ifdef __GNUC__
+	return flags & CPU_I_bm;
+#  else
+	return flags & I_bm;
+#  endif
+#elif MEGA || TINY
+	return flags & (1 << SREG_I);
+#endif
+}
+
+#define cpu_irq_is_enabled()             cpu_irq_is_enabled_flags(SREG)
+
+//! @}
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+// Deprecated definitions.
+#define Enable_global_interrupt()        cpu_irq_enable()
+#define Disable_global_interrupt()       cpu_irq_disable()
+#define Is_global_interrupt_enabled()    cpu_irq_is_enabled()
+//! @}
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.c b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.c
new file mode 100644
index 0000000000..26dcc91ef4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.c
@@ -0,0 +1,86 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "interrupt_sam_nvic.h"
+
+#if !defined(__DOXYGEN__)
+/* Deprecated - global flag to determine the global interrupt state. Required by
+ * QTouch library, however new applications should use cpu_irq_is_enabled()
+ * which probes the true global interrupt state from the CPU special registers.
+ */
+volatile bool g_interrupt_enabled = true;
+#endif
+
+void cpu_irq_enter_critical(void)
+{
+	if (cpu_irq_critical_section_counter == 0) {
+		if (cpu_irq_is_enabled()) {
+			cpu_irq_disable();
+			cpu_irq_prev_interrupt_state = true;
+		} else {
+			/* Make sure the to save the prev state as false */
+			cpu_irq_prev_interrupt_state = false;
+		}
+
+	}
+
+	cpu_irq_critical_section_counter++;
+}
+
+void cpu_irq_leave_critical(void)
+{
+	/* Check if the user is trying to leave a critical section when not in a critical section */
+	Assert(cpu_irq_critical_section_counter > 0);
+
+	cpu_irq_critical_section_counter--;
+
+	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+	   was enabled when entering critical state */
+	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
+		cpu_irq_enable();
+	}
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.h b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.h
new file mode 100644
index 0000000000..419ad2046e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.h
@@ -0,0 +1,189 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+/**
+ * \name Interrupt Service Routine definition
+ *
+ * @{
+ */
+
+/**
+ * \brief Define service routine
+ *
+ * \note For NVIC devices the interrupt service routines are predefined to
+ *       add to vector table in binary generation, so there is no service
+ *       register at run time. The routine collections are in exceptions.h.
+ *
+ * Usage:
+ * \code
+	ISR(foo_irq_handler)
+	{
+	     // Function definition
+	     ...
+	}
+\endcode
+ *
+ * \param func Name for the function.
+ */
+#  define ISR(func)   \
+	void func (void)
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to initialize them, except defined the vector function with
+ * right name.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+#  define irq_initialize_vectors()   \
+	do {                             \
+	} while(0)
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to register them, except defined the vector function with
+ * right name.
+ *
+ * Usage:
+ * \code
+	irq_initialize_vectors();
+	irq_register_handler(foo_irq_handler);
+\endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The functions prototypes can be found in the device exception header
+ *       files (exceptions.h).
+ */
+#  define irq_register_handler(int_num, int_prio)                      \
+	NVIC_ClearPendingIRQ(    (IRQn_Type)int_num);                      \
+	NVIC_SetPriority(    (IRQn_Type)int_num, int_prio);                \
+	NVIC_EnableIRQ(      (IRQn_Type)int_num);                          \
+
+//@}
+
+#  define cpu_irq_enable()                     \
+	do {                                       \
+		g_interrupt_enabled = true;            \
+		__DMB();                               \
+		__enable_irq();                        \
+	} while (0)
+#  define cpu_irq_disable()                    \
+	do {                                       \
+		__disable_irq();                       \
+		__DMB();                               \
+		g_interrupt_enabled = false;           \
+	} while (0)
+
+typedef uint32_t irqflags_t;
+
+#if !defined(__DOXYGEN__)
+extern volatile bool g_interrupt_enabled;
+#endif
+
+#define cpu_irq_is_enabled()    (__get_PRIMASK() == 0)
+
+static volatile uint32_t cpu_irq_critical_section_counter;
+static volatile bool     cpu_irq_prev_interrupt_state;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+	volatile irqflags_t flags = cpu_irq_is_enabled();
+	cpu_irq_disable();
+	return flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+	return (flags);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+	if (cpu_irq_is_enabled_flags(flags))
+		cpu_irq_enable();
+}
+
+void cpu_irq_enter_critical(void);
+void cpu_irq_leave_critical(void);
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt()            cpu_irq_enable()
+#define Disable_global_interrupt()           cpu_irq_disable()
+#define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/make/Makefile.avr.in b/bsp/samd21/sam_d2x_asflib/common/utils/make/Makefile.avr.in
new file mode 100644
index 0000000000..5d9a837547
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/make/Makefile.avr.in
@@ -0,0 +1,483 @@
+# List of available make goals:
+#
+# all                     Default target, builds the project
+# clean                   Clean up the project
+# rebuild                 Rebuild the project
+#
+# doc                     Build the documentation
+# cleandoc                Clean up the documentation
+# rebuilddoc              Rebuild the documentation
+#
+#
+# Copyright (c) 2009 - 2013 Atmel Corporation. All rights reserved.
+#
+# \asf_license_start
+#
+# \page License
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+#    this list of conditions and the following disclaimer in the documentation
+#    and/or other materials provided with the distribution.
+#
+# 3. The name of Atmel may not be used to endorse or promote products derived
+#    from this software without specific prior written permission.
+#
+# 4. This software may only be redistributed and used in connection with an
+#    Atmel microcontroller product.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+# \asf_license_stop
+#
+
+# Include the config.mk file from the current working path, e.g., where the
+# user called make.
+include config.mk
+
+# Tool to use to generate documentation from the source code
+DOCGEN          ?= doxygen
+
+# Look for source files relative to the top-level source directory
+VPATH           := $(PRJ_PATH)
+
+# Output target file
+target          := $(TARGET)
+
+# Output project name (target name minus suffix)
+project         := $(basename $(target))
+
+# Output target file (typically ELF or static library)
+ifeq ($(suffix $(target)),.a)
+target_type     := lib
+else
+ifeq ($(suffix $(target)),.elf)
+target_type     := elf
+else
+$(error "Target type $(target_type) is not supported")
+endif
+endif
+
+# Allow override of operating system detection. The user can add OS=Linux or
+# OS=Windows on the command line to explicit set the host OS.
+#
+# This allows to work around broken uname utility on certain systems.
+ifdef OS
+  ifeq ($(strip $(OS)), Linux)
+    os_type     := Linux
+  endif
+  ifeq ($(strip $(OS)), Windows)
+    os_type     := windows32_64
+  endif
+endif
+
+os_type         ?= $(strip $(shell uname))
+
+ifeq ($(os_type),windows32)
+os              := Windows
+else
+ifeq ($(os_type),windows64)
+os              := Windows
+else
+ifeq ($(os_type),windows32_64)
+os              ?= Windows
+else
+ifeq ($(os_type),)
+os              := Windows
+else
+# Default to Linux style operating system. Both Cygwin and mingw are fully
+# compatible (for this Makefile) with Linux.
+os              := Linux
+endif
+endif
+endif
+endif
+
+# Output documentation directory and configuration file.
+docdir          := ../doxygen/html
+doccfg          := ../doxygen/doxyfile.doxygen
+
+CROSS           ?= avr-
+AR              := $(CROSS)ar
+AS              := $(CROSS)as
+CC              := $(CROSS)gcc
+CPP             := $(CROSS)gcc -E
+CXX             := $(CROSS)g++
+LD              := $(CROSS)gcc
+NM              := $(CROSS)nm
+OBJCOPY         := $(CROSS)objcopy
+OBJDUMP         := $(CROSS)objdump
+SIZE            := $(CROSS)size
+
+RM              := rm
+ifeq ($(os),Windows)
+RMDIR           := rmdir /S /Q
+else
+RMDIR           := rmdir -p --ignore-fail-on-non-empty
+endif
+
+# On Windows, we need to override the shell to force the use of cmd.exe
+ifeq ($(os),Windows)
+SHELL           := cmd
+endif
+
+# Strings for beautifying output
+MSG_CLEAN_FILES         = "RM      *.o *.d"
+MSG_CLEAN_DIRS          = "RMDIR   $(strip $(clean-dirs))"
+MSG_CLEAN_DOC           = "RMDIR   $(docdir)"
+MSG_MKDIR               = "MKDIR   $(dir $@)"
+
+MSG_INFO                = "INFO    "
+MSG_PREBUILD            = "PREBUILD  $(PREBUILD_CMD)"
+MSG_POSTBUILD           = "POSTBUILD $(POSTBUILD_CMD)"
+
+MSG_ARCHIVING           = "AR      $@"
+MSG_ASSEMBLING          = "AS      $@"
+MSG_BINARY_IMAGE        = "OBJCOPY $@"
+MSG_COMPILING           = "CC      $@"
+MSG_COMPILING_CXX       = "CXX     $@"
+MSG_EEPROM_IMAGE        = "OBJCOPY $@"
+MSG_EXTENDED_LISTING    = "OBJDUMP $@"
+MSG_IHEX_IMAGE          = "OBJCOPY $@"
+MSG_LINKING             = "LN      $@"
+MSG_PREPROCESSING       = "CPP     $@"
+MSG_SIZE                = "SIZE    $@"
+MSG_SYMBOL_TABLE        = "NM      $@"
+
+MSG_GENERATING_DOC      = "DOXYGEN $(docdir)"
+
+# Don't use make's built-in rules and variables
+MAKEFLAGS       += -rR
+
+# Don't print 'Entering directory ...'
+MAKEFLAGS       += --no-print-directory
+
+# Function for reversing the order of a list
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))
+
+# Hide command output by default, but allow the user to override this
+# by adding V=1 on the command line.
+#
+# This is inspired by the Kbuild system used by the Linux kernel.
+ifdef V
+  ifeq ("$(origin V)", "command line")
+    VERBOSE = $(V)
+  endif
+endif
+ifndef VERBOSE
+  VERBOSE = 0
+endif
+
+ifeq ($(VERBOSE), 1)
+  Q =
+else
+  Q = @
+endif
+
+arflags-gnu-y           := $(ARFLAGS)
+asflags-gnu-y           := $(ASFLAGS)
+cflags-gnu-y            := $(CFLAGS)
+cxxflags-gnu-y          := $(CXXFLAGS)
+cppflags-gnu-y          := $(CPPFLAGS)
+cpuflags-gnu-y          :=
+dbgflags-gnu-y          := $(DBGFLAGS)
+libflags-gnu-y          := $(foreach LIB,$(LIBS),-l$(LIB))
+ldflags-gnu-y           := $(LDFLAGS)
+flashflags-gnu-y        := $(FLASHFLAGS)
+eepromflags-gnu-y       := $(EEPROMFLAGS)
+clean-files             :=
+clean-dirs              :=
+
+clean-files             += $(wildcard $(target) $(project).map)
+clean-files             += $(wildcard $(project).hex $(project).eep)
+clean-files             += $(wildcard $(project).lss $(project).sym)
+clean-files             += $(wildcard $(build))
+
+# Use pipes instead of temporary files for communication between processes
+cflags-gnu-y    += -pipe
+asflags-gnu-y   += -pipe
+ldflags-gnu-y   += -pipe
+
+# Archiver flags.
+arflags-gnu-y   += rcs
+
+# Always enable warnings. And be very careful about implicit
+# declarations.
+cflags-gnu-y    += -Wall -Wstrict-prototypes -Wmissing-prototypes
+cflags-gnu-y    += -Werror-implicit-function-declaration
+cxxflags-gnu-y  += -Wall
+# IAR doesn't allow arithmetic on void pointers, so warn about that.
+cflags-gnu-y    += -Wpointer-arith
+cxxflags-gnu-y  += -Wpointer-arith
+
+# Preprocessor flags.
+cppflags-gnu-y  += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))
+asflags-gnu-y   += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')
+
+# CPU specific flags.
+cpuflags-gnu-y  += -mmcu=$(MCU)
+
+# Dependency file flags.
+depflags        = -MD -MP -MQ $@
+
+# Debug specific flags.
+ifdef BUILD_DEBUG_LEVEL
+dbgflags-gnu-y  += -g$(BUILD_DEBUG_LEVEL)
+else
+dbgflags-gnu-y  += -gdwarf-2
+endif
+
+# Optimization specific flags.
+ifdef BUILD_OPTIMIZATION
+optflags-gnu-y  = -O$(BUILD_OPTIMIZATION)
+else
+optflags-gnu-y  = $(OPTIMIZATION)
+endif
+
+# Relax compilation and linking.
+cflags-gnu-y    += -mrelax
+cxxflags-gnu-y  += -mrelax
+asflags-gnu-y   += -mrelax
+ldflags-gnu-y   += -Wl,--relax
+
+# Always preprocess assembler files.
+asflags-gnu-y   += -x assembler-with-cpp
+# Compile C files using the GNU99 standard.
+cflags-gnu-y    += -std=gnu99
+# Compile C++ files using the GNU++98 standard.
+cxxflags-gnu-y  += -std=gnu++98
+
+# Use unsigned character type when compiling.
+cflags-gnu-y    += -funsigned-char
+cxxflags-gnu-y  += -funsigned-char
+
+# Don't use strict aliasing (very common in embedded applications).
+cflags-gnu-y    += -fno-strict-aliasing
+cxxflags-gnu-y  += -fno-strict-aliasing
+
+# Separate each function and data into its own separate section to allow
+# garbage collection of unused sections.
+cflags-gnu-y    += -ffunction-sections -fdata-sections
+cxxflags-gnu-y  += -ffunction-sections -fdata-sections
+
+# Garbage collect unreferred sections when linking.
+ldflags-gnu-y   += -Wl,--gc-sections
+
+# Output a link map file and a cross reference table
+ldflags-gnu-y   += -Wl,-Map=$(project).map,--cref
+
+# Add library search paths relative to the top level directory.
+ldflags-gnu-y   += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))
+
+a_flags  = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__
+c_flags  = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)
+l_flags  = $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)
+ar_flags = $(arflags-gnu-y)
+
+# Intel Hex file production flags
+flashflags-gnu-y        += -R .eeprom -R .usb_descriptor_table
+
+# Eeprom file production flags
+eepromflags-gnu-y       += -j .eeprom
+eepromflags-gnu-y       += --set-section-flags=.eeprom="alloc,load"
+eepromflags-gnu-y       += --change-section-lma .eeprom=0
+
+# Source files list and part informations must already be included before
+# running this makefile
+
+# If a custom build directory is specified, use it -- force trailing / in directory name.
+ifdef BUILD_DIR
+	build-dir       := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)
+else
+	build-dir        =
+endif
+
+# Create object files list from source files list.
+obj-y                   := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))
+
+# Create dependency files list from source files list.
+dep-files               := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))
+
+clean-files             += $(wildcard $(obj-y))
+clean-files             += $(dep-files)
+
+clean-dirs              += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))
+
+# Default target.
+.PHONY: all
+ifeq ($(target_type),lib)
+all: $(target) $(project).lss $(project).sym
+else
+ifeq ($(target_type),elf)
+all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild
+endif
+endif
+
+prebuild:
+ifneq ($(strip $(PREBUILD_CMD)),)
+	@echo $(MSG_PREBUILD)
+	$(Q)$(PREBUILD_CMD)
+endif
+
+postbuild:
+ifneq ($(strip $(POSTBUILD_CMD)),)
+	@echo $(MSG_POSTBUILD)
+	$(Q)$(POSTBUILD_CMD)
+endif
+
+# Clean up the project.
+.PHONY: clean
+clean:
+	@$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))
+	$(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)
+	@$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))
+# Remove created directories, and make sure we only remove existing
+# directories, since recursive rmdir might help us a bit on the way.
+ifeq ($(os),Windows)
+	$(Q)$(if $(strip $(clean-dirs)),                        \
+			$(RMDIR) $(strip $(subst /,\,$(clean-dirs))))
+else
+	$(Q)$(if $(strip $(clean-dirs)),                        \
+		for directory in $(strip $(clean-dirs)); do     \
+			if [ -d "$$directory" ]; then           \
+				$(RMDIR) $$directory;           \
+			fi                                      \
+		done                                            \
+	)
+endif
+
+# Rebuild the project.
+.PHONY: rebuild
+rebuild: clean all
+
+.PHONY: objfiles
+objfiles: $(obj-y)
+
+# Create object files from C source files.
+$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_COMPILING)
+	$(Q)$(CC) $(c_flags) -c $< -o $@
+
+# Create object files from C++ source files.
+$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_COMPILING_CXX)
+	$(Q)$(CXX) $(cxx_flags) -c $< -o $@
+
+# Preprocess and assemble: create object files from assembler source files.
+$(build-dir)%.o: %.s $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_ASSEMBLING)
+	$(Q)$(CC) $(a_flags) -c $< -o $@
+
+# Preprocess and assemble: create object files from assembler source files.
+$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_ASSEMBLING)
+	$(Q)$(CC) $(a_flags) -c $< -o $@
+
+# Include all dependency files to add depedency to all header files in use.
+include $(dep-files)
+
+ifeq ($(target_type),lib)
+# Archive object files into an archive
+$(target): $(MAKEFILE_PATH) config.mk $(obj-y)
+	@echo $(MSG_ARCHIVING)
+	$(Q)$(AR) $(ar_flags) $@ $(obj-y)
+	@echo $(MSG_SIZE)
+	$(Q)$(SIZE) -Bxt $@
+else
+ifeq ($(target_type),elf)
+# Link the object files into an ELF file. Also make sure the target is rebuilt
+# if the common Makefile.avr.in or project config.mk is changed.
+$(target): $(MAKEFILE_PATH) config.mk $(obj-y)
+	@echo $(MSG_LINKING)
+	$(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@
+	@echo $(MSG_SIZE)
+	$(Q)$(SIZE) -Ax $@
+	$(Q)$(SIZE) -Bx $@
+endif
+endif
+
+# Create extended function listing from target output file.
+%.lss: $(target)
+	@echo $(MSG_EXTENDED_LISTING)
+	$(Q)$(OBJDUMP) -h -S $< > $@
+
+# Create symbol table from target output file.
+%.sym: $(target)
+	@echo $(MSG_SYMBOL_TABLE)
+	$(Q)$(NM) -n $< > $@
+
+# Create Intel HEX image from ELF output file.
+%.hex: $(target)
+	@echo $(MSG_IHEX_IMAGE)
+	$(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y)  $< $@
+
+# Create EEPROM Intel HEX image from ELF output file.
+%.eep: $(target)
+	@echo $(MSG_EEPROM_IMAGE)
+	$(Q)$(OBJCOPY) $(eepromflags-gnu-y) -O ihex $< $@  || exit 0
+
+# Create binary image from ELF output file.
+%.bin: $(target)
+	@echo $(MSG_BINARY_IMAGE)
+	$(Q)$(OBJCOPY) -O binary $< $@
+
+# Provide information about the detected host operating system.
+.SECONDARY: info-os
+info-os:
+	@echo $(MSG_INFO)$(os) build host detected
+
+# Build Doxygen generated documentation.
+.PHONY: doc
+doc:
+	@echo $(MSG_GENERATING_DOC)
+	$(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))
+
+# Clean Doxygen generated documentation.
+.PHONY: cleandoc
+cleandoc:
+	@$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))
+	$(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))
+
+# Rebuild the Doxygen generated documentation.
+.PHONY: rebuilddoc
+rebuilddoc: cleandoc doc
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.c b/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.c
new file mode 100644
index 0000000000..c6a50c059f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.c
@@ -0,0 +1,325 @@
+/**
+ * \file
+ *
+ * \brief Memory bag allocator
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <membag.h>
+#include "conf_membag.h"
+
+/** \internal
+ *
+ *  Retrieves the number of elements in a statically declared array.
+ */
+#define ARRAY_LEN(a) (sizeof(a) / sizeof((a)[0]))
+
+/**
+ * Static address space which is split up into usable chunks by membag.
+ * For configuration details, see \ref membag_list.
+ */
+static uint8_t membag_pool[CONF_MEMBAG_POOL_SIZE];
+
+/**
+ * Internal structure used by membag to keep track of memory,
+ * with maximum 32 blocks per membag.
+ */
+struct membag {
+	/*! Number of bytes per block in this bag. */
+	size_t block_size;
+	/*! Total number of blocks. */
+	size_t num_blocks;
+	/*! Pointer to start of this bag. */
+	uintptr_t start;
+	/*! Pointer to end of this bag. */
+	uintptr_t end;
+	/*! 32-bit integer used to keep track of allocations. */
+	uint32_t allocated;
+	/*! Counter for number of free blocks. */
+	uint8_t blocks_free;
+};
+
+/**
+ * Array of available membags, provided by the user in the applications
+ * conf_membag.h header file. Example:
+ *
+ * \code
+	 #define CONF_MEMBAG_ARRAY \
+	     MEMBAG(32, 4),        \
+	     MEMBAG(16, 2),
+
+	 #define CONF_MEMBAG_POOL_SIZE \
+	     MEMBAG_SIZE(32, 4) +      \
+	     MEMBAG_SIZE(16, 2)
+\endcode
+ *
+ */
+static struct membag membag_list[] = {
+	CONF_MEMBAG_ARRAY
+};
+
+/**
+ * \brief Initialize the membag system.
+ *
+ * This function sets up the membags, allocates memory from the memory pool, and
+ * initializes them. Any existing allocations are destroyed and all memory pools
+ * reset to their initial states.
+ */
+void membag_init(void)
+{
+	uint8_t i;
+	uintptr_t poolptr;
+
+	poolptr = (uintptr_t)membag_pool;
+
+	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
+		Assert(membag_list[i].block_size > 0);
+		Assert(membag_list[i].num_blocks > 0);
+		Assert(membag_list[i].num_blocks <= 32);
+	
+		membag_list[i].start = poolptr;
+		poolptr += (membag_list[i].block_size *
+				membag_list[i].num_blocks);
+		membag_list[i].end = poolptr;
+		membag_list[i].blocks_free = membag_list[i].num_blocks;
+
+		/* Mark all blocks as free. */
+		membag_list[i].allocated = 0;
+	}
+}
+
+/**
+ * \brief Determine the total remaining free memory from all membags.
+ *
+ * \return Sum of all free memory, in bytes.
+ */
+size_t membag_get_total_free(void)
+{
+	uint8_t i;
+	size_t total_free = 0;
+
+	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
+		total_free += membag_list[i].blocks_free *
+				membag_list[i].block_size;
+	}
+
+	return total_free;
+}
+
+/**
+ * \brief Determine the total memory from all membags.
+ *
+ * \return Sum of all blocks in all bags, in bytes.
+ */
+size_t membag_get_total(void)
+{
+	uint8_t i;
+	size_t total = 0;
+
+	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
+		total += membag_list[i].num_blocks * membag_list[i].block_size;
+	}
+
+	return total;
+}
+
+/**
+ * \brief Determine the smallest available block size.
+ *
+ * Calculates the smallest block which can be allocated by the Membag allocator
+ * if requested. Allocations larger than this amount are not guaranteed to
+ * complete successfully.
+ *
+ * \return Size of the smallest available block, in bytes.
+ */
+size_t membag_get_smallest_free_block_size(void)
+{
+	uint8_t i;
+	struct membag *smallest_bag = NULL;
+
+	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
+		if (membag_list[i].blocks_free == 0) {
+			continue;
+		}
+
+		if (!smallest_bag ||
+				(smallest_bag->block_size > membag_list[i].block_size)) {
+			smallest_bag = &membag_list[i];
+		}
+	}
+
+	if (smallest_bag) {
+		return smallest_bag->block_size;
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Determine the largest available block size.
+ *
+ * Calculates the largest block which can be allocated by the Membag allocator
+ * if requested. Allocations larger than this amount are guaranteed to fail.
+ *
+ * \return Size of the largest available block, in bytes.
+ */
+size_t membag_get_largest_free_block_size(void)
+{
+	uint8_t i;
+	struct membag *largest_bag = NULL;
+
+	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
+		if (membag_list[i].blocks_free == 0) {
+			continue;
+		}
+
+		if (!largest_bag ||
+				(largest_bag->block_size < membag_list[i].block_size)) {
+			largest_bag = &membag_list[i];
+		}
+	}
+
+	if (largest_bag) {
+		return largest_bag->block_size;
+	}
+	
+	return 0;
+}
+
+/**
+ * \brief Allocate a memory block via a block from the Membag pool
+ *
+ * Allocates memory to the user from one of the available Membag pools. Each
+ * Membag pool is examined in sequence, and the first free block of sufficient
+ * size (if any) is chosen for the allocation. Allocated blocks persist until
+ * either the Membag module is re-initialized, or an allocation block is freed
+ * via \ref membag_free().
+ *
+ * \note The execution cycle time for this function is not deterministic; each
+ *       allocation request may take a variable amount of cycles to complete.
+ *
+ * \param size Size of memory block requested, in bytes
+ *
+ * \return Pointer to the start of an allocated block if one was found in the
+ *         Membag pool, NULL if no suitable block was found.
+ */
+void *membag_alloc(const size_t size)
+{
+	uint8_t i;
+	struct membag *smallest_bag = NULL;
+	uintptr_t p;
+
+	/* Find the smallest available block size big enough for the requested
+	 * memory chunk size. */
+	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
+		if (membag_list[i].blocks_free == 0) {
+			continue;
+		}
+
+		if (membag_list[i].block_size >= size) {
+			if (!smallest_bag ||
+					(smallest_bag->block_size > membag_list[i].block_size)) {
+				smallest_bag = &membag_list[i];
+			}
+		}
+	}
+
+	/* We return the first available block in the bag that has one, and if
+	 * there is none, we return NULL.
+	 */
+	if (smallest_bag) {
+		/* We know that there is a free block within the membag's
+		 * memory, and we simply return the first one available.
+		 */
+		p = smallest_bag->start;
+
+		for (i = 0; i < smallest_bag->num_blocks; i++) {
+			/* Check the allocation byte to see whether the block is
+			 * in use. */
+			if (!(smallest_bag->allocated & ((uint32_t)1 << i))) {
+				/* It is free, set it to used. */
+				smallest_bag->allocated |= ((uint32_t)1 << i);
+				smallest_bag->blocks_free--;
+
+				return (void *)(p);
+			}
+
+			p += smallest_bag->block_size;
+		}
+	}
+
+	/* There is no available memory. Return NULL. */
+	return NULL;
+}
+
+/**
+ * \brief Free a previously allocated memory block from the Membag pool
+ *
+ * This function frees memory which has been allocated previously via a
+ * successful call to \ref membag_alloc(). Once deallocated, the given pointer
+ * is no longer valid and should not be used in the user application unless
+ * re-allocated.
+ *
+ * \note The execution cycle time for this function is not deterministic; each
+ *       allocation request may take a variable amount of cycles to complete.
+ *
+ * \param ptr Pointer to an allocated memory block to free
+ */
+void membag_free(const void *ptr)
+{
+	uint8_t i;
+	uintptr_t p = (uintptr_t)ptr;
+	uint8_t block_index;
+
+	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
+		if (p >= membag_list[i].start && p < membag_list[i].end) {
+			block_index = (p - membag_list[i].start) / membag_list[i].block_size;
+			
+			/* Mark the memory as free. */
+			membag_list[i].allocated &= ~((uint32_t)1 << block_index);
+			membag_list[i].blocks_free++;
+
+			return;
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.h b/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.h
new file mode 100644
index 0000000000..88495a53d3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.h
@@ -0,0 +1,123 @@
+/**
+ * \file
+ *
+ * \brief Memory Bag allocator for 8-bit AVR, 32-bit AVR, SAM
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef UTILS_MEMBAG_H
+#define UTILS_MEMBAG_H
+
+#include <stddef.h>
+
+/**
+ * \defgroup membag_group Memory Bag Allocator
+ *
+ * The Membag allocator is a optimized, fragmentationless general purpose
+ * memory allocator utility module designed to replace the standard C library
+ * \c malloc() and \c free() functions in resource constrained environments.
+ *
+ *
+ * Internally, the Membag allocator uses several user defined "bags" of one or
+ * more fixed-size blocks to form a memory pool for use in a user application.
+ * When an allocation is requested, the Membag module will search all available
+ * bags and find the smallest unallocated block of sufficient size, and return
+ * this block to the calling function. The size of each bag and number of blocks
+ * in each bag is user configurable, via the \ref conf_membag.h header file
+ * added to the user project.
+ *
+ * The allocator also has basic statistics functionality to obtain the size of
+ * the entire memory pool, amount of free memory, and the size of the smallest
+ * and largest free memory block.
+ *
+ * The memory bag allocator always allocates memory as a block from a fixed size
+ * bag/pool. This helps reduce memory fragmentation compared to an generic
+ * allocator that gives exactly the bytes requested. While this gives a
+ * trade-off of the maximum number of concurrent allocations and the size of
+ * allocations that are allowable, the allocator prevents memory fragmentation
+ * from occuring in an embedded application.
+ *
+ * The allocation and deallocation of memory with the Membag module is
+ * non-deterministic, however the module functions all have a maximum run time
+ * that is dependent on the number of bags that have been configured.
+ *
+ * @{
+ */
+
+/**
+ * Macro used to create memory bags in conf_membag.h
+ *
+ * \note Multiple bags of the same size are allowed, if more than 32 bags of a
+ *       given size are required in an application.
+ *
+ * \param objsize  Size of each block in the bag
+ * \param nr_objs  Number of blocks in the bag, a value less than 32
+ */
+#define MEMBAG(objsize, nr_objs)\
+	{ .block_size = objsize, .num_blocks = nr_objs }
+
+/**
+ * Macro used to store the size of the membags in conf_membag.h
+ *
+ * \note Multiple bags of the same size are allowed, if more than 32 bags of a
+ *       given size are required in an application.
+ *
+ * \param objsize  Size of each block in the bag
+ * \param nr_objs  Number of blocks in the bag, a value less than 32
+ */
+#define MEMBAG_SIZE(objsize, nr_objs)\
+	(objsize * nr_objs)
+
+void membag_init(void);
+
+size_t membag_get_total(void);
+size_t membag_get_total_free(void);
+
+size_t membag_get_smallest_free_block_size(void);
+size_t membag_get_largest_free_block_size(void);
+
+void *membag_alloc(const size_t size);
+void membag_free(const void *ptr);
+
+/** @} */
+
+#endif /* UTILS_MEMBAG_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/membag/module_config/conf_membag.h b/bsp/samd21/sam_d2x_asflib/common/utils/membag/module_config/conf_membag.h
new file mode 100644
index 0000000000..3112435145
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/membag/module_config/conf_membag.h
@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief Membag configuration header
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_MEMBAG_H
+#define CONF_MEMBAG_H
+
+#include <membag.h>
+
+#define CONF_MEMBAG_ARRAY\
+	MEMBAG(16, 5),\
+	MEMBAG(64, 2),\
+	MEMBAG(128, 10),
+
+#define CONF_MEMBAG_POOL_SIZE\
+	MEMBAG_SIZE(16, 5) +\
+	MEMBAG_SIZE(64, 2) +\
+	MEMBAG_SIZE(128, 10)
+
+#endif /* CONF_MEMBAG_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.c b/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.c
new file mode 100644
index 0000000000..e50748b4c0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.c
@@ -0,0 +1,103 @@
+/**
+ *
+ * \file
+ *
+ * \brief
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include "asf.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "FreeRTOS.h"
+#include "osprintf.h"
+
+xSemaphoreHandle trace_lock;
+
+void osprintf_init(void *usart, const void *opt)
+{
+	trace_lock = xSemaphoreCreateMutex();
+	stdio_serial_init(usart, opt);
+}
+
+void osprintf(const char *fmt, ...)
+{
+	va_list args;
+	va_start(args, fmt);
+	xSemaphoreTake(trace_lock, portMAX_DELAY);
+	vprintf(fmt, args);
+	xSemaphoreGive(trace_lock);
+	va_end(args);
+}
+
+void osprint(const char *s)
+{
+	xSemaphoreTake(trace_lock, portMAX_DELAY);
+	puts(s);
+	xSemaphoreGive(trace_lock);		
+}
+
+void osprint_hex_array(uint8_t *p, int sz)
+{
+	xSemaphoreTake(trace_lock, portMAX_DELAY);
+	while (sz) {
+		if (sz < 8) {
+			while (sz--) {
+				printf("%02x ", *p);
+				p++;
+			}
+			break;
+		} 
+		printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",
+				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+		p += 8;
+		sz -= 8;
+	}
+	printf("\n");
+	xSemaphoreGive(trace_lock);
+}
+ 
+void osprint_sem_take(void)
+{
+	xSemaphoreTake(trace_lock, portMAX_DELAY);
+}
+
+void osprint_sem_give(void)
+{
+	xSemaphoreGive(trace_lock);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.h b/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.h
new file mode 100644
index 0000000000..5c3593316c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.h
@@ -0,0 +1,59 @@
+/**
+ *
+ * \file
+ *
+ * \brief
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef OSPRINTF_H_INCLUDED
+#define OSPRINTF_H_INCLUDED
+
+#include "compiler.h"
+
+void osprintf_init(void *usart, const void *opt);
+void osprintf(const char *fmt, ...) __attribute__ ((format (gnu_printf, 1, 0)));
+
+void osprint(const char *s);
+void osprint_hex_array(uint8_t *p, int sz);
+
+void osprint_sem_take(void);
+void osprint_sem_give(void);
+
+#endif /* OSPRINTF_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/parts.h b/bsp/samd21/sam_d2x_asflib/common/utils/parts.h
new file mode 100644
index 0000000000..27cbe5fd2f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/parts.h
@@ -0,0 +1,1594 @@
+/**
+ * \file
+ *
+ * \brief Atmel part identification macros
+ *
+ * Copyright (C) 2012-2017 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef ATMEL_PARTS_H
+#define ATMEL_PARTS_H
+
+/**
+ * \defgroup part_macros_group Atmel part identification macros
+ *
+ * This collection of macros identify which series and families that the various
+ * Atmel parts belong to. These can be used to select part-dependent sections of
+ * code at compile time.
+ *
+ * @{
+ */
+
+/**
+ * \name Convenience macros for part checking
+ * @{
+ */
+/* ! Check GCC and IAR part definition for 8-bit AVR */
+#define AVR8_PART_IS_DEFINED(part) \
+	(defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
+
+/* ! Check GCC and IAR part definition for 32-bit AVR */
+#define AVR32_PART_IS_DEFINED(part) \
+	(defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
+
+/* ! Check GCC and IAR part definition for SAM */
+#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))
+/** @} */
+
+/**
+ * \defgroup uc3_part_macros_group AVR UC3 parts
+ * @{
+ */
+
+/**
+ * \name AVR UC3 A series
+ * @{
+ */
+#define UC3A0 (	\
+		AVR32_PART_IS_DEFINED(UC3A0128) || \
+		AVR32_PART_IS_DEFINED(UC3A0256) || \
+		AVR32_PART_IS_DEFINED(UC3A0512)	\
+		)
+
+#define UC3A1 (	\
+		AVR32_PART_IS_DEFINED(UC3A1128) || \
+		AVR32_PART_IS_DEFINED(UC3A1256) || \
+		AVR32_PART_IS_DEFINED(UC3A1512)	\
+		)
+
+#define UC3A3 (	\
+		AVR32_PART_IS_DEFINED(UC3A364)   || \
+		AVR32_PART_IS_DEFINED(UC3A364S)  || \
+		AVR32_PART_IS_DEFINED(UC3A3128)  || \
+		AVR32_PART_IS_DEFINED(UC3A3128S) || \
+		AVR32_PART_IS_DEFINED(UC3A3256)  || \
+		AVR32_PART_IS_DEFINED(UC3A3256S) \
+		)
+
+#define UC3A4 (	\
+		AVR32_PART_IS_DEFINED(UC3A464)   || \
+		AVR32_PART_IS_DEFINED(UC3A464S)  || \
+		AVR32_PART_IS_DEFINED(UC3A4128)  || \
+		AVR32_PART_IS_DEFINED(UC3A4128S) || \
+		AVR32_PART_IS_DEFINED(UC3A4256)  || \
+		AVR32_PART_IS_DEFINED(UC3A4256S) \
+		)
+/** @} */
+
+/**
+ * \name AVR UC3 B series
+ * @{
+ */
+#define UC3B0 (	\
+		AVR32_PART_IS_DEFINED(UC3B064)  || \
+		AVR32_PART_IS_DEFINED(UC3B0128) || \
+		AVR32_PART_IS_DEFINED(UC3B0256) || \
+		AVR32_PART_IS_DEFINED(UC3B0512)	\
+		)
+
+#define UC3B1 (	\
+		AVR32_PART_IS_DEFINED(UC3B164)  || \
+		AVR32_PART_IS_DEFINED(UC3B1128) || \
+		AVR32_PART_IS_DEFINED(UC3B1256) || \
+		AVR32_PART_IS_DEFINED(UC3B1512)	\
+		)
+/** @} */
+
+/**
+ * \name AVR UC3 C series
+ * @{
+ */
+#define UC3C0 (	\
+		AVR32_PART_IS_DEFINED(UC3C064C)  || \
+		AVR32_PART_IS_DEFINED(UC3C0128C) || \
+		AVR32_PART_IS_DEFINED(UC3C0256C) || \
+		AVR32_PART_IS_DEFINED(UC3C0512C) \
+		)
+
+#define UC3C1 (	\
+		AVR32_PART_IS_DEFINED(UC3C164C)  || \
+		AVR32_PART_IS_DEFINED(UC3C1128C) || \
+		AVR32_PART_IS_DEFINED(UC3C1256C) || \
+		AVR32_PART_IS_DEFINED(UC3C1512C) \
+		)
+
+#define UC3C2 (	\
+		AVR32_PART_IS_DEFINED(UC3C264C)  || \
+		AVR32_PART_IS_DEFINED(UC3C2128C) || \
+		AVR32_PART_IS_DEFINED(UC3C2256C) || \
+		AVR32_PART_IS_DEFINED(UC3C2512C) \
+		)
+/** @} */
+
+/**
+ * \name AVR UC3 D series
+ * @{
+ */
+#define UC3D3 (	\
+		AVR32_PART_IS_DEFINED(UC64D3)  || \
+		AVR32_PART_IS_DEFINED(UC128D3) \
+		)
+
+#define UC3D4 (	\
+		AVR32_PART_IS_DEFINED(UC64D4)  || \
+		AVR32_PART_IS_DEFINED(UC128D4) \
+		)
+/** @} */
+
+/**
+ * \name AVR UC3 L series
+ * @{
+ */
+#define UC3L0 (	\
+		AVR32_PART_IS_DEFINED(UC3L016) || \
+		AVR32_PART_IS_DEFINED(UC3L032) || \
+		AVR32_PART_IS_DEFINED(UC3L064) \
+		)
+
+#define UC3L0128 ( \
+		AVR32_PART_IS_DEFINED(UC3L0128)	\
+		)
+
+#define UC3L0256 ( \
+		AVR32_PART_IS_DEFINED(UC3L0256)	\
+		)
+
+#define UC3L3 (	\
+		AVR32_PART_IS_DEFINED(UC64L3U)  || \
+		AVR32_PART_IS_DEFINED(UC128L3U) || \
+		AVR32_PART_IS_DEFINED(UC256L3U)	\
+		)
+
+#define UC3L4 (	\
+		AVR32_PART_IS_DEFINED(UC64L4U)  || \
+		AVR32_PART_IS_DEFINED(UC128L4U) || \
+		AVR32_PART_IS_DEFINED(UC256L4U)	\
+		)
+
+#define UC3L3_L4 (UC3L3 || UC3L4)
+/** @} */
+
+/**
+ * \name AVR UC3 families
+ * @{
+ */
+/** AVR UC3 A family */
+#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)
+
+/** AVR UC3 B family */
+#define UC3B (UC3B0 || UC3B1)
+
+/** AVR UC3 C family */
+#define UC3C (UC3C0 || UC3C1 || UC3C2)
+
+/** AVR UC3 D family */
+#define UC3D (UC3D3 || UC3D4)
+
+/** AVR UC3 L family */
+#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)
+/** @} */
+
+/** AVR UC3 product line */
+#define UC3  (UC3A || UC3B || UC3C || UC3D || UC3L)
+
+/** @} */
+
+/**
+ * \defgroup xmega_part_macros_group AVR XMEGA parts
+ * @{
+ */
+
+/**
+ * \name AVR XMEGA A series
+ * @{
+ */
+#define XMEGA_A1 ( \
+		AVR8_PART_IS_DEFINED(ATxmega64A1)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A1) \
+		)
+
+#define XMEGA_A3 ( \
+		AVR8_PART_IS_DEFINED(ATxmega64A3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A3) || \
+		AVR8_PART_IS_DEFINED(ATxmega192A3) || \
+		AVR8_PART_IS_DEFINED(ATxmega256A3) \
+		)
+
+#define XMEGA_A3B ( \
+		AVR8_PART_IS_DEFINED(ATxmega256A3B) \
+		)
+
+#define XMEGA_A4 ( \
+		AVR8_PART_IS_DEFINED(ATxmega16A4) || \
+		AVR8_PART_IS_DEFINED(ATxmega32A4) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA AU series
+ * @{
+ */
+#define XMEGA_A1U ( \
+		AVR8_PART_IS_DEFINED(ATxmega64A1U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A1U) \
+		)
+
+#define XMEGA_A3U ( \
+		AVR8_PART_IS_DEFINED(ATxmega64A3U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
+		AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
+		AVR8_PART_IS_DEFINED(ATxmega256A3U) \
+		)
+
+#define XMEGA_A3BU ( \
+		AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
+		)
+
+#define XMEGA_A4U ( \
+		AVR8_PART_IS_DEFINED(ATxmega16A4U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega32A4U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega64A4U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A4U) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA B series
+ * @{
+ */
+#define XMEGA_B1  ( \
+		AVR8_PART_IS_DEFINED(ATxmega64B1)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128B1) \
+		)
+
+#define XMEGA_B3  ( \
+		AVR8_PART_IS_DEFINED(ATxmega64B3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128B3) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA C series
+ * @{
+ */
+#define XMEGA_C3 ( \
+		AVR8_PART_IS_DEFINED(ATxmega384C3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega256C3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega192C3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128C3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega64C3)   || \
+		AVR8_PART_IS_DEFINED(ATxmega32C3) \
+		)
+
+#define XMEGA_C4 ( \
+		AVR8_PART_IS_DEFINED(ATxmega32C4)  || \
+		AVR8_PART_IS_DEFINED(ATxmega16C4) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA D series
+ * @{
+ */
+#define XMEGA_D3 ( \
+		AVR8_PART_IS_DEFINED(ATxmega32D3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega64D3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128D3) || \
+		AVR8_PART_IS_DEFINED(ATxmega192D3) || \
+		AVR8_PART_IS_DEFINED(ATxmega256D3) || \
+		AVR8_PART_IS_DEFINED(ATxmega384D3) \
+		)
+
+#define XMEGA_D4 ( \
+		AVR8_PART_IS_DEFINED(ATxmega16D4)  || \
+		AVR8_PART_IS_DEFINED(ATxmega32D4)  || \
+		AVR8_PART_IS_DEFINED(ATxmega64D4)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128D4) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA E series
+ * @{
+ */
+#define XMEGA_E5 ( \
+		AVR8_PART_IS_DEFINED(ATxmega8E5)   || \
+		AVR8_PART_IS_DEFINED(ATxmega16E5)  || \
+		AVR8_PART_IS_DEFINED(ATxmega32E5)     \
+	)
+/** @} */
+
+
+/**
+ * \name AVR XMEGA families
+ * @{
+ */
+/** AVR XMEGA A family */
+#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)
+
+/** AVR XMEGA AU family */
+#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)
+
+/** AVR XMEGA B family */
+#define XMEGA_B (XMEGA_B1 || XMEGA_B3)
+
+/** AVR XMEGA C family */
+#define XMEGA_C (XMEGA_C3 || XMEGA_C4)
+
+/** AVR XMEGA D family */
+#define XMEGA_D (XMEGA_D3 || XMEGA_D4)
+
+/** AVR XMEGA E family */
+#define XMEGA_E (XMEGA_E5)
+/** @} */
+
+
+/** AVR XMEGA product line */
+#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)
+
+/** @} */
+
+/**
+ * \defgroup mega_part_macros_group megaAVR parts
+ *
+ * \note These megaAVR groupings are based on the groups in AVR Libc for the
+ * part header files. They are not names of official megaAVR device series or
+ * families.
+ *
+ * @{
+ */
+
+/**
+ * \name ATmegaxx0/xx1 subgroups
+ * @{
+ */
+#define MEGA_XX0 ( \
+		AVR8_PART_IS_DEFINED(ATmega640)  || \
+		AVR8_PART_IS_DEFINED(ATmega1280) || \
+		AVR8_PART_IS_DEFINED(ATmega2560) \
+		)
+
+#define MEGA_XX1 ( \
+		AVR8_PART_IS_DEFINED(ATmega1281) || \
+		AVR8_PART_IS_DEFINED(ATmega2561) \
+		)
+/** @} */
+
+/**
+ * \name megaAVR groups
+ * @{
+ */
+/** ATmegaxx0/xx1 group */
+#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)
+
+/** ATmegaxx4 group */
+#define MEGA_XX4 ( \
+		AVR8_PART_IS_DEFINED(ATmega164A)  || \
+		AVR8_PART_IS_DEFINED(ATmega164PA) || \
+		AVR8_PART_IS_DEFINED(ATmega324A)  || \
+		AVR8_PART_IS_DEFINED(ATmega324PA) || \
+		AVR8_PART_IS_DEFINED(ATmega324PB) || \
+		AVR8_PART_IS_DEFINED(ATmega644)   || \
+		AVR8_PART_IS_DEFINED(ATmega644A)  || \
+		AVR8_PART_IS_DEFINED(ATmega644PA) || \
+		AVR8_PART_IS_DEFINED(ATmega1284P)   || \
+		AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+		)
+
+/** ATmegaxx4 group */
+#define MEGA_XX4_A ( \
+		AVR8_PART_IS_DEFINED(ATmega164A)  || \
+		AVR8_PART_IS_DEFINED(ATmega164PA) || \
+		AVR8_PART_IS_DEFINED(ATmega324A)  || \
+		AVR8_PART_IS_DEFINED(ATmega324PA) || \
+		AVR8_PART_IS_DEFINED(ATmega644A)  || \
+		AVR8_PART_IS_DEFINED(ATmega644PA) || \
+		AVR8_PART_IS_DEFINED(ATmega1284P) \
+		)
+
+/** ATmegaxx8 group */
+#define MEGA_XX8 ( \
+		AVR8_PART_IS_DEFINED(ATmega48)    || \
+		AVR8_PART_IS_DEFINED(ATmega48A)   || \
+		AVR8_PART_IS_DEFINED(ATmega48PA)  || \
+		AVR8_PART_IS_DEFINED(ATmega48PB)  || \
+		AVR8_PART_IS_DEFINED(ATmega88)    || \
+		AVR8_PART_IS_DEFINED(ATmega88A)   || \
+		AVR8_PART_IS_DEFINED(ATmega88PA)  || \
+		AVR8_PART_IS_DEFINED(ATmega88PB)  || \
+		AVR8_PART_IS_DEFINED(ATmega168)   || \
+		AVR8_PART_IS_DEFINED(ATmega168A)  || \
+		AVR8_PART_IS_DEFINED(ATmega168PA) || \
+		AVR8_PART_IS_DEFINED(ATmega168PB) || \
+		AVR8_PART_IS_DEFINED(ATmega328)   || \
+		AVR8_PART_IS_DEFINED(ATmega328P)  || \
+		AVR8_PART_IS_DEFINED(ATmega328PB) \
+		)
+
+/** ATmegaxx8A/P/PA group */
+#define MEGA_XX8_A ( \
+		AVR8_PART_IS_DEFINED(ATmega48A)   || \
+		AVR8_PART_IS_DEFINED(ATmega48PA)  || \
+		AVR8_PART_IS_DEFINED(ATmega88A)   || \
+		AVR8_PART_IS_DEFINED(ATmega88PA)  || \
+		AVR8_PART_IS_DEFINED(ATmega168A)  || \
+		AVR8_PART_IS_DEFINED(ATmega168PA) || \
+		AVR8_PART_IS_DEFINED(ATmega328P) \
+		)
+
+/** ATmegaxx group */
+#define MEGA_XX ( \
+		AVR8_PART_IS_DEFINED(ATmega16)   || \
+		AVR8_PART_IS_DEFINED(ATmega16A)  || \
+		AVR8_PART_IS_DEFINED(ATmega32)   || \
+		AVR8_PART_IS_DEFINED(ATmega32A)  || \
+		AVR8_PART_IS_DEFINED(ATmega64)   || \
+		AVR8_PART_IS_DEFINED(ATmega64A)  || \
+		AVR8_PART_IS_DEFINED(ATmega128)  || \
+		AVR8_PART_IS_DEFINED(ATmega128A) \
+		)
+
+/** ATmegaxxA/P/PA group */
+#define MEGA_XX_A ( \
+		AVR8_PART_IS_DEFINED(ATmega16A)  || \
+		AVR8_PART_IS_DEFINED(ATmega32A)  || \
+		AVR8_PART_IS_DEFINED(ATmega64A)  || \
+		AVR8_PART_IS_DEFINED(ATmega128A) \
+		)
+/** ATmegaxxRFA1 group */
+#define MEGA_RFA1 ( \
+		AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+		)
+
+/** ATmegaxxRFR2 group */
+#define MEGA_RFR2 ( \
+		AVR8_PART_IS_DEFINED(ATmega64RFR2)   || \
+		AVR8_PART_IS_DEFINED(ATmega128RFR2)  || \
+		AVR8_PART_IS_DEFINED(ATmega256RFR2)  || \
+		AVR8_PART_IS_DEFINED(ATmega644RFR2)  || \
+		AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
+		AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
+		)
+
+
+/** ATmegaxxRFxx group */
+#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)
+
+/**
+ * \name ATmegaxx_un0/un1/un2 subgroups
+ * @{
+ */
+#define MEGA_XX_UN0 ( \
+		AVR8_PART_IS_DEFINED(ATmega16)    || \
+		AVR8_PART_IS_DEFINED(ATmega16A)   || \
+		AVR8_PART_IS_DEFINED(ATmega32)    || \
+		AVR8_PART_IS_DEFINED(ATmega32A)	\
+		)
+
+/** ATmegaxx group without power reduction and
+ *  And interrupt sense register.
+ */
+#define MEGA_XX_UN1 ( \
+		AVR8_PART_IS_DEFINED(ATmega64)    || \
+		AVR8_PART_IS_DEFINED(ATmega64A)   || \
+		AVR8_PART_IS_DEFINED(ATmega128)   || \
+		AVR8_PART_IS_DEFINED(ATmega128A) \
+		)
+
+/** ATmegaxx group without power reduction and
+ *  And interrupt sense register.
+ */
+#define MEGA_XX_UN2 ( \
+		AVR8_PART_IS_DEFINED(ATmega169P)  || \
+		AVR8_PART_IS_DEFINED(ATmega169PA) || \
+		AVR8_PART_IS_DEFINED(ATmega329P)  || \
+		AVR8_PART_IS_DEFINED(ATmega329PA) \
+		)
+
+/** Devices added to complete megaAVR offering.
+ *  Please do not use this group symbol as it is not intended
+ *  to be permanent: the devices should be regrouped.
+ */
+#define MEGA_UNCATEGORIZED ( \
+		AVR8_PART_IS_DEFINED(AT90CAN128)     || \
+		AVR8_PART_IS_DEFINED(AT90CAN32)      || \
+		AVR8_PART_IS_DEFINED(AT90CAN64)      || \
+		AVR8_PART_IS_DEFINED(AT90PWM1)       || \
+		AVR8_PART_IS_DEFINED(AT90PWM216)     || \
+		AVR8_PART_IS_DEFINED(AT90PWM2B)      || \
+		AVR8_PART_IS_DEFINED(AT90PWM316)     || \
+		AVR8_PART_IS_DEFINED(AT90PWM3B)      || \
+		AVR8_PART_IS_DEFINED(AT90PWM81)      || \
+		AVR8_PART_IS_DEFINED(AT90USB1286)    || \
+		AVR8_PART_IS_DEFINED(AT90USB1287)    || \
+		AVR8_PART_IS_DEFINED(AT90USB162)     || \
+		AVR8_PART_IS_DEFINED(AT90USB646)     || \
+		AVR8_PART_IS_DEFINED(AT90USB647)     || \
+		AVR8_PART_IS_DEFINED(AT90USB82)      || \
+		AVR8_PART_IS_DEFINED(ATmega1284)     || \
+		AVR8_PART_IS_DEFINED(ATmega162)      || \
+		AVR8_PART_IS_DEFINED(ATmega164P)     || \
+		AVR8_PART_IS_DEFINED(ATmega165A)     || \
+		AVR8_PART_IS_DEFINED(ATmega165P)     || \
+		AVR8_PART_IS_DEFINED(ATmega165PA)    || \
+		AVR8_PART_IS_DEFINED(ATmega168P)     || \
+		AVR8_PART_IS_DEFINED(ATmega169A)     || \
+		AVR8_PART_IS_DEFINED(ATmega16M1)     || \
+		AVR8_PART_IS_DEFINED(ATmega16U2)     || \
+		AVR8_PART_IS_DEFINED(ATmega16U4)     || \
+		AVR8_PART_IS_DEFINED(ATmega256RFA2)  || \
+		AVR8_PART_IS_DEFINED(ATmega324P)     || \
+		AVR8_PART_IS_DEFINED(ATmega325)      || \
+		AVR8_PART_IS_DEFINED(ATmega3250)     || \
+		AVR8_PART_IS_DEFINED(ATmega3250A)    || \
+		AVR8_PART_IS_DEFINED(ATmega3250P)    || \
+		AVR8_PART_IS_DEFINED(ATmega3250PA)   || \
+		AVR8_PART_IS_DEFINED(ATmega325A)     || \
+		AVR8_PART_IS_DEFINED(ATmega325P)     || \
+		AVR8_PART_IS_DEFINED(ATmega325PA)    || \
+		AVR8_PART_IS_DEFINED(ATmega329)      || \
+		AVR8_PART_IS_DEFINED(ATmega3290)     || \
+		AVR8_PART_IS_DEFINED(ATmega3290A)    || \
+		AVR8_PART_IS_DEFINED(ATmega3290P)    || \
+		AVR8_PART_IS_DEFINED(ATmega3290PA)   || \
+		AVR8_PART_IS_DEFINED(ATmega329A)     || \
+		AVR8_PART_IS_DEFINED(ATmega32M1)     || \
+		AVR8_PART_IS_DEFINED(ATmega32U2)     || \
+		AVR8_PART_IS_DEFINED(ATmega32U4)     || \
+		AVR8_PART_IS_DEFINED(ATmega48P)      || \
+		AVR8_PART_IS_DEFINED(ATmega644P)     || \
+		AVR8_PART_IS_DEFINED(ATmega645)      || \
+		AVR8_PART_IS_DEFINED(ATmega6450)     || \
+		AVR8_PART_IS_DEFINED(ATmega6450A)    || \
+		AVR8_PART_IS_DEFINED(ATmega6450P)    || \
+		AVR8_PART_IS_DEFINED(ATmega645A)     || \
+		AVR8_PART_IS_DEFINED(ATmega645P)     || \
+		AVR8_PART_IS_DEFINED(ATmega649)      || \
+		AVR8_PART_IS_DEFINED(ATmega6490)     || \
+		AVR8_PART_IS_DEFINED(ATmega6490A)    || \
+		AVR8_PART_IS_DEFINED(ATmega6490P)    || \
+		AVR8_PART_IS_DEFINED(ATmega649A)     || \
+		AVR8_PART_IS_DEFINED(ATmega649P)     || \
+		AVR8_PART_IS_DEFINED(ATmega64M1)     || \
+		AVR8_PART_IS_DEFINED(ATmega64RFA2)   || \
+		AVR8_PART_IS_DEFINED(ATmega8)        || \
+		AVR8_PART_IS_DEFINED(ATmega8515)     || \
+		AVR8_PART_IS_DEFINED(ATmega8535)     || \
+		AVR8_PART_IS_DEFINED(ATmega88P)      || \
+		AVR8_PART_IS_DEFINED(ATmega8A)       || \
+		AVR8_PART_IS_DEFINED(ATmega8U2)         \
+	)
+
+/** Unspecified group */
+#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \
+	MEGA_UNCATEGORIZED)
+
+/** @} */
+
+/** megaAVR product line */
+#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \
+	MEGA_UNSPECIFIED)
+
+/** @} */
+
+/**
+ * \defgroup sam_part_macros_group SAM parts
+ * @{
+ */
+
+/**
+ * \name SAM3S series
+ * @{
+ */
+#define SAM3S1 ( \
+		SAM_PART_IS_DEFINED(SAM3S1A) ||	\
+		SAM_PART_IS_DEFINED(SAM3S1B) ||	\
+		SAM_PART_IS_DEFINED(SAM3S1C) \
+		)
+
+#define SAM3S2 ( \
+		SAM_PART_IS_DEFINED(SAM3S2A) ||	\
+		SAM_PART_IS_DEFINED(SAM3S2B) ||	\
+		SAM_PART_IS_DEFINED(SAM3S2C) \
+		)
+
+#define SAM3S4 ( \
+		SAM_PART_IS_DEFINED(SAM3S4A) ||	\
+		SAM_PART_IS_DEFINED(SAM3S4B) ||	\
+		SAM_PART_IS_DEFINED(SAM3S4C) \
+		)
+
+#define SAM3S8 ( \
+		SAM_PART_IS_DEFINED(SAM3S8B) ||	\
+		SAM_PART_IS_DEFINED(SAM3S8C) \
+		)
+
+#define SAM3SD8 ( \
+		SAM_PART_IS_DEFINED(SAM3SD8B) || \
+		SAM_PART_IS_DEFINED(SAM3SD8C) \
+		)
+/** @} */
+
+/**
+ * \name SAM3U series
+ * @{
+ */
+#define SAM3U1 ( \
+		SAM_PART_IS_DEFINED(SAM3U1C) ||	\
+		SAM_PART_IS_DEFINED(SAM3U1E) \
+		)
+
+#define SAM3U2 ( \
+		SAM_PART_IS_DEFINED(SAM3U2C) ||	\
+		SAM_PART_IS_DEFINED(SAM3U2E) \
+		)
+
+#define SAM3U4 ( \
+		SAM_PART_IS_DEFINED(SAM3U4C) ||	\
+		SAM_PART_IS_DEFINED(SAM3U4E) \
+		)
+/** @} */
+
+/**
+ * \name SAM3N series
+ * @{
+ */
+#define SAM3N00 ( \
+		SAM_PART_IS_DEFINED(SAM3N00A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N00B) \
+		)
+
+#define SAM3N0 ( \
+		SAM_PART_IS_DEFINED(SAM3N0A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N0B) ||	\
+		SAM_PART_IS_DEFINED(SAM3N0C) \
+		)
+
+#define SAM3N1 ( \
+		SAM_PART_IS_DEFINED(SAM3N1A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N1B) ||	\
+		SAM_PART_IS_DEFINED(SAM3N1C) \
+		)
+
+#define SAM3N2 ( \
+		SAM_PART_IS_DEFINED(SAM3N2A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N2B) ||	\
+		SAM_PART_IS_DEFINED(SAM3N2C) \
+		)
+
+#define SAM3N4 ( \
+		SAM_PART_IS_DEFINED(SAM3N4A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N4B) ||	\
+		SAM_PART_IS_DEFINED(SAM3N4C) \
+		)
+/** @} */
+
+/**
+ * \name SAM3X series
+ * @{
+ */
+#define SAM3X4 ( \
+		SAM_PART_IS_DEFINED(SAM3X4C) ||	\
+		SAM_PART_IS_DEFINED(SAM3X4E) \
+		)
+
+#define SAM3X8 ( \
+		SAM_PART_IS_DEFINED(SAM3X8C) ||	\
+		SAM_PART_IS_DEFINED(SAM3X8E) ||	\
+		SAM_PART_IS_DEFINED(SAM3X8H) \
+		)
+/** @} */
+
+/**
+ * \name SAM3A series
+ * @{
+ */
+#define SAM3A4 ( \
+		SAM_PART_IS_DEFINED(SAM3A4C) \
+		)
+
+#define SAM3A8 ( \
+		SAM_PART_IS_DEFINED(SAM3A8C) \
+		)
+/** @} */
+
+/**
+ * \name SAM4S series
+ * @{
+ */
+#define SAM4S2 ( \
+		SAM_PART_IS_DEFINED(SAM4S2A) || \
+ 		SAM_PART_IS_DEFINED(SAM4S2B) || \
+ 		SAM_PART_IS_DEFINED(SAM4S2C) \
+ 		)
+
+#define SAM4S4 ( \
+		SAM_PART_IS_DEFINED(SAM4S4A) || \
+ 		SAM_PART_IS_DEFINED(SAM4S4B) || \
+ 		SAM_PART_IS_DEFINED(SAM4S4C) \
+ 		)
+
+#define SAM4S8 ( \
+		SAM_PART_IS_DEFINED(SAM4S8B) ||	\
+		SAM_PART_IS_DEFINED(SAM4S8C) \
+		)
+
+#define SAM4S16 ( \
+		SAM_PART_IS_DEFINED(SAM4S16B) || \
+		SAM_PART_IS_DEFINED(SAM4S16C) \
+		)
+
+#define SAM4SA16 ( \
+		SAM_PART_IS_DEFINED(SAM4SA16B) || \
+		SAM_PART_IS_DEFINED(SAM4SA16C)    \
+	)
+
+#define SAM4SD16 ( \
+		SAM_PART_IS_DEFINED(SAM4SD16B) || \
+		SAM_PART_IS_DEFINED(SAM4SD16C)    \
+	)
+
+#define SAM4SD32 ( \
+		SAM_PART_IS_DEFINED(SAM4SD32B) || \
+		SAM_PART_IS_DEFINED(SAM4SD32C)    \
+	)
+/** @} */
+
+/**
+ * \name SAM4L series
+ * @{
+ */
+#define SAM4LS ( \
+		SAM_PART_IS_DEFINED(SAM4LS2A) || \
+		SAM_PART_IS_DEFINED(SAM4LS2B) || \
+		SAM_PART_IS_DEFINED(SAM4LS2C) || \
+		SAM_PART_IS_DEFINED(SAM4LS4A) || \
+		SAM_PART_IS_DEFINED(SAM4LS4B) || \
+		SAM_PART_IS_DEFINED(SAM4LS4C) || \
+		SAM_PART_IS_DEFINED(SAM4LS8A) || \
+		SAM_PART_IS_DEFINED(SAM4LS8B) || \
+		SAM_PART_IS_DEFINED(SAM4LS8C)    \
+		)
+
+#define SAM4LC ( \
+		SAM_PART_IS_DEFINED(SAM4LC2A) || \
+		SAM_PART_IS_DEFINED(SAM4LC2B) || \
+		SAM_PART_IS_DEFINED(SAM4LC2C) || \
+		SAM_PART_IS_DEFINED(SAM4LC4A) || \
+		SAM_PART_IS_DEFINED(SAM4LC4B) || \
+		SAM_PART_IS_DEFINED(SAM4LC4C) || \
+		SAM_PART_IS_DEFINED(SAM4LC8A) || \
+		SAM_PART_IS_DEFINED(SAM4LC8B) || \
+		SAM_PART_IS_DEFINED(SAM4LC8C)    \
+		)
+/** @} */
+
+/**
+ * \name SAMD20 series
+ * @{
+ */
+#define SAMD20J ( \
+		SAM_PART_IS_DEFINED(SAMD20J14) || \
+		SAM_PART_IS_DEFINED(SAMD20J15) || \
+		SAM_PART_IS_DEFINED(SAMD20J16) || \
+		SAM_PART_IS_DEFINED(SAMD20J17) || \
+		SAM_PART_IS_DEFINED(SAMD20J18) \
+	)
+
+#define SAMD20G ( \
+		SAM_PART_IS_DEFINED(SAMD20G14)  || \
+		SAM_PART_IS_DEFINED(SAMD20G15)  || \
+		SAM_PART_IS_DEFINED(SAMD20G16)  || \
+		SAM_PART_IS_DEFINED(SAMD20G17)  || \
+		SAM_PART_IS_DEFINED(SAMD20G17U) || \
+		SAM_PART_IS_DEFINED(SAMD20G18)  || \
+		SAM_PART_IS_DEFINED(SAMD20G18U) \
+	)
+
+#define SAMD20E ( \
+		SAM_PART_IS_DEFINED(SAMD20E14) || \
+		SAM_PART_IS_DEFINED(SAMD20E15) || \
+		SAM_PART_IS_DEFINED(SAMD20E16) || \
+		SAM_PART_IS_DEFINED(SAMD20E17) || \
+		SAM_PART_IS_DEFINED(SAMD20E18) \
+	)
+/** @} */
+
+/**
+ * \name SAMD21 series
+ * @{
+ */
+#define SAMD21J ( \
+		SAM_PART_IS_DEFINED(SAMD21J15A) || \
+		SAM_PART_IS_DEFINED(SAMD21J16A) || \
+		SAM_PART_IS_DEFINED(SAMD21J17A) || \
+		SAM_PART_IS_DEFINED(SAMD21J18A) || \
+		SAM_PART_IS_DEFINED(SAMD21J15B) || \
+		SAM_PART_IS_DEFINED(SAMD21J16B) \
+	)
+
+#define SAMD21G ( \
+		SAM_PART_IS_DEFINED(SAMD21G15A) || \
+		SAM_PART_IS_DEFINED(SAMD21G16A) || \
+		SAM_PART_IS_DEFINED(SAMD21G17A) || \
+		SAM_PART_IS_DEFINED(SAMD21G17AU) || \
+		SAM_PART_IS_DEFINED(SAMD21G18A) || \
+		SAM_PART_IS_DEFINED(SAMD21G18AU) || \
+		SAM_PART_IS_DEFINED(SAMD21G15B) || \
+		SAM_PART_IS_DEFINED(SAMD21G16B) || \
+		SAM_PART_IS_DEFINED(SAMD21G15L) || \
+		SAM_PART_IS_DEFINED(SAMD21G16L) \
+	)
+
+#define SAMD21GXXL ( \
+		SAM_PART_IS_DEFINED(SAMD21G15L) || \
+		SAM_PART_IS_DEFINED(SAMD21G16L) \
+		)
+
+#define SAMD21E ( \
+		SAM_PART_IS_DEFINED(SAMD21E15A) || \
+		SAM_PART_IS_DEFINED(SAMD21E16A) || \
+		SAM_PART_IS_DEFINED(SAMD21E17A) || \
+		SAM_PART_IS_DEFINED(SAMD21E18A) || \
+		SAM_PART_IS_DEFINED(SAMD21E15B) || \
+		SAM_PART_IS_DEFINED(SAMD21E15BU) || \
+		SAM_PART_IS_DEFINED(SAMD21E16B) || \
+		SAM_PART_IS_DEFINED(SAMD21E16BU) || \
+		SAM_PART_IS_DEFINED(SAMD21E15L) || \
+		SAM_PART_IS_DEFINED(SAMD21E16L) \
+	)
+
+#define SAMD21EXXL ( \
+		SAM_PART_IS_DEFINED(SAMD21E15L) || \
+		SAM_PART_IS_DEFINED(SAMD21E16L) \
+		)
+
+/** @} */
+
+/**
+ * \name SAMR21 series
+ * @{
+ */
+#define SAMR21G ( \
+		SAM_PART_IS_DEFINED(SAMR21G16A) || \
+		SAM_PART_IS_DEFINED(SAMR21G17A) || \
+		SAM_PART_IS_DEFINED(SAMR21G18A) \
+	)
+
+#define SAMR21E ( \
+		SAM_PART_IS_DEFINED(SAMR21E16A) || \
+		SAM_PART_IS_DEFINED(SAMR21E17A) || \
+		SAM_PART_IS_DEFINED(SAMR21E18A) || \
+		SAM_PART_IS_DEFINED(SAMR21E19A) \
+	)
+/** @} */
+
+/**
+ * \name SAMR30 series
+ * @{
+ */
+#define SAMR30G ( \
+		SAM_PART_IS_DEFINED(SAMR30G18A) \
+	)
+
+#define SAMR30E ( \
+		SAM_PART_IS_DEFINED(SAMR30E18A) \
+	)
+/** @} */
+
+/**
+ * \name SAMB11 series
+ * @{
+ */
+#define SAMB11G ( \
+		SAM_PART_IS_DEFINED(SAMB11G18A) || \
+		SAM_PART_IS_DEFINED(SAMB11ZR) \
+	)
+#define BTLC1000 ( \
+		SAM_PART_IS_DEFINED(BTLC1000WLCSP) \
+	)
+
+/** @} */
+
+/**
+ * \name SAMD09 series
+ * @{
+ */
+#define SAMD09C ( \
+		SAM_PART_IS_DEFINED(SAMD09C13A) \
+	)
+
+#define SAMD09D ( \
+		SAM_PART_IS_DEFINED(SAMD09D14A) \
+	)
+/** @} */
+
+/**
+ * \name SAMD10 series
+ * @{
+ */
+#define SAMD10C ( \
+		SAM_PART_IS_DEFINED(SAMD10C12A) || \
+		SAM_PART_IS_DEFINED(SAMD10C13A) || \
+		SAM_PART_IS_DEFINED(SAMD10C14A) \
+	)
+
+#define SAMD10DS ( \
+		SAM_PART_IS_DEFINED(SAMD10D12AS) || \
+		SAM_PART_IS_DEFINED(SAMD10D13AS) || \
+		SAM_PART_IS_DEFINED(SAMD10D14AS) \
+	)
+
+#define SAMD10DM ( \
+		SAM_PART_IS_DEFINED(SAMD10D12AM) || \
+		SAM_PART_IS_DEFINED(SAMD10D13AM) || \
+		SAM_PART_IS_DEFINED(SAMD10D14AM) \
+	)
+
+#define SAMD10DU ( \
+		SAM_PART_IS_DEFINED(SAMD10D14AU) \
+	)
+/** @} */
+
+/**
+ * \name SAMD11 series
+ * @{
+ */
+#define SAMD11C ( \
+		SAM_PART_IS_DEFINED(SAMD11C14A) \
+	)
+
+#define SAMD11DS ( \
+		SAM_PART_IS_DEFINED(SAMD11D14AS) \
+	)
+
+#define SAMD11DM ( \
+		SAM_PART_IS_DEFINED(SAMD11D14AM) \
+	)
+
+#define SAMD11DU ( \
+		SAM_PART_IS_DEFINED(SAMD11D14AU) \
+	)
+/** @} */
+
+/**
+ * \name SAML21 series
+ * @{
+ */
+#define SAML21E ( \
+		SAM_PART_IS_DEFINED(SAML21E18A) || \
+		SAM_PART_IS_DEFINED(SAML21E15B) || \
+		SAM_PART_IS_DEFINED(SAML21E16B) || \
+		SAM_PART_IS_DEFINED(SAML21E17B) || \
+		SAM_PART_IS_DEFINED(SAML21E18B) \
+	)
+
+#define SAML21G ( \
+		SAM_PART_IS_DEFINED(SAML21G18A) || \
+		SAM_PART_IS_DEFINED(SAML21G16B) || \
+		SAM_PART_IS_DEFINED(SAML21G17B) || \
+		SAM_PART_IS_DEFINED(SAML21G18B) \
+	)
+
+#define SAML21J ( \
+		SAM_PART_IS_DEFINED(SAML21J18A) || \
+		SAM_PART_IS_DEFINED(SAML21J16B) || \
+		SAM_PART_IS_DEFINED(SAML21J17B) || \
+		SAM_PART_IS_DEFINED(SAML21J18B) \
+	)
+
+/* Group for SAML21 A variant: SAML21[E/G/J][18]A */
+#define SAML21XXXA ( \
+		SAM_PART_IS_DEFINED(SAML21E18A) || \
+		SAM_PART_IS_DEFINED(SAML21G18A) || \
+		SAM_PART_IS_DEFINED(SAML21J18A) \
+	)
+
+/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */
+#define SAML21XXXB ( \
+		SAM_PART_IS_DEFINED(SAML21E15B) || \
+		SAM_PART_IS_DEFINED(SAML21E16B) || \
+		SAM_PART_IS_DEFINED(SAML21E17B) || \
+		SAM_PART_IS_DEFINED(SAML21E18B) || \
+		SAM_PART_IS_DEFINED(SAML21G16B) || \
+		SAM_PART_IS_DEFINED(SAML21G17B) || \
+		SAM_PART_IS_DEFINED(SAML21G18B) || \
+		SAM_PART_IS_DEFINED(SAML21J16B) || \
+		SAM_PART_IS_DEFINED(SAML21J17B) || \
+		SAM_PART_IS_DEFINED(SAML21J18B) \
+	)
+
+/** @} */
+
+/**
+ * \name SAML22 series
+ * @{
+ */
+#define SAML22N ( \
+		SAM_PART_IS_DEFINED(SAML22N16A) || \
+		SAM_PART_IS_DEFINED(SAML22N17A) || \
+		SAM_PART_IS_DEFINED(SAML22N18A) \
+	)
+
+#define SAML22G ( \
+		SAM_PART_IS_DEFINED(SAML22G16A) || \
+		SAM_PART_IS_DEFINED(SAML22G17A) || \
+		SAM_PART_IS_DEFINED(SAML22G18A) \
+	)
+
+#define SAML22J ( \
+		SAM_PART_IS_DEFINED(SAML22J16A) || \
+		SAM_PART_IS_DEFINED(SAML22J17A) || \
+		SAM_PART_IS_DEFINED(SAML22J18A) \
+	)
+/** @} */
+
+/**
+ * \name SAMDA1 series
+ * @{
+ */
+#define SAMDA1J ( \
+		SAM_PART_IS_DEFINED(SAMDA1J14A) || \
+		SAM_PART_IS_DEFINED(SAMDA1J15B) || \
+		SAM_PART_IS_DEFINED(SAMDA1J15A) || \
+		SAM_PART_IS_DEFINED(SAMDA1J15B) || \
+		SAM_PART_IS_DEFINED(SAMDA1J16A) || \
+		SAM_PART_IS_DEFINED(SAMDA1J16B) \
+	)
+
+#define SAMDA1G ( \
+		SAM_PART_IS_DEFINED(SAMDA1G14A) || \
+		SAM_PART_IS_DEFINED(SAMDA1G14B) || \
+		SAM_PART_IS_DEFINED(SAMDA1G15A) || \
+		SAM_PART_IS_DEFINED(SAMDA1G15B) || \
+		SAM_PART_IS_DEFINED(SAMDA1G16A) || \
+		SAM_PART_IS_DEFINED(SAMDA1G16B) \
+	)
+
+#define SAMDA1E ( \
+		SAM_PART_IS_DEFINED(SAMDA1E14A) || \
+		SAM_PART_IS_DEFINED(SAMDA1E14B) || \
+		SAM_PART_IS_DEFINED(SAMDA1E15A) || \
+		SAM_PART_IS_DEFINED(SAMDA1E15B) || \
+		SAM_PART_IS_DEFINED(SAMDA1E16A) || \
+		SAM_PART_IS_DEFINED(SAMDA1E16B) \
+	)
+/** @} */
+
+/**
+ * \name SAMHA1 series
+ * @{
+ */
+#define SAMHA1G ( \
+		SAM_PART_IS_DEFINED(SAMHA1G14A) || \
+		SAM_PART_IS_DEFINED(SAMHA1G15A) || \
+		SAM_PART_IS_DEFINED(SAMHA1G16A) \
+	)
+
+/** @} */
+
+/**
+ * \name SAMC20 series
+ * @{
+ */
+#define SAMC20E ( \
+		SAM_PART_IS_DEFINED(SAMC20E15A) || \
+		SAM_PART_IS_DEFINED(SAMC20E16A) || \
+		SAM_PART_IS_DEFINED(SAMC20E17A) || \
+		SAM_PART_IS_DEFINED(SAMC20E18A) \
+	)
+
+#define SAMC20G ( \
+		SAM_PART_IS_DEFINED(SAMC20G15A) || \
+		SAM_PART_IS_DEFINED(SAMC20G16A) || \
+		SAM_PART_IS_DEFINED(SAMC20G17A) || \
+		SAM_PART_IS_DEFINED(SAMC20G18A) \
+	)
+
+#define SAMC20J ( \
+		SAM_PART_IS_DEFINED(SAMC20J15A) || \
+		SAM_PART_IS_DEFINED(SAMC20J16A) || \
+		SAM_PART_IS_DEFINED(SAMC20J17A) || \
+		SAM_PART_IS_DEFINED(SAMC20J18A) \
+	)
+/** @} */
+
+/**
+ * \name SAMC21 series
+ * @{
+ */
+#define SAMC21E ( \
+		SAM_PART_IS_DEFINED(SAMC21E15A) || \
+		SAM_PART_IS_DEFINED(SAMC21E16A) || \
+		SAM_PART_IS_DEFINED(SAMC21E17A) || \
+		SAM_PART_IS_DEFINED(SAMC21E18A) \
+	)
+
+#define SAMC21G ( \
+		SAM_PART_IS_DEFINED(SAMC21G15A) || \
+		SAM_PART_IS_DEFINED(SAMC21G16A) || \
+		SAM_PART_IS_DEFINED(SAMC21G17A) || \
+		SAM_PART_IS_DEFINED(SAMC21G18A) \
+	)
+
+#define SAMC21J ( \
+		SAM_PART_IS_DEFINED(SAMC21J15A) || \
+		SAM_PART_IS_DEFINED(SAMC21J16A) || \
+		SAM_PART_IS_DEFINED(SAMC21J17A) || \
+		SAM_PART_IS_DEFINED(SAMC21J18A) \
+	)
+/** @} */
+
+/**
+ * \name SAM4E series
+ * @{
+ */
+#define SAM4E8 ( \
+		SAM_PART_IS_DEFINED(SAM4E8C) || \
+		SAM_PART_IS_DEFINED(SAM4E8CB) || \
+		SAM_PART_IS_DEFINED(SAM4E8E) \
+		)
+
+#define SAM4E16 ( \
+		SAM_PART_IS_DEFINED(SAM4E16C) || \
+		SAM_PART_IS_DEFINED(SAM4E16CB) || \
+		SAM_PART_IS_DEFINED(SAM4E16E) \
+		)
+/** @} */
+
+/**
+ * \name SAM4N series
+ * @{
+ */
+#define SAM4N8 ( \
+		SAM_PART_IS_DEFINED(SAM4N8A) || \
+		SAM_PART_IS_DEFINED(SAM4N8B) || \
+		SAM_PART_IS_DEFINED(SAM4N8C) \
+		)
+
+#define SAM4N16 ( \
+		SAM_PART_IS_DEFINED(SAM4N16B) || \
+		SAM_PART_IS_DEFINED(SAM4N16C) \
+		)
+/** @} */
+
+/**
+ * \name SAM4C series
+ * @{
+ */
+#define SAM4C4_0 ( \
+		SAM_PART_IS_DEFINED(SAM4C4C_0) \
+		)
+
+#define SAM4C4_1 ( \
+		SAM_PART_IS_DEFINED(SAM4C4C_1) \
+		)
+
+#define SAM4C4 (SAM4C4_0 || SAM4C4_1)
+
+#define SAM4C8_0 ( \
+		SAM_PART_IS_DEFINED(SAM4C8C_0) \
+		)
+
+#define SAM4C8_1 ( \
+		SAM_PART_IS_DEFINED(SAM4C8C_1) \
+		)
+
+#define SAM4C8 (SAM4C8_0 || SAM4C8_1)
+
+#define SAM4C16_0 ( \
+		SAM_PART_IS_DEFINED(SAM4C16C_0) \
+		)
+
+#define SAM4C16_1 ( \
+		SAM_PART_IS_DEFINED(SAM4C16C_1) \
+		)
+
+#define SAM4C16 (SAM4C16_0 || SAM4C16_1)
+
+#define SAM4C32_0 ( \
+		SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
+		SAM_PART_IS_DEFINED(SAM4C32E_0) \
+		)
+
+#define SAM4C32_1 ( \
+		SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
+		SAM_PART_IS_DEFINED(SAM4C32E_1) \
+		)
+
+
+#define SAM4C32 (SAM4C32_0 || SAM4C32_1)
+
+/** @} */
+
+/**
+ * \name SAM4CM series
+ * @{
+ */
+#define SAM4CMP8_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
+		)
+
+#define SAM4CMP8_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
+		)
+
+#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1)
+
+#define SAM4CMP16_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
+		)
+
+#define SAM4CMP16_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
+		)
+
+#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1)
+
+#define SAM4CMP32_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
+		)
+
+#define SAM4CMP32_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
+		)
+
+#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1)
+
+#define SAM4CMS4_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS4C_0) \
+		)
+
+#define SAM4CMS4_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS4C_1) \
+		)
+
+#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1)
+
+#define SAM4CMS8_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
+		)
+
+#define SAM4CMS8_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
+		)
+
+#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1)
+
+#define SAM4CMS16_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
+		)
+
+#define SAM4CMS16_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
+		)
+
+#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1)
+
+#define SAM4CMS32_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
+		)
+
+#define SAM4CMS32_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
+		)
+
+#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1)
+
+/** @} */
+
+/**
+ * \name SAM4CP series
+ * @{
+ */
+#define SAM4CP16_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CP16B_0) \
+		)
+
+#define SAM4CP16_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CP16B_1) \
+		)
+
+#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1)
+/** @} */
+
+/**
+ * \name SAMG series
+ * @{
+ */
+#define SAMG51 ( \
+		SAM_PART_IS_DEFINED(SAMG51G18) \
+		)
+
+#define SAMG53 ( \
+		SAM_PART_IS_DEFINED(SAMG53G19) ||\
+		SAM_PART_IS_DEFINED(SAMG53N19) \
+		)
+
+#define SAMG54 ( \
+		SAM_PART_IS_DEFINED(SAMG54G19) ||\
+		SAM_PART_IS_DEFINED(SAMG54J19) ||\
+		SAM_PART_IS_DEFINED(SAMG54N19) \
+		)
+
+#define SAMG55 ( \
+		SAM_PART_IS_DEFINED(SAMG55G18) ||\
+		SAM_PART_IS_DEFINED(SAMG55G19) ||\
+		SAM_PART_IS_DEFINED(SAMG55J18) ||\
+		SAM_PART_IS_DEFINED(SAMG55J19) ||\
+		SAM_PART_IS_DEFINED(SAMG55N19) \
+		)
+/** @} */
+
+/**
+ * \name SAMV71 series
+ * @{
+ */
+#define SAMV71J ( \
+		SAM_PART_IS_DEFINED(SAMV71J19) || \
+		SAM_PART_IS_DEFINED(SAMV71J20) || \
+		SAM_PART_IS_DEFINED(SAMV71J21) \
+	)
+
+#define SAMV71N ( \
+		SAM_PART_IS_DEFINED(SAMV71N19) || \
+		SAM_PART_IS_DEFINED(SAMV71N20) || \
+		SAM_PART_IS_DEFINED(SAMV71N21) \
+	)
+
+#define SAMV71Q ( \
+		SAM_PART_IS_DEFINED(SAMV71Q19) || \
+		SAM_PART_IS_DEFINED(SAMV71Q20) || \
+		SAM_PART_IS_DEFINED(SAMV71Q21) \
+	)
+/** @} */
+
+/**
+ * \name SAMV70 series
+ * @{
+ */
+#define SAMV70J ( \
+		SAM_PART_IS_DEFINED(SAMV70J19) || \
+		SAM_PART_IS_DEFINED(SAMV70J20) \
+	)
+
+#define SAMV70N ( \
+		SAM_PART_IS_DEFINED(SAMV70N19) || \
+		SAM_PART_IS_DEFINED(SAMV70N20) \
+	)
+
+#define SAMV70Q ( \
+		SAM_PART_IS_DEFINED(SAMV70Q19) || \
+		SAM_PART_IS_DEFINED(SAMV70Q20) \
+	)
+/** @} */
+
+/**
+ * \name SAMS70 series
+ * @{
+ */
+#define SAMS70J ( \
+		SAM_PART_IS_DEFINED(SAMS70J19) || \
+		SAM_PART_IS_DEFINED(SAMS70J20) || \
+		SAM_PART_IS_DEFINED(SAMS70J21) \
+	)
+
+#define SAMS70N ( \
+		SAM_PART_IS_DEFINED(SAMS70N19) || \
+		SAM_PART_IS_DEFINED(SAMS70N20) || \
+		SAM_PART_IS_DEFINED(SAMS70N21) \
+	)
+
+#define SAMS70Q ( \
+		SAM_PART_IS_DEFINED(SAMS70Q19) || \
+		SAM_PART_IS_DEFINED(SAMS70Q20) || \
+		SAM_PART_IS_DEFINED(SAMS70Q21) \
+	)
+/** @} */
+
+/**
+ * \name SAME70 series
+ * @{
+ */
+#define SAME70J ( \
+		SAM_PART_IS_DEFINED(SAME70J19) || \
+		SAM_PART_IS_DEFINED(SAME70J20) || \
+		SAM_PART_IS_DEFINED(SAME70J21) \
+	)
+
+#define SAME70N ( \
+		SAM_PART_IS_DEFINED(SAME70N19) || \
+		SAM_PART_IS_DEFINED(SAME70N20) || \
+		SAM_PART_IS_DEFINED(SAME70N21) \
+	)
+
+#define SAME70Q ( \
+		SAM_PART_IS_DEFINED(SAME70Q19) || \
+		SAM_PART_IS_DEFINED(SAME70Q20) || \
+		SAM_PART_IS_DEFINED(SAME70Q21) \
+	)
+/** @} */
+
+/**
+ * \name SAM families
+ * @{
+ */
+/** SAM3S Family */
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)
+
+/** SAM3U Family */
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)
+
+/** SAM3N Family */
+#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4)
+
+/** SAM3XA Family */
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)
+
+/** SAM4S Family */
+#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)
+
+/** SAM4L Family */
+#define SAM4L (SAM4LS || SAM4LC)
+
+/** SAMD20 Family */
+#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)
+
+/** SAMD21 Family */
+#define SAMD21 (SAMD21J || SAMD21G || SAMD21E)
+
+/** SAMD09 Family */
+#define SAMD09 (SAMD09C || SAMD09D)
+
+/** SAMD10 Family */
+#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU)
+
+/** SAMD11 Family */
+#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU)
+
+/** SAMDA1 Family */
+#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E)
+
+/** SAMHA1 Family */
+#define SAMHA1 (SAMHA1G)
+
+/** SAMD Family */
+#define SAMD   (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1)
+
+/** SAMR21 Family */
+#define SAMR21 (SAMR21G || SAMR21E)
+
+/** SAMR30 Family */
+#define SAMR30 (SAMR30G || SAMR30E)
+
+/** SAMB11 Family */
+#define SAMB11 (SAMB11G || BTLC1000)
+
+/** SAML21 Family */
+#define SAML21 (SAML21J || SAML21G || SAML21E)
+
+/** SAML22 Family */
+#define SAML22 (SAML22J || SAML22G || SAML22N)
+/** SAMC20 Family */
+#define SAMC20 (SAMC20J || SAMC20G || SAMC20E)
+
+/** SAMC21 Family */
+#define SAMC21 (SAMC21J || SAMC21G || SAMC21E)
+
+/** SAM4E Family */
+#define SAM4E (SAM4E8 || SAM4E16)
+
+/** SAM4N Family */
+#define SAM4N (SAM4N8 || SAM4N16)
+
+/** SAM4C Family */
+#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0)
+#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1)
+#define SAM4C   (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32)
+
+/** SAM4CM Family */
+#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \
+			SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0)
+#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \
+			SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1)
+#define SAM4CM   (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \
+			SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32)
+
+/** SAM4CP Family */
+#define SAM4CP_0 (SAM4CP16_0)
+#define SAM4CP_1 (SAM4CP16_1)
+#define SAM4CP   (SAM4CP16)
+
+/** SAMG Family */
+#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55)
+
+/** SAMB Family */
+#define SAMB (SAMB11)
+
+/** SAMV71 Family */
+#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q)
+
+/** SAMV70 Family */
+#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q)
+
+/** SAME70 Family */
+#define SAME70 (SAME70J || SAME70N || SAME70Q)
+
+/** SAMS70 Family */
+#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q)
+
+/** SAM0 product line (cortex-m0+) */
+#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\
+		SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1)
+
+/** @} */
+
+/** SAM product line */
+#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \
+		SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70)
+
+/** @} */
+
+/** @} */
+
+/** @} */
+
+#endif /* ATMEL_PARTS_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/read.c b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/read.c
new file mode 100644
index 0000000000..1326308be5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/read.c
@@ -0,0 +1,167 @@
+/**
+ * \file
+ *
+ * \brief System-specific implementation of the \ref _read function used by
+ *         the standard library.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "compiler.h"
+
+/**
+ * \defgroup group_common_utils_stdio Standard I/O (stdio)
+ *
+ * Common standard I/O driver that implements the stdio
+ * read and write functions on AVR and SAM devices.
+ *
+ * \{
+ */
+
+extern volatile void *volatile stdio_base;
+void (*ptr_get)(void volatile*, char*);
+
+
+// IAR common implementation
+#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__) )
+
+#include <yfuns.h>
+
+_STD_BEGIN
+
+#pragma module_name = "?__read"
+
+/*! \brief Reads a number of bytes, at most \a size, into the memory area
+ *         pointed to by \a buffer.
+ *
+ * \param handle File handle to read from.
+ * \param buffer Pointer to buffer to write read bytes to.
+ * \param size Number of bytes to read.
+ *
+ * \return The number of bytes read, \c 0 at the end of the file, or
+ *         \c _LLIO_ERROR on failure.
+ */
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+	int nChars = 0;
+	// This implementation only reads from stdin.
+	// For all other file handles, it returns failure.
+	if (handle != _LLIO_STDIN) {
+		return _LLIO_ERROR;
+	}
+	for (; size > 0; --size) {
+		ptr_get(stdio_base, (char*)buffer);
+		buffer++;
+		nChars++;
+	}
+	return nChars;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+int __close(int handle)
+{
+	UNUSED(handle);
+	return 0;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+int remove(const char* val)
+{
+	UNUSED(val);
+	return 0;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+long __lseek(int handle, long val, int val2)
+{
+	UNUSED(handle);
+	UNUSED(val2);
+	return val;
+}
+
+_STD_END
+
+// GCC AVR32 and SAM implementation
+#elif (defined(__GNUC__) && !XMEGA && !MEGA) 
+
+int __attribute__((weak))
+_read (int file, char * ptr, int len); // Remove GCC compiler warning
+
+int __attribute__((weak))
+_read (int file, char * ptr, int len)
+{
+	int nChars = 0;
+
+	if (file != 0) {
+		return -1;
+	}
+
+	for (; len > 0; --len) {
+		ptr_get(stdio_base, ptr);
+		ptr++;
+		nChars++;
+	}
+	return nChars;
+}
+
+// GCC AVR implementation
+#elif (defined(__GNUC__) && (XMEGA || MEGA) )
+
+int _read (int *f); // Remove GCC compiler warning
+
+int _read (int *f)
+{
+	char c;
+	ptr_get(stdio_base,&c);
+	return c;
+}
+#endif
+
+/**
+ * \}
+ */
+
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_serial/stdio_serial.h b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_serial/stdio_serial.h
new file mode 100644
index 0000000000..4315d3fcdc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_serial/stdio_serial.h
@@ -0,0 +1,129 @@
+/**
+ *
+ * \file
+ *
+ * \brief Common Standard I/O Serial Management.
+ *
+ * This file defines a useful set of functions for the Stdio Serial interface on AVR
+ * and SAM devices.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef _STDIO_SERIAL_H_
+#define _STDIO_SERIAL_H_
+
+/**
+ * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio)
+ * \ingroup group_common_utils_stdio
+ *
+ * Common standard serial I/O management driver that
+ * implements a stdio serial interface on AVR and SAM devices.
+ *
+ * \{
+ */
+
+#include <stdio.h>
+#include "compiler.h"
+#ifndef SAMD20
+# include "sysclk.h"
+#endif
+#include "serial.h"
+
+#if (XMEGA || MEGA_RF) && defined(__GNUC__)
+	extern int _write (char c, int *f);
+	extern int _read (int *f);
+#endif
+
+
+//! Pointer to the base of the USART module instance to use for stdio.
+extern volatile void *volatile stdio_base;
+//! Pointer to the external low level write function.
+extern int (*ptr_put)(void volatile*, char);
+
+//! Pointer to the external low level read function.
+extern void (*ptr_get)(void volatile*, char*);
+
+/*! \brief Initializes the stdio in Serial Mode.
+ *
+ * \param usart       Base address of the USART instance.
+ * \param opt         Options needed to set up RS232 communication (see \ref usart_options_t).
+ *
+ */
+static inline void stdio_serial_init(volatile void *usart, const usart_serial_options_t *opt)
+{
+	stdio_base = (void *)usart;
+	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+# if (XMEGA || MEGA_RF)
+	usart_serial_init((USART_t *)usart,opt);
+# elif UC3
+	usart_serial_init(usart,(usart_serial_options_t *)opt);
+# elif SAM
+	usart_serial_init((Usart *)usart,(usart_serial_options_t *)opt);
+# else
+#  error Unsupported chip type
+# endif
+
+# if defined(__GNUC__)
+#  if (XMEGA || MEGA_RF)
+	// For AVR GCC libc print redirection uses fdevopen.
+	fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read));
+#  endif
+#  if UC3 || SAM
+	// For AVR32 and SAM GCC
+	// Specify that stdout and stdin should not be buffered.
+	setbuf(stdout, NULL);
+	setbuf(stdin, NULL);
+	// Note: Already the case in IAR's Normal DLIB default configuration
+	// and AVR GCC library:
+	// - printf() emits one character at a time.
+	// - getchar() requests only 1 byte to exit.
+#  endif
+# endif
+}
+
+/**
+ * \}
+ */
+
+#endif  // _STDIO_SERIAL_H_
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.c b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.c
new file mode 100644
index 0000000000..7eaa962f07
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.c
@@ -0,0 +1,121 @@
+/**
+ * \file
+ *
+ * \brief USB CDC Standard I/O Serial Management.
+ *
+ * This module defines support routines for a stdio serial interface to the
+ * Atmel Software Framework (ASF) common USB CDC service.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#include "stdio_usb.h"
+
+static bool stdio_usb_interface_enable = false;
+
+int stdio_usb_putchar (volatile void * unused, char data)
+{
+	/* A negative return value should be used to indicate that data
+	 * was not written, but this doesn't seem to work with GCC libc.
+	 */
+	if (!stdio_usb_interface_enable) {
+		return 0;  // -1
+	}
+
+	return udi_cdc_putc(data) ? 0 : -1;
+}
+
+void stdio_usb_getchar (void volatile * unused, char *data)
+{
+	/* A negative return value should be used to indicate that data
+	 * was not read, but this doesn't seem to work with GCC libc.
+	 */
+	if (!stdio_usb_interface_enable) {
+		*data = 0;  // -1
+		return;
+	}
+
+	*data = (char)udi_cdc_getc();
+}
+
+bool stdio_usb_enable(void)
+{
+	stdio_usb_interface_enable = true;
+	return true;
+}
+
+void stdio_usb_disable(void)
+{
+	stdio_usb_interface_enable = false;
+}
+
+void stdio_usb_init(void)
+{
+	stdio_base = NULL;
+	ptr_put = stdio_usb_putchar;
+	ptr_get = stdio_usb_getchar;
+
+	/*
+	 * Start and attach USB CDC device interface for devices with
+	 * integrated USB interfaces.  Assume the VBUS is present if
+	 * VBUS monitoring is not available.
+	 */
+	udc_start ();
+
+#if defined(__GNUC__)
+# if XMEGA
+	// For AVR GCC libc print redirection uses fdevopen.
+	fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read));
+# endif
+# if UC3 || SAM
+	// For AVR32 and SAM GCC
+	// Specify that stdout and stdin should not be buffered.
+	setbuf(stdout, NULL);
+	setbuf(stdin, NULL);
+	// Note: Already the case in IAR's Normal DLIB default configuration
+	// and AVR GCC library:
+	// - printf() emits one character at a time.
+	// - getchar() requests only 1 byte to exit.
+# endif
+#endif
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.h b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.h
new file mode 100644
index 0000000000..4d0084f167
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.h
@@ -0,0 +1,123 @@
+/**
+ * \file
+ *
+ * \brief USB Standard I/O Serial Management.
+ *
+ * This file defines a useful set of functions for the Stdio Serial
+ * interface on AVR devices.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _stdio_usb_h_
+#define _stdio_usb_h_
+
+/**
+ * \defgroup group_common_utils_stdio_stdio_usb USB/CDC Standard I/O (stdio)
+ * \ingroup group_common_utils_stdio
+ *
+ * Standard I/O (stdio) management component that implements a stdio
+ * USB CDC interface on AVR devices.
+ *
+ * \{
+ */
+
+#include <compiler.h>
+
+#include <stdio.h>
+
+#include <udc.h>
+#include <udi_cdc.h>
+
+extern int _write (char c, int *f);
+extern int _read (int *f);
+
+
+//! Pointer to the base of the USART module instance to use for stdio.
+extern volatile void *volatile stdio_base;
+//! Pointer to the external low level write function.
+extern int (*ptr_put)(void volatile*, char);
+//! Pointer to the external low level read function.
+extern void (*ptr_get)(void volatile*, char*);
+
+/*! \brief Sends a character with the USART.
+ *
+ * \param usart   Base address of the USART instance.
+ * \param data    Character to write.
+ *
+ * \return Status.
+ *   \retval  0  The character was written.
+ *   \retval -1  The function timed out before the transmitter became ready.
+ */
+int stdio_usb_putchar (volatile void * usart, char data);
+
+/*! \brief Waits until a character is received, and returns it.
+ *
+ * \param usart   Base address of the USART instance.
+ * \param data    Data to read
+ *
+ * \return Nothing.
+ */
+void stdio_usb_getchar (void volatile * usart, char * data);
+
+/*! \brief Enables the stdio in USB Serial Mode.
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+bool stdio_usb_enable(void);
+
+/*! \brief Disables the stdio in USB Serial Mode.
+ *
+ * \return Nothing.
+ */
+void stdio_usb_disable(void);
+
+/*! \brief Initializes the stdio in USB Serial Mode.
+ *
+ * \return Nothing.
+ */
+void stdio_usb_init(void);
+
+/**
+ * \}
+ */
+
+#endif  // _stdio_usb_h_
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/write.c b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/write.c
new file mode 100644
index 0000000000..1e8f459437
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/write.c
@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief System-specific implementation of the \ref _write function used by
+ *         the standard library.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "compiler.h"
+
+/**
+ * \addtogroup group_common_utils_stdio
+ *
+ * \{
+ */
+
+volatile void *volatile stdio_base;
+int (*ptr_put)(void volatile*, char);
+
+
+#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__))
+
+#include <yfuns.h>
+
+_STD_BEGIN
+
+#pragma module_name = "?__write"
+
+/*! \brief Writes a number of bytes, at most \a size, from the memory area
+ *         pointed to by \a buffer.
+ *
+ * If \a buffer is zero then \ref __write performs flushing of internal buffers,
+ * if any. In this case, \a handle can be \c -1 to indicate that all handles
+ * should be flushed.
+ *
+ * \param handle File handle to write to.
+ * \param buffer Pointer to buffer to read bytes to write from.
+ * \param size Number of bytes to write.
+ *
+ * \return The number of bytes written, or \c _LLIO_ERROR on failure.
+ */
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+	size_t nChars = 0;
+
+	if (buffer == 0) {
+		// This means that we should flush internal buffers.
+		return 0;
+	}
+
+	// This implementation only writes to stdout and stderr.
+	// For all other file handles, it returns failure.
+	if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) {
+		return _LLIO_ERROR;
+	}
+
+	for (; size != 0; --size) {
+		if (ptr_put(stdio_base, *buffer++) < 0) {
+			return _LLIO_ERROR;
+		}
+		++nChars;
+	}
+	return nChars;
+}
+
+_STD_END
+
+
+#elif (defined(__GNUC__) && !XMEGA && !MEGA)
+
+int __attribute__((weak))
+_write (int file, const char *ptr, int len);
+
+int __attribute__((weak))
+_write (int file, const char *ptr, int len)
+{
+	int nChars = 0;
+
+	if ((file != 1) && (file != 2) && (file!=3)) {
+		return -1;
+	}
+
+	for (; len != 0; --len) {
+		if (ptr_put(stdio_base, *ptr++) < 0) {
+			return -1;
+		}
+		++nChars;
+	}
+	return nChars;
+}
+
+#elif (defined(__GNUC__) && (XMEGA || MEGA))
+
+int _write (char c, int *f);
+
+int _write (char c, int *f)
+{
+	if (ptr_put(stdio_base, c) < 0) {
+		return -1;
+	}
+	return 1;
+}
+#endif
+
+/**
+ * \}
+ */
+
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/delay.h b/bsp/samd21/sam_d2x_asflib/common2/services/delay/delay.h
new file mode 100644
index 0000000000..9326e2b3a1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/delay.h
@@ -0,0 +1,101 @@
+/**
+ * \file
+ *
+ * \brief Common Delay Service
+ *
+ * Copyright (c) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DELAY_H_INCLUDED
+#define DELAY_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup group_common_services_delay Busy-Wait Delay Routines
+ *
+ * This module provides simple loop-based delay routines for those
+ * applications requiring a brief wait during execution. Common for
+ * API ver. 2.
+ *
+ * @{
+ */
+
+#ifdef SYSTICK_MODE
+#include "sam0/systick_counter.h"
+#endif
+#ifdef CYCLE_MODE
+#include "sam0/cycle_counter.h"
+#endif
+
+void delay_init(void);
+
+/**
+ * \def delay_s
+ * \brief Delay in at least specified number of seconds.
+ * \param delay Delay in seconds
+ */
+#define delay_s(delay)          ((delay) ? cpu_delay_s(delay) : cpu_delay_us(1))
+
+/**
+ * \def delay_ms
+ * \brief Delay in at least specified number of milliseconds.
+ * \param delay Delay in milliseconds
+ */
+#define delay_ms(delay)         ((delay) ? cpu_delay_ms(delay) : cpu_delay_us(1))
+
+/**
+ * \def delay_us
+ * \brief Delay in at least specified number of microseconds.
+ * \param delay Delay in microseconds
+ */
+#define delay_us(delay)         ((delay) ? cpu_delay_us(delay) : cpu_delay_us(1))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* DELAY_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.c b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.c
new file mode 100644
index 0000000000..c14090fe19
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.c
@@ -0,0 +1,75 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "delay.h"
+
+/**
+ * \brief Initialize the delay driver.
+ *
+ * Not used in cycle mode.
+ */
+void delay_init(void)
+{
+}
+
+// Delay loop is put to SRAM so that FWS will not affect delay time
+OPTIMIZE_HIGH
+RAMFUNC
+void portable_delay_cycles(unsigned long n)
+{
+	UNUSED(n);
+
+	__asm (
+		"loop: DMB	\n"
+#ifdef __ICCARM__
+		"SUBS r0, r0, #1 \n"
+#else
+		"SUB r0, r0, #1 \n"
+#endif
+		"CMP r0, #0  \n"
+		"BNE loop         "
+	);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.h b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.h
new file mode 100644
index 0000000000..3a52bc574e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.h
@@ -0,0 +1,123 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CYCLE_COUNTER_H_INCLUDED
+#define CYCLE_COUNTER_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @def F_CPU
+ * @brief MCU Clock Frequency (Hertz)
+ */
+#ifndef F_CPU
+#       define F_CPU system_gclk_gen_get_hz(0)
+#endif
+
+/**
+ * @name Convenience functions for busy-wait delay loops
+ *
+ * @def delay_cycles
+ * @brief Delay program execution for a specified number of CPU cycles.
+ * @param n number of CPU cycles to wait
+ *
+ * @def cpu_delay_ms
+ * @brief Delay program execution for a specified number of milliseconds.
+ * @param delay number of milliseconds to wait
+ * @param f_cpu CPU frequency in Hertz
+ *
+ * @def cpu_delay_us
+ * @brief Delay program execution for a specified number of microseconds.
+ * @param delay number of microseconds to wait
+ * @param f_cpu CPU frequency in Hertz
+ *
+ * @def cpu_ms_2_cy
+ * @brief Convert milli-seconds into CPU cycles.
+ * @param ms number of milliseconds
+ * @param f_cpu CPU frequency in Hertz
+ * @return the converted number of CPU cycles
+ *
+ * @def cpu_us_2_cy
+ * @brief Convert micro-seconds into CPU cycles.
+ * @param ms number of microseconds
+ * @param f_cpu CPU frequency in Hertz
+ * @return the converted number of CPU cycles
+ *
+ * @{
+ */
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ *
+ * \note The function runs in internal RAM so that flash wait states
+ *       will not affect the delay time.
+ *
+ * \param n Number of cycles
+ */
+void portable_delay_cycles(unsigned long n);
+
+#define cpu_ms_2_cy(ms, f_cpu)  \
+	(((uint64_t)(ms) * (f_cpu) + (uint64_t)(7e3-1ul)) / (uint64_t)7e3)
+#define cpu_us_2_cy(us, f_cpu)  \
+	(((uint64_t)(us) * (f_cpu) + (uint64_t)(7e6-1ul)) / (uint64_t)7e6)
+
+#define delay_cycles               portable_delay_cycles
+
+#define cpu_delay_s(delay) delay_cycles(cpu_ms_2_cy(1000 * delay, F_CPU))
+#define cpu_delay_ms(delay) delay_cycles(cpu_ms_2_cy(delay, F_CPU))
+#define cpu_delay_us(delay) delay_cycles(cpu_us_2_cy(delay, F_CPU))
+//! @}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CYCLE_COUNTER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.c b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.c
new file mode 100644
index 0000000000..5a007cdba6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.c
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "delay.h"
+
+/**
+ * Value used to calculate ms delay. Default to be used with a 8MHz clock;
+ */
+static uint32_t cycles_per_ms = 8000000UL / 1000;
+static uint32_t cycles_per_us = 8000000UL / 1000000;
+
+/**
+ * \brief Initialize the delay driver.
+ *
+ * This must be called during start up to initialize the delay routine with
+ * the current used main clock. It must run any time the main CPU clock is changed.
+ */
+void delay_init(void)
+{
+	cycles_per_ms = system_gclk_gen_get_hz(0);
+	cycles_per_ms /= 1000;
+	cycles_per_us = cycles_per_ms / 1000;
+
+	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+ * \brief Delay loop to delay at least n number of microseconds
+ *
+ * \param n  Number of microseconds to wait
+ */
+void delay_cycles_us(
+		uint32_t n)
+{
+	while (n--) {
+		/* Devide up to blocks of 10u */
+		delay_cycles(cycles_per_us);
+	}
+}
+
+/**
+ * \brief Delay loop to delay at least n number of milliseconds
+ *
+ * \param n  Number of milliseconds to wait
+ */
+void delay_cycles_ms(
+		uint32_t n)
+{
+	while (n--) {
+		/* Devide up to blocks of 1ms */
+		delay_cycles(cycles_per_ms);
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.h b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.h
new file mode 100644
index 0000000000..06885e63c6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.h
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CYCLE_COUNTER_H_INCLUDED
+#define CYCLE_COUNTER_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Convenience functions for busy-wait delay loops
+ *
+ * @{
+ */
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ * Delay program execution for at least the specified number of CPU cycles.
+ *
+ * \param n  Number of cycles to delay
+ */
+static inline void delay_cycles(
+		const uint32_t n)
+{
+	if (n > 0) {
+		SysTick->LOAD = n;
+		SysTick->VAL = 0;
+
+		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
+		};
+	}
+}
+
+void delay_cycles_us(uint32_t n);
+
+void delay_cycles_ms(uint32_t n);
+
+/**
+ * \brief Delay program execution for at least the specified number of microseconds.
+ *
+ * \param delay  number of microseconds to wait
+ */
+#define cpu_delay_us(delay)      delay_cycles_us(delay)
+
+/**
+ * \brief Delay program execution for at least the specified number of milliseconds.
+ *
+ * \param delay  number of milliseconds to wait
+ */
+#define cpu_delay_ms(delay)      delay_cycles_ms(delay)
+
+/**
+ * \brief Delay program execution for at least the specified number of seconds.
+ *
+ * \param delay  number of seconds to wait
+ */
+#define cpu_delay_s(delay)       delay_cycles_ms(1000 * delay)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CYCLE_COUNTER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono.h
new file mode 100644
index 0000000000..6b04da6e2d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono.h
@@ -0,0 +1,330 @@
+/**
+ * \file
+ *
+ * \brief Monochrome graphic library API header file
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GFX_MONO_H
+#define GFX_MONO_H
+
+#include <stdint.h>
+
+#include "compiler.h"
+
+#ifndef PROGMEM_DECLARE
+#  define PROGMEM_DECLARE(type, name) const type name
+#  define PROGMEM_T const
+#  define PROGMEM_PTR_T const *
+#  define PROGMEM_READ_BYTE(x) *(x)
+#  define PROGMEM_STRING_T const char*
+#endif
+
+/**
+ * \defgroup asfdoc_common2_gfx_mono Monochrome graphical display system
+ *
+ * See \ref asfdoc_common2_gfx_mono_quickstart.
+ *
+ * This library provides an interface to drawing graphics on monochrome
+ * graphical displays
+ *
+ * The graphics drivers consists of the following:
+ * - Display driver interface (gfx_mono.h)
+ * - General graphics drawing primitives (gfx_mono_generic.h)
+ * - Display specific implementation (ex. gfx_mono_ug_2832hsweg04.h)
+ *
+ * The generic drawing primitives is a library of functions for drawing
+ * graphics primitives such as lines, rectangles and circles. It uses other
+ * functions implemented by the display driver for drawing the primitives. The
+ * implementation of these functions can optionally be used by a display
+ * driver, but if the hardware of the display allows faster handling of any of
+ * the primitives, the display driver can implement it directly.
+ *
+ * The display specific drivers provides an interface to the graphical display.
+ * It implements the low level communication with the display hardware, putting
+ * pixels on the display and drawing primitives such as lines, circles and
+ * rectangles. Depending on the display driver implementation, drawing the
+ * graphics primitives might be handled by the generic graphics drawing
+ * primitives rather than the display driver itself.
+ *
+ * \section asfdoc_common2_gfx_mono_examples Examples
+ * The following examples are available for the driver:
+ * - \ref asfdoc_common2_gfx_mono_quickstart
+ * - \ref asfdoc_common2_gfx_mono_sysfont_example
+ * - \ref asfdoc_common2_gfx_mono_spinner_example
+ *
+ * \section asfdoc_common2_gfx_mono_api_overview API Overview
+ *
+ * \note The functions in the library are not interrupt safe.
+ * @{
+ */
+
+typedef uint8_t gfx_mono_color_t;
+typedef uint8_t gfx_coord_t;
+
+/** Pixel operations */
+enum gfx_mono_color {
+	/** Pixel is cleared */
+	GFX_PIXEL_CLR = 0,
+	/** Pixel is set on screen (OR) */
+	GFX_PIXEL_SET = 1,
+	/** Pixel is XORed */
+	GFX_PIXEL_XOR = 2,
+};
+
+/** Bitmap types */
+enum gfx_mono_bitmap_type {
+	/** Bitmap stored in SRAM */
+	GFX_MONO_BITMAP_RAM,
+	/** Bitmap stored in progmem */
+	GFX_MONO_BITMAP_PROGMEM
+};
+
+/* Cannot be moved to top, as they use the bitmap and color enums. */
+#ifdef USE_SDL
+# include "gfx_mono_sdl.h"
+#elif defined(GFX_MONO_C12832_A1Z)
+# include "gfx_mono_c12832_a1z.h"
+#elif defined(GFX_MONO_UG_2832HSWEG04)
+# include "gfx_mono_ug_2832hsweg04.h"
+#else
+/* NULL driver by default */
+# include "gfx_mono_null.h"
+#endif
+#include "gfx_mono_generic.h"
+
+/** \name Circle Sector Definitions */
+/** @{ */
+
+/** Bitmask for drawing circle octant 0. */
+#define GFX_OCTANT0     (1 << 0)
+/** Bitmask for drawing circle octant 1. */
+#define GFX_OCTANT1     (1 << 1)
+/** Bitmask for drawing circle octant 2. */
+#define GFX_OCTANT2     (1 << 2)
+/** Bitmask for drawing circle octant 3. */
+#define GFX_OCTANT3     (1 << 3)
+/** Bitmask for drawing circle octant 4. */
+#define GFX_OCTANT4     (1 << 4)
+/** Bitmask for drawing circle octant 5. */
+#define GFX_OCTANT5     (1 << 5)
+/** Bitmask for drawing circle octant 6. */
+#define GFX_OCTANT6     (1 << 6)
+/** Bitmask for drawing circle octant 7. */
+#define GFX_OCTANT7     (1 << 7)
+
+/** Bitmask for drawing circle quadrant 0. */
+#define GFX_QUADRANT0   (GFX_OCTANT0 | GFX_OCTANT1)
+/** Bitmask for drawing circle quadrant 1. */
+#define GFX_QUADRANT1   (GFX_OCTANT2 | GFX_OCTANT3)
+/** Bitmask for drawing circle quadrant 2. */
+#define GFX_QUADRANT2   (GFX_OCTANT4 | GFX_OCTANT5)
+/** Bitmask for drawing circle quadrant 3. */
+#define GFX_QUADRANT3   (GFX_OCTANT6 | GFX_OCTANT7)
+
+/** Bitmask for drawing left half of circle. */
+#define GFX_LEFTHALF    (GFX_QUADRANT3 | GFX_QUADRANT0)
+/** Bitmask for drawing top half of circle. */
+#define GFX_TOPHALF     (GFX_QUADRANT0 | GFX_QUADRANT1)
+/** Bitmask for drawing right half of circle. */
+#define GFX_RIGHTHALF   (GFX_QUADRANT1 | GFX_QUADRANT2)
+/** Bitmask for drawing bottom half of circle. */
+#define GFX_BOTTOMHALF  (GFX_QUADRANT2 | GFX_QUADRANT3)
+
+/** Bitmask for drawing whole circle. */
+#define GFX_WHOLE       0xFF
+
+/** @} */
+
+/** \name Graphic Drawing Primitives */
+/** @{ */
+
+/**
+ * \def gfx_mono_draw_horizontal_line(x, y, length, color)
+ * \brief Draw a horizontal line, one pixel wide.
+ *
+ * \param[in]  x          X coordinate of leftmost pixel.
+ * \param[in]  y          Y coordinate of the line.
+ * \param[in]  length     Length of the line in pixels.
+ * \param[in]  color      Pixel operation of the line.
+ */
+
+/**
+ * \def gfx_mono_draw_vertical_line(x, y, length, color)
+ * \brief Draw a vertical line, one pixel wide.
+ *
+ * \param[in]  x          X coordinate of the line.
+ * \param[in]  y          Y coordinate of the topmost pixel.
+ * \param[in]  length     Length of the line in pixels.
+ * \param[in]  color      Pixel operation of the line.
+ */
+
+/**
+ * \def gfx_mono_draw_line(x1, y1, x2, y2, color)
+ * \brief Draw a line between two arbitrary points.
+ *
+ * \param[in]  x1          Start X coordinate.
+ * \param[in]  y1          Start Y coordinate.
+ * \param[in]  x2          End X coordinate.
+ * \param[in]  y2          End Y coordinate.
+ * \param[in]  color       Pixel operation of the line.
+ */
+
+/**
+ * \def gfx_mono_draw_rect(x, y, width, height, color)
+ * \brief Draw an outline of a rectangle.
+ *
+ * \param[in]  x           X coordinate of the left side.
+ * \param[in]  y           Y coordinate of the top side.
+ * \param[in]  width       Width of the rectangle.
+ * \param[in]  height      Height of the rectangle.
+ * \param[in]  color       Pixel operation of the line.
+ */
+
+/**
+ * \def gfx_mono_draw_filled_rect(x, y, width, height, color)
+ * \brief Draw a filled rectangle.
+ *
+ * \param[in]  x           X coordinate of the left side.
+ * \param[in]  y           Y coordinate of the top side.
+ * \param[in]  width       Width of the rectangle.
+ * \param[in]  height      Height of the rectangle.
+ * \param[in]  color       Pixel operation of the line
+ */
+
+/**
+ * \def gfx_mono_draw_circle(x, y, radius, color, octant_mask)
+ * \brief Draw an outline of a circle or arc.
+ *
+ * The radius is the distance from the center to the circumference,
+ * which means that the total width or height of a circle will be
+ * (radius*2+1).
+ *
+ * The octant_mask parameter is a bitmask that decides which octants of
+ * the circle to draw. Use the GFX_OCTANTn, GFX_QUADRANTn, GFX_xHALF and
+ * GFX_WHOLE constants and OR them together if required. Radius equal to
+ * zero gives a single pixel.
+ *
+ * \param[in]  x           X coordinate of center.
+ * \param[in]  y           Y coordinate of center.
+ * \param[in]  radius      Circle radius in pixels.
+ * \param[in]  color       Pixel operation.
+ * \param[in]  octant_mask Bitmask indicating which octants to draw.
+ */
+
+/**
+ * \def gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask)
+ * \brief Draw a filled circle or sector.
+ *
+ * The radius is the distance from the center to the circumference,
+ * which means that the total width or height of a circle will be
+ * (radius*2+1).
+ *
+ * The quadrant_mask parameter is a bitmask that decides which quadrants
+ * of the circle to draw. Use the GFX_QUADRANTn, GFX_xHALF and
+ * GFX_WHOLE constants and OR them together if required. Radius equal to
+ * zero gives a single pixel.
+ *
+ * \note This function only supports quadrants while gfx_draw_circle()
+ *       supports octants. This is to improve performance on drawing
+ *       filled circles.
+ *
+ * \param[in]  x           X coordinate of center.
+ * \param[in]  y           Y coordinate of center.
+ * \param[in]  radius      Circle radius in pixels.
+ * \param[in]  color       Pixel operation.
+ * \param[in]  quadrant_mask Bitmask indicating which quadrants to draw.
+ */
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_common2_gfx_mono_quickstart Quick Start Guide for the mono graphics service
+ *
+ * This is the quick start guide for the \ref asfdoc_common2_gfx_mono "Monochrome Graphics service",
+ * with step-by-step instructions on how to configure and use it for a specific
+ * use case.
+ *
+ * \section asfdoc_common2_gfx_mono_quickstart_basic Basic usage of the graphics service
+ * This use case will demonstrate initializing the mono graphics service and
+ * then draw a black line on the screen from coordinates X=10, Y=10 to X=20,
+ * Y=20.
+ *
+ * \section asfdoc_common2_gfx_mono_basic_usage Usage steps
+ * \subsection asfdoc_common2_gfx_mono_basic_usage_code Example code
+ * Add to, e.g., the main function in the application C-file:
+ * \code
+	system_init();
+	gfx_mono_init();
+	gfx_mono_draw_line(10, 10, 20, 20, GFX_PIXEL_SET);
+\endcode
+ *
+ * \subsection gfx_mono_basic_usage_workflow Workflow
+ * -# Initialize system:
+ *  - \code system_init(); \endcode
+ * -# Initialize monochrome graphics service
+ *  - \code gfx_mono_init(); \endcode
+ *  - \note This will call the init function for the low level display
+ *          controller driver and intialize the screen to a cleared background.
+ * -# Draw a line from 10,10 to 20,20:
+ * -  \code gfx_mono_draw_line(10, 10, 20, 20, GFX_PIXEL_SET); \endcode
+ * -  \note This uses GFX_PIXEL_SET to set the display pixels on the line;
+ *          other options can be found in \ref gfx_mono_color.
+ */
+
+/**
+ * \page asfdoc_common2_gfx_mono_exqsg Examples for GFX Mono Library
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example applications
+ * for \ref asfdoc_common2_gfx_mono. QSGs are simple examples with step-by-step instructions
+ * to configure and use this driver in a selection of use cases. Note that QSGs can be compiled as
+ * a standalone application or be added to the user application.
+ *  - \subpage asfdoc_common2_gfx_mono_quickstart
+ *  - \subpage asfdoc_common2_gfx_mono_font_quickstart
+ *  - \subpage asfdoc_common2_gfx_mono_sysfont_example
+ *  - \subpage asfdoc_common2_gfx_mono_spinner_example
+ *
+ */
+
+
+#endif /* GFX_MONO_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.c
new file mode 100644
index 0000000000..296335726f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.c
@@ -0,0 +1,369 @@
+/**
+ * \file
+ *
+ * \brief Haven Display C12832 A1Z display glue code for display controller
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "gfx_mono_c12832_a1z.h"
+
+/* If we are using a serial interface without readback, use framebuffer */
+#ifdef ST7565R_SERIAL_INTERFACE
+# define CONFIG_ST7565R_FRAMEBUFFER
+#endif
+
+#ifdef CONFIG_ST7565R_FRAMEBUFFER
+static uint8_t framebuffer[GFX_MONO_LCD_FRAMEBUFFER_SIZE];
+#endif
+
+/**
+ * \brief Initialize ST7565R controller and LCD display.
+ * It will also write the graphic controller RAM to all zeroes.
+ *
+ * \note This function will clear the contents of the display.
+ */
+void gfx_mono_st7565r_init(void)
+{
+	uint8_t page;
+	uint8_t column;
+
+#ifdef CONFIG_ST7565R_FRAMEBUFFER
+	gfx_mono_set_framebuffer(framebuffer);
+#endif
+
+	/* Initialize the low-level display controller. */
+	st7565r_init();
+
+	/* Set display to output data from line 0 */
+	st7565r_set_display_start_line_address(0);
+
+	/* Clear the contents of the display.
+	 * If using a framebuffer (SPI interface) it will both clear the
+	 * controller memory and the framebuffer.
+	 */
+	for (page = 0; page < GFX_MONO_LCD_PAGES; page++) {
+		for (column = 0; column < GFX_MONO_LCD_WIDTH; column++) {
+			gfx_mono_put_byte(page, column, 0x00);
+		}
+	}
+}
+
+/**
+ * \brief Put framebuffer to LCD controller
+ *
+ * This function will output the complete framebuffer from RAM to the
+ * LCD controller.
+ *
+ * \note This is done automatically if using the graphic primitives. Only
+ * needed if you are manipulating the framebuffer directly in your code.
+ */
+void gfx_mono_st7565r_put_framebuffer(void)
+{
+	uint8_t page;
+
+	for (page = 0; page < GFX_MONO_LCD_PAGES; page++) {
+		st7565r_set_page_address(page);
+		st7565r_set_column_address(0);
+		gfx_mono_st7565r_put_page(framebuffer
+				+ (page * GFX_MONO_LCD_WIDTH), page, 0,
+				GFX_MONO_LCD_WIDTH);
+	}
+}
+
+/**
+ * \brief Draw pixel to screen
+ *
+ * \param[in] x         X coordinate of the pixel
+ * \param[in] y         Y coordinate of the pixel
+ * \param[in] color     Pixel operation
+ *
+ * The following will set the pixel at x=10,y=10:
+ * \code
+	gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_SET);
+\endcode
+ * The following example will clear the pixel at x=10,y=10:
+ * \code
+	gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_CLR);
+\endcode
+ * And the following will toggle the pixel at x=10,y=10:
+ * \code
+	gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_XOR);
+\endcode
+ */
+void gfx_mono_st7565r_draw_pixel(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t color)
+{
+	uint8_t page;
+	uint8_t pixel_mask;
+	uint8_t pixel_value;
+
+	/* Discard pixels drawn outside the screen */
+	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
+		return;
+	}
+
+	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+	pixel_mask = (1 << (y - (page * 8)));
+
+	/*
+	 * Read the page containing the pixel in interest, then perform the
+	 * requested action on this pixel before writing the page back to the
+	 * display.
+	 */
+	pixel_value = gfx_mono_get_byte(page, x);
+
+	switch (color) {
+	case GFX_PIXEL_SET:
+		pixel_value |= pixel_mask;
+		break;
+
+	case GFX_PIXEL_CLR:
+		pixel_value &= ~pixel_mask;
+		break;
+
+	case GFX_PIXEL_XOR:
+		pixel_value ^= pixel_mask;
+		break;
+
+	default:
+		break;
+	}
+
+	gfx_mono_put_byte(page, x, pixel_value);
+}
+
+/**
+ * \brief Get the pixel value at x,y
+ *
+ * \param[in] x      X coordinate of pixel
+ * \param[in] y      Y coordinate of pixel
+ * \return Non zero value if pixel is set.
+ *
+ * The following example will read the pixel value from x=10,y=10:
+ * \code
+	pixelval = gfx_mono_st7565r_get_pixel(10,10);
+\endcode
+ */
+uint8_t gfx_mono_st7565r_get_pixel(gfx_coord_t x, gfx_coord_t y)
+{
+	uint8_t page;
+	uint8_t pixel_mask;
+
+	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
+		return 0;
+	}
+
+	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+	pixel_mask = (1 << (y - (page * 8)));
+
+	return gfx_mono_get_byte(page, x) & pixel_mask;
+}
+
+/**
+ * \brief Put a page from RAM to display controller.
+ *
+ * If the controller is accessed by the SPI interface, we can not read
+ * back data from the LCD controller RAM. Because of this all data that is
+ * written to the LCD controller in this mode is also written to a framebuffer 
+ * in MCU RAM.
+ *
+ * \param[in] data Pointer to data to be written
+ * \param[in] page Page address
+ * \param[in] column Offset into page (x coordinate)
+ * \param[in] width Number of bytes to be written.
+ *
+ * The following example will write 32 bytes from data_buf to the page 0,
+ * column 10. This will place data_buf in the rectangle x1=10,y1=0,x2=42,y2=8
+ * (10 pixels from the upper left corner of the screen):
+ * \code
+	gfx_mono_st7565r_put_page(data_buf, 0, 10, 32);
+\endcode
+ */
+void gfx_mono_st7565r_put_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t column, gfx_coord_t width)
+{
+#ifdef CONFIG_ST7565R_FRAMEBUFFER
+	gfx_mono_framebuffer_put_page(data, page, column, width);
+#endif
+	st7565r_set_page_address(page);
+	st7565r_set_column_address(column);
+
+	do {
+		st7565r_write_data(*data++);
+	} while (--width);
+}
+
+/**
+ * \brief Read a page from the LCD controller
+ *
+ * If the LCD controller is accessed by the SPI interface we cannot read
+ * data directly from the controller. In that case we will read the data from
+ * the local framebuffer instead.
+ *
+ * \param[in] data   Pointer where to store the read data
+ * \param[in] page   Page address
+ * \param[in] column Offset into page (x coordinate)
+ * \param[in] width  Number of bytes to be read
+ *
+ * The following example will read back the first 128 bytes (first page) from
+ * the display memory:
+ * \code
+	gfx_mono_st7565r_get_page(read_buffer, 0, 0, 128);
+\endcode
+ */
+void gfx_mono_st7565r_get_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t column, gfx_coord_t width)
+{
+#ifdef CONFIG_ST7565R_FRAMEBUFFER
+	gfx_mono_framebuffer_get_page(data, page, column, width);
+#else
+	st7565r_set_page_address(page);
+	st7565r_set_column_address(column);
+
+	do {
+		*data++ = st7565r_read_data();
+	} while (--width);
+#endif
+}
+
+/**
+ * \brief Put a byte to the display controller RAM
+ *
+ * If the LCD controller is accessed by the SPI interface we will also put the
+ * data to the local framebuffer.
+ *
+ * \param[in] page Page address
+ * \param[in] column Page offset (x coordinate)
+ * \param[in] data Data to be written
+ *
+ * This example will put the value 0xFF to the first byte in the display memory
+ * setting a 8 pixel high column of pixels in the upper left corner of the
+ * display.
+ * \code
+	gfx_mono_st7565r_put_byte(0, 0, 0xFF);
+\endcode
+ */
+void gfx_mono_st7565r_put_byte(gfx_coord_t page, gfx_coord_t column,
+		uint8_t data)
+{
+#ifdef CONFIG_ST7565R_FRAMEBUFFER
+	gfx_mono_framebuffer_put_byte(page, column, data);
+#endif
+
+	st7565r_set_page_address(page);
+	st7565r_set_column_address(column);
+
+	st7565r_write_data(data);
+}
+
+/**
+ * \brief Get a byte from the display controller RAM
+ *
+ * If the LCD controller is accessed by the SPI interface we cannot read the
+ * data. In this case return the data from the local framebuffer instead.
+ *
+ * \param page Page address
+ * \param column Page offset (x coordinate)
+ * \return data from LCD controller or framebuffer.
+ *
+ * The following code will read the first byte from the display memory or the
+ * local framebuffer if direct read is not possible. The data represents the
+ * pixels from x = 0 and y = 0 to y = 7.
+ * \code
+	data = gfx_mono_st7565r_get_byte(0, 0);
+\endcode
+ */
+uint8_t gfx_mono_st7565r_get_byte(gfx_coord_t page, gfx_coord_t column)
+{
+#ifdef CONFIG_ST7565R_FRAMEBUFFER
+	return gfx_mono_framebuffer_get_byte(page, column);
+
+#else
+	st7565r_set_page_address(page);
+	st7565r_set_column_address(column);
+
+	return st7565r_read_data();
+
+#endif
+}
+
+/**
+ * \brief Read/Modify/Write a byte on the display controller
+ *
+ * This function will read the byte from the display controller (or the
+ * framebuffer if we cannot read directly from the controller) and
+ * do a mask operation on the byte according to the pixel operation selected
+ * by the color argument and the pixel mask provided.
+ *
+ * \param[in] page Page address
+ * \param[in] column Page offset (x coordinate)
+ * \param[in] pixel_mask Mask for pixel operation
+ * \param[in] color Pixel operation
+ *
+ * A small example that will XOR the first byte of display memory with 0xAA
+ * \code
+	gfx_mono_st7565r_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
+\endcode
+ */
+void gfx_mono_st7565r_mask_byte(gfx_coord_t page, gfx_coord_t column,
+		gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
+{
+	gfx_mono_color_t temp = gfx_mono_get_byte(page, column);
+
+	switch (color) {
+	case GFX_PIXEL_SET:
+		temp |= pixel_mask;
+		break;
+
+	case GFX_PIXEL_CLR:
+		temp &= ~pixel_mask;
+		break;
+
+	case GFX_PIXEL_XOR:
+		temp ^= pixel_mask;
+		break;
+
+	default:
+		break;
+	}
+
+	gfx_mono_put_byte(page, column, temp);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.h
new file mode 100644
index 0000000000..9aa99c02fe
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.h
@@ -0,0 +1,168 @@
+/**
+ * \file
+ *
+ * \brief Haven Display C12832 A1Z display glue code for display controller
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef GFX_MONO_C12832_A1Z_H
+#define GFX_MONO_C12832_A1Z_H
+#include "compiler.h"
+#include "st7565r.h"
+
+#include "gfx_mono.h"
+#include "gfx_mono_framebuffer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_C12832_A1Z_group C12832_A1Z graphic library abstraction
+ *
+ * This module is an abstraction layer between the graphic library and the
+ * C12832_A1Z monochrome LCD display connected to a ST7565R LCD controller.
+ *
+ * As the controller does not provide any hardware accelerated graphic, all the
+ * graphic primitives are provided by the \ref asfdoc_common2_gfx_mono_generic_group service.
+ *
+ * \note Do not call the gfx_mono_st7565r_ functions directly. use the gfx_mono
+ * names that are defined in this header and documented in \ref asfdoc_common2_gfx_mono .
+ * Ie. gfx_mono_draw_pixel() should be used, not gfx_mono_st7565r_draw_pixel()
+ * @{
+ */
+
+#define GFX_MONO_LCD_WIDTH              128
+#ifndef GFX_MONO_LCD_HEIGHT
+#	define GFX_MONO_LCD_HEIGHT             32
+#endif
+#define GFX_MONO_LCD_PIXELS_PER_BYTE    8
+#define GFX_MONO_LCD_PAGES              (GFX_MONO_LCD_HEIGHT / \
+	GFX_MONO_LCD_PIXELS_PER_BYTE)
+#define GFX_MONO_LCD_FRAMEBUFFER_SIZE   ((GFX_MONO_LCD_WIDTH * \
+	GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
+
+#define gfx_mono_draw_horizontal_line(x, y, length, color) \
+	gfx_mono_generic_draw_horizontal_line(x, y, length, color)
+
+#define gfx_mono_draw_vertical_line(x, y, length, color) \
+	gfx_mono_generic_draw_vertical_line(x, y, length, color)
+
+#define gfx_mono_draw_line(x1, y1, x2, y2, color) \
+	gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
+
+#define gfx_mono_draw_rect(x, y, width, height, color) \
+	gfx_mono_generic_draw_rect(x, y, width, height, color)
+
+#define gfx_mono_draw_filled_rect(x, y, width, height, color) \
+	gfx_mono_generic_draw_filled_rect(x, y, width, height, \
+		color)
+
+#define gfx_mono_draw_circle(x, y, radius, color, octant_mask) \
+	gfx_mono_generic_draw_circle(x, y, radius, color, \
+		octant_mask)
+
+#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask)	\
+	gfx_mono_generic_draw_filled_circle(x, y, radius, \
+		color, quadrant_mask)
+
+#define gfx_mono_put_bitmap(bitmap, x, y) \
+	gfx_mono_generic_put_bitmap(bitmap, x, y)
+
+#define gfx_mono_draw_pixel(x, y, color) \
+	gfx_mono_st7565r_draw_pixel(x, y, color)
+
+#define gfx_mono_get_pixel(x, y) \
+	gfx_mono_st7565r_get_pixel(x, y)
+
+#define gfx_mono_init()	\
+	gfx_mono_st7565r_init()
+
+#define gfx_mono_put_page(data, page, column, width) \
+	gfx_mono_st7565r_put_page(data, page, column, width)
+
+#define gfx_mono_get_page(data, page, column, width) \
+	gfx_mono_st7565r_get_page(data, page, column, width)
+
+#define gfx_mono_put_byte(page, column, data) \
+	gfx_mono_st7565r_put_byte(page, column, data)
+
+#define gfx_mono_get_byte(page, column)	\
+	gfx_mono_st7565r_get_byte(page, column)
+
+#define gfx_mono_mask_byte(page, column, pixel_mask, color) \
+	gfx_mono_st7565r_mask_byte(page, column, pixel_mask, color)
+
+#define gfx_mono_put_framebuffer() \
+	gfx_mono_st7565r_put_framebuffer()
+
+void gfx_mono_st7565r_put_framebuffer(void);
+
+void gfx_mono_st7565r_put_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t page_offset, gfx_coord_t width);
+
+void gfx_mono_st7565r_get_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t page_offset, gfx_coord_t width);
+
+void gfx_mono_st7565r_init(void);
+
+void gfx_mono_st7565r_draw_pixel(gfx_coord_t x, gfx_coord_t y,
+		gfx_mono_color_t color);
+
+uint8_t gfx_mono_st7565r_get_pixel(gfx_coord_t x, gfx_coord_t y);
+
+void gfx_mono_st7565r_put_byte(gfx_coord_t page, gfx_coord_t column,
+		uint8_t data);
+
+uint8_t gfx_mono_st7565r_get_byte(gfx_coord_t page, gfx_coord_t column);
+
+void gfx_mono_st7565r_mask_byte(gfx_coord_t page, gfx_coord_t column,
+		gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_C12832_A1Z_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.c
new file mode 100644
index 0000000000..8e44bf8e51
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.c
@@ -0,0 +1,266 @@
+/**
+ * \file
+ *
+ * \brief Local framebuffer
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "gfx_mono_framebuffer.h"
+
+/* Pointer to the framebuffer; updated by the gfx_mono_set_framebuffer function */
+static uint8_t *fbpointer;
+
+/**
+ * \brief Set the LCD framebuffer.
+ *
+ * \param[in] framebuffer A pointer to an allocated area of RAM that can hold the
+ * framebuffer.
+ *
+ * A small example:
+ * \code
+	uint8_t framebuffer[FRAMEBUFFER_SIZE];
+	gfx_mono_set_framebuffer(framebuffer);
+\endcode
+ */
+void gfx_mono_set_framebuffer(uint8_t *framebuffer)
+{
+	fbpointer = framebuffer;
+}
+
+/**
+ * \brief Put a page from RAM to the framebuffer
+ *
+ * \param[in] data Pointer to data to be written
+ * \param[in] page Page address
+ * \param[in] column Offset into page (x coordinate)
+ * \param[in] width Number of bytes to be written.
+ *
+ * The following example will write 32 bytes from data_buf to the page 0,
+ * column 10 (byte 10 to 42 in the framebuffer).
+ * \code
+	gfx_mono_framebuffer_put_page(data_buf, 0, 10, 32);
+\endcode
+ */
+void gfx_mono_framebuffer_put_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t column, gfx_coord_t width)
+{
+	gfx_mono_color_t *data_pt = data;
+	gfx_coord_t *framebuffer_pt = fbpointer +
+			((page * GFX_MONO_LCD_WIDTH) + column);
+
+	do {
+		*framebuffer_pt++ = *data_pt++;
+	} while (--width > 0);
+}
+
+/**
+ * \brief Read a page from the framebuffer
+ *
+ * \param[in] data   Pointer where to store the read data
+ * \param[in] page   Page address
+ * \param[in] column Offset into page (x coordinate)
+ * \param[in] width  Number of bytes to be read
+ *
+ * The following example will read back the first 128 bytes (first page) from
+ * the framebuffer:
+ * \code
+	gfx_mono_framebuffer_get_page(read_buffer, 0, 0, 128);
+\endcode
+ */
+void gfx_mono_framebuffer_get_page(gfx_mono_color_t *data, gfx_coord_t page, \
+		gfx_coord_t column, gfx_coord_t width)
+{
+	gfx_coord_t *framebuffer_pt = fbpointer +
+			((page * GFX_MONO_LCD_WIDTH) + column);
+	do {
+		*data++ = *framebuffer_pt++;
+	} while (--width > 0);
+}
+
+/**
+ * \brief Draw pixel to framebuffer
+ *
+ * \param[in] x         X coordinate of the pixel
+ * \param[in] y         Y coordinate of the pixel
+ * \param[in] color     Pixel operation
+ *
+ */
+void gfx_mono_framebuffer_draw_pixel(gfx_coord_t x, gfx_coord_t y,
+		gfx_mono_color_t color)
+{
+	uint8_t page;
+	uint8_t pixel_mask;
+	uint8_t pixel_value;
+
+	/* Discard pixels drawn outside the screen */
+	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
+		return;
+	}
+
+	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+	pixel_mask = (1 << (y - (page * 8)));
+
+	/*
+	 * Read the page containing the pixel in interest, then perform the
+	 * requested action on this pixel before writing the page back to the
+	 * display.
+	 */
+	pixel_value = gfx_mono_framebuffer_get_byte(page, x);
+
+	switch (color) {
+	case GFX_PIXEL_SET:
+		pixel_value |= pixel_mask;
+		break;
+
+	case GFX_PIXEL_CLR:
+		pixel_value &= ~pixel_mask;
+		break;
+
+	case GFX_PIXEL_XOR:
+		pixel_value ^= pixel_mask;
+		break;
+
+	default:
+		break;
+	}
+
+	gfx_mono_framebuffer_put_byte(page, x, pixel_value);
+}
+
+/**
+ * \brief Get the pixel value at x,y in framebuffer
+ *
+ * \param[in] x      X coordinate of pixel
+ * \param[in] y      Y coordinate of pixel
+ * \return Non zero value if pixel is set.
+ *
+ */
+uint8_t gfx_mono_framebuffer_get_pixel(gfx_coord_t x, gfx_coord_t y)
+{
+	uint8_t page;
+	uint8_t pixel_mask;
+
+	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
+		return 0;
+	}
+
+	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+	pixel_mask = (1 << (y - (page * 8)));
+
+	return gfx_mono_framebuffer_get_byte(page, x) & pixel_mask;
+}
+
+/**
+ * \brief Put a byte to the framebuffer
+ *
+ * \param[in] page   Page address
+ * \param[in] column Page offset (x coordinate)
+ * \param[in] data   Data to be written
+ *
+ * This example will put the value 0xFF to the first byte in the framebuffer
+ * \code
+	gfx_mono_framebuffer_put_byte(0, 0, 0xFF);
+\endcode
+ */
+void gfx_mono_framebuffer_put_byte(gfx_coord_t page, gfx_coord_t column,
+		uint8_t data)
+{
+	*(fbpointer + (page * GFX_MONO_LCD_WIDTH) + column) = data;
+}
+
+/**
+ * \brief Get a byte from the framebuffer
+ *
+ * \param[in] page   Page address
+ * \param[in] column Page offset (x coordinate)
+ * \return       data from LCD controller or framebuffer.
+ *
+ * The following code will read the first byte of the framebuffer
+ * \code
+	data = gfx_mono_framebuffer_get_byte(0, 0);
+\endcode
+ */
+uint8_t gfx_mono_framebuffer_get_byte(gfx_coord_t page, gfx_coord_t column)
+{
+	return *(fbpointer + (page * GFX_MONO_LCD_WIDTH) + column);
+}
+
+/**
+ * \brief Read/Modify/Write a byte in the framebuffer
+ *
+ * This function will read the byte from the framebuffer and
+ * do a mask operation on the byte according to the pixel operation selected
+ * by the color argument and the pixel mask provided.
+ *
+ * \param[in] page       Page address
+ * \param[in] column     Page offset (x coordinate)
+ * \param[in] pixel_mask Mask for pixel operation
+ * \param[in] color      Pixel operation
+ *
+ * A small example that will XOR the first byte of the framebuffer with 0xAA
+ * \code
+	gfx_mono_framebuffer_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
+\endcode
+ */
+void gfx_mono_framebuffer_mask_byte(gfx_coord_t page, gfx_coord_t column,
+		gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
+{
+	gfx_mono_color_t temp;
+
+	temp = gfx_mono_get_byte(page, column);
+
+	switch (color) {
+	case GFX_PIXEL_SET:
+		temp |= pixel_mask;
+		break;
+
+	case GFX_PIXEL_CLR:
+		temp &= ~pixel_mask;
+		break;
+
+	case GFX_PIXEL_XOR:
+		temp ^= pixel_mask;
+		break;
+	}
+
+	gfx_mono_put_byte(page, column, temp);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.h
new file mode 100644
index 0000000000..a7b15436e1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.h
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief Monochrome graphic library framebuffer device
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GFX_MONO_FRAMEBUFFER
+#define GFX_MONO_FRAMEBUFFER
+
+#include "gfx_mono.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_framebuffer_group Framebuffer
+ *
+ * This module provides read/write from and to a framebuffer in RAM. This is
+ * needed when using a controller that does not provide a way to read back data
+ * from the LCD controller memory. In this case we need to buffer the data in
+ * a local framebuffer to allow manipulation on pixel level. It is generally
+ * not recommended to access the framebuffer directly; this is handled by the
+ * graphic driver when needed.
+ *
+ * @{
+ */
+
+void gfx_mono_set_framebuffer(uint8_t *framebuffer);
+
+void gfx_mono_framebuffer_put_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t page_offset, gfx_coord_t width);
+
+void gfx_mono_framebuffer_get_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t page_offset, gfx_coord_t width);
+
+void gfx_mono_framebuffer_draw_pixel(gfx_coord_t x, gfx_coord_t y,
+		gfx_mono_color_t color);
+
+uint8_t gfx_mono_framebuffer_get_pixel(gfx_coord_t x, gfx_coord_t y);
+
+void gfx_mono_framebuffer_put_byte(gfx_coord_t page, gfx_coord_t column,
+		uint8_t data);
+
+uint8_t gfx_mono_framebuffer_get_byte(gfx_coord_t page, gfx_coord_t column);
+
+void gfx_mono_framebuffer_mask_byte(gfx_coord_t page, gfx_coord_t column,
+		gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_FRAMEBUFFER */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.c
new file mode 100644
index 0000000000..42e18bae3c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.c
@@ -0,0 +1,506 @@
+/**
+ * \file
+ *
+ * \brief Generic monochrome LCD graphic primitives
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono_generic_group
+ * @{
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "gfx_mono_generic.h"
+
+/**
+ * \brief Draw a horizontal line, one pixel wide (generic implementation)
+ *
+ * \note This function does a very simple bounds checking that does not
+ * check if the line is placed outside the screen. If you supply an
+ * x- or y-coordinate outside the display the behaviour is undefined,
+ * and you risk overwriting portions of internal SRAM.
+ *
+ * \param[in]  x          X coordinate of leftmost pixel.
+ * \param[in]  y          Y coordinate of the line.
+ * \param[in]  length     Length of the line in pixels.
+ * \param[in]  color      Pixel operation of the line.
+ */
+void gfx_mono_generic_draw_horizontal_line(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t length, enum gfx_mono_color color)
+{
+	uint8_t page;
+	uint8_t pixelmask;
+	uint8_t temp;
+
+	/* Clip line length if too long */
+	if (x + length > GFX_MONO_LCD_WIDTH) {
+		length = GFX_MONO_LCD_WIDTH - x;
+	}
+
+	page = y / 8;
+	pixelmask = (1 << (y - (page * 8)));
+
+	if (length == 0) {
+		/* Nothing to do. Move along. */
+		return;
+	}
+
+	switch (color) {
+	case GFX_PIXEL_SET:
+		while (length-- > 0) {
+			temp = gfx_mono_get_byte(page, x + length);
+			temp |= pixelmask;
+			gfx_mono_put_byte(page, x + length, temp);
+		}
+		break;
+
+	case GFX_PIXEL_CLR:
+		while (length-- > 0) {
+			temp = gfx_mono_get_byte(page, x + length);
+			temp &= ~pixelmask;
+			gfx_mono_put_byte(page, x + length, temp);
+		}
+		break;
+
+	case GFX_PIXEL_XOR:
+		while (length-- > 0) {
+			temp = gfx_mono_get_byte(page, x + length);
+			temp ^= pixelmask;
+			gfx_mono_put_byte(page, x + length, temp);
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+/**
+ * \brief Draw a vertical line, one pixel wide (generic implementation)
+ *
+ * \note This function does a very simple bounds checking that does not
+ * check if the line is placed outside the screen. If you supply an
+ * x- or y-coordinate outside the display the behaviour is undefined,
+ * and you risk overwriting portions of internal SRAM.
+ *
+ * \param[in]  x          X coordinate of the line.
+ * \param[in]  y          Y coordinate of the topmost pixel.
+ * \param[in]  length     Length of the line in pixels.
+ * \param[in]  color      Pixel operation of the line.
+ */
+void gfx_mono_generic_draw_vertical_line(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t length, enum gfx_mono_color color)
+{
+	if (length == 0) {
+		return;
+	}
+
+	gfx_coord_t y2 = y + length - 1;
+
+	if (y == y2) {
+		gfx_mono_draw_pixel(x, y, color);
+		return;
+	}
+
+	if (y2 >= GFX_MONO_LCD_HEIGHT - 1) {
+		y2 = GFX_MONO_LCD_HEIGHT - 1;
+	}
+
+	gfx_coord_t y1page = y / 8;
+	gfx_coord_t y2page = y2 / 8;
+
+	uint8_t y1bitpos = y & 0x07;
+	uint8_t y2bitpos = y2 & 0x07;
+
+	uint8_t y1pixelmask = 0xFF << y1bitpos;
+	uint8_t y2pixelmask = 0xFF >> (7 - y2bitpos);
+
+	/* The pixels are on the same page; combine masks */
+	if (y1page == y2page) {
+		uint8_t pixelmask = y1pixelmask & y2pixelmask;
+		gfx_mono_mask_byte(y1page, x, pixelmask, color);
+	} else {
+		gfx_mono_mask_byte(y1page, x, y1pixelmask, color);
+
+		while (++y1page < y2page) {
+			gfx_mono_mask_byte(y1page, x, 0xFF, color);
+		}
+
+		gfx_mono_mask_byte(y2page, x, y2pixelmask, color);
+	}
+}
+
+/**
+ * \brief Draw a line between two arbitrary points (generic implementation).
+ *
+ * \param[in]  x1          Start X coordinate.
+ * \param[in]  y1          Start Y coordinate.
+ * \param[in]  x2          End X coordinate.
+ * \param[in]  y2          End Y coordinate.
+ * \param[in]  color       Pixel operation of the line.
+ */
+void gfx_mono_generic_draw_line(gfx_coord_t x1, gfx_coord_t y1,
+		gfx_coord_t x2, gfx_coord_t y2,
+		enum gfx_mono_color color)
+{
+	uint8_t i;
+	uint8_t x;
+	uint8_t y;
+	int8_t xinc;
+	int8_t yinc;
+	int8_t dx;
+	int8_t dy;
+	int8_t e;
+
+	/* swap x1,y1  with x2,y2 */
+	if (x1 > x2) {
+		dx = x1;
+		x1 = x2;
+		x2 = dx;
+		dy = y1;
+		y1 = y2;
+		y2 = dy;
+	}
+
+	dx = x2 - x1;
+	dy = y2 - y1;
+
+	x = x1;
+	y = y1;
+
+	if (dx < 0) {
+		xinc = -1;
+		dx = -dx;
+	} else {
+		xinc = 1;
+	}
+
+	if (dy < 0) {
+		yinc = -1;
+		dy = -dy;
+	} else {
+		yinc = 1;
+	}
+
+	if (dx > dy) {
+		e = dy - dx;
+		for (i = 0; i <= dx; i++) {
+			gfx_mono_draw_pixel(x, y, color);
+			if (e >= 0) {
+				e -= dx;
+				y += yinc;
+			}
+
+			e += dy;
+			x += xinc;
+		}
+	} else {
+		e = dx - dy;
+		for (i = 0; i <= dy; i++) {
+			gfx_mono_draw_pixel(x, y, color);
+			if (e >= 0) {
+				e -= dy;
+				x += xinc;
+			}
+
+			e += dx;
+			y += yinc;
+		}
+	}
+}
+
+/**
+ * \brief Draw an outline of a rectangle (generic implementation).
+ *
+ * \param[in]  x           X coordinate of the left side.
+ * \param[in]  y           Y coordinate of the top side.
+ * \param[in]  width       Width of the rectangle.
+ * \param[in]  height      Height of the rectangle.
+ * \param[in] color       Pixel operation of the line.
+ */
+void gfx_mono_generic_draw_rect(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t width, gfx_coord_t height,
+		enum gfx_mono_color color)
+{
+	gfx_mono_draw_horizontal_line(x, y, width, color);
+	gfx_mono_draw_horizontal_line(x, y + height - 1, width, color);
+
+	gfx_mono_draw_vertical_line(x, y, height, color);
+	gfx_mono_draw_vertical_line(x + width - 1, y, height, color);
+}
+
+/**
+ * \brief Draw a filled rectangle (generic implementation).
+ *
+ * \param[in]  x           X coordinate of the left side.
+ * \param[in]  y           Y coordinate of the top side.
+ * \param[in]  width       Width of the rectangle.
+ * \param[in]  height      Height of the rectangle.
+ * \param[in]  color       Pixel operation of the line
+ */
+void gfx_mono_generic_draw_filled_rect(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t width, gfx_coord_t height,
+		enum gfx_mono_color color)
+{
+	if (height == 0) {
+		/* Nothing to do. Move along. */
+		return;
+	}
+
+	while (height-- > 0) {
+		gfx_mono_draw_horizontal_line(x, y + height, width, color);
+	}
+}
+
+/**
+ * \brief Draw an outline of a circle or arc (generic implementation).
+ *
+ * The radius is the distance from the center to the circumference,
+ * which means that the total width or height of a circle will be
+ * (radius*2+1).
+ *
+ * The octant_mask parameter is a bitmask that decides which octants of
+ * the circle to draw. Use the GFX_OCTANTn, GFX_QUADRANTn, GFX_xHALF and
+ * GFX_WHOLE constants and OR them together if required. Radius equal to
+ * zero gives a single pixel.
+ *
+ * \param[in]  x           X coordinate of center.
+ * \param[in]  y           Y coordinate of center.
+ * \param[in]  radius      Circle radius in pixels.
+ * \param[in]  color       Pixel operation.
+ * \param[in]  octant_mask Bitmask indicating which octants to draw.
+ */
+void gfx_mono_generic_draw_circle(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t radius, enum gfx_mono_color color,
+		uint8_t octant_mask)
+{
+	gfx_coord_t offset_x;
+	gfx_coord_t offset_y;
+	int16_t error;
+
+	/* Draw only a pixel if radius is zero. */
+	if (radius == 0) {
+		gfx_mono_draw_pixel(x, y, color);
+		return;
+	}
+
+	/* Set up start iterators. */
+	offset_x = 0;
+	offset_y = radius;
+	error = 3 - 2 * radius;
+
+	/* Iterate offsetX from 0 to radius. */
+	while (offset_x <= offset_y) {
+		/* Draw one pixel for each octant enabled in octant_mask. */
+		if (octant_mask & GFX_OCTANT0) {
+			gfx_mono_draw_pixel(x + offset_y, y - offset_x, color);
+		}
+
+		if (octant_mask & GFX_OCTANT1) {
+			gfx_mono_draw_pixel(x + offset_x, y - offset_y, color);
+		}
+
+		if (octant_mask & GFX_OCTANT2) {
+			gfx_mono_draw_pixel(x - offset_x, y - offset_y, color);
+		}
+
+		if (octant_mask & GFX_OCTANT3) {
+			gfx_mono_draw_pixel(x - offset_y, y - offset_x, color);
+		}
+
+		if (octant_mask & GFX_OCTANT4) {
+			gfx_mono_draw_pixel(x - offset_y, y + offset_x, color);
+		}
+
+		if (octant_mask & GFX_OCTANT5) {
+			gfx_mono_draw_pixel(x - offset_x, y + offset_y, color);
+		}
+
+		if (octant_mask & GFX_OCTANT6) {
+			gfx_mono_draw_pixel(x + offset_x, y + offset_y, color);
+		}
+
+		if (octant_mask & GFX_OCTANT7) {
+			gfx_mono_draw_pixel(x + offset_y, y + offset_x, color);
+		}
+
+		/* Update error value and step offset_y when required. */
+		if (error < 0) {
+			error += ((offset_x << 2) + 6);
+		} else {
+			error += (((offset_x - offset_y) << 2) + 10);
+			--offset_y;
+		}
+
+		/* Next X. */
+		++offset_x;
+	}
+}
+
+/**
+ * \brief Draw a filled circle or sector (generic implementation).
+ *
+ * The radius is the distance from the center to the circumference,
+ * which means that the total width or height of a circle will be
+ * (radius*2+1).
+ *
+ * The quadrant_mask parameter is a bitmask that decides which quadrants
+ * of the circle to draw. Use the GFX_QUADRANTn, GFX_xHALF and
+ * GFX_WHOLE constants and OR them together if required. Radius equal to
+ * zero gives a single pixel.
+ *
+ * \note This function only supports quadrants while gfx_draw_circle()
+ *       supports octants. This is to improve performance on drawing
+ *       filled circles.
+ *
+ * \param[in]  x           X coordinate of center.
+ * \param[in]  y           Y coordinate of center.
+ * \param[in]  radius      Circle radius in pixels.
+ * \param[in]  color       Pixel operation.
+ * \param[in]  quadrant_mask Bitmask indicating which quadrants to draw.
+ */
+void gfx_mono_generic_draw_filled_circle(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t radius, enum gfx_mono_color color,
+		uint8_t quadrant_mask)
+{
+	gfx_coord_t offset_x;
+	gfx_coord_t offset_y;
+	int16_t error;
+
+	/* Draw only a pixel if radius is zero. */
+	if (radius == 0) {
+		gfx_mono_draw_pixel(x, y, color);
+		return;
+	}
+
+	/* Set up start iterators. */
+	offset_x = 0;
+	offset_y = radius;
+	error = 3 - 2 * radius;
+
+	/* Iterate offset_x from 0 to radius. */
+	while (offset_x <= offset_y) {
+		/* Draw vertical lines tracking each quadrant. */
+		if (quadrant_mask & GFX_QUADRANT0) {
+			gfx_mono_draw_vertical_line(x + offset_y,
+					y - offset_x, offset_x + 1, color);
+			gfx_mono_draw_vertical_line(x + offset_x,
+					y - offset_y, offset_y + 1, color);
+		}
+
+		if (quadrant_mask & GFX_QUADRANT1) {
+			gfx_mono_draw_vertical_line(x - offset_y,
+					y - offset_x, offset_x + 1, color);
+			gfx_mono_draw_vertical_line(x - offset_x,
+					y - offset_y, offset_y + 1, color);
+		}
+
+		if (quadrant_mask & GFX_QUADRANT2) {
+			gfx_mono_draw_vertical_line(x - offset_y,
+					y, offset_x + 1, color);
+			gfx_mono_draw_vertical_line(x - offset_x,
+					y, offset_y + 1, color);
+		}
+
+		if (quadrant_mask & GFX_QUADRANT3) {
+			gfx_mono_draw_vertical_line(x + offset_y,
+					y, offset_x + 1, color);
+			gfx_mono_draw_vertical_line(x + offset_x,
+					y, offset_y + 1, color);
+		}
+
+		/* Update error value and step offset_y when required. */
+		if (error < 0) {
+			error += ((offset_x << 2) + 6);
+		} else {
+			error += (((offset_x - offset_y) << 2) + 10);
+			--offset_y;
+		}
+
+		/* Next X. */
+		++offset_x;
+	}
+}
+
+/**
+ * \brief Put bitmap from FLASH or RAM to display
+ *
+ * This function will output bitmap data from FLASH or RAM.
+ * The bitmap y-coordinate will be aligned with display pages, rounded down.
+ * Ie: placing a bitmap at x=10, y=5 will put the bitmap at x = 10,y = 0 and
+ * placing a bitmap at x = 10, y = 10 will put the bitmap at x = 10, y = 8
+ *
+ */
+void gfx_mono_generic_put_bitmap(struct gfx_mono_bitmap *bitmap, gfx_coord_t x,
+		gfx_coord_t y)
+{
+	gfx_coord_t num_pages = bitmap->height / 8;
+	gfx_coord_t page = y / 8;
+	gfx_coord_t column;
+	gfx_coord_t i;
+	gfx_mono_color_t temp;
+
+	switch (bitmap->type) {
+	case GFX_MONO_BITMAP_PROGMEM:
+		for (i = 0; i < num_pages; i++) {
+			for (column = 0; column < bitmap->width; column++) {
+				temp = PROGMEM_READ_BYTE(bitmap->data.progmem
+						+ (i * bitmap->width)
+						+ column);
+				gfx_mono_put_byte(i + page, column + x, temp);
+			}
+		}
+		break;
+
+	case GFX_MONO_BITMAP_RAM:
+		for (i = 0; i < num_pages; i++) {
+			gfx_mono_put_page(bitmap->data.pixmap
+					+ (i * bitmap->width), page + i, x,
+					bitmap->width);
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+/** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.h
new file mode 100644
index 0000000000..10ae0b4b55
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.h
@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief Generic monochrome LCD graphic primitives
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GFX_MONO_GENERIC
+#define GFX_MONO_GENERIC
+#include "gfx_mono.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_generic_group Generic monochrome graphic primitives
+ *
+ * This is a service providing generic implementations of graphic primitives
+ * - Horizontal line
+ * - Vertical line
+ * - Line
+ * - Circle (filled/not filled)
+ * - Rectangle (filled/not filled)
+ *
+ * it also provides functionality to draw a bitmap to the graphic memory.
+ *
+ * These functions are made available if the graphic hardware being used do
+ * not implement the functionality in hardware. This is true in most cases.
+ *
+ * This service is included as a requirement for a
+ * hardware specific component that uses these functions, and provides a
+ * asfdoc_common2_draw_pixel function.
+ *
+ * @{
+ */
+
+/**
+ * \brief Storage structure for bitmap pixel data and metadata
+ */
+struct gfx_mono_bitmap {
+	/** Width of bitmap */
+	gfx_coord_t width;
+	/** Height of bitmap */
+	gfx_coord_t height;
+	/** Bitmap type */
+	enum gfx_mono_bitmap_type type;
+	union {
+		/** Pointer to pixels for bitmap stored in RAM */
+		gfx_mono_color_t *pixmap;
+		/** Pointer to pixels for bitmap stored in progmem */
+		gfx_mono_color_t PROGMEM_T *progmem;
+	}
+	data;
+};
+
+void gfx_mono_generic_draw_horizontal_line(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t length, enum gfx_mono_color color);
+
+void gfx_mono_generic_draw_vertical_line(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t length, enum gfx_mono_color color);
+
+void gfx_mono_generic_draw_line(gfx_coord_t x1, gfx_coord_t y1,
+		gfx_coord_t x2, gfx_coord_t y2,
+		enum gfx_mono_color color);
+
+void gfx_mono_generic_draw_rect(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t width, gfx_coord_t height,
+		enum gfx_mono_color color);
+
+void gfx_mono_generic_draw_filled_rect(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t width, gfx_coord_t height,
+		enum gfx_mono_color color);
+
+void gfx_mono_generic_draw_circle(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t radius, enum gfx_mono_color color,
+		uint8_t octant_mask);
+
+void gfx_mono_generic_draw_filled_circle(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t radius, enum gfx_mono_color color,
+		uint8_t quadrant_mask);
+
+void gfx_mono_generic_put_bitmap(struct gfx_mono_bitmap *bitmap, gfx_coord_t x,
+		gfx_coord_t y);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_GENERIC */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.c
new file mode 100644
index 0000000000..4d66b7a74c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.c
@@ -0,0 +1,187 @@
+/**
+ * \file
+ *
+ * \brief Simple menu system
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "sysfont.h"
+#include <conf_menu.h>
+
+#include "gfx_mono_menu.h"
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono_menu
+ * @{
+ */
+
+PROGMEM_DECLARE(gfx_mono_color_t, arrow_right_data[]) = {
+	GFX_MONO_MENU_INDICATOR_BITMAP
+};
+
+struct gfx_mono_bitmap menu_bitmap_indicator = {
+	.height = GFX_MONO_MENU_INDICATOR_HEIGHT,
+	.width = GFX_MONO_MENU_INDICATOR_WIDTH,
+	.type = GFX_MONO_BITMAP_PROGMEM,
+	.data.progmem = arrow_right_data
+};
+
+/**
+ * \brief Draw menu strings and an icon by the current selection.
+ *
+ * \param[in] menu     a menu struct with menu settings
+ * \param[in] redraw   clear screen before drawing menu
+ */
+static void menu_draw(struct gfx_mono_menu *menu, bool redraw)
+{
+	static bool redraw_state;
+	uint8_t i;
+	uint8_t line = 1;
+	uint8_t menu_page = menu->current_selection /
+			GFX_MONO_MENU_ELEMENTS_PER_SCREEN;
+
+	if (menu->current_page != menu_page || redraw == true) {
+		/* clear screen if we have changed the page or menu and prepare
+		 * redraw */
+		gfx_mono_draw_filled_rect(0, SYSFONT_LINESPACING,
+				GFX_MONO_LCD_WIDTH,
+				GFX_MONO_LCD_HEIGHT - SYSFONT_LINESPACING,
+				GFX_PIXEL_CLR);
+		redraw_state = true;
+	}
+
+	menu->current_page = menu_page;
+
+	/* Clear old indicator icon */
+	gfx_mono_draw_filled_rect(0, SYSFONT_LINESPACING,
+			GFX_MONO_MENU_INDICATOR_WIDTH, GFX_MONO_LCD_HEIGHT -
+			SYSFONT_LINESPACING, GFX_PIXEL_CLR);
+
+	/* Put indicator icon on current selection */
+	gfx_mono_put_bitmap(&menu_bitmap_indicator, 0,
+			SYSFONT_LINESPACING * ((menu->current_selection %
+			GFX_MONO_MENU_ELEMENTS_PER_SCREEN) + 1));
+
+	/* Print visible options if page or menu has changed */
+	if (redraw_state == true) {
+		for (i = menu_page * GFX_MONO_MENU_ELEMENTS_PER_SCREEN;
+				i < menu_page *
+				GFX_MONO_MENU_ELEMENTS_PER_SCREEN +
+				GFX_MONO_MENU_ELEMENTS_PER_SCREEN &&
+				i < menu->num_elements; i++) {
+			gfx_mono_draw_progmem_string(
+					(char PROGMEM_PTR_T)menu->strings[i],
+					GFX_MONO_MENU_INDICATOR_WIDTH + 1,
+					line * SYSFONT_LINESPACING, &sysfont);
+			line++;
+		}
+		redraw_state = false;
+	}
+}
+
+/**
+ * *\brief Initialize the menu handling. Clear screen and draw menu.
+ *
+ * \param[in] menu  menu struct with menu options
+ *
+ */
+void gfx_mono_menu_init(struct gfx_mono_menu *menu)
+{
+	/* Clear screen */
+	gfx_mono_draw_filled_rect(0, 0,
+			GFX_MONO_LCD_WIDTH, GFX_MONO_LCD_HEIGHT, GFX_PIXEL_CLR);
+
+	/* Draw the menu title on the top of the screen */
+	gfx_mono_draw_progmem_string((char PROGMEM_PTR_T)menu->title,
+			0, 0, &sysfont);
+
+	/* Draw menu options below */
+	menu_draw(menu, true);
+}
+
+/**
+ * \brief Update menu depending on input.
+ *
+ * \param[in] menu  menu struct with menu options
+ * \param[in] keycode  keycode to process
+ *
+ * \retval selected menu option or status code
+ */
+uint8_t gfx_mono_menu_process_key(struct gfx_mono_menu *menu, uint8_t keycode)
+{
+	switch (keycode) {
+	case GFX_MONO_MENU_KEYCODE_DOWN:
+		if (menu->current_selection == menu->num_elements - 1) {
+			menu->current_selection = 0;
+		} else {
+			menu->current_selection++;
+		}
+
+		/* Update menu on display */
+		menu_draw(menu, false);
+		/* Nothing selected yet */
+		return GFX_MONO_MENU_EVENT_IDLE;
+
+	case GFX_MONO_MENU_KEYCODE_UP:
+		if (menu->current_selection) {
+			menu->current_selection--;
+		} else {
+			menu->current_selection = menu->num_elements - 1;
+		}
+
+		/* Update menu on display */
+		menu_draw(menu, false);
+		/* Nothing selected yet */
+		return GFX_MONO_MENU_EVENT_IDLE;
+
+	case GFX_MONO_MENU_KEYCODE_ENTER:
+		/* Got what we want. Return selection. */
+		return menu->current_selection;
+
+	case GFX_MONO_MENU_KEYCODE_BACK:
+		/* User pressed "back" key, inform user */
+		return GFX_MONO_MENU_EVENT_EXIT;
+
+	default:
+		/* Unknown key event */
+		return GFX_MONO_MENU_EVENT_IDLE;
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.h
new file mode 100644
index 0000000000..6b88051de3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.h
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief Simple menu system
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GFX_MONO_MENU_H
+#define GFX_MONO_MENU_H
+
+#include "compiler.h"
+#include "conf_menu.h"
+#include "gfx_mono.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_menu Menu system for monochrome graphical displays
+ *
+ * This module provides a simple menu system for monochrome graphical
+ * displays.
+ *
+ * Typical flow of an application using the menu system:
+ *
+ * 1) Define menu structure.\n
+ * 2) Call asfdoc_common2_gfx_mono_menu_init.\n
+ * 3) Get user input.\n
+ * 4) Update menu with user input using function \ref
+ *    gfx_mono_menu_process_key.\n
+ * 5) Interpret \ref gfx_mono_menu_process_key return value.\n
+ * 6) Go to 3.\n
+ *
+ * The menu is declared using the \ref gfx_mono_menu struct.
+ *
+ * To start the menu system, call the \ref gfx_mono_menu_init function.
+ * This function will clear the display and draw the menu.
+ *
+ * Before the menu can be updated, you need input from the user. Methods for
+ * getting input is not part of the menu module.
+ *
+ * As soon as input is received, inform the menu system using the
+ * \ref gfx_mono_menu_process_key function.
+ * This function will then return a status code and act depending on the given
+ * keycode:
+ *
+ * MENU_KEYCODE_DOWN : Change selection to next menu item (or first if at
+ * bottom).
+ * Returns MENU_EVENT_IDLE.
+ *
+ * MENU_KEYCODE_UP : Change selection to previous menu item (or last if at top).
+ * Returns MENU_EVENT_IDLE.
+ *
+ * MENU_KEYCODE_ENTER : Nothing changes in menu. Returns the line selected.
+ *
+ * MENU_KEYCODE_BACK : Nothing changes in menu. Returns MENU_EVENT_EXIT.
+ *
+ * The value of the keycodes used are defined in conf_menu.h. These value can
+ * be changed if needed.
+ *
+ * The graphical indicator used to indicate menu selection is defined in
+ * conf_menu.h. This indicator can be changed if needed.
+ * @{
+ */
+
+/** \name Menu events definitions */
+/** @{ */
+/** Idle. Nothing to report. */
+#define GFX_MONO_MENU_EVENT_IDLE    0xFF
+/** Exit. User has pressed the back button. */
+#define GFX_MONO_MENU_EVENT_EXIT    0xFE
+/** @} */
+
+/** Maximum number of menu elements on display */
+#define GFX_MONO_MENU_ELEMENTS_PER_SCREEN ((GFX_MONO_LCD_HEIGHT / \
+	SYSFONT_LINESPACING) - 1)
+
+/** Menu struct */
+struct gfx_mono_menu {
+	PROGMEM_STRING_T title;
+	PROGMEM_STRING_T *strings;
+	uint8_t num_elements;
+	uint8_t current_selection;
+	uint8_t current_page;
+};
+
+void gfx_mono_menu_init(struct gfx_mono_menu *menu);
+uint8_t gfx_mono_menu_process_key(struct gfx_mono_menu *menu, uint8_t keycode);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_MENU_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.c
new file mode 100644
index 0000000000..bf291a4ef1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.c
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Monochrome graphic library NULL display device with framebuffer
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "gfx_mono_null.h"
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono_null
+ * @{
+ */
+
+/* Memory for the framebuffer */
+static uint8_t framebuffer[GFX_MONO_LCD_FRAMEBUFFER_SIZE];
+
+/**
+ * \brief Initialize NULL driver.
+ */
+void gfx_mono_null_init(void)
+{
+	gfx_mono_set_framebuffer(framebuffer);
+}
+
+/** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.h
new file mode 100644
index 0000000000..e799f25215
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.h
@@ -0,0 +1,138 @@
+/**
+ * \file
+ *
+ * \brief Monochrome graphic library NULL display device with framebuffer
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef GFX_MONO_NULL_H
+#define GFX_MONO_NULL_H
+
+#include "gfx_mono.h"
+#include "gfx_mono_framebuffer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_null NULL display device
+ *
+ * This module provides empty read/write functions to a null device
+ * (framebuffer in RAM), removing the need for an actual display or
+ * controller during testing, and enabling the use of most XMEGA boards.
+ *
+ * @{
+ */
+
+#define GFX_MONO_LCD_WIDTH              128
+#define GFX_MONO_LCD_HEIGHT             32
+#define GFX_MONO_LCD_PIXELS_PER_BYTE    8
+#define GFX_MONO_LCD_PAGES              (GFX_MONO_LCD_HEIGHT / \
+	GFX_MONO_LCD_PIXELS_PER_BYTE)
+#define GFX_MONO_LCD_FRAMEBUFFER_SIZE   ((GFX_MONO_LCD_WIDTH * \
+	GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
+
+#define gfx_mono_draw_horizontal_line(x, y, length, color) \
+	gfx_mono_generic_draw_horizontal_line(x, y, length, color)
+
+#define gfx_mono_draw_vertical_line(x, y, length, color) \
+	gfx_mono_generic_draw_vertical_line(x, y, length, color)
+
+#define gfx_mono_draw_line(x1, y1, x2, y2, color) \
+	gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
+
+#define gfx_mono_draw_rect(x, y, width, height, color) \
+	gfx_mono_generic_draw_rect(x, y, width, height, color)
+
+#define gfx_mono_draw_filled_rect(x, y, width, height, color) \
+	gfx_mono_generic_draw_filled_rect(x, y, width, height, \
+		color)
+
+#define gfx_mono_draw_circle(x, y, radius, color, octant_mask) \
+	gfx_mono_generic_draw_circle(x, y, radius, color, \
+		octant_mask)
+
+#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask)	\
+	gfx_mono_generic_draw_filled_circle(x, y, radius, \
+		color, quadrant_mask)
+
+#define gfx_mono_put_bitmap(bitmap, x, y) \
+	gfx_mono_generic_put_bitmap(bitmap, x, y)
+
+#define gfx_mono_draw_pixel(x, y, color) \
+	gfx_mono_framebuffer_draw_pixel(x, y, color)
+
+#define gfx_mono_get_pixel(x, y) \
+	gfx_mono_framebuffer_get_pixel(x, y)
+
+#define gfx_mono_init()	\
+	gfx_mono_null_init()
+
+#define gfx_mono_put_page(data, page, column, width) \
+	gfx_mono_framebuffer_put_page(data, page, column, width)
+
+#define gfx_mono_get_page(data, page, column, width) \
+	gfx_mono_framebuffer_get_page(data, page, column, width)
+
+#define gfx_mono_put_byte(page, column, data) \
+	gfx_mono_framebuffer_put_byte(page, column, data)
+
+#define gfx_mono_get_byte(page, column)	\
+	gfx_mono_framebuffer_get_byte(page, column)
+
+#define gfx_mono_mask_byte(page, column, pixel_mask, color) \
+	gfx_mono_framebuffer_mask_byte(page, column, pixel_mask, color)
+
+#define gfx_mono_put_framebuffer() \
+	;
+
+void gfx_mono_null_init(void);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_NULL_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_screen_dump.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_screen_dump.h
new file mode 100644
index 0000000000..87ed584078
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_screen_dump.h
@@ -0,0 +1,158 @@
+/**
+ * \file
+ *
+ * \brief Service for performing a screen dump to XPM image file
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GFX_MONO_SCREEN_DUMP_H_INCLUDED
+#define GFX_MONO_SCREEN_DUMP_H_INCLUDED
+
+#include <serial.h>
+#include <gfx_mono.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_screen_dump XPM USART Screendump functions
+ *
+ * This service will add the possibility to dump the LCD screen to the USART
+ * using the XPM file format.
+ *
+ * Before using the screen dump function one should make sure that one has
+ * performed initialization of this service by calling
+ * \ref gfx_mono_screen_dump_init() to set up which USART to use. One should
+ * also make sure that one has initialized the gfx mono driver
+ * \ref gfx_mono_init() which will produce the screen buffer that is dumped
+ * trough the USART.
+ *
+ * \section asfdoc_common2_screen_dump_dependencies Dependencies
+ * This driver depends on the following modules:
+ * - asfdoc_samd20_sercom_spi_group
+ * @{
+ */
+
+/** TODO: This define should be fetched from the GFX display header file. */
+#define LCD_PAGE_HEIGHT 8
+#define GFX_MONO_LCD_PAGE_COUNT GFX_MONO_LCD_HEIGHT / LCD_PAGE_HEIGHT
+
+/* Define used for stringifying number defines */
+#define str(s) # s
+
+#define _XPM_HEADER(w, h) "/* XPM */\r\n" \
+	"static char * asf_screen_dump[] = {\r\n" \
+	"\"" str(w) " " str(h) " 2 1\",\r\n" \
+	"\"   c #FFFFFF\",\r\n"	\
+	"\".  c #000000\",\r\n"
+
+#define XPM_HEADER _XPM_HEADER(GFX_MONO_LCD_WIDTH, GFX_MONO_LCD_HEIGHT)
+
+#if UC3
+typedef avr32_usart_t dump_usart_t;
+#elif XMEGA
+typedef USART_t dump_usart_t;
+#endif
+
+/** storage for the usart to use when dumping data */
+dump_usart_t *dump_usart;
+
+static const uint8_t xpm_header[] = XPM_HEADER;
+
+/**
+ * \brief Init the framebuffer dump function
+ *
+ * \param[in] usart   pointer to the USART to use for dumping the image
+ * \param[in] options pointer to the USART options, see documentation
+ *
+ */
+static inline void gfx_mono_screen_dump_init(dump_usart_t *usart,
+		const usart_serial_options_t *options)
+{
+	dump_usart = usart;
+	usart_serial_init(usart, options);
+}
+
+/**
+ * \brief Function for dumping a LCD framebuffer
+ *
+ * This function will dump a framebuffer to a UART in XPM file format.
+ */
+static inline void gfx_mono_screen_dump(void)
+{
+	uint8_t page_buffer[GFX_MONO_LCD_WIDTH];
+	/* wait to receive a character on UART before sending */
+	uint8_t dummy;
+	usart_serial_getchar(dump_usart, &dummy);
+
+	/* write the XPM header */
+	usart_serial_write_packet(dump_usart, xpm_header,
+			(sizeof(xpm_header) - 1));
+
+	for (uint8_t page = 0; page < GFX_MONO_LCD_PAGE_COUNT; ++page) {
+		gfx_mono_get_page(page_buffer, page, 0, GFX_MONO_LCD_WIDTH);
+		for (uint8_t row = 0; row < LCD_PAGE_HEIGHT; ++row) {
+			usart_putchar(dump_usart, '"');
+			for (uint16_t column = 0; column < GFX_MONO_LCD_WIDTH;
+					++column) {
+				if ((page_buffer[column] & (0x01 << row)) !=
+						0x00) {
+					usart_putchar(dump_usart, '.');
+				} else {
+					usart_putchar(dump_usart, ' ');
+				}
+			}
+			usart_serial_write_packet(dump_usart,
+					(uint8_t *)"\",\r\n", 4);
+		}
+	}
+	usart_serial_write_packet(dump_usart, (uint8_t *)"};\r\n", 4);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_SCREEN_DUMP_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.c
new file mode 100644
index 0000000000..5978f5c5b2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.c
@@ -0,0 +1,697 @@
+/**
+ * \file
+ *
+ * \brief Spin control widget
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "sysfont.h"
+#include "stdio.h"
+#include "gfx_mono.h"
+#include "gfx_mono_spinctrl.h"
+
+PROGMEM_DECLARE(gfx_mono_color_t, spin_indicator_data[]) = {
+	GFX_MONO_SPINCTRL_SPIN_INDICATOR_BITMAP
+};
+
+PROGMEM_DECLARE(gfx_mono_color_t, indicator_data[]) = {
+	GFX_MONO_SPINCTRL_INDICATOR_BITMAP
+};
+
+struct gfx_mono_bitmap gfx_mono_spinctrl_bitmap_spin_indicator = {
+	.height = GFX_MONO_SPINCTRL_SPIN_INDICATOR_HEIGHT,
+	.width = GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+	.type = GFX_MONO_BITMAP_PROGMEM,
+	.data.progmem = spin_indicator_data
+};
+
+struct gfx_mono_bitmap gfx_mono_spinctrl_bitmap_indicator = {
+	.height = GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
+	.width = GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+	.type = GFX_MONO_BITMAP_PROGMEM,
+	.data.progmem = indicator_data
+};
+
+/**
+ * \brief Draw or delete indicator arrow in front of spinner
+ *
+ * \param[in] *spinner initialized gfx_mono_spinctrl struct
+ * \param[in] draw     true on draw, false on delete
+ */
+static void gfx_mono_spinctrl_draw_indicator(struct gfx_mono_spinctrl *spinner,
+		bool draw)
+{
+	if (draw) {
+		gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_indicator, 0,
+				spinner->y);
+	} else {
+		gfx_mono_draw_filled_rect(0, spinner->y,
+				GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+				GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
+				GFX_PIXEL_CLR);
+	}
+}
+
+/**
+ * \brief Draw or delete indicator in front of spinner data
+ *
+ * \param[in] spinner  pointer to initialized gfx_mono_spinctrl struct
+ * \param[in] draw     true on draw, false on delete
+ */
+static void gfx_mono_spinctrl_draw_spin_indicator(struct gfx_mono_spinctrl
+		*spinner, bool draw)
+{
+	if (draw) {
+		gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_spin_indicator,
+				GFX_MONO_LCD_WIDTH - GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+				spinner->y);
+	} else {
+		gfx_mono_draw_filled_rect(GFX_MONO_LCD_WIDTH -
+				GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+				spinner->y,
+				GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+				GFX_MONO_SPINCTRL_SPIN_INDICATOR_HEIGHT,
+				GFX_PIXEL_CLR);
+	}
+}
+
+/**
+ * \brief Draw OK button at bottom of screen
+ *
+ * This function draws an OK button at the bottom of the screen. It will
+ * also draw an indicator arrow in front of the button if the indicator bool
+ * is true. If the draw bool is false, the OK button will be deleted, and if
+ * the indicator bool is false, the indicator will be deleted.
+ *
+ * \param[in] draw       true on draw, false on delete
+ * \param[in] indicator  true on draw indicator, false on delete
+ */
+static void gfx_mono_spinctrl_draw_button(bool draw, bool indicator)
+{
+	uint8_t width;
+	uint8_t height;
+	uint8_t offset;
+	char string_buf[22];
+
+	/* Clear bottom line */
+	gfx_mono_draw_filled_rect(0,
+			(SYSFONT_HEIGHT + 1) *
+			GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
+			GFX_MONO_LCD_WIDTH, SYSFONT_HEIGHT, GFX_PIXEL_CLR);
+
+	snprintf(string_buf, sizeof(string_buf), "OK");
+	gfx_mono_get_string_bounding_box(string_buf, &sysfont, &width, &height);
+	offset = (GFX_MONO_LCD_WIDTH - width) / 2;
+
+	if (draw) {
+		/* Draw OK button in the middle of the last line */
+		gfx_mono_draw_string(string_buf, offset,
+				(SYSFONT_HEIGHT + 1) *
+				GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
+				&sysfont);
+		if (indicator) {
+			/* Draw indicator arrow in front of button */
+			gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_indicator,
+					offset - GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+					(SYSFONT_HEIGHT + 1) *
+					GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION);
+		} else {
+			/* Delete indicator */
+			gfx_mono_draw_filled_rect(offset -
+					GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+					(SYSFONT_HEIGHT + 1) *
+					GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
+					GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+					GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
+					GFX_PIXEL_CLR);
+		}
+	} else {
+		/* Delete OK button */
+		gfx_mono_draw_filled_rect(
+				offset - GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+				(SYSFONT_HEIGHT + 1) *
+				GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION, 20,
+				SYSFONT_HEIGHT, GFX_PIXEL_CLR);
+	}
+}
+
+/**
+ * \brief Draw spinner at its position.
+ *
+ * This function draws a spinner at its position.
+ * The title of the spinner is only drawn if the redraw option is set.
+ * If the spinner is in focus, arrows will be drawn next to the spinner value
+ * to indicate that it is spinnable.
+ *
+ * \param[in] spinner  pointer to initialized gfx_mono_spinctrl struct
+ * \param[in] redraw   true if title of spinner should be drawn
+ */
+void gfx_mono_spinctrl_draw(struct gfx_mono_spinctrl *spinner, bool redraw)
+{
+	char string_buf[GFX_MONO_SPINCTRL_INT_SPINNER_WIDTH];
+	uint8_t index;
+	uint8_t offset;
+
+	if (redraw) {
+		/* Clear line */
+		gfx_mono_draw_filled_rect(0, spinner->y, GFX_MONO_LCD_WIDTH,
+				SYSFONT_HEIGHT, GFX_PIXEL_CLR);
+		/* Draw title */
+		gfx_mono_draw_progmem_string((char PROGMEM_PTR_T)spinner->title,
+				GFX_MONO_SPINCTRL_INDICATOR_WIDTH + 1,
+				spinner->y, &sysfont);
+	}
+
+	if (spinner->in_focus) {
+		gfx_mono_spinctrl_draw_spin_indicator(spinner, true);
+	} else {
+		gfx_mono_spinctrl_draw_spin_indicator(spinner, false);
+	}
+
+	if (spinner->datatype == SPINTYPE_INTEGER) {
+		offset = GFX_MONO_LCD_WIDTH -
+				(SYSFONT_WIDTH *
+				GFX_MONO_SPINCTRL_INT_SPINNER_WIDTH);
+		snprintf(string_buf, sizeof(string_buf), "%d",
+				spinner->integer_data);
+		/* Delete previous spinner data */
+		gfx_mono_draw_filled_rect(offset, spinner->y,
+				GFX_MONO_LCD_WIDTH - offset -
+				GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+				SYSFONT_HEIGHT,
+				GFX_PIXEL_CLR);
+		/* Draw integer data */
+		gfx_mono_draw_string(string_buf, offset, spinner->y, &sysfont);
+	} else if (spinner->datatype == SPINTYPE_STRING) {
+		index = spinner->strings.index;
+		offset = GFX_MONO_LCD_WIDTH -
+				(SYSFONT_WIDTH *
+				GFX_MONO_SPINCTRL_STRING_SPINNER_WIDTH);
+
+		/* Delete previous spinner data */
+		gfx_mono_draw_filled_rect(offset, spinner->y,
+				GFX_MONO_LCD_WIDTH - offset -
+				GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+				SYSFONT_HEIGHT,
+				GFX_PIXEL_CLR);
+
+		/* Draw string data */
+		gfx_mono_draw_progmem_string(
+				(char PROGMEM_PTR_T)spinner->strings.data[index], offset,
+				spinner->y, &sysfont);
+	}
+}
+
+/**
+ * \brief Initialize a spinner.
+ *
+ * This function initializes a spinner to either
+ * \ref gfx_mono_spinctrl_type_t "SPINTYPE_STRING" spinner that spins through
+ * the strings in a \ref PROGMEM_STRING_T or a
+ * \ref gfx_mono_spinctrl_type_t "SPINTYPE_INTEGER" spinner that spins through
+ * integers.
+ * If the spinner type is SPINTYPE_INTEGER, it will spin from lower_limit to
+ * upper_limit.
+ * If the spinner type is SPINTYPE_STRING, a pointer to a PROGMEM_STRING_T must
+ * be provided, and the spinner will spin through the strings starting at
+ * index lower_limit ending at index upper_limit.
+ * The y parameter specifies where to place the spinner on the screen, but is
+ * overwritten if the spinner is put in a spincollection.
+ *
+ * \param[out] spinner      pointer to initialized gfx_mono_spinctrl struct
+ * \param[in] datatype     typer of spinner, integer or string
+ * \param[in] title        title of spinner
+ * \param[in] data         pointer to progmem string array if datatype is string.
+ *                     NULL if datatype is integer.
+ * \param[in] lower_limit  lower limit and start value of spinner's data
+ * \param[in] upper_limit  upper limit of spinner's data
+ * \param[in] y            y position of spinner
+ */
+void gfx_mono_spinctrl_init(struct gfx_mono_spinctrl *spinner,
+		gfx_mono_spinctrl_type_t datatype, PROGMEM_STRING_T title,
+		PROGMEM_STRING_T *data, int16_t lower_limit,
+		int16_t upper_limit,
+		gfx_coord_t y)
+{
+	/* Initialization of spinner parameters */
+	spinner->title = title;
+	spinner->datatype = datatype;
+	spinner->lower_limit = lower_limit;
+	spinner->upper_limit = upper_limit;
+	spinner->y = y;
+	spinner->in_focus = false;
+	spinner->last_saved_value = spinner->lower_limit;
+
+	if (datatype == SPINTYPE_STRING) {
+		spinner->strings.data = data;
+		spinner->strings.index = lower_limit;
+	} else {
+		spinner->integer_data = lower_limit;
+	}
+}
+
+/**
+ * \brief Initialize a spincollection.
+ *
+ * This function initializes a spincollection to which spinners can be added.
+ *
+ * \param[out] collection pointer to gfx_mono_spinctrl_spincollection to Initialize
+ */
+void gfx_mono_spinctrl_spincollection_init(struct
+		gfx_mono_spinctrl_spincollection *collection)
+{
+	collection->active_spinner = false;
+	collection->current_selection = 0;
+	collection->number_of_spinners = 0;
+	collection->init = true;
+}
+
+/**
+ * \brief Add spinner to spincollection
+ *
+ * This function adds an initialized spinner to a spincollection and positions
+ * it below any other spinners in the spincollection on the screen. The
+ * spinners in the spincollection are linked together and number of spinners is
+ * updated.
+ * It is not possible to add more spinners than
+ * \ref GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION "maximum number of
+ * spinners in a spincollection".
+ *
+ * \param[in] spinner   pointer to initialized gfx_mono_spinctrl struct to add
+ *                      to collection
+ * \param[in] spinners  pointer to initialized gfx_mono_spinctrl_spincollection
+ *                      struct
+ *
+ */
+void gfx_mono_spinctrl_spincollection_add_spinner(struct
+		gfx_mono_spinctrl *spinner,
+		struct gfx_mono_spinctrl_spincollection *spinners)
+{
+	uint8_t i;
+	struct gfx_mono_spinctrl *lastspinner;
+
+	/* Do not add more spinner elements than maximum number of spinners */
+	if (spinners->number_of_spinners >=
+			GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION) {
+		return;
+	}
+
+	/* Place new spinner below previous spinners on screen */
+	spinner->y = (SYSFONT_HEIGHT + 1) * spinners->number_of_spinners;
+
+	/* Add pointer to the spinner in spincollection if empty */
+	if (spinners->number_of_spinners == 0) {
+		spinners->collection = spinner;
+	} else {
+		lastspinner = spinners->collection;
+		for (i = 1; i < spinners->number_of_spinners; i++) {
+			lastspinner = lastspinner->next;
+		}
+		/* Link the new spinner to the current last spinner in the
+		 * collection */
+		lastspinner->next = spinner;
+		/* Link the current last spinner as previous spinner for new
+		 * spinner */
+		spinner->prev = lastspinner;
+	}
+
+	/* Set added spinner as last spinner in collection */
+	spinners->collection_last = spinner;
+	/* Update number of spinners in collection */
+	spinners->number_of_spinners++;
+}
+
+/**
+ * \brief Show spincollection
+ *
+ * This function draws all the spinners in a spincollection to the screen,
+ * together with an OK button at the bottom. It also draws an indicator arrow
+ * in front of the top spinner.
+ *
+ * \param[in] spinners pointer to initialized spincollection to display
+ */
+void gfx_mono_spinctrl_spincollection_show(struct
+		gfx_mono_spinctrl_spincollection *spinners)
+{
+	uint8_t i;
+	struct gfx_mono_spinctrl *iterator;
+
+	/* Clear screen */
+	gfx_mono_draw_filled_rect(0, 0, GFX_MONO_LCD_WIDTH, GFX_MONO_LCD_HEIGHT,
+			GFX_PIXEL_CLR);
+
+	/* Make sure there are spinners in the collection */
+	if (spinners->number_of_spinners == 0) {
+		return;
+	}
+
+	/* Draw spinners on screen */
+	iterator = spinners->collection;
+	for (i = 0; i < spinners->number_of_spinners; i++) {
+		gfx_mono_spinctrl_draw(iterator, true);
+		iterator = iterator->next;
+	}
+	/* Draw OK button at bottom of screen */
+	gfx_mono_spinctrl_draw_button(true, false);
+	/* Draw indicator arrow in front of first spinner */
+	gfx_mono_spinctrl_draw_indicator(spinners->collection, true);
+}
+
+/**
+ * \brief Step up spinner data
+ *
+ * This function steps up the data, making sure it does not go
+ * beyond the upper limit. Wraps around if it does.
+ *
+ * \param[in] spinner pointer to initialized spinner.
+ */
+static void gfx_mono_spinctrl_step_up(struct gfx_mono_spinctrl *spinner)
+{
+	/* Check if spinner type is integer or string, increment integer data or
+	 * move to next string index.
+	 */
+	if (spinner->datatype == SPINTYPE_INTEGER) {
+		if (spinner->integer_data < spinner->upper_limit) {
+			spinner->integer_data++;
+		} else {
+			spinner->integer_data = spinner->lower_limit;
+		}
+	} else if (spinner->datatype == SPINTYPE_STRING) {
+		if (spinner->strings.index < spinner->upper_limit) {
+			spinner->strings.index++;
+		} else {
+			(spinner->strings.index) = spinner->lower_limit;
+		}
+	}
+}
+
+/**
+ * \brief Step down spinner data
+ *
+ * * This function steps down the data, making sure it does not go
+ * below the lower limit. Wraps around if it does.
+ *
+ * \param[in] spinner pointer to initialized spinner.
+ */
+static void gfx_mono_spinctrl_step_down(struct gfx_mono_spinctrl *spinner)
+{
+	/* Check if spinner type is integer or string, increment integer data,
+	 * move to next string index.
+	 */
+	if (spinner->datatype == SPINTYPE_INTEGER) {
+		if (spinner->integer_data > spinner->lower_limit) {
+			spinner->integer_data--;
+		} else {
+			spinner->integer_data = spinner->upper_limit;
+		}
+	} else if (spinner->datatype == SPINTYPE_STRING) {
+		if (spinner->strings.index > (spinner->lower_limit)) {
+			spinner->strings.index--;
+		} else {
+			spinner->strings.index = spinner->upper_limit;
+		}
+	}
+}
+
+/**
+ * \brief Update single spinner depending on input.
+ *
+ * \param[in] spinner pointer to initialized spinner.
+ * \param[in] keycode  keycode to process
+ *
+ * \retval selected            selected spinner value
+ * \retval GFX_MONO_SPINCTRL_EVENT_IDLE spinner spinning
+ * \retval GFX_MONO_SPINCTRL_EVENT_BACK spinner deselected
+ */
+int16_t gfx_mono_spinctrl_process_key(struct gfx_mono_spinctrl *spinner,
+		uint8_t keycode)
+{
+	switch (keycode) {
+	case GFX_MONO_SPINCTRL_KEYCODE_DOWN:
+		if (spinner->in_focus) {
+			gfx_mono_spinctrl_step_down(spinner);
+			/* Update spinner on display */
+			gfx_mono_spinctrl_draw(spinner, false);
+		}
+
+		/* Nothing selected yet */
+		return GFX_MONO_SPINCTRL_EVENT_IDLE;
+
+	case GFX_MONO_SPINCTRL_KEYCODE_UP:
+		if (spinner->in_focus) {
+			gfx_mono_spinctrl_step_up(spinner);
+			/* Update spinner on display */
+			gfx_mono_spinctrl_draw(spinner, false);
+		}
+
+		/* Nothing selected yet */
+		return GFX_MONO_SPINCTRL_EVENT_IDLE;
+
+	case GFX_MONO_SPINCTRL_KEYCODE_ENTER:
+		if (spinner->in_focus) {
+			if (spinner->datatype == SPINTYPE_INTEGER) {
+				spinner->in_focus = false;
+				gfx_mono_spinctrl_draw(spinner, false);
+				/* Store saved value in case of aborting spinner
+				 * later */
+				spinner->last_saved_value
+					= spinner->integer_data;
+				/* Got what we want. Return selection. */
+				return spinner->integer_data;
+			} else if (spinner->datatype == SPINTYPE_STRING) {
+				spinner->in_focus = false;
+				gfx_mono_spinctrl_draw(spinner, false);
+				/* Store saved value in case of aborting spinner
+				 * later */
+				spinner->last_saved_value
+					= spinner->strings.index;
+				/* Got what we want. Return selection. */
+				return spinner->strings.index;
+			}
+		} else {
+			/* Spinner selected */
+			spinner->in_focus = true;
+			gfx_mono_spinctrl_draw(spinner, false);
+			return GFX_MONO_SPINCTRL_EVENT_IDLE;
+		}
+
+	case GFX_MONO_SPINCTRL_KEYCODE_BACK:
+		/* User pressed "back" key, */
+		spinner->in_focus = false;
+		/* Spinner choice aborted, show last saved value instead */
+		if (spinner->datatype == SPINTYPE_INTEGER) {
+			spinner->integer_data = spinner->last_saved_value;
+		} else if (spinner->datatype == SPINTYPE_STRING) {
+			spinner->strings.index = spinner->last_saved_value;
+		}
+
+		gfx_mono_spinctrl_draw(spinner, false);
+		return GFX_MONO_SPINCTRL_EVENT_BACK;
+
+	default:
+		/* Unknown key event */
+		return GFX_MONO_SPINCTRL_EVENT_IDLE;
+	}
+}
+
+/**
+ * \brief Update spincollection on screen depending on input
+ *
+ * This function returns \ref GFX_MONO_SPINCTRL_EVENT_FINISH if user has
+ * pressed the OK button. The spinner choices can then be extracted from the
+ * results array. If a spinner is of type SPINTYPE_STRING, the index of the
+ * progmem string will be stored in the results array, else the selected
+ * integer value will be stored.
+ * The choice from the first spinner added to the spincollection will be stored
+ * at index 0 in the results array, the second at index 1 and so on.
+ * If user has pressed the back button, \ref GFX_MONO_SPINCTRL_EVENT_BACK is
+ * returned, signalling that the application should be cancelled.
+ *
+ * \param[in] spinners       pointer to initialized
+ *                       gfx_mono_spinctrl_spincollection
+ * \param[in] keycode        keycode to process
+ * \param[in] results        array to store results from the spinners, must be of
+ *                       same length as number of spinners
+ *
+ * \retval GFX_MONO_SPINCTRL_EVENT_FINISH  user pressed ok button
+ * \retval GFX_MONO_SPINCTRL_EVENT_BACK    user cancelled
+ * \retval GFX_MONO_SPINCTRL_EVENT_IDLE    user is navigating in spincollection
+ */
+int16_t gfx_mono_spinctrl_spincollection_process_key(struct
+		gfx_mono_spinctrl_spincollection *spinners, uint8_t keycode,
+		int16_t results[])
+{
+	uint8_t i;
+	struct gfx_mono_spinctrl *iterator;
+
+	/* Make sure there are spinners in the collection, if not, cancel */
+	if (spinners->number_of_spinners == 0) {
+		return GFX_MONO_SPINCTRL_EVENT_BACK;
+	}
+
+	/* Store initial values in results array first time function is run */
+	if (spinners->init) {
+		iterator = spinners->collection;
+		for (i = 0; i < spinners->number_of_spinners; i++) {
+			if (iterator->datatype == SPINTYPE_INTEGER) {
+				results[i] = iterator->integer_data;
+			} else {
+				results[i] = iterator->strings.index;
+			}
+
+			iterator = iterator->next;
+		}
+		spinners->init = false;
+	}
+
+	/* Find current spinner selection */
+	iterator = spinners->collection;
+	if (spinners->current_selection != GFX_MONO_SPINCTRL_BUTTON) {
+		for (i = 0; i < spinners->current_selection; i++) {
+			iterator = iterator->next;
+		}
+	}
+
+	if (spinners->active_spinner) {
+		/* Process chosen spinner */
+		spinners->selection = gfx_mono_spinctrl_process_key(iterator,
+				keycode);
+		if (spinners->selection == GFX_MONO_SPINCTRL_EVENT_BACK) {
+			/* User has exited spinner without saving the result */
+			spinners->active_spinner = false;
+		} else if (spinners->selection !=
+				GFX_MONO_SPINCTRL_EVENT_IDLE) {
+			/* Value selected, store in array */
+			results[spinners->current_selection]
+				= spinners->selection;
+			/* Step out of spinner and into spincollection */
+			spinners->active_spinner = false;
+		}
+
+		return GFX_MONO_SPINCTRL_EVENT_IDLE;
+	} else {
+		switch (keycode) {
+		case GFX_MONO_SPINCTRL_KEYCODE_DOWN:
+			if (spinners->current_selection ==
+					GFX_MONO_SPINCTRL_BUTTON) {
+				spinners->current_selection = 0;
+				/* Delete indicator arrow in front of button */
+				gfx_mono_spinctrl_draw_button(true, false);
+				/* Draw indicator arrow in front of first
+				 * spinner */
+				gfx_mono_spinctrl_draw_indicator(iterator,
+						true);
+			} else if (spinners->current_selection <
+					spinners->number_of_spinners - 1) {
+				/* Delete indicator arrow */
+				gfx_mono_spinctrl_draw_indicator(iterator,
+						false);
+				spinners->current_selection++;
+				/* Draw indicator arrow in front of new spinner */
+				gfx_mono_spinctrl_draw_indicator(iterator->next,
+						true);
+			} else {
+				/* Delete indicator arrow */
+				gfx_mono_spinctrl_draw_indicator(iterator,
+						false);
+				spinners->current_selection
+					= GFX_MONO_SPINCTRL_BUTTON;
+				/* Draw indicator arrow in front of button */
+				gfx_mono_spinctrl_draw_button(true, true);
+			}
+
+			return GFX_MONO_SPINCTRL_EVENT_IDLE;
+
+		case GFX_MONO_SPINCTRL_KEYCODE_UP:
+			if (spinners->current_selection ==
+					GFX_MONO_SPINCTRL_BUTTON) {
+				/* Delete indicator arrow in front of button */
+				gfx_mono_spinctrl_draw_button(true, false);
+				spinners->current_selection
+					= spinners->number_of_spinners - 1;
+				/* Draw indicator arrow in front of new spinner */
+				gfx_mono_spinctrl_draw_indicator(
+						spinners->collection_last,
+						true);
+			} else if (spinners->current_selection > 0) {
+				/* Delete indicator arrow */
+				gfx_mono_spinctrl_draw_indicator(iterator,
+						false);
+				spinners->current_selection--;
+				/* Draw indicator arrow in front of new spinner */
+				gfx_mono_spinctrl_draw_indicator(iterator->prev,
+						true);
+			} else {
+				/* Delete indicator arrow */
+				gfx_mono_spinctrl_draw_indicator(iterator,
+						false);
+				spinners->current_selection
+					= GFX_MONO_SPINCTRL_BUTTON;
+				/* Draw indicator arrow in front of button */
+				gfx_mono_spinctrl_draw_button(true, true);
+			}
+
+			return GFX_MONO_SPINCTRL_EVENT_IDLE;
+
+		case GFX_MONO_SPINCTRL_KEYCODE_ENTER:
+			if (spinners->current_selection ==
+					GFX_MONO_SPINCTRL_BUTTON) {
+				/* Finished with all selections, return */
+				return GFX_MONO_SPINCTRL_EVENT_FINISH;
+			} else {
+				/* Spinner selected, send next keycode directly
+				 * to spinner */
+				gfx_mono_spinctrl_process_key(iterator,
+						keycode);
+				spinners->active_spinner = true;
+				return GFX_MONO_SPINCTRL_EVENT_IDLE;
+			}
+
+		case GFX_MONO_SPINCTRL_KEYCODE_BACK:
+			/* User pressed "back" key, */
+			return GFX_MONO_SPINCTRL_EVENT_BACK;
+
+		default:
+			/* Unknown key event */
+			return GFX_MONO_SPINCTRL_EVENT_IDLE;
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.h
new file mode 100644
index 0000000000..968222334a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.h
@@ -0,0 +1,251 @@
+/**
+ * \file
+ *
+ * \brief Spin control widget
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GFX_MONO_SPINCTRL_H
+#define GFX_MONO_SPINCTRL_H
+
+#include "gfx_mono.h"
+#include "conf_spinctrl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_spinctrl Spinner widget for monochrome graphical displays
+ *
+ * This module provides a spinner widget system for monochrome graphical
+ * displays.
+ *
+ * There is support for having one single spinner on the screen, or a
+ * collection of spinners.
+ *
+ * Typical flow of an application using the spincollection system:
+ *
+ * 1) Define spinners.\n
+ * 2) Initialize each spinners with \ref gfx_mono_spinctrl_init.\n
+ * 3) Define a spincollection struct and initialize it with
+ * \ref gfx_mono_spinctrl_spincollection_init.\n
+ * 4) Add spinners to spincollection with
+ * \ref gfx_mono_spinctrl_spincollection_add_spinner.\n
+ * 5) Draw spincollection to screen with
+ * \ref gfx_mono_spinctrl_spincollection_show.\n
+ * 6) Define a result array to store the spinner choices.\n
+ * 7) Update spinners and result array with user input using function
+ * \ref gfx_mono_spinctrl_spincollection_process_key.\n
+ * 8) Interpret \ref gfx_mono_spinctrl_spincollection_process_key return
+ * value.\n
+ * 9) Go to 7.\n
+ *
+ * Typical flow of an application using a single spinner:
+ *
+ * 1) Define spinner.\n
+ * 2) Initialize the spinners with \ref gfx_mono_spinctrl_init with preferred y
+ * position on screen.\n
+ * 3) Draw spinner to screen with \ref gfx_mono_spinctrl_draw.\n
+ * 4) Update spinner with user input using function
+ * \ref gfx_mono_spinctrl_process_key.\n
+ * 5) Interpret \ref gfx_mono_spinctrl_process_key return value.\n
+ * 6) Go to 4.\n
+ *
+ * Before the spinners can be updated, you need input from the user. Methods
+ * for getting input is not part of the spinner widget.
+ *
+ * \note The spinners will be linked together when added to a spincollection,
+ * and can therefore not be used in two spincollections at the same time.
+ *
+ * As soon as input is received, inform the spincollection system or the single
+ * spinner using the \ref gfx_mono_spinctrl_spincollection_process_key function
+ * or the \ref gfx_mono_spinctrl_process_key function.
+ * These functions will then return a status code and act depending on the
+ * given keycode:
+ *
+ * GFX_MONO_SPINCTRL_KEYCODE_DOWN : Change selection to next spinner value or
+ * to next spinner or OK button in a spincollection.
+ *
+ * GFX_MONO_SPINCTRL_KEYCODE_UP : Change selection to previous spinner value
+ * or to previous spinner or OK button in a spincollection.
+ *
+ * GFX_MONO_SPINCTRL_KEYCODE_ENTER : Select spinner value or select spinner or
+ * OK button in a spincollection.
+ *
+ * GFX_MONO_SPINCTRL_KEYCODE_BACK : Deselect spinner or cancel spincollection
+ * application.
+ *
+ * The value of the keycodes used are defined in conf_spinctrl.h. These values
+ * can be changed if needed.
+ *
+ * The graphical indicators used to indicate spinner selections are defined in
+ * conf_spinctrl.h. These indicators can be changed if needed.
+ * @{
+ */
+
+/** Spinner idle event */
+#define GFX_MONO_SPINCTRL_EVENT_IDLE                0xFF
+/** Spinner back button pressed event */
+#define GFX_MONO_SPINCTRL_EVENT_BACK                0xFE
+/** Spinner ok button pressed event */
+#define GFX_MONO_SPINCTRL_EVENT_FINISH              0xFD
+
+/** OK button */
+#define GFX_MONO_SPINCTRL_BUTTON        0xFF
+
+/** Maximum number of spinner elements on display */
+#define GFX_MONO_SPINCTRL_ELEMENTS_PER_SCREEN \
+	((GFX_MONO_LCD_HEIGHT / SYSFONT_LINESPACING) - 1)
+
+/**
+ * Maximum numbers of spinner elements in a spincollection - limited to
+ * one screen.
+ */
+#define GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION \
+	GFX_MONO_SPINCTRL_ELEMENTS_PER_SCREEN
+
+/** Width of string spinner choices */
+#define GFX_MONO_SPINCTRL_STRING_SPINNER_WIDTH 9
+/** Width of integer spinner choices */
+#define GFX_MONO_SPINCTRL_INT_SPINNER_WIDTH    9
+
+/** Enum to specify what kind of data spinner should spin */
+typedef enum gfx_mono_spinctrl_type_enum {
+	SPINTYPE_STRING,
+	SPINTYPE_INTEGER
+} gfx_mono_spinctrl_type_t;
+
+/** String struct */
+struct gfx_mono_spinctrl_string {
+	/** Pointer to progmem strings to spin through
+	 * \note Each string must be shorter than
+	 * \ref  GFX_MONO_SPINCTRL_STRING_SPINNER_WIDTH characters.
+	 * If not, printing it to the screen will corrupt the spinner
+	 * appearance.
+	 */
+	PROGMEM_STRING_T *data;
+	/** Index in string array */
+	uint8_t index;
+};
+
+/** Spin control struct */
+struct gfx_mono_spinctrl {
+	/** Spinner title */
+	PROGMEM_STRING_T title;
+	/** Type of data to spin */
+	gfx_mono_spinctrl_type_t datatype;
+	/** Spinner data, depends on spinner datatype. */
+	union {
+		/** Spinner strings and index */
+		struct gfx_mono_spinctrl_string strings;
+		/** Spinner integer data */
+		int16_t integer_data;
+	};
+	/** Variable to store the last selected spinner value */
+	uint16_t last_saved_value;
+
+	/**
+	 * Lower limit for spinning, must be positive and fit in uin8_t for
+	 * spinner type SPINTYPE_STRING
+	 */
+	int16_t lower_limit;
+
+	/**
+	 * Upper limit for spinning, must be positive and fit in uin8_t for
+	 * spinner type SPINTYPE_STRING
+	 */
+	int16_t upper_limit;
+	/** Y coordinate for placement of spinner on screen */
+	gfx_coord_t y;
+	/** Boolean to tell if spinner is in focus or not */
+	bool in_focus;
+	/** Pointer to next spinner in a spincollection */
+	struct gfx_mono_spinctrl *next;
+	/** Pointer to previous spinner in a spincollection */
+	struct gfx_mono_spinctrl *prev;
+};
+
+/** Collection of spinners struct */
+struct gfx_mono_spinctrl_spincollection {
+	/** Pointer to the first spinner in the collection */
+	struct gfx_mono_spinctrl *collection;
+	/** Pointer to the last spinner in the collection */
+	struct gfx_mono_spinctrl *collection_last;
+	/** Number of spinners in collection */
+	uint8_t number_of_spinners;
+	/** Current spinner/button */
+	uint8_t current_selection;
+	/** Return value from selected spinner */
+	uint16_t selection;
+	/** Boolean to tell if input should be sent directly to a spinner */
+	bool active_spinner;
+	/** Boolean to initialize results array when starting key processing */
+	bool init;
+};
+
+void gfx_mono_spinctrl_init(struct gfx_mono_spinctrl *spinner,
+		gfx_mono_spinctrl_type_t datatype, PROGMEM_STRING_T title,
+		PROGMEM_STRING_T *data, int16_t lower_limit,
+		int16_t upper_limit,
+		gfx_coord_t y);
+void gfx_mono_spinctrl_draw(struct gfx_mono_spinctrl *spinner, bool redraw);
+void gfx_mono_spinctrl_spincollection_init(struct
+		gfx_mono_spinctrl_spincollection *collection);
+void gfx_mono_spinctrl_spincollection_add_spinner(struct gfx_mono_spinctrl
+		*spinner, struct gfx_mono_spinctrl_spincollection *spinners);
+void gfx_mono_spinctrl_spincollection_show(struct
+		gfx_mono_spinctrl_spincollection *spinners);
+int16_t gfx_mono_spinctrl_process_key(struct gfx_mono_spinctrl *spinner,
+		uint8_t keycode);
+
+int16_t gfx_mono_spinctrl_spincollection_process_key(struct
+gfx_mono_spinctrl_spincollection *spinners, uint8_t keycode,
+int16_t results[]);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_SPINCTRL_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.c
new file mode 100644
index 0000000000..2fa02379e8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.c
@@ -0,0 +1,425 @@
+/**
+ * \file
+ *
+ * \brief Font and text drawing routines
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "stddef.h"
+#include "assert.h"
+
+#include "gfx_mono.h"
+#include "gfx_mono_text.h"
+#include <asf.h>
+
+#ifndef CONFIG_FONT_PIXELS_PER_BYTE
+# define CONFIG_FONT_PIXELS_PER_BYTE    8
+#endif
+
+#define EXTMEM_BUF_SIZE                 20
+
+#if defined(CONFIG_HUGEMEM) || defined(__DOXYGEN__)
+
+/**
+ * \internal
+ * \brief Helper function that draws a character from a font in hugemem
+ *        to the display
+ *
+ * This function will first calculate the start offset in the font character
+ * data before iterating over the specific character data.
+ *
+ * Only pixels in the character that should be enabled are done so, the caller
+ * is required to prepare the drawing area before printing a character to it.
+ * This is done by the gfx_mono_draw_string() and
+ * gfx_mono_draw_progmem_string() functions.
+ *
+ * \param[in] ch       Character to be drawn
+ * \param[in] x        X coordinate on screen.
+ * \param[in] y        Y coordinate on screen.
+ * \param[in] font     Font to draw character in
+ */
+static void gfx_mono_draw_char_hugemem(const char ch, const gfx_coord_t x,
+		const gfx_coord_t y, const struct font *font)
+{
+	uint8_t i;
+	uint8_t char_row_size;
+	uint8_t glyph_size;
+	uint16_t glyph_data_offset;
+	uint8_t char_buff[EXTMEM_BUF_SIZE];
+	uint8_t buffer_pos;
+	uint8_t rows_left;
+
+	/* Sanity check on parameters, assert if font is NULL. */
+	Assert(font != NULL);
+
+	gfx_coord_t inc_x = x;
+	gfx_coord_t inc_y = y;
+
+	char_row_size = font->width / CONFIG_FONT_PIXELS_PER_BYTE;
+	if (font->width % CONFIG_FONT_PIXELS_PER_BYTE) {
+		char_row_size++;
+	}
+
+	glyph_size = char_row_size * font->height;
+	glyph_data_offset = glyph_size * ((uint8_t)ch - font->first_char);
+	buffer_pos = EXTMEM_BUF_SIZE;
+	rows_left = font->height;
+
+	do {
+		static uint8_t glyph_byte = 0;
+		uint8_t pixelsToDraw = font->width;
+
+		for (i = 0; i < pixelsToDraw; i++) {
+			if (i % CONFIG_FONT_PIXELS_PER_BYTE == 0) {
+				/* Read another byte from hugemem */
+				if (buffer_pos >= EXTMEM_BUF_SIZE) {
+					hugemem_ptr_t source
+						= font->data.hugemem;
+					source = (hugemem_ptr_t)
+							((uint32_t)source +
+							glyph_data_offset);
+
+					hugemem_read_block(char_buff, source,
+							EXTMEM_BUF_SIZE);
+
+					glyph_data_offset += EXTMEM_BUF_SIZE;
+					buffer_pos = 0;
+				}
+
+				glyph_byte = char_buff[buffer_pos];
+				buffer_pos++;
+			}
+
+			/* Draw bit of glyph to screen */
+			if ((glyph_byte & 0x80)) {
+				gfx_mono_draw_pixel(inc_x, inc_y,
+						GFX_PIXEL_SET);
+			}
+
+			inc_x += 1;
+			glyph_byte <<= 1;
+		}
+
+		inc_y += 1;
+		inc_x = x;
+	} while (--rows_left > 0);
+}
+
+#endif
+
+/**
+ * \internal
+ * \brief Helper function that draws a character from a font in progmem
+ *        to the display
+ *
+ * This function will first calculate the start offset in the font character
+ * data before iterating over the specific character data.
+ *
+ * Only pixels in the character that should be enabled are done so, the caller
+ * is required to prepare the drawing area before printing a character to it.
+ * This is done by the gfx_mono_draw_string() and
+ * gfx_mono_draw_progmem_string() functions.
+ *
+ * \param[in] ch       Character to be drawn
+ * \param[in] x        X coordinate on screen.
+ * \param[in] y        Y coordinate on screen.
+ * \param[in] font     Font to draw character in
+ */
+static void gfx_mono_draw_char_progmem(const char ch, const gfx_coord_t x,
+		const gfx_coord_t y, const struct font *font)
+{
+	uint8_t PROGMEM_PTR_T glyph_data;
+	uint16_t glyph_data_offset;
+	uint8_t char_row_size;
+	uint8_t rows_left;
+	uint8_t i;
+
+	/* Sanity check on parameters, assert if font is NULL. */
+	Assert(font != NULL);
+
+	gfx_coord_t inc_x = x;
+	gfx_coord_t inc_y = y;
+
+	char_row_size = font->width / CONFIG_FONT_PIXELS_PER_BYTE;
+	if (font->width % CONFIG_FONT_PIXELS_PER_BYTE) {
+		char_row_size++;
+	}
+
+	glyph_data_offset = char_row_size * font->height *
+			((uint8_t)ch - font->first_char);
+	glyph_data = font->data.progmem + glyph_data_offset;
+	rows_left = font->height;
+
+	do {
+		uint8_t glyph_byte = 0;
+		uint8_t pixelsToDraw = font->width;
+
+		for (i = 0; i < pixelsToDraw; i++) {
+			if (i % CONFIG_FONT_PIXELS_PER_BYTE == 0) {
+				glyph_byte = PROGMEM_READ_BYTE(glyph_data);
+				glyph_data++;
+			}
+
+			if ((glyph_byte & 0x80)) {
+				gfx_mono_draw_pixel(inc_x, inc_y,
+						GFX_PIXEL_SET);
+			}
+
+			inc_x += 1;
+			glyph_byte <<= 1;
+		}
+
+		inc_y += 1;
+		inc_x = x;
+		rows_left--;
+	} while (rows_left > 0);
+}
+
+/**
+ * \brief Draws a character to the display
+ *
+ * \param[in] c        Character to be drawn
+ * \param[in] x        X coordinate on screen.
+ * \param[in] y        Y coordinate on screen.
+ * \param[in] font     Font to draw character in
+ */
+void gfx_mono_draw_char(const char c, const gfx_coord_t x, const gfx_coord_t y,
+		const struct font *font)
+{
+	gfx_mono_draw_filled_rect(x, y, font->width, font->height,
+			GFX_PIXEL_CLR);
+
+	switch (font->type) {
+	case FONT_LOC_PROGMEM:
+		gfx_mono_draw_char_progmem(c, x, y, font);
+		break;
+
+#ifdef CONFIG_HUGEMEM
+	case FONT_LOC_HUGEMEM:
+		gfx_mono_draw_char_hugemem(c, x, y, font);
+		break;
+
+#endif
+	default:
+		/* Unsupported mode, call assert */
+		Assert(false);
+		break;
+	}
+}
+
+/**
+ * \brief Draws a string to the display
+ *
+ * This function will draw a string located in memory to the display.
+ *
+ * \param[in] str       Pointer to string
+ * \param[in] x         X coordinate on screen.
+ * \param[in] y         Y coordinate on screen.
+ * \param[in] font      Font to draw string in
+ */
+void gfx_mono_draw_string(const char *str, gfx_coord_t x, gfx_coord_t y,
+		const struct font *font)
+{
+	/* Save X in order to know where to return to on CR. */
+	const gfx_coord_t start_of_string_position_x = x;
+
+	/* Sanity check on parameters, assert if str or font is NULL. */
+	Assert(str != NULL);
+	Assert(font != NULL);
+
+	/* Draw characters until trailing null byte */
+	do {
+		/* Handle '\n' as newline, draw normal characters. */
+		if (*str == '\n') {
+			x = start_of_string_position_x;
+			y += font->height + 1;
+		} else if (*str == '\r') {
+			/* Skip '\r' characters. */
+		} else {
+			gfx_mono_draw_char(*str, x, y, font);
+			x += font->width;
+		}
+	} while (*(++str));
+}
+
+/**
+ * \brief Draws a string located in program memory to the display
+ *
+ * This function will draw a string located in program memory to the display,
+ * this differs from gfx_mono_draw_string() by using constant string data from
+ * the program memory instead of string data in RAM.
+ *
+ * Using program memory for constant strings will reduce the applications need
+ * for RAM, and thus lower the overall size footprint.
+ *
+ * \param[in] str       Pointer to string located in program memory
+ * \param[in] x         X coordinate on screen.
+ * \param[in] y         Y coordinate on screen.
+ * \param[in] font      Font to draw string in
+ */
+void gfx_mono_draw_progmem_string(char PROGMEM_PTR_T str, gfx_coord_t x,
+		gfx_coord_t y, const struct font *font)
+{
+	char temp_char;
+
+	/* Sanity check on parameters, assert if str or font is NULL. */
+	Assert(str != NULL);
+	Assert(font != NULL);
+
+	/* Save X in order to know where to return to on CR. */
+	const gfx_coord_t start_of_string_position_x = x;
+
+	/* Draw characters until trailing null byte */
+	temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)str);
+
+	while (temp_char) {
+		/* Handle '\n' as newline, draw normal characters. */
+		if (temp_char == '\n') {
+			x = start_of_string_position_x;
+			y += font->height + 1;
+		} else if (temp_char == '\r') {
+			/* Skip '\r' characters. */
+		} else {
+			gfx_mono_draw_char(temp_char, x, y, font);
+			x += font->width;
+		}
+
+		temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)(++str));
+	}
+}
+
+/**
+ * \brief Computes the bounding box of a string
+ *
+ * \note If string is empty the returned width will be 1 pixel and the height
+ * equal to the font height.
+ *
+ * \param[in] str      String to calculate bounding box for
+ * \param[in] font     Font used
+ * \param[in] width    Pointer to width result
+ * \param[in] height   Pointer to height result
+ */
+void gfx_mono_get_string_bounding_box(const char *str, const struct font *font,
+		gfx_coord_t *width, gfx_coord_t *height)
+{
+	gfx_coord_t font_width = font->width;
+	gfx_coord_t font_height = font->height;
+
+	gfx_coord_t max_width = 1;
+	gfx_coord_t max_height = font_height;
+	gfx_coord_t x = 0;
+
+	/* Sanity check on parameters, assert if str or font is NULL. */
+	Assert(str != NULL);
+	Assert(font != NULL);
+
+	/* Handle each character until trailing null byte */
+	do {
+		/* Handle '\n' as newline, draw normal characters. */
+		if (*str == '\n') {
+			x = 0;
+			max_height += font_height;
+		} else if (*str == '\r') {
+			/* Skip '\r' characters. */
+		} else {
+			x += font_width;
+			if (x > max_width) {
+				max_width = x;
+			}
+		}
+	} while (*(++str));
+
+	/* Return values through references */
+	*width = max_width;
+	*height = max_height;
+}
+
+/**
+ * \brief Computes the bounding box of a string located in program memory
+ *
+ * \note If string is empty the returned width will be 1 pixel and the height
+ * equal to the font height.
+ *
+ * \param[in] str      String in program memory to calculate bounding box for
+ * \param[in] font     Font used
+ * \param[in] width    Pointer to width result
+ * \param[in] height   Pointer to height result
+ */
+void gfx_mono_get_progmem_string_bounding_box(char PROGMEM_PTR_T str,
+		const struct font *font, gfx_coord_t *width,
+		gfx_coord_t *height)
+{
+	gfx_coord_t font_width = font->width;
+	gfx_coord_t font_height = font->height;
+
+	char temp_char;
+	gfx_coord_t max_width = 1;
+	gfx_coord_t max_height = font_height;
+	gfx_coord_t x = 0;
+
+	/* Sanity check on parameters, assert if str or font is NULL. */
+	Assert(str != NULL);
+	Assert(font != NULL);
+
+	/* Handle each character until trailing null byte */
+	temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)str);
+
+	while (temp_char) {
+		/* Handle '\n' as newline, draw normal characters. */
+		if (temp_char == '\n') {
+			x = 0;
+			max_height += font_height;
+		} else if (*str == '\r') {
+			/* Skip '\r' characters. */
+		} else {
+			x += font_width;
+			if (x > max_width) {
+				max_width = x;
+			}
+		}
+
+		temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)(++str));
+	}
+
+	/* Return values through references */
+	*width = max_width;
+	*height = max_height;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.h
new file mode 100644
index 0000000000..9884397a95
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.h
@@ -0,0 +1,177 @@
+/**
+ * \file
+ *
+ * \brief Monochrome graphic library API header file
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GFX_MONO_TEXT_H_INCLUDED
+#define GFX_MONO_TEXT_H_INCLUDED
+
+#include <stdint.h>
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_font GFX Mono Font Library
+ * This modules provides functionality for outputting a monochrome font
+ * to a display.
+ *
+ * \section asfdoc_common2_gfx_mono_font_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \brief Valid storage locations for font data
+ *
+ * Add support for fonts in regular ram
+ */
+enum font_data_type {
+	/** Font data stored in program/flash memory. */
+	FONT_LOC_PROGMEM,
+};
+
+/** Storage structure for font meta data. */
+struct font {
+	/** Type of storage used for binary font data. See \ref font_data_type. */
+	enum font_data_type type;
+	union {
+		/**
+		 * Pointer to where the binary font data is stored. This
+		 * variable is accessed either through hugemem or progmem
+		 * depending on the value of \a type.
+		 */
+#ifdef CONFIG_HAVE_HUGEMEM
+		hugemem_ptr_t hugemem;
+#endif
+		uint8_t PROGMEM_PTR_T progmem;
+	} data;
+	/** Width of one font character, in pixels. */
+	uint8_t width;
+	/** Height of one font character, in pixels. */
+	uint8_t height;
+	/** ASCII value of first character in font set. */
+	uint8_t first_char;
+	/** ASCII value of last character in the set. */
+	uint8_t last_char;
+};
+
+/** \name Strings and characters located in RAM */
+/** @{ */
+void gfx_mono_draw_char(const char c, const gfx_coord_t x, const gfx_coord_t y,
+		const struct font *font);
+
+void gfx_mono_draw_string(const char *str, const gfx_coord_t x,
+		const gfx_coord_t y, const struct font *font);
+
+void gfx_mono_get_string_bounding_box(char const *str, const struct font *font,
+		gfx_coord_t *width, gfx_coord_t *height);
+
+/** @} */
+
+/** \name Strings located in flash */
+/** @{ */
+void gfx_mono_draw_progmem_string(char PROGMEM_PTR_T str, gfx_coord_t x,
+		gfx_coord_t y, const struct font *font);
+
+void gfx_mono_get_progmem_string_bounding_box(char PROGMEM_PTR_T str,
+		const struct font *font, gfx_coord_t *width,
+		gfx_coord_t *height);
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_common2_gfx_mono_font_quickstart Quick Start Guide for the mono font service
+ *
+ * This is the quick start guide for the \ref asfdoc_common2_gfx_mono_font
+ * with step-by-step instructions on how to configure and use it for a specific
+ * use case.
+ *
+ * \section asfdoc_common2_gfx_mono_font_quickstart_basic Basic usage of the graphics service
+ * This use case will demonstrate initializing the mono graphics service and
+ * then draw a "Hello world!" sting on the display.
+ *
+ * \section asfdoc_common2_gfx_mono_font_quickstart_depend Dependencies
+ * In order to use this quick start, the following dependencies are needed:
+ * - \ref asfdoc_samd20_system_group
+ * - \ref asfdoc_common2_gfx_mono_font
+ * - \ref conf_sysfont.h Containing the actual font.
+ *
+ * \section asfdoc_common2_gfx_mono_font_basic_usage Usage steps
+ * \subsection gfx_mono_font_basic_usage_code Example code
+ * Add to, e.g., the main function in the application C-file:
+ * \code
+	     system_init();
+
+	     gfx_mono_init();
+
+	     gfx_mono_draw_string("Hello world!",0, 0, &sysfont);
+
+	     while (1) {
+
+	     }
+\endcode
+ *
+ * \subsection asfdoc_common2_gfx_mono_font_basic_usage_workflow Workflow
+ * -# Initialize system:
+ *  - \code system_init(); \endcode
+ * -# Initialize monochrome graphics service
+ *  - \code gfx_mono_init(); \endcode
+ *  - \note This will call the init function for the low level display
+ *          controller driver and intialize the screen to a cleared background.
+ * -# Draw a string on the screen starting at pixel (0,0)
+ * -  \code gfx_mono_draw_string("Hello world!",0, 0, &sysfont); \endcode
+ * -  \note This uses \ref conf_sysfont.h where sysfont is defines to give the font
+ * to be used on the screen.
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_TEXT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.c
new file mode 100644
index 0000000000..bf049033b9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.c
@@ -0,0 +1,372 @@
+/**
+ * \file
+ *
+ * \brief Haven Display UG 2832HSWEG04 display glue code for display controller
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "gfx_mono_ug_2832hsweg04.h"
+
+/* If we are using a serial interface without readback, use framebuffer */
+
+#ifdef CONFIG_SSD1306_FRAMEBUFFER
+static uint8_t framebuffer[GFX_MONO_LCD_FRAMEBUFFER_SIZE];
+#endif
+
+/**
+ * \brief Initialize SSD1306 controller and LCD display.
+ * It will also write the graphic controller RAM to all zeroes.
+ *
+ * \note This function will clear the contents of the display.
+ */
+void gfx_mono_ssd1306_init(void)
+{
+	uint8_t page;
+	uint8_t column;
+
+#ifdef CONFIG_SSD1306_FRAMEBUFFER
+	gfx_mono_set_framebuffer(framebuffer);
+#endif
+
+	/* Initialize the low-level display controller. */
+	ssd1306_init();
+
+	/* Set display to output data from line 0 */
+	ssd1306_set_display_start_line_address(0);
+
+	/* Clear the contents of the display.
+	 * If using a framebuffer (SPI interface) it will both clear the
+	 * controller memory and the framebuffer.
+	 */
+	for (page = 0; page < GFX_MONO_LCD_PAGES; page++) {
+		for (column = 0; column < GFX_MONO_LCD_WIDTH; column++) {
+			gfx_mono_ssd1306_put_byte(page, column, 0x00, true);
+		}
+	}
+}
+
+#ifdef CONFIG_SSD1306_FRAMEBUFFER
+/**
+ * \brief Put framebuffer to LCD controller
+ *
+ * This function will output the complete framebuffer from RAM to the
+ * LCD controller.
+ *
+ * \note This is done automatically if using the graphic primitives. Only
+ * needed if you are manipulating the framebuffer directly in your code.
+ */
+void gfx_mono_ssd1306_put_framebuffer(void)
+{
+	uint8_t page;
+
+	for (page = 0; page < GFX_MONO_LCD_PAGES; page++) {
+		ssd1306_set_page_address(page);
+		ssd1306_set_column_address(0);
+		gfx_mono_ssd1306_put_page(framebuffer
+				+ (page * GFX_MONO_LCD_WIDTH), page, 0,
+				GFX_MONO_LCD_WIDTH);
+	}
+}
+#endif
+
+/**
+ * \brief Draw pixel to screen
+ *
+ * \param[in] x         X coordinate of the pixel
+ * \param[in] y         Y coordinate of the pixel
+ * \param[in] color     Pixel operation
+ *
+ * The following will set the pixel at x=10,y=10:
+ * \code
+	gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_SET);
+\endcode
+ * The following example will clear the pixel at x=10,y=10:
+ * \code
+	gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_CLR);
+\endcode
+ * And the following will toggle the pixel at x=10,y=10:
+ * \code
+	gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_XOR);
+\endcode
+ */
+void gfx_mono_ssd1306_draw_pixel(gfx_coord_t x, gfx_coord_t y,
+		gfx_coord_t color)
+{
+	uint8_t page;
+	uint8_t pixel_mask;
+	uint8_t pixel_value;
+
+	/* Discard pixels drawn outside the screen */
+	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
+		return;
+	}
+
+	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+	pixel_mask = (1 << (y - (page * 8)));
+
+	/*
+	 * Read the page containing the pixel in interest, then perform the
+	 * requested action on this pixel before writing the page back to the
+	 * display.
+	 */
+	pixel_value = gfx_mono_get_byte(page, x);
+
+	switch (color) {
+	case GFX_PIXEL_SET:
+		pixel_value |= pixel_mask;
+		break;
+
+	case GFX_PIXEL_CLR:
+		pixel_value &= ~pixel_mask;
+		break;
+
+	case GFX_PIXEL_XOR:
+		pixel_value ^= pixel_mask;
+		break;
+
+	default:
+		break;
+	}
+
+	gfx_mono_put_byte(page, x, pixel_value);
+}
+
+/**
+ * \brief Get the pixel value at x,y
+ *
+ * \param[in] x      X coordinate of pixel
+ * \param[in] y      Y coordinate of pixel
+ * \return Non zero value if pixel is set.
+ *
+ * The following example will read the pixel value from x=10,y=10:
+ * \code
+	pixelval = gfx_mono_ssd1306_get_pixel(10,10);
+\endcode
+ */
+uint8_t gfx_mono_ssd1306_get_pixel(gfx_coord_t x, gfx_coord_t y)
+{
+	uint8_t page;
+	uint8_t pixel_mask;
+
+	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
+		return 0;
+	}
+
+	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+	pixel_mask = (1 << (y - (page * 8)));
+
+	return gfx_mono_get_byte(page, x) & pixel_mask;
+}
+
+/**
+ * \brief Put a page from RAM to display controller.
+ *
+ * If the controller is accessed by the SPI interface, we can not read
+ * back data from the LCD controller RAM. Because of this all data that is
+ * written to the LCD controller in this mode is also written to a framebuffer
+ * in MCU RAM.
+ *
+ * \param[in] data Pointer to data to be written
+ * \param[in] page Page address
+ * \param[in] column Offset into page (x coordinate)
+ * \param[in] width Number of bytes to be written.
+ *
+ * The following example will write 32 bytes from data_buf to the page 0,
+ * column 10. This will place data_buf in the rectangle x1=10,y1=0,x2=42,y2=8
+ * (10 pixels from the upper left corner of the screen):
+ * \code
+	gfx_mono_ssd1306_put_page(data_buf, 0, 10, 32);
+\endcode
+ */
+void gfx_mono_ssd1306_put_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t column, gfx_coord_t width)
+{
+#ifdef CONFIG_SSD1306_FRAMEBUFFER
+	gfx_mono_framebuffer_put_page(data, page, column, width);
+#endif
+	ssd1306_set_page_address(page);
+	ssd1306_set_column_address(column);
+
+	do {
+		ssd1306_write_data(*data++);
+	} while (--width);
+}
+
+/**
+ * \brief Read a page from the LCD controller
+ *
+ * If the LCD controller is accessed by the SPI interface we cannot read
+ * data directly from the controller. In that case we will read the data from
+ * the local framebuffer instead.
+ *
+ * \param[in] data   Pointer where to store the read data
+ * \param[in] page   Page address
+ * \param[in] column Offset into page (x coordinate)
+ * \param[in] width  Number of bytes to be read
+ *
+ * The following example will read back the first 128 bytes (first page) from
+ * the display memory:
+ * \code
+	gfx_mono_ssd1306_get_page(read_buffer, 0, 0, 128);
+\endcode
+ */
+void gfx_mono_ssd1306_get_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t column, gfx_coord_t width)
+{
+#ifdef CONFIG_SSD1306_FRAMEBUFFER
+	gfx_mono_framebuffer_get_page(data, page, column, width);
+#else
+	ssd1306_set_page_address(page);
+	ssd1306_set_column_address(column);
+
+	do {
+		*data++ = ssd1306_read_data();
+	} while (--width);
+#endif
+}
+
+/**
+ * \brief Put a byte to the display controller RAM
+ *
+ * If the LCD controller is accessed by the SPI interface we will also put the
+ * data to the local framebuffer.
+ *
+ * \param[in] page Page address
+ * \param[in] column Page offset (x coordinate)
+ * \param[in] data Data to be written
+ * \param[in] force Forces the write
+ *
+ * This example will put the value 0xFF to the first byte in the display memory
+ * setting a 8 pixel high column of pixels in the upper left corner of the
+ * display.
+ * \code
+	gfx_mono_ssd1306_put_byte(0, 0, 0xFF, false);
+\endcode
+  */
+ void gfx_mono_ssd1306_put_byte(gfx_coord_t page, gfx_coord_t column,
+		uint8_t data, bool force)
+{
+#ifdef CONFIG_SSD1306_FRAMEBUFFER
+	if (!force && data == gfx_mono_framebuffer_get_byte(page, column)) {
+		return;
+	}
+	gfx_mono_framebuffer_put_byte(page, column, data);
+#endif
+
+	ssd1306_set_page_address(page);
+	ssd1306_set_column_address(column);
+
+	ssd1306_write_data(data);
+}
+
+/**
+ * \brief Get a byte from the display controller RAM
+ *
+ * If the LCD controller is accessed by the SPI interface we cannot read the
+ * data. In this case return the data from the local framebuffer instead.
+ *
+ * \param[in] page Page address
+ * \param[in] column Page offset (x coordinate)
+ * \return data from LCD controller or framebuffer.
+ *
+ * The following code will read the first byte from the display memory or the
+ * local framebuffer if direct read is not possible. The data represents the
+ * pixels from x = 0 and y = 0 to y = 7.
+ * \code
+	data = gfx_mono_ssd1306_get_byte(0, 0);
+\endcode
+ */
+uint8_t gfx_mono_ssd1306_get_byte(gfx_coord_t page, gfx_coord_t column)
+{
+#ifdef CONFIG_SSD1306_FRAMEBUFFER
+	return gfx_mono_framebuffer_get_byte(page, column);
+
+#else
+	ssd1306_set_page_address(page);
+	ssd1306_set_column_address(column);
+
+	return ssd1306_read_data();
+
+#endif
+}
+
+/**
+ * \brief Read/Modify/Write a byte on the display controller
+ *
+ * This function will read the byte from the display controller (or the
+ * framebuffer if we cannot read directly from the controller) and
+ * do a mask operation on the byte according to the pixel operation selected
+ * by the color argument and the pixel mask provided.
+ *
+ * \param[in] page Page address
+ * \param[in] column Page offset (x coordinate)
+ * \param[in] pixel_mask Mask for pixel operation
+ * \param[in] color Pixel operation
+ *
+ * A small example that will XOR the first byte of display memory with 0xAA
+ * \code
+	gfx_mono_ssd1306_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
+\endcode
+ */
+void gfx_mono_ssd1306_mask_byte(gfx_coord_t page, gfx_coord_t column,
+		gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
+{
+	gfx_mono_color_t temp = gfx_mono_get_byte(page, column);
+
+	switch (color) {
+	case GFX_PIXEL_SET:
+		temp |= pixel_mask;
+		break;
+
+	case GFX_PIXEL_CLR:
+		temp &= ~pixel_mask;
+		break;
+
+	case GFX_PIXEL_XOR:
+		temp ^= pixel_mask;
+		break;
+
+	default:
+		break;
+	}
+
+	gfx_mono_put_byte(page, column, temp);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.h
new file mode 100644
index 0000000000..5cb0ddd834
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.h
@@ -0,0 +1,168 @@
+/**
+ * \file
+ *
+ * \brief Haven Display UG 2832HSWEG04 display glue code for display controller
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef GFX_MONO_2832HSWEG04_H
+#define GFX_MONO_2832HSWEG04_H
+#include "compiler.h"
+#include "ssd1306.h"
+
+#include "gfx_mono.h"
+#include "gfx_mono_framebuffer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono
+ * \defgroup asfdoc_common2_gfx_mono_2832hsweg04_group 2832HSWEG04 graphic library abstraction
+ *
+ * This module is an abstraction layer between the graphic library and the
+ * 2832HSWEG04 monochrome LCD display connected to a SSD1306 LCD controller.
+ *
+ * As the controller does not provide any hardware accelerated graphic, all the
+ * graphic primitives are provided by the \ref asfdoc_common2_gfx_mono_generic_group service.
+ *
+ * \note Do not call the gfx_mono_ssd1306_ functions directly. use the gfx_mono
+ * names that are defined in this header and documented in \ref asfdoc_common2_gfx_mono .
+ * Ie. gfx_mono_draw_pixel() should be used, not gfx_mono_ssd1306_draw_pixel()
+ * @{
+ */
+
+#define GFX_MONO_LCD_WIDTH              128
+#ifndef GFX_MONO_LCD_HEIGHT
+#       define GFX_MONO_LCD_HEIGHT             32
+#endif
+#define GFX_MONO_LCD_PIXELS_PER_BYTE    8
+#define GFX_MONO_LCD_PAGES              (GFX_MONO_LCD_HEIGHT / \
+	GFX_MONO_LCD_PIXELS_PER_BYTE)
+#define GFX_MONO_LCD_FRAMEBUFFER_SIZE   ((GFX_MONO_LCD_WIDTH * \
+	GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
+
+#define gfx_mono_draw_horizontal_line(x, y, length, color) \
+	gfx_mono_generic_draw_horizontal_line(x, y, length, color)
+
+#define gfx_mono_draw_vertical_line(x, y, length, color) \
+	gfx_mono_generic_draw_vertical_line(x, y, length, color)
+
+#define gfx_mono_draw_line(x1, y1, x2, y2, color) \
+	gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
+
+#define gfx_mono_draw_rect(x, y, width, height, color) \
+	gfx_mono_generic_draw_rect(x, y, width, height, color)
+
+#define gfx_mono_draw_filled_rect(x, y, width, height, color) \
+	gfx_mono_generic_draw_filled_rect(x, y, width, height, \
+		color)
+
+#define gfx_mono_draw_circle(x, y, radius, color, octant_mask) \
+	gfx_mono_generic_draw_circle(x, y, radius, color, \
+		octant_mask)
+
+#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask)	\
+	gfx_mono_generic_draw_filled_circle(x, y, radius, \
+		color, quadrant_mask)
+
+#define gfx_mono_put_bitmap(bitmap, x, y) \
+	gfx_mono_generic_put_bitmap(bitmap, x, y)
+
+#define gfx_mono_draw_pixel(x, y, color) \
+	gfx_mono_ssd1306_draw_pixel(x, y, color)
+
+#define gfx_mono_get_pixel(x, y) \
+	gfx_mono_ssd1306_get_pixel(x, y)
+
+#define gfx_mono_init()	\
+	gfx_mono_ssd1306_init()
+
+#define gfx_mono_put_page(data, page, column, width) \
+	gfx_mono_ssd1306_put_page(data, page, column, width)
+
+#define gfx_mono_get_page(data, page, column, width) \
+	gfx_mono_ssd1306_get_page(data, page, column, width)
+
+#define gfx_mono_put_byte(page, column, data) \
+	gfx_mono_ssd1306_put_byte(page, column, data, false)
+
+#define gfx_mono_get_byte(page, column)	\
+	gfx_mono_ssd1306_get_byte(page, column)
+
+#define gfx_mono_mask_byte(page, column, pixel_mask, color) \
+	gfx_mono_ssd1306_mask_byte(page, column, pixel_mask, color)
+
+#define gfx_mono_put_framebuffer() \
+	gfx_mono_ssd1306_put_framebuffer()
+
+void gfx_mono_ssd1306_put_framebuffer(void);
+
+void gfx_mono_ssd1306_put_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t page_offset, gfx_coord_t width);
+
+void gfx_mono_ssd1306_get_page(gfx_mono_color_t *data, gfx_coord_t page,
+		gfx_coord_t page_offset, gfx_coord_t width);
+
+void gfx_mono_ssd1306_init(void);
+
+void gfx_mono_ssd1306_draw_pixel(gfx_coord_t x, gfx_coord_t y,
+		gfx_mono_color_t color);
+
+uint8_t gfx_mono_ssd1306_get_pixel(gfx_coord_t x, gfx_coord_t y);
+
+void gfx_mono_ssd1306_put_byte(gfx_coord_t page, gfx_coord_t column,
+		uint8_t data, bool force);
+
+uint8_t gfx_mono_ssd1306_get_byte(gfx_coord_t page, gfx_coord_t column);
+
+void gfx_mono_ssd1306_mask_byte(gfx_coord_t page, gfx_coord_t column,
+		gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GFX_MONO_2832HSWEG04_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_menu.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_menu.h
new file mode 100644
index 0000000000..5a765a7712
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_menu.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief Default configurations for menu system
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef DEFAULT_MENU_H_INCLUDED
+#define DEFAULT_MENU_H_INCLUDED
+
+//! \name Indicator icon definitions
+//@{
+//! Bitmap data, row by row, MSB is leftmost pixel, one byte per row.
+#define GFX_MONO_MENU_INDICATOR_BITMAP 0xFF, 0x7E, 0x3C, 0x18
+//! Height in pixels of indicator icon
+#define GFX_MONO_MENU_INDICATOR_HEIGHT 8
+//! Width in pixels of indicator icon
+#define GFX_MONO_MENU_INDICATOR_WIDTH  4
+//@}
+
+//! \name Keyboard codes
+//@{
+//! Down
+#define GFX_MONO_MENU_KEYCODE_DOWN  40
+//! Up
+#define GFX_MONO_MENU_KEYCODE_UP    38
+//! Back/exit
+#define GFX_MONO_MENU_KEYCODE_BACK  8
+//! Enter/select
+#define GFX_MONO_MENU_KEYCODE_ENTER 13
+//@}
+
+#endif /* DEFAULT_MENU_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_spinctrl.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_spinctrl.h
new file mode 100644
index 0000000000..2090b6a136
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_spinctrl.h
@@ -0,0 +1,75 @@
+/**
+ * \file
+ *
+ * \brief Default configurations for gfx_mono_spinctrl
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef DEFAULT_GFX_MONO_SPINCTRL_H_INCLUDED
+#define DEFAULT_GFX_MONO_SPINCTRL_H_INCLUDED
+
+//! Spinner value indicator
+/* Bitmap data, row by row, MSB is leftmost pixel, one byte per row. */
+#define GFX_MONO_SPINCTRL_SPIN_INDICATOR_BITMAP 0x18, 0x3C, 0x7E, 0xFF
+//! Height of spinner value indicator
+#define GFX_MONO_SPINCTRL_SPIN_INDICATOR_HEIGHT 8
+//! Width of spinner value indicator
+#define GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH  4
+
+//! Spinner indicator
+/* Bitmap data, row by row, MSB is leftmost pixel, one byte per row. */
+#define GFX_MONO_SPINCTRL_INDICATOR_BITMAP 0xFF, 0x7E, 0x3C, 0x18
+//! Height of spinner indicator
+#define GFX_MONO_SPINCTRL_INDICATOR_HEIGHT 8
+//! Width of spinner indicator
+#define GFX_MONO_SPINCTRL_INDICATOR_WIDTH  4
+
+//! Keyboard code down
+#define GFX_MONO_SPINCTRL_KEYCODE_DOWN  40
+//! Keyboard code up
+#define GFX_MONO_SPINCTRL_KEYCODE_UP    38
+//! Keyboard code back
+#define GFX_MONO_SPINCTRL_KEYCODE_BACK  8
+//! Keyboard code enter
+#define GFX_MONO_SPINCTRL_KEYCODE_ENTER 13
+
+#endif /* DEFAULT_GFX_MONO_SPINCTRL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_sysfont.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_sysfont.h
new file mode 100644
index 0000000000..05daa73bee
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_sysfont.h
@@ -0,0 +1,1170 @@
+/**
+ * \file
+ *
+ * \brief Default configurations for sysfont
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_SYSFONT_H
+#define CONF_SYSFONT_H
+
+/**
+ * \weakgroup gfx_mono_sysfont
+ * @{
+ */
+
+#include <stdint.h>
+
+/* #define USE_FONT_BPMONO_10x16 */
+/* #define USE_FONT_BPMONO_10x14 */
+/* #define USE_FONT_MONO_MMM_10x12 */
+#define USE_FONT_BASIC_6x7
+
+#if defined(USE_FONT_BPMONO_10x16)
+/** Width of each glyph, including spacer column. */
+#  define SYSFONT_WIDTH           10
+/** Height of each glyph, excluding spacer line. */
+#  define SYSFONT_HEIGHT          16
+/** Line height. */
+#  define SYSFONT_LINESPACING     8
+/** First character defined. */
+#  define SYSFONT_FIRSTCHAR       ((uint8_t)' ')
+/** Last character defined. */
+#  define SYSFONT_LASTCHAR        ((uint8_t)'}')
+
+/** Define variable containing the font */
+#  define SYSFONT_DEFINE_GLYPHS \
+        /* Glyph data, row by row, MSB is leftmost pixel, one byte per row. */ \
+	static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[]) = { \
+		/* "BPmono" font (http://www.backpacker.gr) at size 10x16 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /*   */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, \
+		0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, \
+		0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* ! */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C, 0x00, 0x6C, 0x00, \
+		0x6C, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* " */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, \
+		0x48, 0x00, 0xFC, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, \
+		0xFC, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* # */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x3C, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, 0x04, 0x00, \
+		0x78, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* $ */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, \
+		0xA4, 0x00, 0xA8, 0x00, 0x48, 0x00, 0x10, 0x00, 0x14, 0x00, \
+		0x2A, 0x00, 0x4A, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* % */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x8A, 0x00, \
+		0x8A, 0x00, 0x8C, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* & */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* ' */ \
+		0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* ( */ \
+		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* ) */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x10, 0x00, \
+		0x7C, 0x00, 0x10, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* * */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* + */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x30, 0x00, 0x20, 0x00, \
+		0x00, 0x00, /* , */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* - */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* . */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* / */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x8C, 0x00, 0x94, 0x00, 0xA4, 0x00, 0xC4, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 0 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
+		0x50, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 1 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 2 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x88, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 3 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x18, 0x00, \
+		0x28, 0x00, 0x28, 0x00, 0x48, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0xFC, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 4 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x04, 0x00, 0x04, 0x00, \
+		0x04, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 5 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x40, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0xB0, 0x00, 0xC8, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 6 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
+		0x04, 0x00, 0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 7 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 8 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x8C, 0x00, 0x74, 0x00, 0x04, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* 9 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* : */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x80, 0x00, \
+		0x00, 0x00, /* ; */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x04, 0x00, 0x18, 0x00, 0x60, 0x00, 0x80, 0x00, \
+		0x60, 0x00, 0x18, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* < */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* = */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x40, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x02, 0x00, \
+		0x0C, 0x00, 0x30, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* > */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* ? */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x3C, 0x00, 0x42, 0x00, 0xBA, 0x00, 0xAA, 0x00, 0xAA, 0x00, \
+		0xAA, 0x00, 0xBC, 0x00, 0x40, 0x00, 0x3C, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* @ */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x44, 0x00, 0x7C, 0x00, \
+		0x44, 0x00, 0x82, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* A */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* B */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x44, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x44, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* C */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* D */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x40, 0x00, \
+		0x40, 0x00, 0x40, 0x00, 0x78, 0x00, 0x40, 0x00, 0x40, 0x00, \
+		0x40, 0x00, 0x40, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* E */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x40, 0x00, \
+		0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x78, 0x00, 0x40, 0x00, \
+		0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* F */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x44, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x9C, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x44, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* G */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0xFC, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* H */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* I */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* J */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* K */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* L */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0xCC, 0x00, 0xCC, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* M */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xC4, 0x00, \
+		0xC4, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0x94, 0x00, 0x94, 0x00, \
+		0x8C, 0x00, 0x8C, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* N */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* O */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* P */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x20, 0x00, 0x1C, 0x00, \
+		0x00, 0x00, /* Q */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x90, 0x00, \
+		0x88, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* R */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+		0x80, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, 0x04, 0x00, \
+		0x04, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* S */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* T */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* U */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x82, 0x00, \
+		0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
+		0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* V */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0xB4, 0x00, \
+		0x78, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* W */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x44, 0x00, \
+		0x44, 0x00, 0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x28, 0x00, \
+		0x44, 0x00, 0x44, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* X */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x44, 0x00, \
+		0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* Y */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+		0x40, 0x00, 0x40, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* Z */ \
+		0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0xE0, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* [ */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* \ */ \
+		0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xE0, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* ] */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, \
+		0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* ^ */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* _ */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, \
+		0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* ` */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x78, 0x00, 0x04, 0x00, 0x04, 0x00, 0x7C, 0x00, \
+		0x84, 0x00, 0x8C, 0x00, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* a */ \
+		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* b */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* c */ \
+		0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, \
+		0x02, 0x00, 0x3E, 0x00, 0x42, 0x00, 0x82, 0x00, 0x82, 0x00, \
+		0x82, 0x00, 0x42, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* d */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x82, 0x00, 0xFE, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* e */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* f */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x8C, 0x00, 0x74, 0x00, 0x04, 0x00, 0x44, 0x00, \
+		0x38, 0x00, /* g */ \
+		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* h */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x70, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* i */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x10, 0x00, \
+		0xE0, 0x00, /* j */ \
+		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xE0, 0x00, \
+		0x90, 0x00, 0x88, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* k */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* l */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0xAC, 0x00, 0xD4, 0x00, 0x94, 0x00, 0x94, 0x00, \
+		0x94, 0x00, 0x94, 0x00, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* m */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* n */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x78, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* o */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, /* p */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x7C, 0x00, 0x04, 0x00, 0x04, 0x00, \
+		0x04, 0x00, /* q */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0xCC, 0x00, 0x30, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* r */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, 0x80, 0x00, 0x78, 0x00, \
+		0x04, 0x00, 0x04, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* s */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x20, 0x00, 0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* t */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* u */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x82, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
+		0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* v */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x84, 0x00, 0x84, 0x00, 0xB4, 0x00, 0xB4, 0x00, \
+		0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* w */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, \
+		0x28, 0x00, 0x44, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* x */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x82, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
+		0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+		0x20, 0x00, /* y */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, \
+		0x20, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* z */ \
+		0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* { */ \
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* | */ \
+		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, \
+		0x00, 0x00, /* } */ \
+	};
+#elif defined(USE_FONT_BPMONO_10x14)
+/** Width of each glyph, including spacer column. */
+#  define SYSFONT_WIDTH           10
+/** Height of each glyph, excluding spacer line. */
+#  define SYSFONT_HEIGHT          14
+/** Line height. */
+#  define SYSFONT_LINESPACING     8
+/** First character defined. */
+#  define SYSFONT_FIRSTCHAR       ((uint8_t)' ')
+/** Last character defined. */
+#  define SYSFONT_LASTCHAR        ((uint8_t)'}')
+
+/** Define variable containing the font */
+#  define SYSFONT_DEFINE_GLYPHS \
+        /* Glyph data, row by row, MSB is leftmost pixel, one byte per row. */ \
+	static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[]) = { \
+		/* "BPmono" font (http://www.backpacker.gr) at size 10x14 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*   */	\
+		0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, \
+		0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 0x00, \
+		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ! */	\
+		0x00, 0x00, 0x00, 0x00, 0x6C, 0x00, 0x6C, 0x00, 0x6C, 0x00, \
+		0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* " */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x28, 0x00, \
+		0x7C, 0x00, 0x28, 0x00, 0x28, 0x00, 0x7C, 0x00, 0x28, 0x00, \
+		0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* # */	\
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x3C, 0x00, 0x40, 0x00, \
+		0x20, 0x00, 0x10, 0x00, 0x08, 0x00, 0x04, 0x00, 0x78, 0x00, \
+		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* $ */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0xA4, 0x00, \
+		0xA8, 0x00, 0x50, 0x00, 0x28, 0x00, 0x54, 0x00, 0x94, 0x00, \
+		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* % */	\
+		0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x90, 0x00, 0x90, 0x00, \
+		0x90, 0x00, 0x60, 0x00, 0x94, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* & */	\
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ' */	\
+		0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, /* ( */	\
+		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, /* ) */	\
+		0x00, 0x00, 0x28, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x10, 0x00, \
+		0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* * */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* + */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x10, 0x00, 0x30, 0x00, 0x20, 0x00, 0x00, 0x00, /* , */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* - */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
+		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* . */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x40, 0x00, \
+		0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* / */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+		0x8C, 0x00, 0x94, 0x00, 0xA4, 0x00, 0xC4, 0x00, 0x84, 0x00, \
+		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
+		0x50, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 1 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x08, 0x00, 0x88, 0x00, \
+		0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 3 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x18, 0x00, \
+		0x28, 0x00, 0x48, 0x00, 0x88, 0x00, 0xFC, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 4 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xF0, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 5 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40, 0x00, \
+		0x80, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x40, 0x00, \
+		0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 7 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x78, 0x00, 0x08, 0x00, 0x10, 0x00, \
+		0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 9 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
+		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* : */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
+		0x30, 0x00, 0x60, 0x00, 0x40, 0x00, 0x00, 0x00, /* ; */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, \
+		0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, \
+		0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* < */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* = */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, \
+		0x20, 0x00, 0x10, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, \
+		0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* > */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ? */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, \
+		0x42, 0x00, 0x9A, 0x00, 0xAA, 0x00, 0xAA, 0x00, 0xBE, 0x00, \
+		0x80, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, /* @ */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, \
+		0x28, 0x00, 0x44, 0x00, 0x7C, 0x00, 0x44, 0x00, 0x44, 0x00, \
+		0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* A */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0xF8, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* B */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x40, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x40, 0x00, \
+		0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* C */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x88, 0x00, \
+		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* D */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* E */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* F */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x40, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x9C, 0x00, 0x84, 0x00, 0x44, 0x00, \
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* G */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* H */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* I */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* J */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x88, 0x00, \
+		0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* K */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* L */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xCC, 0x00, \
+		0xCC, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* M */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xC4, 0x00, \
+		0xC4, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0x94, 0x00, 0x94, 0x00, \
+		0x8C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* N */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* O */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* P */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x78, 0x00, 0x20, 0x00, 0x18, 0x00, 0x00, 0x00, /* Q */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* R */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x60, 0x00, 0x18, 0x00, 0x04, 0x00, 0x04, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* S */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* T */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* U */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x30, 0x00, \
+		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* V */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xA8, 0x00, \
+		0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
+		0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* W */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x50, 0x00, 0x20, 0x00, 0x20, 0x00, 0x50, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* X */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Y */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, \
+		0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Z */	\
+		0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x40, 0x00, 0x40, 0x00, \
+		0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, \
+		0x40, 0x00, 0x40, 0x00, 0x70, 0x00, 0x00, 0x00, /* [ */	\
+		0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, /* \ */	\
+		0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x38, 0x00, 0x00, 0x00, /* ] */	\
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, 0x44, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ^ */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* _ */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ` */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x70, 0x00, 0x08, 0x00, 0x08, 0x00, 0x78, 0x00, 0x88, 0x00, \
+		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* a */	\
+		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0xF8, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* b */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x78, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c */	\
+		0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, \
+		0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x8C, 0x00, \
+		0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* d */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x78, 0x00, 0x84, 0x00, 0xFC, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* e */	\
+		0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* f */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x7C, 0x00, 0x04, 0x00, 0x78, 0x00, 0x00, 0x00, /* g */	\
+		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* h */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, \
+		0x70, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* i */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, \
+		0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x70, 0x00, /* j */	\
+		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* k */	\
+		0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* l */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xA4, 0x00, 0xFC, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0xA4, 0x00, \
+		0xA4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* m */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* n */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x78, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* o */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* p */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+		0x7C, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, /* q */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xD8, 0x00, 0x60, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, \
+		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* r */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x78, 0x00, 0x80, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, \
+		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* s */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, \
+		0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* t */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* u */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x48, 0x00, 0x48, 0x00, \
+		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* v */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x88, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, \
+		0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* w */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x88, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, 0x50, 0x00, \
+		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* x */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x84, 0x00, 0x84, 0x00, 0x48, 0x00, 0x48, 0x00, 0x30, 0x00, \
+		0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x00, 0x00, /* y */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF8, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* z */	\
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, /* { */	\
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, /* | */	\
+		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x10, 0x00, \
+		0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, /* } */	\
+	};
+#elif defined(USE_FONT_MONO_MMM_10x12)
+/** Width of each glyph, including spacer column. */
+#  define SYSFONT_WIDTH           10
+/** Height of each glyph, excluding spacer line. */
+#  define SYSFONT_HEIGHT          12
+/** Line height. */
+#  define SYSFONT_LINESPACING     8
+/** First character defined. */
+#  define SYSFONT_FIRSTCHAR       ((uint8_t)' ')
+/** Last character defined. */
+#  define SYSFONT_LASTCHAR        ((uint8_t)'}')
+
+/** Define variable containing the font */
+#  define SYSFONT_DEFINE_GLYPHS \
+        /* Glyph data, row by row, MSB is leftmost pixel, one byte per row. */ \
+	static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[]) = { \
+		/* "MonoMMM" font (http://www.dafont.com/monommm-5.font) size 10x12 */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /*   */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* ! */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x50, 0x00, \
+		0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* " */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0xF8, 0x00, \
+		0x50, 0x00, 0xF8, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* # */	\
+		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x70, 0x00, 0xA8, 0x00, \
+		0xA0, 0x00, 0x70, 0x00, 0x28, 0x00, 0xA8, 0x00, 0x70, 0x00, \
+		0x20, 0x00, 0x00, 0x00, /* $ */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC8, 0x00, 0xB0, 0x00, \
+		0x50, 0x00, 0x20, 0x00, 0x50, 0x00, 0x68, 0x00, 0x98, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* % */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x90, 0x00, \
+		0xA0, 0x00, 0x40, 0x00, 0xA8, 0x00, 0x90, 0x00, 0x68, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* & */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* ' */	\
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x10, 0x00, 0x00, 0x00, /* ( */	\
+		0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x40, 0x00, 0x00, 0x00, /* ) */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0xF8, 0x00, \
+		0x70, 0x00, 0xF8, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* * */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0xF8, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* + */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x40, 0x00, /* , */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* - */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* . */	\
+		0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x60, 0x00, 0x40, 0x00, \
+		0xC0, 0x00, 0x00, 0x00, /* / */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x98, 0x00, 0xA8, 0x00, 0xC8, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 0 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0xE0, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 1 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 2 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 3 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
+		0x50, 0x00, 0x90, 0x00, 0xF8, 0x00, 0x10, 0x00, 0x10, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 4 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+		0xF0, 0x00, 0x08, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 5 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 6 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 7 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 8 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* 9 */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* : */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x40, 0x00, /* ; */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, \
+		0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, 0x08, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* < */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF8, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* = */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, \
+		0x10, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* > */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* ? */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0xB8, 0x00, 0xA8, 0x00, 0xB8, 0x00, 0x80, 0x00, 0x78, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* @ */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* A */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* B */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* C */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* D */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* E */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* F */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x80, 0x00, 0x98, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* G */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* H */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* I */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x08, 0x00, 0x08, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* J */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x00, 0xB0, 0x00, \
+		0xE0, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0xB0, 0x00, 0x98, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* K */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* L */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xD8, 0x00, \
+		0xF8, 0x00, 0xA8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* M */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xC8, 0x00, \
+		0xC8, 0x00, 0xA8, 0x00, 0x98, 0x00, 0x98, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* N */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* O */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* P */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xA8, 0x00, 0x70, 0x00, \
+		0x08, 0x00, 0x00, 0x00, /* Q */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* R */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+		0x80, 0x00, 0x70, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* S */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* T */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* U */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x50, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* V */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x88, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* W */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x50, 0x00, \
+		0x70, 0x00, 0x20, 0x00, 0x70, 0x00, 0x50, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* X */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x50, 0x00, \
+		0x70, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* Y */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+		0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* Z */	\
+		0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x30, 0x00, 0x00, 0x00, /* [ */	\
+		0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x40, 0x00, 0x60, 0x00, \
+		0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x04, 0x00, 0x00, 0x00, /* \ */	\
+		0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x60, 0x00, 0x00, 0x00, /* ] */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x00, \
+		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* ^ */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0xFC, 0x00, /* _ */	\
+		0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* ` */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF0, 0x00, 0x08, 0x00, 0xF8, 0x00, 0x88, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* a */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* b */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x70, 0x00, 0x88, 0x00, 0x80, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* c */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
+		0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* d */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x70, 0x00, 0x88, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x78, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* e */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x20, 0x00, \
+		0x70, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* f */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+		0x08, 0x00, 0x70, 0x00, /* g */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* h */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, \
+		0x60, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* i */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, \
+		0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0xC0, 0x00, /* j */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x98, 0x00, 0xA0, 0x00, 0xE0, 0x00, 0x90, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* k */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* l */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* m */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* n */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* o */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+		0x80, 0x00, 0x80, 0x00, /* p */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+		0x08, 0x00, 0x08, 0x00, /* q */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF8, 0x00, 0x88, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* r */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF8, 0x00, 0x80, 0x00, 0xF8, 0x00, 0x08, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* s */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x78, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x18, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* t */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* u */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x88, 0x00, 0x50, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* v */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* w */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xD8, 0x00, 0x50, 0x00, 0x20, 0x00, 0x50, 0x00, 0xD8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* x */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+		0x08, 0x00, 0x70, 0x00, /* y */	\
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+		0xF8, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0xF8, 0x00, \
+		0x00, 0x00, 0x00, 0x00, /* z */	\
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x10, 0x00, 0x00, 0x00, /* { */	\
+		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x00, 0x00, /* | */	\
+		0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x20, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+		0x40, 0x00, 0x00, 0x00, /* } */	\
+	};
+#elif defined(USE_FONT_BASIC_6x7)
+/** Width of each glyph, including spacer column. */
+#  define SYSFONT_WIDTH           6
+/** Height of each glyph, excluding spacer line. */
+#  define SYSFONT_HEIGHT          7
+/** Line height. */
+#  define SYSFONT_LINESPACING     8
+/** First character defined. */
+#  define SYSFONT_FIRSTCHAR       ((uint8_t)' ')
+/** Last character defined. */
+#  define SYSFONT_LASTCHAR        ((uint8_t)'}')
+
+/** Define variable containing the font */
+#  define SYSFONT_DEFINE_GLYPHS \
+        /* Glyph data, row by row, MSB is leftmost pixel, one byte per row. */ \
+	static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[]) = { \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,          /* " " */ \
+		0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x20,          /* "!" */ \
+		0x50, 0x50, 0x50, 0x00, 0x00, 0x00, 0x00,          /* """ */ \
+		0x50, 0x50, 0xf8, 0x50, 0xf8, 0x50, 0x50,          /* "#" */ \
+		0x20, 0x78, 0xa0, 0x70, 0x28, 0xf0, 0x20,          /* "$" */ \
+		0xc0, 0xc8, 0x10, 0x20, 0x40, 0x98, 0x18,          /* "%" */ \
+		0x60, 0x90, 0xa0, 0x40, 0xa8, 0x90, 0x68,          /* "&" */ \
+		0x60, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00,          /* "'" */ \
+		0x10, 0x20, 0x40, 0x40, 0x40, 0x20, 0x10,          /* "(" */ \
+		0x40, 0x20, 0x10, 0x10, 0x10, 0x20, 0x40,          /* ")" */ \
+		0x00, 0x50, 0x20, 0xf8, 0x20, 0x50, 0x00,          /* "*" */ \
+		0x00, 0x20, 0x20, 0xf8, 0x20, 0x20, 0x00,          /* "+" */ \
+		0x00, 0x00, 0x00, 0x00, 0x60, 0x20, 0x40,          /* "," */ \
+		0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00,          /* "-" */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x60,          /* "." */ \
+		0x00, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00,          /* "/" */ \
+		0x70, 0x88, 0x98, 0xa8, 0xc8, 0x88, 0x70,          /* "0" */ \
+		0x20, 0x60, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "1" */ \
+		0x70, 0x88, 0x08, 0x10, 0x20, 0x40, 0xf8,          /* "2" */ \
+		0xf8, 0x10, 0x20, 0x10, 0x08, 0x88, 0x70,          /* "3" */ \
+		0x10, 0x30, 0x50, 0x90, 0xf8, 0x10, 0x10,          /* "4" */ \
+		0xf8, 0x80, 0xf0, 0x08, 0x08, 0x88, 0x70,          /* "5" */ \
+		0x30, 0x40, 0x80, 0xf0, 0x88, 0x88, 0x70,          /* "6" */ \
+		0xf8, 0x08, 0x10, 0x20, 0x40, 0x40, 0x40,          /* "7" */ \
+		0x70, 0x88, 0x88, 0x70, 0x88, 0x88, 0x70,          /* "8" */ \
+		0x70, 0x88, 0x88, 0x78, 0x08, 0x10, 0x60,          /* "9" */ \
+		0x00, 0x60, 0x60, 0x00, 0x60, 0x60, 0x00,          /* ":" */ \
+		0x00, 0x60, 0x60, 0x00, 0x60, 0x20, 0x40,          /* ";" */ \
+		0x08, 0x10, 0x20, 0x40, 0x20, 0x10, 0x08,          /* "<" */ \
+		0x00, 0x00, 0xf8, 0x00, 0xf8, 0x00, 0x00,          /* "=" */ \
+		0x80, 0x40, 0x20, 0x10, 0x20, 0x40, 0x80,          /* ">" */ \
+		0x70, 0x88, 0x08, 0x10, 0x20, 0x00, 0x20,          /* "?" */ \
+		0x70, 0x88, 0x08, 0x68, 0xa8, 0xa8, 0x70,          /* "@" */ \
+		0x70, 0x88, 0x88, 0x88, 0xf8, 0x88, 0x88,          /* "A" */ \
+		0xf0, 0x88, 0x88, 0xf0, 0x88, 0x88, 0xf0,          /* "B" */ \
+		0x70, 0x88, 0x80, 0x80, 0x80, 0x88, 0x70,          /* "C" */ \
+		0xe0, 0x90, 0x88, 0x88, 0x88, 0x90, 0xe0,          /* "D" */ \
+		0xf8, 0x80, 0x80, 0xf0, 0x80, 0x80, 0xf8,          /* "E" */ \
+		0xf8, 0x80, 0x80, 0xe0, 0x80, 0x80, 0x80,          /* "F" */ \
+		0x70, 0x88, 0x80, 0x80, 0x98, 0x88, 0x70,          /* "G" */ \
+		0x88, 0x88, 0x88, 0xf8, 0x88, 0x88, 0x88,          /* "H" */ \
+		0x70, 0x20, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "I" */ \
+		0x38, 0x10, 0x10, 0x10, 0x10, 0x90, 0x60,          /* "J" */ \
+		0x88, 0x90, 0xa0, 0xc0, 0xa0, 0x90, 0x88,          /* "K" */ \
+		0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xf8,          /* "L" */ \
+		0x88, 0xd8, 0xa8, 0x88, 0x88, 0x88, 0x88,          /* "M" */ \
+		0x88, 0x88, 0xc8, 0xa8, 0x98, 0x88, 0x88,          /* "N" */ \
+		0x70, 0x88, 0x88, 0x88, 0x88, 0x88, 0x70,          /* "O" */ \
+		0xf0, 0x88, 0x88, 0xf0, 0x80, 0x80, 0x80,          /* "P" */ \
+		0x70, 0x88, 0x88, 0x88, 0xa8, 0x90, 0x68,          /* "Q" */ \
+		0xf0, 0x88, 0x88, 0xf0, 0xa0, 0x90, 0x88,          /* "R" */ \
+		0x78, 0x80, 0x80, 0x70, 0x08, 0x08, 0xf0,          /* "S" */ \
+		0xf8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,          /* "T" */ \
+		0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x70,          /* "U" */ \
+		0x88, 0x88, 0x88, 0x88, 0x88, 0x50, 0x20,          /* "V" */ \
+		0x88, 0x88, 0x88, 0xa8, 0xa8, 0xd8, 0x88,          /* "W" */ \
+		0x88, 0x88, 0x50, 0x20, 0x50, 0x88, 0x88,          /* "X" */ \
+		0x88, 0x88, 0x50, 0x20, 0x20, 0x20, 0x20,          /* "Y" */ \
+		0xf8, 0x08, 0x10, 0x20, 0x40, 0x80, 0xf8,          /* "Z" */ \
+		0x38, 0x20, 0x20, 0x20, 0x20, 0x20, 0x38,          /* "[" */ \
+		0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x00,          /* "\" */ \
+		0xe0, 0x20, 0x20, 0x20, 0x20, 0x20, 0xe0,          /* "]" */ \
+		0x20, 0x50, 0x88, 0x00, 0x00, 0x00, 0x00,          /* "^" */ \
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,          /* "_" */ \
+		0x40, 0x20, 0x10, 0x00, 0x00, 0x00, 0x00,          /* "`" */ \
+		0x00, 0x00, 0x70, 0x08, 0x78, 0x88, 0x78,          /* "a" */ \
+		0x80, 0x80, 0xb0, 0xc8, 0x88, 0x88, 0xf0,          /* "b" */ \
+		0x00, 0x00, 0x70, 0x80, 0x80, 0x88, 0x70,          /* "c" */ \
+		0x08, 0x08, 0x68, 0x98, 0x88, 0x88, 0x78,          /* "d" */ \
+		0x00, 0x00, 0x70, 0x88, 0xf8, 0x80, 0x70,          /* "e" */ \
+		0x30, 0x48, 0x40, 0xe0, 0x40, 0x40, 0x40,          /* "f" */ \
+		0x00, 0x00, 0x78, 0x88, 0x78, 0x08, 0x30,          /* "g" */ \
+		0x80, 0x80, 0xb0, 0xc8, 0x88, 0x88, 0x88,          /* "h" */ \
+		0x20, 0x00, 0x60, 0x20, 0x20, 0x20, 0x70,          /* "i" */ \
+		0x10, 0x00, 0x30, 0x10, 0x10, 0x90, 0x60,          /* "j" */ \
+		0x40, 0x40, 0x48, 0x50, 0x60, 0x50, 0x48,          /* "k" */ \
+		0x60, 0x20, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "l" */ \
+		0x00, 0x00, 0xd0, 0xa8, 0xa8, 0x88, 0x88,          /* "m" */ \
+		0x00, 0x00, 0xb0, 0xc8, 0x88, 0x88, 0x88,          /* "n" */ \
+		0x00, 0x00, 0x70, 0x88, 0x88, 0x88, 0x70,          /* "o" */ \
+		0x00, 0x00, 0xf0, 0x88, 0xf0, 0x80, 0x80,          /* "p" */ \
+		0x00, 0x00, 0x68, 0x98, 0x78, 0x08, 0x08,          /* "q" */ \
+		0x00, 0x00, 0xb0, 0xc8, 0x80, 0x80, 0x80,          /* "r" */ \
+		0x00, 0x00, 0x70, 0x80, 0x70, 0x08, 0xf0,          /* "s" */ \
+		0x40, 0x40, 0xe0, 0x40, 0x40, 0x48, 0x30,          /* "t" */ \
+		0x00, 0x00, 0x88, 0x88, 0x88, 0x98, 0x68,          /* "u" */ \
+		0x00, 0x00, 0x88, 0x88, 0x88, 0x50, 0x20,          /* "v" */ \
+		0x00, 0x00, 0x88, 0x88, 0xa8, 0xa8, 0x50,          /* "w" */ \
+		0x00, 0x00, 0x88, 0x50, 0x20, 0x50, 0x88,          /* "x" */ \
+		0x00, 0x00, 0x88, 0x88, 0x78, 0x08, 0x70,          /* "y" */ \
+		0x00, 0x00, 0xf8, 0x10, 0x20, 0x40, 0xf8,          /* "z" */ \
+		0x10, 0x20, 0x20, 0x40, 0x20, 0x20, 0x10,          /* "{" */ \
+		0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,          /* "|" */ \
+		0x40, 0x20, 0x20, 0x10, 0x20, 0x20, 0x40,          /* "}" */ \
+	};
+#endif
+
+/** @} */
+
+#endif /* CONF_SYSFONT_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.c
new file mode 100644
index 0000000000..cd0d0275c4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.c
@@ -0,0 +1,75 @@
+/**
+ * \file
+ *
+ * \brief Graphical font support
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <assert.h>
+
+#include "conf_sysfont.h"
+
+#include "gfx_mono.h"
+#include "sysfont.h"
+
+// Use macro from conf_sysfont.h to define font glyph data.
+SYSFONT_DEFINE_GLYPHS;
+
+/**
+ * \brief Initialize a basic system font
+ *
+ * This initializes a basic system font globally usable by the application.
+ */
+struct font sysfont = {
+	.type           = FONT_LOC_PROGMEM,
+	.width          = SYSFONT_WIDTH,
+	.height         = SYSFONT_HEIGHT,
+	.first_char     = SYSFONT_FIRSTCHAR,
+	.last_char      = SYSFONT_LASTCHAR,
+	.data           = {
+		.progmem        = sysfont_glyphs,
+	},
+};
+
+/** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.h
new file mode 100644
index 0000000000..837d7c3023
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.h
@@ -0,0 +1,70 @@
+/**
+ * \file
+ *
+ * \brief Graphical System Font system
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SYSFONT_H_INCLUDED
+#define SYSFONT_H_INCLUDED
+
+#include "conf_sysfont.h"
+#include "gfx_mono.h"
+#include "gfx_mono_text.h"
+
+/**
+ * \ingroup asfdoc_common2_gfx_mono_font
+ * \defgroup asfdoc_common2_gfx_mono_sysfont System font
+ *
+ * The system font objects are globally available for a graphical application.
+ * System fonts are by design read only, hence there are not any functions to
+ * change them during runtime. If the application needs additional fonts it
+ * should add additional font objects.
+ * \section asfdoc_common2_gfx_mono_sysfont_api_overview API Overview
+ * @{
+ */
+
+extern struct font sysfont;
+
+/** @} */
+
+#endif /* SYSFONT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/bitmap.py b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/bitmap.py
new file mode 100644
index 0000000000..fcddb9ca48
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/bitmap.py
@@ -0,0 +1,58 @@
+##
+# \file
+#
+# \brief Output a 2 color bitmap as an uint8_t array
+#
+# Copyright (C) 2011-2014 Atmel Corporation. All rights reserved.
+#
+# \page License
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. The name of Atmel may not be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# 4. This software may only be redistributed and used in connection with an
+# Atmel microcontroller product.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from PIL import Image
+import sys
+
+im = Image.open(sys.argv[1]);
+new_im = im.load()
+
+width, height = im.size
+
+for y in range(0, height) :
+	for x in range(0, width) :
+		if 0 < new_im[x, y]:
+			new_im[x, y] = 1
+		sys.stdout.write(str(new_im[x, y]))
+	sys.stdout.write("\n")
+
+sys.stdout.write("\n uint8_t image_header[] = {\n")
+for y in range(0, height, 8) :
+	for x in range(0, width) :
+		first_byte = str(new_im[x, y + 7]) + str(new_im[x, y+6]) + str(new_im[x, y+5]) + str(new_im[x, y+4]) + str(new_im[x, y+3]) + str(new_im[x, y+2]) + str(new_im[x, y+1]) + str(new_im[x, y+0])
+		print "0x%x," % int(first_byte, 2),
+
+sys.stdout.write("};\n")
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/dump_display_over_serial.py b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/dump_display_over_serial.py
new file mode 100644
index 0000000000..5b532420fa
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/dump_display_over_serial.py
@@ -0,0 +1,133 @@
+##
+# \file
+#
+# \brief Convert display data on a serial line to a graphical representation
+#
+# Copyright (C) 2011-2014 Atmel Corporation. All rights reserved.
+#
+# \page License
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. The name of Atmel may not be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# 4. This software may only be redistributed and used in connection with an
+# Atmel microcontroller product.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+import sys
+import serial
+import os.path
+import argparse
+
+def scan_for_ports():
+	available_ports = []
+
+	for index in range(64):
+		try:
+			serial_port = serial.Serial(index)
+			available_ports.append((index, serial_port.portstr))
+			serial_port.close()
+		except serial.SerialException:
+			pass
+		except IndexError as Error:
+			pass
+
+	for port_number, port_name in available_ports:
+		print "%02d - %s" % (port_number, port_name)
+
+	return available_ports
+
+def dump_display_data(serial_port, baud_rate, output_file_name):
+	try:
+		output_file = open(output_file_name, 'w')
+		port        = serial.Serial(port = serial_port,
+				baudrate = baud_rate, timeout = 1)
+		port.close()
+		port.open()
+	except ValueError as e:
+		print "error: invalid serial port parameters. %s" % (str(e))
+		output_file.close()
+		return -1
+	except serial.SerialException as e:
+		print "error: could not open serial port. %s" % (str(e))
+		output_file.close()
+		return -1
+	except IOError as e:
+		print "error: could not open output file. %s" % (str(e))
+		return -1
+
+	print "Display on %s: %u,8,N,1" % (port.name, port.baudrate)
+	port.write("D")
+	line = port.readline()
+	display_data = ""
+	while(line[:2] != "};") :
+		display_data = display_data + line[:-1]
+		line = port.readline()
+	display_data = display_data + line
+	port.close()
+
+	print "Writing data to file %s" % (output_file_name)
+	output_file.write(display_data)
+
+	output_file.close()
+
+def main():
+	parser = argparse.ArgumentParser(description="This script will try to "
+			"open the given serial port, send a string to "
+			"instruct the target device to dump the contents of "
+			"the display to a serial link in XPM format. The "
+			"received file is then written to 'display.xpm', "
+			"unless a file is specified by the -o option.")
+	parser.add_argument("-p", "--port", dest="serial_port",
+			help="which serial port to open")
+	parser.add_argument("-b", "--baud", dest="baudrate", type=int,
+			help="baud rate to use for serial communication",
+			default=19200)
+	parser.add_argument("-o", "--output", dest="output_file",
+			help="write XPM image to FILE. Default is display.xpm.",
+			metavar="FILE", default="display.xpm")
+	parser.add_argument("-s", "--scan", action="store_true",
+			dest="scan_ports",
+			help="scan for available serial ports and exit",
+			default=False)
+
+	arguments = parser.parse_args()
+
+	if arguments.scan_ports:
+		scan_for_ports()
+		sys.exit()
+
+	if arguments.serial_port is None:
+		parser.print_usage()
+		sys.exit()
+
+	if os.path.exists(arguments.output_file):
+		print "Warning: output file '%s' already exists" % (arguments.output_file)
+		print "Do you want to write over file '%s'?" % (arguments.output_file)
+		answer = raw_input("[yes/NO] ")
+		if answer not in ("yes", "Yes", "YES"):
+			sys.exit()
+
+	dump_display_data(arguments.serial_port, arguments.baudrate, arguments.output_file)
+
+if __name__ == "__main__":
+	main()
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/readme.txt b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/readme.txt
new file mode 100644
index 0000000000..ebe2b166ab
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/tools/readme.txt
@@ -0,0 +1,6 @@
+
+dump_display_over_serial.py
+	Convert display data on a serial line to a .XPM file
+
+bitmap.py
+	Convert an indexed 2 color bitmap to an uint8_t array
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/dummy/dummy_board.h b/bsp/samd21/sam_d2x_asflib/sam0/boards/dummy/dummy_board.h
new file mode 100644
index 0000000000..5ea4d98a93
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/dummy/dummy_board.h
@@ -0,0 +1,56 @@
+/*****************************************************************************
+ *
+ * \file
+ *
+ * \brief Dummy board header file.
+ *
+ * This file contains empty definitions to support board-independant applications (e.g. bootloader)
+ *
+ * To use this board, define BOARD=DUMMY_BOARD.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef _DUMMY_BOARD_H_
+#define _DUMMY_BOARD_H_
+
+#endif  // _DUMMY_BOARD_H_
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_config/conf_board.h b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_config/conf_board.h
new file mode 100644
index 0000000000..a1d6bfe3f0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_config/conf_board.h
@@ -0,0 +1,50 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 Xplained Pro board configuration.
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_BOARD_H_INCLUDED
+#define CONF_BOARD_H_INCLUDED
+
+#endif /* CONF_BOARD_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_init.c b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_init.c
new file mode 100644
index 0000000000..9a2327da50
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_init.c
@@ -0,0 +1,97 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 Xplained Pro board initialization
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <board.h>
+#include <conf_board.h>
+#include <port.h>
+
+#if defined(__GNUC__)
+void board_init(void) WEAK __attribute__((alias("system_board_init")));
+#elif defined(__ICCARM__)
+void board_init(void);
+#  pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Configure LEDs as outputs, turn them off */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(LED_0_PIN, &pin_conf);
+	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+
+	/* Set buttons as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
+#ifdef CONF_BOARD_AT86RFX
+	port_get_config_defaults(&pin_conf);
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
+	port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
+	port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
+	port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
+	port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
+	port_pin_set_output_level(AT86RFX_SPI_SCK, true);
+	port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
+	port_pin_set_output_level(AT86RFX_SPI_CS, true);
+	port_pin_set_output_level(AT86RFX_RST_PIN, true);
+	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
+#ifdef EXT_RF_FRONT_END_CTRL	
+	port_pin_set_config(AT86RFX_CPS, &pin_conf);
+	port_pin_set_output_level(AT86RFX_CPS, HIGH);	
+	port_pin_set_config(AT86RFX_CSD, &pin_conf);
+	port_pin_set_output_level(AT86RFX_CSD, HIGH);	
+#endif		
+
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
+	
+#endif
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/gcc/samd20_xplained_pro_flash.gdb b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/gcc/samd20_xplained_pro_flash.gdb
new file mode 100644
index 0000000000..43f7eab3ed
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/gcc/samd20_xplained_pro_flash.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = ATSAMD20J18A
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Initializing PC and stack pointer
+mon reg sp=(0x22008000)
+mon reg pc=(0x00000000)
+info reg
+
+# end of 'reset' command
+end
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/gcc/samd20_xplained_pro_sram.gdb b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/gcc/samd20_xplained_pro_sram.gdb
new file mode 100644
index 0000000000..ee29272b44
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/gcc/samd20_xplained_pro_sram.gdb
@@ -0,0 +1,27 @@
+#*************************************************
+#
+#  Connect to J-Link and debug application in sram.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x22008000)
+mon reg pc=(0x20000000)
+info reg
+
+# end of 'reset' command
+end
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/iar/samd20_xplained_pro_flash.mac b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/iar/samd20_xplained_pro_flash.mac
new file mode 100644
index 0000000000..a524388b57
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/iar/samd20_xplained_pro_flash.mac
@@ -0,0 +1,59 @@
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+
+    // Hardware Reset: CPU is automatically halted after the reset
+    __hwReset(0);
+
+    // peripheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400E1400,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+	// Hardware Reset: CPU is automatically halted after the reset
+    __hwReset(0);
+
+    // peripheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400E1400,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserFlashInit()
+*/
+execUserFlashInit()
+{
+    __message "------------------------------ execUserFlashInit ---------------------------------";
+
+   // perpheral reset RSTC_CR
+   __writeMemory32(0xA5000004,0x400E1400,"Memory");
+
+   //Watch dog disable
+   __writeMemory32(0x000008000,0x400E1454,"Memory");
+
+   // Set 6 WS for Embedded Flash Access
+   __writeMemory32(0x0000600,0x400E0A00,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserFlashExit()
+*/
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+execUserFlashExit()
+{
+    __message "------------------------------ execUserFlashExit ---------------------------------";
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/iar/samd20_xplained_pro_sram.mac b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/iar/samd20_xplained_pro_sram.mac
new file mode 100644
index 0000000000..a524388b57
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/debug_scripts/iar/samd20_xplained_pro_sram.mac
@@ -0,0 +1,59 @@
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+
+    // Hardware Reset: CPU is automatically halted after the reset
+    __hwReset(0);
+
+    // peripheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400E1400,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+	// Hardware Reset: CPU is automatically halted after the reset
+    __hwReset(0);
+
+    // peripheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400E1400,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserFlashInit()
+*/
+execUserFlashInit()
+{
+    __message "------------------------------ execUserFlashInit ---------------------------------";
+
+   // perpheral reset RSTC_CR
+   __writeMemory32(0xA5000004,0x400E1400,"Memory");
+
+   //Watch dog disable
+   __writeMemory32(0x000008000,0x400E1454,"Memory");
+
+   // Set 6 WS for Embedded Flash Access
+   __writeMemory32(0x0000600,0x400E0A00,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserFlashExit()
+*/
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+execUserFlashExit()
+{
+    __message "------------------------------ execUserFlashExit ---------------------------------";
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h
new file mode 100644
index 0000000000..e24a7b0ce0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h
@@ -0,0 +1,609 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 Xplained Pro board definition
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAMD20_XPLAINED_PRO_H_INCLUDED
+#define SAMD20_XPLAINED_PRO_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samd20_xplained_pro_group SAM D20 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samd20_xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME                "SAMD20_XPLAINED_PRO"
+
+/** \name Resonator definitions
+ *  @{ */
+#define BOARD_FREQ_SLCK_XTAL      (32768U)
+#define BOARD_FREQ_SLCK_BYPASS    (32768U)
+#define BOARD_FREQ_MAINCK_XTAL    0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS  0 /* Not Mounted */
+#define BOARD_MCK                 CHIP_FREQ_CPU_MAX
+#define BOARD_OSC_STARTUP_US      15625
+/** @} */
+
+/** \name LED0 definitions
+ *  @{ */
+#define LED0_PIN                  PIN_PA14
+#define LED0_ACTIVE               false
+#define LED0_INACTIVE             !LED0_ACTIVE
+/** @} */
+
+/** \name SW0 definitions
+ *  @{ */
+#define SW0_PIN                   PIN_PA15
+#define SW0_ACTIVE                false
+#define SW0_INACTIVE              !SW0_ACTIVE
+#define SW0_EIC_PIN               PIN_PA15A_EIC_EXTINT15
+#define SW0_EIC_MUX               MUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_PINMUX            PINMUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_LINE              15
+/** @} */
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define LED_0_NAME                "LED0 (yellow)"
+#define LED_0_PIN                 LED0_PIN
+#define LED_0_ACTIVE              LED0_ACTIVE
+#define LED_0_INACTIVE            LED0_INACTIVE
+#define LED0_GPIO 				  LED0_PIN
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT                 1
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define BUTTON_0_NAME             "SW0"
+#define BUTTON_0_PIN              SW0_PIN
+#define BUTTON_0_ACTIVE           SW0_ACTIVE
+#define BUTTON_0_INACTIVE         SW0_INACTIVE
+#define BUTTON_0_EIC_PIN          SW0_EIC_PIN
+#define BUTTON_0_EIC_MUX          SW0_EIC_MUX
+#define BUTTON_0_EIC_PINMUX       SW0_EIC_PINMUX
+#define BUTTON_0_EIC_LINE         SW0_EIC_LINE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+/** \name Extension header #1 pin definitions
+ *  @{
+ */
+#define EXT1_PIN_3                PIN_PB00
+#define EXT1_PIN_4                PIN_PB01
+#define EXT1_PIN_5                PIN_PB06
+#define EXT1_PIN_6                PIN_PB07
+#define EXT1_PIN_7                PIN_PB02
+#define EXT1_PIN_8                PIN_PB03
+#define EXT1_PIN_9                PIN_PB04
+#define EXT1_PIN_10               PIN_PB05
+#define EXT1_PIN_11               PIN_PA08
+#define EXT1_PIN_12               PIN_PA09
+#define EXT1_PIN_13               PIN_PB09
+#define EXT1_PIN_14               PIN_PB08
+#define EXT1_PIN_15               PIN_PA05
+#define EXT1_PIN_16               PIN_PA06
+#define EXT1_PIN_17               PIN_PA04
+#define EXT1_PIN_18               PIN_PA07
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ *  @{
+ */
+#define EXT1_PIN_ADC_0            EXT1_PIN_3
+#define EXT1_PIN_ADC_1            EXT1_PIN_4
+#define EXT1_PIN_GPIO_0           EXT1_PIN_5
+#define EXT1_PIN_GPIO_1           EXT1_PIN_6
+#define EXT1_PIN_PWM_0            EXT1_PIN_7
+#define EXT1_PIN_PWM_1            EXT1_PIN_8
+#define EXT1_PIN_IRQ              EXT1_PIN_9
+#define EXT1_PIN_I2C_SDA          EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL          EXT1_PIN_12
+#define EXT1_PIN_UART_RX          EXT1_PIN_13
+#define EXT1_PIN_UART_TX          EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_1         EXT1_PIN_10
+#define EXT1_PIN_SPI_SS_0         EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI         EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO         EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK          EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ *  @{
+ */
+#define EXT1_ADC_MODULE           ADC
+#define EXT1_ADC_0_CHANNEL        8
+#define EXT1_ADC_0_PIN            PIN_PB00B_ADC_AIN8
+#define EXT1_ADC_0_MUX            MUX_PB00B_ADC_AIN8
+#define EXT1_ADC_0_PINMUX         PINMUX_PB00B_ADC_AIN8
+#define EXT1_ADC_1_CHANNEL        9
+#define EXT1_ADC_1_PIN            PIN_PB01B_ADC_AIN9
+#define EXT1_ADC_1_MUX            MUX_PB01B_ADC_AIN9
+#define EXT1_ADC_1_PINMUX         PINMUX_PB01B_ADC_AIN9
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ *  @{
+ */
+#define EXT1_PWM_MODULE           TC6
+#define EXT1_PWM_0_CHANNEL        0
+#define EXT1_PWM_0_PIN            PIN_PB02F_TC6_WO0
+#define EXT1_PWM_0_MUX            MUX_PB02F_TC6_WO0
+#define EXT1_PWM_0_PINMUX         PINMUX_PB02F_TC6_WO0
+#define EXT1_PWM_1_CHANNEL        1
+#define EXT1_PWM_1_PIN            PIN_PB03F_TC6_WO1
+#define EXT1_PWM_1_MUX            MUX_PB03F_TC6_WO1
+#define EXT1_PWM_1_PINMUX         PINMUX_PB03F_TC6_WO1
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT1_IRQ_MODULE           EIC
+#define EXT1_IRQ_INPUT            4
+#define EXT1_IRQ_PIN              PIN_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_MUX              MUX_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_PINMUX           PINMUX_PB04A_EIC_EXTINT4
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ *  @{
+ */
+#define EXT1_I2C_MODULE              SERCOM2
+#define EXT1_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT1_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ *  @{
+ */
+#define EXT1_UART_MODULE              SERCOM4
+#define EXT1_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT1_UART_SERCOM_PINMUX_PAD0  PINMUX_PB08D_SERCOM4_PAD0
+#define EXT1_UART_SERCOM_PINMUX_PAD1  PINMUX_PB09D_SERCOM4_PAD1
+#define EXT1_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ *  @{
+ */
+#define EXT1_SPI_MODULE              SERCOM0
+#define EXT1_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT1_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA06D_SERCOM0_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA07D_SERCOM0_PAD3
+/** @} */
+
+/** \name Extension header #2 pin definitions
+ *  @{
+ */
+#define EXT2_PIN_3                PIN_PA10
+#define EXT2_PIN_4                PIN_PA11
+#define EXT2_PIN_5                PIN_PA20
+#define EXT2_PIN_6                PIN_PA21
+#define EXT2_PIN_7                PIN_PA22
+#define EXT2_PIN_8                PIN_PA23
+#define EXT2_PIN_9                PIN_PB14
+#define EXT2_PIN_10               PIN_PB15
+#define EXT2_PIN_11               PIN_PA08
+#define EXT2_PIN_12               PIN_PA09
+#define EXT2_PIN_13               PIN_PB13
+#define EXT2_PIN_14               PIN_PB12
+#define EXT2_PIN_15               PIN_PA17
+#define EXT2_PIN_16               PIN_PA18
+#define EXT2_PIN_17               PIN_PA16
+#define EXT2_PIN_18               PIN_PA19
+/** @} */
+
+/** \name Extension header #2 pin definitions by function
+ *  @{
+ */
+#define EXT2_PIN_ADC_0            EXT2_PIN_3
+#define EXT2_PIN_ADC_1            EXT2_PIN_4
+#define EXT2_PIN_GPIO_0           EXT2_PIN_5
+#define EXT2_PIN_GPIO_1           EXT2_PIN_6
+#define EXT2_PIN_PWM_0            EXT2_PIN_7
+#define EXT2_PIN_PWM_1            EXT2_PIN_8
+#define EXT2_PIN_IRQ              EXT2_PIN_9
+#define EXT2_PIN_I2C_SDA          EXT2_PIN_11
+#define EXT2_PIN_I2C_SCL          EXT2_PIN_12
+#define EXT2_PIN_UART_RX          EXT2_PIN_13
+#define EXT2_PIN_UART_TX          EXT2_PIN_14
+#define EXT2_PIN_SPI_SS_1         EXT2_PIN_10
+#define EXT2_PIN_SPI_SS_0         EXT2_PIN_15
+#define EXT2_PIN_SPI_MOSI         EXT2_PIN_16
+#define EXT2_PIN_SPI_MISO         EXT2_PIN_17
+#define EXT2_PIN_SPI_SCK          EXT2_PIN_18
+/** @} */
+
+/** \name Extension header #2 ADC definitions
+ *  @{
+ */
+#define EXT2_ADC_MODULE           ADC
+#define EXT2_ADC_0_CHANNEL        18
+#define EXT2_ADC_0_PIN            PIN_PA10B_ADC_AIN18
+#define EXT2_ADC_0_MUX            MUX_PA10B_ADC_AIN18
+#define EXT2_ADC_0_PINMUX         PINMUX_PA10B_ADC_AIN18
+#define EXT2_ADC_1_CHANNEL        19
+#define EXT2_ADC_1_PIN            PIN_PA11B_ADC_AIN19
+#define EXT2_ADC_1_MUX            MUX_PA11B_ADC_AIN19
+#define EXT2_ADC_1_PINMUX         PINMUX_PA11B_ADC_AIN19
+/** @} */
+
+/** \name Extension header #2 PWM definitions
+ *  @{
+ */
+#define EXT2_PWM_MODULE           TC4
+#define EXT2_PWM_0_CHANNEL        0
+#define EXT2_PWM_0_PIN            PIN_PA22F_TC4_WO0
+#define EXT2_PWM_0_MUX            MUX_PA22F_TC4_WO0
+#define EXT2_PWM_0_PINMUX         PINMUX_PA22F_TC4_WO0
+#define EXT2_PWM_1_CHANNEL        1
+#define EXT2_PWM_1_PIN            PIN_PA23F_TC4_WO1
+#define EXT2_PWM_1_MUX            MUX_PA23F_TC4_WO1
+#define EXT2_PWM_1_PINMUX         PINMUX_PA23F_TC4_WO1
+/** @} */
+
+/** \name Extension header #2 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT2_IRQ_MODULE           EIC
+#define EXT2_IRQ_INPUT            14
+#define EXT2_IRQ_PIN              PIN_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_MUX              MUX_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_PINMUX           PINMUX_PB14A_EIC_EXTINT14
+/** @} */
+
+ /** \name Extension header #2 I2C definitions
+ *  @{
+ */
+#define EXT2_I2C_MODULE              SERCOM2
+#define EXT2_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT2_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+/** @} */
+
+/** \name Extension header #2 UART definitions
+ *  @{
+ */
+#define EXT2_UART_MODULE              SERCOM4
+#define EXT2_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT2_UART_SERCOM_PINMUX_PAD0  PINMUX_PB12C_SERCOM4_PAD0
+#define EXT2_UART_SERCOM_PINMUX_PAD1  PINMUX_PB13C_SERCOM4_PAD1
+#define EXT2_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT2_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+/** @} */
+
+/** \name Extension header #2 SPI definitions
+ *  @{
+ */
+#define EXT2_SPI_MODULE              SERCOM1
+#define EXT2_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT2_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA16C_SERCOM1_PAD0
+#define EXT2_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA17C_SERCOM1_PAD1
+#define EXT2_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA18C_SERCOM1_PAD2
+#define EXT2_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA19C_SERCOM1_PAD3
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ *  @{
+ */
+#define EXT3_PIN_3                PIN_PA02
+#define EXT3_PIN_4                PIN_PA03
+#define EXT3_PIN_5                PIN_PB30
+#define EXT3_PIN_6                PIN_PA15
+#define EXT3_PIN_7                PIN_PA12
+#define EXT3_PIN_8                PIN_PA13
+#define EXT3_PIN_9                PIN_PA28
+#define EXT3_PIN_10               PIN_PA27
+#define EXT3_PIN_11               PIN_PA08
+#define EXT3_PIN_12               PIN_PA09
+#define EXT3_PIN_13               PIN_PB11
+#define EXT3_PIN_14               PIN_PB10
+#define EXT3_PIN_15               PIN_PB17
+#define EXT3_PIN_16               PIN_PB22
+#define EXT3_PIN_17               PIN_PB16
+#define EXT3_PIN_18               PIN_PB23
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ *  @{
+ */
+#define EXT3_PIN_ADC_0            EXT3_PIN_3
+#define EXT3_PIN_ADC_1            EXT3_PIN_4
+#define EXT3_PIN_GPIO_0           EXT3_PIN_5
+#define EXT3_PIN_GPIO_1           EXT3_PIN_6
+#define EXT3_PIN_PWM_0            EXT3_PIN_7
+#define EXT3_PIN_PWM_1            EXT3_PIN_8
+#define EXT3_PIN_IRQ              EXT3_PIN_9
+#define EXT3_PIN_I2C_SDA          EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL          EXT3_PIN_12
+#define EXT3_PIN_UART_RX          EXT3_PIN_13
+#define EXT3_PIN_UART_TX          EXT3_PIN_14
+#define EXT3_PIN_SPI_SS_1         EXT3_PIN_10
+#define EXT3_PIN_SPI_SS_0         EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI         EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO         EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK          EXT3_PIN_18
+/** @} */
+
+/** \name Extension header #3 ADC definitions
+ *  @{
+ */
+#define EXT3_ADC_MODULE           ADC
+#define EXT3_ADC_0_CHANNEL        0
+#define EXT3_ADC_0_PIN            PIN_PA02B_ADC_AIN0
+#define EXT3_ADC_0_MUX            MUX_PA02B_ADC_AIN0
+#define EXT3_ADC_0_PINMUX         PINMUX_PA02B_ADC_AIN0
+#define EXT3_ADC_1_CHANNEL        1
+#define EXT3_ADC_1_PIN            PIN_PA03B_ADC_AIN1
+#define EXT3_ADC_1_MUX            MUX_PA03B_ADC_AIN1
+#define EXT3_ADC_1_PINMUX         PINMUX_PA03B_ADC_AIN1
+/** @} */
+
+/** \name Extension header #3 PWM definitions
+ *  @{
+ */
+#define EXT3_PWM_MODULE           TC2
+#define EXT3_PWM_0_CHANNEL        0
+#define EXT3_PWM_0_PIN            PIN_PA12E_TC2_WO0
+#define EXT3_PWM_0_MUX            MUX_PA12E_TC2_WO0
+#define EXT3_PWM_0_PINMUX         PINMUX_PA12E_TC2_WO0
+#define EXT3_PWM_1_CHANNEL        1
+#define EXT3_PWM_1_PIN            PIN_PA13E_TC2_WO1
+#define EXT3_PWM_1_MUX            MUX_PA13E_TC2_WO1
+#define EXT3_PWM_1_PINMUX         PINMUX_PA13E_TC2_WO1
+/** @} */
+
+/** \name Extension header #3 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT3_IRQ_MODULE           EIC
+#define EXT3_IRQ_INPUT            8
+#define EXT3_IRQ_PIN              PIN_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_MUX              MUX_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_PINMUX           PINMUX_PA28A_EIC_EXTINT8
+/** @} */
+
+/** \name Extension header #3 I2C definitions
+ *  @{
+ */
+#define EXT3_I2C_MODULE              SERCOM2
+#define EXT3_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT3_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+/** @} */
+
+/** \name Extension header #3 UART definitions
+ *  @{
+ */
+#define EXT3_UART_MODULE              SERCOM4
+#define EXT3_UART_SERCOM_MUX_SETTING  USART_RX_3_TX_2_XCK_3
+#define EXT3_UART_SERCOM_PINMUX_PAD0  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD2  PINMUX_PB10D_SERCOM4_PAD2
+#define EXT3_UART_SERCOM_PINMUX_PAD3  PINMUX_PB11D_SERCOM4_PAD3
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ *  @{
+ */
+#define EXT3_SPI_MODULE              SERCOM5
+#define EXT3_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT3_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
+#define EXT3_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB17C_SERCOM5_PAD1
+#define EXT3_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EXT3_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+/** @} */
+
+/** \name Embedded debugger GPIO interface definitions
+ * @{
+ */
+#define EDBG_GPIO0_PIN            PIN_PA27
+#define EDBG_GPIO1_PIN            PIN_PA28
+#define EDBG_GPIO2_PIN            PIN_PA20
+#define EDBG_GPIO3_PIN            PIN_PA21
+/** @} */
+
+/** \name Embedded debugger USART interface definitions
+ * @{
+ */
+#define EDBG_UART_MODULE          -1 /* Not available on this board */
+#define EDBG_UART_RX_PIN          -1 /* Not available on this board */
+#define EDBG_UART_RX_MUX          -1 /* Not available on this board */
+#define EDBG_UART_RX_PINMUX       -1 /* Not available on this board */
+#define EDBG_UART_RX_SERCOM_PAD   -1 /* Not available on this board */
+#define EDBG_UART_TX_PIN          -1 /* Not available on this board */
+#define EDBG_UART_TX_MUX          -1 /* Not available on this board */
+#define EDBG_UART_TX_PINMUX       -1 /* Not available on this board */
+#define EDBG_UART_TX_SERCOM_PAD   -1 /* Not available on this board */
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_I2C_MODULE              SERCOM2
+#define EDBG_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EDBG_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+/** @} */
+
+/** \name Embedded debugger SPI interface definitions
+ * @{
+ */
+#define EDBG_SPI_MODULE              SERCOM5
+#define EDBG_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EDBG_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
+#define EDBG_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB31D_SERCOM5_PAD1
+#define EDBG_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_MODULE              SERCOM3
+#define EDBG_CDC_SERCOM_MUX_SETTING  USART_RX_3_TX_2_XCK_3
+#define EDBG_CDC_SERCOM_PINMUX_PAD0  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD2  PINMUX_PA24C_SERCOM3_PAD2
+#define EDBG_CDC_SERCOM_PINMUX_PAD3  PINMUX_PA25C_SERCOM3_PAD3
+/** @} */
+
+/** @} */
+
+/** @} */
+
+
+
+#define AT86RFX_SPI                  EXT1_SPI_MODULE
+#define AT86RFX_RST_PIN              EXT1_PIN_7
+#define AT86RFX_MISC_PIN             EXT1_PIN_12
+#define AT86RFX_IRQ_PIN              EXT1_PIN_9
+#define AT86RFX_SLP_PIN              EXT1_PIN_10
+#define AT86RFX_SPI_CS               EXT1_PIN_15
+#define AT86RFX_SPI_MOSI             EXT1_PIN_16
+#define AT86RFX_SPI_MISO             EXT1_PIN_17
+#define AT86RFX_SPI_SCK              EXT1_PIN_18
+#define AT86RFX_CSD                  EXT1_PIN_5
+#define AT86RFX_CPS                  EXT1_PIN_8
+#define LED0 LED0_PIN
+
+#define AT86RFX_SPI_SERCOM_MUX_SETTING   EXT1_SPI_SERCOM_MUX_SETTING
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD0   EXT1_SPI_SERCOM_PINMUX_PAD0
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD1   PINMUX_UNUSED
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD2   EXT1_SPI_SERCOM_PINMUX_PAD2
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD3   EXT1_SPI_SERCOM_PINMUX_PAD3
+
+#define AT86RFX_IRQ_CHAN       EXT1_IRQ_INPUT
+#define AT86RFX_IRQ_PINMUX     EXT1_IRQ_PINMUX
+
+
+/** Enables the transceiver main interrupt. */
+#define ENABLE_TRX_IRQ()      \
+		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Disables the transceiver main interrupt. */
+#define DISABLE_TRX_IRQ()     \
+		extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Clears the transceiver main interrupt. */
+#define CLEAR_TRX_IRQ()       \
+		extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+
+/*
+ * This macro saves the trx interrupt status and disables the trx interrupt.
+ */
+#define ENTER_TRX_REGION()   \
+		{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/*
+ *  This macro restores the transceiver interrupt status
+ */
+#define LEAVE_TRX_REGION()   \
+		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+
+/**
+ * \brief Turns off the specified LEDs.
+ *
+ * \param led_gpio LED to turn off (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Off(led_gpio)     port_pin_set_output_level(led_gpio,true)
+
+/**
+ * \brief Turns on the specified LEDs.
+ *
+ * \param led_gpio LED to turn on (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_On(led_gpio)      port_pin_set_output_level(led_gpio,false)
+
+/**
+ * \brief Toggles the specified LEDs.
+ *
+ * \param led_gpio LED to toggle (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Toggle(led_gpio)  port_pin_toggle_output_level(led_gpio)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* SAMD20_XPLAINED_PRO_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_config/conf_board.h b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_config/conf_board.h
new file mode 100644
index 0000000000..52087745e2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_config/conf_board.h
@@ -0,0 +1,50 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board configuration.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_BOARD_H_INCLUDED
+#define CONF_BOARD_H_INCLUDED
+
+#endif /* CONF_BOARD_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_init.c b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_init.c
new file mode 100644
index 0000000000..66cedb3e4e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_init.c
@@ -0,0 +1,90 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board initialization
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <board.h>
+#include <conf_board.h>
+#include <port.h>
+
+#if defined(__GNUC__)
+void board_init(void) WEAK __attribute__((alias("system_board_init")));
+#elif defined(__ICCARM__)
+void board_init(void);
+#  pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Configure LEDs as outputs, turn them off */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(LED_0_PIN, &pin_conf);
+	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+
+	/* Set buttons as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
+	
+#ifdef CONF_BOARD_AT86RFX
+	port_get_config_defaults(&pin_conf);
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
+	port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
+	port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
+	port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
+	port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
+	port_pin_set_output_level(AT86RFX_SPI_SCK, true);
+	port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
+	port_pin_set_output_level(AT86RFX_SPI_CS, true);
+	port_pin_set_output_level(AT86RFX_RST_PIN, true);
+	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
+#endif	
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/gcc/samd21_xplained_pro_flash.gdb b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/gcc/samd21_xplained_pro_flash.gdb
new file mode 100644
index 0000000000..6b3b154f08
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/gcc/samd21_xplained_pro_flash.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = ATSAMD21J18A
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Initializing PC and stack pointer
+mon reg sp=(0x00000000)
+mon reg pc=(0x00000004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/gcc/samd21_xplained_pro_sram.gdb b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/gcc/samd21_xplained_pro_sram.gdb
new file mode 100644
index 0000000000..23bfc87aee
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/gcc/samd21_xplained_pro_sram.gdb
@@ -0,0 +1,24 @@
+#*************************************************
+#
+#  Connect to J-Link and debug application in sram.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Initializing PC and stack pointer
+mon reg sp=(0x20000000)
+mon reg pc=(0x20000004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/iar/samd21_xplained_pro_flash.mac b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/iar/samd21_xplained_pro_flash.mac
new file mode 100644
index 0000000000..89690b9ba8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/iar/samd21_xplained_pro_flash.mac
@@ -0,0 +1,50 @@
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+
+    // Hardware Reset: CPU is automatically halted after the reset
+    __hwReset(0);
+
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+	// Hardware Reset: CPU is automatically halted after the reset
+    __hwReset(0);
+
+}
+
+/*********************************************************************
+*
+*       execUserFlashInit()
+*/
+execUserFlashInit()
+{
+    __message "------------------------------ execUserFlashInit ---------------------------------";
+
+   //Watch dog disable
+   __writeMemory32(0x000000000,0x40001000,"Memory");
+
+}
+
+/*********************************************************************
+*
+*       execUserFlashExit()
+*/
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+execUserFlashExit()
+{
+    __message "------------------------------ execUserFlashExit ---------------------------------";
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/iar/samd21_xplained_pro_sram.mac b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/iar/samd21_xplained_pro_sram.mac
new file mode 100644
index 0000000000..89690b9ba8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/debug_scripts/iar/samd21_xplained_pro_sram.mac
@@ -0,0 +1,50 @@
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+
+    // Hardware Reset: CPU is automatically halted after the reset
+    __hwReset(0);
+
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+	// Hardware Reset: CPU is automatically halted after the reset
+    __hwReset(0);
+
+}
+
+/*********************************************************************
+*
+*       execUserFlashInit()
+*/
+execUserFlashInit()
+{
+    __message "------------------------------ execUserFlashInit ---------------------------------";
+
+   //Watch dog disable
+   __writeMemory32(0x000000000,0x40001000,"Memory");
+
+}
+
+/*********************************************************************
+*
+*       execUserFlashExit()
+*/
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+execUserFlashExit()
+{
+    __message "------------------------------ execUserFlashExit ---------------------------------";
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
new file mode 100644
index 0000000000..39e611773c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
@@ -0,0 +1,709 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board definition
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
+#define SAMD21_XPLAINED_PRO_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samd21_xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME                "SAMD21_XPLAINED_PRO"
+
+/** \name Resonator definitions
+ *  @{ */
+#define BOARD_FREQ_SLCK_XTAL      (32768U)
+#define BOARD_FREQ_SLCK_BYPASS    (32768U)
+#define BOARD_FREQ_MAINCK_XTAL    0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS  0 /* Not Mounted */
+#define BOARD_MCK                 CHIP_FREQ_CPU_MAX
+#define BOARD_OSC_STARTUP_US      15625
+/** @} */
+
+/** \name LED0 definitions
+ *  @{ */
+#define LED0_PIN                  PIN_PB30
+#define LED0_ACTIVE               false
+#define LED0_INACTIVE             !LED0_ACTIVE
+/** @} */
+
+/** \name SW0 definitions
+ *  @{ */
+#define SW0_PIN                   PIN_PA15
+#define SW0_ACTIVE                false
+#define SW0_INACTIVE              !SW0_ACTIVE
+#define SW0_EIC_PIN               PIN_PA15A_EIC_EXTINT15
+#define SW0_EIC_MUX               MUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_PINMUX            PINMUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_LINE              15
+/** @} */
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define LED_0_NAME                "LED0 (yellow)"
+#define LED_0_PIN                 LED0_PIN
+#define LED_0_ACTIVE              LED0_ACTIVE
+#define LED_0_INACTIVE            LED0_INACTIVE
+#define LED0_GPIO                 LED0_PIN
+#define LED0                      LED0_PIN
+
+#define LED_0_PWM4CTRL_MODULE     TCC0
+#define LED_0_PWM4CTRL_CHANNEL    0
+#define LED_0_PWM4CTRL_OUTPUT     0
+#define LED_0_PWM4CTRL_PIN        PIN_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_MUX        MUX_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_PINMUX     PINMUX_PB30E_TCC0_WO0
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT                 1
+
+/**
+ * \name Serialflash definitions
+ *
+ * On board Serialflash definitions.
+ *
+ *  @{ */
+#define SERIALFLASH_SPI_MODULE      SERCOM5
+#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
+#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define SERIALFLASH_SPI_CS PIN_PA13
+/** @} */
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define BUTTON_0_NAME             "SW0"
+#define BUTTON_0_PIN              SW0_PIN
+#define BUTTON_0_ACTIVE           SW0_ACTIVE
+#define BUTTON_0_INACTIVE         SW0_INACTIVE
+#define BUTTON_0_EIC_PIN          SW0_EIC_PIN
+#define BUTTON_0_EIC_MUX          SW0_EIC_MUX
+#define BUTTON_0_EIC_PINMUX       SW0_EIC_PINMUX
+#define BUTTON_0_EIC_LINE         SW0_EIC_LINE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+/** \name Extension header #1 pin definitions
+ *  @{
+ */
+#define EXT1_PIN_3                PIN_PB00
+#define EXT1_PIN_4                PIN_PB01
+#define EXT1_PIN_5                PIN_PB06
+#define EXT1_PIN_6                PIN_PB07
+#define EXT1_PIN_7                PIN_PB02
+#define EXT1_PIN_8                PIN_PB03
+#define EXT1_PIN_9                PIN_PB04
+#define EXT1_PIN_10               PIN_PB05
+#define EXT1_PIN_11               PIN_PA08
+#define EXT1_PIN_12               PIN_PA09
+#define EXT1_PIN_13               PIN_PB09
+#define EXT1_PIN_14               PIN_PB08
+#define EXT1_PIN_15               PIN_PA05
+#define EXT1_PIN_16               PIN_PA06
+#define EXT1_PIN_17               PIN_PA04
+#define EXT1_PIN_18               PIN_PA07
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ *  @{
+ */
+#define EXT1_PIN_ADC_0            EXT1_PIN_3
+#define EXT1_PIN_ADC_1            EXT1_PIN_4
+#define EXT1_PIN_GPIO_0           EXT1_PIN_5
+#define EXT1_PIN_GPIO_1           EXT1_PIN_6
+#define EXT1_PIN_PWM_0            EXT1_PIN_7
+#define EXT1_PIN_PWM_1            EXT1_PIN_8
+#define EXT1_PIN_IRQ              EXT1_PIN_9
+#define EXT1_PIN_I2C_SDA          EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL          EXT1_PIN_12
+#define EXT1_PIN_UART_RX          EXT1_PIN_13
+#define EXT1_PIN_UART_TX          EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_1         EXT1_PIN_10
+#define EXT1_PIN_SPI_SS_0         EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI         EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO         EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK          EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ *  @{
+ */
+#define EXT1_ADC_MODULE           ADC
+#define EXT1_ADC_0_CHANNEL        8
+#define EXT1_ADC_0_PIN            PIN_PB00B_ADC_AIN8
+#define EXT1_ADC_0_MUX            MUX_PB00B_ADC_AIN8
+#define EXT1_ADC_0_PINMUX         PINMUX_PB00B_ADC_AIN8
+#define EXT1_ADC_1_CHANNEL        9
+#define EXT1_ADC_1_PIN            PIN_PB01B_ADC_AIN9
+#define EXT1_ADC_1_MUX            MUX_PB01B_ADC_AIN9
+#define EXT1_ADC_1_PINMUX         PINMUX_PB01B_ADC_AIN9
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ *  @{
+ */
+#define EXT1_PWM_MODULE           TC6
+#define EXT1_PWM_0_CHANNEL        0
+#define EXT1_PWM_0_PIN            PIN_PB02E_TC6_WO0
+#define EXT1_PWM_0_MUX            MUX_PB02E_TC6_WO0
+#define EXT1_PWM_0_PINMUX         PINMUX_PB02E_TC6_WO0
+#define EXT1_PWM_1_CHANNEL        1
+#define EXT1_PWM_1_PIN            PIN_PB03E_TC6_WO1
+#define EXT1_PWM_1_MUX            MUX_PB03E_TC6_WO1
+#define EXT1_PWM_1_PINMUX         PINMUX_PB03E_TC6_WO1
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT1_IRQ_MODULE           EIC
+#define EXT1_IRQ_INPUT            4
+#define EXT1_IRQ_PIN              PIN_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_MUX              MUX_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_PINMUX           PINMUX_PB04A_EIC_EXTINT4
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ *  @{
+ */
+#define EXT1_I2C_MODULE              SERCOM2
+#define EXT1_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT1_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT1_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT1_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ *  @{
+ */
+#define EXT1_UART_MODULE              SERCOM4
+#define EXT1_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT1_UART_SERCOM_PINMUX_PAD0  PINMUX_PB08D_SERCOM4_PAD0
+#define EXT1_UART_SERCOM_PINMUX_PAD1  PINMUX_PB09D_SERCOM4_PAD1
+#define EXT1_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT1_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ *  @{
+ */
+#define EXT1_SPI_MODULE              SERCOM0
+#define EXT1_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT1_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA06D_SERCOM0_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA07D_SERCOM0_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX   SERCOM0_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX   SERCOM0_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 pin definitions
+ *  @{
+ */
+#define EXT2_PIN_3                PIN_PA10
+#define EXT2_PIN_4                PIN_PA11
+#define EXT2_PIN_5                PIN_PA20
+#define EXT2_PIN_6                PIN_PA21
+#define EXT2_PIN_7                PIN_PB12
+#define EXT2_PIN_8                PIN_PB13
+#define EXT2_PIN_9                PIN_PB14
+#define EXT2_PIN_10               PIN_PB15
+#define EXT2_PIN_11               PIN_PA08
+#define EXT2_PIN_12               PIN_PA09
+#define EXT2_PIN_13               PIN_PB11
+#define EXT2_PIN_14               PIN_PB10
+#define EXT2_PIN_15               PIN_PA17
+#define EXT2_PIN_16               PIN_PA18
+#define EXT2_PIN_17               PIN_PA16
+#define EXT2_PIN_18               PIN_PA19
+/** @} */
+
+/** \name Extension header #2 pin definitions by function
+ *  @{
+ */
+#define EXT2_PIN_ADC_0            EXT2_PIN_3
+#define EXT2_PIN_ADC_1            EXT2_PIN_4
+#define EXT2_PIN_GPIO_0           EXT2_PIN_5
+#define EXT2_PIN_GPIO_1           EXT2_PIN_6
+#define EXT2_PIN_PWM_0            EXT2_PIN_7
+#define EXT2_PIN_PWM_1            EXT2_PIN_8
+#define EXT2_PIN_IRQ              EXT2_PIN_9
+#define EXT2_PIN_I2C_SDA          EXT2_PIN_11
+#define EXT2_PIN_I2C_SCL          EXT2_PIN_12
+#define EXT2_PIN_UART_RX          EXT2_PIN_13
+#define EXT2_PIN_UART_TX          EXT2_PIN_14
+#define EXT2_PIN_SPI_SS_1         EXT2_PIN_10
+#define EXT2_PIN_SPI_SS_0         EXT2_PIN_15
+#define EXT2_PIN_SPI_MOSI         EXT2_PIN_16
+#define EXT2_PIN_SPI_MISO         EXT2_PIN_17
+#define EXT2_PIN_SPI_SCK          EXT2_PIN_18
+/** @} */
+
+/** \name Extension header #2 ADC definitions
+ *  @{
+ */
+#define EXT2_ADC_MODULE           ADC
+#define EXT2_ADC_0_CHANNEL        18
+#define EXT2_ADC_0_PIN            PIN_PA10B_ADC_AIN18
+#define EXT2_ADC_0_MUX            MUX_PA10B_ADC_AIN18
+#define EXT2_ADC_0_PINMUX         PINMUX_PA10B_ADC_AIN18
+#define EXT2_ADC_1_CHANNEL        19
+#define EXT2_ADC_1_PIN            PIN_PA11B_ADC_AIN19
+#define EXT2_ADC_1_MUX            MUX_PA11B_ADC_AIN19
+#define EXT2_ADC_1_PINMUX         PINMUX_PA11B_ADC_AIN19
+/** @} */
+
+/** \name Extension header #2 PWM definitions
+ *  @{
+ */
+#define EXT2_PWM_MODULE           TC4
+#define EXT2_PWM_0_CHANNEL        0
+#define EXT2_PWM_0_PIN            PIN_PB12E_TC4_WO0
+#define EXT2_PWM_0_MUX            MUX_PB12E_TC4_WO0
+#define EXT2_PWM_0_PINMUX         PINMUX_PB12E_TC4_WO0
+#define EXT2_PWM_1_CHANNEL        1
+#define EXT2_PWM_1_PIN            PIN_PB13E_TC4_WO1
+#define EXT2_PWM_1_MUX            MUX_PB13E_TC4_WO1
+#define EXT2_PWM_1_PINMUX         PINMUX_PB13E_TC4_WO1
+/** @} */
+
+/** \name Extension header #2 PWM for Control definitions
+ *  @{
+ */
+#define EXT2_PWM4CTRL_MODULE      TCC0
+#define EXT2_PWM4CTRL_0_CHANNEL   2
+#define EXT2_PWM4CTRL_0_OUTPUT    6
+#define EXT2_PWM4CTRL_0_PIN       PIN_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_MUX       MUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_PINMUX    PINMUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_1_CHANNEL   3
+#define EXT2_PWM4CTRL_1_OUTPUT    7
+#define EXT2_PWM4CTRL_1_PIN       PIN_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_MUX       MUX_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_PINMUX    PINMUX_PB13F_TCC0_WO7
+/** @} */
+
+/** \name Extension header #2 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT2_IRQ_MODULE           EIC
+#define EXT2_IRQ_INPUT            14
+#define EXT2_IRQ_PIN              PIN_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_MUX              MUX_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_PINMUX           PINMUX_PB14A_EIC_EXTINT14
+/** @} */
+
+ /** \name Extension header #2 I2C definitions
+ *  @{
+ */
+#define EXT2_I2C_MODULE              SERCOM2
+#define EXT2_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT2_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT2_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT2_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 UART definitions
+ *  @{
+ */
+#define EXT2_UART_MODULE              SERCOM4
+#define EXT2_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT2_UART_SERCOM_PINMUX_PAD0  PINMUX_PB12C_SERCOM4_PAD0
+#define EXT2_UART_SERCOM_PINMUX_PAD1  PINMUX_PB13C_SERCOM4_PAD1
+#define EXT2_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT2_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EXT2_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT2_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 SPI definitions
+ *  @{
+ */
+#define EXT2_SPI_MODULE              SERCOM1
+#define EXT2_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT2_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA16C_SERCOM1_PAD0
+#define EXT2_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA17C_SERCOM1_PAD1
+#define EXT2_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA18C_SERCOM1_PAD2
+#define EXT2_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA19C_SERCOM1_PAD3
+#define EXT2_SPI_SERCOM_DMAC_ID_TX   SERCOM1_DMAC_ID_TX
+#define EXT2_SPI_SERCOM_DMAC_ID_RX   SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ *  @{
+ */
+#define EXT3_PIN_3                PIN_PA02
+#define EXT3_PIN_4                PIN_PA03
+#define EXT3_PIN_5                PIN_PB30
+#define EXT3_PIN_6                PIN_PA15
+#define EXT3_PIN_7                PIN_PA12
+#define EXT3_PIN_8                PIN_PA13
+#define EXT3_PIN_9                PIN_PA28
+#define EXT3_PIN_10               PIN_PA27
+#define EXT3_PIN_11               PIN_PA08
+#define EXT3_PIN_12               PIN_PA09
+#define EXT3_PIN_13               PIN_PB11
+#define EXT3_PIN_14               PIN_PB10
+#define EXT3_PIN_15               PIN_PB17
+#define EXT3_PIN_16               PIN_PB22
+#define EXT3_PIN_17               PIN_PB16
+#define EXT3_PIN_18               PIN_PB23
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ *  @{
+ */
+#define EXT3_PIN_ADC_0            EXT3_PIN_3
+#define EXT3_PIN_ADC_1            EXT3_PIN_4
+#define EXT3_PIN_GPIO_0           EXT3_PIN_5
+#define EXT3_PIN_GPIO_1           EXT3_PIN_6
+#define EXT3_PIN_PWM_0            EXT3_PIN_7
+#define EXT3_PIN_PWM_1            EXT3_PIN_8
+#define EXT3_PIN_IRQ              EXT3_PIN_9
+#define EXT3_PIN_I2C_SDA          EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL          EXT3_PIN_12
+#define EXT3_PIN_UART_RX          EXT3_PIN_13
+#define EXT3_PIN_UART_TX          EXT3_PIN_14
+#define EXT3_PIN_SPI_SS_1         EXT3_PIN_10
+#define EXT3_PIN_SPI_SS_0         EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI         EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO         EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK          EXT3_PIN_18
+/** @} */
+
+/** \name Extension header #3 ADC definitions
+ *  @{
+ */
+#define EXT3_ADC_MODULE           ADC
+#define EXT3_ADC_0_CHANNEL        0
+#define EXT3_ADC_0_PIN            PIN_PA02B_ADC_AIN0
+#define EXT3_ADC_0_MUX            MUX_PA02B_ADC_AIN0
+#define EXT3_ADC_0_PINMUX         PINMUX_PA02B_ADC_AIN0
+#define EXT3_ADC_1_CHANNEL        1
+#define EXT3_ADC_1_PIN            PIN_PA03B_ADC_AIN1
+#define EXT3_ADC_1_MUX            MUX_PA03B_ADC_AIN1
+#define EXT3_ADC_1_PINMUX         PINMUX_PA03B_ADC_AIN1
+/** @} */
+
+/** \name Extension header #3 PWM for Control definitions
+ *  @{
+ */
+#define EXT3_PWM4CTRL_MODULE      TCC2
+#define EXT3_PWM4CTRL_0_CHANNEL   0
+#define EXT3_PWM4CTRL_0_OUTPUT    0
+#define EXT3_PWM4CTRL_0_PIN       PIN_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_MUX       MUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_PINMUX    PINMUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_1_CHANNEL   1
+#define EXT3_PWM4CTRL_1_OUTPUT    1
+#define EXT3_PWM4CTRL_1_PIN       PIN_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_MUX       MUX_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_PINMUX    PINMUX_PA13E_TCC2_WO1
+/** @} */
+
+/** \name Extension header #3 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT3_IRQ_MODULE           EIC
+#define EXT3_IRQ_INPUT            8
+#define EXT3_IRQ_PIN              PIN_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_MUX              MUX_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_PINMUX           PINMUX_PA28A_EIC_EXTINT8
+/** @} */
+
+/** \name Extension header #3 I2C definitions
+ *  @{
+ */
+#define EXT3_I2C_MODULE              SERCOM2
+#define EXT3_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT3_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT3_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT3_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 UART definitions
+ *  @{
+ */
+#define EXT3_UART_MODULE              SERCOM4
+#define EXT3_UART_SERCOM_MUX_SETTING  USART_RX_3_TX_2_XCK_3
+#define EXT3_UART_SERCOM_PINMUX_PAD0  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD2  PINMUX_PB10D_SERCOM4_PAD2
+#define EXT3_UART_SERCOM_PINMUX_PAD3  PINMUX_PB11D_SERCOM4_PAD3
+#define EXT3_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT3_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ *  @{
+ */
+#define EXT3_SPI_MODULE              SERCOM5
+#define EXT3_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT3_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
+#define EXT3_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB17C_SERCOM5_PAD1
+#define EXT3_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EXT3_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EXT3_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EXT3_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 Dataflash
+ *  @{
+ */
+#define EXT3_DATAFLASH_SPI_MODULE      EXT3_SPI_MODULE
+#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
+/** @} */
+
+/** \name USB definitions
+ * @{
+ */
+#define USB_ID
+#define USB_TARGET_DP_PIN            PIN_PA25G_USB_DP
+#define USB_TARGET_DP_MUX            MUX_PA25G_USB_DP
+#define USB_TARGET_DP_PINMUX         PINMUX_PA25G_USB_DP
+#define USB_TARGET_DM_PIN            PIN_PA24G_USB_DM
+#define USB_TARGET_DM_MUX            MUX_PA24G_USB_DM
+#define USB_TARGET_DM_PINMUX         PINMUX_PA24G_USB_DM
+#define USB_VBUS_PIN                 PIN_PA14
+#define USB_VBUS_EIC_LINE            14
+#define USB_VBUS_EIC_MUX             MUX_PA14A_EIC_EXTINT14
+#define USB_VBUS_EIC_PINMUX          PINMUX_PA14A_EIC_EXTINT14
+#define USB_ID_PIN                   PIN_PA03
+#define USB_ID_EIC_LINE              3
+#define USB_ID_EIC_MUX               MUX_PA03A_EIC_EXTINT3
+#define USB_ID_EIC_PINMUX            PINMUX_PA03A_EIC_EXTINT3
+/** @} */
+
+/** \name Embedded debugger GPIO interface definitions
+ * @{
+ */
+#define EDBG_GPIO0_PIN            PIN_PA27
+#define EDBG_GPIO1_PIN            PIN_PA28
+#define EDBG_GPIO2_PIN            PIN_PA20
+#define EDBG_GPIO3_PIN            PIN_PA21
+/** @} */
+
+/** \name Embedded debugger USART interface definitions
+ * @{
+ */
+#define EDBG_UART_MODULE          -1 /* Not available on this board */
+#define EDBG_UART_RX_PIN          -1 /* Not available on this board */
+#define EDBG_UART_RX_MUX          -1 /* Not available on this board */
+#define EDBG_UART_RX_PINMUX       -1 /* Not available on this board */
+#define EDBG_UART_RX_SERCOM_PAD   -1 /* Not available on this board */
+#define EDBG_UART_TX_PIN          -1 /* Not available on this board */
+#define EDBG_UART_TX_MUX          -1 /* Not available on this board */
+#define EDBG_UART_TX_PINMUX       -1 /* Not available on this board */
+#define EDBG_UART_TX_SERCOM_PAD   -1 /* Not available on this board */
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_I2C_MODULE              SERCOM2
+#define EDBG_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EDBG_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EDBG_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EDBG_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger SPI interface definitions
+ * @{
+ */
+#define EDBG_SPI_MODULE              SERCOM5
+#define EDBG_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EDBG_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
+#define EDBG_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB31D_SERCOM5_PAD1
+#define EDBG_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EDBG_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EDBG_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_MODULE              SERCOM3
+#define EDBG_CDC_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EDBG_CDC_SERCOM_PINMUX_PAD0  PINMUX_PA22C_SERCOM3_PAD0
+#define EDBG_CDC_SERCOM_PINMUX_PAD1  PINMUX_PA23C_SERCOM3_PAD1
+#define EDBG_CDC_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_DMAC_ID_TX   SERCOM3_DMAC_ID_TX
+#define EDBG_CDC_SERCOM_DMAC_ID_RX   SERCOM3_DMAC_ID_RX
+/** @} */
+
+/** @} */
+
+/** \name 802.15.4 TRX Interface definitions
+ * @{
+ */
+#ifndef EXT2_CONFIG
+#define AT86RFX_SPI                  EXT1_SPI_MODULE
+#define AT86RFX_RST_PIN              EXT1_PIN_7
+#define AT86RFX_MISC_PIN             EXT1_PIN_12
+#define AT86RFX_IRQ_PIN              EXT1_PIN_9
+#define AT86RFX_SLP_PIN              EXT1_PIN_10
+#define AT86RFX_SPI_CS               EXT1_PIN_15
+#define AT86RFX_SPI_MOSI             EXT1_PIN_16
+#define AT86RFX_SPI_MISO             EXT1_PIN_17
+#define AT86RFX_SPI_SCK              EXT1_PIN_18
+#define AT86RFX_CSD                  EXT1_PIN_5
+#define AT86RFX_CPS                  EXT1_PIN_8
+
+#define AT86RFX_SPI_SERCOM_MUX_SETTING   EXT1_SPI_SERCOM_MUX_SETTING
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD0   EXT1_SPI_SERCOM_PINMUX_PAD0
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD1   PINMUX_UNUSED
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD2   EXT1_SPI_SERCOM_PINMUX_PAD2
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD3   EXT1_SPI_SERCOM_PINMUX_PAD3
+
+#define AT86RFX_IRQ_CHAN       EXT1_IRQ_INPUT
+#define AT86RFX_IRQ_PINMUX     EXT1_IRQ_PINMUX
+
+
+#endif
+/** Enables the transceiver main interrupt. */
+#define ENABLE_TRX_IRQ()     \
+		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Disables the transceiver main interrupt. */
+#define DISABLE_TRX_IRQ()    \
+		extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Clears the transceiver main interrupt. */
+#define CLEAR_TRX_IRQ()      \
+		extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+
+/*
+ * This macro saves the trx interrupt status and disables the trx interrupt.
+ */
+#define ENTER_TRX_REGION()   \
+		{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/*
+ *  This macro restores the transceiver interrupt status
+ */
+#define LEAVE_TRX_REGION()   \
+		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+
+/** @} */
+
+/**
+ * \brief Turns off the specified LEDs.
+ *
+ * \param led_gpio LED to turn off (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Off(led_gpio)     port_pin_set_output_level(led_gpio,true)
+
+/**
+ * \brief Turns on the specified LEDs.
+ *
+ * \param led_gpio LED to turn on (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_On(led_gpio)      port_pin_set_output_level(led_gpio,false)
+
+/**
+ * \brief Toggles the specified LEDs.
+ *
+ * \param led_gpio LED to toggle (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Toggle(led_gpio)  port_pin_toggle_output_level(led_gpio)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* SAMD21_XPLAINED_PRO_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac.h
new file mode 100644
index 0000000000..1003b93088
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac.h
@@ -0,0 +1,1436 @@
+/**
+ * \file
+ *
+ * \brief SAM Analog Comparator Driver
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef AC_H_INCLUDED
+#define AC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_ac_group SAM Analog Comparator (AC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers
+ * provides an interface for the configuration
+ * and management of the device's Analog Comparator functionality, for the
+ * comparison of analog voltages against a known reference voltage to determine
+ * its relative level. The following driver API modes are covered by this
+ * manual:
+ * - Polled APIs
+ * \if AC_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripherals are used by this module:
+ *  - AC (Analog Comparator)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_ac_prerequisites
+ *  - \ref asfdoc_sam0_ac_module_overview
+ *  - \ref asfdoc_sam0_ac_special_considerations
+ *  - \ref asfdoc_sam0_ac_extra_info
+ *  - \ref asfdoc_sam0_ac_examples
+ *  - \ref asfdoc_sam0_ac_api_overview
+ *
+ *
+ * \section asfdoc_sam0_ac_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_ac_module_overview Module Overview
+ *
+ * The Analog Comparator module provides an interface for the comparison of one
+ * or more analog voltage inputs (sourced from external or internal inputs)
+ * against a known reference voltage, to determine if the unknown voltage is
+ * higher or lower than the reference. Additionally, window functions are
+ * provided so that two comparators can be connected together to determine if
+ * an input is below, inside, above, or outside the two reference points of the
+ * window.
+ *
+ * Each comparator requires two analog input voltages, a positive and negative
+ * channel input. The result of the comparison is a binary \c true if the
+ * comparator's positive channel input is higher than the comparator's negative
+ * input channel, and \c false if otherwise.
+ *
+ *
+ * \subsection asfdoc_sam0_ac_module_features Driver Feature Macro Definition
+ * <table>
+ *    <tr>
+ *      <th>Driver Feature Macro</th>
+ *      <th>Supported devices</th>
+ *    </tr>
+ *    <tr>
+ *      <td>FEATURE_AC_HYSTERESIS_LEVEL</td>
+ *      <td>SAM L21/L22/C20/C21</td>
+ *    </tr>
+ *    <tr>
+ *      <td>FEATURE_AC_SYNCBUSY_SCHEME_VERSION_2</td>
+ *      <td>SAM L21/L22/C20/C21</td>
+ *    </tr>
+ *    <tr>
+ *      <td>FEATURE_AC_RUN_IN_STANDY_EACH_COMPARATOR</td>
+ *      <td>SAM L21/L22/C20/C21</td>
+ *    </tr>
+ *    <tr>
+ *      <td>FEATURE_AC_RUN_IN_STANDY_PAIR_COMPARATOR</td>
+ *      <td>SAM D20/L22/D21/D10/D11/R21/DA1/HA1</td>
+ *    </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_ac_module_overview_pairs Window Comparators and Comparator Pairs
+ * Each comparator module contains one or more comparator pairs, a set of two
+ * distinct comparators which can be used independently or linked together for
+ * Window Comparator mode. In this latter mode, the two comparator units in a
+ * comparator pair are linked together to allow the module to detect if an input
+ * voltage is below, inside, above, or outside a window set by the upper and
+ * lower threshold voltages set by the two comparators. If not required, window
+ * comparison mode can be turned off and the two comparator units can be
+ * configured and used separately.
+ *
+ * \subsection asfdoc_sam0_ac_module_overview_pos_neg_mux Positive and Negative Input MUXes
+ * Each comparator unit requires two input voltages, a positive and a negative
+ * channel (note that these names refer to the logical operation that the unit
+ * performs, and both voltages should be above GND), which are then compared with
+ * one another. Both the positive and the negative channel inputs are connected to
+ * a pair of multiplexers (MUXes), which allows one of several possible inputs to be 
+ * selected for each comparator channel.
+ *
+ * The exact channels available for each comparator differ for the positive and
+ * the negative inputs, but the same MUX choices are available for all comparator
+ * units (i.e. all positive MUXes are identical, all negative MUXes are
+ * identical). This allows the user application to select which voltages are
+ * compared to one another.
+ *
+ * When used in window mode, both comparators in the window pair should have
+ * their positive channel input MUXes configured to the same input channel, with
+ * the negative channel input MUXes used to set the lower and upper window
+ * bounds.
+ *
+ * \subsection asfdoc_sam0_ac_module_overview_output_filtering Output Filtering
+ * The output of each comparator unit can either be used directly with no
+ * filtering (giving a lower latency signal, with potentially more noise around
+ * the comparison threshold) or be passed through a multiple stage
+ * digital majority filter. Several filter lengths are available, with the
+ * longer stages producing a more stable result, at the expense of a higher
+ * latency.
+ *
+ * When output filtering is used in single shot mode, a single trigger of the
+ * comparator will automatically perform the required number of samples to
+ * produce a correctly filtered result.
+ *
+ * \subsection asfdoc_sam0_ac_module_overview_input_hysteresis Input Hysteresis
+ * To prevent unwanted noise around the threshold where the comparator unit's
+ * positive and negative input channels are close in voltage to one another, an
+ * optional hysteresis can be used to widen the point at which the output result
+ * flips. This mode will prevent a change in the comparison output unless the
+ * inputs cross one another beyond the hysteresis gap introduces by this mode.
+ *
+ * \subsection asfdoc_sam0_ac_module_overview_sampling Single Shot and Continuous Sampling Modes
+ * Comparators can be configured to run in either Single Shot or Continuous
+ * sampling modes; when in Single Shot mode, the comparator will only perform a
+ * comparison (and any resulting filtering, see
+ * \ref asfdoc_sam0_ac_module_overview_output_filtering) when triggered via a
+ * software or event trigger. This mode improves the power efficiency of the
+ * system by only performing comparisons when actually required by the
+ * application.
+ *
+ * For systems requiring a lower latency or more frequent comparisons,
+ * continuous mode will place the comparator into continuous sampling mode,
+ * which increases the module's power consumption, but decreases the latency
+ * between each comparison result by automatically performing a comparison on
+ * every cycle of the module's clock.
+ *
+ * \subsection asfdoc_sam0_ac_module_overview_events Events
+ * Each comparator unit is capable of being triggered by both software and
+ * hardware triggers. Hardware input events allow for other peripherals to
+ * automatically trigger a comparison on demand - for example, a timer output
+ * event could be used to trigger comparisons at a desired regular interval.
+ *
+ * The module's output events can similarly be used to trigger other hardware
+ * modules each time a new comparison result is available. This scheme allows
+ * for reduced levels of CPU usage in an application and lowers the overall
+ * system response latency by directly triggering hardware peripherals from one
+ * another without requiring software intervention.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * \subsection asfdoc_sam0_ac_module_overview_physical Physical Connection
+ * Physically, the modules are interconnected within the device as shown in
+ * \ref asfdoc_sam0_ac_module_int_connections "the diagram below".
+ *
+ * \anchor asfdoc_sam0_ac_module_int_connections
+ * \dot
+ * digraph overview {
+ *  rankdir = LR;
+ *  splines = false;
+ *
+ *  pos_src1_1 [label="GPIO Pins", shape=none, height=0];
+ *  neg_src1_1 [label="GPIO Pins", shape=none, height=0];
+ *  neg_src1_2 [label="Internal DAC", shape=none, height=0];
+ *  neg_src1_3 [label="Internal Refs", shape=none, height=0];
+ *  pos_src2_1 [label="GPIO Pins", shape=none, height=0];
+ *  neg_src2_1 [label="GPIO Pins", shape=none, height=0];
+ *  neg_src2_2 [label="Internal DAC", shape=none, height=0];
+ *  neg_src2_3 [label="Internal Refs", shape=none, height=0];
+ *  res_out1 [label="", style=invisible];
+ *  res_out2 [label="", style=invisible];
+ *  res_window [label="", style=invisible];
+ *
+ *  mux_pos1 [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2];
+ *  mux_neg1 [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2];
+ *  mux_neg2 [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2];
+ *  mux_pos2 [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2];
+ *  ac1 [label="AC 1", shape=triangle, orientation=-90, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ *  ac2 [label="AC 2", shape=triangle, orientation=-90, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ *
+ *  window_comp [label="Window\nLogic", shape=rectangle style=filled fillcolor=lightgray];
+ *
+ *  edge [dir="forward"];
+ *
+ *  pos_src1_1:e -> mux_pos1:w;
+ *  mux_pos1:e -> ac1:nw [label="+"];
+ *  neg_src1_1:e -> mux_neg1:nw;
+ *  neg_src1_2:e -> mux_neg1:w;
+ *  neg_src1_3:e -> mux_neg1:sw;
+ *  mux_neg1:e -> ac1:sw [label="-"];
+ *  ac1:e -> res_out1 [label="Comparator 1 Result"];
+ *
+ *  pos_src2_1:e -> mux_pos2:w;
+ *  mux_pos2:e -> ac2:sw [label="+"];
+ *  neg_src2_1:e -> mux_neg2:nw;
+ *  neg_src2_2:e -> mux_neg2:w;
+ *  neg_src2_3:e -> mux_neg2:sw;
+ *  mux_neg2:e -> ac2:nw [label="-"];
+ *  ac2:e -> res_out2 [label="Comparator 2 Result"];
+ *
+ *  ac1:e -> window_comp:nw;
+ *  ac2:e -> window_comp:sw;
+ *  window_comp:e -> res_window:w [label="Window Result"];
+ *
+ *  {rank=same; pos_src1_1 neg_src1_1 neg_src1_2 neg_src1_3 pos_src2_1 neg_src2_1 neg_src2_2 neg_src2_3 }
+ *  {rank=same; mux_pos1 mux_neg1 mux_pos2 mux_neg2 }
+ *  {rank=same; ac1 ac2 }
+ *  {rank=same; res_out1 res_out2 res_window }
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_ac_special_considerations Special Considerations
+ *
+ * The number of comparator pairs (and, thus, window comparators) within a
+ * single hardware instance of the Analog Comparator module is device-specific.
+ * Some devices will contain a single comparator pair, while others may have two
+ * pairs; refer to your device specific datasheet for details.
+ *
+ *
+ * \section asfdoc_sam0_ac_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_ac_extra. This includes:
+ *  - \ref asfdoc_sam0_ac_extra_acronyms
+ *  - \ref asfdoc_sam0_ac_extra_dependencies
+ *  - \ref asfdoc_sam0_ac_extra_errata
+ *  - \ref asfdoc_sam0_ac_extra_history
+ *
+ *
+ * \section asfdoc_sam0_ac_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_ac_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_ac_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define AC driver feature set according to different device family.
+ * @{
+ */
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+   /** Setting of hysteresis level */
+#  define FEATURE_AC_HYSTERESIS_LEVEL
+   /** SYNCBUSY scheme version 2 */
+#  define FEATURE_AC_SYNCBUSY_SCHEME_VERSION_2
+#endif
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+ 	/** Run in standby feature for each comparator */
+#  define FEATURE_AC_RUN_IN_STANDY_EACH_COMPARATOR
+#else
+ 	/** Run in standby feature for comparator pair */
+#  define FEATURE_AC_RUN_IN_STANDY_PAIR_COMPARATOR
+#endif
+/* @} */
+
+#if !defined(__DOXYGEN__)
+/* Forward declaration of struct */
+struct ac_module;
+
+extern struct ac_module *_ac_instance[AC_INST_NUM];
+#endif
+
+
+/**
+ * \name AC Window Channel Status Flags
+ *
+ * AC window channel status flags, returned by \ref ac_win_get_status().
+ *
+ * @{
+ */
+
+ /** Unknown output state; the comparator window channel was not ready. */
+#define AC_WIN_STATUS_UNKNOWN         (1UL << 0)
+/** Window Comparator's input voltage is above the window */
+#define AC_WIN_STATUS_ABOVE           (1UL << 1)
+/** Window Comparator's input voltage is inside the window */
+#define AC_WIN_STATUS_INSIDE          (1UL << 2)
+/** Window Comparator's input voltage is below the window */
+#define AC_WIN_STATUS_BELOW           (1UL << 3)
+/**
+ * This state reflects the window interrupt flag. When the interrupt flag
+ * should be set is configured in \ref ac_win_set_config(). This state needs
+ * to be cleared by the of \ref ac_win_clear_status().
+ */
+#define AC_WIN_STATUS_INTERRUPT_SET   (1UL << 4)
+/** @} */
+
+/**
+ * \name AC Channel Status Flags
+ *
+ * AC channel status flags, returned by \ref ac_chan_get_status().
+ *
+ * @{
+ */
+
+/** Unknown output state; the comparator channel was not ready. */
+#define AC_CHAN_STATUS_UNKNOWN        (1UL << 0)
+/** Comparator's negative input pin is higher in voltage than the positive
+ *  input pin. */
+#define AC_CHAN_STATUS_NEG_ABOVE_POS  (1UL << 1)
+/** Comparator's positive input pin is higher in voltage than the negative
+ *  input pin. */
+#define AC_CHAN_STATUS_POS_ABOVE_NEG  (1UL << 2)
+/**
+ * This state reflects the channel interrupt flag. When the interrupt flag
+ * should be set is configured in ac_chan_set_config(). This state needs
+ * to be cleared by the of ac_chan_clear_status().
+ */
+#define AC_CHAN_STATUS_INTERRUPT_SET  (1UL << 3)
+/** @} */
+
+/** Type definition for a AC module callback function. */
+typedef void (*ac_callback_t)(struct ac_module *const module_inst);
+
+/** Enum for possible callback types for the AC module. */
+enum ac_callback {
+	/** Callback for comparator 0 */
+	AC_CALLBACK_COMPARATOR_0 = 0,
+	/** Callback for comparator 1 */
+	AC_CALLBACK_COMPARATOR_1 = 1,
+	/** Callback for window 0 */
+	AC_CALLBACK_WINDOW_0     = 4,
+#if (AC_NUM_CMP > 2)
+	/** Callback for comparator 2 */
+	AC_CALLBACK_COMPARATOR_2 = 2,
+	/** Callback for comparator 3 */
+	AC_CALLBACK_COMPARATOR_3 = 3,
+	/** Callback for window 1 */
+	AC_CALLBACK_WINDOW_1     = 5,
+	/** Number of available callbacks */
+#endif /* (AC_NUM_CMP == 2) */
+#if !defined(__DOXYGEN__)
+	AC_CALLBACK_N,
+#endif /* !defined(__DOXYGEN__) */
+};
+
+#ifdef FEATURE_AC_HYSTERESIS_LEVEL
+/** Enum for possible hysteresis level types for AC module. */
+enum ac_hysteresis_level {
+	/** Hysteresis level of 50mV */
+	AC_HYSTERESIS_LEVEL_50 = 0,
+	/** Hysteresis level of 70mV */
+	AC_HYSTERESIS_LEVEL_70,
+	/** Hysteresis level of 90mV */
+	AC_HYSTERESIS_LEVEL_90,
+	/** Hysteresis level of 110mV */
+	AC_HYSTERESIS_LEVEL_110
+};
+#endif
+
+/**
+ * \brief AC comparator channel selection enum.
+ *
+ * Enum for the possible comparator channels.
+ */
+enum ac_chan_channel {
+	/** Comparator channel 0 (Pair 0, Comparator 0) */
+	AC_CHAN_CHANNEL_0 = 0,
+	/** Comparator channel 1 (Pair 0, Comparator 1) */
+	AC_CHAN_CHANNEL_1 = 1,
+#if defined(__DOXYGEN__) || (AC_NUM_CMP > 2)
+	/** Comparator channel 2 (Pair 1, Comparator 0) */
+	AC_CHAN_CHANNEL_2 = 2,
+	/** Comparator channel 3 (Pair 1, Comparator 1) */
+	AC_CHAN_CHANNEL_3 = 3,
+#endif
+};
+
+/**
+ * \brief AC channel input sampling mode configuration enum.
+ *
+ * Enum for the possible channel sampling modes of an Analog Comparator channel.
+ */
+enum ac_chan_sample_mode {
+	/** Continuous sampling mode; when the channel is enabled the comparator
+	 *  output is available for reading at any time */
+	AC_CHAN_MODE_CONTINUOUS    = 0,
+	/** Single shot mode; when used the comparator channel must be triggered to
+	 *  perform a comparison before reading the result */
+	AC_CHAN_MODE_SINGLE_SHOT   = AC_COMPCTRL_SINGLE,
+};
+
+/**
+ * \brief AC channel positive comparator pin input configuration enum.
+ *
+ * Enum for the possible channel positive pin input of an Analog Comparator
+ * channel.
+ */
+enum ac_chan_pos_mux {
+	/** Positive comparator input is connected to physical AC input pin 0 */
+	AC_CHAN_POS_MUX_PIN0       = AC_COMPCTRL_MUXPOS_PIN0,
+	/** Positive comparator input is connected to physical AC input pin 1 */
+	AC_CHAN_POS_MUX_PIN1       = AC_COMPCTRL_MUXPOS_PIN1,
+	/** Positive comparator input is connected to physical AC input pin 2 */
+	AC_CHAN_POS_MUX_PIN2       = AC_COMPCTRL_MUXPOS_PIN2,
+	/** Positive comparator input is connected to physical AC input pin 3 */
+	AC_CHAN_POS_MUX_PIN3       = AC_COMPCTRL_MUXPOS_PIN3,
+};
+
+/**
+ * \brief AC channel negative comparator pin input configuration enum.
+ *
+ * Enum for the possible channel negative pin input of an Analog Comparator
+ * channel.
+ */
+enum ac_chan_neg_mux {
+	/** Negative comparator input is connected to physical AC input pin 0 */
+	AC_CHAN_NEG_MUX_PIN0       = AC_COMPCTRL_MUXNEG_PIN0,
+	/** Negative comparator input is connected to physical AC input pin 1 */
+	AC_CHAN_NEG_MUX_PIN1       = AC_COMPCTRL_MUXNEG_PIN1,
+	/** Negative comparator input is connected to physical AC input pin 2 */
+	AC_CHAN_NEG_MUX_PIN2       = AC_COMPCTRL_MUXNEG_PIN2,
+	/** Negative comparator input is connected to physical AC input pin 3 */
+	AC_CHAN_NEG_MUX_PIN3       = AC_COMPCTRL_MUXNEG_PIN3,
+	/** Negative comparator input is connected to the internal ground plane */
+	AC_CHAN_NEG_MUX_GND        = AC_COMPCTRL_MUXNEG_GND,
+	/** Negative comparator input is connected to the channel's internal V<SUB>CC</SUB>
+	 *  plane voltage scalar */
+	AC_CHAN_NEG_MUX_SCALED_VCC = AC_COMPCTRL_MUXNEG_VSCALE,
+	/** Negative comparator input is connected to the internal band gap voltage
+	 *  reference */
+	AC_CHAN_NEG_MUX_BANDGAP    = AC_COMPCTRL_MUXNEG_BANDGAP,
+#if !(SAML22)
+	/**
+	 * For SAM D20/D21/D10/D11/R21/DA1/HA1:
+	 *     Negative comparator input is connected to the channel's internal DAC
+	 *     channel 0 output.
+	 * For SAM L21/C20/C21:
+	 *     Negative comparator input is connected to the channel's internal DAC
+	 *     channel 0 output for Comparator 0 or OPAMP output for Comparator 1.
+	 */
+	AC_CHAN_NEG_MUX_DAC0       = AC_COMPCTRL_MUXNEG_DAC,
+#endif
+};
+
+/**
+ * \brief AC channel output filtering configuration enum.
+ *
+ * Enum for the possible channel output filtering configurations of an Analog
+ * Comparator channel.
+ */
+enum ac_chan_filter {
+	/** No output filtering is performed on the comparator channel */
+	AC_CHAN_FILTER_NONE        = AC_COMPCTRL_FLEN_OFF,
+	/** Comparator channel output is passed through a Majority-of-Three
+	 *  filter */
+	AC_CHAN_FILTER_MAJORITY_3  = AC_COMPCTRL_FLEN_MAJ3,
+	/** Comparator channel output is passed through a Majority-of-Five
+	 *  filter */
+	AC_CHAN_FILTER_MAJORITY_5  = AC_COMPCTRL_FLEN_MAJ5,
+};
+
+/**
+ * \brief AC channel GPIO output routing configuration enum.
+ *
+ * Enum for the possible channel GPIO output routing configurations of an Analog
+ * Comparator channel.
+ */
+enum ac_chan_output {
+	/** Comparator channel output is not routed to a physical GPIO pin, and is
+	 *  used internally only */
+	AC_CHAN_OUTPUT_INTERNAL    = AC_COMPCTRL_OUT_OFF,
+	/** Comparator channel output is routed to its matching physical GPIO pin,
+	 *  via an asynchronous path */
+	AC_CHAN_OUTPUT_ASYNCRONOUS = AC_COMPCTRL_OUT_ASYNC,
+	/** Comparator channel output is routed to its matching physical GPIO pin,
+	 *  via a synchronous path */
+	AC_CHAN_OUTPUT_SYNCHRONOUS = AC_COMPCTRL_OUT_SYNC,
+};
+
+/**
+ * \brief AC window channel selection enum.
+ *
+ * Enum for the possible window comparator channels.
+ */
+enum ac_win_channel {
+	/** Window channel 0 (Pair 0, Comparators 0 and 1) */
+	AC_WIN_CHANNEL_0 = 0,
+#if defined(__DOXYGEN__) || (AC_PAIRS > 1)
+	/** Window channel 1 (Pair 1, Comparators 2 and 3) */
+	AC_WIN_CHANNEL_1 = 1,
+#endif
+};
+
+/**
+ * \brief Channel interrupt selection enum.
+ *
+ * This enum is used to select when a channel interrupt should occur.
+ */
+enum ac_chan_interrupt_selection {
+	/** An interrupt will be generated when the comparator level is passed */
+	AC_CHAN_INTERRUPT_SELECTION_TOGGLE          = AC_COMPCTRL_INTSEL_TOGGLE,
+	/** An interrupt will be generated when the measurement goes above the
+	 *  compare level
+	 */
+	AC_CHAN_INTERRUPT_SELECTION_RISING          = AC_COMPCTRL_INTSEL_RISING,
+	/** An interrupt will be generated when the measurement goes below the
+	 *  compare level
+	 */
+	AC_CHAN_INTERRUPT_SELECTION_FALLING         = AC_COMPCTRL_INTSEL_FALLING,
+	/**
+	 * An interrupt will be generated when a new measurement is complete.
+	 * Interrupts will only be generated in single shot mode. This state needs
+	 * to be cleared by the use of ac_chan_cleare_status()
+	 */
+	AC_CHAN_INTERRUPT_SELECTION_END_OF_COMPARE  = AC_COMPCTRL_INTSEL_EOC,
+};
+
+/**
+ * \brief Window interrupt selection enum.
+ *
+ * This enum is used to select when a window interrupt should occur.
+ */
+enum ac_win_interrupt_selection {
+	/** Interrupt is generated when the compare value goes above the window */
+	AC_WIN_INTERRUPT_SELECTION_ABOVE    = AC_WINCTRL_WINTSEL0_ABOVE,
+	/** Interrupt is generated when the compare value goes inside the window */
+	AC_WIN_INTERRUPT_SELECTION_INSIDE   = AC_WINCTRL_WINTSEL0_INSIDE,
+	/** Interrupt is generated when the compare value goes below the window */
+	AC_WIN_INTERRUPT_SELECTION_BELOW    = AC_WINCTRL_WINTSEL0_BELOW,
+	/** Interrupt is generated when the compare value goes outside the window */
+	AC_WIN_INTERRUPT_SELECTION_OUTSIDE  = AC_WINCTRL_WINTSEL0_OUTSIDE,
+};
+
+/**
+ * \brief AC software device instance structure.
+ *
+ * AC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct ac_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware module pointer of the associated Analog Comparator peripheral. */
+	Ac *hw;
+#  if AC_CALLBACK_MODE == true
+	/** Array of callbacks */
+	ac_callback_t callback[AC_CALLBACK_N];
+	/** Bit mask for callbacks registered */
+	uint8_t register_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t enable_callback_mask;
+#  endif
+#endif
+};
+
+/**
+ * \brief AC event enable/disable structure.
+ *
+ * Event flags for the Analog Comparator module. This is used to enable and
+ * disable events via \ref ac_enable_events() and \ref ac_disable_events().
+ */
+struct ac_events {
+	/** If \c true, an event will be generated when a comparator window state
+	 *  changes */
+	bool generate_event_on_window[AC_PAIRS];
+
+	/** If \c true, an event will be generated when a comparator state
+	 *  changes */
+	bool generate_event_on_state[AC_NUM_CMP];
+
+	/** If \c true, a comparator will be sampled each time an event is
+	 *  received */
+	bool on_event_sample[AC_NUM_CMP];
+};
+
+/**
+ * \brief Analog Comparator module configuration structure.
+ *
+ *  Configuration structure for a comparator channel, to configure the input and
+ *  output settings of the comparator.
+ */
+struct ac_config {
+#ifdef FEATURE_AC_RUN_IN_STANDY_PAIR_COMPARATOR
+	/** If \c true, the comparator pairs will continue to sample during sleep
+	 *  mode when triggered */
+	bool run_in_standby[AC_PAIRS];
+#endif
+
+#if (SAMD) || (SAMHA1) || (SAMR21)
+	/** Digital source generator for AC GCLK */
+	enum gclk_generator dig_source_generator;
+	/** Analog source generator for AC GCLK */
+	enum gclk_generator ana_source_generator;
+#else
+	/** Source generator for AC GCLK */
+	enum gclk_generator source_generator;
+#endif
+};
+
+/**
+ * \brief Analog Comparator Comparator channel configuration structure.
+ *
+ *  Configuration structure for a comparator channel, to configure the input and
+ *  output settings of the comparator.
+ */
+struct ac_chan_config {
+	/** Sampling mode of the comparator channel */
+	enum ac_chan_sample_mode sample_mode;
+	/** Filtering mode for the comparator output, when the comparator is used
+	 *  in a supported mode */
+	enum ac_chan_filter filter;
+	/** When \c true, hysteresis mode is enabled on the comparator inputs */
+	bool enable_hysteresis;
+#ifdef FEATURE_AC_RUN_IN_STANDY_EACH_COMPARATOR
+	/** If \c true, the comparator will continue to sample during sleep
+	 *  mode when triggered */
+	bool run_in_standby;
+#endif
+#ifdef FEATURE_AC_HYSTERESIS_LEVEL
+	/** Hysteresis level of the comparator channel */
+	enum ac_hysteresis_level hysteresis_level;
+#endif
+	/** Output mode of the comparator, whether it should be available for
+	 *  internal use, or asynchronously/synchronously linked to a 
+	 *  general-purpose input/output (GPIO) pin */
+	enum ac_chan_output output_mode;
+	/** Input multiplexer selection for the comparator's positive input pin */
+	enum ac_chan_pos_mux positive_input;
+	/** Input multiplexer selection for the comparator's negative input pin.
+	 *  Any internal reference source, such as a bandgap reference voltage or
+	 *  the DAC, must be configured and enabled prior to its use as a
+	 *  comparator input.*/
+	enum ac_chan_neg_mux negative_input;
+	/** Scaled VCC voltage division factor for the channel, when a comparator
+	 *  pin is connected to the V<SUB>CC</SUB> voltage scalar input. The formular is:
+	 *      Vscale = Vdd * vcc_scale_factor / 64.
+	 *  If the V<SUB>CC</SUB> voltage scalar is not selected as a comparator
+	 *  channel pin's input, this value will be ignored. */
+	uint8_t vcc_scale_factor;
+	/** Interrupt criteria for the comparator channel, to select the condition
+	 *  that will trigger a callback */
+	enum ac_chan_interrupt_selection interrupt_selection;
+};
+
+/**
+ * \brief Analog Comparator Window configuration structure.
+ */
+struct ac_win_config {
+	/** Interrupt criteria for the comparator window channel, to select the
+	 *  condition that will trigger a callback */
+	enum ac_win_interrupt_selection interrupt_selection;
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+enum status_code ac_reset(
+		struct ac_module *const module_inst);
+
+enum status_code ac_init(
+		struct ac_module *const module_inst,
+		Ac *const hw,
+		struct ac_config *const config);
+
+#if (AC_INST_NUM > 1) && !defined(__DOXYGEN__)
+/**
+ * \internal Find the index of given AC module instance.
+ *
+ * \param[in] AC module instance pointer.
+ *
+ * \return Index of the given AC module instance.
+ */
+static uint8_t _ac_get_inst_index(
+		Ac *const hw)
+{
+	/* List of available AC modules. */
+	static Ac *const ac_modules[AC_INST_NUM] = AC_INSTS;
+
+	/* Find index for AC instance. */
+	for (uint32_t i = 0; i < AC_INST_NUM; i++) {
+		if (hw == ac_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given. */
+	Assert(false);
+	return 0;
+}
+#endif /* (AC_INST_NUM > 1) && !defined(__DOXYGEN__) */
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module_inst  Pointer to the AC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false If the module has completed synchronization
+ * \retval ture If the module synchronization is ongoing
+ */
+static inline bool ac_is_syncing(
+        struct ac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Ac *const ac_module = module_inst->hw;
+
+#ifdef FEATURE_AC_SYNCBUSY_SCHEME_VERSION_2
+	if (ac_module->SYNCBUSY.reg & AC_SYNCBUSY_MASK) {
+		return true;
+	}
+
+	return false;
+#else
+	if (ac_module->STATUSB.reg & AC_STATUSB_SYNCBUSY) {
+		return true;
+	}
+
+	return false;
+#endif
+}
+
+/**
+ * \brief Initializes all members of an Analog Comparator configuration
+ * structure to safe defaults.
+ *
+ *  Initializes all members of a given Analog Comparator configuration
+ *  structure to safe known default values. This function should be called on
+ *  all new instances of these configuration structures before being modified
+ *  by the user application.
+ *
+ *  The default configuration is as follows:
+ *   \li All comparator pairs disabled during sleep mode (if has this feature)
+ *   \li Generator 0 is the default GCLK generator
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void ac_get_config_defaults(
+		struct ac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+#ifdef FEATURE_AC_RUN_IN_STANDY_PAIR_COMPARATOR
+	/* Default configuration values */
+	for (uint32_t i = 0; i < AC_PAIRS; i++) {
+		config->run_in_standby[i] = false;
+	}
+#endif
+#if (SAMD) || (SAMHA1) || (SAMR21)
+	config->dig_source_generator = GCLK_GENERATOR_0;
+	config->ana_source_generator = GCLK_GENERATOR_3;
+#else
+	config->source_generator = GCLK_GENERATOR_0;
+#endif
+}
+
+/**
+ * \brief Enables an Analog Comparator that was previously configured.
+ *
+ * Enables an Analog Comparator that was previously configured via a
+ * call to \ref ac_init().
+ *
+ * \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ */
+static inline void ac_enable(
+		struct ac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Write the new comparator module control configuration */
+	ac_module->CTRLA.reg |= AC_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disables an Analog Comparator that was previously enabled.
+ *
+ * Disables an Analog Comparator that was previously started via a call to
+ * \ref ac_enable().
+ *
+ * \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ */
+static inline void ac_disable(
+		struct ac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Disbale interrupt */
+	ac_module->INTENCLR.reg = AC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	ac_module->INTFLAG.reg = AC_INTFLAG_MASK;
+
+	/* Write the new comparator module control configuration */
+	ac_module->CTRLA.reg &= ~AC_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Enables an Analog Comparator event input or output.
+ *
+ *  Enables one or more input or output events to or from the Analog Comparator
+ *  module. See \ref ac_events for a list of events this module
+ *  supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+static inline void ac_enable_events(
+		struct ac_module *const module_inst,
+		struct ac_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Ac *const ac_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure window output events for each comparator pair */
+	for (uint8_t i = 0; i < AC_PAIRS; i++) {
+		if (events->generate_event_on_window[i] == true) {
+			event_mask |= (AC_EVCTRL_WINEO0 << i);
+		}
+	}
+
+	/* Configure sample input/output events for each comparator */
+	for (uint8_t i = 0; i < AC_NUM_CMP; i++) {
+		if (events->on_event_sample[i] == true) {
+			event_mask |= (AC_EVCTRL_COMPEI0 << i);
+		}
+
+		if (events->generate_event_on_state[i] == true) {
+			event_mask |= (AC_EVCTRL_COMPEO0 << i);
+		}
+	}
+
+	ac_module->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables an Analog Comparator event input or output.
+ *
+ *  Disables one or more input or output events to or from the Analog Comparator
+ *  module. See \ref ac_events for a list of events this module
+ *  supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] events       Struct containing flags of events to disable
+ */
+static inline void ac_disable_events(
+		struct ac_module *const module_inst,
+		struct ac_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Ac *const ac_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure window output events for each comparator pair */
+	for (uint8_t i = 0; i < AC_PAIRS; i++) {
+		if (events->generate_event_on_window[i] == true) {
+			event_mask |= (AC_EVCTRL_WINEO0 << i);
+		}
+	}
+
+	/* Configure sample input/output events for each comparator */
+	for (uint8_t i = 0; i < AC_NUM_CMP; i++) {
+		if (events->on_event_sample[i] == true) {
+			event_mask |= (AC_EVCTRL_COMPEI0 << i);
+		}
+
+		if (events->generate_event_on_state[i] == true) {
+			event_mask |= (AC_EVCTRL_COMPEO0 << i);
+		}
+	}
+
+	ac_module->EVCTRL.reg &= ~event_mask;
+}
+
+/** @} */
+
+
+/**
+ * \name Channel Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes all members of an Analog Comparator channel configuration
+ * structure to safe defaults.
+ *
+ *  Initializes all members of an Analog Comparator channel configuration
+ *  structure to safe defaults. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Continuous sampling mode
+ *   \li Majority of five sample output filter
+ *   \li Comparator disabled during sleep mode (if has this feature)
+ *   \li Hysteresis enabled on the input pins
+ *   \li Hysteresis level of 50mV if having this feature
+ *   \li Internal comparator output mode
+ *   \li Comparator pin multiplexer 0 selected as the positive input
+ *   \li Scaled V<SUB>CC</SUB> voltage selected as the negative input
+ *   \li V<SUB>CC</SUB> voltage scaler set for a division factor of two
+ *   \li Channel interrupt set to occur when the compare threshold is passed
+ *
+ *   \param[out] config  Channel configuration structure to initialize to
+ *                       default values
+ */
+static inline void ac_chan_get_config_defaults(
+		struct ac_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->sample_mode         = AC_CHAN_MODE_CONTINUOUS;
+	config->filter              = AC_CHAN_FILTER_MAJORITY_5;
+	config->enable_hysteresis   = true;
+#ifdef FEATURE_AC_RUN_IN_STANDY_EACH_COMPARATOR
+	config->run_in_standby      = false;
+#endif
+#ifdef FEATURE_AC_HYSTERESIS_LEVEL
+	config->hysteresis_level    = AC_HYSTERESIS_LEVEL_50;
+#endif
+	config->output_mode         = AC_CHAN_OUTPUT_INTERNAL;
+	config->positive_input      = AC_CHAN_POS_MUX_PIN0;
+	config->negative_input      = AC_CHAN_NEG_MUX_SCALED_VCC;
+	config->vcc_scale_factor    = 32;
+	config->interrupt_selection = AC_CHAN_INTERRUPT_SELECTION_TOGGLE;
+}
+
+enum status_code ac_chan_set_config(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel,
+		struct ac_chan_config *const config);
+
+/**
+ * \brief Enables an Analog Comparator channel that was previously configured.
+ *
+ *  Enables an Analog Comparator channel that was previously
+ *  configured via a call to \ref ac_chan_set_config().
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] channel      Comparator channel to enable
+ */
+static inline void ac_chan_enable(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Write the new comparator module control configuration */
+	ac_module->COMPCTRL[(uint8_t)channel].reg |= AC_COMPCTRL_ENABLE;
+}
+
+/**
+ * \brief Disables an Analog Comparator channel that was previously enabled.
+ *
+ *  Stops an Analog Comparator channel that was previously started via a call to
+ *  \ref ac_chan_enable().
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] channel      Comparator channel to disable
+ */
+static inline void ac_chan_disable(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Write the new comparator module control configuration */
+	ac_module->COMPCTRL[(uint8_t)channel].reg &= ~AC_COMPCTRL_ENABLE;
+}
+
+/** @} */
+
+
+/**
+ * \name Channel Control
+ * @{
+ */
+
+/**
+ * \brief Triggers a comparison on a comparator that is configured in single shot mode.
+ *
+ *  Triggers a single conversion on a comparator configured to compare on demand
+ *  (single shot mode) rather than continuously.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] channel      Comparator channel to trigger
+ */
+static inline void ac_chan_trigger_single_shot(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	/* Write the new comparator module control configuration */
+	ac_module->CTRLB.reg |= (AC_CTRLB_START0 << (uint8_t)channel);
+}
+
+/**
+ * \brief Determines if a given comparator channel is ready for comparisons.
+ *
+ *  Checks a comparator channel to see if the comparator is currently ready to
+ *  begin comparisons.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] channel      Comparator channel to test
+ *
+ *  \return Comparator channel readiness state.
+ */
+static inline bool ac_chan_is_ready(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	return (ac_module->STATUSB.reg & (AC_STATUSB_READY0 << (uint8_t)channel));
+}
+
+/**
+ * \brief Determines the output state of a comparator channel.
+ *
+ *  Retrieves the last comparison value (after filtering) of a given comparator.
+ *  If the comparator was not ready at the time of the check, the comparison
+ *  result will be indicated as being unknown.
+ *
+ *  \param[in] module_inst   Software instance for the Analog Comparator peripheral
+ *  \param[in] channel       Comparator channel to test
+ *
+ *  \return Bit mask of comparator channel status flags.
+ */
+static inline uint8_t ac_chan_get_status(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	uint8_t status_mask = 0;
+
+	if (ac_module->INTFLAG.reg & (1 << channel)) {
+		status_mask = AC_CHAN_STATUS_INTERRUPT_SET;
+	}
+
+	if (ac_chan_is_ready(module_inst, channel) == false) {
+		status_mask |= AC_CHAN_STATUS_UNKNOWN;
+		return status_mask;
+	}
+
+	if (ac_module->STATUSA.reg & (AC_STATUSA_STATE0 << (uint8_t)channel)) {
+		status_mask |= AC_CHAN_STATUS_POS_ABOVE_NEG;
+	} else {
+		status_mask |= AC_CHAN_STATUS_NEG_ABOVE_POS;
+	}
+	return status_mask;
+}
+
+/**
+ * \brief Clears an interrupt status flag.
+ *
+ * This function is used to clear the AC_CHAN_STATUS_INTERRUPT_SET flag
+ * it will clear the flag for the channel indicated by the channel argument.
+ *
+ * \param[in]  module_inst  Software instance for the Analog Comparator peripheral
+ * \param[in]  channel      Comparator channel to clear
+ */
+static inline void ac_chan_clear_status(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->INTFLAG.reg = (1 << channel);
+}
+/** @} */
+
+
+/**
+ * \name Window Mode Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes an Analog Comparator window configuration structure to defaults.
+ *
+ *  Initializes a given Analog Comparator channel configuration structure to a
+ *  set of known default values. This function should be called if window interrupts
+ *  are needed and before ac_win_set_config().
+ *
+ *  The default configuration is as follows:
+ *   \li Channel interrupt set to occur when the measurement is above the window
+ *
+ *   \param[out] config  Window configuration structure to initialize to
+ *                       default values
+ */
+static inline void ac_win_get_config_defaults(
+		struct ac_win_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->interrupt_selection = AC_WIN_INTERRUPT_SELECTION_ABOVE;
+}
+
+enum status_code ac_win_set_config(
+		struct ac_module *const module_inst,
+		enum ac_win_channel const win_channel,
+		struct ac_win_config *const config);
+
+enum status_code ac_win_enable(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel);
+
+void ac_win_disable(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel);
+
+/** @} */
+
+
+/**
+ * \name Window Mode Control
+ * @{
+ */
+
+/**
+ * \brief Determines if a given Window Comparator is ready for comparisons.
+ *
+ *  Checks a Window Comparator to see if the both comparators used for window
+ *  detection is currently ready to begin comparisons.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] win_channel  Window Comparator channel to test
+ *
+ *  \return Window Comparator channel readiness state.
+ */
+static inline bool ac_win_is_ready(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Convert a window channel index to the individual comparator channels */
+	enum ac_chan_channel win_pair_comp0 =
+			(enum ac_chan_channel)((uint8_t)win_channel * 2);
+	enum ac_chan_channel win_pair_comp1 =
+			(enum ac_chan_channel)(((uint8_t)win_channel * 2) + 1);
+
+	/* Check if the two comparators used in the window are ready */
+	bool win_pair_comp0_ready = ac_chan_is_ready(module_inst, win_pair_comp0);
+	bool win_pair_comp1_ready = ac_chan_is_ready(module_inst, win_pair_comp1);
+
+	/* If one or both window comparators not ready, return failure */
+	if ((win_pair_comp0_ready == false) || (win_pair_comp1_ready == false)) {
+		return false;
+	}
+
+	return true;
+}
+
+uint8_t ac_win_get_status(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel);
+
+/**
+ * \brief Clears an interrupt status flag.
+ *
+ * This function is used to clear the AC_WIN_STATUS_INTERRUPT_SET flag
+ * it will clear the flag for the channel indicated by the win_channel argument.
+ *
+ * \param[in]  module_inst  Software instance for the Analog Comparator peripheral
+ * \param[in]  win_channel      Window channel to clear
+ */
+static inline void ac_win_clear_status(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->INTFLAG.reg = (1 << (win_channel + AC_INTFLAG_WIN0_Pos));
+}
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+
+/**
+ * \page asfdoc_sam0_ac_extra Extra Information for AC Driver
+ *
+ * \section asfdoc_sam0_ac_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *    <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *    </tr>
+ *    <tr>
+ *      <td>AC</td>
+ *      <td>Analog Comparator</td>
+ *    </tr>
+ *    <tr>
+ *      <td>DAC</td>
+ *      <td>Digital-to-Analog Converter</td>
+ *    </tr>
+ *    <tr>
+ *      <td>MUX</td>
+ *      <td>Multiplexer</td>
+ *    </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_ac_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_ac_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_ac_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *    <tr>
+ *      <th>Changelog</th>
+ *    </tr>
+ *    <tr>
+ *      <td>Initial Release</td>
+ *    </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_ac_exqsg Examples for AC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_ac_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_ac_basic_use_case
+ * \if AC_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_ac_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_ac_document_revision_history Document Revision History
+ *
+ * <table>
+ *    <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *    </tr>
+ *    <tr>
+ *      <td>42106F</td>
+ *      <td>12/2015</td>
+ *      <td>Fixed typos and legal disclaimer</td>
+ *    </tr>
+ *    <tr>
+ *      <td>42106E</td>
+ *      <td>08/2015</td>
+ *      <td>Added support for SAM L21, SAM C20/C21, and SAM DA1</td>
+ *    </tr>
+ *    <tr>
+ *      <td>42106D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *    </tr>
+ *    <tr>
+ *      <td>42106C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *    </tr>
+ *    <tr>
+ *      <td>42106B</td>
+ *      <td>06/2013</td>
+ *      <td>Added additional documentation on the event system. Corrected
+ *          documentation typos.</td>
+ *    </tr>
+ *    <tr>
+ *      <td>42106A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *    </tr>
+ * </table>
+ */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.c
new file mode 100644
index 0000000000..4f1fc7d1ac
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.c
@@ -0,0 +1,206 @@
+/**
+ * \file
+ *
+ * \brief SAM AC - Analog Comparator Callback Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "ac_callback.h"
+
+struct ac_module *_ac_instance[AC_INST_NUM];
+
+void _ac_interrupt_handler(const uint32_t instance_index);
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref ac_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module      Pointer to software instance struct
+ * \param[in]     callback_func Pointer to callback function
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \retval STATUS_OK  The function exited successfully
+ */
+enum status_code ac_register_callback(
+		struct ac_module *const module,
+		ac_callback_t callback_func,
+		const enum ac_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set software flag for callback */
+	module->register_callback_mask |= (1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters a callback function implemented by the user.
+ *
+ * \param[in]     module Pointer to AC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \retval STATUS_OK  The function exited successfully
+ */
+enum status_code ac_unregister_callback(
+		struct ac_module *const module,
+		const enum ac_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear software flag for callback */
+	module->register_callback_mask &= ~(1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal ISR handler for AC
+ */
+#if (AC_INST_NUM == 1)
+void AC_Handler(void)
+{
+	_ac_interrupt_handler(0);
+}
+#elif (AC_INST_NUM == 2)
+void AC_Handler(void)
+{
+	_ac_interrupt_handler(0);
+}
+
+void AC1_Handler(void)
+{
+	_ac_interrupt_handler(1);
+}
+#else
+#  error This driver is not support more than three AC instances.
+#endif
+
+/**
+ * \brief Interrupt Handler for AC module.
+ *
+ * Handles interrupts as they occur, it will run the callback functions
+ * that are registered and enabled.
+ *
+ * \param [in] instance_index  Default value 0
+ */
+void _ac_interrupt_handler(const uint32_t instance_index)
+{
+	/* Temporary variable */
+	uint8_t interrupt_and_callback_status_mask;
+
+	/* Get device instance from the look-up table */
+
+	struct ac_module *module = _ac_instance[instance_index];
+
+	/* Read and mask interrupt flag register */
+	interrupt_and_callback_status_mask =
+			_ac_instance[instance_index]->hw->INTFLAG.reg &
+			(module->register_callback_mask & module->enable_callback_mask);
+
+	/* Check if comparator channel 0 needs to be serviced */
+	if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP0) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[AC_CALLBACK_COMPARATOR_0])(module);
+		/* Clear interrupt flag */
+		module->hw->INTFLAG.reg = AC_INTFLAG_COMP0;
+	}
+
+	/* Check if comparator channel 1 needs to be serviced */
+	if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP1) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[AC_CALLBACK_COMPARATOR_1])(module);
+		/* Clear interrupt flag */
+		module->hw->INTFLAG.reg = AC_INTFLAG_COMP1;
+	}
+
+	/* Check if window 0 needs to be serviced */
+	if (interrupt_and_callback_status_mask & AC_INTFLAG_WIN0) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[AC_CALLBACK_WINDOW_0])(module);
+		/* Clear interrupt flag */
+		module->hw->INTFLAG.reg = AC_INTFLAG_WIN0;
+	}
+
+#if (AC_NUM_CMP > 2)
+		/* Check if comparator channel 2 needs to be serviced */
+	if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP2) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[AC_CALLBACK_COMPARATOR_2])(module);
+		/* Clear interrupt flag */
+		module->hw->INTFLAG.reg = AC_INTFLAG_COMP2;
+	}
+
+	/* Check if comparator channel 3 needs to be serviced */
+	if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP3) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[AC_CALLBACK_COMPARATOR_3])(module);
+		/* Clear interrupt flag */
+		module->hw->INTFLAG.reg = AC_INTFLAG_COMP3;
+	}
+
+#  if !(SAMC20)
+		/* Check if window 1 needs to be serviced */
+	if (interrupt_and_callback_status_mask & AC_INTFLAG_WIN1) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[AC_CALLBACK_WINDOW_1])(module);
+		/* Clear interrupt flag */
+		module->hw->INTFLAG.reg = AC_INTFLAG_WIN1;
+	}
+#  endif
+#endif /* (AC_NUM_CMP > 2) */
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.h
new file mode 100644
index 0000000000..fa48a7c817
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.h
@@ -0,0 +1,223 @@
+/**
+ * \file
+ *
+ * \brief SAM AC - Analog Comparator Callback Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef AC_CALLBACK_H_INCLUDED
+#define AC_CALLBACK_H_INCLUDED
+
+#include <compiler.h>
+#include <system_interrupt.h>
+#include "ac.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (AC_INST_NUM > 1) && !defined(__DOXYGEN__)
+/**
+ * \internal Get the interrupt vector for the given device instance
+ *
+ * \param[in] TC module instance number
+ *
+ * \return Interrupt vector for of the given TC module instance.
+ */
+static enum system_interrupt_vector _ac_interrupt_get_interrupt_vector(
+		uint32_t inst_num)
+{
+	static uint8_t ac_interrupt_vectors[AC_INST_NUM] =
+		{
+			SYSTEM_INTERRUPT_MODULE_AC,
+#if (AC_INST_NUM == 2)
+			SYSTEM_INTERRUPT_MODULE_AC1,
+#endif
+#if (AC_INST_NUM >= 3)
+#  error This driver is not support more than three AC instances.
+#endif
+		};
+
+	return ac_interrupt_vectors[inst_num];
+}
+#endif /* (AC_INST_NUM > 1) !defined(__DOXYGEN__)*/
+
+/**
+ * \name Callback Management
+ * {@
+ */
+
+enum status_code ac_register_callback(
+		struct ac_module *const module,
+		ac_callback_t callback_func,
+		const enum ac_callback callback_type);
+
+enum status_code ac_unregister_callback(
+		struct ac_module *const module,
+		const enum ac_callback callback_type);
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback function registered by the \ref
+ * ac_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are
+ * met. This function will also enable the appropriate interrupts.
+ *
+ * \param[in]     module Pointer to AC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+static inline void ac_enable_callback(
+		struct ac_module *const module,
+		const enum ac_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Set software flag for the callback */
+	module->enable_callback_mask |= (1 << callback_type);
+
+	uint32_t inenset_temp = 0;
+
+	switch (callback_type)
+	{
+		case AC_CALLBACK_COMPARATOR_0:
+			inenset_temp |= AC_INTFLAG_COMP0;
+			break;
+		case AC_CALLBACK_COMPARATOR_1:
+			inenset_temp |= AC_INTFLAG_COMP1;
+			break;
+		case AC_CALLBACK_WINDOW_0:
+			inenset_temp |= AC_INTFLAG_WIN0;
+			break;
+#if (AC_NUM_CMP > 2)
+		case AC_CALLBACK_COMPARATOR_2:
+			inenset_temp |= AC_INTFLAG_COMP2;
+			break;
+		case AC_CALLBACK_COMPARATOR_3:
+			inenset_temp |= AC_INTFLAG_COMP3;
+			break;
+#  if !(SAMC20)
+		case AC_CALLBACK_WINDOW_1:
+			inenset_temp |= AC_INTFLAG_WIN1;
+			break;
+#  endif
+#endif
+		default:
+			break;
+	}
+
+	/* Enable the interrupt for the callback */
+	module->hw->INTENSET.reg = inenset_temp;
+
+#if (AC_INST_NUM == 1)
+	/* Enable interrupts for AC module */
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_AC);
+#elif (AC_INST_NUM > 1)
+	system_interrupt_enable(_ac_interrupt_get_interrupt_vector(_ac_get_inst_index(module->hw)));
+#endif /* (AC_INST_NUM > 1) */
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback function registered by the \ref
+ * ac_register_callback, and the callback will not be called from the
+ * interrupt routine. The function will also disable the appropriate
+ * interrupts.
+ *
+ * \param[in]     module Pointer to AC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+static inline void ac_disable_callback(
+		struct ac_module *const module,
+		const enum ac_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Clear software flag for the callback */
+	module->enable_callback_mask &= ~(1 << callback_type);
+
+	uint32_t inenclr_temp = 0;
+
+	switch (callback_type)
+	{
+		case AC_CALLBACK_COMPARATOR_0:
+			inenclr_temp |= AC_INTFLAG_COMP0;
+			break;
+		case AC_CALLBACK_COMPARATOR_1:
+			inenclr_temp |= AC_INTFLAG_COMP1;
+			break;
+		case AC_CALLBACK_WINDOW_0:
+			inenclr_temp |= AC_INTFLAG_WIN0;
+			break;
+#if (AC_NUM_CMP > 2)
+		case AC_CALLBACK_COMPARATOR_2:
+			inenclr_temp |= AC_INTFLAG_COMP2;
+			break;
+		case AC_CALLBACK_COMPARATOR_3:
+			inenclr_temp |= AC_INTFLAG_COMP3;
+			break;
+#  if !(SAMC20)
+		case AC_CALLBACK_WINDOW_1:
+			inenclr_temp |= AC_INTFLAG_WIN1;
+			break;
+#  endif
+#endif
+		default:
+			break;
+	}
+
+	/* Disable the interrupt for the callback */
+	module->hw->INTENCLR.reg = inenclr_temp;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AC_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_d_r_h/ac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_d_r_h/ac.c
new file mode 100644
index 0000000000..7eac51ea19
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_d_r_h/ac.c
@@ -0,0 +1,440 @@
+/**
+ * \file
+ *
+ * \brief SAM Analog Comparator Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "ac.h"
+
+static enum status_code _ac_set_config(
+		struct ac_module *const module_inst,
+		struct ac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(config);
+
+	Ac *const ac_module = module_inst->hw;
+
+	/* Use a temporary register for computing the control bits */
+	uint32_t ctrla_temp = 0;
+
+	/* Check if the comparators should be enabled during sleep */
+	for (uint32_t i = 0; i < AC_PAIRS; i++) {
+		if (config->run_in_standby[i] == true) {
+			ctrla_temp |= (AC_CTRLA_RUNSTDBY_Msk << i);
+		}
+	}
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Write the new comparator module control configuration */
+	ac_module->CTRLA.reg = ctrla_temp;
+
+	return STATUS_OK;
+}
+
+/** \brief Resets and disables the Analog Comparator driver.
+ *
+ *  Resets and disables the Analog Comparator driver, resets the internal
+ *  states and registers of the hardware module to their power-on defaults.
+ *
+ * \param[out] module_inst  Pointer to the AC software instance struct
+ */
+enum status_code ac_reset(
+		struct ac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	/* Disable the hardware module */
+	ac_disable(module_inst);
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Software reset the module */
+	ac_module->CTRLA.reg |= AC_CTRLA_SWRST;
+
+	return STATUS_OK;
+}
+
+/** \brief Initializes and configures the Analog Comparator driver.
+ *
+ *  Initializes the Analog Comparator driver, configuring it to the user
+ *  supplied configuration parameters, ready for use. This function should be
+ *  called before enabling the Analog Comparator.
+ *
+ *  \note Once called the Analog Comparator will not be running; to start the
+ *        Analog Comparator call \ref ac_enable() after configuring the module.
+ *
+ * \param[out] module_inst  Pointer to the AC software instance struct
+ * \param[in]  hw           Pointer to the AC module instance
+ * \param[in]  config       Pointer to the config struct, created by the user
+ *                          application
+ */
+enum status_code ac_init(
+		struct ac_module *const module_inst,
+		Ac *const hw,
+		struct ac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module_inst->hw = hw;
+
+	/* Turn on the digital interface clock and GCLK */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+
+	if (hw == AC) {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_AC);
+		gclk_chan_conf.source_generator = config->dig_source_generator;
+		system_gclk_chan_set_config(AC_GCLK_ID_DIG, &gclk_chan_conf);
+		system_gclk_chan_enable(AC_GCLK_ID_DIG);
+		gclk_chan_conf.source_generator = config->ana_source_generator;
+		system_gclk_chan_set_config(AC_GCLK_ID_ANA, &gclk_chan_conf);
+		system_gclk_chan_enable(AC_GCLK_ID_ANA);
+	}
+#if (AC_INST_NUM == 2)
+	else if (hw == AC1) {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_AC1);
+		gclk_chan_conf.source_generator = config->dig_source_generator;
+		system_gclk_chan_set_config(AC1_GCLK_ID_DIG, &gclk_chan_conf);
+		system_gclk_chan_enable(AC1_GCLK_ID_DIG);
+		gclk_chan_conf.source_generator = config->ana_source_generator;
+		system_gclk_chan_set_config(AC1_GCLK_ID_ANA, &gclk_chan_conf);
+		system_gclk_chan_enable(AC1_GCLK_ID_ANA);
+	}
+#elif (AC_INST_NUM >= 3)
+#  error This driver is not support more than three AC instances.
+#endif
+
+#if AC_CALLBACK_MODE == true
+	/* Initialize parameters */
+	for (uint8_t i = 0; i < AC_CALLBACK_N; i++) {
+		module_inst->callback[i]        = NULL;
+	}
+
+	/* Initialize software flags*/
+	module_inst->register_callback_mask = 0x00;
+	module_inst->enable_callback_mask   = 0x00;
+
+#  if (AC_INST_NUM == 1)
+	_ac_instance[0] = module_inst;
+#  else
+	/* Register this instance for callbacks*/
+	_ac_instance[_ac_get_inst_index(hw)] = module_inst;
+#  endif
+#endif
+
+	/* Write configuration to module */
+	return _ac_set_config(module_inst, config);
+}
+
+/** \brief Writes an Analog Comparator channel configuration to the hardware module.
+ *
+ *  Writes a given Analog Comparator channel configuration to the hardware
+ *  module.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] channel      Analog Comparator channel to configure
+ *  \param[in] config       Pointer to the channel configuration struct
+ */
+enum status_code ac_chan_set_config(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel,
+		struct ac_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(config);
+
+	Ac *const ac_module = module_inst->hw;
+
+	/* Use a temporary variable to compute the comparator configuration */
+	uint32_t compctrl_temp = 0;
+
+	/* Enable output filter mode */
+	compctrl_temp |= config->filter;
+
+	/* Enable output hysteresis if required */
+	if (config->enable_hysteresis == true) {
+		compctrl_temp |= AC_COMPCTRL_HYST;
+	}
+
+	/* Set output signal routing mode */
+	compctrl_temp |= config->output_mode;
+
+	/* Configure comparator positive and negative pin MUX configurations */
+	compctrl_temp |=
+			(uint32_t)config->positive_input |
+			(uint32_t)config->negative_input;
+
+	/* Set sampling mode (single shot or continuous) */
+	compctrl_temp |= config->sample_mode;
+
+	/* Set channel interrupt selection */
+	compctrl_temp |= config->interrupt_selection;
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Write the final configuration to the module's control register */
+	ac_module->COMPCTRL[(uint8_t)channel].reg = compctrl_temp;
+
+	/* Configure VCC voltage scaling for the comparator */
+	ac_module->SCALER[(uint8_t)channel].reg   = config->vcc_scale_factor - 1;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Function used to setup interrupt selection of a window
+ *
+ * This function is used to setup when an interrupt should occur
+ * for a given window.
+ *
+ * \note This must be done before enabling the channel.
+ *
+ * \param[in]  module_inst  Pointer to software instance struct
+ * \param[in]  win_channel  Window channel to setup
+ * \param[in]  config       Configuration for the given window channel
+ *
+ * \retval  STATUS_OK               Function exited successful
+ * \retval  STATUS_ERR_INVALID_ARG  win_channel argument incorrect
+ */
+enum status_code ac_win_set_config(
+		struct ac_module *const module_inst,
+		enum ac_win_channel const win_channel,
+		struct ac_win_config *const config)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(config);
+
+	uint8_t winctrl_mask;
+
+	winctrl_mask = module_inst->hw->WINCTRL.reg;
+
+	if (win_channel == AC_WIN_CHANNEL_0) {
+		winctrl_mask &= ~AC_WINCTRL_WINTSEL0_Msk;
+		winctrl_mask |= config->interrupt_selection;
+	}
+#if (AC_PAIRS > 1)
+	else if (win_channel == AC_WIN_CHANNEL_1) {
+		winctrl_mask &= ~AC_WINCTRL_WINTSEL1_Msk;
+		winctrl_mask = (config->interrupt_selection << (AC_WINCTRL_WINTSEL1_Pos -
+		AC_WINCTRL_WINTSEL0_Pos);
+	}
+#endif /* (AC_PAIRS > 1) */
+	else {
+		return STATUS_ERR_INVALID_ARG ;
+	}
+
+	module_inst->hw->WINCTRL.reg = winctrl_mask;
+
+	return STATUS_OK;
+}
+
+/** \brief Enables an Analog Comparator window channel that was previously configured.
+ *
+ *  Enables and starts an Analog Comparator window channel.
+ *
+ *  \note The comparator channels used by the window channel must be configured
+ *        and enabled before calling this function. The two comparator channels
+ *        forming each window comparator pair must have identical configurations
+ *        other than the negative pin multiplexer setting.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] win_channel  Comparator window channel to enable
+ *
+ *  \return Status of the window enable procedure.
+ *
+ *  \retval STATUS_OK              The window comparator was enabled
+ *  \retval STATUS_ERR_IO          One or both comparators in the window
+ *                                 comparator pair is disabled
+ *  \retval STATUS_ERR_BAD_FORMAT  The comparator channels in the window pair
+ *                                 were not configured correctly
+ */
+enum status_code ac_win_enable(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	/* Load the configurations of the two comparators used in the window */
+	uint32_t win_pair_comp0_conf = ac_module->COMPCTRL[win_channel * 2].reg;
+	uint32_t win_pair_comp1_conf = ac_module->COMPCTRL[win_channel * 2 + 1].reg;
+
+	/* Make sure both comparators in the window comparator pair are enabled */
+	if (!(win_pair_comp0_conf & AC_COMPCTRL_ENABLE) ||
+			!(win_pair_comp1_conf & AC_COMPCTRL_ENABLE)) {
+		return STATUS_ERR_IO;
+	}
+
+	/* Make sure the comparators are configured in the same way, other than the
+	 * negative pin multiplexers */
+	if ((win_pair_comp0_conf & ~AC_COMPCTRL_MUXNEG_Msk) !=
+			(win_pair_comp1_conf & ~AC_COMPCTRL_MUXNEG_Msk)) {
+		return STATUS_ERR_BAD_FORMAT;
+	}
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Enable the requested window comparator */
+	switch (win_channel)
+	{
+		case AC_WIN_CHANNEL_0:
+			ac_module->WINCTRL.reg |= AC_WINCTRL_WEN0;
+			break;
+
+#if (AC_PAIRS > 1)
+		case AC_WIN_CHANNEL_1:
+			ac_module->WINCTRL.reg |= AC_WINCTRL_WEN1;
+			break;
+#endif
+	}
+
+	return STATUS_OK;
+}
+
+/** \brief Disables an Analog Comparator window channel that was previously enabled.
+ *
+ *  Stops an Analog Comparator window channel that was previously started via a
+ *  call to \ref ac_win_enable().
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] win_channel  Comparator window channel to disable
+ */
+void ac_win_disable(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Disable the requested window comparator */
+	switch (win_channel)
+	{
+		case AC_WIN_CHANNEL_0:
+			ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+			break;
+
+#if (AC_PAIRS > 1)
+		case AC_WIN_CHANNEL_1:
+			ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN1;
+			break;
+#endif
+	}
+}
+
+/** \brief Determines the state of a specified Window Comparator.
+ *
+ *  Retrieves the current window detection state, indicating what the input
+ *  signal is currently comparing to relative to the window boundaries.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] win_channel  Comparator Window channel to test
+ *
+ *  \return Bit mask of Analog Comparator window channel status flags.
+ */
+uint8_t ac_win_get_status(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	uint32_t win_status = 0;
+
+	/* Check if interrupt flag is set */
+	if (ac_module->INTFLAG.reg & (AC_INTFLAG_WIN0 << win_channel)) {
+		win_status |= AC_WIN_STATUS_INTERRUPT_SET;
+	}
+
+	/* If one or both window comparators not ready, return unknown result */
+	if (ac_win_is_ready(module_inst, win_channel) == false) {
+		win_status |= AC_WIN_STATUS_UNKNOWN;
+		return win_status;
+	}
+
+	uint8_t statusa_tmp = ac_module->STATUSA.reg;
+
+	/* Map hardware comparison states to logical window states */
+	if (statusa_tmp & (AC_STATUSA_WSTATE0_BELOW << win_channel)) {
+		return win_status | AC_WIN_STATUS_BELOW;
+	} else if (statusa_tmp & (AC_STATUSA_WSTATE0_INSIDE << win_channel)) {
+		return win_status | AC_WIN_STATUS_INSIDE;
+	} else {
+		return win_status | AC_WIN_STATUS_ABOVE;
+	}
+
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_l_c/ac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_l_c/ac.c
new file mode 100644
index 0000000000..58aa561d0d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_l_c/ac.c
@@ -0,0 +1,420 @@
+/**
+ * \file
+ *
+ * \brief SAM Analog Comparator Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "ac.h"
+
+static enum status_code _ac_set_config(
+		struct ac_module *const module_inst,
+		struct ac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(config);
+
+	UNUSED(module_inst);
+
+	/* Set up GCLK */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->source_generator;
+#if (SAMC21) || (SAMC20)
+	/* The Analog Comparators and ADC1 use the same generic clock configuration.
+ 	 * GCLK_ADC1 must be used to configure the clock for AC as GCLK_AC is not 
+ 	 * functional. Errata reference: 13404 
+ 	 */
+	system_gclk_chan_set_config(34, &gclk_chan_conf);
+	system_gclk_chan_enable(34);
+#else
+	system_gclk_chan_set_config(AC_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(AC_GCLK_ID);
+#endif
+
+	return STATUS_OK;
+}
+
+/** \brief Resets and disables the Analog Comparator driver.
+ *
+ *  Resets and disables the Analog Comparator driver, resets the internal
+ *  states and registers of the hardware module to their power-on defaults.
+ *
+ * \param[out] module_inst  Pointer to the AC software instance struct
+ */
+enum status_code ac_reset(
+		struct ac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	/* Disable the hardware module */
+	ac_disable(module_inst);
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Software reset the module */
+	ac_module->CTRLA.reg |= AC_CTRLA_SWRST;
+
+	return STATUS_OK;
+}
+
+/** \brief Initializes and configures the Analog Comparator driver.
+ *
+ *  Initializes the Analog Comparator driver, configuring it to the user
+ *  supplied configuration parameters, ready for use. This function should be
+ *  called before enabling the Analog Comparator.
+ *
+ *  \note Once called the Analog Comparator will not be running; to start the
+ *        Analog Comparator call \ref ac_enable() after configuring the module.
+ *
+ * \param[out] module_inst  Pointer to the AC software instance struct
+ * \param[in]  hw           Pointer to the AC module instance
+ * \param[in]  config       Pointer to the config struct, created by the user
+ *                          application
+ */
+enum status_code ac_init(
+		struct ac_module *const module_inst,
+		Ac *const hw,
+		struct ac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module_inst->hw = hw;
+
+#if (SAML21) || (SAMR30)
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_AC);
+#else
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_AC);
+#endif
+
+#if AC_CALLBACK_MODE == true
+	/* Initialize parameters */
+	for (uint8_t i = 0; i < AC_CALLBACK_N; i++) {
+		module_inst->callback[i]        = NULL;
+	}
+
+	/* Initialize software flags*/
+	module_inst->register_callback_mask = 0x00;
+	module_inst->enable_callback_mask   = 0x00;
+
+#  if (AC_INST_NUM == 1)
+	_ac_instance[0] = module_inst;
+#  else
+	/* Register this instance for callbacks*/
+	_ac_instance[_ac_get_inst_index(hw)] = module_inst;
+#  endif
+#endif
+
+	/* Write configuration to module */
+	return _ac_set_config(module_inst, config);
+}
+
+/** \brief Writes an Analog Comparator channel configuration to the hardware module.
+ *
+ *  Writes a given Analog Comparator channel configuration to the hardware
+ *  module.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] channel      Analog Comparator channel to configure
+ *  \param[in] config       Pointer to the channel configuration struct
+ */
+enum status_code ac_chan_set_config(
+		struct ac_module *const module_inst,
+		const enum ac_chan_channel channel,
+		struct ac_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(config);
+
+	Ac *const ac_module = module_inst->hw;
+
+	/* Use a temporary variable to compute the comparator configuration */
+	uint32_t compctrl_temp = 0;
+
+	/* Enable output filter mode */
+	compctrl_temp |= config->filter;
+
+	/* Comparators should be enabled during sleep */
+	if (config->run_in_standby == true) {
+		compctrl_temp |= AC_COMPCTRL_RUNSTDBY;
+	}
+
+	/* Set output signal routing mode */
+	compctrl_temp |= config->output_mode;
+
+	/* Configure comparator positive and negative pin MUX configurations */
+	compctrl_temp |=
+			(uint32_t)config->positive_input |
+			(uint32_t)config->negative_input;
+
+	/* Set sampling mode (single shot or continuous) */
+	compctrl_temp |= config->sample_mode;
+
+	/* Set channel interrupt selection */
+	compctrl_temp |= config->interrupt_selection;
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Write the final configuration to the module's control register */
+	ac_module->COMPCTRL[(uint8_t)channel].reg = compctrl_temp;
+
+	/* Configure VCC voltage scaling for the comparator */
+	ac_module->SCALER[(uint8_t)channel].reg   = config->vcc_scale_factor - 1;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Function used to setup interrupt selection of a window.
+ *
+ * This function is used to setup when an interrupt should occur
+ * for a given window.
+ *
+ * \note This must be done before enabling the channel.
+ *
+ * \param[in]  module_inst  Pointer to software instance struct
+ * \param[in]  win_channel  Window channel to setup
+ * \param[in]  config       Configuration for the given window channel
+ *
+ * \retval  STATUS_OK               Function exited successful
+ * \retval  STATUS_ERR_INVALID_ARG  win_channel argument incorrect
+ */
+enum status_code ac_win_set_config(
+		struct ac_module *const module_inst,
+		enum ac_win_channel const win_channel,
+		struct ac_win_config *const config)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(config);
+
+	uint8_t winctrl_mask;
+
+	winctrl_mask = module_inst->hw->WINCTRL.reg;
+
+	if (win_channel == AC_WIN_CHANNEL_0) {
+		winctrl_mask &= ~AC_WINCTRL_WINTSEL0_Msk;
+		winctrl_mask |= config->interrupt_selection;
+	}
+#if (AC_PAIRS > 1)
+	else if (win_channel == AC_WIN_CHANNEL_1) {
+		winctrl_mask &= ~AC_WINCTRL_WINTSEL1_Msk;
+		winctrl_mask = (config->interrupt_selection << (AC_WINCTRL_WINTSEL1_Pos -
+		AC_WINCTRL_WINTSEL0_Pos));
+	}
+#endif /* (AC_PAIRS > 1) */
+	else {
+		return STATUS_ERR_INVALID_ARG ;
+	}
+
+	module_inst->hw->WINCTRL.reg = winctrl_mask;
+
+	return STATUS_OK;
+}
+
+/** \brief Enables an Analog Comparator window channel that was previously configured.
+ *
+ *  Enables and starts an Analog Comparator window channel.
+ *
+ *  \note The comparator channels used by the window channel must be configured
+ *        and enabled before calling this function. The two comparator channels
+ *        forming each window comparator pair must have identical configurations
+ *        other than the negative pin multiplexer setting.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] win_channel  Comparator window channel to enable
+ *
+ *  \return Status of the window enable procedure.
+ *
+ *  \retval STATUS_OK              The window comparator was enabled
+ *  \retval STATUS_ERR_IO          One or both comparators in the window
+ *                                 comparator pair is disabled
+ *  \retval STATUS_ERR_BAD_FORMAT  The comparator channels in the window pair
+ *                                 were not configured correctly
+ */
+enum status_code ac_win_enable(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	/* Load the configurations of the two comparators used in the window */
+	uint32_t win_pair_comp0_conf = ac_module->COMPCTRL[win_channel * 2].reg;
+	uint32_t win_pair_comp1_conf = ac_module->COMPCTRL[win_channel * 2 + 1].reg;
+
+	/* Make sure both comparators in the window comparator pair are enabled */
+	if (!(win_pair_comp0_conf & AC_COMPCTRL_ENABLE) ||
+			!(win_pair_comp1_conf & AC_COMPCTRL_ENABLE)) {
+		return STATUS_ERR_IO;
+	}
+
+	/* Make sure the comparators are configured in the same way, other than the
+	 * negative pin multiplexers */
+	if ((win_pair_comp0_conf & ~AC_COMPCTRL_MUXNEG_Msk) !=
+			(win_pair_comp1_conf & ~AC_COMPCTRL_MUXNEG_Msk)) {
+		return STATUS_ERR_BAD_FORMAT;
+	}
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Enable the requested window comparator */
+	switch (win_channel)
+	{
+		case AC_WIN_CHANNEL_0:
+			ac_module->WINCTRL.reg |= AC_WINCTRL_WEN0;
+			break;
+
+#if (AC_PAIRS > 1)
+		case AC_WIN_CHANNEL_1:
+			ac_module->WINCTRL.reg |= AC_WINCTRL_WEN1;
+			break;
+#endif
+	}
+
+	return STATUS_OK;
+}
+
+/** \brief Disables an Analog Comparator window channel that was previously enabled.
+ *
+ *  Stops an Analog Comparator window channel that was previously started via a
+ *  call to \ref ac_win_enable().
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] win_channel  Comparator window channel to disable
+ */
+void ac_win_disable(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	while (ac_is_syncing(module_inst)) {
+		/* Wait until synchronization is complete */
+	}
+
+	/* Disable the requested window comparator */
+	switch (win_channel)
+	{
+		case AC_WIN_CHANNEL_0:
+			ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+			break;
+
+#if (AC_PAIRS > 1)
+		case AC_WIN_CHANNEL_1:
+			ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN1;
+			break;
+#endif
+	}
+}
+
+/** \brief Determines the state of a specified Window Comparator.
+ *
+ *  Retrieves the current window detection state, indicating what the input
+ *  signal is currently comparing to relative to the window boundaries.
+ *
+ *  \param[in] module_inst  Software instance for the Analog Comparator peripheral
+ *  \param[in] win_channel  Comparator Window channel to test
+ *
+ *  \return Bit mask of Analog Comparator window channel status flags.
+ */
+uint8_t ac_win_get_status(
+		struct ac_module *const module_inst,
+		const enum ac_win_channel win_channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Ac *const ac_module = module_inst->hw;
+
+	uint32_t win_status = 0;
+
+	/* Check if interrupt flag is set */
+	if (ac_module->INTFLAG.reg & (AC_INTFLAG_WIN0 << win_channel)) {
+		win_status |= AC_WIN_STATUS_INTERRUPT_SET;
+	}
+
+	/* If one or both window comparators not ready, return unknown result */
+	if (ac_win_is_ready(module_inst, win_channel) == false) {
+		win_status |= AC_WIN_STATUS_UNKNOWN;
+		return win_status;
+	}
+
+	uint8_t statusa_tmp = ac_module->STATUSA.reg;
+
+	/* Map hardware comparison states to logical window states */
+	if (statusa_tmp & (AC_STATUSA_WSTATE0_BELOW << win_channel)) {
+		return win_status | AC_WIN_STATUS_BELOW;
+	} else if (statusa_tmp & (AC_STATUSA_WSTATE0_INSIDE << win_channel)) {
+		return win_status | AC_WIN_STATUS_INSIDE;
+	} else {
+		return win_status | AC_WIN_STATUS_ABOVE;
+	}
+
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc.h
new file mode 100644
index 0000000000..f273e60937
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc.h
@@ -0,0 +1,1156 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef ADC_H_INCLUDED
+#define ADC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_adc_group SAM Analog-to-Digital Converter (ADC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Analog-to-Digital Converter functionality, for
+ * the conversion of analog voltages into a corresponding digital form.
+ * The following driver Application Programming Interface (API) modes are covered by this manual:
+ * - Polled APIs
+ * \if ADC_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - ADC (Analog-to-Digital Converter)
+ *
+ * The following devices can use this module:
+ * \if DEVICE_SAML21_SUPPORT
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM C20/C21
+ * \else
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM HA1
+ * \endif
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_adc_prerequisites
+ *  - \ref asfdoc_sam0_adc_module_overview
+ *  - \ref asfdoc_sam0_adc_special_considerations
+ *  - \ref asfdoc_sam0_adc_extra_info
+ *  - \ref asfdoc_sam0_adc_examples
+ *  - \ref asfdoc_sam0_adc_api_overview
+ *
+ *
+ * \section asfdoc_sam0_adc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_adc_module_overview Module Overview
+ *
+ * This driver provides an interface for the Analog-to-Digital conversion
+ * functions on the device, to convert analog voltages to a corresponding
+ * digital value. The ADC has up to 12-bit resolution, and is capable of
+ * \if DEVICE_SAML21_SUPPORT
+ * converting up to 1,000,000 samples per second (MSPS).
+ * \else
+ * converting up to 500K samples per second (KSPS).
+ * \endif
+ *
+ * The ADC has a compare function for accurate monitoring of user defined
+ * thresholds with minimum software intervention required.
+ * The ADC may be configured for 8-, 10-, or 12-bit result, reducing the
+ * conversion time. ADC conversion results are provided left or right adjusted
+ * which eases calculation when the result is represented as a signed integer.
+ *
+ * The input selection is flexible, and both single-ended and differential
+ * measurements can be made. For differential measurements, an optional gain
+ * stage is available to increase the dynamic range. In addition, several
+ * internal signal inputs are available. The ADC can provide both signed and
+ * unsigned results.
+ *
+ * The ADC measurements can either be started by application software or an
+ * incoming event from another peripheral in the device, and both internal and
+ * external reference voltages can be selected.
+ *
+ * \note Internal references will be enabled by the driver, but not disabled.
+ *       Any reference not used by the application should be disabled by the application.
+ *
+ * A simplified block diagram of the ADC can be seen in
+ * \ref asfdoc_sam0_adc_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_adc_module_block_diagram
+ * \dot
+ * digraph overview {
+ * splines = false;
+ * rankdir=LR;
+ *
+ * mux1 [label="Positive input", shape=box];
+ * mux2 [label="Negative input", shape=box];
+ *
+ *
+ * mux3 [label="Reference", shape=box];
+ *
+ * adc [label="ADC", shape=polygon, sides=5, orientation=90, distortion=-0.6, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ * prescaler [label="PRESCALER", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * mux1 -> adc;
+ * mux2 -> adc;
+ * mux3 -> adc:sw;
+ * prescaler -> adc;
+ *
+ * postproc [label="Post processing", shape=box];
+ * result [label="RESULT", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * adc:e -> postproc:w;
+ * postproc:e -> result:w;
+ *
+ * {rank=same; mux1 mux2}
+ * {rank=same; prescaler adc}
+ *
+ * }
+ * \enddot
+ *
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_prescaler Sample Clock Prescaler
+ * The ADC features a prescaler, which enables conversion at lower clock rates
+ * than the input Generic Clock to the ADC module. This feature can be used to
+ * lower the synchronization time of the digital interface to the ADC module
+ * via a high speed Generic Clock frequency, while still allowing the ADC
+ * sampling rate to be reduced.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_resolution ADC Resolution
+ * The ADC supports full 8-, 10-, or 12-bit resolution. Hardware
+ * oversampling and decimation can be used to increase the
+ * effective resolution at the expense of throughput. Using oversampling and
+ * decimation mode the ADC resolution is increased from 12-bit to an effective
+ * 13-, 14-, 15-, or 16-bit. In these modes the conversion rate is reduced, as
+ * a greater number of samples is used to achieve the increased resolution. The
+ * available resolutions and effective conversion rate is listed in
+ * \ref asfdoc_sam0_adc_module_conversion_rate "the table below".
+ *
+ * \anchor asfdoc_sam0_adc_module_conversion_rate
+ * <table>
+ *	<caption>Effective ADC Conversion Speed Using Oversampling</caption>
+ *	<tr>
+ *		<th>Resolution</th>
+ *		<th>Effective conversion rate</th>
+ *	</tr>
+ *	<tr>
+ *		<td>13-bit</td>
+ *		<td>Conversion rate divided by 4</td>
+ *	</tr>
+ *	<tr>
+ *		<td>14-bit</td>
+ *		<td>Conversion rate divided by 16</td>
+ *	</tr>
+ *	<tr>
+ *		<td>15-bit</td>
+ *		<td>Conversion rate divided by 64</td>
+ *	</tr>
+ *	<tr>
+ *		<td>16-bit</td>
+ *		<td>Conversion rate divided by 256</td>
+ *	</tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_conversion Conversion Modes
+ * ADC conversions can be software triggered on demand by the user application,
+ * if continuous sampling is not required. It is also possible to configure the
+ * ADC in free running mode, where new conversions are started as soon as the
+ * previous conversion is completed, or configure the ADC to scan across a
+ * number of input pins (see \ref asfdoc_sam0_adc_module_overview_pin_scan).
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_diff_mode Differential and Single-ended Conversion
+ * The ADC has two conversion modes; differential and single-ended. When
+ * measuring signals where the positive input pin is always at a higher voltage
+ * than the negative input pin, the single-ended conversion mode should be used
+ * in order to achieve a full 12-bit output resolution.
+ *
+ * If however the positive input pin voltage may drop below the negative input
+ * pin the signed differential mode should be used.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_sample_time Sample Time
+ * The sample time for each ADC conversion is configurable as a number of half
+ * prescaled ADC clock cycles (depending on the prescaler value), allowing the
+ * user application to achieve faster or slower sampling depending on the
+ * source impedance of the ADC input channels. For applications with high
+ * impedance inputs the sample time can be increased to give the ADC an adequate
+ * time to sample and convert the input channel.
+ *
+ * The resulting sampling time is given by the following equation:
+ * \f[
+ * t_{SAMPLE} = (sample\_length+1) \times \frac{ADC_{CLK}} {2}
+ * \f]
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_averaging Averaging
+ * The ADC can be configured to trade conversion speed for accuracy by averaging
+ * multiple samples in hardware. This feature is suitable when operating in
+ * noisy conditions.
+ *
+ * You can specify any number of samples to accumulate (up to 1024) and the
+ * divide ratio to use (up to divide by 128). To modify these settings the
+ * ADC_RESOLUTION_CUSTOM needs to be set as the resolution. When this is set
+ * the number of samples to accumulate and the division ratio can be set by
+ * the configuration struct members \ref adc_config.accumulate_samples and
+ * \ref adc_config.divide_result. When using this mode the ADC result register
+ * will be set to be 16-bit wide to accommodate the larger result sizes
+ * produced by the accumulator.
+ *
+ * The effective ADC conversion rate will be reduced by a factor of the number
+ * of accumulated samples;
+ * however, the effective resolution will be increased according to
+ * \ref asfdoc_sam0_adc_module_hw_av_resolution "the table below".
+ *
+ * \anchor asfdoc_sam0_adc_module_hw_av_resolution
+ * <table>
+ *   <caption>Effective ADC Resolution From Various Hardware Averaging Modes</caption>
+ *   <tr>
+ *     <th>Number of samples</tr>
+ *     <th>Final result</tr>
+ *   </tr>
+ *   <tr>
+ *     <td>1</td>
+ *     <td>12-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>2</td>
+ *      <td>13-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>4</td>
+ *      <td>14-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>8</td>
+ *      <td>15-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>16</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>32</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>64</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>128</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>256</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>512</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>1024</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_offset_corr Offset and Gain Correction
+ * Inherent gain and offset errors affect the absolute accuracy of the ADC.
+ *
+ * The offset error is defined as the deviation of the ADC's actual transfer
+ * function from ideal straight line at zero input voltage.
+ *
+ * The gain error is defined as the deviation of the last output step's
+ * midpoint from the ideal straight line, after compensating for offset error.
+ *
+ * The offset correction value is subtracted from the converted data before the
+ * result is ready. The gain correction value is multiplied with the offset
+ * corrected value.
+ *
+ * The equation for both offset and gain error compensation is shown below:
+ * \f[
+ * ADC_{RESULT} = (VALUE_{CONV} + CORR_{OFFSET}) \times CORR_{GAIN}
+ * \f]
+ *
+ * When enabled, a given set of offset and gain correction values can be applied
+ * to the sampled data in hardware, giving a corrected stream of sample data to
+ * the user application at the cost of an increased sample latency.
+ *
+ * In single conversion, a latency of 13 ADC Generic Clock cycles is added for
+ * the final sample result availability. As the correction time is always less
+ * than the propagation delay, in free running mode this latency appears only
+ * during the first conversion. After the first conversion is complete, future
+ * conversion results are available at the defined sampling rate.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_pin_scan Pin Scan
+ * In pin scan mode, the first ADC conversion will begin from the configured
+ * positive channel, plus the requested starting offset. When the first
+ * conversion is completed, the next conversion will start at the next positive
+ * input channel and so on, until all requested pins to scan have been sampled
+ * and converted.
+ * SAM L21/L22 has automatic sequences feature instead of pin scan mode. In automatic
+ * sequence mode, all of 32 positives inputs can be included in a sequence. The
+ * sequence starts from the lowest input, and go to the next enabled input
+ * automatically.
+ *
+ * Pin scanning gives a simple mechanism to sample a large number of physical
+ * input channel samples, using a single physical ADC channel.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_window_monitor Window Monitor
+ * The ADC module window monitor function can be used to automatically compare
+ * the conversion result against a preconfigured pair of upper and lower
+ * threshold values.
+ *
+ * The threshold values are evaluated differently, depending on whether
+ * differential or single-ended mode is selected. In differential mode, the
+ * upper and lower thresholds are evaluated as signed values for the comparison,
+ * while in single-ended mode the comparisons are made as a set of unsigned
+ * values.
+ *
+ * The significant bits of the lower window monitor threshold and upper window
+ * monitor threshold values are user-configurable, and follow the overall ADC
+ * sampling bit precision set when the ADC is configured by the user application.
+ * For example, only the eight lower bits of the window threshold values will be
+ * compared to the sampled data whilst the ADC is configured in 8-bit mode.
+ * In addition, if using differential mode, the 8<SUP>th</SUP> bit will be considered as
+ * the sign bit even if bit 9 is zero.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_events Events
+ * Event generation and event actions are configurable in the ADC.
+ *
+ * The ADC has two actions that can be triggered upon event reception:
+ * \li Start conversion
+ * \li Flush pipeline and start conversion
+ *
+ * The ADC can generate two events:
+ * \li Window monitor
+ * \li Result ready
+ *
+ * If the event actions are enabled in the configuration, any incoming event
+ * will trigger the action.
+ *
+ * If the window monitor event is enabled, an event will be generated
+ * when the configured window condition is detected.
+ *
+ * If the result ready event is enabled, an event will be generated when a
+ * conversion is completed.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ *
+ * \section asfdoc_sam0_adc_special_considerations Special Considerations
+ *
+ * An integrated analog temperature sensor is available for use with the ADC.
+ * The bandgap voltage, as well as the scaled I/O and core voltages can also be
+ * measured by the ADC. For internal ADC inputs, the internal source(s) may need
+ * to be manually enabled by the user application before they can be measured.
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_adc_extra. This includes:
+ *  - \ref asfdoc_sam0_adc_extra_acronyms
+ *  - \ref asfdoc_sam0_adc_extra_dependencies
+ *  - \ref asfdoc_sam0_adc_extra_errata
+ *  - \ref asfdoc_sam0_adc_extra_history
+ *
+ *
+ * \section asfdoc_sam0_adc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_adc_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_adc_api_overview API Overview
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system.h>
+#include <adc_feature.h>
+
+/**
+ * \name Module Status Flags
+ *
+ * ADC status flags, returned by \ref adc_get_status() and cleared by
+ * \ref adc_clear_status().
+ *
+ * @{
+ */
+
+/** ADC result ready. */
+#define ADC_STATUS_RESULT_READY  (1UL << 0)
+/** Window monitor match. */
+#define ADC_STATUS_WINDOW        (1UL << 1)
+/** ADC result overwritten before read. */
+#define ADC_STATUS_OVERRUN       (1UL << 2)
+
+/** @} */
+
+#if ADC_CALLBACK_MODE == true
+#   if (ADC_INST_NUM > 1)
+#       define _ADC_INTERRUPT_VECT_NUM(n, unused) \
+			SYSTEM_INTERRUPT_MODULE_ADC##n,
+/**
+ * \internal Get the interrupt vector for the given device instance
+ *
+ * \param[in] The ADC module instance number
+ *
+ * \return Interrupt vector for of the given ADC module instance.
+ */
+static enum system_interrupt_vector _adc_interrupt_get_interrupt_vector(
+		uint32_t inst_num)
+{
+	static uint8_t adc_interrupt_vectors[ADC_INST_NUM] = {
+		MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_VECT_NUM, 0)
+	};
+
+	return (enum system_interrupt_vector)adc_interrupt_vectors[inst_num];
+}
+#   endif
+#endif
+
+#if !defined(__DOXYGEN__)
+uint8_t _adc_get_inst_index(
+		Adc *const hw);
+#endif
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+enum status_code adc_init(
+		struct adc_module *const module_inst,
+		Adc *hw,
+		struct adc_config *config);
+
+void adc_get_config_defaults(
+		struct adc_config *const config);
+
+#if (SAMD) || (SAMHA1) || (SAMR21)
+void adc_regular_ain_channel(
+		uint32_t *pin_array, uint8_t size);
+#endif
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ *
+ * \return Bitmask of \c ADC_STATUS_* flags.
+ *
+ * \retval ADC_STATUS_RESULT_READY  ADC result is ready to be read
+ * \retval ADC_STATUS_WINDOW        ADC has detected a value inside the set
+ *                                  window range
+ * \retval ADC_STATUS_OVERRUN       ADC result has overrun
+ */
+static inline uint32_t adc_get_status(
+		struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	uint32_t int_flags = adc_module->INTFLAG.reg;
+
+	uint32_t status_flags = 0;
+
+	/* Check for ADC Result Ready */
+	if (int_flags & ADC_INTFLAG_RESRDY) {
+		status_flags |= ADC_STATUS_RESULT_READY;
+	}
+
+	/* Check for ADC Window Match */
+	if (int_flags & ADC_INTFLAG_WINMON) {
+		status_flags |= ADC_STATUS_WINDOW;
+	}
+
+	/* Check for ADC Overrun */
+	if (int_flags & ADC_INTFLAG_OVERRUN) {
+		status_flags |= ADC_STATUS_OVERRUN;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst   Pointer to the ADC software instance struct
+ * \param[in] status_flags  Bitmask of \c ADC_STATUS_* flags to clear
+ */
+static inline void adc_clear_status(
+		struct adc_module *const module_inst,
+		const uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	uint32_t int_flags = 0;
+
+	/* Check for ADC Result Ready */
+	if (status_flags & ADC_STATUS_RESULT_READY) {
+		int_flags |= ADC_INTFLAG_RESRDY;
+	}
+
+	/* Check for ADC Window Match */
+	if (status_flags & ADC_STATUS_WINDOW) {
+		int_flags |= ADC_INTFLAG_WINMON;
+	}
+
+	/* Check for ADC Overrun */
+	if (status_flags & ADC_STATUS_OVERRUN) {
+		int_flags |= ADC_INTFLAG_OVERRUN;
+	}
+
+	/* Clear interrupt flag */
+	adc_module->INTFLAG.reg = int_flags;
+}
+/** @} */
+
+/**
+ * \name Enable, Disable, and Reset ADC Module, Start Conversion and Read Result
+ * @{
+ */
+
+/**
+ * \brief Enables the ADC module.
+ *
+ * Enables an ADC module that has previously been configured. If any internal reference
+ * is selected it will be enabled.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_enable(
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+#if ADC_CALLBACK_MODE == true
+#   if (ADC_INST_NUM > 1)
+	system_interrupt_enable(_adc_interrupt_get_interrupt_vector(
+			_adc_get_inst_index(adc_module)));
+#   elif (SAMC20)
+		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC0);
+#	else
+		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
+#   endif
+#endif
+
+	/* Disbale interrupt */
+	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
+
+	adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables the ADC module.
+ *
+ * Disables an ADC module that was previously enabled.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_disable(
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+#if ADC_CALLBACK_MODE == true
+#   if (ADC_INST_NUM > 1)
+	system_interrupt_disable(_adc_interrupt_get_interrupt_vector(
+			_adc_get_inst_index(adc_module)));
+#   elif (SAMC20)
+		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC0);
+#	else
+		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC);
+#   endif
+#endif
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Disbale interrupt */
+	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
+
+	adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Resets the ADC module.
+ *
+ * Resets an ADC module, clearing all module state, and registers to their
+ * default values.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_reset(
+		struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	/* Disable to make sure the pipeline is flushed before reset */
+	adc_disable(module_inst);
+
+	/* Software reset the module */
+	adc_module->CTRLA.reg |= ADC_CTRLA_SWRST;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Enables an ADC event input or output.
+ *
+ *  Enables one or more input or output events to or from the ADC module. See
+ *  \ref adc_events "Struct adc_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the ADC peripheral
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+static inline void adc_enable_events(
+		struct adc_module *const module_inst,
+		struct adc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Adc *const adc_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Window Monitor event */
+	if (events->generate_event_on_window_monitor) {
+		event_mask |= ADC_EVCTRL_WINMONEO;
+	}
+
+	/* Configure Result Ready event */
+	if (events->generate_event_on_conversion_done) {
+		event_mask |= ADC_EVCTRL_RESRDYEO;
+	}
+
+	adc_module->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables an ADC event input or output.
+ *
+ *  Disables one or more input or output events to or from the ADC module. See
+ *  \ref adc_events "Struct adc_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the ADC peripheral
+ *  \param[in] events       Struct containing flags of events to disable
+ */
+static inline void adc_disable_events(
+		struct adc_module *const module_inst,
+		struct adc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Adc *const adc_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Window Monitor event */
+	if (events->generate_event_on_window_monitor) {
+		event_mask |= ADC_EVCTRL_WINMONEO;
+	}
+
+	/* Configure Result Ready event */
+	if (events->generate_event_on_conversion_done) {
+		event_mask |= ADC_EVCTRL_RESRDYEO;
+	}
+
+	adc_module->EVCTRL.reg &= ~event_mask;
+}
+
+/**
+ * \brief Starts an ADC conversion.
+ *
+ * Starts a new ADC conversion.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline void adc_start_conversion(
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Reads the ADC result.
+ *
+ * Reads the result from an ADC conversion that was previously started.
+ *
+ * \param[in]  module_inst  Pointer to the ADC software instance struct
+ * \param[out] result       Pointer to store the result value in
+ *
+ * \return Status of the ADC read request.
+ * \retval STATUS_OK           The result was retrieved successfully
+ * \retval STATUS_BUSY         A conversion result was not ready
+ * \retval STATUS_ERR_OVERFLOW The result register has been overwritten by the
+ *                             ADC module before the result was read by the software
+ */
+static inline enum status_code adc_read(
+		struct adc_module *const module_inst,
+		uint16_t *result)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(result);
+
+	if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) {
+		/* Result not ready */
+		return STATUS_BUSY;
+	}
+
+	Adc *const adc_module = module_inst->hw;
+
+#if (SAMD) || (SAMHA1) || (SAMR21)
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+#endif
+
+	/* Get ADC result */
+	*result = adc_module->RESULT.reg;
+
+	/* Reset ready flag */
+	adc_clear_status(module_inst, ADC_STATUS_RESULT_READY);
+
+	if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) {
+		adc_clear_status(module_inst, ADC_STATUS_OVERRUN);
+		return STATUS_ERR_OVERFLOW;
+	}
+
+	return STATUS_OK;
+}
+
+/** @} */
+
+/**
+ * \name Runtime Changes of ADC Module
+ * @{
+ */
+
+/**
+ * \brief Flushes the ADC pipeline.
+ *
+ * Flushes the pipeline and restarts the ADC clock on the next peripheral clock
+ * edge. All conversions in progress will be lost. When flush is complete, the
+ * module will resume where it left off.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline void adc_flush(
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+void adc_set_window_mode(
+		struct adc_module *const module_inst,
+		const enum adc_window_mode window_mode,
+		const int16_t window_lower_value,
+		const int16_t window_upper_value);
+
+/**
+ * \brief Sets positive ADC input pin.
+ *
+ * Sets the positive ADC input pin selection.
+ *
+ * \param[in] module_inst     Pointer to the ADC software instance struct
+ * \param[in] positive_input  Positive input pin
+ */
+static inline void adc_set_positive_input(
+		struct adc_module *const module_inst,
+		const enum adc_positive_input positive_input)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set positive input pin */
+	adc_module->INPUTCTRL.reg =
+			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) |
+			(positive_input);
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+
+
+/**
+ * \brief Sets negative ADC input pin for differential mode.
+ *
+ * Sets the negative ADC input pin, when the ADC is configured in differential
+ * mode.
+ *
+ * \param[in] module_inst     Pointer to the ADC software instance struct
+ * \param[in] negative_input  Negative input pin
+ */
+static inline void adc_set_negative_input(
+		struct adc_module *const module_inst,
+		const enum adc_negative_input negative_input)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set negative input pin */
+	adc_module->INPUTCTRL.reg =
+			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) |
+			(negative_input);
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+
+/** @} */
+
+#if ADC_CALLBACK_MODE == true
+/**
+ * \name Enable and Disable Interrupts
+ * @{
+ */
+
+/**
+ * \brief Enable interrupt.
+ *
+ * Enable the given interrupt request from the ADC module.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] interrupt Interrupt to enable
+ */
+static inline void adc_enable_interrupt(struct adc_module *const module_inst,
+		enum adc_interrupt_flag interrupt)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+	/* Enable interrupt */
+	adc_module->INTENSET.reg = interrupt;
+}
+
+/**
+ * \brief Disable interrupt.
+ *
+ * Disable the given interrupt request from the ADC module.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] interrupt Interrupt to disable
+ */
+static inline void adc_disable_interrupt(struct adc_module *const module_inst,
+		enum adc_interrupt_flag interrupt)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+	/* Enable interrupt */
+	adc_module->INTENCLR.reg = interrupt;
+}
+
+/** @} */
+#endif /* ADC_CALLBACK_MODE == true */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+
+/**
+ * \page asfdoc_sam0_adc_extra Extra Information for ADC Driver
+ *
+ * \section asfdoc_sam0_adc_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>ADC</td>
+ *		<td>Analog-to-Digital Converter</td>
+ *	</tr>
+ *  <tr>
+ *		<td>DAC</td>
+ *		<td>Digital-to-Analog Converter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>LSB</td>
+ *		<td>Least Significant Bit</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MSB</td>
+ *		<td>Most Significant Bit</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DMA</td>
+ *		<td>Direct Memory Access</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ * \if DEVICE_SAML21_SUPPORT
+ *  <tr>
+ *		<td>Initial Release</td>
+ * </tr>
+ * \else
+ *	<tr>
+ *		<td>Added support for SAM R21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for SAM D21 and new DMA quick start guide</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added ADC calibration constant loading from the device signature
+ *          row when the module is initialized</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * \endif
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_adc_exqsg Examples for ADC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_adc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_adc_basic_use_case
+ * \if ADC_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_adc_basic_use_case_callback
+ * \endif
+ *  - \subpage asfdoc_sam0_adc_dma_use_case
+ *
+ * \page asfdoc_sam0_adc_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ * \if DEVICE_SAML21_SUPPORT
+ *	<tr>
+ *		<td>42451B</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L22</td>
+ *	</tr>
+ *  <tr>
+ *      <td>42451A</td>
+ *      <td>07/2015</td>
+ *      <td>Initial document release</td>
+ * </tr>
+ * \else
+ *	<tr>
+ *		<td>42109E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM DA1 and SAM D09</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42109D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42109C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42109B</td>
+ *		<td>06/2013</td>
+ *		<td>Added additional documentation on the event system. Corrected
+ *          documentation typos.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42109A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * \endif
+ * </table>
+ */
+
+#endif /* ADC_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_callback.h
new file mode 100644
index 0000000000..f6b30e86ed
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_callback.h
@@ -0,0 +1,182 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef ADC_CALLBACK_H_INCLUDED
+#define ADC_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_adc_group
+ *
+ * @{
+ */
+
+#include <adc.h>
+
+/**
+ * Enum for the possible types of ADC asynchronous jobs that may be issued to
+ * the driver.
+ */
+enum adc_job_type {
+	/** Asynchronous ADC read into a user provided buffer */
+	ADC_JOB_READ_BUFFER,
+};
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void adc_register_callback(
+		struct adc_module *const module,
+		adc_callback_t callback_func,
+		enum adc_callback callback_type);
+
+void adc_unregister_callback(
+		struct adc_module *module,
+		enum adc_callback callback_type);
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback function registered by \ref
+ * adc_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are met.
+ *
+ * \param[in]     module Pointer to ADC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return    Status of the operation.
+ * \retval     STATUS_OK              If operation was completed
+ * \retval     STATUS_ERR_INVALID     If operation was not completed,
+ *                                    due to invalid callback_type
+ *
+ */
+static inline void adc_enable_callback(
+		struct adc_module *const module,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->enabled_callback_mask |= (1 << callback_type);
+
+	/* Enable window interrupt if this is a window callback */
+	if (callback_type == ADC_CALLBACK_WINDOW) {
+		adc_enable_interrupt(module, ADC_INTERRUPT_WINDOW);
+	}
+	/* Enable overrun interrupt if error callback is registered */
+	if (callback_type == ADC_CALLBACK_ERROR) {
+		adc_enable_interrupt(module, ADC_INTERRUPT_OVERRUN);
+	}
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback function registered by the \ref
+ * adc_register_callback.
+ *
+ * \param[in]     module Pointer to ADC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return    Status of the operation.
+ * \retval     STATUS_OK              If operation was completed
+ * \retval     STATUS_ERR_INVALID     If operation was not completed,
+ *                                    due to invalid callback_type
+ *
+ */
+static inline void adc_disable_callback(
+		struct adc_module *const module,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->enabled_callback_mask &= ~(1 << callback_type);
+
+	/* Disable window interrupt if this is a window callback */
+	if (callback_type == ADC_CALLBACK_WINDOW) {
+		adc_disable_interrupt(module, ADC_INTERRUPT_WINDOW);
+	}
+	/* Disable overrun interrupt if this is the error callback */
+	if (callback_type == ADC_CALLBACK_ERROR) {
+		adc_disable_interrupt(module, ADC_INTERRUPT_OVERRUN);
+	}
+}
+
+/** @} */
+
+
+/**
+ * \name Job Management
+ * @{
+ */
+enum status_code adc_read_buffer_job(
+		struct adc_module *const module_inst,
+		uint16_t *buffer,
+		uint16_t samples);
+
+enum status_code adc_get_job_status(
+		struct adc_module *module_inst,
+		enum adc_job_type type);
+
+void adc_abort_job(
+		struct adc_module *module_inst,
+		enum adc_job_type type);
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ADC_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b.h
new file mode 100644
index 0000000000..5323ad92a1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b.h
@@ -0,0 +1,426 @@
+/**
+ * \file
+ *
+ * \brief SAMB Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef ADC_SAM_B_H_INCLUDED
+#define ADC_SAM_B_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_adc_group SAM Analog-to-Digital Converter (ADC) Driver
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's Analog-to-Digital Converter
+ * functionality, for the conversion of analog voltages into a corresponding
+ * digital form.
+ *
+ * The following peripheral is used by this module:
+ *  - ADC (Analog-to-Digital Converter)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_adc_prerequisites
+ *  - \ref asfdoc_samb_adc_module_overview
+ *  - \ref asfdoc_samb_adc_special_considerations
+ *  - \ref asfdoc_samb_adc_extra_info
+ *  - \ref asfdoc_samb_adc_examples
+ *  - \ref asfdoc_samb_adc_api_overview
+ *
+ *
+ * \section asfdoc_samb_adc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_adc_module_overview Module Overview
+ *
+ * This driver provides an interface for the Analog-to-Digital conversion
+ * functions on the device, to convert analog voltages to a corresponding
+ * digital value. The ADC has up to 12-bit resolution.
+ *
+ * \subsection asfdoc_samb_adc_module_overview_prescaler Sample Clock Prescaler
+ * \f[
+ *      F_{clk} = N + 2 \times {(throughput\_frequency)}
+ * \f]
+ * \f[
+ *      (N = ADC resolution)
+ * \f]
+ *
+ * Example: For throughput of 100KS/s use sampling clock (Fclk=1.3MHz)
+ *
+ * \subsection asfdoc_samb_adc_module_overview_resolution ADC Resolution
+ * There are two ADC resolution of operation:
+ * - \b High Resolution (11-bit)
+ *
+ *   Set the reference voltage to half the supply voltage or below. In this
+ *   mode the input signal dynamic range equals twice the reference voltage.
+ *
+ *   Example: If supply voltage =3V and reference voltage= 1.4V, input signal
+ *   dynamic range can be from ground to 2*reference voltage (0~2.8V).
+ * - \b Medium Resolution (10-bit)
+ *
+ *   Set the reference voltage to any value below supply voltage (up to
+ *   supply voltage - 300mV) and in this condition the input dynamic range is
+ *   from zero to reference voltage.
+ *
+ *   Example: If supply voltage =3V and reference voltage= 2.7V, input signal
+ *   dynamic range can be from ground to reference voltage (0~2.7V).
+ *
+ * \subsection asfdoc_samb_adc_module_overview_conversion Channel Modes
+ * There are two modes for input channel selection:
+ * - Either to assign a specific input channel
+ * - Time domain multiplexing between 4 input channels
+ *   - Channel1 to channel4
+ *   - channel5 to channel8
+ *
+ * \section asfdoc_samb_adc_special_considerations Special Considerations
+ * An integrated analog temperature sensor is available for use with the ADC.
+ * The internal specific voltage can also be measured by the ADC. For internal
+ * ADC inputs, the internal source(s) may need to be manually enabled by the
+ * user application before they can be measured.
+ *
+ *
+ * \section asfdoc_samb_adc_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_adc_extra. This includes:
+ *  - \ref asfdoc_samb_adc_extra_acronyms
+ *  - \ref asfdoc_samb_adc_extra_dependencies
+ *  - \ref asfdoc_samb_adc_extra_errata
+ *  - \ref asfdoc_samb_adc_extra_history
+ *
+ *
+ * \section asfdoc_samb_adc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_adc_exqsg.
+ *
+ *
+ * \section asfdoc_samb_adc_api_overview API Overview
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system_sam_b.h>
+
+/**
+ * \brief ADC internal reference voltage level enum
+ *
+ * Enum for the possible internal reference voltage level for the ADC.
+ *
+ */
+enum adc_internal_buf {
+	/** Internal buffer voltage level: 0.5V */
+	ADC_INTERNAL_BUF_0_5 = 0,
+	/** Internal buffer voltage level: 0.6V */
+	ADC_INTERNAL_BUF_0_6,
+	/** Internal buffer voltage level: 0.7V */
+	ADC_INTERNAL_BUF_0_7,
+	/** Internal buffer voltage level: 0.8V */
+	ADC_INTERNAL_BUF_0_8,
+	/** Internal buffer voltage level: 0.9V */
+	ADC_INTERNAL_BUF_0_9,
+	/** Internal buffer voltage level: 1.0V */
+	ADC_INTERNAL_BUF_1_0,
+	/** Internal buffer voltage level: 1.1V */
+	ADC_INTERNAL_BUF_1_1,
+	/** Internal buffer voltage level: 1.2V */
+	ADC_INTERNAL_BUF_1_2,
+	/** Internal buffer voltage level: 1.3V */
+	ADC_INTERNAL_BUF_1_3,
+	/** Internal buffer voltage level: 1.4V */
+	ADC_INTERNAL_BUF_1_4,
+	/** Internal buffer voltage level: 1.5V */
+	ADC_INTERNAL_BUF_1_5,
+	/** Internal buffer voltage level: 1.6V */
+	ADC_INTERNAL_BUF_1_6,
+	/** Internal buffer voltage level: 1.7V */
+	ADC_INTERNAL_BUF_1_7,
+	/** Internal buffer voltage level: 1.8V */
+	ADC_INTERNAL_BUF_1_8,
+	/** Internal buffer voltage level: 1.9V */
+	ADC_INTERNAL_BUF_1_9,
+	/** Internal buffer voltage level: 2.0V */
+	ADC_INTERNAL_BUF_2_0,
+};
+
+/**
+ * \brief ADC reference voltage enum
+ *
+ * Enum for the possible reference voltages for the ADC.
+ *
+ */
+enum adc_reference {
+	/** Internal form buffer reference */
+	ADC_REFERENCE_INTERNAL_BUF = 0,
+	/** Internal from IxR reference */
+	ADC_REFERENCE_INTERNAL_IR,
+	/**  VBATT/2 reference */
+	ADC_REFERENCE_VBATT_2,
+	/** GPIO_MS1 reference */
+	ADC_REFERENCE_GPIO_MS1,
+	/** GPIO_MS2 reference */
+	ADC_REFERENCE_GPIO_MS2,
+	/** GPIO_MS3 reference */
+	ADC_REFERENCE_GPIO_MS3,
+	/** GPIO_MS4 reference */
+	ADC_REFERENCE_GPIO_MS4,
+	/** VBATTERY reference */
+	ADC_REFERENCE_VBATT,
+};
+
+/**
+ * \brief ADC input channel selection enum
+ *
+ * Enum for the possible input channel selections for the ADC.
+ *
+ */
+enum adc_input_channel {
+	/** GPIO_MS1 input */
+	ADC_INPUT_CH_GPIO_MS1 = 0,
+	/** GPIO_MS2 input */
+	ADC_INPUT_CH_GPIO_MS2,
+	/** GPIO_MS3 input */
+	ADC_INPUT_CH_GPIO_MS3,
+	/** GPIO_MS4 input */
+	ADC_INPUT_CH_GPIO_MS4,
+	/** On chip temperature measurement input */
+	ADC_INPUT_CH_TEMPERATURE,
+	/** VBATT divided by 4 voltage level */
+	ADC_INPUT_CH_VBATT_4,
+	/** LP_LDO_OUT_1P2 low power domain voltage */
+	ADC_INPUT_CH_LPD0_LDO,
+	/**  ADC reference voltage level */
+	ADC_INPUT_CH_VREF,
+};
+
+/**
+ * \brief ADC input channel time multiplexing selection mode enum
+ *
+ * Enum for the possible channel time multiplexing mode for the ADC.
+ *
+ */
+enum adc_channel_mode {
+	/**
+	 * Input channels time multiplexing is between channel 0 to channel 3.
+	 * In this mode, ADC input channel selection is invalid.
+	 */
+	ADC_CH_MODE_CH0_TO_CH3,
+	/**
+	 * Input channels time multiplexing is between channel 4 to channel 7.
+	 * In this mode, ADC input channel selection is invalid.
+	 */
+	ADC_CH_MODE_CH4_TO_CH7,
+	/** Assign a specific input channel using \ref adc_input_channel */
+	ADC_CH_MODE_ASSIGN,
+};
+
+/**
+ * \brief ADC input dynamic range selection enum
+ *
+ * Enum for the possible input dynamic range for the ADC.
+ *
+ */
+enum adc_input_dynamic_range{
+	/** Input dynamic range from 0V to VBATT voltage level */
+	ADC_INPUT_DYNAMIC_RANGE_0 = 0,
+	/** Input dynamic range from 0.08*VBATT to 0.92*VBATT voltage level */
+	ADC_INPUT_DYNAMIC_RANGE_1,
+	/** Input dynamic range from 0.17*VBATT to 0.83*VBATT voltage level */
+	ADC_INPUT_DYNAMIC_RANGE_2,
+	/** Input dynamic range from 0.25*VBATT to 0.75*VBATT voltage level */
+	ADC_INPUT_DYNAMIC_RANGE_3,
+};
+
+/**
+ * \brief ADC comparator biasing current enum
+ *
+ * Enum for the possible comparator biasing current for the ADC different
+ * sampling rates.
+ *
+ */
+enum adc_bias_current {
+	/** Comparator bias current is 4uA for throughput 100KS/s */
+	ADC_BIAS_CURRENT_0 = 0,
+	/** Comparator bias current is 8uA */
+	ADC_BIAS_CURRENT_1,
+	/** Comparator bias current is 20uA */
+	ADC_BIAS_CURRENT_2,
+	/** Comparator bias current is 24uA for throughput 1MS/s */
+	ADC_BIAS_CURRENT_3,
+};
+
+/**
+ * \brief ADC configuration structure
+ *
+ * Configuration structure for an ADC instance. This structure should be
+ * initialized by the \ref adc_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct adc_config {
+	/** Voltage reference */
+	enum adc_reference reference;
+	/** Internal reference voltage level */
+	enum adc_internal_buf internal_vref;
+	/** Input channel */
+	enum adc_input_channel input_channel;
+	/** Input channel selection */
+	enum adc_channel_mode channel_mode;
+	/** Input channel time multiplexing selection mode */
+	enum adc_input_dynamic_range input_dynamic_range;
+	/** Comparator biasing current selection */
+	enum adc_bias_current bias_current;
+	/** Invert ADC Clock */
+	bool invert_clock;
+	/** Fractional part for the clock divider */
+	uint8_t frac_part;
+	/** Integer part for the clock divider */
+	uint16_t int_part;
+};
+
+/** \name Configuration, initialization and get status
+ * @{
+ */
+void adc_get_config_defaults(struct adc_config *const config);
+void adc_init(struct adc_config *config);
+uint32_t adc_get_status(void);
+/** @}*/
+
+/** \name Enable/Disable and Reset
+ * @{
+ */
+void adc_enable(void);
+void adc_disable(void);
+void adc_reset(void);
+/** @}*/
+
+/** \name Read Result
+ * @{
+ */
+enum status_code adc_read(enum adc_input_channel input_channel, uint16_t *result);
+/** @}*/
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \page asfdoc_samb_adc_extra Extra Information for ADC Driver
+ *
+ * \section asfdoc_samb_adc_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>ADC</td>
+ *		<td>Analog-to-Digital Converter</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_samb_adc_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_adc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_adc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_adc_exqsg Examples for ADC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_adc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_adc_basic_use_case
+ *
+ * \page asfdoc_samb_adc_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>09/2015</td>
+ *      <td>Initial document release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif /* ADC_SAM_B_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b/adc_sam_b.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b/adc_sam_b.c
new file mode 100644
index 0000000000..1db4725f2f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b/adc_sam_b.c
@@ -0,0 +1,280 @@
+/**
+ * \file
+ *
+ * \brief SAMB Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "adc_sam_b.h"
+
+static enum status_code _adc_gpio_ms_enable(enum adc_input_channel channel)
+{
+	switch (channel) {
+		case ADC_INPUT_CH_GPIO_MS1:
+			AON_GP_REGS0->MS_GPIO_MODE.reg |= \
+				AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_44;
+			break;
+		case ADC_INPUT_CH_GPIO_MS2:
+			AON_GP_REGS0->MS_GPIO_MODE.reg |= \
+				AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_45;
+		break;
+		case ADC_INPUT_CH_GPIO_MS3:
+			AON_GP_REGS0->MS_GPIO_MODE.reg |= \
+				AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_46;
+		break;
+		case ADC_INPUT_CH_GPIO_MS4:
+			AON_GP_REGS0->MS_GPIO_MODE.reg |= \
+				AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_47;
+		break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes an ADC configuration structure to defaults
+ *
+ * Initializes a given ADC configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li VBATT/2 as voltage reference
+ *  \li Internal reference voltage level 0.7V
+ *  \li On GPIO_MS1 input channel
+ *  \li Select one external input channels
+ *  \li Input channel time multiplexing selection mode
+ *  \li Comparator biasing current selection
+ *  \li No invert ADC clock
+ *  \li Fractional part for the clock divider is 0
+ *  \li Integer part for the clock divider is 0x12
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+void adc_get_config_defaults(struct adc_config *const config)
+{
+	Assert(config);
+	config->reference = ADC_REFERENCE_VBATT_2;
+	config->internal_vref = ADC_INTERNAL_BUF_1_5;
+	config->input_channel = ADC_INPUT_CH_GPIO_MS1;
+	config->channel_mode = ADC_CH_MODE_ASSIGN;
+	config->input_dynamic_range = ADC_INPUT_DYNAMIC_RANGE_3;
+	config->bias_current = ADC_BIAS_CURRENT_3;
+	config->invert_clock = false;
+	config->frac_part = 0;
+	config->int_part = 0x12;
+}
+
+/**
+ * \brief Initializes the ADC
+ *
+ * Initializes the ADC device struct and the hardware module based on the
+ * given configuration struct values.
+ *
+ * \param[in]  config      Pointer to the configuration struct
+ *
+ */
+void adc_init(struct adc_config *config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	if (config->invert_clock) {
+		LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg = LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_INVERT;
+	} else {
+		LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg &= ~LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_MASK;
+	}
+
+	/* Setting ADC clock */
+	LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg |= \
+			LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_FRAC_PART(config->frac_part) | \
+			LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_INT_PART(config->int_part);
+
+	if ((config->reference == ADC_REFERENCE_GPIO_MS1) || \
+		(config->reference == ADC_REFERENCE_GPIO_MS2) || \
+		(config->reference == ADC_REFERENCE_GPIO_MS3) || \
+		(config->reference == ADC_REFERENCE_GPIO_MS4)) {
+		_adc_gpio_ms_enable(config->reference - ADC_REFERENCE_GPIO_MS1);
+	}
+
+	AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_REF_SEL = config->reference;
+	AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_BIAS_RES_CTRL = config->internal_vref;
+
+	if (config->channel_mode == ADC_CH_MODE_ASSIGN) {
+		AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_CTRL = \
+				AON_GP_REGS_RF_PMU_REGS_1_SADC_CHN_CTRL_1_Val;
+		AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_SEL = config->input_channel;
+		
+		if (config->input_channel <= ADC_INPUT_CH_GPIO_MS4) {
+			/* Enable GPIO_MS pin */
+			_adc_gpio_ms_enable(config->input_channel);
+		}
+	} else if (config->channel_mode == ADC_CH_MODE_CH0_TO_CH3) {
+		/* Input channels time multiplexing is between channel 0 to channel 3 */
+		/* Config GPIO_MS1 ~ GPIO_MS4 pin */
+		AON_GP_REGS0->MS_GPIO_MODE.reg = AON_GP_REGS_MS_GPIO_MODE_MASK;
+	} else if (config->channel_mode == ADC_CH_MODE_CH4_TO_CH7) {
+		/* Input channels time multiplexing is between channel 4 to channel 7 */
+		AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_SEL = 0x4;
+	}
+
+	AON_GP_REGS0->RF_PMU_REGS_1.bit.CODE_IN = config->input_dynamic_range;
+	AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_LP_CTRL = config->bias_current;
+}
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \return ADC status.
+ */
+uint32_t adc_get_status(void)
+{
+	return (LPMCU_MISC_REGS0->SENS_ADC_RAW_STATUS.reg);
+}
+
+/**
+ * \brief Enables the ADC module.
+ *
+ * Enables an ADC module that has previously been configured.
+ *
+ */
+void adc_enable(void)
+{
+	///* Enable ADC clock */
+	system_clock_peripheral_enable(PERIPHERAL_ADC);
+
+	/* Enable ADC module */
+	AON_GP_REGS0->AON_PMU_CTRL.reg &= \
+		~AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_RST;
+	AON_GP_REGS0->AON_PMU_CTRL.reg |= \
+			AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_EN | \
+			AON_GP_REGS_AON_PMU_CTRL_PMU_BGR_EN;
+	for (uint16_t i = 0; i < 0xFF; i++) {
+		/* Waiting... */
+	}
+}
+
+/**
+ * \brief Disable the ADC module.
+ *
+ * Disable an ADC module that has previously been configured.
+ *
+ */
+void adc_disable(void)
+{
+	/* Disable ADC clock */
+	system_clock_peripheral_disable(PERIPHERAL_ADC);
+
+	/* Disable ADC module */
+	AON_GP_REGS0->AON_PMU_CTRL.reg &= \
+			~(AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_EN | \
+			AON_GP_REGS_AON_PMU_CTRL_PMU_BGR_EN);
+}
+
+/**
+ * \brief Reset the ADC module.
+ *
+ * Reset an ADC module that has previously been configured.
+ *
+ */
+void adc_reset(void)
+{
+	/* Reset ADC module */
+	system_peripheral_reset(PERIPHERAL_ADC);
+}
+
+/**
+ * \brief Reads the ADC result.
+ *
+ * Reads the result from an ADC conversion that was previously started.
+ *
+ * \param[in]  input_channel  Input channel which need to read the result
+ * \param[out] result         Pointer to store the result value in
+ *
+ * \return Status of the ADC read request.
+ * \retval STATUS_OK           The result was retrieved successfully
+ * \retval STATUS_BUSY         A conversion result was not ready
+ */
+enum status_code adc_read(enum adc_input_channel input_channel, uint16_t *result)
+
+{
+	Assert(result);
+
+	/* The transition of the ADC_DONE signal from LO to HI indicates that the
+	 * ADC conversion is done. */
+	while (adc_get_status() & LPMCU_MISC_REGS_SENS_ADC_RAW_STATUS_ADC_DONE) {
+		/* Waiting... */
+	}
+
+	while(!(adc_get_status() & LPMCU_MISC_REGS_SENS_ADC_RAW_STATUS_ADC_DONE)) {
+		/* Waiting... */
+	}
+
+	switch (input_channel) {
+		case ADC_INPUT_CH_GPIO_MS1:
+		case ADC_INPUT_CH_TEMPERATURE:
+			*result = LPMCU_MISC_REGS0->SENS_ADC_CH0_DATA.reg;
+			break;
+
+		case ADC_INPUT_CH_GPIO_MS2:
+		case ADC_INPUT_CH_VBATT_4:
+			*result = LPMCU_MISC_REGS0->SENS_ADC_CH1_DATA.reg;
+			break;
+
+		case ADC_INPUT_CH_GPIO_MS3:
+		case ADC_INPUT_CH_LPD0_LDO:
+			*result = LPMCU_MISC_REGS0->SENS_ADC_CH2_DATA.reg;
+			break;
+
+		case ADC_INPUT_CH_GPIO_MS4:
+		case ADC_INPUT_CH_VREF:
+			*result = LPMCU_MISC_REGS0->SENS_ADC_CH3_DATA.reg;
+			break;
+	}
+
+	return STATUS_OK;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc.c
new file mode 100644
index 0000000000..ddc2cfbd72
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc.c
@@ -0,0 +1,727 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "adc.h"
+
+#if SAMD20
+/* The Die revision D number */
+#define REVISON_D_NUM    3
+#endif
+
+/**
+ * \brief Initializes an ADC configuration structure to defaults
+ *
+ * Initializes a given ADC configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li GCLK generator 0 (GCLK main) clock source
+ *  \li 1V from internal bandgap reference
+ *  \li Div 4 clock prescaler
+ *  \li 12-bit resolution
+ *  \li Window monitor disabled
+ *  \li No gain
+ *  \li Positive input on ADC PIN 0
+ *  \li Negative input on ADC PIN 1
+ *  \li Averaging disabled
+ *  \li Oversampling disabled
+ *  \li Right adjust data
+ *  \li Single-ended mode
+ *  \li Free running disabled
+ *  \li All events (input and generation) disabled
+ *  \li Sleep operation disabled
+ *  \li No reference compensation
+ *  \li No gain/offset correction
+ *  \li No added sampling time
+ *  \li Pin scan mode disabled
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+void adc_get_config_defaults(struct adc_config *const config)
+{
+	Assert(config);
+	config->clock_source                  = GCLK_GENERATOR_0;
+	config->reference                     = ADC_REFERENCE_INT1V;
+	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV4;
+	config->resolution                    = ADC_RESOLUTION_12BIT;
+	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
+	config->window.window_upper_value     = 0;
+	config->window.window_lower_value     = 0;
+	config->gain_factor                   = ADC_GAIN_FACTOR_1X;
+#if SAMR21
+	config->positive_input                = ADC_POSITIVE_INPUT_PIN6 ;
+#else
+ 	config->positive_input                = ADC_POSITIVE_INPUT_PIN0 ;
+#endif
+	config->negative_input                = ADC_NEGATIVE_INPUT_GND ;
+	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
+	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
+	config->left_adjust                   = false;
+	config->differential_mode             = false;
+	config->freerunning                   = false;
+	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
+	config->run_in_standby                = false;
+	config->reference_compensation_enable = false;
+	config->correction.correction_enable  = false;
+	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
+	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
+	config->sample_length                 = 0;
+	config->pin_scan.offset_start_scan    = 0;
+	config->pin_scan.inputs_to_scan       = 0;
+}
+
+/**
+ * \brief Sets the ADC window mode
+ *
+ * Sets the ADC window mode to a given mode and value range.
+ *
+ * \param[in] module_inst         Pointer to the ADC software instance struct
+ * \param[in] window_mode         Window monitor mode to set
+ * \param[in] window_lower_value  Lower window monitor threshold value
+ * \param[in] window_upper_value  Upper window monitor threshold value
+  */
+void adc_set_window_mode(
+		struct adc_module *const module_inst,
+		const enum adc_window_mode window_mode,
+		const int16_t window_lower_value,
+		const int16_t window_upper_value)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set window mode */
+	adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set lower window monitor threshold value */
+	adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set upper window monitor threshold value */
+	adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
+}
+
+/**
+* \internal Configure MUX settings for the analog pins
+*
+* This function will set the given ADC input pins
+* to the analog function in the pinmux, giving
+* the ADC access to the analog signal
+*
+* \param [in] pin AINxx pin to configure
+*/
+static inline void _adc_configure_ain_pin(uint32_t pin)
+{
+#define PIN_INVALID_ADC_AIN    0xFFFFUL
+
+	/* Pinmapping table for AINxx -> GPIO pin number */
+	const uint32_t pinmapping[] = {
+#if (SAMD20E) || (SAMD21E)|| (SAMDA1E)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif SAMR21E
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif SAMR21G
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD09C) || (SAMD10C) || (SAMD11C)
+			PIN_PA02B_ADC_AIN0,  PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD09D)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD10DS) || (SAMD10DU) || (SAMD11DS) || (SAMD11DU)
+			PIN_PA02B_ADC_AIN0,  PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD10DM) || (SAMD11DM)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+			PIN_PA10B_ADC_AIN8,  PIN_PA11B_ADC_AIN9,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif SAM_PART_IS_DEFINED(SAMHA1G14A) || SAM_PART_IS_DEFINED(SAMHA1G15A) || \
+		SAM_PART_IS_DEFINED(SAMHA1G16A)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#else
+#  error ADC pin mappings are not defined for this device.
+#endif
+		};
+
+	uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
+
+	if (pin <= ADC_EXTCHANNEL_MSB) {
+		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+
+		Assert(pin_map_result != PIN_INVALID_ADC_AIN);
+
+		struct system_pinmux_config config;
+		system_pinmux_get_config_defaults(&config);
+
+		/* Analog functions are all on MUX setting B */
+		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+		config.mux_position = 1;
+
+		system_pinmux_pin_set_config(pin_map_result, &config);
+	}
+}
+
+/**
+ * \internal Writes an ADC configuration to the hardware module
+ *
+ * Writes out a given ADC module configuration to the hardware module.
+ *
+ * \param[out] module_inst  Pointer to the ADC software instance struct
+ * \param[in]  config       Pointer to configuration struct
+ *
+ * \return Status of the configuration procedure
+ * \retval STATUS_OK               The configuration was successful
+ * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
+ */
+static enum status_code _adc_set_config(
+		struct adc_module *const module_inst,
+		struct adc_config *const config)
+{
+	uint8_t adjres = 0;
+	uint32_t resolution = ADC_RESOLUTION_16BIT;
+	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+#if SAMD20
+	uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos);
+#endif
+
+	/* Get the hardware module pointer */
+	Adc *const adc_module = module_inst->hw;
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(ADC_GCLK_ID);
+
+	/* Setup pinmuxing for analog inputs */
+	if (config->pin_scan.inputs_to_scan != 0) {
+		uint8_t offset = config->pin_scan.offset_start_scan;
+		uint8_t start_pin =
+				offset +(uint8_t)config->positive_input;
+		uint8_t end_pin =
+				start_pin + config->pin_scan.inputs_to_scan;
+
+		while (start_pin < end_pin) {
+			_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
+			start_pin++;
+			offset++;
+		}
+		_adc_configure_ain_pin(config->negative_input);
+	} else {
+		_adc_configure_ain_pin(config->positive_input);
+		_adc_configure_ain_pin(config->negative_input);
+	}
+
+	/* Configure run in standby */
+	adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
+
+	/* Configure reference */
+	adc_module->REFCTRL.reg =
+			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
+			(config->reference);
+
+	/* Set adjusting result and number of samples */
+	switch (config->resolution) {
+
+	case ADC_RESOLUTION_CUSTOM:
+		adjres = config->divide_result;
+		accumulate = config->accumulate_samples;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_13BIT:
+		/* Increase resolution by 1 bit */
+		adjres = ADC_DIVIDE_RESULT_2;
+		accumulate = ADC_ACCUMULATE_SAMPLES_4;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_14BIT:
+		/* Increase resolution by 2 bit */
+		adjres = ADC_DIVIDE_RESULT_4;
+		accumulate = ADC_ACCUMULATE_SAMPLES_16;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+#if SAMD20
+	/* See $35.1.8 for ADC errata of SAM D20.
+	   The revisions before D have this issue.*/
+	case ADC_RESOLUTION_15BIT:
+		/* Increase resolution by 3 bit */
+		if(revision_num < REVISON_D_NUM) {
+			adjres = ADC_DIVIDE_RESULT_8;
+		} else {
+			adjres = ADC_DIVIDE_RESULT_2;
+		}
+		accumulate = ADC_ACCUMULATE_SAMPLES_64;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_16BIT:
+		if(revision_num < REVISON_D_NUM) {
+			/* Increase resolution by 4 bit */
+			adjres = ADC_DIVIDE_RESULT_16;
+		} else {
+			adjres = ADC_DIVIDE_RESULT_DISABLE;
+		}
+		accumulate = ADC_ACCUMULATE_SAMPLES_256;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+#else
+	case ADC_RESOLUTION_15BIT:
+		/* Increase resolution by 3 bit */
+		adjres = ADC_DIVIDE_RESULT_2;
+		accumulate = ADC_ACCUMULATE_SAMPLES_64;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_16BIT:
+		/* Increase resolution by 4 bit */
+		adjres = ADC_DIVIDE_RESULT_DISABLE;
+		accumulate = ADC_ACCUMULATE_SAMPLES_256;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+#endif
+	case ADC_RESOLUTION_8BIT:
+		/* 8-bit result register */
+		resolution = ADC_RESOLUTION_8BIT;
+		break;
+	case ADC_RESOLUTION_10BIT:
+		/* 10-bit result register */
+		resolution = ADC_RESOLUTION_10BIT;
+		break;
+	case ADC_RESOLUTION_12BIT:
+		/* 12-bit result register */
+		resolution = ADC_RESOLUTION_12BIT;
+		break;
+
+	default:
+		/* Unknown. Abort. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
+
+	/* Check validity of sample length value */
+	if (config->sample_length > 63) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		/* Configure sample length */
+		adc_module->SAMPCTRL.reg =
+				(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure CTRLB */
+	adc_module->CTRLB.reg =
+			config->clock_prescaler |
+			resolution |
+			(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
+			(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
+			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
+			(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
+
+	/* Check validity of window thresholds */
+	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
+		switch (resolution) {
+		case ADC_RESOLUTION_8BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 127 ||
+					config->window.window_lower_value < -128 ||
+					config->window.window_upper_value > 127 ||
+					config->window.window_upper_value < -128)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 255 ||
+					config->window.window_upper_value > 255){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_10BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 511 ||
+					config->window.window_lower_value < -512 ||
+					config->window.window_upper_value > 511 ||
+					config->window.window_upper_value < -512)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 1023 ||
+					config->window.window_upper_value > 1023){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_12BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 2047 ||
+					config->window.window_lower_value < -2048 ||
+					config->window.window_upper_value > 2047 ||
+					config->window.window_upper_value < -2048)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 4095 ||
+					config->window.window_upper_value > 4095){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_16BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 32767 ||
+					config->window.window_lower_value < -32768 ||
+					config->window.window_upper_value > 32767 ||
+					config->window.window_upper_value < -32768)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 65535 ||
+					config->window.window_upper_value > 65535){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		}
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure window mode */
+	adc_module->WINCTRL.reg = config->window.window_mode;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	adc_module->WINLT.reg =
+			config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	adc_module->WINUT.reg = config->window.window_upper_value <<
+			ADC_WINUT_WINUT_Pos;
+
+	uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
+	if (inputs_to_scan > 0) {
+		/*
+		* Number of input sources included is the value written to INPUTSCAN
+		* plus 1.
+		*/
+		inputs_to_scan--;
+	}
+
+	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+			config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
+		/* Invalid number of input pins or input offset */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure pin scan mode and positive and negative input pins */
+	adc_module->INPUTCTRL.reg =
+			config->gain_factor |
+			(config->pin_scan.offset_start_scan <<
+			ADC_INPUTCTRL_INPUTOFFSET_Pos) |
+			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
+			config->negative_input |
+			config->positive_input;
+
+	/* Configure events */
+	adc_module->EVCTRL.reg = config->event_action;
+
+	/* Disable all interrupts */
+	adc_module->INTENCLR.reg =
+			(1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
+			(1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
+
+	if (config->correction.correction_enable){
+		/* Make sure gain_correction value is valid */
+		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
+			return STATUS_ERR_INVALID_ARG;
+		} else {
+			/* Set gain correction value */
+			adc_module->GAINCORR.reg = config->correction.gain_correction <<
+					ADC_GAINCORR_GAINCORR_Pos;
+		}
+
+		/* Make sure offset correction value is valid */
+		if (config->correction.offset_correction > 2047 ||
+				config->correction.offset_correction < -2048) {
+			return STATUS_ERR_INVALID_ARG;
+		} else {
+			/* Set offset correction value */
+			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+					ADC_OFFSETCORR_OFFSETCORR_Pos;
+		}
+	}
+
+	/* Load in the fixed device ADC calibration constants */
+	adc_module->CALIB.reg =
+			ADC_CALIB_BIAS_CAL(
+				(*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
+			) |
+			ADC_CALIB_LINEARITY_CAL(
+				(*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
+			);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the ADC channel sequence
+ *
+ * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one 
+ * automatically after a conversion done, causing the next conversion 
+ * to be done with the positive input equal to MUXPOS + INPUTOFFSET, 
+ * it is scanning continuously one by one even ADC channels are not continuous.
+ *
+ * Initializes the ADC channel sequence by the sequence of pin_array.
+ *
+ * \param[in]  pin_array   The array of the Mux selection for the positive ADC input
+ * \param[in]  size        The size of pin_array
+ */
+void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size)
+{
+	for (int i = 0; i < size; i++) {
+		_adc_configure_ain_pin(pin_array[i]);
+  	}
+}	
+
+/**
+ * \brief Initializes the ADC
+ *
+ * Initializes the ADC device struct and the hardware module based on the
+ * given configuration struct values.
+ *
+ * \param[out] module_inst Pointer to the ADC software instance struct
+ * \param[in]  hw          Pointer to the ADC module instance
+ * \param[in]  config      Pointer to the configuration struct
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK                The initialization was successful
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) were provided
+ * \retval STATUS_BUSY          The module is busy with a reset operation
+ * \retval STATUS_ERR_DENIED        The module is enabled
+ */
+enum status_code adc_init(
+		struct adc_module *const module_inst,
+		Adc *hw,
+		struct adc_config *config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
+
+	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Store the selected reference for later use */
+	module_inst->reference = config->reference;
+
+	/* Make sure bandgap is enabled if requested by the config */
+	if (module_inst->reference == ADC_REFERENCE_INT1V) {
+		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
+	}
+
+#if ADC_CALLBACK_MODE == true
+	for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
+		module_inst->callback[i] = NULL;
+	};
+
+	module_inst->registered_callback_mask = 0;
+	module_inst->enabled_callback_mask = 0;
+	module_inst->remaining_conversions = 0;
+	module_inst->job_status = STATUS_OK;
+
+	_adc_instances[0] = module_inst;
+
+	if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
+			!config->freerunning) {
+		module_inst->software_trigger = true;
+	} else {
+		module_inst->software_trigger = false;
+	}
+#endif
+
+	/* Write configuration to module */
+	return _adc_set_config(module_inst, config);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c
new file mode 100644
index 0000000000..bc66eb5158
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c
@@ -0,0 +1,255 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "adc_callback.h"
+
+struct adc_module *_adc_instances[ADC_INST_NUM];
+
+static void _adc_interrupt_handler(const uint8_t instance)
+{
+	struct adc_module *module = _adc_instances[instance];
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->INTFLAG.reg;
+
+	if (flags & ADC_INTFLAG_RESRDY) {
+		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)) &&
+				(module->registered_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER))) {
+			/* clear interrupt flag */
+			module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+
+			while (adc_is_syncing(module)) {
+				/* Wait for synchronization */
+			}
+
+			/* store ADC result in job buffer */
+			*(module->job_buffer++) = module->hw->RESULT.reg;
+
+			if (--module->remaining_conversions > 0) {
+				if (module->software_trigger == true) {
+					adc_start_conversion(module);
+				}
+			} else {
+				if (module->job_status == STATUS_BUSY) {
+					/* job is complete. update status,disable interrupt
+					 *and call callback */
+					module->job_status = STATUS_OK;
+					adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY);
+
+					(module->callback[ADC_CALLBACK_READ_BUFFER])(module);
+				}
+			}
+		}
+	}
+
+	if (flags & ADC_INTFLAG_WINMON) {
+		module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON;
+		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) &&
+				(module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW))) {
+			(module->callback[ADC_CALLBACK_WINDOW])(module);
+		}
+
+	}
+
+	if (flags & ADC_INTFLAG_OVERRUN) {
+		module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) &&
+				(module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR))) {
+			(module->callback[ADC_CALLBACK_ERROR])(module);
+		}
+	}
+}
+
+/** Interrupt handler for the ADC module. */
+void ADC_Handler(void)
+{
+	_adc_interrupt_handler(0);
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by for the interrupt handler to call it
+ * when the condition for the callback is met.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] callback_func  Pointer to callback function
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void adc_register_callback(
+		struct adc_module *const module,
+		adc_callback_t callback_func,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->registered_callback_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void adc_unregister_callback(
+		struct adc_module *const module,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->registered_callback_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Read multiple samples from ADC
+ *
+ * Read \c samples samples from the ADC into the buffer \c buffer.
+ * If there is no hardware trigger defined (event action) the
+ * driver will retrigger the ADC conversion whenever a conversion
+ * is complete until \c samples samples has been acquired. To avoid
+ * jitter in the sampling frequency using an event trigger is advised.
+ *
+ * \param[in]  module_inst  Pointer to the ADC software instance struct
+ * \param[in]  samples      Number of samples to acquire
+ * \param[out] buffer       Buffer to store the ADC samples
+ *
+ * \return Status of the job start.
+ * \retval STATUS_OK        The conversion job was started successfully and is
+ *                          in progress
+ * \retval STATUS_BUSY      The ADC is already busy with another job
+ */
+enum status_code adc_read_buffer_job(
+		struct adc_module *const module_inst,
+		uint16_t *buffer,
+		uint16_t samples)
+{
+	Assert(module_inst);
+	Assert(samples);
+	Assert(buffer);
+
+	if(module_inst->remaining_conversions != 0 ||
+			module_inst->job_status == STATUS_BUSY){
+		return STATUS_BUSY;
+	}
+
+	module_inst->job_status = STATUS_BUSY;
+	module_inst->remaining_conversions = samples;
+	module_inst->job_buffer = buffer;
+
+	adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+
+	if(module_inst->software_trigger == true) {
+		adc_start_conversion(module_inst);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Gets the status of a job
+ *
+ * Gets the status of an ongoing or the last job.
+ *
+ * \param [in]  module_inst Pointer to the ADC software instance struct
+ * \param [in]  type        Type of job to get status
+ *
+ * \return Status of the job.
+ */
+enum status_code adc_get_job_status(
+		struct adc_module *module_inst,
+		enum adc_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == ADC_JOB_READ_BUFFER ) {
+		return module_inst->job_status;
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Aborts an ongoing job
+ *
+ * Aborts an ongoing job.
+ *
+ * \param [in]  module_inst Pointer to the ADC software instance struct
+ * \param [in]  type        Type of job to abort
+ */
+void adc_abort_job(
+		struct adc_module *module_inst,
+		enum adc_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == ADC_JOB_READ_BUFFER) {
+		/* Disable interrupt */
+		adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+		/* Mark job as aborted */
+		module_inst->job_status = STATUS_ABORTED;
+		module_inst->remaining_conversions = 0;
+	}
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
new file mode 100644
index 0000000000..203f15be14
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
@@ -0,0 +1,728 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC functionality
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef ADC_FEATURE_H_INCLUDED
+#define ADC_FEATURE_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_adc_group
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if ADC_CALLBACK_MODE == true
+#  include <system_interrupt.h>
+
+#if !defined(__DOXYGEN__)
+extern struct adc_module *_adc_instances[ADC_INST_NUM];
+#endif
+
+/** Forward definition of the device instance. */
+struct adc_module;
+
+/** Type of the callback functions. */
+typedef void (*adc_callback_t)(struct adc_module *const module);
+
+/**
+ * \brief ADC Callback enum
+ *
+ * Callback types for ADC callback driver.
+ *
+ */
+enum adc_callback {
+	/** Callback for buffer received */
+	ADC_CALLBACK_READ_BUFFER,
+	/** Callback when window is hit */
+	ADC_CALLBACK_WINDOW,
+	/** Callback for error */
+	ADC_CALLBACK_ERROR,
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	ADC_CALLBACK_N,
+#  endif
+};
+
+#endif
+
+/**
+ * \brief ADC reference voltage enum
+ *
+ * Enum for the possible reference voltages for the ADC.
+ *
+ */
+enum adc_reference {
+	/** 1.0V voltage reference */
+	ADC_REFERENCE_INT1V   = ADC_REFCTRL_REFSEL_INT1V,
+	/** 1/1.48V<SUB>CC</SUB> reference */
+	ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
+	/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
+	ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
+	/** External reference A */
+	ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
+	/** External reference B */
+	ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
+};
+
+/**
+ * \brief ADC clock prescaler enum
+ *
+ * Enum for the possible clock prescaler values for the ADC.
+ *
+ */
+enum adc_clock_prescaler {
+	/** ADC clock division factor 4 */
+	ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
+	/** ADC clock division factor 8 */
+	ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
+	/** ADC clock division factor 16 */
+	ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
+	/** ADC clock division factor 32 */
+	ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
+	/** ADC clock division factor 64 */
+	ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
+	/** ADC clock division factor 128 */
+	ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
+	/** ADC clock division factor 256 */
+	ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
+	/** ADC clock division factor 512 */
+	ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
+};
+
+/**
+ * \brief ADC resolution enum
+ *
+ * Enum for the possible resolution values for the ADC.
+ *
+ */
+enum adc_resolution {
+	/** ADC 12-bit resolution */
+	ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
+	/** ADC 16-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
+	/** ADC 10-bit resolution */
+	ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
+	/** ADC 8-bit resolution */
+	ADC_RESOLUTION_8BIT  = ADC_CTRLB_RESSEL_8BIT,
+	/** ADC 13-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_13BIT,
+	/** ADC 14-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_14BIT,
+	/** ADC 15-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_15BIT,
+	/** ADC 16-bit result register for use with averaging. When using this mode
+	  * the ADC result register will be set to 16-bit wide, and the number of
+	  * samples to accumulate and the division factor is configured by the
+	  * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
+	  * members in the configuration struct.
+	  */
+	ADC_RESOLUTION_CUSTOM,
+};
+
+/**
+ * \brief ADC window monitor mode enum
+ *
+ * Enum for the possible window monitor modes for the ADC.
+ *
+ */
+enum adc_window_mode {
+	/** No window mode */
+	ADC_WINDOW_MODE_DISABLE          = ADC_WINCTRL_WINMODE_DISABLE,
+	/** RESULT > WINLT */
+	ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_WINCTRL_WINMODE_MODE1,
+	/** RESULT < WINUT */
+	ADC_WINDOW_MODE_BELOW_UPPER      = ADC_WINCTRL_WINMODE_MODE2,
+	/** WINLT < RESULT < WINUT */
+	ADC_WINDOW_MODE_BETWEEN          = ADC_WINCTRL_WINMODE_MODE3,
+	/** !(WINLT < RESULT < WINUT) */
+	ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
+};
+
+/**
+ * \brief ADC gain factor selection enum
+ *
+ * Enum for the possible gain factor values for the ADC.
+ *
+ */
+enum adc_gain_factor {
+	/** 1x gain */
+	ADC_GAIN_FACTOR_1X   = ADC_INPUTCTRL_GAIN_1X,
+	/** 2x gain */
+	ADC_GAIN_FACTOR_2X   = ADC_INPUTCTRL_GAIN_2X,
+	/** 4x gain */
+	ADC_GAIN_FACTOR_4X   = ADC_INPUTCTRL_GAIN_4X,
+	/** 8x gain */
+	ADC_GAIN_FACTOR_8X   = ADC_INPUTCTRL_GAIN_8X,
+	/** 16x gain */
+	ADC_GAIN_FACTOR_16X  = ADC_INPUTCTRL_GAIN_16X,
+	/** 1/2x gain */
+	ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
+};
+
+/**
+ * \brief ADC event action enum
+ *
+ * Enum for the possible actions to take on an incoming event.
+ *
+ */
+enum adc_event_action {
+	/** Event action disabled */
+	ADC_EVENT_ACTION_DISABLED         = 0,
+	/** Flush ADC and start conversion */
+	ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
+	/** Start conversion */
+	ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
+};
+
+/**
+ * \brief ADC positive MUX input selection enum
+ *
+ * Enum for the possible positive MUX input selections for the ADC.
+ *
+ */
+enum adc_positive_input {
+	/** ADC0 pin */
+	ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_PIN0,
+	/** ADC1 pin */
+	ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_PIN1,
+	/** ADC2 pin */
+	ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_PIN2,
+	/** ADC3 pin */
+	ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_PIN3,
+	/** ADC4 pin */
+	ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_PIN4,
+	/** ADC5 pin */
+	ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_PIN5,
+	/** ADC6 pin */
+	ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_PIN6,
+	/** ADC7 pin */
+	ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_PIN7,
+	/** ADC8 pin */
+	ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_PIN8,
+	/** ADC9 pin */
+	ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_PIN9,
+	/** ADC10 pin */
+	ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_PIN10,
+	/** ADC11 pin */
+	ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_PIN11,
+	/** ADC12 pin */
+	ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_PIN12,
+	/** ADC13 pin */
+	ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_PIN13,
+	/** ADC14 pin */
+	ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_PIN14,
+	/** ADC15 pin */
+	ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_PIN15,
+	/** ADC16 pin */
+	ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_PIN16,
+	/** ADC17 pin */
+	ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_PIN17,
+	/** ADC18 pin */
+	ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_PIN18,
+	/** ADC19 pin */
+	ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_PIN19,
+	/** Temperature reference */
+	ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
+	/** Bandgap voltage */
+	ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
+	/** 1/4 scaled core supply */
+	ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
+	/** 1/4 scaled I/O supply */
+	ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
+	/** DAC input */
+	ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
+};
+
+/**
+ * \brief ADC negative Multiplexer(MUX) input selection enum
+ *
+ * Enum for the possible negative Multiplexer(MUX) input selections for the ADC.
+ *
+ */
+enum adc_negative_input {
+	/** ADC0 pin */
+	ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_PIN0,
+	/** ADC1 pin */
+	ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_PIN1,
+	/** ADC2 pin */
+	ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_PIN2,
+	/** ADC3 pin */
+	ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_PIN3,
+	/** ADC4 pin */
+	ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_PIN4,
+	/** ADC5 pin */
+	ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_PIN5,
+	/** ADC6 pin */
+	ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_PIN6,
+	/** ADC7 pin */
+	ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_PIN7,
+	/** Internal ground */
+	ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG_GND,
+	/** I/O ground */
+	ADC_NEGATIVE_INPUT_IOGND         = ADC_INPUTCTRL_MUXNEG_IOGND,
+};
+
+/**
+ * \brief ADC number of accumulated samples enum
+ *
+ * Enum for the possible numbers of ADC samples to accumulate.
+ * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
+ * resolution setting is used.
+ *
+ */
+enum adc_accumulate_samples {
+	/** No averaging */
+	ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
+	/** Average 2 samples */
+	ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
+	/** Average 4 samples */
+	ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
+	/** Average 8 samples */
+	ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
+	/** Average 16 samples */
+	ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
+	/** Average 32 samples */
+	ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
+	/** Average 64 samples */
+	ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
+	/** Average 128 samples */
+	ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
+	/** Average 256 samples */
+	ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
+	/** Average 512 samples */
+	ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
+	/** Average 1024 samples */
+	ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
+};
+
+/**
+ * \brief ADC possible dividers for the result register
+ *
+ * Enum for the possible division factors to use when accumulating
+ * multiple samples. To keep the same resolution for the averaged
+ * result and the actual input value, the division factor must
+ * be equal to the number of samples accumulated. This setting is only
+ * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
+ */
+enum adc_divide_result {
+	/** Don't divide result register after accumulation */
+	ADC_DIVIDE_RESULT_DISABLE = 0,
+	/** Divide result register by 2 after accumulation */
+	ADC_DIVIDE_RESULT_2       = 1,
+	/** Divide result register by 4 after accumulation */
+	ADC_DIVIDE_RESULT_4       = 2,
+	/** Divide result register by 8 after accumulation */
+	ADC_DIVIDE_RESULT_8       = 3,
+	/** Divide result register by 16 after accumulation */
+	ADC_DIVIDE_RESULT_16      = 4,
+	/** Divide result register by 32 after accumulation */
+	ADC_DIVIDE_RESULT_32      = 5,
+	/** Divide result register by 64 after accumulation */
+	ADC_DIVIDE_RESULT_64      = 6,
+	/** Divide result register by 128 after accumulation */
+	ADC_DIVIDE_RESULT_128     = 7,
+};
+
+#if ADC_CALLBACK_MODE == true
+/**
+ * Enum for the possible ADC interrupt flags.
+ */
+enum adc_interrupt_flag {
+	/** ADC result ready */
+	ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
+	/** Window monitor match */
+	ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
+	/** ADC result overwritten before read */
+	ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
+};
+#endif
+
+/**
+ * \brief ADC oversampling and decimation enum
+ *
+ * Enum for the possible numbers of bits resolution can be increased by when
+ * using oversampling and decimation.
+ *
+ */
+enum adc_oversampling_and_decimation {
+	/** Don't use oversampling and decimation mode */
+	ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
+	/** 1-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
+	/** 2-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
+	/** 3-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
+	/** 4-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_4BIT
+};
+
+/**
+ * \brief Window monitor configuration structure
+ *
+ * Window monitor configuration structure.
+ */
+struct adc_window_config {
+	/** Selected window mode */
+	enum adc_window_mode window_mode;
+	/** Lower window value */
+	int32_t window_lower_value;
+	/** Upper window value */
+	int32_t window_upper_value;
+};
+
+/**
+ * \brief ADC event enable/disable structure.
+ *
+ * Event flags for the ADC module. This is used to enable and
+ * disable events via \ref adc_enable_events() and \ref adc_disable_events().
+ */
+struct adc_events {
+	/** Enable event generation on conversion done */
+	bool generate_event_on_conversion_done;
+	/** Enable event generation on window monitor */
+	bool generate_event_on_window_monitor;
+};
+
+/**
+ * \brief Gain and offset correction configuration structure
+ *
+ * Gain and offset correction configuration structure.
+ * Part of the \ref adc_config struct and will  be initialized by
+ * \ref adc_get_config_defaults.
+ */
+struct adc_correction_config {
+	/**
+	 * Enables correction for gain and offset based on values of gain_correction and
+	 * offset_correction if set to true
+	 */
+	bool correction_enable;
+	/**
+	 * This value defines how the ADC conversion result is compensated for gain
+	 * error before written to the result register. This is a fractional value,
+	 * 1-bit integer plus an 11-bit fraction, therefore
+	 * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
+	 * \c 0b010000000000 to \c 0b111111111111.
+	 */
+	uint16_t gain_correction;
+	/**
+	 * This value defines how the ADC conversion result is compensated for
+	 * offset error before written to the result register. This is a 12-bit
+	 * value in two's complement format.
+	 */
+	int16_t offset_correction;
+};
+
+/**
+ * \brief Pin scan configuration structure
+ *
+ * Pin scan configuration structure. Part of the \ref adc_config struct and will
+ * be initialized by \ref adc_get_config_defaults.
+ */
+struct adc_pin_scan_config {
+	/**
+	 * Offset (relative to selected positive input) of the first input pin to be
+	 * used in pin scan mode
+	 */
+	uint8_t offset_start_scan;
+	/**
+	 * Number of input pins to scan in pin scan mode. A value below two will
+	 * disable pin scan mode.
+	 */
+	uint8_t inputs_to_scan;
+};
+
+/**
+ * \brief ADC configuration structure
+ *
+ * Configuration structure for an ADC instance. This structure should be
+ * initialized by the \ref adc_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct adc_config {
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+	/** Voltage reference */
+	enum adc_reference reference;
+	/** Clock prescaler */
+	enum adc_clock_prescaler clock_prescaler;
+	/** Result resolution */
+	enum adc_resolution resolution;
+	/** Gain factor */
+	enum adc_gain_factor gain_factor;
+	/** Positive Multiplexer (MUX) input */
+	enum adc_positive_input positive_input;
+	/** Negative MUX input. For singled-ended conversion mode, the negative
+	 * input must be connected to ground. This ground could be the internal
+	 * GND, IOGND or an external ground connected to a pin. */
+	enum adc_negative_input negative_input;
+	/** Number of ADC samples to accumulate when using the
+	 *  \c ADC_RESOLUTION_CUSTOM mode. Note: if the result width increases,
+	 *  result resolution will be changed accordingly.
+	 */
+	enum adc_accumulate_samples accumulate_samples;
+	/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
+	enum adc_divide_result divide_result;
+	/** Left adjusted result */
+	bool left_adjust;
+	/** Enables differential mode if true. 
+	 * if false, ADC will run in singled-ended mode. */
+	bool differential_mode;
+	/** Enables free running mode if true */
+	bool freerunning;
+	/** Enables ADC in standby sleep mode if true */
+	bool run_in_standby;
+	/**
+	 * Enables reference buffer offset compensation if true.
+	 * This will increase the accuracy of the gain stage, but decreases the input
+	 * impedance; therefore the startup time of the reference must be increased.
+	 */
+	bool reference_compensation_enable;
+	/**
+	 * This value (0-63) control the ADC sampling time in number of half ADC
+	 * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
+	 * controlling the ADC input impedance. Sampling time is set according to
+	 * the formula:
+	 * Sample time = (sample_length+1) * (ADCclk / 2).
+	 */
+	uint8_t sample_length;
+	/** Window monitor configuration structure */
+	struct adc_window_config window;
+	/** Gain and offset correction configuration structure */
+	struct adc_correction_config correction;
+	/** Event action to take on incoming event */
+	enum adc_event_action event_action;
+	/** Pin scan configuration structure */
+	struct adc_pin_scan_config pin_scan;
+};
+
+/**
+ * \brief ADC software device instance structure.
+ *
+ * ADC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct adc_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to ADC hardware module */
+	Adc *hw;
+	/** Keep reference configuration so we know when enable is called */
+	enum adc_reference reference;
+#  if ADC_CALLBACK_MODE == true
+	/** Array to store callback functions */
+	adc_callback_t callback[ADC_CALLBACK_N];
+	/** Pointer to buffer used for ADC results */
+	volatile uint16_t *job_buffer;
+	/** Remaining number of conversions in current job */
+	volatile uint16_t remaining_conversions;
+	/** Bit mask for callbacks registered */
+	uint8_t registered_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t enabled_callback_mask;
+	/** Holds the status of the ongoing or last conversion job */
+	volatile enum status_code job_status;
+	/** If software triggering is needed */
+	bool software_trigger;
+#  endif
+#endif
+};
+
+#if !defined(__DOXYGEN__)
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static inline bool adc_is_syncing(
+	struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+
+	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+		return true;
+	}
+
+	return false;
+}
+#endif
+
+/**
+ * \name ADC Gain and Pin Scan Mode
+ * @{
+ */
+
+/**
+ * \brief Sets ADC gain factor
+ *
+ * Sets the ADC gain factor to a specified gain setting.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ * \param[in] gain_factor  Gain factor value to set
+ */
+static inline void adc_set_gain(
+		struct adc_module *const module_inst,
+		const enum adc_gain_factor gain_factor)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set new gain factor */
+	adc_module->INPUTCTRL.reg =
+			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
+			(gain_factor);
+}
+
+/**
+ * \brief Sets the ADC pin scan mode
+ *
+ * Configures the pin scan mode of the ADC module. In pin scan mode, the first
+ * conversion will start at the configured positive input + start_offset. When
+ * a conversion is done, a conversion will start on the next input, until
+ * \c inputs_to_scan number of conversions are made.
+ *
+ * \param[in] module_inst     Pointer to the ADC software instance struct
+ * \param[in] inputs_to_scan  Number of input pins to perform a conversion on
+ *                            (must be two or more)
+ * \param[in] start_offset    Offset of first pin to scan (relative to
+ *                            configured positive input)
+ *
+ * \return Status of the pin scan configuration set request.
+ *
+ * \retval STATUS_OK               Pin scan mode has been set successfully
+ * \retval STATUS_ERR_INVALID_ARG  Number of input pins to scan or offset has
+ *                                 an invalid value
+ */
+static inline enum status_code adc_set_pin_scan_mode(
+		struct adc_module *const module_inst,
+		uint8_t inputs_to_scan,
+		const uint8_t start_offset)
+
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	if (inputs_to_scan > 0) {
+		/*
+		* Number of input sources included is the value written to INPUTSCAN
+		* plus 1.
+		*/
+		inputs_to_scan--;
+	}
+
+	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+			start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
+		/* Invalid number of input pins */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set pin scan mode */
+	adc_module->INPUTCTRL.reg =
+			(adc_module->INPUTCTRL.reg &
+			~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
+			(start_offset   << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
+			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables pin scan mode
+ *
+ * Disables pin scan mode. The next conversion will be made on only one pin
+ * (the configured positive input pin).
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline void adc_disable_pin_scan_mode(
+		struct adc_module *const module_inst)
+{
+	/* Disable pin scan mode */
+	adc_set_pin_scan_mode(module_inst, 0, 0);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_FEATURE_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc.c
new file mode 100644
index 0000000000..77d02388d8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc.c
@@ -0,0 +1,820 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "adc.h"
+#if (ADC_INST_NUM > 1) || (SAMC20)
+
+#  define _ADC_GCLK_ID(n,unused)           TPASTE3(ADC,n,_GCLK_ID),
+#  define _ADC_APBCMASK(n,unused)          TPASTE2(MCLK_APBCMASK_ADC,n),
+
+#  define _ADC_FUSES_BIASCOMP_ADDR(n,unused)        TPASTE3(ADC,n,_FUSES_BIASCOMP_ADDR),
+#  define _ADC_FUSES_BIASCOMP_Pos(n,unused)         TPASTE3(ADC,n,_FUSES_BIASCOMP_Pos),
+#  define _ADC_FUSES_BIASREFBUF_ADDR(n,unused)      TPASTE3(ADC,n,_FUSES_BIASREFBUF_ADDR),
+#  define _ADC_FUSES_BIASREFBUF_Pos(n,unused)       TPASTE3(ADC,n,_FUSES_BIASREFBUF_Pos),
+#  define _ADC_EXTCHANNEL_MSB(n,unused)             TPASTE3(ADC,n,_EXTCHANNEL_MSB),
+
+#  define ADC_GCLK_ID       MREPEAT(ADC_INST_NUM, _ADC_GCLK_ID, 0)
+#  define ADC_APBCMASKS     MREPEAT(ADC_INST_NUM, _ADC_APBCMASK, 0)
+
+#  define ADC_FUSES_BIASCOMP_ADDR     MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_ADDR, 0)
+#  define ADC_FUSES_BIASCOMP_Pos      MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_Pos, 0)
+#  define ADC_FUSES_BIASREFBUF_ADDR   MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_ADDR, 0)
+#  define ADC_FUSES_BIASREFBUF_Pos    MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_Pos, 0)
+#  define ADC_EXTCHANNEL_MSB          MREPEAT(ADC_INST_NUM, _ADC_EXTCHANNEL_MSB, 0)
+
+#endif
+
+/* List of ADC GCLK IDs */
+const uint8_t _adc_gclk_ids[ADC_INST_NUM] = { ADC_GCLK_ID };
+
+/* List of ADC APB Masks */
+#if (ADC_INST_NUM > 1) || (SAMC20)
+const uint32_t _adc_apbcmasks[ADC_INST_NUM] = { ADC_APBCMASKS };
+#endif
+
+/* List of Number of external channels of ADC modules. */
+const uint32_t _adc_extchannel_msb[ADC_INST_NUM] = { ADC_EXTCHANNEL_MSB };
+
+/* List of address of comparator scaling of ADC modules. */
+const uint32_t _adc_biascomp_addr[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_ADDR };
+
+/* List of address of bias reference buffer scaling of ADC modules. */
+const uint32_t _adc_biasrefbuf_addr[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_ADDR };
+
+/* List of offset of comparator scaling of ADC modules. */
+const uint8_t _adc_biascomp_pos[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_Pos };
+
+/* List of offset of bias reference buffer scaling of ADC modules. */
+const uint8_t _adc_biasrefbuf_pos[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_Pos };
+
+
+/**
+ * \internal Find the index of given ADC module instance.
+ *
+ * \param[in] ADC module instance pointer.
+ *
+ * \return Index of the given ADC module instance.
+ */
+uint8_t _adc_get_inst_index(
+		Adc *const hw)
+{
+	/* List of available ADC modules. */
+	Adc *const adc_modules[ADC_INST_NUM] = ADC_INSTS;
+
+	/* Find index for ADC instance. */
+	for (uint32_t i = 0; i < ADC_INST_NUM; i++) {
+		if (hw == adc_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given. */
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Initializes an ADC configuration structure to defaults.
+ *
+ * Initializes a given ADC configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li GCLK generator 0 (GCLK main) clock source
+ *  \li Internal bandgap reference
+ *  \li Div 2 clock prescaler
+ *  \li 12-bit resolution
+ *  \li Window monitor disabled
+ *  \li Positive input on ADC PIN 1
+ *  \li Negative input on Internal ground
+ *  \li Averaging disabled
+ *  \li Oversampling disabled
+ *  \li Right adjust data
+ *  \li Single-ended mode
+ *  \li Free running disabled
+ *  \li All events (input and generation) disabled
+ *  \li ADC run in standby disabled
+ *  \li ADC On demand disabled
+ *  \li No sampling time compensation
+ *  \li Disable the positive input sequense
+ *  \li No reference compensation
+ *  \li No gain/offset correction
+ *  \li No added sampling time
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+void adc_get_config_defaults(struct adc_config *const config)
+{
+	Assert(config);
+	config->clock_source                  = GCLK_GENERATOR_0;
+	config->reference                     = ADC_REFERENCE_INTREF;
+	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV2;
+	config->resolution                    = ADC_RESOLUTION_12BIT;
+	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
+	config->window.window_upper_value     = 0;
+	config->window.window_lower_value     = 0;
+#if SAMR30
+	config->positive_input                = ADC_POSITIVE_INPUT_PIN6;
+#else
+	config->positive_input                = ADC_POSITIVE_INPUT_PIN1;
+#endif
+	config->negative_input                = ADC_NEGATIVE_INPUT_GND;
+	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
+	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
+	config->left_adjust                   = false;
+	config->differential_mode             = false;
+	config->freerunning                   = false;
+	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
+	config->run_in_standby                = false;
+	config->on_demand                     = false;
+	config->sampling_time_compensation_enable  = false;
+	config->positive_input_sequence_mask_enable = 0;
+	config->reference_compensation_enable = false;
+	config->correction.correction_enable  = false;
+	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
+	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
+	config->sample_length                 = 0;
+}
+
+/**
+ * \brief Sets the ADC window mode.
+ *
+ * Sets the ADC window mode to a given mode and value range.
+ *
+ * \param[in] module_inst         Pointer to the ADC software instance struct
+ * \param[in] window_mode         Window monitor mode to set
+ * \param[in] window_lower_value  Lower window monitor threshold value
+ * \param[in] window_upper_value  Upper window monitor threshold value
+  */
+void adc_set_window_mode(
+		struct adc_module *const module_inst,
+		const enum adc_window_mode window_mode,
+		const int16_t window_lower_value,
+		const int16_t window_upper_value)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set window mode */
+	adc_module->CTRLC.reg = window_mode;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set lower window monitor threshold value */
+	adc_module->WINLT.reg = window_lower_value;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set upper window monitor threshold value */
+	adc_module->WINUT.reg = window_upper_value;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+* \internal Configure MUX settings for the analog pins.
+*
+* This function will set the given ADC input pins
+* to the analog function in the pin mux, giving
+* the ADC access to the analog signal.
+*
+* \param [in] index   Index of the ADC module instance.
+* \param [in] pin     AINxx pin to configure
+*/
+static inline void _adc_configure_ain_pin(uint8_t index, uint32_t pin)
+{
+#define PIN_INVALID_ADC_AIN    0xFFFFUL
+
+	/* Pinmapping table for AINxx -> GPIO pin number */
+#if (SAML21) || (SAML22) || (SAMR30)
+	const uint32_t pinmapping[] = {
+#if (SAML21E) || (SAMR30E)
+#if !(SAMR30)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+#endif
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML21G) || (SAMR30G)
+#if !(SAMR30)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+#endif
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML21J)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML22G)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML22J)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML22N)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_PC00B_ADC_AIN16, PIN_PC01B_ADC_AIN17,
+			PIN_PC02B_ADC_AIN18, PIN_PC03B_ADC_AIN19,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#   else
+#       error ADC pin mappings are not defined for this device.
+#   endif
+	};
+#elif (SAMC20)
+	const uint32_t pinmapping[] = {
+#   if (SAMC20E)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   elif (SAMC20G)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   elif (SAMC20J)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   else
+#       error ADC pin mappings are not defined for this device.
+#   endif
+	};
+#elif (SAMC21)
+	const uint32_t *pinmapping = NULL;;
+	const uint32_t pinmapping0[] = {
+#   if (SAMC21E)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   elif (SAMC21G)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   elif (SAMC21J)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   else
+#       error ADC pin mappings are not defined for this device.
+#   endif
+		};
+	const uint32_t pinmapping1[] = {
+#   if (SAMC21E)
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+#   elif (SAMC21G)
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_PB02B_ADC1_AIN2,  PIN_PB03B_ADC1_AIN3,
+		PIN_PB08B_ADC1_AIN4,  PIN_PB09B_ADC1_AIN5,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+#   elif (SAMC21J)
+		PIN_PB00B_ADC1_AIN0,  PIN_PB01B_ADC1_AIN1,
+		PIN_PB02B_ADC1_AIN2,  PIN_PB03B_ADC1_AIN3,
+		PIN_PB08B_ADC1_AIN4,  PIN_PB09B_ADC1_AIN5,
+		PIN_PB04B_ADC1_AIN6,  PIN_PB05B_ADC1_AIN7,
+		PIN_PB06B_ADC1_AIN8,  PIN_PB07B_ADC1_AIN9,
+		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+#   else
+#       error ADC pin mappings are not defined for this device.
+#   endif
+	};
+
+	switch(index) {
+	case 0:
+		pinmapping = pinmapping0;
+		break;
+	case 1:
+		pinmapping = pinmapping1;
+		break;
+	default:
+		break;
+	}
+	Assert(pinmapping);
+#endif
+
+	uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
+
+	if (pin <= _adc_extchannel_msb[index]) {
+		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+
+		Assert(pin_map_result != PIN_INVALID_ADC_AIN);
+
+		struct system_pinmux_config config;
+		system_pinmux_get_config_defaults(&config);
+
+		/* Analog functions are all on MUX setting B */
+		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+		config.mux_position = 1;
+
+		system_pinmux_pin_set_config(pin_map_result, &config);
+	}
+}
+
+/**
+ * \internal Writes an ADC configuration to the hardware module.
+ *
+ * Writes out a given ADC module configuration to the hardware module.
+ *
+ * \param[in]  index        Index of the ADC module instance
+ * \param[out] module_inst  Pointer to the ADC software instance struct
+ * \param[in]  config       Pointer to configuration struct
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               The configuration was successful
+ * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
+ */
+static enum status_code _adc_set_config(
+		uint8_t index,
+		struct adc_module *const module_inst,
+		struct adc_config *const config)
+{
+	uint8_t adjres = 0;
+	uint32_t resolution = ADC_RESOLUTION_16BIT;
+	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+
+	/* Get the hardware module pointer */
+	Adc *const adc_module = module_inst->hw;
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(_adc_gclk_ids[index], &gclk_chan_conf);
+	system_gclk_chan_enable(_adc_gclk_ids[index]);
+
+	/* Setup pinmuxing for analog inputs */
+	_adc_configure_ain_pin(index, config->positive_input);
+	_adc_configure_ain_pin(index, config->negative_input);
+
+	/* Set pinmux for positive input sequence*/
+	for(uint8_t i=0;i <= _adc_extchannel_msb[index];i++){
+		if(config->positive_input_sequence_mask_enable & (1 << i)){
+			_adc_configure_ain_pin(index, i);
+		}
+	}
+
+	/* Configure run in standby and on demand */
+	adc_module->CTRLA.reg = ((config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos)
+						    | (config->on_demand << ADC_CTRLA_ONDEMAND_Pos)) ;
+
+	/* Configure reference */
+	adc_module->REFCTRL.reg =
+			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos)
+			| (config->reference);
+
+	/* Set adjusting result and number of samples */
+	switch (config->resolution) {
+
+	case ADC_RESOLUTION_CUSTOM:
+		adjres = config->divide_result;
+		accumulate = config->accumulate_samples;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_13BIT:
+		/* Increase resolution by 1 bit */
+		adjres = ADC_DIVIDE_RESULT_2;
+		accumulate = ADC_ACCUMULATE_SAMPLES_4;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_14BIT:
+		/* Increase resolution by 2 bit */
+		adjres = ADC_DIVIDE_RESULT_4;
+		accumulate = ADC_ACCUMULATE_SAMPLES_16;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+	case ADC_RESOLUTION_15BIT:
+		/* Increase resolution by 3 bit */
+		adjres = ADC_DIVIDE_RESULT_2;
+		accumulate = ADC_ACCUMULATE_SAMPLES_64;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_16BIT:
+		/* Increase resolution by 4 bit */
+		adjres = ADC_DIVIDE_RESULT_DISABLE;
+		accumulate = ADC_ACCUMULATE_SAMPLES_256;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+	case ADC_RESOLUTION_8BIT:
+		/* 8-bit result register */
+		resolution = ADC_RESOLUTION_8BIT;
+		break;
+	case ADC_RESOLUTION_10BIT:
+		/* 10-bit result register */
+		resolution = ADC_RESOLUTION_10BIT;
+		break;
+	case ADC_RESOLUTION_12BIT:
+		/* 12-bit result register */
+		resolution = ADC_RESOLUTION_12BIT;
+		break;
+
+	default:
+		/* Unknown. Abort. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Check validity of sample length value */
+	if (config->sample_length > 63) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		/* Configure sample length */
+		adc_module->SAMPCTRL.reg =
+				(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos)
+				| (config->sampling_time_compensation_enable << ADC_SAMPCTRL_OFFCOMP_Pos);
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure CTRLB */
+	adc_module->CTRLB.reg =
+			config->clock_prescaler;
+	adc_module->CTRLC.reg =
+			resolution |
+			(config->correction.correction_enable << ADC_CTRLC_CORREN_Pos) |
+			(config->freerunning << ADC_CTRLC_FREERUN_Pos) |
+			(config->left_adjust << ADC_CTRLC_LEFTADJ_Pos) |
+			(config->differential_mode << ADC_CTRLC_DIFFMODE_Pos);
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Check validity of window thresholds */
+	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
+		switch (resolution) {
+		case ADC_RESOLUTION_8BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 127 ||
+					config->window.window_lower_value < -128 ||
+					config->window.window_upper_value > 127 ||
+					config->window.window_upper_value < -128)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 255 ||
+					config->window.window_upper_value > 255){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_10BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 511 ||
+					config->window.window_lower_value < -512 ||
+					config->window.window_upper_value > 511 ||
+					config->window.window_upper_value < -512)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 1023 ||
+					config->window.window_upper_value > 1023){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_12BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 2047 ||
+					config->window.window_lower_value < -2048 ||
+					config->window.window_upper_value > 2047 ||
+					config->window.window_upper_value < -2048)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 4095 ||
+					config->window.window_upper_value > 4095){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_16BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 32767 ||
+					config->window.window_lower_value < -32768 ||
+					config->window.window_upper_value > 32767 ||
+					config->window.window_upper_value < -32768)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 65535 ||
+					config->window.window_upper_value > 65535){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		}
+	}
+
+	/* Configure window mode */
+	adc_module->CTRLC.reg |= config->window.window_mode;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	adc_module->WINLT.reg =
+			config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	adc_module->WINUT.reg = config->window.window_upper_value <<
+			ADC_WINUT_WINUT_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure pin scan mode and positive and negative input pins */
+	adc_module->INPUTCTRL.reg =
+			config->negative_input |
+			config->positive_input;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure events */
+	adc_module->EVCTRL.reg = config->event_action;
+
+	/* Disable all interrupts */
+	adc_module->INTENCLR.reg =
+			(1 << ADC_INTENCLR_WINMON_Pos) |(1 << ADC_INTENCLR_OVERRUN_Pos)
+			| (1 << ADC_INTENCLR_RESRDY_Pos);
+
+	if (config->correction.correction_enable){
+		/* Make sure gain_correction value is valid */
+		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
+			return STATUS_ERR_INVALID_ARG;
+		} else {
+			/* Set gain correction value */
+			adc_module->GAINCORR.reg = config->correction.gain_correction <<
+					ADC_GAINCORR_GAINCORR_Pos;
+		}
+
+		while (adc_is_syncing(module_inst)) {
+			/* Wait for synchronization */
+		}
+
+		/* Make sure offset correction value is valid */
+		if (config->correction.offset_correction > 2047 ||
+				config->correction.offset_correction < -2048) {
+			return STATUS_ERR_INVALID_ARG;
+		} else {
+			/* Set offset correction value */
+			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+					ADC_OFFSETCORR_OFFSETCORR_Pos;
+		}
+
+		while (adc_is_syncing(module_inst)) {
+			/* Wait for synchronization */
+		}
+	}
+
+	/* Load in the fixed device ADC calibration constants */
+	adc_module->CALIB.reg =
+			ADC_CALIB_BIASREFBUF(
+				(*(uint32_t *)_adc_biasrefbuf_addr[index] >> _adc_biasrefbuf_pos[index])
+			) |
+			ADC_CALIB_BIASCOMP(
+				(*(uint32_t *)_adc_biascomp_addr[index] >> _adc_biascomp_pos[index])
+			);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the ADC.
+ *
+ * Initializes the ADC device struct and the hardware module based on the
+ * given configuration struct values.
+ *
+ * \param[out] module_inst Pointer to the ADC software instance struct
+ * \param[in]  hw          Pointer to the ADC module instance
+ * \param[in]  config      Pointer to the configuration struct
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK                The initialization was successful
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) were provided
+ * \retval STATUS_BUSY          The module is busy with a reset operation
+ * \retval STATUS_ERR_DENIED        The module is enabled
+ */
+enum status_code adc_init(
+		struct adc_module *const module_inst,
+		Adc *hw,
+		struct adc_config *config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Temporary variable to hold ADC instance number */
+	uint8_t instance = _adc_get_inst_index(hw);
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+#if (SAML22)
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_ADC);
+#elif (SAML21) || (SAMR30)
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_ADC);
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, _adc_apbcmasks[instance]);
+#endif
+
+	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Store the selected reference for later use */
+	module_inst->reference = config->reference;
+
+	/* Make sure the voltage reference is enabled if requested by the config */
+	if (module_inst->reference == ADC_REFERENCE_INTREF) {
+		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
+	}
+
+#if ADC_CALLBACK_MODE == true
+	for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
+		module_inst->callback[i] = NULL;
+	};
+
+	module_inst->registered_callback_mask = 0;
+	module_inst->enabled_callback_mask = 0;
+	module_inst->remaining_conversions = 0;
+	module_inst->job_status = STATUS_OK;
+
+	_adc_instances[instance] = module_inst;
+
+	if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
+			!config->freerunning) {
+		module_inst->software_trigger = true;
+	} else {
+		module_inst->software_trigger = false;
+	}
+#endif
+
+	/* Write configuration to module */
+	return _adc_set_config(instance, module_inst, config);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_callback.c
new file mode 100644
index 0000000000..555956b06b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_callback.c
@@ -0,0 +1,261 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "adc_callback.h"
+
+struct adc_module *_adc_instances[ADC_INST_NUM];
+
+static void _adc_interrupt_handler(const uint8_t instance)
+{
+	struct adc_module *module = _adc_instances[instance];
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->INTFLAG.reg;
+
+	if (flags & ADC_INTFLAG_RESRDY) {
+		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)) &&
+				(module->registered_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER))) {
+			/* clear interrupt flag */
+			module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+
+			/* store ADC result in job buffer */
+			*(module->job_buffer++) = module->hw->RESULT.reg;
+
+			if (--module->remaining_conversions > 0) {
+				if (module->software_trigger == true
+					&& (!(module->hw->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY))) {
+					adc_start_conversion(module);
+				}
+			} else {
+				if (module->job_status == STATUS_BUSY) {
+					/* job is complete. update status,disable interrupt
+					 *and call callback */
+					module->job_status = STATUS_OK;
+					adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY);
+					(module->callback[ADC_CALLBACK_READ_BUFFER])(module);
+				}
+			}
+		}
+	}
+
+	if (flags & ADC_INTFLAG_WINMON) {
+		module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON;
+		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) &&
+				(module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW))) {
+			(module->callback[ADC_CALLBACK_WINDOW])(module);
+		}
+
+	}
+
+	if (flags & ADC_INTFLAG_OVERRUN) {
+		module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) &&
+				(module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR))) {
+			(module->callback[ADC_CALLBACK_ERROR])(module);
+		}
+	}
+}
+
+/** Interrupt handler for the ADC module. */
+#if (ADC_INST_NUM > 1) || (SAMC20)
+#   define _ADC_INTERRUPT_HANDLER(n, m) \
+		void ADC##n##_Handler(void) \
+		{ \
+			_adc_interrupt_handler(n); \
+		}
+
+	MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_HANDLER, 0)
+#else
+void ADC_Handler(void)
+{
+	_adc_interrupt_handler(0);
+}
+#endif
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled for the interrupt handler to call it
+ * when the condition for the callback is met.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] callback_func  Pointer to callback function
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void adc_register_callback(
+		struct adc_module *const module,
+		adc_callback_t callback_func,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->registered_callback_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void adc_unregister_callback(
+		struct adc_module *const module,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->registered_callback_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Read multiple samples from ADC.
+ *
+ * Read \c samples from the ADC into the \c buffer.
+ * If there is no hardware trigger defined (event action) the
+ * driver will retrigger the ADC conversion whenever a conversion
+ * is complete until \c samples has been acquired. To avoid
+ * jitter in the sampling frequency using an event trigger is advised.
+ *
+ * \param[in]  module_inst  Pointer to the ADC software instance struct
+ * \param[in]  samples      Number of samples to acquire
+ * \param[out] buffer       Buffer to store the ADC samples
+ *
+ * \return Status of the job start.
+ * \retval STATUS_OK        The conversion job was started successfully and is
+ *                          in progress
+ * \retval STATUS_BUSY      The ADC is already busy with another job
+ */
+enum status_code adc_read_buffer_job(
+		struct adc_module *const module_inst,
+		uint16_t *buffer,
+		uint16_t samples)
+{
+	Assert(module_inst);
+	Assert(samples);
+	Assert(buffer);
+
+	if(module_inst->remaining_conversions != 0 ||
+			module_inst->job_status == STATUS_BUSY){
+		return STATUS_BUSY;
+	}
+
+	module_inst->job_status = STATUS_BUSY;
+	module_inst->remaining_conversions = samples;
+	module_inst->job_buffer = buffer;
+
+	adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+
+	if(module_inst->software_trigger == true) {
+		adc_start_conversion(module_inst);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Gets the status of a job.
+ *
+ * Gets the status of an ongoing or the last job.
+ *
+ * \param [in]  module_inst Pointer to the ADC software instance struct
+ * \param [in]  type        Type of to get status
+ *
+ * \return Status of the job.
+ */
+enum status_code adc_get_job_status(
+		struct adc_module *module_inst,
+		enum adc_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == ADC_JOB_READ_BUFFER ) {
+		return module_inst->job_status;
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Aborts an ongoing job.
+ *
+ * Aborts an ongoing job.
+ *
+ * \param [in]  module_inst Pointer to the ADC software instance struct
+ * \param [in]  type        Type of job to abort
+ */
+void adc_abort_job(
+		struct adc_module *module_inst,
+		enum adc_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == ADC_JOB_READ_BUFFER) {
+		/* Disable interrupt */
+		adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+		/* Mark job as aborted */
+		module_inst->job_status = STATUS_ABORTED;
+		module_inst->remaining_conversions = 0;
+	}
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_feature.h
new file mode 100644
index 0000000000..0274cd7c92
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_feature.h
@@ -0,0 +1,737 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC functionality
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef ADC_FEATURE_H_INCLUDED
+#define ADC_FEATURE_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_adc_group
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*@{*/
+#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
+/** Output Driver Strength Selection feature support. */
+#  define FEATURE_ADC_SUPPORT_MASTER_SLAVE
+#endif
+/*@}*/
+
+#if ADC_CALLBACK_MODE == true
+#  include <system_interrupt.h>
+
+#if !defined(__DOXYGEN__)
+extern struct adc_module *_adc_instances[ADC_INST_NUM];
+#endif
+
+/** Forward definition of the device instance. */
+struct adc_module;
+
+/** Type of the callback functions. */
+typedef void (*adc_callback_t)(struct adc_module *const module);
+
+/**
+ * \brief ADC callback enum.
+ *
+ * Callback types for ADC callback driver.
+ *
+ */
+enum adc_callback {
+	/** Callback for buffer received */
+	ADC_CALLBACK_READ_BUFFER,
+	/** Callback when window is hit */
+	ADC_CALLBACK_WINDOW,
+	/** Callback for error */
+	ADC_CALLBACK_ERROR,
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	ADC_CALLBACK_N,
+#  endif
+};
+
+#endif
+
+/**
+ * \brief ADC reference voltage enum.
+ *
+ * Enum for the possible reference voltages for the ADC.
+ *
+ */
+enum adc_reference {
+	/** Internal Bandgap Reference */
+	ADC_REFERENCE_INTREF  = ADC_REFCTRL_REFSEL_INTREF,
+	/** 1/1.48V<SUB>CC</SUB> reference */
+	ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
+	/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
+	ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
+	/** External reference A */
+	ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
+#if (SAML21) || (SAMR30)
+	/** External reference B */
+	ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
+#endif
+#if (SAMC20) || (SAMC21)
+	/** DAC */
+	ADC_REFERENCE_DAC     = ADC_REFCTRL_REFSEL_DAC,
+#endif
+	/** VDDANA */
+	ADC_REFERENCE_INTVCC2 = ADC_REFCTRL_REFSEL_INTVCC2,
+};
+
+/**
+ * \brief ADC clock prescaler enum.
+ *
+ * Enum for the possible clock prescaler values for the ADC.
+ *
+ */
+enum adc_clock_prescaler {
+	/** ADC clock division factor 2 */
+	ADC_CLOCK_PRESCALER_DIV2   = ADC_CTRLB_PRESCALER_DIV2,
+	/** ADC clock division factor 4 */
+	ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
+	/** ADC clock division factor 8 */
+	ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
+	/** ADC clock division factor 16 */
+	ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
+	/** ADC clock division factor 32 */
+	ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
+	/** ADC clock division factor 64 */
+	ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
+	/** ADC clock division factor 128 */
+	ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
+	/** ADC clock division factor 256 */
+	ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
+};
+
+/**
+ * \brief ADC resolution enum.
+ *
+ * Enum for the possible resolution values for the ADC.
+ *
+ */
+enum adc_resolution {
+	/** ADC 12-bit resolution */
+	ADC_RESOLUTION_12BIT = ADC_CTRLC_RESSEL_12BIT,
+	/** ADC 16-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_16BIT = ADC_CTRLC_RESSEL_16BIT,
+	/** ADC 10-bit resolution */
+	ADC_RESOLUTION_10BIT = ADC_CTRLC_RESSEL_10BIT,
+	/** ADC 8-bit resolution */
+	ADC_RESOLUTION_8BIT  = ADC_CTRLC_RESSEL_8BIT,
+	/** ADC 13-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_13BIT,
+	/** ADC 14-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_14BIT,
+	/** ADC 15-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_15BIT,
+	/** ADC 16-bit result register for use with averaging. When using this mode
+	  * the ADC result register will be set to 16-bit wide, and the number of
+	  * samples to accumulate and the division factor is configured by the
+	  * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
+	  * members in the configuration struct.
+	  */
+	ADC_RESOLUTION_CUSTOM,
+};
+
+/**
+ * \brief ADC window monitor mode enum.
+ *
+ * Enum for the possible window monitor modes for the ADC.
+ *
+ */
+enum adc_window_mode {
+	/** No window mode */
+	ADC_WINDOW_MODE_DISABLE          = ADC_CTRLC_WINMODE_DISABLE,
+	/** RESULT > WINLT */
+	ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_CTRLC_WINMODE_MODE1,
+	/** RESULT < WINUT */
+	ADC_WINDOW_MODE_BELOW_UPPER      = ADC_CTRLC_WINMODE_MODE2,
+	/** WINLT < RESULT < WINUT */
+	ADC_WINDOW_MODE_BETWEEN          = ADC_CTRLC_WINMODE_MODE3,
+	/** !(WINLT < RESULT < WINUT) */
+	ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_CTRLC_WINMODE_MODE4,
+};
+
+/**
+ * \brief ADC event action enum.
+ *
+ * Enum for the possible actions to take on an incoming event.
+ *
+ */
+enum adc_event_action {
+	/** Event action disabled */
+	ADC_EVENT_ACTION_DISABLED         = 0,
+	/** Flush ADC and start conversion */
+	ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_FLUSHEI,
+	/** Start conversion */
+	ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
+};
+
+/**
+ * \brief ADC positive MUX input selection enum.
+ *
+ * Enum for the possible positive MUX input selections for the ADC.
+ *
+ */
+enum adc_positive_input {
+	/** ADC0 pin */
+	ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_AIN0,
+	/** ADC1 pin */
+	ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_AIN1,
+	/** ADC2 pin */
+	ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_AIN2,
+	/** ADC3 pin */
+	ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_AIN3,
+	/** ADC4 pin */
+	ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_AIN4,
+	/** ADC5 pin */
+	ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_AIN5,
+	/** ADC6 pin */
+	ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_AIN6,
+	/** ADC7 pin */
+	ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_AIN7,
+	/** ADC8 pin */
+	ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_AIN8,
+	/** ADC9 pin */
+	ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_AIN9,
+	/** ADC10 pin */
+	ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_AIN10,
+	/** ADC11 pin */
+	ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_AIN11,
+#if !(SAMC20) && !(SAMC21)
+	/** ADC12 pin */
+	ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_AIN12,
+	/** ADC13 pin */
+	ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_AIN13,
+	/** ADC14 pin */
+	ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_AIN14,
+	/** ADC15 pin */
+	ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_AIN15,
+	/** ADC16 pin */
+	ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_AIN16,
+	/** ADC17 pin */
+	ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_AIN17,
+	/** ADC18 pin */
+	ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_AIN18,
+	/** ADC19 pin */
+	ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_AIN19,
+#if !(SAML22 || SAMR30)
+	/** ADC20 pin. */
+	ADC_POSITIVE_INPUT_PIN20         = ADC_INPUTCTRL_MUXPOS_AIN20,
+	/** ADC21 pin */
+	ADC_POSITIVE_INPUT_PIN21         = ADC_INPUTCTRL_MUXPOS_AIN21,
+	/** ADC22 pin */
+	ADC_POSITIVE_INPUT_PIN22         = ADC_INPUTCTRL_MUXPOS_AIN22,
+	/** ADC23 pin */
+	ADC_POSITIVE_INPUT_PIN23         = ADC_INPUTCTRL_MUXPOS_AIN23,
+#endif
+	/** Temperature reference. */
+	ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
+#endif
+	/** Bandgap voltage */
+	ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
+	/** 1/4 scaled core supply */
+	ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
+	/** 1/4 scaled I/O supply */
+	ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
+#if !(SAML22|| SAMR30)
+	/** DAC input */
+	ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
+#endif
+
+#if (SAML21)
+	/** SCALEDVBAT */
+	ADC_POSITIVE_INPUT_SCALEDVBAT    = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
+	/** OPAMP01 */
+	ADC_POSITIVE_INPUT_OPAMP01       = ADC_INPUTCTRL_MUXPOS_OPAMP01,
+	/** OPAMP02 */
+	ADC_POSITIVE_INPUT_OPAMP2        = ADC_INPUTCTRL_MUXPOS_OPAMP2,
+#endif
+#if (SAML22)
+	/** SCALEDVBAT */
+	ADC_POSITIVE_INPUT_SCALEDVBAT    = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
+	/** CTAT. */
+	ADC_POSITIVE_INPUT_CTAT          = ADC_INPUTCTRL_MUXPOS_CTAT,
+#endif
+};
+
+/**
+ * \brief ADC negative MUX input selection enum.
+ *
+ * Enum for the possible negative MUX input selections for the ADC.
+ *
+ */
+enum adc_negative_input {
+	/** ADC0 pin */
+	ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_AIN0,
+	/** ADC1 pin */
+	ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_AIN1,
+	/** ADC2 pin */
+	ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_AIN2,
+	/** ADC3 pin */
+	ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_AIN3,
+	/** ADC4 pin */
+	ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_AIN4,
+	/** ADC5 pin */
+	ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_AIN5,
+#if !(SAMC20) && !(SAMC21) && !(SAMR30)
+	/** ADC6 pin */
+	ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_AIN6,
+	/** ADC7 pin */
+	ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_AIN7,
+#endif
+	/** Internal ground */
+	ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG(0x18u),
+};
+
+/**
+ * \brief ADC number of accumulated samples enum.
+ *
+ * Enum for the possible numbers of ADC samples to accumulate.
+ * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
+ * resolution setting is used.
+ *
+ */
+enum adc_accumulate_samples {
+	/** No averaging */
+	ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
+	/** Average 2 samples */
+	ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
+	/** Average 4 samples */
+	ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
+	/** Average 8 samples */
+	ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
+	/** Average 16 samples */
+	ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
+	/** Average 32 samples */
+	ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
+	/** Average 64 samples */
+	ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
+	/** Average 128 samples */
+	ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
+	/** Average 256 samples */
+	ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
+	/** Average 512 samples */
+	ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
+	/** Average 1024 samples */
+	ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
+};
+
+/**
+ * \brief ADC possible dividers for the result register.
+ *
+ * Enum for the possible division factors to use when accumulating
+ * multiple samples. To keep the same resolution for the averaged
+ * result and the actual input value, the division factor must
+ * be equal to the number of samples accumulated. This setting is only
+ * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
+ */
+enum adc_divide_result {
+	/** Don't divide result register after accumulation */
+	ADC_DIVIDE_RESULT_DISABLE = 0,
+	/** Divide result register by 2 after accumulation */
+	ADC_DIVIDE_RESULT_2       = 1,
+	/** Divide result register by 4 after accumulation */
+	ADC_DIVIDE_RESULT_4       = 2,
+	/** Divide result register by 8 after accumulation */
+	ADC_DIVIDE_RESULT_8       = 3,
+	/** Divide result register by 16 after accumulation */
+	ADC_DIVIDE_RESULT_16      = 4,
+	/** Divide result register by 32 after accumulation */
+	ADC_DIVIDE_RESULT_32      = 5,
+	/** Divide result register by 64 after accumulation */
+	ADC_DIVIDE_RESULT_64      = 6,
+	/** Divide result register by 128 after accumulation */
+	ADC_DIVIDE_RESULT_128     = 7,
+};
+
+#if ADC_CALLBACK_MODE == true
+/**
+ * Enum for the possible ADC interrupt flags.
+ */
+enum adc_interrupt_flag {
+	/** ADC result ready */
+	ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
+	/** Window monitor match */
+	ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
+	/** ADC result overwritten before read */
+	ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
+};
+#endif
+
+/**
+ * \brief ADC oversampling and decimation enum.
+ *
+ * Enum for the possible numbers of bits resolution can be increased by when
+ * using oversampling and decimation.
+ *
+ */
+enum adc_oversampling_and_decimation {
+	/** Don't use oversampling and decimation mode */
+	ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
+	/** 1-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
+	/** 2-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
+	/** 3-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
+	/** 4-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_4BIT
+};
+
+#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE
+/**
+ * Enum for the trigger selection in dual mode.
+ */
+enum adc_dual_mode_trigger_selection {
+	/** Start event or software trigger will start a conversion on both ADCs */
+	ADC_DUAL_MODE_BOTH         = ADC_CTRLC_DUALSEL_BOTH,
+	/** START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
+	ADC_DUAL_MODE_INTERLEAVE   = ADC_CTRLC_DUALSEL_INTERLEAVE,
+};
+#endif
+
+/**
+ * \brief Window monitor configuration structure.
+ *
+ * Window monitor configuration structure.
+ */
+struct adc_window_config {
+	/** Selected window mode */
+	enum adc_window_mode window_mode;
+	/** Lower window value */
+	int32_t window_lower_value;
+	/** Upper window value */
+	int32_t window_upper_value;
+};
+
+/**
+ * \brief ADC event enable/disable structure.
+ *
+ * Event flags for the ADC module. This is used to enable and
+ * disable events via \ref adc_enable_events() and \ref adc_disable_events().
+ */
+struct adc_events {
+	/** Enable event generation on conversion done */
+	bool generate_event_on_conversion_done;
+	/** Enable event generation on window monitor */
+	bool generate_event_on_window_monitor;
+};
+
+/**
+ * \brief Gain and offset correction configuration structure.
+ *
+ * Gain and offset correction configuration structure.
+ * Part of the \ref adc_config struct and will  be initialized by
+ * \ref adc_get_config_defaults.
+ */
+struct adc_correction_config {
+	/**
+	 * Enables correction for gain and offset based on values of gain_correction and
+	 * offset_correction if set to true
+	 */
+	bool correction_enable;
+	/**
+	 * This value defines how the ADC conversion result is compensated for gain
+	 * error before written to the result register. This is a fractional value,
+	 * 1-bit integer plus an 11-bit fraction, therefore
+	 * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
+	 * \c 0b010000000000 to \c 0b111111111111.
+	 */
+	uint16_t gain_correction;
+	/**
+	 * This value defines how the ADC conversion result is compensated for
+	 * offset error before written to the result register. This is a 12-bit
+	 * value in two's complement format.
+	 */
+	int16_t offset_correction;
+};
+
+/**
+ * \brief ADC configuration structure.
+ *
+ * Configuration structure for an ADC instance. This structure should be
+ * initialized by the \ref adc_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct adc_config {
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+	/** Voltage reference */
+	enum adc_reference reference;
+	/** Clock prescaler */
+	enum adc_clock_prescaler clock_prescaler;
+	/** Result resolution */
+	enum adc_resolution resolution;
+	/** Positive MUX input */
+	enum adc_positive_input positive_input;
+	/** Negative MUX input */
+	enum adc_negative_input negative_input;
+	/** Number of ADC samples to accumulate when using the
+	 *  \c ADC_RESOLUTION_CUSTOM mode
+	 */
+	enum adc_accumulate_samples accumulate_samples;
+	/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
+	enum adc_divide_result divide_result;
+	/** Left adjusted result */
+	bool left_adjust;
+	/** Enables differential mode if true */
+	bool differential_mode;
+	/** Enables free running mode if true */
+	bool freerunning;
+	/** ADC run in standby control */
+	bool run_in_standby;
+	/** ADC On demand control */
+	bool on_demand;
+	/**
+	 * Enables sampling period offset compensation if true
+	 */
+	bool sampling_time_compensation_enable;
+	/**
+	 * Positive input enabled mask for conversion sequence.
+	 * The sequence start from the lowest input, and go to the next enabled input
+	 * automatically when the conversion is done. If no bits are set the
+	 * sequence is disabled.
+	 */
+	uint32_t positive_input_sequence_mask_enable;
+	/**
+	 * Enables reference buffer offset compensation if true.
+	 * This will increase the accuracy of the gain stage, but decreases the input
+	 * impedance; therefore the startup time of the reference must be increased.
+	 */
+	bool reference_compensation_enable;
+	/**
+	 * This value (0-63) control the ADC sampling time in number of half ADC
+	 * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
+	 * controlling the ADC input impedance. Sampling time is set according to
+	 * the formula:
+	 * Sample time = (sample_length+1) * (ADCclk / 2).
+	 */
+	uint8_t sample_length;
+	/** Window monitor configuration structure */
+	struct adc_window_config window;
+	/** Gain and offset correction configuration structure */
+	struct adc_correction_config correction;
+	/** Event action to take on incoming event */
+	enum adc_event_action event_action;
+};
+
+/**
+ * \brief ADC software device instance structure.
+ *
+ * ADC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct adc_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to ADC hardware module */
+	Adc *hw;
+	/** Keep reference configuration so we know when enable is called */
+	enum adc_reference reference;
+#  if ADC_CALLBACK_MODE == true
+	/** Array to store callback functions */
+	adc_callback_t callback[ADC_CALLBACK_N];
+	/** Pointer to buffer used for ADC results */
+	volatile uint16_t *job_buffer;
+	/** Remaining number of conversions in current job */
+	volatile uint16_t remaining_conversions;
+	/** Bit mask for callbacks registered */
+	uint8_t registered_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t enabled_callback_mask;
+	/** Holds the status of the ongoing or last conversion job */
+	volatile enum status_code job_status;
+	/** If software triggering is needed */
+	bool software_trigger;
+#  endif
+#endif
+};
+
+#if !defined(__DOXYGEN__)
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static inline bool adc_is_syncing(
+	struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+
+	if (adc_module->SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+#endif
+
+/**
+ * \name  Positive Input Sequence
+ * @{
+ */
+
+/**
+ * \brief Enable positive input sequence mask for conversion.
+ *
+ * The sequence start from the lowest input, and go to the next enabled input
+ * automatically when the conversion is done. If no bits are set the
+ * sequence is disabled.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ * \param[in] eanble_seq_mask  Sequence mask
+ */
+static inline void adc_enable_positive_input_sequence(
+		struct adc_module *const module_inst,
+		uint32_t positive_input_sequence_mask_enable)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+	adc_module->SEQCTRL.reg = positive_input_sequence_mask_enable;
+}
+
+/**
+ * \brief Disable positive input in the sequence.
+ *
+ * Disable positive input in the sequence.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline void adc_disable_positive_input_sequence(
+		struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+	adc_module->SEQCTRL.reg = 0;
+}
+
+/**
+ * \brief Get ADC sequence status.
+ *
+ * Check if a sequence is done and get last conversion done in the sequence.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ * \param[out] is_sequence_busy  Sequence busy status
+ * \param[out] sequence_state This value identifies the last conversion
+ *             done in the sequence
+ */
+static inline void adc_get_sequence_status(
+		struct adc_module *const module_inst,
+		bool  * is_sequence_busy,
+		uint8_t *sequence_state)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	uint8_t temp = false;
+	Adc *const adc_module = module_inst->hw;
+	temp = adc_module->SEQSTATUS.reg;
+	if(temp & ADC_SEQSTATUS_SEQBUSY){
+		*is_sequence_busy = true;
+	}
+	*sequence_state = temp & ADC_SEQSTATUS_SEQSTATE_Msk;
+}
+
+/** @} */
+
+#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE
+/**
+ * \brief Set ADC master and slave mode.
+ *
+ * Enable ADC module Master-Slave Operation and select dual mode trigger.
+ *
+ * \param[in] master_inst  Pointer to the master ADC software instance struct
+ * \param[in] slave_inst   Pointer to the slave ADC software instance struct
+ * \param[in] dualsel      Dual mode trigger selection
+ *
+ */
+static inline void adc_set_master_slave_mode(
+		struct adc_module *const master_inst,
+		struct adc_module *const slave_inst,
+		enum adc_dual_mode_trigger_selection dualsel)
+{
+	/* Sanity check arguments */
+	Assert(master_inst);
+	Assert(slave_inst);
+
+	slave_inst->hw->CTRLA.reg |= ADC_CTRLA_SLAVEEN;
+	master_inst->hw->CTRLC.reg |= dualsel;
+
+};
+#endif
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_FEATURE_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.c
new file mode 100644
index 0000000000..078a6a73a1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.c
@@ -0,0 +1,329 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Advanced Encryption Standard driver.
+ *
+ * This file defines a useful set of functions for the AES on SAM devices.
+ *
+ * Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <aes.h>
+#include <system.h>
+
+/**
+ * \brief Initializes an AES configuration structure to defaults.
+ *
+ * Initializes the specified AES configuration structure to a set of
+ * known default values.
+ *
+ * \note This function should be called to initialize <b>all</b> new instances of
+ * AES configuration structures before they are further modified by the user
+ * application.
+ *
+ *  The default configuration is as follows:
+ *  - Data encryption
+ *  - 128-bit AES key size
+ *  - 128-bit cipher feedback size
+ *  - Manual start mode
+ *  - Electronic Codebook (ECB) mode
+ *  - All countermeasures are enabled
+ *  - XRO key is disabled
+ *  - Key generation is disabled
+ *  - Last output data mode is disabled
+ *
+ *  \param[out] config Pointer to an AES configuration structure
+ */
+void aes_get_config_defaults(
+		struct aes_config *const config)
+{
+
+	/* Sanity check arguments */
+	Assert(config);
+	config->encrypt_mode = AES_ENCRYPTION;
+	config->key_size = AES_KEY_SIZE_128;
+	config->start_mode = AES_MANUAL_START;
+	config->opmode= AES_ECB_MODE;
+	config->cfb_size = AES_CFB_SIZE_128;
+	config->ctype = AES_COUNTERMEASURE_TYPE_ALL;
+	config->enable_xor_key = false;
+	config->enable_key_gen = false;
+	config->lod = false;
+}
+
+/**
+ * \brief Initialize the AES module.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in] hw Module hardware register base address pointer
+ * \param[in] config  Pointer to an AES configuration structure
+ */
+void aes_init(
+		struct aes_module *const module,
+		Aes *const hw,
+		struct aes_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(hw);
+	Assert(config);
+	Assert(module);
+
+	/* Enable clock for AES */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_AES);
+
+	/* Perform a software reset */
+	hw->CTRLA.reg = AES_CTRLA_SWRST;
+
+	/* Initialize the AES with new configurations */
+	aes_set_config(module,hw, config);
+}
+
+/**
+ * \brief Enable the AES module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void aes_enable(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+	module->hw->CTRLA.reg |= AES_CTRLA_ENABLE;
+
+}
+
+/**
+ * \brief Disable the AES module.
+ * \param[in] module  Pointer to the software instance struct
+ */
+void aes_disable(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	/* Disbale interrupt */
+	module->hw->INTENCLR.reg = AES_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	module->hw->INTFLAG.reg = AES_INTFLAG_MASK;
+
+	module->hw->CTRLA.reg &= (~AES_CTRLA_ENABLE);
+}
+
+/**
+ * \brief Configure the AES module.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in] hw Module hardware register base address pointer
+ * \param[in] config  Pointer to an AES configuration structure
+ */
+void aes_set_config(
+		struct aes_module *const module,
+		Aes *const hw,
+		struct aes_config *const config)
+{
+	uint32_t ul_mode = 0;
+
+	/* Validate arguments. */
+	Assert(hw);
+	Assert(config);
+	Assert(module);
+
+	module->opmode = config->opmode;
+	module->hw = hw;
+	module->key_size = config->key_size;
+	module->cfb_size = config->cfb_size;
+
+	ul_mode |= (config->encrypt_mode << AES_CTRLA_CIPHER_Pos)
+			 | (config->start_mode << AES_CTRLA_STARTMODE_Pos)
+			 | (config->key_size << AES_CTRLA_KEYSIZE_Pos)
+			 | (config->opmode << AES_CTRLA_AESMODE_Pos)
+			 | (config->cfb_size << AES_CTRLA_CFBS_Pos)
+			 | (AES_CTRLA_CTYPE(config->ctype))
+			 | (config->enable_xor_key << AES_CTRLA_XORKEY_Pos)
+			 | (config->enable_key_gen << AES_CTRLA_KEYGEN_Pos)
+			 | (config->lod << AES_CTRLA_LOD_Pos);
+	if (hw->CTRLA.reg & AES_CTRLA_ENABLE) {
+		aes_disable(module);
+		hw->CTRLA.reg = ul_mode;
+		aes_enable(module);
+	} else {
+		hw->CTRLA.reg = ul_mode;
+	}
+}
+
+/**
+ * \brief Write the 128/192/256-bit cryptographic key.
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in]  key Pointer to 4/6/8 contiguous 32-bit words
+ *
+ * \note The key size depends on the current AES configuration.
+ */
+void aes_write_key(
+		struct aes_module *const module,
+		const uint32_t *key)
+{
+	uint32_t i, key_length = 0;
+
+	/* Validate arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(key);
+
+	switch (module->key_size) {
+	case AES_KEY_SIZE_128:
+		key_length = 4;
+		break;
+
+	case AES_KEY_SIZE_192:
+		key_length = 6;
+		break;
+
+	case AES_KEY_SIZE_256:
+		key_length = 8;
+		break;
+
+	default:
+		break;
+	}
+
+	for (i = 0; i < key_length; i++) {
+		module->hw->KEYWORD[i].reg = *key;
+		key++;
+	}
+}
+
+/**
+ * \brief Write the initialization vector (for the CBC, CFB, OFB, CTR, and GCM
+ * cipher modes).
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] vector Pointer to four contiguous 32-bit words
+ */
+void aes_write_init_vector(
+		struct aes_module *const module,
+		const uint32_t *vector)
+{
+	uint32_t i;
+
+	/* Validate arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(module->opmode != AES_ECB_MODE);
+
+	for (i = 0; i < 4; i++) {
+		module->hw->INTVECTV[i].reg = *vector;
+		vector++;
+	}
+}
+
+/**
+ * \brief Write the input data (four consecutive 32-bit words).
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] input_data_buffer Pointer to an input data buffer
+ */
+void aes_write_input_data(
+		struct aes_module *const module,
+		const uint32_t *input_data_buffer)
+{
+	uint32_t i;
+
+	/* Validate arguments. */
+	Assert(module);
+	Assert(module->hw);;
+	Assert(input_data_buffer);
+
+	module->hw->DATABUFPTR.reg = 0;
+	if (module->opmode == AES_CFB_MODE
+		&& module->cfb_size == AES_CFB_SIZE_64){
+		for (i = 0; i < 2; i++) {
+			module->hw->INDATA.reg = *input_data_buffer;
+			input_data_buffer++;
+		}
+	} else if (module->opmode == AES_CFB_MODE
+		&& (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16)){
+		module->hw->INDATA.reg = *input_data_buffer;
+	} else {
+		for (i = 0; i < 4; i++) {
+			module->hw->INDATA.reg = *input_data_buffer;
+			input_data_buffer++;
+		}
+	}
+}
+
+/**
+ * \brief Read the output data.
+ *
+ * \note The data buffer that holds the processed data must be large enough to hold
+ * four consecutive 32-bit words.
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] output_data_buffer Pointer to an output buffer
+ */
+void aes_read_output_data(
+		struct aes_module *const module,
+		uint32_t *output_data_buffer)
+{
+	uint32_t i;
+
+	/* Validate arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(output_data_buffer);
+
+	module->hw->DATABUFPTR.reg = 0;
+	if (module->opmode == AES_CFB_MODE
+		&& module->cfb_size == AES_CFB_SIZE_64){
+		for (i = 0; i < 2; i++) {
+			*output_data_buffer = module->hw->INDATA.reg;
+			output_data_buffer++;
+		}
+	} else if (module->opmode == AES_CFB_MODE
+		&& (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16)){
+		*output_data_buffer = module->hw->INDATA.reg;
+	} else {
+		for (i = 0; i < 4; i++) {
+			*output_data_buffer = module->hw->INDATA.reg;
+			output_data_buffer++;
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.h
new file mode 100644
index 0000000000..4d064018a4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.h
@@ -0,0 +1,715 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Advanced Encryption Standard driver.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef AES_H_INCLUDED
+#define AES_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_drivers_aes_group SAM Advanced Encryption Standard (AES) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Advanced Encryption Standard functionality. The following
+ * driver API modes are covered by this manual:
+ *
+ *  - Polled APIs
+ *  - Callback APIs
+ *
+ * The Advanced Encryption Standard module supports all five confidentiality
+ * modes of operation for symmetrical key block cipher algorithms (as specified
+ * in the NIST Special Publication 800-38A Recommendation):
+ * - Electronic Code Book (ECB)
+ * - Cipher Block Chaining (CBC)
+ * - Output Feedback (OFB)
+ * - Cipher Feedback (CFB)
+ * - Counter (CTR)
+ *
+ * The following peripheral is used by this module:
+ *  - AES (Advanced Encryption Standard)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L21
+ *  - Atmel | SMART SAM L22
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_drivers_aes_prerequisites
+ *  - \ref asfdoc_sam0_drivers_aes_module_overview
+ *  - \ref asfdoc_sam0_drivers_aes_special_considerations
+ *  - \ref asfdoc_sam0_drivers_aes_extra_info
+ *  - \ref asfdoc_sam0_drivers_aes_examples
+ *  - \ref asfdoc_sam0_drivers_aes_api_overview
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_module_overview Module Overview
+ *
+ * The Advanced Encryption Standard (AES) is a specification for the encryption of
+ * electronic data established by the U.S. National Institute of Standards and
+ * Technology (NIST) in 2001. It is compliant with the American FIPS
+ * (Federal Information Processing Standard) Publication 197 specification.
+ *
+ * The AES supports all five confidentiality modes of operation for symmetrical
+ * key block cipher algorithms (as specified in the NIST Special Publication
+ * 800-38A Recommendation):
+ * - Electronic Code Book (ECB)
+ * - Cipher Block Chaining (CBC)
+ * - Output Feedback (OFB)
+ * - Cipher Feedback (CFB)
+ * - Counter (CTR)
+ *
+ * Data transfers both to and from the AES module can occur using the peripheral
+ * DMA controller channels, thus minimizing processor intervention for
+ * large data buffer transfers.
+ *
+ * As soon as the initialization vector, the input data and the key are
+ * configured, the encryption/decryption process may be started. Once the
+ * process has completed the encrypted/decrypted data can be read out via
+ * registers or through DMA channels.
+ *
+ * \subsection asfdoc_sam0_drivers_aes_module_overview_en_de Encryption and Decryption
+ * The AES is capable of using cryptographic keys of 128/192/256 bits to
+ * encrypt and decrypt data in blocks of 128 bits. In Cipher Feedback Mode (CFB),
+ * five data sizes are possible (8, 16, 32, 64, or 128 bits).
+ *
+ * The input to the encryption processes of the CBC, CFB, and OFB modes includes,
+ * in addition to the plaintext, a 128-bit data block called the Initialization
+ * Vector (IV). The Initialization Vector is used in the initial step in the
+ * encryption of a message and in the corresponding decryption of the message.
+ *
+ * There are three encryption/decryption start modes:
+ * - Manual Mode: Start encryption/decryption manually
+ * - Auto Start Mode: Once the correct number of input data registers is written,
+ * processing is automatically started, DMA operation uses this mode
+ * - Last Output Data Mode (LOD): This mode is used to generate message
+ * authentication code (MAC) on data in CCM mode of operation
+ *
+ * \subsection asfdoc_sam0_drivers_aes_module_overview_hardware_countermeasures Hardware Countermeasures
+ * The AES module features four types of hardware countermeasures that are
+ * useful for protecting data against differential power analysis attacks:
+ * - Type 1: Randomly add one cycle to data processing
+ * - Type 2: Randomly add one cycle to data processing (other version)
+ * - Type 3: Add a random number of clock cycles to data processing, subject to
+ * a maximum of 11/13/15 clock cycles for key sizes of 128/192/256 bits
+ * - Type 4: Add random spurious power consumption during data processing
+ *
+ * \subsection asfdoc_sam0_drivers_aes_module_overview_gcm Galois Counter Mode (GCM)
+ * GCM is comprised of the AES engine in CTR mode along with a universal hash
+ * function (GHASH engine) that is defined over a binary Galois field to produce
+ * a message authentication tag. The GHASH engine processes data packets after the
+ * AES operation. GCM provides assurance of the confidentiality of data through the
+ * AES Counter mode of operation for DRAFT 920 encryption. Authenticity of the
+ * confidential data is assured through the GHASH engine. Refer to the NIST Special
+ * Publication 800-38D Recommendation for more complete information.
+ *
+ * \section asfdoc_sam0_drivers_aes_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_drivers_aes_extra. This includes:
+ *  - \ref asfdoc_sam0_drivers_aes_extra_acronyms
+ *  - \ref asfdoc_sam0_drivers_aes_extra_dependencies
+ *  - \ref asfdoc_sam0_drivers_aes_extra_errata
+ *  - \ref asfdoc_sam0_drivers_aes_extra_history
+ *
+ * \section asfdoc_sam0_drivers_aes_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_drivers_aes_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AES processing mode. */
+enum aes_encrypt_mode {
+	AES_DECRYPTION = 0,     /**< Decryption of data will be performed */
+	AES_ENCRYPTION,         /**< Encryption of data will be performed */
+};
+
+/** AES cryptographic key size. */
+enum aes_key_size {
+	AES_KEY_SIZE_128 = 0,   /**< AES key size is 128-bit */
+	AES_KEY_SIZE_192,       /**< AES key size is 192-bit */
+	AES_KEY_SIZE_256,       /**< AES key size is 256-bit */
+};
+
+/** AES start mode. */
+enum aes_start_mode {
+	AES_MANUAL_START = 0,   /**< Manual start mode */
+	AES_AUTO_START,         /**< Auto start mode */
+};
+
+/** AES operation mode. */
+enum aes_operation_mode {
+	AES_ECB_MODE = 0,       /**< Electronic Codebook (ECB) */
+	AES_CBC_MODE,           /**< Cipher Block Chaining (CBC) */
+	AES_OFB_MODE,           /**< Output Feedback (OFB) */
+	AES_CFB_MODE,           /**< Cipher Feedback (CFB) */
+	AES_CTR_MODE,           /**< Counter (CTR) */
+	AES_CCM_MODE,           /**< Counter (CCM) */
+	AES_GCM_MODE,           /**< Galois Counter Mode (GCM) */
+};
+
+/** AES Cipher FeedBack (CFB) size. */
+enum aes_cfb_size {
+	AES_CFB_SIZE_128 = 0,   /**< Cipher feedback data size is 128-bit */
+	AES_CFB_SIZE_64,        /**< Cipher feedback data size is 64-bit */
+	AES_CFB_SIZE_32,        /**< Cipher feedback data size is 32-bit */
+	AES_CFB_SIZE_16,        /**< Cipher feedback data size is 16-bit */
+	AES_CFB_SIZE_8,         /**< Cipher feedback data size is 8-bit */
+};
+
+/** AES countermeasure type */
+enum aes_countermeature_type {
+	AES_COUNTERMEASURE_TYPE_disabled = 0x0,    /**< Countermeasure type all disabled */
+	AES_COUNTERMEASURE_TYPE_1 = 0x01,          /**< Countermeasure1 enabled */
+	AES_COUNTERMEASURE_TYPE_2 = 0x02,          /**< Countermeasure2 enabled */
+	AES_COUNTERMEASURE_TYPE_3 = 0x04,          /**< Countermeasure3 enabled */
+	AES_COUNTERMEASURE_TYPE_4 = 0x08,          /**< Countermeasure4 enabled */
+	AES_COUNTERMEASURE_TYPE_ALL = 0x0F,        /**< Countermeasure type all enabled */
+};
+
+/**
+ * \name Module Status Flags
+ *
+ * AES status flags, returned by \ref aes_get_status() and cleared by
+ * \ref aes_clear_status().
+ *
+ * @{
+ */
+
+/** AES encryption complete.
+ */
+#define AES_ENCRYPTION_COMPLETE  (1UL << 0)
+
+/** AES GF multiplication complete.
+ */
+#define AES_GF_MULTI_COMPLETE    (1UL << 1)
+/** @} */
+
+
+/** AES Configuration structure. */
+struct aes_config {
+	/** AES data mode (decryption or encryption) */
+	enum aes_encrypt_mode encrypt_mode;
+	/** AES key size */
+	enum aes_key_size key_size;
+	/** Start mode */
+	enum aes_start_mode start_mode;
+	/** AES cipher operation mode*/
+	enum aes_operation_mode opmode;
+	/** Cipher feedback data size */
+	enum aes_cfb_size cfb_size;
+	/** Countermeasure type */
+	enum aes_countermeature_type ctype;
+	/** Enable XOR key */
+	bool enable_xor_key;
+	/** Enable key generation */
+	bool enable_key_gen;
+	/** Last output data mode enable/disable */
+	bool lod;
+};
+
+#if !defined(__DOXYGEN__)
+/**
+ * \brief Device structure.
+ */
+struct aes_module {
+	/** AES hardware module. */
+	Aes *hw;
+	/** AES cipher operation mode.*/
+	enum aes_operation_mode opmode;
+	/** AES key size. */
+	enum aes_key_size key_size;
+	/** Cipher feedback data size. */
+	enum aes_cfb_size cfb_size;
+};
+#endif
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+void aes_get_config_defaults(struct aes_config *const config);
+
+void aes_set_config(struct aes_module *const module,
+					Aes *const hw,
+					struct aes_config *const config);
+
+void aes_init(struct aes_module *const module,
+				Aes *const hw,
+				struct aes_config *const config);
+
+/** @} */
+
+/**
+ * \name Start, Enable, and Write
+ * @{
+ */
+
+/**
+ * \brief Start a manual encryption/decryption process.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ */
+static inline void aes_start(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CTRLB.reg |= AES_CTRLB_START;
+}
+/**
+ * \brief Notifies the module that the next input data block
+ * is the beginning of a new message.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ *
+ */
+static inline void aes_set_new_message(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+	module->hw->CTRLB.reg |= AES_CTRLB_NEWMSG;
+}
+/**
+ * \brief Clear the indication of the beginning for a new message
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ *
+ */
+static inline void aes_clear_new_message(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+	module->hw->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
+}
+
+void aes_enable(struct aes_module *const module);
+
+void aes_disable(struct aes_module *const module);
+
+void aes_write_key(struct aes_module *const module, const uint32_t *key);
+
+void aes_write_init_vector(struct aes_module *const module, const uint32_t *vector);
+
+void aes_write_input_data(struct aes_module *const module,
+		const uint32_t *p_input_data_buffer);
+
+void aes_read_output_data(struct aes_module *const module,
+		uint32_t *p_output_data_buffer);
+
+/**
+ * \brief Write AES random seed.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] seed Seed for the random number generator
+ */
+static inline void aes_write_random_seed(struct aes_module *const module,
+										uint32_t seed)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->RANDSEED.reg = seed;
+}
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ *
+ * \retval AES_ENCRYPTION_COMPLETE   AES encryption complete
+ * \retval AES_GF_MULTI_COMPLETE   AES GF multiplication complete
+ */
+static inline uint32_t aes_get_status(struct aes_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	uint32_t int_flags = module->hw->INTFLAG.reg;
+	uint32_t status_flags = 0;
+
+	if (int_flags & AES_INTFLAG_ENCCMP) {
+		status_flags |= AES_ENCRYPTION_COMPLETE;
+	}
+
+	if (int_flags & AES_INTFLAG_GFMCMP) {
+		status_flags |= AES_GF_MULTI_COMPLETE;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] status_flags Bitmask flags to clear
+ */
+static inline void aes_clear_status(
+		struct aes_module *const module,
+		const uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	uint32_t int_flags = 0;
+
+	if (status_flags & AES_ENCRYPTION_COMPLETE) {
+		int_flags |= AES_INTENCLR_ENCCMP;
+	}
+
+	if (status_flags & AES_GF_MULTI_COMPLETE) {
+		int_flags |= AES_INTENCLR_GFMCMP;
+	}
+
+	/* Clear interrupt flag */
+	module->hw->INTFLAG.reg = int_flags;
+}
+
+/** @} */
+
+/**
+ * \name Galois Counter Mode
+ * @{
+ */
+
+/**
+ * \brief  Get the AES GCM Hash Value.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] id Index into the GHASH array (range 0 to 3)
+ *
+ * \return The content of the GHASHRx[x = 0...3] value.
+ */
+static inline uint32_t aes_gcm_read_ghash(struct aes_module *const module, uint32_t id)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	return module->hw->GHASH[id].reg;
+}
+
+/**
+ * \brief  Set the AES GCM Hash Value.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] id Index into the GHASHx array (range 0 to 3)
+ * \param[in] ghash GCM hash value
+ */
+static inline void aes_gcm_write_ghash(struct aes_module *const module,
+									uint32_t id,uint32_t ghash)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->GHASH[id].reg = ghash;
+}
+
+
+/**
+ * \brief  Get AES GCM Hash key.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in]  id    Index into the Hash key array (range 0 to 3)
+ *
+ * \return The contents of the HASHKEYx[x = 0...3] specified.
+ */
+static inline uint32_t aes_gcm_read_hash_key(struct aes_module *const module,
+											uint32_t id)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	return module->hw->HASHKEY[id].reg;
+}
+
+/**
+ * \brief  Set the AES GCM Hash key.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] id Index into the Hash key array (range 0 to 3)
+ * \param[in] key GCM Hash key
+ */
+static inline void aes_gcm_write_hash_key(struct aes_module *const module,
+										uint32_t id, uint32_t key)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->HASHKEY[id].reg = key;
+}
+
+/**
+ * \brief  Get the AES GCM cipher length.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ *
+ * \return The contents of the HASHKEYx[x = 0...3] specified.
+ */
+static inline uint32_t aes_gcm_read_cipher_len(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	return (module->hw->CIPLEN.reg);
+}
+
+/**
+ * \brief  Set the AES GCM cipher length.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] len Cipher length
+ */
+static inline void aes_gcm_write_cipher_len(struct aes_module *const module,
+										uint32_t len)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CIPLEN.reg = len;
+}
+
+/**
+ * \brief  Set GCM end of input message status.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ */
+static inline void aes_gcm_set_end_message_status(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CTRLB.reg |= AES_CTRLB_EOM;
+}
+
+/**
+ * \brief  Clear GCM end of input message status.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ */
+static inline void aes_gcm_clear_end_message_status(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CTRLB.reg &= ~AES_CTRLB_EOM;
+}
+
+/**
+ * \brief  Set GF multiplication of GCM mode.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ */
+static inline void aes_gcm_set_gf_multiplication(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CTRLB.reg |= AES_CTRLB_GFMUL;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+ /** @} */
+
+/**
+ * \page asfdoc_sam0_drivers_aes_extra Extra Information for Advanced Encryption Standard
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>AAD</td>
+ *      <td>Additional Authenticated Data</td>
+ * </tr>
+ *  <tr>
+ *      <td>CBC</td>
+ *      <td>Cipher Block Chaining</td>
+ * </tr>
+ *  <tr>
+ *      <td>CFB</td>
+ *      <td>Cipher Feedback</td>
+ * </tr>
+ *  <tr>
+ *      <td>CTR</td>
+ *      <td> Counter</td>
+ * </tr>
+ *  <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ * </tr>
+ *  <tr>
+ *      <td>DMAC</td>
+ *      <td>DMA Controller</td>
+ * </tr>
+ *  <tr>
+ *      <td>ECB</td>
+ *      <td>Electronic Codebook</td>
+ * </tr>
+ *  <tr>
+ *      <td>GCM</td>
+ *      <td>Galois Counter Mode</td>
+ * </tr>
+ *  <tr>
+ *      <td>OFB</td>
+ *      <td>Output Feedback</td>
+ * </tr>
+ *  <tr>
+ *      <td>QSG</td>
+ *      <td>Quick Start Guide</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_drivers_aes_exqsg Examples for Advanced Encryption Standard
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_drivers_aes_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_aes_basic_use_case
+ *  - \subpage asfdoc_sam0_aes_callback_use_case
+ *  - \subpage asfdoc_sam0_aes_dma_use_case
+ *
+ * \page asfdoc_sam0_drivers_aes_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *      <th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *      <td>42445B</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L22</td>
+ *	</tr>
+ *	<tr>
+ *      <td>42445A</td>
+ *		<td>06/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ *
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif  /* AES_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.c
new file mode 100644
index 0000000000..ee30a5ae02
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.c
@@ -0,0 +1,111 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Advanced Encryption Standard driver.
+ *
+ * This file defines a useful set of functions for the AES on SAM devices.
+ *
+ * Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "aes.h"
+#include "aes_callback.h"
+
+/** \internal Max number of callback type. */
+#define AES_CALLBACK_TYPE_NUM 2
+
+/**
+* \internal
+* \brief AES callback function pointer
+*/
+aes_callback_t aes_callback_pointer[AES_CALLBACK_TYPE_NUM]={NULL,NULL};
+
+
+enum status_code aes_register_callback(
+	const aes_callback_t callback,
+	const enum aes_callback_type type)
+{
+	if (type >= AES_CALLBACK_TYPE_NUM){
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	aes_callback_pointer[type] = callback;
+	return STATUS_OK;
+}
+
+enum status_code aes_unregister_callback(
+	const aes_callback_t callback,
+	const enum aes_callback_type type)
+{
+	if (type >= AES_CALLBACK_TYPE_NUM){
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	aes_callback_pointer[type] = NULL;
+	return STATUS_OK;
+}
+
+
+
+/**
+* \internal The AES interrupt handler.
+*/
+void AES_Handler(void)
+{
+	uint32_t status = AES->INTFLAG.reg;
+
+	if (status & AES_INTFLAG_ENCCMP) {
+		if (aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]) {
+			AES->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+			aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]();
+		}
+	}
+
+	if (status & AES_INTFLAG_GFMCMP) {
+		if (aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]) {
+			AES->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+			aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]();
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.h
new file mode 100644
index 0000000000..bf6f9a50ff
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.h
@@ -0,0 +1,155 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Advanced Encryption Standard driver.
+ *
+ * This file defines a useful set of functions for the AES on SAM devices.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef AES_CALLBACK_H_INCLUDED
+#define AES_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system_interrupt.h>
+/**
+ * \addtogroup asfdoc_sam0_drivers_aes_group
+ *
+ * @{
+ */
+
+/** AES interrupt callback function type. */
+typedef void (*aes_callback_t)(void); 
+
+/** AES callback type. */
+enum aes_callback_type {
+	/** Encryption complete callback */
+	AES_CALLBACK_ENCRYPTION_COMPLETE = 0,
+	/** GF Multiplication Complete callback */
+	AES_CALLBACK_GF_MULTI_COMPLETE = 1,
+};
+ 
+/** \name Callback Configuration and Initialization
+ * @{
+ */
+ 
+enum status_code aes_register_callback(
+	const aes_callback_t callback,
+	const enum aes_callback_type type);
+
+enum status_code aes_unregister_callback(
+	const aes_callback_t callback,
+	const enum aes_callback_type type);
+
+/** @} */
+
+
+/** \name Callback Enabling and Disabling
+ * @{
+ */
+
+/**
+ * \brief Enable an AES callback.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] type Callback source type
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
+ */
+static inline enum status_code aes_enable_callback(struct aes_module *const module,
+		const enum aes_callback_type type)
+{
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_AES);
+	if (type == AES_CALLBACK_ENCRYPTION_COMPLETE){
+		module->hw->INTENSET.reg = AES_INTENSET_ENCCMP;
+	} else if (type == AES_CALLBACK_GF_MULTI_COMPLETE){
+		module->hw->INTENSET.reg = AES_INTENSET_GFMCMP;
+	} else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disable an AES callback.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in]  type Callback source type
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
+ */
+static inline enum status_code aes_disable_callback(struct aes_module *const module,
+		 const enum aes_callback_type type)
+{
+	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_AES);
+	if (type == AES_CALLBACK_ENCRYPTION_COMPLETE){
+		module->hw->INTENCLR.reg = AES_INTENCLR_ENCCMP;
+	} else if (type == AES_CALLBACK_GF_MULTI_COMPLETE){
+		module->hw->INTENCLR.reg = AES_INTENCLR_GFMCMP;
+	} else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* AES_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.c
new file mode 100644
index 0000000000..a469f8a869
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.c
@@ -0,0 +1,217 @@
+/**
+ * \file
+ *
+ * \brief SAM AON Sleep Timer Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "aon_sleep_timer.h"
+
+static aon_sleep_timer_callback_t aon_sleep_timer_callback = NULL;
+
+static void delay_cycle(uint32_t cycles)
+{
+	volatile uint32_t i = 0;
+
+	for (i = 0; i < cycles*100; i++) {
+		asm volatile ("nop");
+	}
+}
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given AON Sleep Timer configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structures before being
+ * modified by the user application.
+ *
+ * \param[out]  config  Pointer to a AON Sleep Timer module configuration structure to set
+ */
+void aon_sleep_timer_get_config_defaults(struct aon_sleep_timer_config *config)
+{
+	/* Default configuration values */
+	config->wakeup = AON_SLEEP_TIMER_WAKEUP_ARM;
+	config->mode = AON_SLEEP_TIMER_SINGLE_MODE;
+	config->counter = 32000;
+}
+
+/**
+ * \brief Disable AON Sleep Timer module instance.
+ *
+ * AON Sleep Timer module instance disable.
+ */
+void aon_sleep_timer_disable(void)
+{
+	uint32_t regval;
+
+	AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = 0;
+	regval = AON_SLEEP_TIMER0->CONTROL.reg;
+	regval &= ~AON_SLEEP_TIMER_CONTROL_RELOAD_ENABLE;
+	regval &= ~AON_SLEEP_TIMER_CONTROL_SINGLE_COUNT_ENABLE;
+	AON_SLEEP_TIMER0->CONTROL.reg = regval;
+
+	while (AON_SLEEP_TIMER0->CONTROL.reg & (1 << 14)) {
+	}
+}
+
+/**
+ * \brief Get AON Sleep Timer module instance current value.
+ *
+ * \retval Current value
+ */
+uint32_t aon_sleep_timer_get_current_value(void)
+{
+	return AON_SLEEP_TIMER0->CURRENT_COUNT_VALUE.reg;
+}
+
+/**
+ * \brief If AON Sleep Timer is active
+ *
+ * \return Active status of the AON Sleep Timer.
+ */
+bool aon_sleep_timer_sleep_timer_active(void)
+{
+	return AON_SLEEP_TIMER0->CONTROL.bit.SLEEP_TIMER_ACTIVE;
+}
+
+/**
+ * \brief Clear AON Sleep Timer module instance interrupt.
+ *
+ * This flag will be cleared automatically once the IRQ
+ * has been seen on the sleep clock.
+ */
+void aon_sleep_timer_clear_interrup(void)
+{
+	AON_SLEEP_TIMER0->CONTROL.reg |= AON_SLEEP_TIMER_CONTROL_IRQ_CLEAR;
+}
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers and enable a callback function which is implemented by the user.
+ *
+ * \param[in]     callback_func Pointer to callback function
+ */
+void aon_sleep_timer_register_callback(aon_sleep_timer_callback_t fun)
+{
+	aon_sleep_timer_callback = fun;
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters and disable a callback function implemented by the user.
+ *
+ */
+void aon_sleep_timer_unregister_callback(void)
+{
+	aon_sleep_timer_callback = NULL;
+}
+
+/**
+ * \brief Timer ISR handler.
+ *
+ * Timer ISR handler.
+ *
+ */
+static void aon_sleep_timer_isr_handler(void)
+{
+	aon_sleep_timer_clear_interrup();
+
+	if (aon_sleep_timer_callback) {
+		aon_sleep_timer_callback();
+	}
+}
+
+/**
+ * \brief Initializes AON Sleep Timer module instance.
+ *
+ * Initializes the AON Sleep Timer module, based on the parameters,
+ * and start timer.
+ *
+ * \param[in]     config       Pointer to the AON Sleep Timer configuration options struct
+ *
+ */
+void aon_sleep_timer_init(const struct aon_sleep_timer_config *config)
+{
+	uint32_t aon_st_ctrl = 0;
+
+	AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg = AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_RESETVALUE;
+	if (config->wakeup == AON_SLEEP_TIMER_WAKEUP_ARM_BLE) {
+		AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg |=
+				AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_ARM_ENABLE |
+				AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_BLE_ENABLE;
+	} else if (config->wakeup == AON_SLEEP_TIMER_WAKEUP_ARM) {
+		AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg |=
+				AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_ARM_ENABLE;
+	}
+
+	aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
+	while (aon_st_ctrl & ((1UL << 31) - 1)) {
+		AON_SLEEP_TIMER0->CONTROL.reg = 0;
+		delay_cycle(3);
+		while (aon_st_ctrl & ((config->mode == AON_SLEEP_TIMER_RELOAD_MODE) ?
+				(1 << 9) : (1 << 14))) {
+			aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
+		}
+		aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
+	}
+
+	if (config->mode == AON_SLEEP_TIMER_RELOAD_MODE) {
+		/* Reload counter will start here */
+		AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = config->counter;
+		AON_SLEEP_TIMER0->CONTROL.reg = AON_SLEEP_TIMER_CONTROL_RELOAD_ENABLE;
+	} else {
+		/* Single counter will start here */
+		AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = config->counter;
+		AON_SLEEP_TIMER0->CONTROL.reg = AON_SLEEP_TIMER_CONTROL_SINGLE_COUNT_ENABLE;
+	}
+
+	if (config->mode == AON_SLEEP_TIMER_SINGLE_MODE) {
+		while ((AON_SLEEP_TIMER0->CONTROL.reg &
+				AON_SLEEP_TIMER_CONTROL_SLP_TIMER_SINGLE_COUNT_ENABLE_DLY_Msk)
+				!= AON_SLEEP_TIMER_CONTROL_SLP_TIMER_SINGLE_COUNT_ENABLE_DLY_Msk) {
+		}
+	}
+
+	system_register_isr(RAM_ISR_TABLE_AON_SLEEP_TIMER_INDEX, (uint32_t)aon_sleep_timer_isr_handler);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.h
new file mode 100644
index 0000000000..27bfa52fde
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.h
@@ -0,0 +1,273 @@
+/**
+ * \file
+ *
+ * \brief SAM Always ON Sleep Timer Driver for SAMB11
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef AON_SLEEP_TIMER_H_INCLUDED
+#define AON_SLEEP_TIMER_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_aon_sleep_timer_group SAM AON SLEEP TIMER
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's Always-On Sleep Timer functionality,
+ * for the setup the period of wakeup the MCU from the sleep state.
+ *
+ * The following peripherals are used by this module:
+ *  - AON SLEEP TIMER
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_aon_sleep_timer_prerequisites
+ *  - \ref asfdoc_samb_aon_sleep_timer_module_overview
+ *  - \ref asfdoc_samb_aon_sleep_timer_special_considerations
+ *  - \ref asfdoc_samb_aon_sleep_timer_extra_info
+ *  - \ref asfdoc_samb_aon_sleep_timer_examples
+ *  - \ref asfdoc_samb_aon_sleep_timer_api_overview
+ *
+ *
+ * \section asfdoc_samb_aon_sleep_timer_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_aon_sleep_timer_module_overview Module Overview
+ * This driver provides an interrupt for the MCU which in the sleep state
+ * when the timer counter is decline to 0.
+ *
+ * \subsection asfdoc_samb_aon_sleep_timer_module_overview_wakeup_control Wakeup Control
+ * You can control wakeup domain, there'er three choices:
+ * - Disable wakeup
+ * - Wakeup arm
+ * - Wakeup arm and blue-tooth
+ *
+ * \subsection asfdoc_samb_aon_sleep_timer_module_overview_load_mode Counter Load Mode
+ * There are two counter load mode:
+ * - Single mode
+ *
+ *   The timer will trigger interrupt when the counter is decline to 0, then the counter is
+ *   always 0.
+ * - Reload mode
+ *
+ *   The timer will trigger interrupt when the counter is decline to 0, then the counter is
+ *   reload to the initial count.
+ *
+ * \section asfdoc_samb_aon_sleep_timer_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_samb_aon_sleep_timer_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_aon_sleep_timer_extra. This includes:
+ *  - \ref asfdoc_samb_aon_sleep_timer_extra_acronyms
+ *  - \ref asfdoc_samb_aon_sleep_timer_extra_dependencies
+ *  - \ref asfdoc_samb_aon_sleep_timer_extra_errata
+ *  - \ref asfdoc_samb_aon_sleep_timer_extra_history
+ *
+ *
+ * \section asfdoc_samb_aon_sleep_timer_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_aon_sleep_timer_exqsg.
+ *
+ *
+ * \section asfdoc_samb_aon_sleep_timer_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system_sam_b.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Type definition for a AON SLEEP TIMER module callback function. */
+typedef void (*aon_sleep_timer_callback_t)(void);
+
+/**
+ * \brief Specifies the counter mode is reload or single mode.
+ *
+ * This enum specifies counter with reload or single mode.
+ */
+enum aon_sleep_timer_mode {
+	/** Counter in reload mode */
+	AON_SLEEP_TIMER_RELOAD_MODE = 0,
+	/** Counter in single mode */
+	AON_SLEEP_TIMER_SINGLE_MODE,
+};
+
+/**
+ * \brief Enable or disable arm wakeup.
+ *
+ * This enum specifies arm wakeup enable or disable.
+ */
+enum aon_sleep_timer_wakeup {
+	/** Wakeup disable */
+	AON_SLEEP_TIMER_WAKEUP_DIS = 0,
+	/** Arm wakeup */
+	AON_SLEEP_TIMER_WAKEUP_ARM,
+	/** Arm and blue-tooth wakeup */
+	AON_SLEEP_TIMER_WAKEUP_ARM_BLE,
+};
+
+/**
+ *  \brief AON Sleep Timer configuration structure.
+ *
+ *  Configuration structure for a AON Sleep Timer instance. This structure should be
+ *  initialized by the \ref aon_sleep_timer_get_config_defaults() function before being
+ *  modified by the user application.
+ */
+struct aon_sleep_timer_config {
+	/** Enable wakeup arm or wakeup arm and blue-tooth 
+	  * or disable arm wakeup */
+	enum aon_sleep_timer_wakeup wakeup;
+	/** Counter is reload or single mode */
+	enum aon_sleep_timer_mode mode;
+	/** Counter value */
+	uint32_t counter;
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+void aon_sleep_timer_get_config_defaults(struct aon_sleep_timer_config *config);
+void aon_sleep_timer_init(const struct aon_sleep_timer_config *config);
+void aon_sleep_timer_disable(void);
+/** @} */
+
+/**
+ * \name Get value
+ * @{
+ */
+uint32_t aon_sleep_timer_get_current_value(void);
+/** @} */
+
+/**
+ * \name Callback
+ * @{
+ */
+void aon_sleep_timer_clear_interrup(void);
+bool aon_sleep_timer_sleep_timer_active(void);
+void aon_sleep_timer_register_callback(aon_sleep_timer_callback_t fun);
+void aon_sleep_timer_unregister_callback(void);
+/** @} */
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_samb_aon_sleep_timer_extra Extra Information for TIMER Driver
+ *
+ * \section asfdoc_samb_aon_sleep_timer_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>AON SLEEP TIMER</td>
+ *		<td>    </td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_samb_aon_sleep_timer_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_aon_sleep_timer_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_aon_sleep_timer_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_aon_sleep_timer_exqsg Examples for AON SLEEP TIMER Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_aon_sleep_timer_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_aon_sleep_timer_basic_use_case
+ *
+ * \page asfdoc_samb_aon_sleep_timer_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *    <th>Doc. Rev.</td>
+ *    <th>Date</td>
+ *    <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *    <td>A</td>
+ *    <td>09/2015</td>
+ *    <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod.h
new file mode 100644
index 0000000000..43786d5532
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod.h
@@ -0,0 +1,52 @@
+/**
+ * \file
+ *
+ * \brief SAM Brown Out Detector Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef BOD_H_INCLUDED
+#define BOD_H_INCLUDED
+
+#include <compiler.h>
+#include <bod_feature.h>
+
+#endif /* BOD_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod.c
new file mode 100644
index 0000000000..ee20b004e4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod.c
@@ -0,0 +1,92 @@
+/**
+ * \file
+ *
+ * \brief SAM Brown Out Detector Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "bod.h"
+
+/**
+ * \brief Configure a Brown Out Detector module.
+ *
+ * Configures a given BOD module with the settings stored in the given
+ * configuration structure.
+ *
+ * \param[in] conf     Configuration settings to use for the specified BODVDD
+ *
+ * \retval STATUS_OK                  Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG     An invalid BOD was supplied
+ * \retval STATUS_ERR_INVALID_OPTION  The requested BOD level was outside the acceptable range
+ */
+enum status_code bodvdd_set_config(
+		struct bodvdd_config *const conf)
+{
+	/* Sanity check arguments */
+	Assert(conf);
+
+	uint32_t temp = 0;
+
+	/* Check if module is enabled. */
+	if (SUPC->BODVDD.reg & SUPC_BODVDD_ENABLE) {
+		SUPC->BODVDD.reg &= ~SUPC_BODVDD_ENABLE;
+	}
+
+	/* Convert BOD prescaler, trigger action and mode to a bitmask */
+	temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
+			(uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
+
+	if (conf->hysteresis == true) {
+		temp |= SUPC_BODVDD_HYST;
+	}
+
+	if (conf->run_in_standby == true) {
+		temp |= SUPC_BODVDD_RUNSTDBY;
+	}
+
+	if (conf->level > 0x3F) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	SUPC->BODVDD.reg = SUPC_BODVDD_LEVEL(conf->level) | temp;
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod_feature.h
new file mode 100644
index 0000000000..ad35d381a7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod_feature.h
@@ -0,0 +1,414 @@
+/**
+ * \file
+ *
+ * \brief SAM Brown Out Detector Driver
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef BOD_FEATURE_H_INCLUDED
+#define BOD_FEATURE_H_INCLUDED
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_bod_group SAM Brown Out Detector (BOD) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Brown Out Detector (BOD) modules, to detect
+ * and respond to under-voltage events and take an appropriate action.
+ *
+ * The following peripherals are used by this module:
+ * - SUPC (Supply Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM C20/C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_bod_prerequisites
+ *  - \ref asfdoc_sam0_bod_module_overview
+ *  - \ref asfdoc_sam0_bod_special_considerations
+ *  - \ref asfdoc_sam0_bod_extra_info
+ *  - \ref asfdoc_sam0_bod_examples
+ *  - \ref asfdoc_sam0_bod_api_overview
+ *
+ *
+ * \section asfdoc_sam0_bod_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_bod_module_overview Module Overview
+ *
+ * The SAM devices contain a number of Brown Out Detector (BOD) modules.
+ * Each BOD monitors the supply voltage for any dips that go below the set
+ * threshold for the module. In case of a BOD detection the BOD will either reset
+ * the system or raise a hardware interrupt so that a safe power-down sequence can
+ * be attempted.
+ *
+ *
+ * \section asfdoc_sam0_bod_special_considerations Special Considerations
+ *
+ * The time between a BOD interrupt being raised and a failure of the processor
+ * to continue executing (in the case of a core power failure) is system
+ * specific; care must be taken that all critical BOD detection events can
+ * complete within the amount of time available.
+ *
+ * \section asfdoc_sam0_bod_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_bod_extra. This includes:
+ *  - \ref asfdoc_sam0_bod_extra_acronyms
+ *  - \ref asfdoc_sam0_bod_extra_dependencies
+ *  - \ref asfdoc_sam0_bod_extra_errata
+ *  - \ref asfdoc_sam0_bod_extra_history
+ *
+ *
+ * \section asfdoc_sam0_bod_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_bod_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_bod_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \brief Brown Out Detector input clock prescale values.
+ *
+ * List of possible BODVDD controller prescaler values, to reduce the sampling
+ * speed of a BODVDD to lower the power consumption.
+ */
+enum bodvdd_prescale {
+	/** Divide input prescaler clock by 2 */
+	BODVDD_PRESCALE_DIV_2       = SUPC_BODVDD_PSEL(0),
+	/** Divide input prescaler clock by 4 */
+	BODVDD_PRESCALE_DIV_4       = SUPC_BODVDD_PSEL(1),
+	/** Divide input prescaler clock by 8 */
+	BODVDD_PRESCALE_DIV_8       = SUPC_BODVDD_PSEL(2),
+	/** Divide input prescaler clock by 16 */
+	BODVDD_PRESCALE_DIV_16      = SUPC_BODVDD_PSEL(3),
+	/** Divide input prescaler clock by 32 */
+	BODVDD_PRESCALE_DIV_32      = SUPC_BODVDD_PSEL(4),
+	/** Divide input prescaler clock by 64 */
+	BODVDD_PRESCALE_DIV_64      = SUPC_BODVDD_PSEL(5),
+	/** Divide input prescaler clock by 128 */
+	BODVDD_PRESCALE_DIV_128     = SUPC_BODVDD_PSEL(6),
+	/** Divide input prescaler clock by 256 */
+	BODVDD_PRESCALE_DIV_256     = SUPC_BODVDD_PSEL(7),
+	/** Divide input prescaler clock by 512 */
+	BODVDD_PRESCALE_DIV_512     = SUPC_BODVDD_PSEL(8),
+	/** Divide input prescaler clock by 1024 */
+	BODVDD_PRESCALE_DIV_1024    = SUPC_BODVDD_PSEL(9),
+	/** Divide input prescaler clock by 2048 */
+	BODVDD_PRESCALE_DIV_2048    = SUPC_BODVDD_PSEL(10),
+	/** Divide input prescaler clock by 4096 */
+	BODVDD_PRESCALE_DIV_4096    = SUPC_BODVDD_PSEL(11),
+	/** Divide input prescaler clock by 8192 */
+	BODVDD_PRESCALE_DIV_8192    = SUPC_BODVDD_PSEL(12),
+	/** Divide input prescaler clock by 16384 */
+	BODVDD_PRESCALE_DIV_16384   = SUPC_BODVDD_PSEL(13),
+	/** Divide input prescaler clock by 32768 */
+	BODVDD_PRESCALE_DIV_32768   = SUPC_BODVDD_PSEL(14),
+	/** Divide input prescaler clock by 65536 */
+	BODVDD_PRESCALE_DIV_65536   = SUPC_BODVDD_PSEL(15),
+};
+
+/**
+ * \brief Brown Out Detector sampling modes in active sleep mode.
+ *
+ * List of possible BODVDD module voltage sampling modes in active sleep mode.
+ */
+enum bodvdd_mode_in_active {
+	/** BODVDD will sample the supply line continuously */
+	BODVDD_ACTCFG_CONTINUOUS = 0,
+	/** BODVDD will use the BODVDD sampling clock (1kHz) to sample the supply line */
+	BODVDD_ACTCFG_SAMPLED    = SUPC_BODVDD_ACTCFG,
+};
+
+/**
+ * \brief Brown Out Detector sampling modes in standby sleep mode.
+ *
+ * List of possible BODVDD module voltage sampling modes in standby sleep mode.
+ */
+enum bodvdd_mode_in_standby {
+	/** BODVDD will sample the supply line continuously */
+	BODVDD_STDBYCFG_CONTINUOUS = 0,
+	/** BODVDD will use the BODVDD sampling clock (1kHz) to sample the supply line */
+	BODVDD_STDBYCFG_SAMPLED    = SUPC_BODVDD_STDBYCFG,
+};
+
+/**
+ * \brief Brown Out Detector detection actions.
+ *
+ * List of possible BODVDD actions when a BODVDD module detects a brown-out condition.
+ */
+enum bodvdd_action {
+	/** A BODVDD detect will do nothing, and the BODVDD state must be polled */
+	BODVDD_ACTION_NONE      = SUPC_BODVDD_ACTION(0),
+	/** A BODVDD detect will reset the device */
+	BODVDD_ACTION_RESET     = SUPC_BODVDD_ACTION(1),
+	/** A BODVDD detect will fire an interrupt */
+	BODVDD_ACTION_INTERRUPT = SUPC_BODVDD_ACTION(2),
+	/** A BODVDD detect will put the device in backup sleep mode */
+	BODVDD_ACTION_BACKUP    = SUPC_BODVDD_ACTION(3),
+};
+
+/** Configuration structure for a BODVDD module. */
+struct bodvdd_config {
+	/** Input sampler clock prescaler factor, to reduce the 1kHz clock from the
+	 *  ULP32K to lower the sampling rate of the BODVDD */
+	enum bodvdd_prescale prescaler;
+	/** BODVDD configuration in active mode */
+	enum bodvdd_mode_in_active mode_in_active;
+	/** BODVDD configuration in backup sleep mode */
+	enum bodvdd_mode_in_standby mode_in_standby;
+	/** Action to perform when a low power detection is made */
+	enum bodvdd_action action;
+	/** BODVDD level to trigger at when monitors VDD except in backup sleep mode */
+	uint8_t level;
+	/** If \c true, the BODVDD is kept enabled and sampled during standby */
+	bool run_in_standby;
+	/** If \c true, enables detection hysteresis */
+	bool hysteresis;
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Get default BODVDD configuration.
+ *
+ * The default BODVDD configuration is:
+ * - Clock prescaler set to divide the input clock by two
+ * - Continuous in active mode
+ * - Continuous in standby mode
+ * - Reset on BODVDD detect
+ * - Hysteresis enabled
+ * - BODVDD level 42 on V<SUB>DD</SUB>
+ * - BODVDD kept enabled during standby
+ *
+ * \param[out] conf  BODVDD configuration struct to set to default settings
+ */
+static inline void bodvdd_get_config_defaults(
+		struct bodvdd_config *const conf)
+{
+	/* Sanity check arguments */
+	Assert(conf);
+
+	conf->prescaler       = BODVDD_PRESCALE_DIV_2;
+	conf->mode_in_active  = BODVDD_ACTCFG_CONTINUOUS;
+	conf->mode_in_standby = BODVDD_STDBYCFG_CONTINUOUS;
+	conf->action          = BODVDD_ACTION_RESET;
+	conf->level           = 0x2A;
+	conf->run_in_standby  = true;
+	conf->hysteresis      = true;
+}
+
+enum status_code bodvdd_set_config(
+		struct bodvdd_config *const conf);
+
+/**
+ * \brief Enables a configured BODVDD module.
+ *
+ * Enables the BODVDD module that has been previously configured.
+ *
+ * \return Error code indicating the status of the enable operation.
+ *
+ * \retval STATUS_OK               If the BODVDD was successfully enabled
+ */
+static inline enum status_code bodvdd_enable(void)
+{
+	SUPC->BODVDD.reg |= SUPC_BODVDD_ENABLE;
+	while (!(SUPC->STATUS.reg & SUPC_STATUS_BVDDSRDY)) {
+		/* Wait for BODVDD register sync ready */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables an enabled BODVDD module.
+ *
+ * Disables the BODVDD module that was previously enabled.
+ *
+ * \return Error code indicating the status of the disable operation.
+ *
+ * \retval STATUS_OK               If the BODVDD was successfully disabled
+ */
+static inline enum status_code bodvdd_disable(void)
+{
+	SUPC->INTENCLR.reg = SUPC_INTENCLR_BODVDDRDY | SUPC_INTENCLR_BODVDDDET | SUPC_INTENCLR_BVDDSRDY;
+	SUPC->INTFLAG.reg = SUPC_INTFLAG_BODVDDRDY | SUPC_INTFLAG_BODVDDDET | SUPC_INTFLAG_BVDDSRDY;
+	SUPC->BODVDD.reg &= ~SUPC_BODVDD_ENABLE;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Checks if the BODVDD low voltage detection has occurred.
+ *
+ * Determines if the BODVDD has detected a voltage lower than its
+ * configured threshold.
+ *
+ * \return Detection status of the BODVDD.
+ *
+ * \retval true   If the BODVDD has detected a low voltage condition
+ * \retval false  If the BODVDD has not detected a low voltage condition
+ */
+static inline bool bodvdd_is_detected(void)
+{
+	return SUPC->STATUS.bit.BODVDDDET;
+}
+
+/**
+ * \brief Clears the low voltage detection state of the BODVDD.
+ *
+ * Clears the low voltage condition of the BODVDD module, so that new
+ * low voltage conditions can be detected.
+ *
+ */
+static inline void bodvdd_clear_detected(void)
+{
+	SUPC->INTFLAG.reg = SUPC_INTFLAG_BODVDDDET;
+	return;
+}
+
+
+/** @} */
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_bod_extra Extra Information for BOD Driver
+ *
+ * \section asfdoc_sam0_bod_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>BOD</td>
+ *      <td>Brown Out Detector</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_bod_exqsg Examples for BOD Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_bod_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_bod_basic_use_case
+ *
+ *  - \subpage asfdoc_sam0_bod_application_use_case
+ *
+ * \page asfdoc_sam0_bod_application_use_case Application Use Case for BOD - Application
+ * The preferred method of setting BODVDD levels and settings is trough the fuses.
+ * When it is desirable to set it in software, see the below use case.
+ *
+ * In this use case, a new BODVDD level might be set in SW if the clock settings
+ * are adjusted after a battery has charged to a higher level. When the battery
+ * discharges, the chip will reset when the battery level is below the SW BODVDD level.
+ * Now the chip will run at a lower clock rate and the BODVDD level from fuse.
+ * The chip should always measure the voltage before adjusting the frequency up.
+ *
+ * \page asfdoc_sam0_bod_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42701A</td>
+ *		<td>07/2016</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOD_FEATURE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod.c
new file mode 100644
index 0000000000..1c1fa1188a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod.c
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief SAM Brown Out Detector Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "bod.h"
+
+/**
+ * \brief Configure a Brown Out Detector module.
+ *
+ * Configures a given BOD module with the settings stored in the given
+ * configuration structure.
+ *
+ * \param[in] bod_id   BOD module to configure
+ * \param[in] conf     Configuration settings to use for the specified BOD
+ *
+ * \retval STATUS_OK                  Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG     An invalid BOD was supplied
+ * \retval STATUS_ERR_INVALID_OPTION  The requested BOD level was outside the acceptable range
+ */
+enum status_code bod_set_config(
+		const enum bod bod_id,
+		struct bod_config *const conf)
+{
+	/* Sanity check arguments */
+	Assert(conf);
+
+	uint32_t temp = 0;
+
+	/* Check if module is enabled. */
+	if (SYSCTRL->BOD33.reg & SYSCTRL_BOD33_ENABLE) {
+		SYSCTRL->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE;
+	}
+
+	/* Convert BOD prescaler, trigger action and mode to a bitmask */
+	temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
+			(uint32_t)conf->mode;
+
+	if (conf->mode == BOD_MODE_SAMPLED) {
+		/* Enable sampling clock if sampled mode */
+		temp |= SYSCTRL_BOD33_CEN;
+	}
+
+	if (conf->hysteresis == true) {
+		temp |= SYSCTRL_BOD33_HYST;
+	}
+
+	if (conf->run_in_standby == true) {
+		temp |= SYSCTRL_BOD33_RUNSTDBY;
+	}
+
+	switch (bod_id) {
+		case BOD_BOD33:
+			if (conf->level > 0x3F) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			SYSCTRL->BOD33.reg = SYSCTRL_BOD33_LEVEL(conf->level) | temp;
+
+			while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_B33SRDY)) {
+				/* Wait for BOD33 register sync ready */
+			}
+			break;
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod_feature.h
new file mode 100644
index 0000000000..d8cbb078ea
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod_feature.h
@@ -0,0 +1,470 @@
+/**
+ * \file
+ *
+ * \brief SAM Brown Out Detector Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef BOD_FEATURE_H_INCLUDED
+#define BOD_FEATURE_H_INCLUDED
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_bod_group SAM Brown Out Detector (BOD) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Brown Out Detector (BOD) modules, to detect
+ * and respond to under-voltage events and take an appropriate action.
+ *
+ * The following peripheral is used by this module:
+ * - SYSCTRL (System Control)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D10/D11
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_bod_prerequisites
+ *  - \ref asfdoc_sam0_bod_module_overview
+ *  - \ref asfdoc_sam0_bod_special_considerations
+ *  - \ref asfdoc_sam0_bod_extra_info
+ *  - \ref asfdoc_sam0_bod_examples
+ *  - \ref asfdoc_sam0_bod_api_overview
+ *
+ *
+ * \section asfdoc_sam0_bod_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_bod_module_overview Module Overview
+ *
+ * The SAM devices contain a number of Brown Out Detector (BOD) modules.
+ * Each BOD monitors the supply voltage for any dips that go below the set
+ * threshold for the module. In case of a BOD detection the BOD will either 
+ * reset the system or raise a hardware interrupt so that a safe power-down
+ * sequence can be attempted.
+ *
+ *
+ * \section asfdoc_sam0_bod_special_considerations Special Considerations
+ *
+ * The time between a BOD interrupt being raised and a failure of the processor
+ * to continue executing (in the case of a core power failure) is system
+ * specific; care must be taken that all critical BOD detection events can
+ * complete within the amount of time available.
+ *
+ * \section asfdoc_sam0_bod_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_bod_extra. This includes:
+ *  - \ref asfdoc_sam0_bod_extra_acronyms
+ *  - \ref asfdoc_sam0_bod_extra_dependencies
+ *  - \ref asfdoc_sam0_bod_extra_errata
+ *  - \ref asfdoc_sam0_bod_extra_history
+ *
+ *
+ * \section asfdoc_sam0_bod_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_bod_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_bod_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \brief Brown Out Detector hardware instance IDs.
+ *
+ * List of possible BOD controllers within the device.
+ */
+enum bod {
+	/** BOD33 External I/O voltage */
+	BOD_BOD33,
+};
+
+/**
+ * \brief Brown Out Detector input clock prescale values.
+ *
+ * List of possible BOD controller prescaler values, to reduce the sampling
+ * speed of a BOD to lower the power consumption.
+ */
+enum bod_prescale {
+	/** Divide input prescaler clock by 2 */
+	BOD_PRESCALE_DIV_2       = SYSCTRL_BOD33_PSEL(0),
+	/** Divide input prescaler clock by 4 */
+	BOD_PRESCALE_DIV_4       = SYSCTRL_BOD33_PSEL(1),
+	/** Divide input prescaler clock by 8 */
+	BOD_PRESCALE_DIV_8       = SYSCTRL_BOD33_PSEL(2),
+	/** Divide input prescaler clock by 16 */
+	BOD_PRESCALE_DIV_16      = SYSCTRL_BOD33_PSEL(3),
+	/** Divide input prescaler clock by 32*/
+	BOD_PRESCALE_DIV_32      = SYSCTRL_BOD33_PSEL(4),
+	/** Divide input prescaler clock by 64 */
+	BOD_PRESCALE_DIV_64      = SYSCTRL_BOD33_PSEL(5),
+	/** Divide input prescaler clock by 128 */
+	BOD_PRESCALE_DIV_128     = SYSCTRL_BOD33_PSEL(6),
+	/** Divide input prescaler clock by 256 */
+	BOD_PRESCALE_DIV_256     = SYSCTRL_BOD33_PSEL(7),
+	/** Divide input prescaler clock by 512 */
+	BOD_PRESCALE_DIV_512     = SYSCTRL_BOD33_PSEL(8),
+	/** Divide input prescaler clock by 1024 */
+	BOD_PRESCALE_DIV_1024    = SYSCTRL_BOD33_PSEL(9),
+	/** Divide input prescaler clock by 2048 */
+	BOD_PRESCALE_DIV_2048    = SYSCTRL_BOD33_PSEL(10),
+	/** Divide input prescaler clock by 4096 */
+	BOD_PRESCALE_DIV_4096    = SYSCTRL_BOD33_PSEL(11),
+	/** Divide input prescaler clock by 8192 */
+	BOD_PRESCALE_DIV_8192    = SYSCTRL_BOD33_PSEL(12),
+	/** Divide input prescaler clock by 16384 */
+	BOD_PRESCALE_DIV_16384   = SYSCTRL_BOD33_PSEL(13),
+	/** Divide input prescaler clock by 32768 */
+	BOD_PRESCALE_DIV_32768   = SYSCTRL_BOD33_PSEL(14),
+	/** Divide input prescaler clock by 65536 */
+	BOD_PRESCALE_DIV_65536   = SYSCTRL_BOD33_PSEL(15),
+};
+
+/**
+ * \brief Brown Out Detector detection actions.
+ *
+ * List of possible BOD actions when a BOD module detects a brown out condition.
+ */
+enum bod_action {
+	/** A BOD detect will do nothing, and the BOD state can't be polled */
+	BOD_ACTION_NONE      = SYSCTRL_BOD33_ACTION(0),
+	/** A BOD detect will reset the device */
+	BOD_ACTION_RESET     = SYSCTRL_BOD33_ACTION(1),
+	/** A BOD detect will fire an interrupt */
+	BOD_ACTION_INTERRUPT = SYSCTRL_BOD33_ACTION(2),
+};
+
+/**
+ * \brief Brown Out Detector sampling modes.
+ *
+ * List of possible BOD module voltage sampling modes.
+ */
+enum bod_mode {
+	/** BOD will sample the supply line continuously */
+	BOD_MODE_CONTINUOUS  = 0,
+	/** BOD will use the BOD sampling clock (1KHz) to sample the supply line */
+	BOD_MODE_SAMPLED     = SYSCTRL_BOD33_MODE,
+};
+
+/** Configuration structure for a BOD module. */
+struct bod_config {
+	/** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
+	 *  ULP32K to lower the sampling rate of the BOD */
+	enum bod_prescale prescaler;
+	/** Sampling configuration mode for the BOD */
+	enum bod_mode mode;
+	/** Action to perform when a low power detection is made */
+	enum bod_action action;
+	/** BOD level to trigger at (see electrical section of device datasheet) */
+	uint8_t level;
+	/** If \c true, enables detection hysteresis */
+	bool hysteresis;
+	/** If \c true, the BOD is kept enabled and sampled during device sleep */
+	bool run_in_standby;
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Get default BOD configuration.
+ *
+ * The default BOD configuration is:
+ * - Clock prescaler set to divide the input clock by two
+ * - Continuous mode
+ * - Reset on BOD detect
+ * - Hysteresis enabled
+ * - BOD level 0x12
+ * - BOD kept enabled during device sleep
+ *
+ * \param[out] conf  BOD configuration struct to set to default settings
+ */
+static inline void bod_get_config_defaults(
+		struct bod_config *const conf)
+{
+	/* Sanity check arguments */
+	Assert(conf);
+
+	conf->prescaler      = BOD_PRESCALE_DIV_2;
+	conf->mode           = BOD_MODE_CONTINUOUS;
+	conf->action         = BOD_ACTION_RESET;
+	conf->level          = 0x27;
+	conf->hysteresis     = true;
+	conf->run_in_standby = true;
+}
+
+enum status_code bod_set_config(
+		const enum bod bod_id,
+		struct bod_config *const conf);
+
+/**
+ * \brief Enables a configured BOD module.
+ *
+ * Enables the specified BOD module that has been previously configured.
+ *
+ * \param[in] bod_id  BOD module to enable
+ *
+ * \return Error code indicating the status of the enable operation.
+ *
+ * \retval STATUS_OK               If the BOD was successfully enabled
+ * \retval STATUS_ERR_INVALID_ARG  An invalid BOD was supplied
+ */
+static inline enum status_code bod_enable(
+		const enum bod bod_id)
+{
+	switch (bod_id) {
+		case BOD_BOD33:
+			SYSCTRL->BOD33.reg |= SYSCTRL_BOD33_ENABLE;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables an enabled BOD module.
+ *
+ * Disables the specified BOD module that was previously enabled.
+ *
+ * \param[in] bod_id  BOD module to disable
+ *
+ * \return Error code indicating the status of the disable operation.
+ *
+ * \retval STATUS_OK               If the BOD was successfully disabled
+ * \retval STATUS_ERR_INVALID_ARG  An invalid BOD was supplied
+ */
+static inline enum status_code bod_disable(
+		const enum bod bod_id)
+{
+	switch (bod_id) {
+		case BOD_BOD33:
+			SYSCTRL->INTENCLR.reg = SYSCTRL_INTENCLR_BOD33RDY | SYSCTRL_INTENCLR_BOD33DET | SYSCTRL_INTENCLR_B33SRDY;
+			SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | SYSCTRL_INTFLAG_B33SRDY;
+			SYSCTRL->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Checks if a specified BOD low voltage detection has occurred.
+ *
+ * Determines if a specified BOD has detected a voltage lower than its
+ * configured threshold.
+ *
+ * \param[in] bod_id  BOD module to check
+ *
+ * \return Detection status of the specified BOD.
+ *
+ * \retval true   If the BOD has detected a low voltage condition
+ * \retval false  If the BOD has not detected a low voltage condition
+ */
+static inline bool bod_is_detected(
+		const enum bod bod_id)
+{
+	switch (bod_id) {
+		case BOD_BOD33:
+			return SYSCTRL->INTFLAG.bit.BOD33DET;
+		default:
+			Assert(false);
+			return false;
+	}
+}
+
+/**
+ * \brief Clears the low voltage detection state of a specified BOD.
+ *
+ * Clears the low voltage condition of a specified BOD module, so that new
+ * low voltage conditions can be detected.
+ *
+ * \param[in] bod_id  BOD module to clear
+ */
+static inline void bod_clear_detected(
+		const enum bod bod_id)
+{
+	switch (bod_id) {
+		case BOD_BOD33:
+			SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET;
+			return;
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/** @} */
+
+/**
+ * @}
+ */
+
+
+/**
+ * \page asfdoc_sam0_bod_extra Extra Information for BOD Driver
+ *
+ * \section asfdoc_sam0_bod_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>BOD</td>
+ *      <td>Brown Out Detector</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Removed BOD12 reference</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_bod_exqsg Examples for BOD Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_bod_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_bod_basic_use_case
+ *
+ *  - \subpage asfdoc_sam0_bod_application_use_case
+ *
+ * \page asfdoc_sam0_bod_application_use_case Application Use Case for BOD - Application
+ * The preferred method of setting BOD33 levels and settings is through the fuses.
+ * When it is desirable to set it in software, see the below use case.
+ *
+ * In this use case, a new BOD33 level might be set in SW if the clock settings
+ * are adjusted up after a battery has charged to a higher level. When the battery
+ * discharges, the chip will reset when the battery level is below SW BOD33 level.
+ * Now the chip will run at a lower clock rate and the BOD33 level from fuse.
+ * The chip should always measure the voltage before adjusting the frequency up.
+ *
+ * \page asfdoc_sam0_bod_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42149E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM DA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42149D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21, and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42149C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42149B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42149A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOD_FEATURE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod.c
new file mode 100644
index 0000000000..97bdaa6dff
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod.c
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief SAM Brown Out Detector Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "bod.h"
+
+/**
+ * \brief Configure a Brown Out Detector module.
+ *
+ * Configures a given BOD module with the settings stored in the given
+ * configuration structure.
+ *
+ * \param[in] conf     Configuration settings to use for the specified BOD33
+ *
+ * \retval STATUS_OK                  Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG     An invalid BOD was supplied
+ * \retval STATUS_ERR_INVALID_OPTION  The requested BOD level was outside the acceptable range
+ */
+enum status_code bod33_set_config(
+		struct bod33_config *const conf)
+{
+	/* Sanity check arguments */
+	Assert(conf);
+
+	uint32_t temp = 0;
+
+	/* Check if module is enabled. */
+	if (SUPC->BOD33.reg & SUPC_BOD33_ENABLE) {
+		SUPC->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+	}
+
+	/* Convert BOD prescaler, trigger action and mode to a bitmask */
+	temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action | (uint32_t)conf->monitor |
+			(uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
+
+	if (conf->hysteresis == true) {
+		temp |= SUPC_BOD33_HYST;
+	}
+
+	if (conf->run_in_standby == true) {
+		temp |= SUPC_BOD33_RUNSTDBY;
+	}
+
+	if (conf->run_in_backup == true) {
+		temp |= SUPC_BOD33_RUNBKUP;
+	}
+
+	if (conf->level > 0x3F || conf->backuplevel > 0x3F) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	SUPC->BOD33.reg = SUPC_BOD33_LEVEL(conf->level) |
+			SUPC_BOD33_BKUPLEVEL(conf->backuplevel) | temp;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Configure a Brown Out Detector module.
+ *
+ * Configures a given BOD module with the settings stored in the given
+ * configuration structure.
+ *
+ * \param[in] conf     Configuration settings to use for the specified BOD12
+ *
+ * \retval STATUS_OK                  Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG     An invalid BOD was supplied
+ * \retval STATUS_ERR_INVALID_OPTION  The requested BOD level was outside the acceptable range
+ */
+enum status_code bod12_set_config(
+		struct bod12_config *const conf)
+{
+	/* Sanity check arguments */
+	Assert(conf);
+
+	uint32_t temp = 0;
+
+	/* Check if module is enabled. */
+	if (SUPC->BOD12.reg & SUPC_BOD12_ENABLE) {
+		SUPC->BOD12.reg &= ~SUPC_BOD12_ENABLE;
+	}
+
+/* Convert BOD prescaler, trigger action and mode to a bitmask */
+	temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
+			(uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
+
+	if (conf->hysteresis == true) {
+		temp |= SUPC_BOD12_HYST;
+	}
+
+	if (conf->run_in_standby == true) {
+		temp |= SUPC_BOD12_RUNSTDBY;
+	}
+
+	if (conf->level > 0x3F) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	SUPC->BOD12.reg = SUPC_BOD12_LEVEL(conf->level) | temp;
+
+	return STATUS_OK;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod_feature.h
new file mode 100644
index 0000000000..ae191464e7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod_feature.h
@@ -0,0 +1,640 @@
+/**
+ * \file
+ *
+ * \brief SAM Brown Out Detector Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef BOD_FEATURE_H_INCLUDED
+#define BOD_FEATURE_H_INCLUDED
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_bod_group SAM Brown Out Detector (BOD) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Brown Out Detector (BOD) modules, to detect
+ * and respond to under-voltage events and take an appropriate action.
+ *
+ * The following peripheral is used by this module:
+ * - SUPC (Supply Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L21/L22
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_bod_prerequisites
+ *  - \ref asfdoc_sam0_bod_module_overview
+ *  - \ref asfdoc_sam0_bod_special_considerations
+ *  - \ref asfdoc_sam0_bod_extra_info
+ *  - \ref asfdoc_sam0_bod_examples
+ *  - \ref asfdoc_sam0_bod_api_overview
+ *
+ *
+ * \section asfdoc_sam0_bod_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_bod_module_overview Module Overview
+ *
+ * The SAM devices contain a number of Brown Out Detector (BOD) modules.
+ * Each BOD monitors the supply voltage for any dips that go below the set
+ * threshold for the module. In case of a BOD detection the BOD will either reset
+ * the system or raise a hardware interrupt so that a safe power-down sequence can
+ * be attempted.
+ *
+ *
+ * \section asfdoc_sam0_bod_special_considerations Special Considerations
+ *
+ * The time between a BOD interrupt being raised and a failure of the processor
+ * to continue executing (in the case of a core power failure) is system
+ * specific; care must be taken that all critical BOD detection events can
+ * complete within the amount of time available.
+ *
+ * \section asfdoc_sam0_bod_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_bod_extra. This includes:
+ *  - \ref asfdoc_sam0_bod_extra_acronyms
+ *  - \ref asfdoc_sam0_bod_extra_dependencies
+ *  - \ref asfdoc_sam0_bod_extra_errata
+ *  - \ref asfdoc_sam0_bod_extra_history
+ *
+ *
+ * \section asfdoc_sam0_bod_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_bod_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_bod_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \brief Brown Out Detector input clock prescale values.
+ *
+ * List of possible BOD33 controller prescaler values, to reduce the sampling
+ * speed of a BOD33 to lower the power consumption.
+ */
+enum bod33_prescale {
+	/** Divide input prescaler clock by 2 */
+	BOD33_PRESCALE_DIV_2       = SUPC_BOD33_PSEL(0),
+	/** Divide input prescaler clock by 4 */
+	BOD33_PRESCALE_DIV_4       = SUPC_BOD33_PSEL(1),
+	/** Divide input prescaler clock by 8 */
+	BOD33_PRESCALE_DIV_8       = SUPC_BOD33_PSEL(2),
+	/** Divide input prescaler clock by 16 */
+	BOD33_PRESCALE_DIV_16      = SUPC_BOD33_PSEL(3),
+	/** Divide input prescaler clock by 32 */
+	BOD33_PRESCALE_DIV_32      = SUPC_BOD33_PSEL(4),
+	/** Divide input prescaler clock by 64 */
+	BOD33_PRESCALE_DIV_64      = SUPC_BOD33_PSEL(5),
+	/** Divide input prescaler clock by 128 */
+	BOD33_PRESCALE_DIV_128     = SUPC_BOD33_PSEL(6),
+	/** Divide input prescaler clock by 256 */
+	BOD33_PRESCALE_DIV_256     = SUPC_BOD33_PSEL(7),
+	/** Divide input prescaler clock by 512 */
+	BOD33_PRESCALE_DIV_512     = SUPC_BOD33_PSEL(8),
+	/** Divide input prescaler clock by 1024 */
+	BOD33_PRESCALE_DIV_1024    = SUPC_BOD33_PSEL(9),
+	/** Divide input prescaler clock by 2048 */
+	BOD33_PRESCALE_DIV_2048    = SUPC_BOD33_PSEL(10),
+	/** Divide input prescaler clock by 4096 */
+	BOD33_PRESCALE_DIV_4096    = SUPC_BOD33_PSEL(11),
+	/** Divide input prescaler clock by 8192 */
+	BOD33_PRESCALE_DIV_8192    = SUPC_BOD33_PSEL(12),
+	/** Divide input prescaler clock by 16384 */
+	BOD33_PRESCALE_DIV_16384   = SUPC_BOD33_PSEL(13),
+	/** Divide input prescaler clock by 32768 */
+	BOD33_PRESCALE_DIV_32768   = SUPC_BOD33_PSEL(14),
+	/** Divide input prescaler clock by 65536 */
+	BOD33_PRESCALE_DIV_65536   = SUPC_BOD33_PSEL(15),
+};
+
+/**
+ * \brief Brown Out Detector voltage monitors.
+ *
+ * List of possible BOD33 module voltage monitored in active and standby mode.
+ */
+enum bod33_vol_monitor {
+	/** The BOD33 monitors the VDD power pin in active and standby mode */
+	BOD33_VMON_VDD  = 0,
+	/** The BOD33 monitors the VBAT power pin in active and standby mode */
+	BOD33_VMON_VBAT = SUPC_BOD33_VMON,
+};
+
+/**
+ * \brief Brown Out Detector sampling modes in active sleep mode.
+ *
+ * List of possible BOD33 module voltage sampling modes in active sleep mode.
+ */
+enum bod33_mode_in_active {
+	/** BOD33 will sample the supply line continuously */
+	BOD33_ACTCFG_CONTINUOUS = 0,
+	/** BOD33 will use the BOD33 sampling clock (1KHz) to sample the supply line */
+	BOD33_ACTCFG_SAMPLED    = SUPC_BOD33_ACTCFG,
+};
+
+/**
+ * \brief Brown Out Detector sampling modes in standby sleep mode.
+ *
+ * List of possible BOD33 module voltage sampling modes in standby sleep mode.
+ */
+enum bod33_mode_in_standby {
+	/** BOD33 will sample the supply line continuously */
+	BOD33_STDBYCFG_CONTINUOUS = 0,
+	/** BOD33 will use the BOD33 sampling clock (1KHz) to sample the supply line */
+	BOD33_STDBYCFG_SAMPLED    = SUPC_BOD33_STDBYCFG,
+};
+
+/**
+ * \brief Brown Out Detector detection actions.
+ *
+ * List of possible BOD33 actions when a BOD33 module detects a brown-out condition.
+ */
+enum bod33_action {
+	/** A BOD33 detect will do nothing, and the BOD33 state must be polled */
+	BOD33_ACTION_NONE      = SUPC_BOD33_ACTION(0),
+	/** A BOD33 detect will reset the device */
+	BOD33_ACTION_RESET     = SUPC_BOD33_ACTION(1),
+	/** A BOD33 detect will fire an interrupt */
+	BOD33_ACTION_INTERRUPT = SUPC_BOD33_ACTION(2),
+	/** A BOD33 detect will put the device in backup sleep mode */
+	BOD33_ACTION_BACKUP    = SUPC_BOD33_ACTION(3),
+};
+
+/** Configuration structure for a BOD33 module. */
+struct bod33_config {
+	/** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
+	 *  ULP32K to lower the sampling rate of the BOD33 */
+	enum bod33_prescale prescaler;
+	/** Voltage monitored in active and standby mode */
+	enum bod33_vol_monitor monitor;
+	/** BOD33 configuration in active mode */
+	enum bod33_mode_in_active mode_in_active;
+	/** BOD33 configuration in backup sleep mode */
+	enum bod33_mode_in_standby mode_in_standby;
+	/** Action to perform when a low power detection is made */
+	enum bod33_action action;
+	/** BOD33 level to trigger at when monitors VBAT or in backup sleep mode */
+	uint8_t backuplevel;
+	/** BOD33 level to trigger at when monitors VDD excpt in backup sleep mode */
+	uint8_t level;
+	/** If \c true, the BOD33 is kept enabled and sampled during device sleep */
+	bool run_in_backup;
+	/** If \c true, the BOD33 is kept enabled and sampled during standby */
+	bool run_in_standby;
+	/** If \c true, enables detection hysteresis */
+	bool hysteresis;
+};
+
+
+/**
+ * \brief Brown Out Detector input clock prescale values.
+ *
+ * List of possible BOD12 controller prescaler values, to reduce the sampling
+ * speed of a BOD12 to lower the power consumption.
+ */
+enum bod12_prescale {
+	/** Divide input prescaler clock by 2 */
+	BOD12_PRESCALE_DIV_2       = SUPC_BOD12_PSEL(0),
+	/** Divide input prescaler clock by 4 */
+	BOD12_PRESCALE_DIV_4       = SUPC_BOD12_PSEL(1),
+	/** Divide input prescaler clock by 8 */
+	BOD12_PRESCALE_DIV_8       = SUPC_BOD12_PSEL(2),
+	/** Divide input prescaler clock by 16 */
+	BOD12_PRESCALE_DIV_16      = SUPC_BOD12_PSEL(3),
+	/** Divide input prescaler clock by 32 */
+	BOD12_PRESCALE_DIV_32      = SUPC_BOD12_PSEL(4),
+	/** Divide input prescaler clock by 64 */
+	BOD12_PRESCALE_DIV_64      = SUPC_BOD12_PSEL(5),
+	/** Divide input prescaler clock by 128 */
+	BOD12_PRESCALE_DIV_128     = SUPC_BOD12_PSEL(6),
+	/** Divide input prescaler clock by 256 */
+	BOD12_PRESCALE_DIV_256     = SUPC_BOD12_PSEL(7),
+	/** Divide input prescaler clock by 512 */
+	BOD12_PRESCALE_DIV_512     = SUPC_BOD12_PSEL(8),
+	/** Divide input prescaler clock by 1024 */
+	BOD12_PRESCALE_DIV_1024    = SUPC_BOD12_PSEL(9),
+	/** Divide input prescaler clock by 2048 */
+	BOD12_PRESCALE_DIV_2048    = SUPC_BOD12_PSEL(10),
+	/** Divide input prescaler clock by 4096 */
+	BOD12_PRESCALE_DIV_4096    = SUPC_BOD12_PSEL(11),
+	/** Divide input prescaler clock by 8192 */
+	BOD12_PRESCALE_DIV_8192    = SUPC_BOD12_PSEL(12),
+	/** Divide input prescaler clock by 16384 */
+	BOD12_PRESCALE_DIV_16384   = SUPC_BOD12_PSEL(13),
+	/** Divide input prescaler clock by 32768 */
+	BOD12_PRESCALE_DIV_32768   = SUPC_BOD12_PSEL(14),
+	/** Divide input prescaler clock by 65536 */
+	BOD12_PRESCALE_DIV_65536   = SUPC_BOD12_PSEL(15),
+};
+
+/**
+ * \brief Brown Out Detector sampling modes in active sleep mode.
+ *
+ * List of possible BOD12 module voltage sampling modes in active sleep mode.
+ */
+enum bod12_mode_in_active {
+	/** BOD12 will sample the supply line continuously */
+	BOD12_ACTCFG_CONTINUOUS = 0,
+	/** BOD12 will use the BOD12 sampling clock (1KHz) to sample the supply line */
+	BOD12_ACTCFG_SAMPLED    = SUPC_BOD12_ACTCFG,
+};
+
+/**
+ * \brief Brown Out Detector sampling modes in standby sleep mode.
+ *
+ * List of possible BOD12 module voltage sampling modes in standby sleep mode.
+ */
+enum bod12_mode_in_standby {
+	/** BOD12 will sample the supply line continuously */
+	BOD12_STDBYCFG_CONTINUOUS = 0,
+	/** BOD12 will use the BOD12 sampling clock (1KHz) to sample the supply line */
+	BOD12_STDBYCFG_SAMPLED    = SUPC_BOD12_STDBYCFG,
+};
+
+/**
+ * \brief Brown Out Detector detection actions.
+ *
+ * List of possible BOD12 actions when a BOD12 module detects a brown-out condition.
+ */
+enum bod12_action {
+	/** A BOD12 detect will do nothing, and the BOD12 state must be polled */
+	BOD12_ACTION_NONE      = SUPC_BOD12_ACTION(0),
+	/** A BOD12 detect will reset the device */
+	BOD12_ACTION_RESET     = SUPC_BOD12_ACTION(1),
+	/** A BOD12 detect will fire an interrupt */
+	BOD12_ACTION_INTERRUPT = SUPC_BOD12_ACTION(2),
+};
+
+/** Configuration structure for a BOD12 module. */
+struct bod12_config {
+	/** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
+	 *  ULP32K to lower the sampling rate of the BOD12 */
+	enum bod12_prescale prescaler;
+	/** BOD12 configuration in active mode */
+	enum bod12_mode_in_active mode_in_active;
+	/** BOD12 configuration in backup sleep mode */
+	enum bod12_mode_in_standby mode_in_standby;
+	/** Action to perform when a low power detection is made */
+	enum bod12_action action;
+	/** BOD12 level to trigger at (see electrical section of device datasheet) */
+	uint8_t level;
+	/** If \c true, the BOD12 is kept enabled and sampled during device sleep */
+	bool run_in_standby;
+	/** If \c true, enables detection hysteresis */
+	bool hysteresis;
+};
+
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Get default BOD33 configuration.
+ *
+ * The default BOD33 configuration is:
+ * - Clock prescaler set to divide the input clock by two
+ * - Continuous in active mode
+ * - Continuous in standby mode
+ * - Monitor the V<SUB>DD</SUB> power pin
+ * - No action on BOD33 detect
+ * - Hysteresis enabled
+ * - BOD33 level 0x7 on V<SUB>DD</SUB>
+ * - BOD33 level 0x7 on V<SUB>BAT</SUB>
+ * - BOD33 kept enabled during device sleep
+ * - BOD33 kept enabled during standby
+ *
+ * \param[out] conf  BOD33 configuration struct to set to default settings
+ */
+static inline void bod33_get_config_defaults(
+		struct bod33_config *const conf)
+{
+	/* Sanity check arguments */
+	Assert(conf);
+
+	conf->prescaler       = BOD33_PRESCALE_DIV_2;
+	conf->monitor         = BOD33_VMON_VDD;
+	conf->mode_in_active  = BOD33_ACTCFG_CONTINUOUS;
+	conf->mode_in_standby = BOD33_STDBYCFG_CONTINUOUS;
+	conf->action          = BOD33_ACTION_NONE;
+	conf->level           = 0x7;
+	conf->backuplevel     = 0x7;
+	conf->run_in_backup   = true;
+	conf->run_in_standby  = true;
+	conf->hysteresis      = true;
+}
+
+enum status_code bod33_set_config(
+		struct bod33_config *const conf);
+
+/**
+ * \brief Enables a configured BOD33 module.
+ *
+ * Enables the BOD33 module that has been previously configured.
+ *
+ * \return Error code indicating the status of the enable operation.
+ *
+ * \retval STATUS_OK               If the BOD33 was successfully enabled
+ */
+static inline enum status_code bod33_enable(void)
+{
+	SUPC->BOD33.reg |= SUPC_BOD33_ENABLE;
+	while (!(SUPC->STATUS.reg & SUPC_STATUS_B33SRDY)) {
+		/* Wait for BOD33 register sync ready */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables an enabled BOD33 module.
+ *
+ * Disables the BOD33 module that was previously enabled.
+ *
+ * \return Error code indicating the status of the disable operation.
+ *
+ * \retval STATUS_OK               If the BOD33 was successfully disabled
+ */
+static inline enum status_code bod33_disable(void)
+{
+	SUPC->INTENCLR.reg = SUPC_INTENCLR_BOD33RDY | SUPC_INTENCLR_BOD33DET | SUPC_INTENCLR_B33SRDY;
+	SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY | SUPC_INTFLAG_BOD33DET | SUPC_INTFLAG_B33SRDY;
+	SUPC->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Checks if the BOD33 low voltage detection has occurred.
+ *
+ * Determines if the BOD33 has detected a voltage lower than its
+ * configured threshold.
+ *
+ * \return Detection status of the BOD33.
+ *
+ * \retval true   If the BOD33 has detected a low voltage condition
+ * \retval false  If the BOD33 has not detected a low voltage condition
+ */
+static inline bool bod33_is_detected(void)
+{
+	return SUPC->STATUS.bit.BOD33DET;
+}
+
+/**
+ * \brief Clears the low voltage detection state of the BOD33.
+ *
+ * Clears the low voltage condition of BOD33 module, so that new
+ * low voltage conditions can be detected.
+ *
+ */
+static inline void bod33_clear_detected(void)
+{
+	SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+	return;
+}
+
+/**
+ * \brief Get default BOD12 configuration.
+ *
+ * The default BOD12 configuration is:
+ * - Clock prescaler set to divide the input clock by two
+ * - Continuous in active mode
+ * - Continuous in standby mode
+ * - Reset on BOD12 detect
+ * - Hysteresis enabled
+ * - BOD12 level 0x12
+ * - BOD12 kept enabled during device sleep
+ *
+ * \param[out] conf  BOD12 configuration struct to set to default settings
+ */
+static inline void bod12_get_config_defaults(
+		struct bod12_config *const conf)
+{
+	/* Sanity check arguments */
+	Assert(conf);
+
+	conf->prescaler       = BOD12_PRESCALE_DIV_2;
+	conf->mode_in_active  = BOD12_ACTCFG_CONTINUOUS;
+	conf->mode_in_standby = BOD12_STDBYCFG_CONTINUOUS;
+	conf->action          = BOD12_ACTION_RESET;
+	conf->level           = 0x12;
+	conf->run_in_standby  = true;
+	conf->hysteresis      = true;
+}
+
+enum status_code bod12_set_config(
+		struct bod12_config *const conf);
+
+/**
+ * \brief Enables a configured BOD12 module.
+ *
+ * Enables the BOD12 module that has been previously configured.
+ *
+ * \return Error code indicating the status of the enable operation.
+ *
+ * \retval STATUS_OK               If the BOD12 was successfully enabled
+ */
+static inline enum status_code bod12_enable(void)
+{
+	SUPC->BOD12.reg |= SUPC_BOD12_ENABLE;
+	while (!(SUPC->STATUS.reg & SUPC_STATUS_B12SRDY)) {
+		/* Wait for BOD12 register sync ready */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables an enabled BOD12 module.
+ *
+ * Disables the BOD12 module that was previously enabled.
+ *
+ * \return Error code indicating the status of the disable operation.
+ *
+ * \retval STATUS_OK               If the BOD12 was successfully disabled
+ */
+static inline enum status_code bod12_disable(void)
+{
+	SUPC->INTENCLR.reg = SUPC_INTENCLR_BOD12RDY | SUPC_INTENCLR_BOD12DET | SUPC_INTENCLR_B12SRDY;
+	SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY | SUPC_INTFLAG_BOD12DET | SUPC_INTFLAG_B12SRDY;
+	SUPC->BOD12.reg &= ~SUPC_BOD12_ENABLE;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Checks if the BOD12 low voltage detection has occurred.
+ *
+ * Determines if the BOD12 has detected a voltage lower than its
+ * configured threshold.
+ *
+ * \return Detection status of the BOD12.
+ *
+ * \retval true   If the BOD12 has detected a low voltage condition
+ * \retval false  If the BOD12 has not detected a low voltage condition
+ */
+static inline bool bod12_is_detected(void)
+{
+	return SUPC->STATUS.bit.BOD12DET;
+}
+
+/**
+ * \brief Clears the low voltage detection state of the BOD12.
+ *
+ * Clears the low voltage condition of BOD12 module, so that new
+ * low voltage conditions can be detected.
+ *
+ */
+static inline void bod12_clear_detected(void)
+{
+	SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
+	return;
+}
+
+
+/** @} */
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_bod_extra Extra Information for BOD Driver
+ *
+ * \section asfdoc_sam0_bod_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>BOD</td>
+ *      <td>Brown Out Detector</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_bod_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_bod_exqsg Examples for BOD Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_bod_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_bod_basic_use_case
+ *
+ *  - \subpage asfdoc_sam0_bod_application_use_case
+ *
+ * \page asfdoc_sam0_bod_application_use_case Application Use Case for BOD - Application
+ * The preferred method of setting BOD33 levels and settings is through the fuses.
+ * When it is desirable to set it in software, see the below use case.
+ *
+ * In this use case, a new BOD33 level might be set in SW if the clock settings
+ * are adjusted up after a battery has charged to a higher level. When the battery
+ * discharges, the chip will reset when the battery level is below SW BOD33 level.
+ * Now the chip will run at a lower clock rate and the BOD33 level from fuse.
+ * The chip should always measure the voltage before adjusting the frequency up.
+ *
+ * \page asfdoc_sam0_bod_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42453B</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L22</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42453A</td>
+ *		<td>06/2015</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOD_FEATURE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.c
new file mode 100644
index 0000000000..8065ff2470
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.c
@@ -0,0 +1,527 @@
+/**
+ * \file
+ *
+ * \brief SAM Control Area Network (CAN) Low Level Driver
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "can.h"
+#include <string.h>
+
+/* Instance for GCLK setting. */
+struct system_gclk_chan_config gclk_chan_conf;
+
+/* Message ram definition. */
+COMPILER_ALIGNED(4)
+static struct can_rx_element_buffer can0_rx_buffer[CONF_CAN0_RX_BUFFER_NUM];
+COMPILER_ALIGNED(4)
+static struct can_rx_element_fifo_0 can0_rx_fifo_0[CONF_CAN0_RX_FIFO_0_NUM];
+COMPILER_ALIGNED(4)
+static struct can_rx_element_fifo_1 can0_rx_fifo_1[CONF_CAN0_RX_FIFO_1_NUM];
+COMPILER_ALIGNED(4)
+static struct can_tx_element can0_tx_buffer[CONF_CAN0_TX_BUFFER_NUM + CONF_CAN0_TX_FIFO_QUEUE_NUM];
+COMPILER_ALIGNED(4)
+static struct can_tx_event_element can0_tx_event_fifo[CONF_CAN0_TX_EVENT_FIFO];
+COMPILER_ALIGNED(4)
+static struct can_standard_message_filter_element can0_rx_standard_filter[CONF_CAN0_RX_STANDARD_ID_FILTER_NUM];
+COMPILER_ALIGNED(4)
+static struct can_extended_message_filter_element can0_rx_extended_filter[CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM];
+
+COMPILER_ALIGNED(4)
+static struct can_rx_element_buffer can1_rx_buffer[CONF_CAN1_RX_BUFFER_NUM];
+COMPILER_ALIGNED(4)
+static struct can_rx_element_fifo_0 can1_rx_fifo_0[CONF_CAN1_RX_FIFO_0_NUM];
+COMPILER_ALIGNED(4)
+static struct can_rx_element_fifo_1 can1_rx_fifo_1[CONF_CAN1_RX_FIFO_1_NUM];
+COMPILER_ALIGNED(4)
+static struct can_tx_element can1_tx_buffer[CONF_CAN1_TX_BUFFER_NUM + CONF_CAN1_TX_FIFO_QUEUE_NUM];
+COMPILER_ALIGNED(4)
+static struct can_tx_event_element can1_tx_event_fifo[CONF_CAN1_TX_EVENT_FIFO];
+COMPILER_ALIGNED(4)
+static struct can_standard_message_filter_element can1_rx_standard_filter[CONF_CAN1_RX_STANDARD_ID_FILTER_NUM];
+COMPILER_ALIGNED(4)
+static struct can_extended_message_filter_element can1_rx_extended_filter[CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM];
+
+static void _can_message_memory_init(Can *hw)
+{
+	if (hw == CAN0) {
+		hw->SIDFC.reg = CAN_SIDFC_FLSSA((uint32_t)can0_rx_standard_filter) |
+				CAN_SIDFC_LSS(CONF_CAN0_RX_STANDARD_ID_FILTER_NUM);
+		hw->XIDFC.reg = CAN_XIDFC_FLESA((uint32_t)can0_rx_extended_filter) |
+				CAN_XIDFC_LSE(CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM);
+		hw->RXF0C.reg = CAN_RXF0C_F0SA((uint32_t)can0_rx_fifo_0) |
+				CAN_RXF0C_F0S(CONF_CAN0_RX_FIFO_0_NUM);
+		hw->RXF1C.reg = CAN_RXF1C_F1SA((uint32_t)can0_rx_fifo_1) |
+				CAN_RXF1C_F1S(CONF_CAN0_RX_FIFO_1_NUM);
+		hw->RXBC.reg = CAN_RXBC_RBSA((uint32_t)can0_rx_buffer);
+		hw->TXBC.reg = CAN_TXBC_TBSA((uint32_t)can0_tx_buffer) |
+				CAN_TXBC_NDTB(CONF_CAN0_TX_BUFFER_NUM) |
+				CAN_TXBC_TFQS(CONF_CAN0_TX_FIFO_QUEUE_NUM);
+		hw->TXEFC.reg = CAN_TXEFC_EFSA((uint32_t)can0_tx_event_fifo) |
+				CAN_TXEFC_EFS(CONF_CAN0_TX_EVENT_FIFO);
+	} else if (hw == CAN1) {
+		hw->SIDFC.reg = CAN_SIDFC_FLSSA((uint32_t)can1_rx_standard_filter) |
+				CAN_SIDFC_LSS(CONF_CAN1_RX_STANDARD_ID_FILTER_NUM);
+		hw->XIDFC.reg = CAN_XIDFC_FLESA((uint32_t)can1_rx_extended_filter) |
+				CAN_XIDFC_LSE(CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM);
+		hw->RXF0C.reg = CAN_RXF0C_F0SA((uint32_t)can1_rx_fifo_0) |
+				CAN_RXF0C_F0S(CONF_CAN1_RX_FIFO_0_NUM);
+		hw->RXF1C.reg = CAN_RXF1C_F1SA((uint32_t)can1_rx_fifo_1) |
+				CAN_RXF1C_F1S(CONF_CAN1_RX_FIFO_1_NUM);
+		hw->RXBC.reg = CAN_RXBC_RBSA((uint32_t)can1_rx_buffer);
+		hw->TXBC.reg = CAN_TXBC_TBSA((uint32_t)can1_tx_buffer) |
+				CAN_TXBC_NDTB(CONF_CAN1_TX_BUFFER_NUM) |
+				CAN_TXBC_TFQS(CONF_CAN1_TX_FIFO_QUEUE_NUM);
+		hw->TXEFC.reg = CAN_TXEFC_EFSA((uint32_t)can1_tx_event_fifo) |
+				CAN_TXEFC_EFS(CONF_CAN1_TX_EVENT_FIFO);
+	}
+
+	/**
+	 * The data size in conf_can.h should be 8/12/16/20/24/32/48/64,
+	 * The corresponding setting value in register is 0/1//2/3/4/5/6/7.
+	 * To simplify the calculation, seperate to two group 8/12/16/20/24 which
+	 * increased with 4 and 32/48/64 which increased with 16.
+	 */
+	if (CONF_CAN_ELEMENT_DATA_SIZE <= 24) {
+		hw->RXESC.reg = CAN_RXESC_RBDS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4) |
+				CAN_RXESC_F0DS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4) |
+				CAN_RXESC_F1DS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4);
+		hw->TXESC.reg = CAN_TXESC_TBDS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4);
+	} else {
+		hw->RXESC.reg = CAN_RXESC_RBDS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
+				CAN_RXESC_F0DS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
+				CAN_RXESC_F1DS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
+		hw->TXESC.reg = CAN_TXESC_TBDS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
+	}
+}
+
+static void _can_set_configuration(Can *hw, struct can_config *config)
+{
+	/* Timing setting. */
+	hw->NBTP.reg = CAN_NBTP_NBRP(CONF_CAN_NBTP_NBRP_VALUE) |
+			CAN_NBTP_NSJW(CONF_CAN_NBTP_NSJW_VALUE) |
+			CAN_NBTP_NTSEG1(CONF_CAN_NBTP_NTSEG1_VALUE) |
+			CAN_NBTP_NTSEG2(CONF_CAN_NBTP_NTSEG2_VALUE);
+	hw->DBTP.reg = CAN_DBTP_DBRP(CONF_CAN_DBTP_DBRP_VALUE) |
+			CAN_DBTP_DSJW(CONF_CAN_DBTP_DSJW_VALUE) |
+			CAN_DBTP_DTSEG1(CONF_CAN_DBTP_DTSEG1_VALUE) |
+			CAN_DBTP_DTSEG2(CONF_CAN_DBTP_DTSEG2_VALUE);
+
+	if (config->tdc_enable) {
+		hw->DBTP.reg |= CAN_DBTP_TDC;
+	}
+	
+	if (config->run_in_standby) {
+		hw->MRCFG.reg |= 0x01<<6;
+	}
+
+	hw->RWD.reg |= CAN_RWD_WDC(config->watchdog_configuration);
+
+	if (config->transmit_pause) {
+		hw->CCCR.reg |= CAN_CCCR_TXP;
+	}
+
+	if (config->edge_filtering) {
+		hw->CCCR.reg |= CAN_CCCR_EFBI;
+	}
+
+	if (config->protocol_exception_handling) {
+		hw->CCCR.reg |= CAN_CCCR_PXHD;
+	}
+
+	if (!config->automatic_retransmission) {
+		hw->CCCR.reg |= CAN_CCCR_DAR;
+	}
+
+	if (config->clock_stop_request) {
+		hw->CCCR.reg |= CAN_CCCR_CSR;
+	}
+
+	if (config->clock_stop_acknowledge) {
+		hw->CCCR.reg |= CAN_CCCR_CSA;
+	}
+
+	hw->TSCC.reg = CAN_TSCC_TCP(config->timestamp_prescaler) |
+			CAN_TSCC_TSS_INC_Val;
+
+	hw->TOCC.reg = CAN_TOCC_TOP(config->timeout_period) |
+			config->timeout_mode | config->timeout_enable;
+
+	hw->TDCR.reg = CAN_TDCR_TDCO(config->delay_compensation_offset) |
+			CAN_TDCR_TDCF(config->delay_compensation_filter_window_length);
+
+	hw->GFC.reg = CAN_GFC_ANFS(config->nonmatching_frames_action_standard) |
+			CAN_GFC_ANFE(config->nonmatching_frames_action_extended);
+	if (config->remote_frames_standard_reject) {
+		hw->GFC.reg |= CAN_GFC_RRFS;
+	}
+	if (config->remote_frames_extended_reject) {
+		hw->GFC.reg |= CAN_GFC_RRFE;
+	}
+
+	hw->XIDAM.reg = config->extended_id_mask;
+
+	if (config->rx_fifo_0_overwrite) {
+		hw->RXF0C.reg |= CAN_RXF0C_F0OM;
+	}
+	hw->RXF0C.reg |= CAN_RXF0C_F0WM(config->rx_fifo_0_watermark);
+
+	if (config->rx_fifo_1_overwrite) {
+		hw->RXF1C.reg |= CAN_RXF1C_F1OM;
+	}
+	hw->RXF1C.reg |= CAN_RXF1C_F1WM(config->rx_fifo_1_watermark);
+
+	if (config->tx_queue_mode) {
+		hw->TXBC.reg |= CAN_TXBC_TFQM;
+	}
+
+	hw->TXEFC.reg |= CAN_TXEFC_EFWM(config->tx_event_fifo_watermark);
+}
+
+static void _can_enable_peripheral_clock(struct can_module *const module_inst)
+{
+	if (module_inst->hw == CAN0) {
+		/* Turn on the digital interface clock. */
+		system_ahb_clock_set_mask(MCLK_AHBMASK_CAN0);
+	} else if (module_inst->hw == CAN1) {
+		/* Turn on the digital interface clock. */
+		system_ahb_clock_set_mask(MCLK_AHBMASK_CAN1);
+	}
+}
+
+void can_init(struct can_module *const module_inst, Can *hw,
+		struct can_config *config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+
+	/* Enable peripheral clock */
+	_can_enable_peripheral_clock(module_inst);
+
+	/* Configure GCLK channel */
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+
+	if (hw == CAN0) {
+		system_gclk_chan_set_config(CAN0_GCLK_ID, &gclk_chan_conf);
+		system_gclk_chan_enable(CAN0_GCLK_ID);
+	} else if (hw == CAN1) {
+		system_gclk_chan_set_config(CAN1_GCLK_ID, &gclk_chan_conf);
+		system_gclk_chan_enable(CAN1_GCLK_ID);
+	}
+
+
+	/* Configuration Change Enable. */
+	hw->CCCR.reg |= CAN_CCCR_CCE;
+
+	/* Initialize the message memory address. */
+	_can_message_memory_init(hw);
+
+	/* Set the configuration. */
+	_can_set_configuration(hw, config);
+
+	/* Enable the interrupt setting which no need change. */
+	hw->ILE.reg = CAN_ILE_EINT0 | CAN_ILE_EINT1;
+	hw->TXBTIE.reg = CAN_TXBTIE_MASK;
+	hw->TXBCIE.reg = CAN_TXBCIE_MASK;
+}
+
+void can_set_baudrate(Can *hw, uint32_t baudrate)
+{
+	uint32_t gclk_can_value = 0;
+	uint32_t can_nbtp_nbrp_value;
+	uint32_t can_nbtp_nsgw_value = 3, can_nbtp_ntseg1_value = 10, can_nbtp_ntseg2_value = 3;
+	
+	if (hw == CAN0) {
+		gclk_can_value = system_gclk_chan_get_hz(CAN0_GCLK_ID);
+		} else if (hw == CAN1) {
+		gclk_can_value = system_gclk_chan_get_hz(CAN1_GCLK_ID);
+	}
+	
+	can_nbtp_nbrp_value = gclk_can_value / baudrate / (3 + can_nbtp_ntseg1_value + can_nbtp_ntseg2_value);
+	
+	hw->NBTP.reg = CAN_NBTP_NBRP(can_nbtp_nbrp_value) |
+			CAN_NBTP_NSJW(can_nbtp_nsgw_value) |
+			CAN_NBTP_NTSEG1(can_nbtp_ntseg1_value) |
+			CAN_NBTP_NTSEG2(can_nbtp_ntseg2_value);
+}
+
+void can_fd_set_baudrate(Can *hw, uint32_t baudrate)
+{
+	uint32_t gclk_can_fd_value = 0;
+	uint32_t can_fd_dbtp_dbrp_value;
+	uint32_t can_fd_dbtp_dsgw_value = 3, can_fd_dbtp_dtseg1_value = 10, can_fd_dbtp_dtseg2_value = 3;
+	
+	if (hw == CAN0) {
+		gclk_can_fd_value = system_gclk_chan_get_hz(CAN0_GCLK_ID);
+		} else if (hw == CAN1) {
+		gclk_can_fd_value = system_gclk_chan_get_hz(CAN1_GCLK_ID);
+	}
+	
+	can_fd_dbtp_dbrp_value = gclk_can_fd_value / baudrate / (3 + can_fd_dbtp_dtseg1_value + can_fd_dbtp_dtseg2_value);
+	
+	hw->NBTP.reg = CAN_DBTP_DBRP(can_fd_dbtp_dbrp_value) |
+			CAN_DBTP_DSJW(can_fd_dbtp_dsgw_value) |
+			CAN_DBTP_DTSEG1(can_fd_dbtp_dtseg1_value) |
+			CAN_DBTP_DTSEG2(can_fd_dbtp_dtseg2_value);
+}
+
+void can_start(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg &= ~CAN_CCCR_INIT;
+	/* Wait for the sync. */
+	while (module_inst->hw->CCCR.reg & CAN_CCCR_INIT);
+}
+
+void can_stop(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+	/* Wait for the sync. */
+	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+}
+
+void can_enable_fd_mode(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+	/* Wait for the sync. */
+	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+	module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
+
+	module_inst->hw->CCCR.reg |= CAN_CCCR_FDOE;
+	module_inst->hw->CCCR.reg |= CAN_CCCR_BRSE;
+}
+
+void can_disable_fd_mode(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg &= ~CAN_CCCR_FDOE;
+}
+
+void can_enable_restricted_operation_mode(
+		struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+	/* Wait for the sync. */
+	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+	module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
+
+	module_inst->hw->CCCR.reg |= CAN_CCCR_ASM;
+}
+
+void can_disable_restricted_operation_mode(
+		struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg &= ~CAN_CCCR_ASM;
+}
+
+void can_enable_bus_monitor_mode(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+	/* Wait for the sync. */
+	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+	module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
+
+	module_inst->hw->CCCR.reg |= CAN_CCCR_MON;
+}
+
+void can_disable_bus_monitor_mode(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg &= ~CAN_CCCR_MON;
+}
+
+void can_enable_sleep_mode(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg |= CAN_CCCR_CSR;
+	/* Wait for the sync. */
+	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+
+	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_CSA));
+}
+
+void can_disable_sleep_mode(struct can_module *const module_inst)
+{
+	/* Enable peripheral clock */
+	_can_enable_peripheral_clock(module_inst);
+	if (module_inst->hw == CAN0) {
+		system_gclk_chan_set_config(CAN0_GCLK_ID, &gclk_chan_conf);
+		system_gclk_chan_enable(CAN0_GCLK_ID);
+	}
+
+	if (module_inst->hw == CAN1) {
+		system_gclk_chan_set_config(CAN1_GCLK_ID, &gclk_chan_conf);
+		system_gclk_chan_enable(CAN1_GCLK_ID);
+	}
+	module_inst->hw->CCCR.reg &= CAN_CCCR_CSR;
+	while ((module_inst->hw->CCCR.reg & CAN_CCCR_CSA));
+}
+
+void can_enable_test_mode(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+	/* Wait for the sync. */
+	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+	module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
+
+	module_inst->hw->CCCR.reg |= CAN_CCCR_TEST;
+	module_inst->hw->TEST.reg |= CAN_TEST_LBCK;
+}
+
+void can_disable_test_mode(struct can_module *const module_inst)
+{
+	module_inst->hw->CCCR.reg &= ~CAN_CCCR_TEST;
+}
+
+enum status_code can_set_rx_standard_filter(
+		struct can_module *const module_inst,
+		struct can_standard_message_filter_element *sd_filter, uint32_t index)
+{
+	if (module_inst->hw == CAN0) {
+		can0_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
+		return STATUS_OK;
+	} else if (module_inst->hw == CAN1) {
+		can1_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
+		return STATUS_OK;
+	}
+	return STATUS_ERR_INVALID_ARG;
+}
+
+enum status_code can_set_rx_extended_filter(
+		struct can_module *const module_inst,
+		struct can_extended_message_filter_element *et_filter, uint32_t index)
+{
+	if (module_inst->hw == CAN0) {
+		can0_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
+		can0_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
+		return STATUS_OK;
+	} else if (module_inst->hw == CAN1) {
+		can1_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
+		can1_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
+		return STATUS_OK;
+	}
+	return STATUS_ERR_INVALID_ARG;
+}
+
+enum status_code can_get_rx_buffer_element(
+		struct can_module *const module_inst,
+		struct can_rx_element_buffer *rx_element, uint32_t index)
+{
+	if (module_inst->hw == CAN0) {
+		memcpy(rx_element, &can0_rx_buffer[index], sizeof(struct can_rx_element_buffer));
+		return STATUS_OK;
+	} else if (module_inst->hw == CAN1) {
+		memcpy(rx_element, &can1_rx_buffer[index], sizeof(struct can_rx_element_buffer));
+		return STATUS_OK;
+	}
+	return STATUS_ERR_INVALID_ARG;
+}
+
+enum status_code can_get_rx_fifo_0_element(
+		struct can_module *const module_inst,
+		struct can_rx_element_fifo_0 *rx_element, uint32_t index)
+{
+	if (module_inst->hw == CAN0) {
+		memcpy(rx_element, &can0_rx_fifo_0[index], sizeof(struct can_rx_element_buffer));
+		return STATUS_OK;
+	} else if (module_inst->hw == CAN1) {
+		memcpy(rx_element, &can1_rx_fifo_0[index], sizeof(struct can_rx_element_buffer));
+		return STATUS_OK;
+	}
+	return STATUS_ERR_INVALID_ARG;
+}
+
+enum status_code can_get_rx_fifo_1_element(
+		struct can_module *const module_inst,
+		struct can_rx_element_fifo_1 *rx_element, uint32_t index)
+{
+	if (module_inst->hw == CAN0) {
+		memcpy(rx_element, &can0_rx_fifo_1[index], sizeof(struct can_rx_element_buffer));
+		return STATUS_OK;
+	} else if (module_inst->hw == CAN1) {
+		memcpy(rx_element, &can1_rx_fifo_1[index], sizeof(struct can_rx_element_buffer));
+		return STATUS_OK;
+	}
+	return STATUS_ERR_INVALID_ARG;
+}
+
+enum status_code can_set_tx_buffer_element(
+		struct can_module *const module_inst,
+		struct can_tx_element *tx_element, uint32_t index)
+{
+	uint32_t i;
+	if (module_inst->hw == CAN0) {
+		can0_tx_buffer[index].T0.reg = tx_element->T0.reg;
+		can0_tx_buffer[index].T1.reg = tx_element->T1.reg;
+		for (i = 0; i < CONF_CAN_ELEMENT_DATA_SIZE; i++) {
+			can0_tx_buffer[index].data[i] = tx_element->data[i];
+		}
+		return STATUS_OK;
+	} else if (module_inst->hw == CAN1) {
+		can1_tx_buffer[index].T0.reg = tx_element->T0.reg;
+		can1_tx_buffer[index].T1.reg = tx_element->T1.reg;
+		for (i = 0; i < CONF_CAN_ELEMENT_DATA_SIZE; i++) {
+			can1_tx_buffer[index].data[i] = tx_element->data[i];
+		}
+		return STATUS_OK;
+	}
+	return STATUS_ERR_INVALID_ARG;
+}
+
+enum status_code can_get_tx_event_fifo_element(
+		struct can_module *const module_inst,
+		struct can_tx_event_element *tx_event_element, uint32_t index)
+{
+	if (module_inst->hw == CAN0) {
+		tx_event_element->E0.reg = can0_tx_event_fifo[index].E0.reg;
+		tx_event_element->E1.reg = can0_tx_event_fifo[index].E1.reg;
+		return STATUS_OK;
+	} else if (module_inst->hw == CAN1) {
+		tx_event_element->E0.reg = can1_tx_event_fifo[index].E0.reg;
+		tx_event_element->E1.reg = can1_tx_event_fifo[index].E1.reg;
+		return STATUS_OK;
+	}
+	return STATUS_ERR_INVALID_ARG;
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.h
new file mode 100644
index 0000000000..653780dc56
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.h
@@ -0,0 +1,1419 @@
+/**
+ * \file
+ *
+ * \brief SAM Control Area Network (CAN) Low Level Driver
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CAN_H_INCLUDED
+#define CAN_H_INCLUDED
+
+#include <compiler.h>
+#include <system.h>
+#include <conf_can.h>
+
+/**
+ * \name Message RAM
+ * @{
+ */
+
+/* -------- CAN_RX_ELEMENT_R0 : (CAN RX element: 0x00) (R/W 32) Rx Element R0 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t ID:29;            /*!< bit:  0..28  Identifier */
+    uint32_t RTR:1;            /*!< bit:  29     Remote Transmission Request */
+    uint32_t XTD:1;            /*!< bit:  30     Extended Identifier */
+    uint32_t ESI:1;            /*!< bit:  31     Error State Indicator */
+  } bit;                       /*!< Structure used for bit access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_RX_ELEMENT_R0_Type;
+
+#define CAN_RX_ELEMENT_R0_ID_Pos          0
+#define CAN_RX_ELEMENT_R0_ID_Msk          (0x1FFFFFFFul << CAN_RX_ELEMENT_R0_ID_Pos)
+#define CAN_RX_ELEMENT_R0_ID(value)       ((CAN_RX_ELEMENT_R0_ID_Msk & ((value) << CAN_RX_ELEMENT_R0_ID_Pos)))
+#define CAN_RX_ELEMENT_R0_RTR_Pos         29
+#define CAN_RX_ELEMENT_R0_RTR             (0x1ul << CAN_RX_ELEMENT_R0_RTR_Pos)
+#define CAN_RX_ELEMENT_R0_XTD_Pos         30
+#define CAN_RX_ELEMENT_R0_XTD             (0x1ul << CAN_RX_ELEMENT_R0_XTD_Pos)
+#define CAN_RX_ELEMENT_R0_ESI_Pos         31
+#define CAN_RX_ELEMENT_R0_ESI             (0x1ul << CAN_RX_ELEMENT_R0_ESI_Pos)
+
+/* -------- CAN_RX_ELEMENT_R1 : (CAN RX element: 0x01) (R/W 32) Rx Element R1 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t RXTS:16;          /*!< bit: 0..15   Rx Timestamp */
+    uint32_t DLC:4;            /*!< bit: 16..19  Data Length Code */
+    uint32_t BRS:1;            /*!< bit: 20      Bit Rate Switch */
+    uint32_t FDF:1;            /*!< bit: 21      FD Format */
+    uint32_t :2;               /*!< bit: 22..23  Reserved */
+    uint32_t FIDX:7;           /*!< bit: 24..30  Filter Index */
+    uint32_t ANMF:1;           /*!< bit: 31      Accepted Non-matching Frame */
+  } bit;                       /*!< Structure used for bit  access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_RX_ELEMENT_R1_Type;
+
+#define CAN_RX_ELEMENT_R1_RXTS_Pos        0
+#define CAN_RX_ELEMENT_R1_RXTS_Msk        (0xFFFFul << CAN_RX_ELEMENT_R1_RXTS_Pos)
+#define CAN_RX_ELEMENT_R1_RXTS(value)     ((CAN_RX_ELEMENT_R1_RXTS_Msk & ((value) << CAN_RX_ELEMENT_R1_RXTS_Pos)))
+#define CAN_RX_ELEMENT_R1_DLC_Pos         16
+#define CAN_RX_ELEMENT_R1_DLC_Msk         (0xFul << CAN_RX_ELEMENT_R1_DLC_Pos)
+#define CAN_RX_ELEMENT_R1_DLC(value)      ((CAN_RX_ELEMENT_R1_DLC_Msk & ((value) << CAN_RX_ELEMENT_R1_DLC_Pos)))
+#define CAN_RX_ELEMENT_R1_BRS_Pos         20
+#define CAN_RX_ELEMENT_R1_BRS             (0x1ul << CAN_RX_ELEMENT_R1_BRS_Pos)
+#define CAN_RX_ELEMENT_R1_FDF_Pos         21
+#define CAN_RX_ELEMENT_R1_FDF             (0x1ul << CAN_RX_ELEMENT_R1_FDF_Pos)
+#define CAN_RX_ELEMENT_R1_FIDX_Pos        24
+#define CAN_RX_ELEMENT_R1_FIDX_Msk        (0x7Ful << CAN_RX_ELEMENT_R1_FIDX_Pos)
+#define CAN_RX_ELEMENT_R1_FIDX(value)     ((CAN_RX_ELEMENT_R1_FIDX_Msk & ((value) << CAN_RX_ELEMENT_R1_FIDX_Pos)))
+#define CAN_RX_ELEMENT_R1_ANMF_Pos        31
+#define CAN_RX_ELEMENT_R1_ANMF            (0x1ul << CAN_RX_ELEMENT_R1_ANMF_Pos)
+
+/**
+ * \brief CAN receive element structure for buffer.
+ */
+struct can_rx_element_buffer {
+	__IO CAN_RX_ELEMENT_R0_Type R0;
+	__IO CAN_RX_ELEMENT_R1_Type R1;
+	uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
+};
+
+/**
+ * \brief CAN receive element structure for FIFO 0.
+ */
+struct can_rx_element_fifo_0 {
+	__IO CAN_RX_ELEMENT_R0_Type R0;
+	__IO CAN_RX_ELEMENT_R1_Type R1;
+	uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
+};
+
+/**
+ * \brief CAN receive element structure for FIFO 1.
+ */
+struct can_rx_element_fifo_1 {
+	__IO CAN_RX_ELEMENT_R0_Type R0;
+	__IO CAN_RX_ELEMENT_R1_Type R1;
+	uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
+};
+
+/* -------- CAN_TX_ELEMENT_T0 : (CAN TX element: 0x00) (R/W 32) Tx Element T0 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t ID:29;            /*!< bit:  0..28  Identifier */
+    uint32_t RTR:1;            /*!< bit:  29     Remote Transmission Request */
+    uint32_t XTD:1;            /*!< bit:  30     Extended Identifier */
+    uint32_t ESI:1;            /*!< bit:  31     Error State Indicator */
+  } bit;                       /*!< Structure used for bit  access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_TX_ELEMENT_T0_Type;
+
+#define CAN_TX_ELEMENT_T0_EXTENDED_ID_Pos          0
+#define CAN_TX_ELEMENT_T0_EXTENDED_ID_Msk          (0x1FFFFFFFul << CAN_TX_ELEMENT_T0_EXTENDED_ID_Pos)
+#define CAN_TX_ELEMENT_T0_EXTENDED_ID(value)       ((CAN_TX_ELEMENT_T0_EXTENDED_ID_Msk & ((value) << CAN_TX_ELEMENT_T0_EXTENDED_ID_Pos)))
+#define CAN_TX_ELEMENT_T0_STANDARD_ID_Pos          18
+#define CAN_TX_ELEMENT_T0_STANDARD_ID_Msk          (0x7FFul << CAN_TX_ELEMENT_T0_STANDARD_ID_Pos)
+#define CAN_TX_ELEMENT_T0_STANDARD_ID(value)       ((CAN_TX_ELEMENT_T0_STANDARD_ID_Msk & ((value) << CAN_TX_ELEMENT_T0_STANDARD_ID_Pos)))
+#define CAN_TX_ELEMENT_T0_RTR_Pos         29
+#define CAN_TX_ELEMENT_T0_RTR             (0x1ul << CAN_TX_ELEMENT_T0_RTR_Pos)
+#define CAN_TX_ELEMENT_T0_XTD_Pos         30
+#define CAN_TX_ELEMENT_T0_XTD             (0x1ul << CAN_TX_ELEMENT_T0_XTD_Pos)
+#define CAN_TX_ELEMENT_T0_ESI_Pos         31
+#define CAN_TX_ELEMENT_T0_ESI             (0x1ul << CAN_TX_ELEMENT_T0_ESI_Pos)
+
+/* -------- CAN_TX_ELEMENT_T1 : (CAN TX element: 0x01) (R/W 32) Tx Element T1 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t :16;              /*!< bit: 0..15   Reserved */
+    uint32_t DLC:4;            /*!< bit: 16..19  Data Length Code */
+    uint32_t BRS:1;            /*!< bit: 20      Bit Rate Switch */
+    uint32_t FDF:1;            /*!< bit: 21      FD Format */
+    uint32_t :1;               /*!< bit: 22      Reserved */
+    uint32_t EFC:1;            /*!< bit: 23      Event FIFO Control */
+    uint32_t MM:8;             /*!< bit: 24..31  Message Marker */
+  } bit;                       /*!< Structure used for bit  access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_TX_ELEMENT_T1_Type;
+
+#define CAN_TX_ELEMENT_T1_DLC_Pos         16
+#define CAN_TX_ELEMENT_T1_DLC_Msk         (0xFul << CAN_TX_ELEMENT_T1_DLC_Pos)
+#define CAN_TX_ELEMENT_T1_DLC(value)      ((CAN_TX_ELEMENT_T1_DLC_Msk & ((value) << CAN_TX_ELEMENT_T1_DLC_Pos)))
+#define   CAN_TX_ELEMENT_T1_DLC_DATA8_Val        0x8ul  /**< \brief (CAN_RXESC) 8 byte data field */
+#define   CAN_TX_ELEMENT_T1_DLC_DATA12_Val       0x9ul  /**< \brief (CAN_RXESC) 12 byte data field */
+#define   CAN_TX_ELEMENT_T1_DLC_DATA16_Val       0xAul  /**< \brief (CAN_RXESC) 16 byte data field */
+#define   CAN_TX_ELEMENT_T1_DLC_DATA20_Val       0xBul  /**< \brief (CAN_RXESC) 20 byte data field */
+#define   CAN_TX_ELEMENT_T1_DLC_DATA24_Val       0xCul  /**< \brief (CAN_RXESC) 24 byte data field */
+#define   CAN_TX_ELEMENT_T1_DLC_DATA32_Val       0xDul  /**< \brief (CAN_RXESC) 32 byte data field */
+#define   CAN_TX_ELEMENT_T1_DLC_DATA48_Val       0xEul  /**< \brief (CAN_RXESC) 48 byte data field */
+#define   CAN_TX_ELEMENT_T1_DLC_DATA64_Val       0xFul  /**< \brief (CAN_RXESC) 64 byte data field */
+#define CAN_TX_ELEMENT_T1_BRS_Pos         20
+#define CAN_TX_ELEMENT_T1_BRS             (0x1ul << CAN_TX_ELEMENT_T1_BRS_Pos)
+#define CAN_TX_ELEMENT_T1_FDF_Pos         21
+#define CAN_TX_ELEMENT_T1_FDF             (0x1ul << CAN_TX_ELEMENT_T1_FDF_Pos)
+#define CAN_TX_ELEMENT_T1_EFC_Pos         23
+#define CAN_TX_ELEMENT_T1_EFC             (0x1ul << CAN_TX_ELEMENT_T1_EFC_Pos)
+#define CAN_TX_ELEMENT_T1_MM_Pos          24
+#define CAN_TX_ELEMENT_T1_MM_Msk          (0xFFul << CAN_TX_ELEMENT_T1_MM_Pos)
+#define CAN_TX_ELEMENT_T1_MM(value)       ((CAN_TX_ELEMENT_T1_MM_Msk & ((value) << CAN_TX_ELEMENT_T1_MM_Pos)))
+
+/**
+ * \brief CAN transfer element structure.
+ *
+ *  Common element structure for transfer buffer and FIFO/QUEUE.
+ */
+struct can_tx_element {
+	__IO CAN_TX_ELEMENT_T0_Type T0;
+	__IO CAN_TX_ELEMENT_T1_Type T1;
+	uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
+};
+
+/* -------- CAN_TX_EVENT_ELEMENT_E0 : (CAN TX event element: 0x00) (R/W 32) Tx Event Element E0 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t ID:29;            /*!< bit: 0..28  Identifier */
+    uint32_t RTR:1;            /*!< bit: 29     Remote Transmission Request */
+    uint32_t XTD:1;            /*!< bit: 30     Extended Identifier */
+    uint32_t ESI:1;            /*!< bit: 31     Error State Indicator */
+  } bit;                       /*!< Structure used for bit  access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_TX_EVENT_ELEMENT_E0_Type;
+
+#define CAN_TX_EVENT_ELEMENT_E0_ID_Pos          0
+#define CAN_TX_EVENT_ELEMENT_E0_ID_Msk          (0x1FFFFFFFul << CAN_TX_EVENT_ELEMENT_E0_ID_Pos)
+#define CAN_TX_EVENT_ELEMENT_E0_ID(value)       ((CAN_TX_EVENT_ELEMENT_E0_ID_Msk & ((value) << CAN_TX_EVENT_ELEMENT_E0_ID_Pos)))
+#define CAN_TX_EVENT_ELEMENT_E0_RTR_Pos         29
+#define CAN_TX_EVENT_ELEMENT_E0_RTR             (0x1ul << CAN_TX_EVENT_ELEMENT_E0_RTR_Pos)
+#define CAN_TX_EVENT_ELEMENT_E0_XTD_Pos         30
+#define CAN_TX_EVENT_ELEMENT_E0_XTD             (0x1ul << CAN_TX_EVENT_ELEMENT_E0_XTD_Pos)
+#define CAN_TX_EVENT_ELEMENT_E0_ESI_Pos         31
+#define CAN_TX_EVENT_ELEMENT_E0_ESI             (0x1ul << CAN_TX_EVENT_ELEMENT_E0_ESI_Pos)
+
+/* -------- CAN_TX_EVENT_ELEMENT_E1 : (CAN TX event element: 0x01) (R/W 32) Tx Event Element E1 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t TXTS:16;          /*!< bit: 0..15   Tx Timestamp */
+    uint32_t DLC:4;            /*!< bit: 16..19  Data Length Code */
+    uint32_t BRS:1;            /*!< bit: 20      Bit Rate Switch */
+    uint32_t FDF:1;            /*!< bit: 21      FD Format */
+    uint32_t ET:2;             /*!< bit: 22..23  Event Type */
+    uint32_t MM:8;             /*!< bit: 24..31  Message Marker */
+  } bit;                       /*!< Structure used for bit  access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_TX_EVENT_ELEMENT_E1_Type;
+
+#define CAN_TX_EVENT_ELEMENT_E1_TXTS_Pos        0
+#define CAN_TX_EVENT_ELEMENT_E1_TXTS_Msk        (0xFFFFul << CAN_TX_EVENT_ELEMENT_E1_TXTS_Pos)
+#define CAN_TX_EVENT_ELEMENT_E1_TXTS(value)     ((CAN_TX_EVENT_ELEMENT_E1_TXTS_Msk & ((value) << CAN_TX_EVENT_ELEMENT_E1_TXTS_Pos)))
+#define CAN_TX_EVENT_ELEMENT_E1_DLC_Pos         16
+#define CAN_TX_EVENT_ELEMENT_E1_DLC_Msk         (0xFul << CAN_TX_EVENT_ELEMENT_E1_DLC_Pos)
+#define CAN_TX_EVENT_ELEMENT_E1_DLC(value)      ((CAN_TX_EVENT_ELEMENT_E1_DLC_Msk & ((value) << CAN_TX_EVENT_ELEMENT_E1_DLC_Pos)))
+#define CAN_TX_EVENT_ELEMENT_E1_BRS_Pos         20
+#define CAN_TX_EVENT_ELEMENT_E1_BRS             (0x1ul << CAN_TX_EVENT_ELEMENT_E1_BRS_Pos)
+#define CAN_TX_EVENT_ELEMENT_E1_FDF_Pos         21
+#define CAN_TX_EVENT_ELEMENT_E1_FDF             (0x1ul << CAN_TX_EVENT_ELEMENT_E1_FDF_Pos)
+#define CAN_TX_EVENT_ELEMENT_E1_ET_Pos          22
+#define CAN_TX_EVENT_ELEMENT_E1_ET_Msk          (0x3ul << CAN_TX_EVENT_ELEMENT_E1_ET_Pos)
+#define CAN_TX_EVENT_ELEMENT_E1_ET(value)       ((CAN_TX_EVENT_ELEMENT_E1_ET_Msk & ((value) << CAN_TX_EVENT_ELEMENT_E1_ET_Pos)))
+#define CAN_TX_EVENT_ELEMENT_E1_MM_Pos          24
+#define CAN_TX_EVENT_ELEMENT_E1_MM_Msk          (0xFFul << CAN_TX_EVENT_ELEMENT_E1_MM_Pos)
+#define CAN_TX_EVENT_ELEMENT_E1_MM(value)       ((CAN_TX_EVENT_ELEMENT_E1_MM_Msk & ((value) << CAN_TX_EVENT_ELEMENT_E1_MM_Pos)))
+
+/**
+ * \brief CAN transfer event  FIFO element structure.
+ *
+ *  Common element structure for transfer event FIFO.
+ */
+struct can_tx_event_element {
+	__IO CAN_TX_EVENT_ELEMENT_E0_Type E0;
+	__IO CAN_TX_EVENT_ELEMENT_E1_Type E1;
+};
+
+/* -------- CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0 : (CAN standard message ID filter element: 0x00) (R/W 32) Standard Message ID Filter Element S0 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t SFID2:11;         /*!< bit: 0..10   Standard Filter ID 2 */
+    uint32_t :5;               /*!< bit: 11..15  Reserved */
+    uint32_t SFID1:11;         /*!< bit: 16..26  Standard Filter ID 1 */
+    uint32_t SFEC:3;           /*!< bit: 27..29  Standard Filter Element Configuration */
+    uint32_t SFT:2;            /*!< bit: 30..31  Standard Filter Type */
+  } bit;                       /*!< Structure used for bit  access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type;
+
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos          0
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk          (0x7FFul << CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos)
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2(value)       ((CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk & ((value) << CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos)))
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos          16
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Msk          (0x7FFul << CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos)
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(value)       ((CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Msk & ((value) << CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos)))
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos           27
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Msk           (0x7ul << CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos)
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC(value)        ((CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Msk & ((value) << CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos)))
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_DISABLE_Val     0
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val       1
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF1M_Val       2
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_REJECT_Val      3
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIORITY_Val    4
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIF0M_Val      5
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIF1M_Val      6
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STRXBUF_Val     7
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos            30
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Msk            (0x3ul << CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos)
+#define CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(value)         ((CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Msk & ((value) << CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos)))
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_RANGE          CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(0)
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_DUAL           CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(1)
+#define   CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC        CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(2)
+
+/**
+ * \brief CAN standard message ID filter element structure.
+ *
+ *  Common element structure for standard message ID filter element.
+ */
+struct can_standard_message_filter_element {
+	__IO CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type S0;
+};
+
+/* -------- CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0 : (CAN extended message ID filter element: 0x00) (R/W 32) Extended Message ID Filter Element F0 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t EFID1:29;         /*!< bit: 0..28   Extended Filter ID 1 */
+    uint32_t EFEC:3;           /*!< bit: 29..31  Extended Filter Element Configuration */
+  } bit;                       /*!< Structure used for bit  access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type;
+
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos          0
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Msk          (0x1FFFFFFFul << CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos)
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(value)       ((CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Msk & ((value) << CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos)))
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos           29
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Msk           (0x7ul << CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos)
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC(value)        ((CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Msk & ((value) << CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos)))
+#  define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_DISABLE_Val       0
+#  define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF0M_Val         1
+#  define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val         2
+#  define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_REJECT_Val        3
+#  define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIORITY_Val      4
+#  define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIF0M_Val        5
+#  define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIF1M_Val        6
+#  define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STRXBUF_Val       7
+
+/* -------- CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1 : (CAN extended message ID filter element: 0x01) (R/W 32) Extended Message ID Filter Element F1 Configuration -------- */
+typedef union {
+  struct {
+    uint32_t EFID2:29;         /*!< bit: 0..28  Extended Filter ID 2 */
+    uint32_t :1;               /*!< bit: 29     Reserved */
+    uint32_t EFT:2;            /*!< bit: 30..31 Extended Filter Type */
+  } bit;                       /*!< Structure used for bit  access */
+  uint32_t reg;                /*!< Type used for register access */
+} CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type;
+
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos          0
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk          (0x1FFFFFFFul << CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos)
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2(value)       ((CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk & ((value) << CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos)))
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos            30
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Msk            (0x3ul << CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos)
+#define CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(value)         ((CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Msk & ((value) << CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos)))
+#define   CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_RANGEM       CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(0)
+#define   CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_DUAL         CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(1)
+#define   CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC      CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(2)
+#define   CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_RANGE        CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(3)
+
+/**
+ * \brief CAN extended message ID filter element structure.
+ *
+ *  Common element structure for extended message ID filter element.
+ */
+struct can_extended_message_filter_element {
+	__IO CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type F0;
+	__IO CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type F1;
+};
+/** @} */
+
+/**
+ * \defgroup asfdoc_sam0_can_group SAM Control Area Network (CAN) Low Level Driver
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an low level
+ * interface for the configuration and management of the device's
+ * Control Area Network functionality.
+ *
+ * \note  Since "The Control Area Network (CAN) performs communication according
+ * to ISO 11898-1 (Bosch CAN specification 2.0 part A,B) and to Bosch CAN FD
+ * specification V1.0", the driver is focus on the MAC layer and try to offer
+ * the APIs which can be used by upper application layer.
+ *
+ * For storage of Rx/Tx messages and for storage of the filter configuration,
+ * a message RAM is needed to the CAN module. In this driver, the message RAM
+ * is static allocated, the related setting is defined and can be changed in
+ * the module configuration file "conf_can.h".
+ *
+ * The following peripherals are used by this module:
+ *  - CAN (Control Area Network)
+ *
+ * The following devices can use this module:
+ *  - SAM C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_can_prerequisites
+ *  - \ref asfdoc_sam0_can_module_overview
+ *  - \ref asfdoc_sam0_can_special_considerations
+ *  - \ref asfdoc_sam0_can_extra_info
+ *  - \ref asfdoc_sam0_can_examples
+ *  - \ref asfdoc_sam0_can_api_overview
+ *
+ *
+ * \section asfdoc_sam0_can_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_can_module_overview Module Overview
+ *
+ * This driver provides an interface for the Control Area Network Controller
+ * functions on the device.
+ *
+ *
+ * \section asfdoc_sam0_can_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_can_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_can_extra. This includes:
+ *  - \ref asfdoc_sam0_can_extra_acronyms
+ *  - \ref asfdoc_sam0_can_extra_dependencies
+ *  - \ref asfdoc_sam0_can_extra_errata
+ *  - \ref asfdoc_sam0_can_extra_history
+ *
+ *
+ * \section asfdoc_sam0_can_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_can_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_can_api_overview API Overview
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Module Setting
+ * @{
+ */
+
+/**
+ * \brief Can time out modes.
+ */
+enum can_timeout_mode {
+	/** Continuous operation. */
+	CAN_TIMEOUT_CONTINUES = CAN_TOCC_TOS_CONT,
+	/** Timeout controlled by TX Event FIFO. */
+	CAN_TIMEOUT_TX_EVEN_FIFO = CAN_TOCC_TOS_TXEF,
+	/** Timeout controlled by Rx FIFO 0. */
+	CAN_TIMEOUT_RX_FIFO_0 = CAN_TOCC_TOS_RXF0,
+	/** Timeout controlled by Rx FIFO 1. */
+	CAN_TIMEOUT_RX_FIFO_1 = CAN_TOCC_TOS_RXF1,
+};
+
+/**
+ * \brief Can nonmatching frames action.
+ */
+enum can_nonmatching_frames_action {
+	/** Accept in Rx FIFO 0. */
+	CAN_NONMATCHING_FRAMES_FIFO_0,
+	/** Accept in Rx FIFO 1. */
+	CAN_NONMATCHING_FRAMES_FIFO_1,
+	/** Reject. */
+	CAN_NONMATCHING_FRAMES_REJECT,
+};
+
+/**
+ * \brief CAN software device instance structure.
+ *
+ * CAN software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct can_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to CAN hardware module. */
+	Can *hw;
+#endif
+};
+
+/**
+ * \brief CAN configuration structure.
+ *
+ * Configuration structure for an CAN instance. This structure should be
+ * initialized by the \ref can_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct can_config {
+	/** GCLK generator used to clock the peripheral. */
+	enum gclk_generator clock_source;
+	/** CAN run in standby control. */
+	bool run_in_standby;
+	/** Start value of the Message RAM Watchdog Counter */
+	uint8_t watchdog_configuration;
+	/** Transmit Pause. */
+	bool transmit_pause;
+	/** Edge Filtering during Bus Integration. */
+	bool edge_filtering;
+	/** Protocol Exception Handling. */
+	bool protocol_exception_handling;
+	/** Automatic Retransmission. */
+	bool automatic_retransmission;
+	/** Clock Stop Request. */
+	bool clock_stop_request;
+	/** Clock Stop Acknowledge. */
+	bool clock_stop_acknowledge;
+	/** Timestamp Counter Prescaler: 0x0-0xF */
+	uint8_t timestamp_prescaler;
+	/** Timeout Period. */
+	uint16_t timeout_period;
+	/** Timeout Mode. */
+	enum can_timeout_mode timeout_mode;
+	/** Timeout enable. */
+	bool timeout_enable;
+	/** Transceiver Delay Compensation enable. */		
+	bool tdc_enable;
+	/** Transmitter Delay Compensation Offset : 0x0-0x7F */
+	uint8_t delay_compensation_offset;
+	/** Transmitter Delay Compensation Filter Window Length : 0x0-0x7F */
+	uint8_t delay_compensation_filter_window_length;
+	/** Nonmatching frames action for standard frames. */
+	enum can_nonmatching_frames_action nonmatching_frames_action_standard;
+	/** Nonmatching frames action for extended frames. */
+	enum can_nonmatching_frames_action nonmatching_frames_action_extended;
+	/** Reject Remote Standard Frames. */
+	bool remote_frames_standard_reject;
+	/** Reject Remote Extended Frames. */
+	bool remote_frames_extended_reject;
+	/** Extended ID Mask: 0x0-0x1FFFFFFF. */
+	uint32_t extended_id_mask;
+	/** Rx FIFO 0 Operation Mode. */
+	bool rx_fifo_0_overwrite;
+	/** Rx FIFO 0 Watermark: 1-64, other value disable it. */
+	uint8_t rx_fifo_0_watermark;
+	/** Rx FIFO 1 Operation Mode. */
+	bool rx_fifo_1_overwrite;
+	/** Rx FIFO 1 Watermark: 1-64, other value disable it. */
+	uint8_t rx_fifo_1_watermark;
+	/** Tx FIFO/Queue Mode, 0 for FIFO and 1 for Queue. */
+	bool tx_queue_mode;
+	/** Tx Event FIFO Watermark: 1-32, other value disable it. */
+	uint8_t tx_event_fifo_watermark;
+
+};
+
+/**
+ * \brief Initializes an CAN configuration structure to defaults
+ *
+ * Initializes a given CAN configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li GCLK generator 8 (GCLK main) clock source
+ *  \li Not run in standby mode
+ *  \li Disable Watchdog
+ *  \li Transmit pause enabled
+ *  \li Edge filtering during bus integration enabled
+ *  \li Protocol exception handling enabled
+ *  \li Automatic retransmission enabled
+ *  \li Clock stop request disabled
+ *  \li Clock stop acknowledge disabled
+ *  \li Timestamp Counter Prescaler 1
+ *  \li Timeout Period with 0xFFFF
+ *  \li Timeout Mode: Continuous operation
+ *  \li Disable Timeout
+ *  \li Transmitter Delay Compensation Offset is 0
+ *  \li Transmitter Delay Compensation Filter Window Length is 0
+ *  \li Reject nonmatching standard frames
+ *  \li Reject nonmatching extended frames
+ *  \li Reject remote standard frames
+ *  \li Reject remote extended frames
+ *  \li Extended ID Mask is 0x1FFFFFFF
+ *  \li Rx FIFO 0 Operation Mode: overwrite
+ *  \li Disable Rx FIFO 0 Watermark
+ *  \li Rx FIFO 1 Operation Mode: overwrite
+ *  \li Disable Rx FIFO 1 Watermark
+ *  \li Tx FIFO/Queue Mode: FIFO
+ *  \li Disable Tx Event FIFO Watermark
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+static inline void can_get_config_defaults(
+		struct can_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->clock_source = GCLK_GENERATOR_8;
+	config->run_in_standby = false;
+	config->watchdog_configuration = 0x00;
+	config->transmit_pause = true;
+	config->edge_filtering = true;
+	config->protocol_exception_handling = true;
+	config->automatic_retransmission = true;
+	config->clock_stop_request = false;
+	config->clock_stop_acknowledge = false;
+	config->timestamp_prescaler = 0;
+	config->timeout_period = 0xFFFF;
+	config->timeout_mode = CAN_TIMEOUT_CONTINUES;
+	config->timeout_enable = false;
+	config->tdc_enable = false;
+	config->delay_compensation_offset = 0;
+	config->delay_compensation_filter_window_length = 0;
+	config->nonmatching_frames_action_standard = CAN_NONMATCHING_FRAMES_REJECT;
+	config->nonmatching_frames_action_extended = CAN_NONMATCHING_FRAMES_REJECT;
+	config->remote_frames_standard_reject = true;
+	config->remote_frames_extended_reject = true;
+	config->extended_id_mask = 0x1FFFFFFF;
+	config->rx_fifo_0_overwrite = true;
+	config->rx_fifo_0_watermark = 0;
+	config->rx_fifo_1_overwrite = true;
+	config->rx_fifo_1_watermark = 0;
+	config->tx_queue_mode = false;
+	config->tx_event_fifo_watermark = 0;
+}
+
+
+/**
+ * \brief Initializes CAN module.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in]  hw          Pointer to the CAN module instance
+ * \param[in]  config      Pointer to the configuration struct
+ */
+void can_init(struct can_module *const module_inst, Can *hw,
+		struct can_config *config);
+
+/**
+ * \brief Set CAN baudrate.
+ *
+ * \param[in]  hw          Pointer to the CAN module instance
+ * \param[in]  baudrate    CAN baudrate
+ */
+void can_set_baudrate(Can *hw, uint32_t baudrate);
+
+/**
+ * \brief Set CAN_FD baudrate.
+ *
+ * \param[in]  hw          Pointer to the CAN module instance
+ * \param[in]  baudrate    CAN_FD baudrate
+ */
+void can_fd_set_baudrate(Can *hw, uint32_t baudrate);
+
+/**
+ * \brief Start CAN module communication.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_start(struct can_module *const module_inst);
+
+/**
+ * \brief Stop CAN module communication.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_stop(struct can_module *const module_inst);
+
+/**
+ * \brief Enable CAN FD mode.
+ *
+ * \note This function will set the CCCR.INIT bit, can_start() is needed to
+ * restart the communication.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_enable_fd_mode(struct can_module *const module_inst);
+
+/**
+ * \brief Disable CAN FD mode.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_disable_fd_mode(struct can_module *const module_inst);
+
+/**
+ * \brief Enable CAN restricted operation mode.
+ *
+ * \note This function will set the CCCR.INIT bit, can_start() is needed to
+ * restart the communication.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_enable_restricted_operation_mode(
+		struct can_module *const module_inst);
+
+/**
+ * \brief Disable CAN restricted operation mode.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_disable_restricted_operation_mode(
+		struct can_module *const module_inst);
+
+/**
+ * \brief Enable CAN bus monitor mode.
+ *
+ * \note This function will set the CCCR.INIT bit, can_start() is needed to
+ * restart the communication.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_enable_bus_monitor_mode(struct can_module *const module_inst);
+
+/**
+ * \brief Disable CAN bus monitor mode.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_disable_bus_monitor_mode(struct can_module *const module_inst);
+
+/**
+ * \brief Enable CAN sleep mode.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_enable_sleep_mode(struct can_module *const module_inst);
+
+/**
+ * \brief Disable CAN sleep mode.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_disable_sleep_mode(struct can_module *const module_inst);
+
+/**
+ * \brief Enable CAN test mode.
+ *
+ * \note This function will set the CCCR.INIT bit, can_start() is needed to
+ * restart the communication.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_enable_test_mode(struct can_module *const module_inst);
+
+/**
+ * \brief Disable CAN test mode.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+void can_disable_test_mode(struct can_module *const module_inst);
+
+/**
+ * \brief Can read timestamp count value.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return Timestamp count value.
+ */
+static inline uint16_t can_read_timestamp_count_value(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->TSCV.bit.TSC;
+}
+
+/**
+ * \brief Can read timeout  count value.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return Timeout count value.
+ */
+static inline uint16_t can_read_timeout_count_value(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->TOCV.bit.TOC;
+}
+
+/**
+ * \brief Can read error count.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return Error count value.
+ */
+static inline uint32_t can_read_error_count(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->ECR.reg;
+}
+
+/**
+ * \brief Can read protocol status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return protocol status value.
+ */
+static inline uint32_t can_read_protocal_status(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->PSR.reg;
+}
+
+/** @} */
+
+/**
+ * \name Rx Handling
+ * @{
+ */
+
+/**
+ * \brief Read high priority message status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return High priority message status value.
+ */
+static inline uint32_t can_read_high_priority_message_status(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->HPMS.reg;
+}
+
+/**
+ * \brief Get Rx buffer status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] index  Index offset in Rx buffer
+ *
+ * \return Rx buffer status value.
+ *
+ *  \retval true Rx Buffer updated from new message.
+ *  \retval false Rx Buffer not updated.
+ */
+static inline bool can_rx_get_buffer_status(
+		struct can_module *const module_inst, uint32_t index)
+{
+	if (index < 32) {
+		if (module_inst->hw->NDAT1.reg & (1 << index)) {
+			return true;
+		} else {
+			return false;
+		}
+	} else {
+		index -= 32;
+		if (module_inst->hw->NDAT2.reg & (1 << index)) {
+			return true;
+		} else {
+			return false;
+		}
+	}
+}
+
+/**
+ * \brief Clear Rx buffer status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] index  Index offset in Rx buffer
+ *
+ */
+static inline void can_rx_clear_buffer_status(
+		struct can_module *const module_inst, uint32_t index)
+{
+	if (index < 32) {
+		module_inst->hw->NDAT1.reg = (1 << index);
+	} else {
+		index -= 32;
+		module_inst->hw->NDAT2.reg = (1 << index);
+	}
+}
+
+/**
+ * \brief Get Rx FIFO status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] fifo_number  Rx FIFO 0 or 1
+ *
+ * \return Rx FIFO status value.
+ */
+static inline uint32_t can_rx_get_fifo_status(
+		struct can_module *const module_inst, bool fifo_number)
+{
+	if (!fifo_number) {
+		return module_inst->hw->RXF0S.reg;
+	} else {
+		return module_inst->hw->RXF1S.reg;
+	}
+}
+
+/**
+ * \brief Set Rx acknowledge.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] fifo_number  Rx FIFO 0 or 1
+ * \param[in] index  Index offset in FIFO
+ */
+static inline void can_rx_fifo_acknowledge(
+		struct can_module *const module_inst, bool fifo_number, uint32_t index)
+{
+	if (!fifo_number) {
+		module_inst->hw->RXF0A.reg = CAN_RXF0A_F0AI(index);
+	} else {
+		module_inst->hw->RXF1A.reg = CAN_RXF1A_F1AI(index);
+	}
+}
+
+/**
+ * \brief Get the standard message filter default value.
+ *
+ * The default configuration is as follows:
+ *  \li Classic filter: SFID1 = filter, SFID2 = mask
+ *  \li Store in Rx FIFO 0 if filter matches
+ *  \li SFID2 = 0x7FFul
+ *  \li SFID1 = 0x0ul
+ *
+ * \param[out] sd_filter  Pointer to standard filter element struct to initialize to default values
+ */
+static inline void can_get_standard_message_filter_element_default(
+		struct can_standard_message_filter_element *sd_filter)
+{
+	sd_filter->S0.reg = CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk |
+			CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(0) |
+			CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC(
+			CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val) |
+			CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC;
+}
+
+/**
+ * \brief Set the standard message filter.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] sd_filter  Pointer to standard filter element struct
+ * \param[in] index  Index offset in standard filter element
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Set the correct standard message filter.
+ *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
+ */
+enum status_code can_set_rx_standard_filter(
+		struct can_module *const module_inst,
+		struct can_standard_message_filter_element *sd_filter, uint32_t index);
+
+/**
+ * \brief Get the extended message filter default value.
+ *
+ * The default configuration is as follows:
+ *  \li Classic filter: SFID1 = filter, SFID2 = mask
+ *  \li Store in Rx FIFO 1 if filter matches
+ *  \li SFID2 = 0x1FFFFFFFul
+ *  \li SFID1 = 0x0ul
+ *
+ * \param[out] et_filter  Pointer to extended filter element struct to initialize to default values
+ */
+static inline void can_get_extended_message_filter_element_default(
+		struct can_extended_message_filter_element *et_filter)
+{
+	et_filter->F0.reg = CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(0) |
+			CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC(
+			CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val);
+	et_filter->F1.reg = CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk |
+			CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC;
+}
+
+/**
+ * \brief Set the extended message filter.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] et_filter  Pointer to extended filter element struct
+ * \param[in] index  Index offset in extended filter element
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Set the correct extended message filter.
+ *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
+ */
+enum status_code can_set_rx_extended_filter(
+		struct can_module *const module_inst,
+		struct can_extended_message_filter_element *et_filter, uint32_t index);
+
+/**
+ * \brief Get the pointer to the receive buffer element.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] rx_element  Pointer to receive buffer element
+ * \param[in] index  Index offset in receive buffer
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Get the correct pointer to the receive buffer element.
+ *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
+ */
+enum status_code can_get_rx_buffer_element(
+		struct can_module *const module_inst,
+		struct can_rx_element_buffer *rx_element, uint32_t index);
+
+/**
+ * \brief Get the pointer to the receive FIFO 0 element.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] rx_element  Pointer to receive FIFO 0
+ * \param[in] index  Index offset in receive FIFO 0
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Get the correct pointer to the receive FIFO 0 element.
+ *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
+ */
+enum status_code can_get_rx_fifo_0_element(
+		struct can_module *const module_inst,
+		struct can_rx_element_fifo_0 *rx_element, uint32_t index);
+
+/**
+ * \brief Get the pointer to the receive FIFO 1 element.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] rx_element  Pointer to receive FIFO 1
+ * \param[in] index  Index offset in receive FIFO 1
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Get the correct pointer to the receive FIFO 1 element.
+ *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
+ */
+enum status_code can_get_rx_fifo_1_element(
+		struct can_module *const module_inst,
+		struct can_rx_element_fifo_1 *rx_element, uint32_t index);
+
+/** @} */
+
+/**
+ * \name Tx Handling
+ * @{
+ */
+
+/**
+ * \brief Get Tx FIFO/Queue status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return Tx FIFO/Queue status value.
+ */
+static inline uint32_t can_tx_get_fifo_queue_status(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->TXFQS.reg;
+}
+
+/**
+ * \brief Get Tx buffer request pending status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return Bit mask of Tx buffer request pending status value.
+ */
+static inline uint32_t can_tx_get_pending_status(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->TXBRP.reg;
+}
+
+/**
+ * \brief Tx buffer add transfer request.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] trig_mask  The mask value to trigger transfer buffer
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Set the transfer request.
+ *  \retval STATUS_BUSY The module is in configuration.
+ */
+static inline enum status_code can_tx_transfer_request(
+		struct can_module *const module_inst, uint32_t trig_mask)
+{
+	if (module_inst->hw->CCCR.reg & CAN_CCCR_CCE) {
+		return STATUS_BUSY;
+	}
+	module_inst->hw->TXBAR.reg = trig_mask;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Set Tx Queue operation.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] trig_mask  The mask value to cancel transfer buffer
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Set the transfer request.
+ *  \retval STATUS_BUSY The module is in configuration.
+ */
+static inline enum status_code can_tx_cancel_request(
+		struct can_module *const module_inst, uint32_t trig_mask)
+{
+	if (module_inst->hw->CCCR.reg & CAN_CCCR_CCE) {
+		return STATUS_BUSY;
+	}
+	module_inst->hw->TXBCR.reg = trig_mask;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get Tx transmission status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return Bit mask of Tx transmission status value.
+ */
+static inline uint32_t can_tx_get_transmission_status(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->TXBTO.reg;
+}
+
+/**
+ * \brief Get Tx cancellation status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return Bit mask of Tx cancellation status value.
+ */
+static inline uint32_t can_tx_get_cancellation_status(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->TXBCF.reg;
+}
+
+/**
+ * \brief Get Tx event FIFO status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ *
+ * \return Tx event FIFO status value.
+ */
+static inline uint32_t can_tx_get_event_fifo_status(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->TXEFS.reg;
+}
+
+/**
+ * \brief Set Tx Queue operation.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] index  Index for the transfer FIFO
+ */
+static inline void can_tx_event_fifo_acknowledge(
+		struct can_module *const module_inst, uint32_t index)
+{
+	module_inst->hw->TXEFA.reg = CAN_TXEFA_EFAI(index);
+}
+
+/**
+ * \brief Get the default transfer buffer element.
+ *
+ * The default configuration is as follows:
+ *  \li 11-bit standard identifier
+ *  \li Transmit data frame
+ *  \li ID = 0x0ul
+ *  \li Store Tx events
+ *  \li Frame transmitted in Classic CAN format
+ *  \li Data Length Code is 8
+ *
+ * \param[out] tx_element  Pointer to transfer element struct to initialize to default values
+ */
+static inline void can_get_tx_buffer_element_defaults(
+		struct can_tx_element *tx_element)
+{
+	tx_element->T0.reg = 0;
+	tx_element->T1.reg = CAN_TX_ELEMENT_T1_EFC |
+			CAN_TX_ELEMENT_T1_DLC(CAN_TX_ELEMENT_T1_DLC_DATA8_Val);
+}
+
+/**
+ * \brief Set the transfer buffer element.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] tx_element  Pointer to transfer element struct
+ * \param[in] index  Index for the transfer buffer
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Set the correct transfer buffer element.
+ *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
+ */
+enum status_code can_set_tx_buffer_element(
+		struct can_module *const module_inst,
+		struct can_tx_element *tx_element, uint32_t index);
+
+/**
+ * \brief Get the pointer to the transfer event FIFO element.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] tx_event_element  Pointer to transfer event element
+ * \param[in] index  Index offset in transfer event FIFO
+ *
+ *  \return Status of the result.
+ *
+ *  \retval STATUS_OK   Get the correct pointer to the transfer event FIFO element.
+ *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
+ */
+enum status_code can_get_tx_event_fifo_element(
+		struct can_module *const module_inst,
+		struct can_tx_event_element *tx_event_element, uint32_t index);
+
+/** @} */
+
+/**
+ * \name Interrupt Handling
+ * @{
+ */
+
+/**
+ * \brief Can module interrupt source.
+ *
+ * Enum for the interrupt source.
+ */
+enum can_interrupt_source {
+	/** Rx FIFO 0 New Message Interrupt Enable. */
+	CAN_RX_FIFO_0_NEW_MESSAGE = CAN_IE_RF0NE,
+	/** Rx FIFO 0 Watermark Reached Interrupt Enable. */
+	CAN_RX_FIFO_0_WATERMARK = CAN_IE_RF0WE,
+	/** Rx FIFO 0 Full Interrupt Enable. */
+	CAN_RX_FIFO_0_FULL = CAN_IE_RF0FE,
+	/** Rx FIFO 0 Message Lost Interrupt Enable. */
+	CAN_RX_FIFO_0_LOST_MESSAGE = CAN_IE_RF0LE,
+	/** Rx FIFO 1 New Message Interrupt Enable. */
+	CAN_RX_FIFO_1_NEW_MESSAGE = CAN_IE_RF1NE,
+	/** Rx FIFO 1 Watermark Reached Interrupt Enable. */
+	CAN_RX_FIFO_1_WATERMARK = CAN_IE_RF1WE,
+	/** Rx FIFO 1 Full Interrupt Enable. */
+	CAN_RX_FIFO_1_FULL = CAN_IE_RF1FE,
+	/** Rx FIFO 1 Message Lost Interrupt Enable. */
+	CAN_RX_FIFO_1_MESSAGE_LOST = CAN_IE_RF1LE,
+	/** High Priority Message Interrupt Enable. */
+	CAN_RX_HIGH_PRIORITY_MESSAGE = CAN_IE_HPME,
+	/** Timestamp Completed Interrupt Enable. */
+	CAN_TIMESTAMP_COMPLETE = CAN_IE_TCE,
+	/** Transmission Cancellation Finished Interrupt Enable. */
+	CAN_TX_CANCELLATION_FINISH = CAN_IE_TCFE,
+	/** Tx FIFO Empty Interrupt Enable. */
+	CAN_TX_FIFO_EMPTY = CAN_IE_TFEE,
+	/** Tx Event FIFO New Entry Interrupt Enable. */
+	CAN_TX_EVENT_FIFO_NEW_ENTRY = CAN_IE_TEFNE,
+	/** Tx Event FIFO Watermark Reached Interrupt Enable. */
+	CAN_TX_EVENT_FIFO_WATERMARK = CAN_IE_TEFWE,
+	/** Tx Event FIFO Full Interrupt Enable. */
+	CAN_TX_EVENT_FIFO_FULL = CAN_IE_TEFFE,
+	/** Tx Event FIFO Element Lost Interrupt Enable. */
+	CAN_TX_EVENT_FIFO_ELEMENT_LOST = CAN_IE_TEFLE,
+	/** Timestamp Wraparound Interrupt Enable. */
+	CAN_TIMESTAMP_WRAPAROUND = CAN_IE_TSWE,
+	/** Message RAM Access Failure Interrupt Enable. */
+	CAN_MESSAGE_RAM_ACCESS_FAILURE = CAN_IE_MRAFE,
+	/** Timeout Occurred Interrupt Enable. */
+	CAN_TIMEOUT_OCCURRED = CAN_IE_TOOE,
+	/** Message stored to Dedicated Rx Buffer Interrupt Enable. */
+	CAN_RX_BUFFER_NEW_MESSAGE = CAN_IE_DRXE,
+	/** Bit Error Corrected Interrupt Enable. */
+	CAN_BIT_ERROR_CORRECTED = CAN_IE_BECE,
+	/** Bit Error Uncorrected Interrupt Enable. */
+	CAN_BIT_ERROR_UNCORRECTED = CAN_IE_BEUE,
+	/** Error Logging Overflow Interrupt Enable. */
+	CAN_ERROR_LOGGING_OVERFLOW = CAN_IE_ELOE,
+	/** Error Passive Interrupt Enable. */
+	CAN_ERROR_PASSIVE = CAN_IE_EPE,
+	/** Warning Status Interrupt Enable. */
+	CAN_WARNING_STATUS = CAN_IE_EWE,
+	/** Bus_Off Status Interrupt Enable. */
+	CAN_BUS_OFF = CAN_IE_BOE,
+	/** Watchdog Interrupt Interrupt Enable. */
+	CAN_WATCHDOG = CAN_IE_WDIE,
+	/** Protocol Error in Arbitration Phase Enable. */
+	CAN_PROTOCOL_ERROR_ARBITRATION = CAN_IE_PEAE,
+	/** Protocol Error in Data Phase Enable. */
+	CAN_PROTOCOL_ERROR_DATA = CAN_IE_PEDE,
+	/** Access to Reserved Address Enable. */
+	CAN_ACCESS_RESERVED_ADDRESS = CAN_IE_ARAE,
+};
+
+/**
+ * \brief Enable CAN interrupt.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] source  Interrupt source type
+ */
+static inline void can_enable_interrupt(struct can_module *const module_inst,
+		const enum can_interrupt_source source)
+{
+	module_inst->hw->IE.reg |= source;
+}
+
+/**
+ * \brief Disable CAN interrupt.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] source  Interrupt source type
+ */
+static inline void can_disable_interrupt(struct can_module *const module_inst,
+		const enum can_interrupt_source source)
+{
+	module_inst->hw->IE.reg &= ~source;
+}
+
+/**
+ * \brief Get CAN interrupt status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ */
+static inline uint32_t can_read_interrupt_status(
+		struct can_module *const module_inst)
+{
+	return module_inst->hw->IR.reg;
+}
+
+/**
+ * \brief Clear CAN interrupt status.
+ *
+ * \param[in] module_inst  Pointer to the CAN software instance struct
+ * \param[in] source  Interrupt source type
+ *
+ * \return Bit mask of interrupt status value.
+ */
+static inline void can_clear_interrupt_status(
+		struct can_module *const module_inst,
+		const enum can_interrupt_source source)
+{
+	module_inst->hw->IR.reg = source;
+}
+
+/** @} */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_can_extra Extra Information for CAN Driver
+ *
+ * \section asfdoc_sam0_can_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>CAN</td>
+ *		<td>Control Area Network (CAN) Controller</td>
+ *	</tr>
+ *  <tr>
+ *		<td>CAN FD</td>
+ *		<td>CAN with Flexible Data-Rate</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_can_extra_dependencies Dependencies
+ * This driver has no dependencies.
+ *
+ *
+ * \section asfdoc_sam0_can_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_can_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+  *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_can_exqsg Examples for CAN Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_can_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_can_basic_use_case
+ *
+ *  - \subpage asfdoc_sam0_can_fd_use_case
+ *
+ * \page asfdoc_sam0_can_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>A</td>
+ *		<td>03/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* CAN_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/module_config/conf_can.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/module_config/conf_can.h
new file mode 100644
index 0000000000..c70c0b623a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/module_config/conf_can.h
@@ -0,0 +1,106 @@
+/**
+ * \file
+ *
+ * \brief SAM Control Area Network Driver Configuration Header
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_CAN_H_INCLUDED
+#define CONF_CAN_H_INCLUDED
+
+/*
+ * Below is the message RAM setting, it will be stored in the system RAM.
+ * Please adjust the message size according to your application.
+ */
+#define CONF_CAN0_RX_FIFO_0_NUM         16            /* Range: 1..64 */ 
+#define CONF_CAN0_RX_FIFO_1_NUM         16            /* Range: 1..64 */ 
+#define CONF_CAN0_RX_BUFFER_NUM         16            /* Range: 1..64 */ 
+#define CONF_CAN0_TX_BUFFER_NUM         4             /* Range: 1..16 */ 
+#define CONF_CAN0_TX_FIFO_QUEUE_NUM     4             /* Range: 1..16 */ 
+#define CONF_CAN0_TX_EVENT_FIFO         8             /* Range: 1..32 */ 
+
+#define CONF_CAN0_RX_STANDARD_ID_FILTER_NUM     32    /* Range: 1..128 */ 
+#define CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM     16    /* Range: 1..64 */ 
+
+#define CONF_CAN1_RX_FIFO_0_NUM         16            /* Range: 1..64 */ 
+#define CONF_CAN1_RX_FIFO_1_NUM         16            /* Range: 1..64 */ 
+#define CONF_CAN1_RX_BUFFER_NUM         16            /* Range: 1..64 */ 
+#define CONF_CAN1_TX_BUFFER_NUM         4             /* Range: 1..16 */ 
+#define CONF_CAN1_TX_FIFO_QUEUE_NUM     4             /* Range: 1..16 */ 
+#define CONF_CAN1_TX_EVENT_FIFO         8             /* Range: 1..32 */ 
+
+#define CONF_CAN1_RX_STANDARD_ID_FILTER_NUM     32    /* Range: 1..128 */ 
+#define CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM     16    /* Range: 1..64 */ 
+
+/* The value should be 8/12/16/20/24/32/48/64. */
+#define CONF_CAN_ELEMENT_DATA_SIZE         8
+
+/*
+ * The setting of the nominal bit rate is based on the GCLK_CAN is 48M which you can
+ * change in the conf_clock.h. Below is the default configuration. The
+ * time quanta is 48MHz / (5+1) =  8MHz. And each bit is (3+10+3) = 16 time
+ * quanta which means the bit rate is 8MHz / 16 = 500KHz.
+ */
+/* Nominal bit Baud Rate Prescaler */
+#define CONF_CAN_NBTP_NBRP_VALUE    5
+/* Nominal bit (Re)Synchronization Jump Width */
+#define CONF_CAN_NBTP_NSJW_VALUE    3
+/* Nominal bit Time segment before sample point */
+#define CONF_CAN_NBTP_NTSEG1_VALUE  10
+/* Nominal bit Time segment after sample point */
+#define CONF_CAN_NBTP_NTSEG2_VALUE  3
+
+/*
+ * The setting of the data bit rate is based on the GCLK_CAN is 48M which you can
+ * change in the conf_clock.h. Below is the default configuration. The
+ * time quanta is 48MHz / (5+1) =  8MHz. And each bit is (3+10+3) = 16 time
+ * quanta which means the bit rate is 8MHz / 16 = 500KHz.
+ */
+/* Data bit Baud Rate Prescaler */
+#define CONF_CAN_DBTP_DBRP_VALUE    5
+/* Data bit (Re)Synchronization Jump Width */
+#define CONF_CAN_DBTP_DSJW_VALUE    3
+/* Data bit Time segment before sample point */
+#define CONF_CAN_DBTP_DTSEG1_VALUE  10
+/* Data bit Time segment after sample point */
+#define CONF_CAN_DBTP_DTSEG2_VALUE  3
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.c
new file mode 100644
index 0000000000..abcf7d6c3e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.c
@@ -0,0 +1,154 @@
+/**
+ * \file
+ *
+ * \brief SAM Configurable Custom Logic (CCL) Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "ccl.h"
+
+void ccl_init(struct ccl_config *const config)
+{
+#if (SAML22) || (SAMC20) || (SAMC21)
+	/* Turn on the digital interface clock. */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_CCL);
+#else
+	/* Turn on the digital interface clock. */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_CCL);
+#endif
+	/* Reset module. */
+	ccl_module_reset();
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(CCL_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(CCL_GCLK_ID);
+
+	if(config->run_in_standby) {
+		/* Enable run in standy mode. */
+		CCL->CTRL.reg |= CCL_CTRL_RUNSTDBY;
+	} else {
+		/* Disable run in standy mode. */
+		CCL->CTRL.reg &= ~ CCL_CTRL_RUNSTDBY;
+	}
+}
+
+void ccl_lut_get_config_defaults(struct ccl_lut_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->truth_table_value = 0x00;
+	config->event_output_enable = false;
+	config->event_input_enable = false;
+	config->event_input_inverted_enable = false;
+	config->input0_src_sel = CCL_LUT_INPUT_SRC_MASK;
+	config->input1_src_sel = CCL_LUT_INPUT_SRC_MASK;
+	config->input2_src_sel = CCL_LUT_INPUT_SRC_MASK;
+	config->edge_selection_enable = false;
+	config->filter_sel = CCL_LUT_FILTER_DISABLE;
+}
+
+enum status_code ccl_lut_set_config(const enum ccl_lut_id number,
+		struct ccl_lut_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	uint32_t temp = 0;
+
+	if(CCL->CTRL.reg & CCL_CTRL_ENABLE)
+		return STATUS_BUSY;
+
+	if (config->event_output_enable) {
+		temp |= CCL_LUTCTRL_LUTEO;
+	}
+
+	if (config->event_input_enable) {
+		temp |= CCL_LUTCTRL_LUTEI;
+	}
+
+	if (config->event_input_inverted_enable) {
+		temp |= CCL_LUTCTRL_INVEI;
+	}
+
+	if (config->edge_selection_enable) {
+		temp |= CCL_LUTCTRL_EDGESEL;
+	}
+
+	CCL->LUTCTRL[number].reg = temp |
+		CCL_LUTCTRL_INSEL0(config->input0_src_sel) |
+		CCL_LUTCTRL_INSEL1(config->input1_src_sel) |
+		CCL_LUTCTRL_INSEL2(config->input2_src_sel) |
+		CCL_LUTCTRL_TRUTH(config->truth_table_value) |
+		config->filter_sel;
+
+	return STATUS_OK;
+}
+
+enum status_code ccl_seq_config(const enum ccl_seq_id number,
+		const enum ccl_seq_selection seq_selection)
+{
+	if(CCL->CTRL.reg & CCL_CTRL_ENABLE)
+		return STATUS_BUSY;
+
+	CCL->SEQCTRL[number].reg = seq_selection;
+
+	return STATUS_OK;
+}
+
+void ccl_lut_enable(const enum ccl_lut_id number)
+{
+	/* Enable the LUTx */
+	CCL->LUTCTRL[number].reg |= CCL_LUTCTRL_ENABLE;
+}
+
+void ccl_lut_disable(const enum ccl_lut_id number)
+{
+	/* Disable the LUTx */
+	CCL->LUTCTRL[number].reg &= ~CCL_LUTCTRL_ENABLE;
+}
+
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.h
new file mode 100644
index 0000000000..b9294edd53
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.h
@@ -0,0 +1,494 @@
+/**
+ * \file
+ *
+ * \brief SAM Configurable Custom Logic (CCL) Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CCL_H_INCLUDED
+#define CCL_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_ccl_group SAM Configurable Custom Logic (CCL) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Configurable Custom Logic functionality.
+ *
+ * The following peripheral is used by this module:
+ *  - CCL (Configurable Custom Logic)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM C20/C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_ccl_prerequisites
+ *  - \ref asfdoc_sam0_ccl_module_overview
+ *  - \ref asfdoc_sam0_ccl_special_considerations
+ *  - \ref asfdoc_sam0_ccl_extra_info
+ *  - \ref asfdoc_sam0_ccl_examples
+ *  - \ref asfdoc_sam0_ccl_api_overview
+ *
+ *
+ * \section asfdoc_sam0_ccl_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_ccl_module_overview Module Overview
+ *
+ * This driver provides an interface for the Configurable Custom Logic
+ * functions on the device.
+ *
+ * The Configurable Custom Logic (CCL) contains programmable logic
+ * which can be connected to the device pins, events, or internal peripherals.
+ *
+ * Each LUT consists of three inputs, a truth table and optional synchronizer,
+ * filter and edge detector. Each LUT can generate an output as a user programmable
+ * logic expression with three inputs.
+ *
+ * The output can be combinatorially generated from the inputs, or filtered to remove spike.
+ * An optional sequential module can be enabled. The inputs of sequential module are
+ * individually controlled by two independent, adjacent LUT(LUT0/LUT1, LUT2/LUT3 etc.) outputs,
+ * enabling complex waveform generation.
+ *
+ * \section asfdoc_sam0_ccl_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_ccl_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_ccl_extra. This includes:
+ *  - \ref asfdoc_sam0_ccl_extra_acronyms
+ *  - \ref asfdoc_sam0_ccl_extra_dependencies
+ *  - \ref asfdoc_sam0_ccl_extra_errata
+ *  - \ref asfdoc_sam0_ccl_extra_history
+ *
+ *
+ * \section asfdoc_sam0_ccl_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_ccl_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_ccl_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief CCL LUT(look up table) ID number enum.
+ */
+enum ccl_lut_id {
+	/** CCL LUT 0 */
+	CCL_LUT_0 = 0,
+	/** CCL LUT 1 */
+	CCL_LUT_1 = 1,
+	/** CCL LUT 2 */
+	CCL_LUT_2 = 2,
+	/** CCL LUT 3 */
+	CCL_LUT_3 = 3,
+};
+
+/**
+ * \brief CCL sequential module ID number enum.
+ */
+enum ccl_seq_id {
+	/** CCL SEQ 0 */
+	CCL_SEQ_0 = 0,
+	/** CCL SEQ 1 */
+	CCL_SEQ_1 = 1,
+};
+
+/**
+ * \brief Sequential selection enum.
+ *
+ * Enum for the sequential selection configuration.
+ */
+enum ccl_seq_selection {
+	/** Sequential logic is disabled */
+	CCL_SEQ_DISABLED = CCL_SEQCTRL_SEQSEL_DISABLE,
+	/** D flip flop */
+	CCL_SEQ_D_FLIP_FLOP = CCL_SEQCTRL_SEQSEL_DFF,
+	/** JK flip flop */
+	CCL_SEQ_JK_FLIP_FLOP = CCL_SEQCTRL_SEQSEL_JK,
+	/** D latch */
+	CCL_SEQ_D_LATCH = CCL_SEQCTRL_SEQSEL_LATCH,
+	/** RS latch */
+	CCL_SEQ_RS_LATCH = CCL_SEQCTRL_SEQSEL_RS,
+};
+
+/**
+ * \brief LUT Input source selection configuration enum.
+ *
+ * Enum for the LUT Input source selection.
+ */
+enum ccl_lut_input_src_sel {
+	/** Masked input */
+	CCL_LUT_INPUT_SRC_MASK = 0,
+	/** Feedback input source */
+	CCL_LUT_INPUT_SRC_FEEDBACK = 1,
+	/** Linked LUT input source */
+	CCL_LUT_INPUT_SRC_LINK = 2,
+	/** Event input source */
+	CCL_LUT_INPUT_SRC_EVENT = 3,
+	/** I/O pin input source */
+	CCL_LUT_INPUT_SRC_IO = 4,
+	/** AC input source */
+	CCL_LUT_INPUT_SRC_AC = 5,
+	/** TC input source */
+	CCL_LUT_INPUT_SRC_TC = 6,
+	/** Alternative TC input source */
+	CCL_LUT_INPUT_SRC_ALTTC = 7,
+	/** TCC input source */
+	CCL_LUT_INPUT_SRC_TCC = 8,
+	/** SERCOM input source */
+	CCL_LUT_INPUT_SRC_SERCOM = 9,
+};
+
+/**
+ * \brief Select the LUT output filter options enum.
+ *
+ * Enum for the LUT output filter options.
+ */
+enum ccl_lut_filter_sel {
+	/** Filter disabled */
+	CCL_LUT_FILTER_DISABLE = CCL_LUTCTRL_FILTSEL_DISABLE,
+	/** Synchronizer enabled */
+	CCL_LUT_FILTER_SYNC = CCL_LUTCTRL_FILTSEL_SYNCH,
+	/** Filter enabled */
+	CCL_LUT_FILTER_ENABLE = CCL_LUTCTRL_FILTSEL_FILTER,
+};
+
+/**
+ * \brief CCL module configuration structure.
+ *
+ *  Configuration structure for CCL module.
+ */
+struct ccl_config {
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+	/** If \c true, the GCLK_CCL clock will not stop in standby sleep mode */
+	bool run_in_standby;
+};
+
+/**
+ * \brief CCL LUT 0 to 3 configuration structure.
+ *
+ *  Configuration structure for CCL LUT 0 to 3.
+ */
+struct ccl_lut_config {
+	/**  The value of truth logic as a function of inputs IN[2:0] */
+	uint8_t truth_table_value;
+	/** If \c true, LUT event output is enabled */
+	bool event_output_enable;
+	/** If \c true, LUT incoming event is enabled */
+	bool event_input_enable;
+	/** If \c true, incoming event is inverted */
+	bool event_input_inverted_enable;
+	/** Selection of the input0 source */
+	enum ccl_lut_input_src_sel input0_src_sel;
+	/** Selection of the input1 source */
+	enum ccl_lut_input_src_sel input1_src_sel;
+	/** Selection of the input2 source */
+	enum ccl_lut_input_src_sel input2_src_sel;
+	/** If \c true, Edge detector is enabled */
+	bool edge_selection_enable;
+	/**  Selection of the LUT output filter options */
+	enum ccl_lut_filter_sel filter_sel;
+};
+
+/**
+ * \name Initialize and Reset CCL Module
+ * @{
+ */
+
+/**
+ * \brief Initializes CCL module.
+ *
+ * Resets all registers in the MODULE to their initial state,
+ * and then enable the module.
+ */
+void ccl_init(struct ccl_config *const config);
+
+/**
+ * \brief Initializes all members of a CCL configuration structure
+ *  to safe defaults.
+ *
+ *  Initializes all members of a given Configurable Custom Logic configuration
+ *  structure to safe and known default values. This function should be called on
+ *  all new instances of these configuration structures before being modified
+ *  by the user application.
+ *
+ *  The default configuration is as follows:
+ *   \li GCLK_CLL will be stopped in standby sleep mode
+ *   \li Generator 0 is the default GCLK generator
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void ccl_get_config_defaults(
+		struct ccl_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	config->clock_source = GCLK_GENERATOR_0;
+	/* Default configuration values */
+	config->run_in_standby = false;
+}
+
+/**
+ * \brief Resets CCL module.
+ *
+ * Resets all registers in the MODULE to their initial state,
+ * and the CCL will be disabled.
+ */
+static inline void ccl_module_reset(void)
+{
+	/* Reset CCL. */
+	CCL->CTRL.reg |= CCL_CTRL_SWRST;
+
+	while((CCL->CTRL.reg & CCL_CTRL_SWRST));
+}
+/** @} */
+
+/**
+ * \name Enable and Disable CCL Module
+ * @{
+ */
+
+/**
+ * \brief Enables CCL module.
+ *
+ * Enable the peripheral.
+ *
+ */
+static inline void ccl_module_enable(void)
+{
+	/* Enable CCL. */
+	CCL->CTRL.reg |= CCL_CTRL_ENABLE;
+}
+
+/**
+ * \brief Disables CCL module.
+ *
+ * Disables the peripheral.
+ */
+static inline void ccl_module_disable(void)
+{
+	/* Disable CCL. */
+	CCL->CTRL.reg &= ~CCL_CTRL_ENABLE;
+}
+
+/** @} */
+
+/**
+ * \name Configure LUT
+ * @{
+ */
+
+/**
+ *  \brief Writes sequential selection to the hardware module.
+ *
+ *  Writes a given sequential selection configuration to the hardware module.
+ *
+ *  \note This function can only be used when the CCL module is disabled.
+ *
+ *  \param[in] seq_selection       Enum for the sequential selection configuration
+ *  \param[in] number     SEQ unit number to config
+ */
+enum status_code ccl_seq_config(const enum ccl_seq_id number,
+		const enum ccl_seq_selection seq_selection);
+
+/**
+ * \brief Initializes all members of LUT configuration
+ * structure to safe defaults.
+ *
+ *  Initializes all members of LUT configuration
+ *  structure to safe defaults. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Truth table value is 0x00
+ *   \li LUT event output is disabled
+ *   \li LUT incoming event is disabled
+ *   \li LUT incoming event is not inverted
+ *   \li The input IN[2:0] source is masked
+ *   \li The edge detector is disabled
+ *   \li The LUT output filter is disabled
+ *
+ *  \param[out] config  LUT configuration structure to initialize to
+ *                       default values
+ */
+void ccl_lut_get_config_defaults(struct ccl_lut_config *const config);
+
+/** \brief Writes LUT configuration to the hardware module.
+ *
+ *  Writes a given LUT configuration to the hardware  module.
+ *
+ *  \note This function can only be used when the CCL module is disabled.
+ *
+ *  \param[in] config       Pointer to the LUT configuration struct
+ *  \param[in] number     LUT number to config
+ */
+enum status_code ccl_lut_set_config(const enum ccl_lut_id number,
+		struct ccl_lut_config *const config);
+/** @} */
+
+/**
+ * \name Enable and Disable LUT
+ * @{
+ */
+
+/**
+ * \brief Enables an LUT that was previously configured.
+ *
+ *  Enables an LUT that was previously configured via a call to
+ *  \ref ccl_lut_set_config function.
+ *
+ *  \param[in] number      LUT number to enable
+ */
+void ccl_lut_enable(const enum ccl_lut_id number);
+
+/**
+ * \brief Disables an LUT that was previously enabled.
+ *
+ *  Disables an LUT that was previously enabled via a call to
+ *  \ref ccl_lut_enable().
+ *
+ *  \param[in] number      LUT number to enable
+ */
+void ccl_lut_disable(const enum ccl_lut_id number);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_ccl_extra Extra Information for CCL Driver
+ *
+ * \section asfdoc_sam0_ccl_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>CCL</td>
+ *		<td>Configurable Custom Logic</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_ccl_extra_dependencies Dependencies
+ * This driver has no dependencies.
+ *
+ *
+ * \section asfdoc_sam0_ccl_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_ccl_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+  *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_ccl_exqsg Examples for CCL Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_ccl_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_ccl_basic_use_case
+ *
+ * \page asfdoc_sam0_ccl_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42448B</td>
+ *		<td>08/2015</td>
+ *		<td>Add support for SAM L22</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42448A</td>
+ *		<td>06/2015</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* CCL_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac.h
new file mode 100644
index 0000000000..1841b2fd0c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac.h
@@ -0,0 +1,207 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Digital-to-Analog Converter Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DAC_H_INCLUDED
+#define DAC_H_INCLUDED
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+
+/**
+ * \addtogroup asfdoc_sam0_dac_group
+ *
+ * @{
+ */
+
+/**
+ * Define DAC features set according to different device families.
+ * @{
+ */
+#if (SAMD21 || SAMD10 || SAMD11 || SAMDA1 || SAMHA1)
+#  define FEATURE_DAC_DATABUF_WRITE_PROTECTION
+#endif
+/**@}*/
+
+#ifndef DAC_TIMEOUT
+#  define DAC_TIMEOUT 0xFFFF
+#endif
+
+#if DAC_CALLBACK_MODE == true
+#  include <system_interrupt.h>
+
+/** Forward definition of the device instance. */
+struct dac_module;
+
+#if !defined(__DOXYGEN__)
+extern struct dac_module *_dac_instances[DAC_INST_NUM];
+#endif
+
+/** Type definition for a DAC module callback function. */
+typedef void (*dac_callback_t)(uint8_t channel);
+
+/** Enum for the possible callback types for the DAC module. */
+enum dac_callback {
+	/** Callback type for when a DAC channel data empty condition occurs
+	 *  (requires event triggered mode) */
+	DAC_CALLBACK_DATA_EMPTY,
+
+	/** Callback type for when a DAC channel data underrun condition occurs
+	 *  (requires event triggered mode) */
+	DAC_CALLBACK_DATA_UNDERRUN,
+
+	/** Callback type for when a DAC channel write buffer job complete (requires
+	 *  event triggered mode) */
+	DAC_CALLBACK_TRANSFER_COMPLETE,
+#if !defined(__DOXYGEN__)
+	DAC_CALLBACK_N,
+#endif
+};
+
+#endif
+
+#include <dac_feature.h>
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+bool dac_is_syncing(
+		struct dac_module *const dev_inst);
+
+void dac_get_config_defaults(
+		struct dac_config *const config);
+
+enum status_code dac_init(
+		struct dac_module *const dev_inst,
+		Dac *const module,
+		struct dac_config *const config);
+
+void dac_reset(
+		struct dac_module *const dev_inst);
+
+void dac_enable(
+		struct dac_module *const dev_inst);
+
+void dac_disable(
+		struct dac_module *const dev_inst);
+
+void dac_enable_events(
+		struct dac_module *const module_inst,
+		struct dac_events *const events);
+
+void dac_disable_events(
+		struct dac_module *const module_inst,
+		struct dac_events *const events);
+
+/** @} */
+
+/**
+ * \name Configuration and Initialization (Channel)
+ * @{
+ */
+
+void dac_chan_get_config_defaults(
+		struct dac_chan_config *const config);
+
+void dac_chan_set_config(
+		struct dac_module *const dev_inst,
+		const enum dac_channel channel,
+		struct dac_chan_config *const config);
+
+void dac_chan_enable(
+		struct dac_module *const dev_inst,
+		enum dac_channel channel);
+
+void dac_chan_disable(
+		struct dac_module *const dev_inst,
+		enum dac_channel channel);
+
+/** @} */
+
+/**
+ * \name Channel Data Management
+ * @{
+ */
+
+enum status_code dac_chan_write(
+		struct dac_module *const dev_inst,
+		enum dac_channel channel,
+		const uint16_t data);
+
+enum status_code dac_chan_write_buffer_wait(
+		struct dac_module *const module_inst,
+		enum dac_channel channel,
+		uint16_t *buffer,
+		uint32_t length);
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+uint32_t dac_get_status(
+		struct dac_module *const module_inst);
+void dac_clear_status(
+		struct dac_module *const module_inst,
+		uint32_t status_flags);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+
+#endif /* DAC_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_callback.h
new file mode 100644
index 0000000000..0de73056b0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_callback.h
@@ -0,0 +1,119 @@
+/**
+ * \file
+ *
+ * \brief SAM Digital-to-Analog Interrupt Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DAC_CALLBACK_H_INCLUDED
+#define DAC_CALLBACK_H_INCLUDED
+
+#include <compiler.h>
+#include "dac.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_dac_group
+ *
+ * @{
+ */
+
+/** \name Callback Configuration and Initialization
+ * @{
+ */
+enum status_code dac_chan_write_buffer_job(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		uint16_t *buffer,
+		uint32_t buffer_size);
+
+enum status_code dac_chan_write_job(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		uint16_t data);
+
+enum status_code dac_register_callback(
+		struct dac_module *const module,
+		const enum dac_channel channel,
+		const dac_callback_t callback,
+		const enum dac_callback type);
+
+enum status_code dac_unregister_callback(
+		struct dac_module *const module,
+		const enum dac_channel channel,
+		const enum dac_callback type);
+
+/** @} */
+
+/** \name Callback Enabling and Disabling (Channel)
+ * @{
+ */
+
+enum status_code dac_chan_enable_callback(
+		struct dac_module *const module,
+		const enum dac_channel channel,
+		const enum dac_callback type);
+
+enum status_code dac_chan_disable_callback(
+		struct dac_module *const module,
+		const enum dac_channel channel,
+		const enum dac_callback type);
+
+enum status_code dac_chan_get_job_status(
+		struct dac_module *module_inst,
+		const enum dac_channel channel);
+
+void dac_chan_abort_job(
+		struct dac_module *module_inst,
+		const enum dac_channel channel);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac.c
new file mode 100644
index 0000000000..aa73badd3a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac.c
@@ -0,0 +1,779 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Digital-to-Analog Converter Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "dac.h"
+#include <system.h>
+#include <pinmux.h>
+
+/**
+ * \internal Writes a DAC configuration to the hardware module.
+ *
+ * Writes out a given configuration to the hardware module.
+ *
+ * \param[out] module_inst  Pointer to the DAC software instance struct
+ * \param[in]  config       Pointer to the configuration struct
+ *
+ */
+static void _dac_set_config(
+		struct dac_module *const module_inst,
+		struct dac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(config);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Set selected DAC output to be enabled when enabling the module */
+	module_inst->output = config->output;
+	module_inst->start_on_event = false;
+
+	uint32_t new_ctrla = 0;
+	uint32_t new_ctrlb = 0;
+
+	/* Enable DAC in standby sleep mode if configured */
+	if (config->run_in_standby) {
+		new_ctrla |= DAC_CTRLA_RUNSTDBY;
+	}
+
+	/* Set reference voltage */
+	new_ctrlb |= config->reference;
+
+	/* Left adjust data if configured */
+	if (config->left_adjust) {
+		new_ctrlb |= DAC_CTRLB_LEFTADJ;
+	}
+
+#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
+	/* Bypass DATABUF write protection if configured */
+	if (config->databuf_protection_bypass) {
+		new_ctrlb |= DAC_CTRLB_BDWP;
+	}
+#endif
+
+	/* Voltage pump disable if configured */
+	if (config->voltage_pump_disable) {
+		new_ctrlb |= DAC_CTRLB_VPD;
+	}
+
+	/* Apply the new configuration to the hardware module */
+	dac_module->CTRLA.reg = new_ctrla;
+
+	while (dac_is_syncing(module_inst)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	dac_module->CTRLB.reg = new_ctrlb;
+}
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] dev_inst  Pointer to the DAC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+bool dac_is_syncing(
+		struct dac_module *const dev_inst)
+{
+	/* Sanity check arguments */
+	Assert(dev_inst);
+
+	Dac *const dac_module = dev_inst->hw;
+
+#if (SAMC21)
+	if (dac_module->SYNCBUSY.reg) {
+#else
+	if (dac_module->STATUS.reg & DAC_STATUS_SYNCBUSY) {
+#endif
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Initializes a DAC configuration structure to defaults.
+ *
+ *  Initializes a given DAC configuration structure to a set of
+ *  known default values. This function should be called on any new
+ *  instance of the configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li 1V from internal bandgap reference
+ *   \li Drive the DAC output to the VOUT pin
+ *   \li Right adjust data
+ *   \li GCLK generator 0 (GCLK main) clock source
+ *   \li The output buffer is disabled when the chip enters STANDBY sleep
+ *       mode
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void dac_get_config_defaults(
+		struct dac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->reference      = DAC_REFERENCE_INT1V;
+	config->output         = DAC_OUTPUT_EXTERNAL;
+	config->left_adjust    = false;
+#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
+	config->databuf_protection_bypass = false;
+#endif
+	config->voltage_pump_disable = false;
+	config->clock_source   = GCLK_GENERATOR_0;
+	config->run_in_standby = false;
+#if (SAMC21)
+	config->dither_mode    = false;
+#endif
+}
+
+/**
+ * \brief Initialize the DAC device struct.
+ *
+ * Use this function to initialize the Digital to Analog Converter. Resets the
+ * underlying hardware module and configures it.
+ *
+ * \note The DAC channel must be configured separately.
+ *
+ * \param[out] module_inst  Pointer to the DAC software instance struct
+ * \param[in]  module       Pointer to the DAC module instance
+ * \param[in]  config       Pointer to the config struct, created by the user
+ *                          application
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK          Module initiated correctly
+ * \retval STATUS_ERR_DENIED  If module is enabled
+ * \retval STATUS_BUSY        If module is busy resetting
+ */
+enum status_code dac_init(
+		struct dac_module *const module_inst,
+		Dac *const module,
+		struct dac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module);
+	Assert(config);
+
+	/* Initialize device instance */
+	module_inst->hw = module;
+
+	/* Turn on the digital interface clock */
+#if (SAMC21)
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC);
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_DAC);
+#endif
+
+	/* Check if module is enabled. */
+	if (module->CTRLA.reg & DAC_CTRLA_ENABLE) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if reset is in progress. */
+	if (module->CTRLA.reg & DAC_CTRLA_SWRST) {
+		return STATUS_BUSY;
+	}
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(DAC_GCLK_ID);
+
+	/* MUX the DAC VOUT pin */
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+
+	/* Set up the DAC VOUT pin */
+	pin_conf.mux_position = MUX_PA02B_DAC_VOUT;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pin_conf.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+	system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT, &pin_conf);
+
+	/* Write configuration to module */
+	_dac_set_config(module_inst, config);
+
+	/* Store reference selection for later use */
+	module_inst->reference = config->reference;
+
+#if DAC_CALLBACK_MODE == true
+	for (uint8_t i = 0; i < DAC_CALLBACK_N; i++) {
+		module_inst->callback[i] = NULL;
+	};
+
+	_dac_instances[0] = module_inst;
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Resets the DAC module.
+ *
+ * This function will reset the DAC module to its power on default values and
+ * disable it.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ */
+void dac_reset(
+		struct dac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	while (dac_is_syncing(module_inst)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Software reset the module */
+	dac_module->CTRLA.reg |= DAC_CTRLA_SWRST;
+}
+
+/**
+ * \brief Enable the DAC module.
+ *
+ * Enables the DAC interface and the selected output. If any internal reference
+ * is selected it will be enabled.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ *
+ */
+void dac_enable(
+		struct dac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Enable selected output */
+	dac_module->CTRLB.reg |= module_inst->output;
+
+	while (dac_is_syncing(module_inst)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Enable the module */
+	dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE;
+
+	/* Enable internal bandgap reference if selected in the configuration */
+	if (module_inst->reference == DAC_REFERENCE_INT1V) {
+#if (SAMC21)
+		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
+	}
+
+	if(dac_module->CTRLA.reg & DAC_CTRLA_ENABLE) {
+		while(! (dac_module->STATUS.reg & DAC_STATUS_READY)) {
+		};
+	}
+#else
+		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
+	}
+
+#endif
+}
+
+/**
+ * \brief Disable the DAC module.
+ *
+ * Disables the DAC interface and the output buffer.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ *
+ */
+void dac_disable(
+		struct dac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Wait until the synchronization is complete */
+	while (dac_is_syncing(module_inst)) {
+	};
+
+	/* Disbale interrupt */
+	dac_module->INTENCLR.reg = DAC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	dac_module->INTFLAG.reg = DAC_INTFLAG_MASK;
+
+	/* Disable DAC */
+	dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Enables a DAC event input or output.
+ *
+ *  Enables one or more input or output events to or from the DAC module. See
+ *  \ref dac_events "dac_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the DAC peripheral
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+void dac_enable_events(
+		struct dac_module *const module_inst,
+		struct dac_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+#if(SAMC21)
+	/* Configure Enable Inversion of input event */
+	if (events->generate_event_on_chan_falling_edge) {
+		event_mask |= DAC_EVCTRL_INVEI;
+	}
+#endif
+
+	/* Configure Buffer Empty event */
+	if (events->generate_event_on_buffer_empty) {
+		event_mask |= DAC_EVCTRL_EMPTYEO;
+	}
+
+	/* Configure Conversion Start event */
+	if (events->on_event_start_conversion) {
+		event_mask |= DAC_EVCTRL_STARTEI;
+		module_inst->start_on_event = true;
+	}
+
+	dac_module->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables a DAC event input or output.
+ *
+ *  Disables one or more input or output events to or from the DAC module. See
+ *  \ref dac_events "dac_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the DAC peripheral
+ *  \param[in] events       Struct containing flags of events to disable
+ */
+void dac_disable_events(
+		struct dac_module *const module_inst,
+		struct dac_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Buffer Empty event */
+	if (events->generate_event_on_buffer_empty) {
+		event_mask |= DAC_EVCTRL_EMPTYEO;
+	}
+
+	/* Configure Conversion Start event */
+	if (events->on_event_start_conversion) {
+		event_mask |= DAC_EVCTRL_STARTEI;
+		module_inst->start_on_event = false;
+	}
+
+	dac_module->EVCTRL.reg &= ~event_mask;
+}
+
+/**
+ * \brief Initializes a DAC channel configuration structure to defaults.
+ *
+ * Initializes a given DAC channel configuration structure to a set of
+ * known default values. This function should be called on any new
+ * instance of the configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Start Conversion Event Input enabled
+ *  \li Start Data Buffer Empty Event Output disabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void dac_chan_get_config_defaults(
+		struct dac_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+}
+
+/**
+ * \brief Writes a DAC channel configuration to the hardware module.
+ *
+ * Writes a given channel configuration to the hardware module.
+ *
+ * \note The DAC device instance structure must be initialized before calling
+ *       this function.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      Channel to configure
+ * \param[in] config       Pointer to the configuration struct
+ *
+ */
+void dac_chan_set_config(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		struct dac_chan_config *const config)
+{
+	/* No channel support yet */
+	UNUSED(channel);
+}
+
+/**
+ * \brief Enable a DAC channel.
+ *
+ * Enables the selected DAC channel.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      Channel to enable
+ *
+ */
+void dac_chan_enable(
+		struct dac_module *const module_inst,
+		enum dac_channel channel)
+{
+	/* No channel support yet */
+	UNUSED(channel);
+}
+
+/**
+ * \brief Disable a DAC channel.
+ *
+ * Disables the selected DAC channel.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      Channel to disable
+ *
+ */
+void dac_chan_disable(
+		struct dac_module *const module_inst,
+		enum dac_channel channel)
+{
+	/* No channel support yet */
+	UNUSED(channel);
+}
+
+/**
+ * \brief Enable the output buffer.
+ *
+ * Enables the output buffer and drives the DAC output to the VOUT pin.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      DAC channel to alter
+ */
+void dac_chan_enable_output_buffer(
+		struct dac_module *const module_inst,
+		enum dac_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* No channel support yet */
+	UNUSED(channel);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Enable output buffer */
+	dac_module->CTRLB.reg |= DAC_OUTPUT_EXTERNAL;
+}
+
+/**
+ * \brief Disable the output buffer.
+ *
+ * Disables the output buffer.
+ *
+ * \note The output buffer(s) should be disabled when a channel's output is not
+ *       currently needed, as it will draw current even if the system is in
+ *       sleep mode.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      DAC channel to alter
+ */
+void dac_chan_disable_output_buffer(
+		struct dac_module *const module_inst,
+		enum dac_channel channel)
+{
+	/* Sanity check arguments*/
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* No channel support yet */
+	UNUSED(channel);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Disable output buffer */
+	dac_module->CTRLB.reg &= ~DAC_OUTPUT_EXTERNAL;
+}
+
+/**
+ * \brief Write to the DAC.
+ *
+ * This function writes to the DATA or DATABUF register.
+ * If the conversion is not event-triggered, the data will be written to
+ * the DATA register and the conversion will start.
+ * If the conversion is event-triggered, the data will be written to DATABUF
+ * and transferred to the DATA register and converted when a Start Conversion
+ * Event is issued.
+ * Conversion data must be right or left adjusted according to configuration
+ * settings.
+ * \note To be event triggered, the enable_start_on_event must be
+ * enabled in the configuration.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] channel          DAC channel to write to
+ * \param[in] data             Conversion data
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK           If the data was written
+ */
+enum status_code dac_chan_write(
+		struct dac_module *const module_inst,
+		enum dac_channel channel,
+		const uint16_t data)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* No channel support yet */
+	UNUSED(channel);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Wait until the synchronization is complete */
+	while (dac_is_syncing(module_inst)) {
+	};
+
+	if (module_inst->start_on_event) {
+		/* Write the new value to the buffered DAC data register */
+		dac_module->DATABUF.reg = data;
+	} else {
+		/* Write the new value to the DAC data register */
+		dac_module->DATA.reg = data;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Write to the DAC.
+ *
+ * This function converts a specific number of digital data.
+ * The conversion should be event-triggered, the data will be written to DATABUF
+ * and transferred to the DATA register and converted when a Start Conversion
+ * Event is issued.
+ * Conversion data must be right or left adjusted according to configuration
+ * settings.
+ * \note To be event triggered, the enable_start_on_event must be
+ * enabled in the configuration.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] channel          DAC channel to write to
+ * \param[in] buffer           Pointer to the digital data write buffer to be converted
+ * \param[in] length           Length of the write buffer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK           If the data was written or no data conversion required
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  The DAC is not configured as using event trigger
+ * \retval STATUS_BUSY                 The DAC is busy to convert
+ */
+enum status_code dac_chan_write_buffer_wait(
+		struct dac_module *const module_inst,
+		enum dac_channel channel,
+		uint16_t *buffer,
+		uint32_t length)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* No channel support yet */
+	UNUSED(channel);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Wait until the synchronization is complete */
+	while (dac_is_syncing(module_inst)) {
+	};
+
+	/* Zero length request */
+	if (length == 0) {
+		/* No data to be converted */
+		return STATUS_OK;
+	}
+
+#if DAC_CALLBACK_MODE == true
+	/* Check if busy */
+	if (module_inst->job_status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Only support event triggered conversion */
+	if (module_inst->start_on_event == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Blocks while buffer is being transferred */
+	while (length--) {
+		/* Convert one data */
+		dac_chan_write(module_inst, channel, buffer[length]);
+
+		/* Wait until Transmit is complete or timeout */
+		for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) {
+			if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY) {
+				break;
+			} else if (i == DAC_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the current module status
+ *
+ * Checks the status of the module and returns it as a bitmask of status
+ * flags.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ *
+ * \return Bitmask of status flags.
+ *
+ * \retval DAC_STATUS_CHANNEL_0_EMPTY    Data has been transferred from DATABUF
+ *                                       to DATA by a start conversion event
+ *                                       and DATABUF is ready for new data
+ * \retval DAC_STATUS_CHANNEL_0_UNDERRUN A start conversion event has occurred
+ *                                       when DATABUF is empty
+ *
+ */
+uint32_t dac_get_status(
+		struct dac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint8_t intflags = dac_module->INTFLAG.reg;
+	uint32_t status_flags = 0;
+
+	if (intflags & DAC_INTFLAG_EMPTY) {
+		status_flags |= DAC_STATUS_CHANNEL_0_EMPTY;
+	}
+
+	if (intflags & DAC_INTFLAG_UNDERRUN) {
+		status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] status_flags     Bit mask of status flags to clear
+ *
+ */
+void dac_clear_status(
+		struct dac_module *const module_inst,
+		uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint32_t intflags = 0;
+
+	if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) {
+		intflags |= DAC_INTFLAG_EMPTY;
+	}
+
+	if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) {
+		intflags |= DAC_INTFLAG_UNDERRUN;
+	}
+
+	dac_module->INTFLAG.reg = intflags;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_callback.c
new file mode 100644
index 0000000000..24542cc74b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_callback.c
@@ -0,0 +1,435 @@
+/**
+ * \file
+ *
+ * \brief SAM Digital-to-Analog Interrupt Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "dac.h"
+#include "dac_callback.h"
+
+struct dac_module *_dac_instances[DAC_INST_NUM];
+
+/**
+ * \brief Convert a specific number digital data to analog through DAC.
+ *
+ * This function will perform a conversion of specific number of digital data.
+ * The conversion should be event-triggered, the data will be written to DATABUF
+ * and transferred to the DATA register and converted when a Start Conversion
+ * Event is issued.
+ * Conversion data must be right or left adjusted according to configuration
+ * settings.
+ * \note To be event triggered, the enable_start_on_event must be
+ * enabled in the configuration.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] channel          DAC channel to write to
+ * \param[in] buffer             Pointer to the digital data write buffer to be converted
+ * \param[in] length             Size of the write buffer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK           If the data was written
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ * \retval STATUS_BUSY      The DAC is busy to accept new job
+ */
+enum status_code dac_chan_write_buffer_job(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		uint16_t *buffer,
+		uint32_t length)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(buffer);
+
+	UNUSED(channel);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if(module_inst->remaining_conversions != 0 ||
+			module_inst->job_status == STATUS_BUSY){
+		return STATUS_BUSY;
+	}
+
+	/* Wait until the synchronization is complete */
+	while (dac_is_syncing(module_inst)) {
+	};
+
+	module_inst->job_status = STATUS_BUSY;
+
+	module_inst->remaining_conversions = length;
+	module_inst->job_buffer = buffer;
+	module_inst->transferred_conversions = 0;
+
+	/* Enable interrupt */
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DAC);
+	dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN | DAC_INTFLAG_EMPTY;
+	dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN | DAC_INTENSET_EMPTY;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Convert one digital data job.
+ *
+ * This function will perform a conversion of specfic number of digital data.
+ * The conversion is event-triggered, the data will be written to DATABUF
+ * and transferred to the DATA register and converted when a Start Conversion
+ * Event is issued.
+ * Conversion data must be right or left adjusted according to configuration
+ * settings.
+ * \note To be event triggered, the enable_start_on_event must be
+ * enabled in the configuration.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] channel          DAC channel to write to
+ * \param[in] data             Digital data to be converted
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK           If the data was written
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ * \retval STATUS_BUSY      The DAC is busy to accept new job
+ */
+enum status_code dac_chan_write_job(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		uint16_t data)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	UNUSED(channel);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if(module_inst->remaining_conversions != 0 ||
+			module_inst->job_status == STATUS_BUSY){
+		return STATUS_BUSY;
+	}
+
+	dac_chan_write_buffer_job(module_inst, channel, &data, 1);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers an asynchronous callback function with the driver.
+ *
+ * Registers an asynchronous callback with the DAC driver, fired when a callback
+ * condition occurs.
+ *
+ * \param[in,out] module_inst  Pointer to the DAC software instance struct
+ * \param[in]     callback    Pointer to the callback function to register
+ * \param[in]     channel     Logical channel to register callback function
+ * \param[in]     type        Type of callback function to register
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK                   The callback was registered successfully
+ * \retval STATUS_ERR_INVALID_ARG      If an invalid callback type was supplied
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ */
+enum status_code dac_register_callback(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		const dac_callback_t callback,
+		const enum dac_callback type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(callback);
+
+	UNUSED(channel);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if ((uint8_t)type < DAC_CALLBACK_N) {
+		module_inst->callback[(uint8_t)type] = callback;
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Unregisters an asynchronous callback function with the driver.
+ *
+ * Unregisters an asynchronous callback with the DAC driver, removing it
+ * from the internal callback registration table.
+ *
+ * \param[in,out] module_inst  Pointer to the DAC software instance struct
+ * \param[in]     channel     Logical channel to unregister callback function
+ * \param[in]     type        Type of callback function to unregister
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK                   The callback was unregistered successfully
+ * \retval STATUS_ERR_INVALID_ARG      If an invalid callback type was supplied
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ */
+enum status_code dac_unregister_callback(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		const enum dac_callback type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	UNUSED(channel);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if ((uint8_t)type < DAC_CALLBACK_N) {
+		module_inst->callback[(uint8_t)type] = NULL;
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Enables asynchronous callback generation for a given channel and type.
+ *
+ * Enables asynchronous callbacks for a given logical DAC channel and type. This
+ * must be called before a DAC channel will generate callback events.
+ *
+ * \param[in,out] dac_module  Pointer to the DAC software instance struct
+ * \param[in]     channel     Logical channel to enable callback function
+ * \param[in]     type        Type of callback function callbacks to enable
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK                   The callback was enabled successfully
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ */
+enum status_code dac_chan_enable_callback(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		const enum dac_callback type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	UNUSED(channel);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	module_inst->callback_enable[type] = true;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables asynchronous callback generation for a given channel and type.
+ *
+ * Disables asynchronous callbacks for a given logical DAC channel and type.
+ *
+ * \param[in,out] dac_module  Pointer to the DAC software instance struct
+ * \param[in]     channel     Logical channel to disable callback function
+ * \param[in]     type        Type of callback function callbacks to disable
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK                   The callback was disabled successfully
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ */
+enum status_code dac_chan_disable_callback(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		const enum dac_callback type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	UNUSED(channel);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	module_inst->callback_enable[type] = false;
+
+	return STATUS_OK;
+}
+
+/** \internal
+ *  Internal handler for DAC module interrupts.
+ *
+ * \param[in] instance  DAC instance number
+ */
+static void _dac_interrupt_handler(const uint8_t instance)
+{
+	struct dac_module *module = _dac_instances[instance];
+	Dac *const dac_hw = module->hw;
+
+	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) {
+		dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN;
+
+		if ((module->callback) &&
+			 (module->callback_enable[DAC_CALLBACK_DATA_UNDERRUN])){
+			module->callback[DAC_CALLBACK_DATA_UNDERRUN](0);
+		}
+	}
+
+	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY) {
+		dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY;
+
+		/* If in a write buffer job */
+		if (module->remaining_conversions) {
+
+			/* Fill the data buffer with next data in write buffer */
+			dac_hw->DATABUF.reg =
+				module->job_buffer[module->transferred_conversions++];
+
+			/* Write buffer size decrement */
+			module->remaining_conversions --;
+
+			/* If in a write buffer job and all the data are converted */
+			if (module->remaining_conversions == 0) {
+				module->job_status = STATUS_OK;
+
+				/* Disable interrupt */
+				dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY;
+				dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY;
+				system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
+
+				if ((module->callback) &&
+					 (module->callback_enable[DAC_CALLBACK_TRANSFER_COMPLETE])) {
+					module->callback[DAC_CALLBACK_TRANSFER_COMPLETE](0);
+				}
+			}
+		}
+
+		if ((module->callback) &&
+			 (module->callback_enable[DAC_CALLBACK_DATA_EMPTY])) {
+			module->callback[DAC_CALLBACK_DATA_EMPTY](0);
+		}
+	}
+}
+
+/** Handler for the DAC hardware module interrupt. */
+void DAC_Handler(void)
+{
+	_dac_interrupt_handler(0);
+}
+
+/**
+ * \brief Gets the status of a job
+ *
+ * Gets the status of an ongoing or the last job.
+ *
+ * \param[in]  module_inst Pointer to the DAC software instance struct
+ * \param[in]  channel     Logical channel to enable callback function
+ *
+ * \return Status of the job.
+ */
+enum status_code dac_chan_get_job_status(
+		struct dac_module *module_inst,
+		const enum dac_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	UNUSED(channel);
+
+	return module_inst->job_status;
+}
+
+/**
+ * \brief Aborts an ongoing job
+ *
+ * Aborts an ongoing job.
+ *
+ * \param[in]  module_inst Pointer to the DAC software instance struct
+ * \param[in]  channel     Logical channel to enable callback function
+ */
+void dac_chan_abort_job(
+		struct dac_module *module_inst,
+		const enum dac_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	UNUSED(channel);
+
+	/* Disable interrupt */
+	module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN | DAC_INTFLAG_EMPTY;
+	module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN | DAC_INTENCLR_EMPTY;
+
+	/* Mark job as aborted */
+	module_inst->job_status = STATUS_ABORTED;
+	module_inst->remaining_conversions = 0;
+
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_feature.h
new file mode 100644
index 0000000000..3718e557d3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_feature.h
@@ -0,0 +1,635 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Digital-to-Analog Converter Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DAC_FEATURE_H_INCLUDED
+#define DAC_FEATURE_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_dac_group SAM Digital-to-Analog (DAC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the conversion of
+ * digital values to analog voltage. The following driver API modes are covered
+ * by this manual:
+ *
+ *  - Polled APIs
+ * \if DAC_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - DAC (Digital-to-Analog Converter)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM D10/D11
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_dac_prerequisites
+ *  - \ref asfdoc_sam0_dac_module_overview
+ *  - \ref asfdoc_sam0_dac_special_considerations
+ *  - \ref asfdoc_sam0_dac_extra_info
+ *  - \ref asfdoc_sam0_dac_examples
+ *  - \ref asfdoc_sam0_dac_api_overview
+ *
+ *
+ * \section asfdoc_sam0_dac_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_dac_module_overview Module Overview
+ *
+ * The Digital-to-Analog converter converts a digital value to analog voltage.
+ * The SAM DAC module has one channel with 10-bit resolution,
+ * and is capable of converting up to 350k samples per second (ksps).
+ *
+ * A common use of DAC is to generate audio signals by connecting the DAC
+ * output to a speaker, or to generate a reference voltage; either for an
+ * external circuit or an internal peripheral such as the Analog Comparator.
+ *
+ * After being set up, the DAC will convert new digital values written to the
+ * conversion data register (DATA) to an analog value either on the VOUT pin of
+ * the device, or internally for use as an input to the AC, ADC, and other analog
+ * modules.
+ *
+ * Writing the DATA register will start a new conversion. It is also possible
+ * to trigger the conversion from the event system.
+ *
+ * A simplified block diagram of the DAC can be seen in
+ * \ref asfdoc_sam0_dac_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_dac_module_block_diagram
+ * \image html dac_block_diagram.svg "DAC Block Diagram"
+ *
+ * \subsection asfdoc_sam0_dac_conversion_range Conversion Range
+ * The conversion range is between GND and the selected voltage reference.
+ * Available voltage references are:
+ * \li AVCC voltage reference
+ * \li Internal 1V reference (INT1V)
+ * \li External voltage reference (AREF)
+ *
+ * \note Internal references will be enabled by the driver, but not disabled.
+ * Any reference not used by the application should be disabled by the application.
+ *
+ * The output voltage from a DAC channel is given as:
+ * \f[
+ *    V_{OUT} = \frac{DATA}{0x3FF} \times VREF
+ * \f]
+ *
+ * \subsection asfdoc_sam0_dac_conversion Conversion
+ * The digital value written to the conversion data register (DATA) will be
+ * converted to an analog value.
+ * Writing the DATA register will start a new conversion.
+ * It is also possible to write the conversion data to the DATABUF register,
+ * the writing of the DATA register can then be triggered from the event
+ * system, which will load the value from DATABUF to DATA.
+ *
+ * \subsection asfdoc_sam0_dac_analog_output Analog Output
+ * The analog output value can be output to either the VOUT pin or internally,
+ * but not both at the same time.
+ *
+ * \subsubsection asfdoc_sam0_dac_analog_output_external External Output
+ * The output buffer must be enabled in order to drive the DAC output to the
+ * VOUT pin. Due to the output buffer, the DAC has high drive strength, and is
+ * capable of driving both resistive and capacitive loads, as well as loads
+ * which combine both.
+ *
+ * \subsubsection asfdoc_sam0_dac_analog_output_internal Internal Output
+ * The analog value can be internally available for use as input to the
+ * AC or ADC modules.
+ *
+ * \subsection asfdoc_sam0_dac_events Events
+ * Events generation and event actions are configurable in the DAC.
+ * The DAC has one event line input and one event output: <i>Start Conversion</i>
+ * and <i>Data Buffer Empty</i>.
+ *
+ * If the Start Conversion input event is enabled in the module configuration,
+ * an incoming event will load data from the data buffer to the data register
+ * and start a new conversion. This method synchronizes conversions with
+ * external events (such as those from a timer module) and ensures regular and
+ * fixed conversion intervals.
+ *
+ * If the Data Buffer Empty output event is enabled in the module configuration,
+ * events will be generated when the DAC data buffer register becomes empty and
+ * new data can be loaded to the buffer.
+ *
+ * \note The connection of events between modules requires the use of the event
+ *       driver to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the documentation
+ *       \ref asfdoc_sam0_events_group "SAM Event System (EVENTS) Driver".
+ *
+ * \subsection asfdoc_sam0_dac_data_adjust Left and Right Adjusted Values
+ * The 10-bit input value to the DAC is contained in a 16-bit register. This
+ * can be configured to be either left or right adjusted. In
+ * \ref asfdoc_sam0_dac_module_adj_modes "the figure below" both options are
+ * shown, and the position of the most (MSB) and the least (LSB) significant bits
+ * are indicated. The unused bits should always be written to zero.
+ *
+ * \anchor asfdoc_sam0_dac_module_adj_modes
+ * \dot
+ * digraph {
+ *   subgraph cluster_right {
+ *      msbl [label="MSB", shape=none, group="msbl"];
+ *      lsbl [label="LSB", shape=none];
+ *      node [shape=none];
+ *      color="white";
+ *      reg_left [label=<
+ *        <table cellspacing="0" cellpadding="2" width="100%">
+ *          <tr>
+ *            <td port="msb">15</td>
+ *            <td>14</td>
+ *            <td>13</td>
+ *            <td>12</td>
+ *            <td>11</td>
+ *            <td>10</td>
+ *            <td>9</td>
+ *            <td>8</td>
+ *            <td>7</td>
+ *            <td port="lsb">6</td>
+ *            <td>5</td>
+ *            <td>4</td>
+ *            <td>3</td>
+ *            <td>2</td>
+ *            <td>1</td>
+ *            <td>0</td>
+ *          </tr>
+ *          <tr>
+ *            <td COLSPAN="10"> DATA[9:0] </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *          </tr>
+ *        </table>
+ *      >];
+ *      msbl -> reg_left:msb:n;
+ *      lsbl -> reg_left:lsb;
+ *      label ="Left adjusted.\n";
+ *   }
+ *   subgraph cluster_left {
+ *      rankdir=TB;
+ *      msb [label="MSB", shape=none];
+ *      lsb [label="LSB", shape=none];
+ *      color="white";
+ *      node [shape=none];
+ *      reg_right [label=<
+ *        <table cellspacing="0" cellpadding="2">
+ *          <tr>
+ *            <td>15</td>
+ *            <td>14</td>
+ *            <td>13</td>
+ *            <td>12</td>
+ *            <td>11</td>
+ *            <td>10</td>
+ *            <td port="msb">9</td>
+ *            <td>8</td>
+ *            <td>7</td>
+ *            <td>6</td>
+ *            <td>5</td>
+ *            <td>4</td>
+ *            <td>3</td>
+ *            <td>2</td>
+ *            <td>1</td>
+ *            <td port="lsb">0</td>
+ *          </tr>
+ *          <tr>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td COLSPAN="10"> DATA[9:0] </td>
+ *          </tr>
+ *        </table>
+ *      >];
+ *      msb -> reg_right:msb;
+ *      lsb -> reg_right:lsb:n;
+ *      label = "Right adjusted.\n";
+ *      graph [shape=none];
+ *  }
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_dac_clk_sources Clock Sources
+ * The clock for the DAC interface (CLK_DAC) is generated by the Power Manager.
+ * This clock is turned on by default, and can be enabled and disabled in the
+ * Power Manager.
+ *
+ * Additionally, an asynchronous clock source (GCLK_DAC) is required.
+ * These clocks are normally disabled by default. The selected clock source
+ * must be enabled in the Power Manager before it can be used by the DAC.
+ * The DAC core operates asynchronously from the user interface and
+ * peripheral bus. As a consequence, the DAC needs two clock cycles of both
+ * CLK_DAC and GCLK_DAC to synchronize the values written to some of the
+ * control and data registers.
+ * The oscillator source for the GCLK_DAC clock is selected in the System
+ * Control Interface (SCIF).
+ *
+ * \section asfdoc_sam0_dac_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_dac_special_considerations_output_buffer Output Driver
+ * The DAC can only do conversions in Active or Idle modes. However, if the
+ * output buffer is enabled it will draw current even if the system is in
+ * sleep mode. Therefore, always make sure that the output buffer is not
+ * enabled when it is not needed, to ensure minimum power consumption.
+ *
+ * \subsection asfdoc_sam0_dac_special_considerations_conversion_time Conversion Time
+ * DAC conversion time is approximately 2.85渭s. The user must ensure that new
+ * data is not written to the DAC before the last conversion is complete.
+ * Conversions should be triggered by a periodic event from a Timer/Counter or
+ * another peripheral.
+ *
+ *
+ * \section asfdoc_sam0_dac_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_dac_extra. This includes:
+ *  - \ref asfdoc_sam0_dac_extra_acronyms
+ *  - \ref asfdoc_sam0_dac_extra_dependencies
+ *  - \ref asfdoc_sam0_dac_extra_errata
+ *  - \ref asfdoc_sam0_dac_extra_history
+ *
+ *
+ * \section asfdoc_sam0_dac_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_dac_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_dac_api_overview API Overview
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+
+
+/**
+ * \name DAC Status Flags
+ *
+ * DAC status flags, returned by \ref dac_get_status() and cleared by
+ * \ref dac_clear_status().
+ * @{
+ */
+
+/** Data Buffer Empty Channel 0 - Set when data is transferred from DATABUF
+ *  to DATA by a start conversion event and DATABUF is ready for new data.
+ */
+#define DAC_STATUS_CHANNEL_0_EMPTY     (1UL << 0)
+
+/** Under-run Channel 0 - Set when a start conversion event occurs when
+ *  DATABUF is empty.
+ */
+#define DAC_STATUS_CHANNEL_0_UNDERRUN  (1UL << 1)
+
+/** @} */
+
+/**
+ * \brief DAC reference voltage enum.
+ *
+ * Enum for the possible reference voltages for the DAC.
+ */
+enum dac_reference {
+	/** 1V from the internal band-gap reference*/
+	DAC_REFERENCE_INT1V = DAC_CTRLB_REFSEL(0),
+	/** Analog V<SUB>CC</SUB> as reference */
+	DAC_REFERENCE_AVCC  = DAC_CTRLB_REFSEL(1),
+	/** External reference on AREF */
+	DAC_REFERENCE_AREF  = DAC_CTRLB_REFSEL(2),
+};
+
+/**
+ * \brief DAC output selection enum.
+ *
+ * Enum for the DAC output selection.
+ */
+enum dac_output {
+	/** DAC output to VOUT pin */
+	DAC_OUTPUT_EXTERNAL = DAC_CTRLB_EOEN,
+	/** DAC output as internal reference */
+	DAC_OUTPUT_INTERNAL = DAC_CTRLB_IOEN,
+	/** No output */
+	DAC_OUTPUT_NONE     = 0,
+};
+
+/**
+ * \brief DAC channel selection enum.
+ *
+ * Enum for the DAC channel selection.
+ */
+enum dac_channel {
+	/** DAC output channel 0 */
+	DAC_CHANNEL_0,
+};
+
+/**
+ * \brief DAC software device instance structure.
+ *
+ * DAC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct dac_module {
+#if !defined(__DOXYGEN__)
+	/** DAC hardware module */
+	Dac *hw;
+	/** DAC output selection */
+	enum dac_output output;
+	/** Reference selection */
+	enum dac_reference reference;
+	/** DAC event selection */
+	bool start_on_event;
+#  if DAC_CALLBACK_MODE == true
+	/** Pointer to buffer used for ADC results */
+	volatile uint16_t *job_buffer;
+	/** Remaining number of conversions in current job */
+	volatile uint16_t remaining_conversions;
+	/** Transferred number of conversions in current job */
+	volatile uint16_t transferred_conversions;
+	/** DAC callback enable */
+	bool callback_enable[DAC_CALLBACK_N];
+	/** DAC registered callback functions */
+	dac_callback_t callback[DAC_CALLBACK_N];
+	/** Holds the status of the ongoing or last conversion job */
+	volatile enum status_code job_status;
+#  endif
+#endif
+};
+
+/**
+ * \brief DAC configuration structure.
+ *
+ * Configuration structure for a DAC instance. This structure should be
+ * initialized by the \ref dac_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct dac_config {
+	/** Reference voltage */
+	enum dac_reference reference;
+	/** Select DAC output */
+	enum dac_output output;
+	/** Left adjusted data */
+	bool left_adjust;
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
+	/** Bypass DATABUF write protection */
+	bool databuf_protection_bypass;
+#endif
+	/** Voltage pump disable */
+	bool voltage_pump_disable;
+	/**
+	 * The DAC behaves as in normal mode when the chip enters STANDBY sleep
+	 * mode
+	 */
+	bool run_in_standby;
+#if (SAMC21)
+	/** Dither mode enable data */
+	bool dither_mode;
+#endif
+};
+
+/**
+ * \brief DAC event enable/disable structure.
+ *
+ * Event flags for the DAC module. This is used to enable and
+ * disable events via \ref dac_enable_events() and \ref dac_disable_events().
+ */
+struct dac_events {
+	/** Start a new DAC conversion */
+	bool on_event_start_conversion;
+	/** Enable event generation on data buffer empty */
+	bool generate_event_on_buffer_empty;
+#if (SAMC21)
+	/** Enable the falling edge of the input event for DAC1 */
+	bool generate_event_on_chan_falling_edge;
+#endif
+};
+
+/**
+ * \brief DAC channel configuration structure
+ *
+ * Configuration for a DAC channel. This structure should be initialized by the
+ * \ref dac_chan_get_config_defaults() function before being modified by the
+ * user application.
+ */
+struct dac_chan_config {
+#if !defined(__DOXYGEN__)
+	/** Dummy value to ensure the struct has at least one member */
+	uint8_t _dummy;
+#endif
+};
+
+/**
+ * \name Configuration and Initialization (Channel)
+ * @{
+ */
+
+void dac_chan_enable_output_buffer(
+		struct dac_module *const dev_inst,
+		const enum dac_channel channel);
+
+void dac_chan_disable_output_buffer(
+		struct dac_module *const dev_inst,
+		const enum dac_channel channel);
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_dac_extra Extra Information for DAC Driver
+ *
+ * \section asfdoc_sam0_dac_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>ADC</td>
+ *		<td>Analog-to-Digital Converter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>AC</td>
+ *		<td>Analog Comparator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DAC</td>
+ *		<td>Digital-to-Analog Converter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>LSB</td>
+ *		<td>Least Significant Bit</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MSB</td>
+ *		<td>Most Significant Bit</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DMA</td>
+ *		<td>Direct Memory Access</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_dac_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_dac_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_dac_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Add configuration for using 14-bit hardware dithering (SAMC21 support)</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added new configuration parameters \c databuf_protection_bypass,
+ *		\c voltage_pump_disable. Added new callback functions
+ *		\c dac_chan_write_buffer_wait,
+ *		\c dac_chan_write_buffer_job, \c dac_chan_write_job,
+ *		\c dac_get_job_status, \c dac_abort_job and new callback type
+ *		\c DAC_CALLBACK_TRANSFER_COMPLETE for DAC conversion job</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_dac_exqsg Examples for DAC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_dac_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_dac_basic_use_case
+ * \if DAC_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_dac_basic_use_case_callback
+ * \endif
+ * \if DAC_DMA_USE_MODE_SELECTION
+ *  - \subpage asfdoc_sam0_adc_dma_use_case_dac_in_dma
+ * \endif
+ *
+ * \if DAC_DMA_USE_MODE_SELECTION
+ * \page asfdoc_sam0_adc_dma_use_case_dac_in_dma Quick Start Guide for Using DMA with ADC/DAC
+ * For this examples, see
+ * \ref asfdoc_sam0_adc_dma_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_dac_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42110E</td>
+ *		<td>09/2015</td>
+ *		<td>Add SAM C21 and SAM DA1 support</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42110D</td>
+ *		<td>12/2014</td>
+ *		<td>Add SAM D10/D11 support</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42110C</td>
+ *		<td>01/2014</td>
+ *		<td>Add SAM D21 support</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42110B</td>
+ *		<td>06/2013</td>
+ *		<td>Added additional documentation on the event system. Corrected
+ *          documentation typos.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42110A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* DAC_FEATURE_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac.c
new file mode 100644
index 0000000000..484b14f9d9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac.c
@@ -0,0 +1,796 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Digital-to-Analog Converter Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "dac.h"
+#include <system.h>
+#include <pinmux.h>
+
+/**
+ * \internal Writes a DAC configuration to the hardware module.
+ *
+ * Writes out a given configuration to the hardware module.
+ *
+ * \param[out] module_inst  Pointer to the DAC software instance struct
+ * \param[in]  config       Pointer to the configuration struct
+ *
+ */
+static void _dac_set_config(
+		struct dac_module *const module_inst,
+		struct dac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(config);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Set selected DAC start on event to be disable when enabling the module */
+	module_inst->start_on_event[DAC_CHANNEL_0] = false;
+	module_inst->start_on_event[DAC_CHANNEL_1] = false;
+
+	uint32_t new_ctrlb = 0;
+
+	/* Enable DAC in differential mode if configured */
+	if (config->differential_mode) {
+		new_ctrlb |= DAC_CTRLB_DIFF;
+	}
+
+	/* Set reference voltage */
+	new_ctrlb |= config->reference;
+
+	/* Apply the new configuration to the hardware module */
+	dac_module->CTRLB.reg = new_ctrlb;
+}
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] dev_inst  Pointer to the DAC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+bool dac_is_syncing(
+		struct dac_module *const dev_inst)
+{
+	/* Sanity check arguments */
+	Assert(dev_inst);
+
+	Dac *const dac_module = dev_inst->hw;
+
+	if (dac_module->SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Initializes a DAC configuration structure to defaults.
+ *
+ *  Initializes a given DAC configuration structure to a set of
+ *  known default values. This function should be called on any new
+ *  instance of the configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li 1V from internal bandgap reference
+ *   \li Drive the DAC output to the VOUT pin
+ *   \li Right adjust data
+ *   \li GCLK generator 0 (GCLK main) clock source
+ *   \li The output buffer is disabled when the chip enters STANDBY sleep
+ *       mode
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void dac_get_config_defaults(
+		struct dac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->differential_mode = false;
+    config->reference      = DAC_REFERENCE_INTREF;
+	config->clock_source   = GCLK_GENERATOR_0;
+}
+
+/**
+ * \brief Initialize the DAC device struct.
+ *
+ * Use this function to initialize the Digital to Analog Converter. Resets the
+ * underlying hardware module and configures it.
+ *
+ * \note The DAC channel must be configured separately.
+ *
+ * \param[out] module_inst  Pointer to the DAC software instance struct
+ * \param[in]  module       Pointer to the DAC module instance
+ * \param[in]  config       Pointer to the config struct, created by the user
+ *                          application
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK          Module initiated correctly
+ * \retval STATUS_ERR_DENIED  If module is enabled
+ * \retval STATUS_BUSY        If module is busy resetting
+ */
+enum status_code dac_init(
+		struct dac_module *const module_inst,
+		Dac *const module,
+		struct dac_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module);
+	Assert(config);
+
+	/* Initialize device instance */
+	module_inst->hw = module;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC);
+
+	/* Check if module is enabled. */
+	if (module->CTRLA.reg & DAC_CTRLA_ENABLE) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if reset is in progress. */
+	if (module->CTRLA.reg & DAC_CTRLA_SWRST) {
+		return STATUS_BUSY;
+	}
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(DAC_GCLK_ID);
+
+	/* Write configuration to module */
+	_dac_set_config(module_inst, config);
+
+	/* Store reference selection for later use */
+	module_inst->reference = config->reference;
+
+#if DAC_CALLBACK_MODE == true
+	for (uint8_t i = 0; i < DAC_CHANNEL_N; i++) {
+		for (uint8_t j = 0; j < DAC_CALLBACK_N; j++) {
+			module_inst->callback[i][j] = NULL;
+		}
+	};
+
+	_dac_instances[0] = module_inst;
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Resets the DAC module.
+ *
+ * This function will reset the DAC module to its power on default values and
+ * disable it.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ */
+void dac_reset(
+		struct dac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	while (dac_is_syncing(module_inst)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Software reset the module */
+	dac_module->CTRLA.reg |= DAC_CTRLA_SWRST;
+}
+
+/**
+ * \brief Enable the DAC module.
+ *
+ * Enables the DAC interface and the selected output. If any internal reference
+ * is selected it will be enabled.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ *
+ */
+void dac_enable(
+		struct dac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	while (dac_is_syncing(module_inst)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Enable the module */
+	dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE;
+
+	/* Enable internal bandgap reference if selected in the configuration */
+	if (module_inst->reference == DAC_REFERENCE_INTREF) {
+		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
+	}
+
+	if(dac_module->DACCTRL[DAC_CHANNEL_0].reg & DAC_DACCTRL_ENABLE) {
+		while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_0 + 1))) {
+		};
+	} else if(dac_module->DACCTRL[DAC_CHANNEL_1].reg & DAC_DACCTRL_ENABLE) {
+		while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_1 + 1))) {
+		};
+	}
+}
+
+/**
+ * \brief Disable the DAC module.
+ *
+ * Disables the DAC interface and the output buffer.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ *
+ */
+void dac_disable(
+		struct dac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	while (dac_is_syncing(module_inst)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Disbale interrupt */
+	dac_module->INTENCLR.reg = DAC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	dac_module->INTFLAG.reg = DAC_INTFLAG_MASK;
+
+	/* Disable DAC */
+	dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Enables a DAC event input or output.
+ *
+ *  Enables one or more input or output events to or from the DAC module. See
+ *  \ref dac_events "Struct dac_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the DAC peripheral
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+void dac_enable_events(
+		struct dac_module *const module_inst,
+		struct dac_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Enable Inversion of input event */
+	if (events->generate_event_on_chan0_falling_edge) {
+		event_mask |= DAC_EVCTRL_INVEI0;
+	}
+
+	/* Configure Enable Inversion of input event */
+	if (events->generate_event_on_chan1_falling_edge) {
+		event_mask |= DAC_EVCTRL_INVEI1;
+	}
+
+	/* Configure Buffer Empty event */
+	if (events->generate_event_on_chan0_buffer_empty) {
+		event_mask |= DAC_EVCTRL_EMPTYEO0;
+	}
+
+	/* Configure Buffer Empty event */
+	if (events->generate_event_on_chan1_buffer_empty) {
+		event_mask |= DAC_EVCTRL_EMPTYEO1;
+	}
+
+	/* Configure Conversion Start event */
+	if (events->on_event_chan0_start_conversion) {
+		event_mask |= DAC_EVCTRL_STARTEI0;
+		module_inst->start_on_event[DAC_CHANNEL_0] = true;
+	}
+
+	/* Configure Conversion Start event */
+	if (events->on_event_chan1_start_conversion) {
+		event_mask |= DAC_EVCTRL_STARTEI1;
+		module_inst->start_on_event[DAC_CHANNEL_1] = true;
+	}
+
+	dac_module->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables a DAC event input or output.
+ *
+ *  Disables one or more input or output events to or from the DAC module. See
+ *  \ref dac_events "Struct dac_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the DAC peripheral
+ *  \param[in] events       Struct containing flags of events to disable
+ */
+void dac_disable_events(
+		struct dac_module *const module_inst,
+		struct dac_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Buffer Empty event */
+	if (events->on_event_chan0_start_conversion) {
+		event_mask |= DAC_EVCTRL_EMPTYEO0;
+	}
+
+	/* Configure Buffer Empty event */
+	if (events->on_event_chan1_start_conversion) {
+		event_mask |= DAC_EVCTRL_EMPTYEO1;
+	}
+
+	/* Configure Conversion Start event */
+	if (events->generate_event_on_chan0_buffer_empty) {
+		event_mask |= DAC_EVCTRL_STARTEI0;
+		module_inst->start_on_event[DAC_CHANNEL_0] = false;
+	}
+
+	/* Configure Conversion Start event */
+	if (events->generate_event_on_chan0_buffer_empty) {
+		event_mask |= DAC_EVCTRL_STARTEI1;
+		module_inst->start_on_event[DAC_CHANNEL_1] = false;
+	}
+
+	dac_module->EVCTRL.reg &= ~event_mask;
+}
+
+void dac_chan_get_config_defaults(
+		struct dac_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Dac channel default configuration values */
+	config->left_adjust    = false;
+	config->current        = DAC_CURRENT_12M;
+	config->run_in_standby = false;
+	config->dither_mode    = false;
+	config->refresh_period = 2;
+}
+
+
+/**
+ * \brief Writes a DAC channel configuration to the hardware module.
+ *
+ * Writes out a given channel configuration to the hardware module.
+ *
+ * \note The DAC device instance structure must be initialized before calling
+ *       this function.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      Channel to configure
+ * \param[in] config       Pointer to the configuration struct
+ *
+ */
+void dac_chan_set_config(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		struct dac_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(config);
+
+	/* MUX the DAC VOUT pin */
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pin_conf.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+	if(channel == DAC_CHANNEL_0) {
+		/* Set up the DAC VOUT0 pin */
+		pin_conf.mux_position = MUX_PA02B_DAC_VOUT0;
+		system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT0, &pin_conf);
+	}
+	else if(channel == DAC_CHANNEL_1) {
+		/* Set up the DAC VOUT1 pin */
+		pin_conf.mux_position = MUX_PA05B_DAC_VOUT1;
+		system_pinmux_pin_set_config(PIN_PA05B_DAC_VOUT1, &pin_conf);
+	}
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint32_t new_dacctrl = 0;
+
+	/* Left adjust data if configured */
+	if (config->left_adjust) {
+		new_dacctrl |= DAC_DACCTRL_LEFTADJ;
+	}
+
+	/* Set current control */
+	new_dacctrl |= config->current;
+
+	/* Enable DAC in standby sleep mode if configured */
+	if (config->run_in_standby) {
+		new_dacctrl |= DAC_DACCTRL_RUNSTDBY;
+	}
+
+	/* Voltage pump disable if configured */
+	if (config->dither_mode) {
+		new_dacctrl |= DAC_DACCTRL_DITHER;
+	}
+
+	new_dacctrl |= DAC_DACCTRL_REFRESH(config->refresh_period);
+
+	/* Apply the new configuration to the hardware module */
+	dac_module->DACCTRL[channel].reg = new_dacctrl;
+}
+
+/**
+ * \brief Enable a DAC channel.
+ *
+ * Enables the selected DAC channel.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      Channel to enable
+ *
+ */
+void dac_chan_enable(
+		struct dac_module *const module_inst,
+		enum dac_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Enable the module */
+	dac_module->DACCTRL[channel].reg |= DAC_DACCTRL_ENABLE;
+}
+
+/**
+ * \brief Disable a DAC channel.
+ *
+ * Disables the selected DAC channel.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      Channel to disable
+ *
+ */
+void dac_chan_disable(
+		struct dac_module *const module_inst,
+		enum dac_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* Enable the module */
+	dac_module->DACCTRL[channel].reg &= ~DAC_DACCTRL_ENABLE;
+
+}
+
+/**
+ * \brief Write to the DAC.
+ *
+ * This function writes to the DATA or DATABUF register.
+ * If the conversion is not event-triggered, the data will be written to
+ * the DATA register and the conversion will start.
+ * If the conversion is event-triggered, the data will be written to DATABUF
+ * and transferred to the DATA register and converted when a Start Conversion
+ * Event is issued.
+ * Conversion data must be right or left adjusted according to configuration
+ * settings.
+ * \note To be event triggered, the enable_start_on_event must be
+ * enabled in the configuration.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] channel          DAC channel to write to
+ * \param[in] data             Conversion data
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK           If the data was written
+ */
+enum status_code dac_chan_write(
+		struct dac_module *const module_inst,
+		enum dac_channel channel,
+		const uint16_t data)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	while (dac_is_syncing(module_inst)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	if (module_inst->start_on_event[channel]) {
+		/* Write the new value to the buffered DAC data register */
+		dac_module->DATABUF[channel].reg = data;
+	} else {
+		/* Write the new value to the DAC data register */
+		dac_module->DATA[channel].reg = data;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Write to the DAC.
+ *
+ * This function converts a specific number of digital data.
+ * The conversion should be event-triggered, the data will be written to DATABUF
+ * and transferred to the DATA register and converted when a Start Conversion
+ * Event is issued.
+ * Conversion data must be right or left adjusted according to configuration
+ * settings.
+ * \note To be event triggered, the enable_start_on_event must be
+ * enabled in the configuration.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] channel          DAC channel to write to
+ * \param[in] buffer           Pointer to the digital data write buffer to be converted
+ * \param[in] length           Length of the write buffer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK           If the data was written or no data conversion required
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  The DAC is not configured as using event trigger
+ * \retval STATUS_BUSY                 The DAC is busy and can not do the conversion
+ */
+enum status_code dac_chan_write_buffer_wait(
+		struct dac_module *const module_inst,
+		enum dac_channel channel,
+		uint16_t *buffer,
+		uint32_t length)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	while (dac_is_syncing(module_inst)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Zero length request */
+	if (length == 0) {
+		/* No data to be converted */
+		return STATUS_OK;
+	}
+
+#if DAC_CALLBACK_MODE == true
+	/* Check if busy */
+	if (module_inst->job_status[channel] == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Only support event triggered conversion */
+	if (module_inst->start_on_event[channel] == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Blocks while buffer is being transferred */
+	while (length--) {
+		/* Convert one data */
+		dac_chan_write(module_inst, channel, buffer[length]);
+
+		/* Wait until Transmit is complete or timeout */
+		for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) {
+			if(channel == DAC_CHANNEL_0) {
+				if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY0) {
+					break;
+				} else if (i == DAC_TIMEOUT) {
+					return STATUS_ERR_TIMEOUT;
+				}
+			} else if(channel == DAC_CHANNEL_1) {
+				if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY1) {
+					break;
+				} else if (i == DAC_TIMEOUT) {
+					return STATUS_ERR_TIMEOUT;
+				}
+			}
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the status of DAC channel end of conversion.
+ *
+ * Checks if the conversion is completed or not and returns boolean flag
+ * of status.
+ *
+ * \param[in] module_inst  Pointer to the DAC software instance struct
+ * \param[in] channel      Channel to disable
+ *
+ * \retval true     Conversion is complete, VOUT is stable
+ * \retval false    No conversion completed since last load of DATA
+ */
+bool dac_chan_is_end_of_conversion(
+		struct dac_module *const module_inst,
+		enum dac_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	if(dac_module->STATUS.reg & DAC_STATUS_EOC(channel + 1)) {
+		return true;
+	} else {
+		return false;
+	}
+}
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Checks the status of the module and returns it as a bitmask of status
+ * flags.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ *
+ * \return Bitmask of status flags.
+ *
+ * \retval DAC_STATUS_CHANNEL_0_EMPTY    Data has been transferred from DATABUF
+ *                                       to DATA by a start conversion event
+ *                                       and DATABUF is ready for new data
+ * \retval DAC_STATUS_CHANNEL_0_UNDERRUN A start conversion event has occurred
+ *                                       when DATABUF is empty
+ *
+ */
+uint32_t dac_get_status(
+		struct dac_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint8_t intflags = dac_module->INTFLAG.reg;
+	uint32_t status_flags = 0;
+
+	if (intflags & DAC_INTFLAG_EMPTY0) {
+		status_flags |= DAC_STATUS_CHANNEL_0_EMPTY;
+	}
+
+	if (intflags & DAC_INTFLAG_EMPTY1) {
+		status_flags |= DAC_STATUS_CHANNEL_1_EMPTY;
+	}
+
+	if (intflags & DAC_INTFLAG_UNDERRUN0) {
+		status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN;
+	}
+
+	if (intflags & DAC_INTFLAG_UNDERRUN1) {
+		status_flags |= DAC_STATUS_CHANNEL_1_UNDERRUN;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] status_flags     Bit mask of status flags to clear
+ *
+ */
+void dac_clear_status(
+		struct dac_module *const module_inst,
+		uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Dac *const dac_module = module_inst->hw;
+
+	uint32_t intflags = 0;
+
+	if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) {
+		intflags |= DAC_INTFLAG_EMPTY0;
+	}
+
+	if (status_flags & DAC_STATUS_CHANNEL_1_EMPTY) {
+		intflags |= DAC_INTFLAG_EMPTY1;
+	}
+
+	if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) {
+		intflags |= DAC_INTFLAG_UNDERRUN0;
+	}
+
+	if (status_flags & DAC_STATUS_CHANNEL_1_UNDERRUN) {
+		intflags |= DAC_INTFLAG_UNDERRUN1;
+	}
+
+	dac_module->INTFLAG.reg = intflags;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_callback.c
new file mode 100644
index 0000000000..f15688a9b4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_callback.c
@@ -0,0 +1,484 @@
+/**
+ * \file
+ *
+ * \brief SAM Digital-to-Analog Interrupt Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "dac.h"
+#include "dac_callback.h"
+
+struct dac_module *_dac_instances[DAC_INST_NUM];
+
+/**
+ * \brief Convert a specific number digital data to analog through DAC.
+ *
+ * This function will perform a conversion of specific number of digital data.
+ * The conversion should be event-triggered, the data will be written to DATABUF
+ * and transferred to the DATA register and converted when a Start Conversion
+ * Event is issued.
+ * Conversion data must be right or left adjusted according to configuration
+ * settings.
+ * \note To be event triggered, the enable_start_on_event must be
+ * enabled in the configuration.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] channel          DAC channel to write to
+ * \param[in] buffer             Pointer to the digital data write buffer to be converted
+ * \param[in] length             Size of the write buffer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK           If the data was written
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ * \retval STATUS_BUSY      The DAC is busy and can not accept a new job
+ */
+enum status_code dac_chan_write_buffer_job(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		uint16_t *buffer,
+		uint32_t length)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(buffer);
+
+	Dac *const dac_module = module_inst->hw;
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event[channel] == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if(module_inst->remaining_conversions[channel] != 0 ||
+			module_inst->job_status[channel] == STATUS_BUSY){
+		return STATUS_BUSY;
+	}
+
+	/* Wait until the synchronization is complete */
+	while (dac_is_syncing(module_inst)) {
+	};
+
+	module_inst->job_status[channel] = STATUS_BUSY;
+
+	module_inst->remaining_conversions[channel] = length;
+	module_inst->job_buffer[channel] = buffer;
+	module_inst->transferred_conversions[channel] = 0;
+
+	/* Enable interrupt */
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DAC);
+	switch(channel){
+	case DAC_CHANNEL_0:
+		dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_EMPTY0;
+		dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN0 | DAC_INTENSET_EMPTY0;
+		break;
+	case DAC_CHANNEL_1:
+		dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1 | DAC_INTFLAG_EMPTY1;
+		dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN1 | DAC_INTENSET_EMPTY1;
+		break;
+	default:
+		break;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Convert one digital data job.
+ *
+ * This function will perform a conversion of specfic number of digital data.
+ * The conversion is event-triggered, the data will be written to DATABUF
+ * and transferred to the DATA register and converted when a Start Conversion
+ * Event is issued.
+ * Conversion data must be right or left adjusted according to configuration
+ * settings.
+ * \note To be event triggered, the enable_start_on_event must be
+ * enabled in the configuration.
+ *
+ * \param[in] module_inst      Pointer to the DAC software device struct
+ * \param[in] channel          DAC channel to write to
+ * \param[in] data             Digital data to be converted
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK           If the data was written
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ * \retval STATUS_BUSY      The DAC is busy and can not accept a new job
+ */
+enum status_code dac_chan_write_job(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		uint16_t data)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event[channel] == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if(module_inst->remaining_conversions[channel] != 0 ||
+			module_inst->job_status[channel] == STATUS_BUSY){
+		return STATUS_BUSY;
+	}
+
+	dac_chan_write_buffer_job(module_inst, channel, &data, 1);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers an asynchronous callback function with the driver.
+ *
+ * Registers an asynchronous callback with the DAC driver, fired when a callback
+ * condition occurs.
+ *
+ * \param[in,out] module_inst  Pointer to the DAC software instance struct
+ * \param[in]     callback    Pointer to the callback function to register
+ * \param[in]     channel     Logical channel to register callback function
+ * \param[in]     type        Type of callback function to register
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK                   The callback was registered successfully
+ * \retval STATUS_ERR_INVALID_ARG      If an invalid callback type was supplied
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ */
+enum status_code dac_register_callback(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		const dac_callback_t callback,
+		const enum dac_callback type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(callback);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event[channel] == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if ((uint8_t)type < DAC_CALLBACK_N) {
+		module_inst->callback[channel][(uint8_t)type] = callback;
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Unregisters an asynchronous callback function with the driver.
+ *
+ * Unregisters an asynchronous callback with the DAC driver, removing it
+ * from the internal callback registration table.
+ *
+ * \param[in,out] module_inst  Pointer to the DAC software instance struct
+ * \param[in]     channel     Logical channel to unregister callback function
+ * \param[in]     type        Type of callback function to unregister
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK                   The callback was unregistered successfully
+ * \retval STATUS_ERR_INVALID_ARG      If an invalid callback type was supplied
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ */
+enum status_code dac_unregister_callback(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		const enum dac_callback type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event[channel] == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if ((uint8_t)type < DAC_CALLBACK_N) {
+		module_inst->callback[channel][(uint8_t)type] = NULL;
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Enables asynchronous callback generation for a given channel and type.
+ *
+ * Enables asynchronous callbacks for a given logical DAC channel and type. This
+ * must be called before a DAC channel will generate callback events.
+ *
+ * \param[in,out] dac_module  Pointer to the DAC software instance struct
+ * \param[in]     channel     Logical channel to enable callback function
+ * \param[in]     type        Type of callback function callbacks to enable
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK                   The callback was enabled successfully
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ */
+enum status_code dac_chan_enable_callback(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		const enum dac_callback type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event[channel] == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	module_inst->callback_enable[channel][type] = true;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables asynchronous callback generation for a given channel and type.
+ *
+ * Disables asynchronous callbacks for a given logical DAC channel and type.
+ *
+ * \param[in,out] dac_module  Pointer to the DAC software instance struct
+ * \param[in]     channel     Logical channel to disable callback function
+ * \param[in]     type        Type of callback function callbacks to disable
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK                   The callback was disabled successfully
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If a callback that requires event driven
+ *                                     mode was specified with a DAC instance
+ *                                     configured in non-event mode
+ */
+enum status_code dac_chan_disable_callback(
+		struct dac_module *const module_inst,
+		const enum dac_channel channel,
+		const enum dac_callback type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	UNUSED(channel);
+
+	/* DAC interrupts require it to be driven by events to work, fail if in
+	 * unbuffered (polled) mode */
+	if (module_inst->start_on_event[channel] == false) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	module_inst->callback_enable[channel][type] = false;
+
+	return STATUS_OK;
+}
+
+/** \internal
+ *  Internal handler for DAC module interrupts.
+ *
+ * \param[in] instance  DAC instance number
+ */
+static void _dac_interrupt_handler(const uint8_t instance)
+{
+	struct dac_module *module = _dac_instances[instance];
+	Dac *const dac_hw = module->hw;
+
+	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) {
+		dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
+
+		if ((module->callback) &&
+			 (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_DATA_UNDERRUN])) {
+			module->callback[DAC_CHANNEL_0][DAC_CALLBACK_DATA_UNDERRUN](0);
+		}
+	}
+
+	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) {
+		dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
+
+		if ((module->callback) &&
+			 (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_DATA_UNDERRUN])) {
+			module->callback[DAC_CHANNEL_1][DAC_CALLBACK_DATA_UNDERRUN](0);
+		}
+	}
+
+	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY0) {
+		dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+
+		if ((module->callback) &&
+			 (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_DATA_EMPTY])) {
+			module->callback[DAC_CHANNEL_0][DAC_CALLBACK_DATA_EMPTY](0);
+		}
+	}
+
+	/* If in a write buffer job */
+	if (module->remaining_conversions[DAC_CHANNEL_0]) {
+
+		/* Fill the data buffer with next data in write buffer */
+		dac_hw->DATABUF[DAC_CHANNEL_0].reg =
+			module->job_buffer[DAC_CHANNEL_0][module->transferred_conversions[DAC_CHANNEL_0]++];
+
+		/* Write buffer size decrement */
+		module->remaining_conversions[DAC_CHANNEL_0] --;
+
+		/* If in a write buffer job and all the data are converted */
+		if (module->remaining_conversions[DAC_CHANNEL_0] == 0) {
+			module->job_status[DAC_CHANNEL_0] = STATUS_OK;
+
+			/* Disable interrupt */
+			dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY0;
+			dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+			system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
+
+			if ((module->callback) &&
+				 (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_TRANSFER_COMPLETE])) {
+				module->callback[DAC_CHANNEL_0][DAC_CALLBACK_TRANSFER_COMPLETE](0);
+			}
+		}
+	}
+
+	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY1) {
+		dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+
+		if ((module->callback) &&
+			 (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_DATA_EMPTY])) {
+			module->callback[DAC_CHANNEL_1][DAC_CALLBACK_DATA_EMPTY](0);
+		}
+	}
+	/* If in a write buffer job */
+	if (module->remaining_conversions[DAC_CHANNEL_1]) {
+
+		/* Fill the data buffer with next data in write buffer */
+		dac_hw->DATABUF[DAC_CHANNEL_1].reg =
+			module->job_buffer[DAC_CHANNEL_1][module->transferred_conversions[DAC_CHANNEL_1]++];
+
+		/* Write buffer size decrement */
+		module->remaining_conversions[DAC_CHANNEL_1] --;
+
+		/* If in a write buffer job and all the data are converted */
+		if (module->remaining_conversions[DAC_CHANNEL_1] == 0) {
+			module->job_status[DAC_CHANNEL_1] = STATUS_OK;
+
+			/* Disable interrupt */
+			dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY1;
+			dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+			system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
+
+			if ((module->callback) &&
+				 (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_TRANSFER_COMPLETE])) {
+				module->callback[DAC_CHANNEL_1][DAC_CALLBACK_TRANSFER_COMPLETE](0);
+			}
+		}
+	}
+}
+
+/** Handler for the DAC hardware module interrupt. */
+void DAC_Handler(void)
+{
+	_dac_interrupt_handler(0);
+}
+
+/**
+ * \brief Gets the status of a job.
+ *
+ * Gets the status of an ongoing or the last job.
+ *
+ * \param[in]  module_inst Pointer to the DAC software instance struct
+ * \param[in]  channel     Logical channel to enable callback function
+ *
+ * \return Status of the job.
+ */
+enum status_code dac_chan_get_job_status(
+		struct dac_module *module_inst,
+		const enum dac_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	return module_inst->job_status[channel];
+}
+
+/**
+ * \brief Aborts an ongoing job.
+ *
+ * Aborts an ongoing job.
+ *
+ * \param[in]  module_inst Pointer to the DAC software instance struct
+ * \param[in]  channel     Logical channel to enable callback function
+ */
+void dac_chan_abort_job(
+		struct dac_module *module_inst,
+		const enum dac_channel channel)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	/* Disable interrupt */
+	switch(channel) {
+	case DAC_CHANNEL_0:
+		module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_EMPTY0;
+		module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN0 | DAC_INTENCLR_EMPTY0;
+		break;
+	case DAC_CHANNEL_1:
+		module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1 | DAC_INTFLAG_EMPTY1;
+		module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN1 | DAC_INTENCLR_EMPTY1;
+		break;
+	default:
+		break;
+	}
+
+	/* Mark job as aborted */
+	module_inst->job_status[channel] = STATUS_ABORTED;
+	module_inst->remaining_conversions[channel] = 0;
+
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_feature.h
new file mode 100644
index 0000000000..3385396e61
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_feature.h
@@ -0,0 +1,611 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Digital-to-Analog Converter Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DAC_FEATURE_H_INCLUDED
+#define DAC_FEATURE_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_dac_group SAM Digital-to-Analog (DAC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the conversion of
+ * digital values to analog voltage. The following driver API modes are covered
+ * by this manual:
+ *
+ *  - Polled APIs
+ * \if DAC_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - DAC (Digital-to-Analog Converter)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_dac_prerequisites
+ *  - \ref asfdoc_sam0_dac_module_overview
+ *  - \ref asfdoc_sam0_dac_special_considerations
+ *  - \ref asfdoc_sam0_dac_extra_info
+ *  - \ref asfdoc_sam0_dac_examples
+ *  - \ref asfdoc_sam0_dac_api_overview
+ *
+ *
+ * \section asfdoc_sam0_dac_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_dac_module_overview Module Overview
+ *
+ * The Digital-to-Analog converter converts a digital value to an analog voltage.
+ * The DAC Controller can operate as two independent DACs or as a single DAC
+ * in differential mode. Each DAC has a 12-bit resolution and it is capable of
+ * converting up to 1M samples per second (Msps).
+ *
+ * A common use of DAC is to generate audio signals by connecting the DAC
+ * output to a speaker, or to generate a reference voltage; either for an
+ * external circuit or an internal peripheral such as the Analog Comparator.
+ *
+ * After being set up, the DAC will convert new digital values written to the
+ * conversion data register (DATA0 or DATA1) to an analog value either on the
+ * DAC output (VOUT0 or VOUT1) pin of the device, or internally for use as an
+ * input to the AC, ADC, and other analog modules.
+ *
+ * Writing the DATA register will start a new conversion. It is also possible
+ * to trigger the conversion from the event system.
+ *
+ * A simplified block diagram of the DAC can be seen in
+ * \ref asfdoc_sam0_dac_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_dac_module_block_diagram
+ * \image html dac_block_diagram_saml.svg "DAC Block Diagram"
+ *
+ * \subsection asfdoc_sam0_dac_conversion_range Conversion Range
+ * The conversion range is between GND and the selected voltage reference.
+ * Available voltage references are:
+ * \li Voltage supply (VDDANA)
+ * \li Internal bandgap reference (INTREF)
+ * \li Unbuffered External voltage reference (VREFPU)
+ * \li Buffered External voltage reference (VREFPB)
+ *
+ * \note Internal references will be enabled by the driver, but not disabled.
+ * Any reference not used by the application should be disabled by the application.
+ *
+ * The output voltage from a DAC channel is given as:
+ * \f[
+ *    V_{OUTx} = \frac{DATAx}{0x3FF} \times VREF
+ * \f]
+ * The differential output voltage is given as:
+ * \f[
+ *    V_{OUT} = \frac{DATA0}{0x1FF} \times VREF = (V_{OUT0}-V_{OUT1})
+ * \f]
+ *
+ * \subsection asfdoc_sam0_dac_conversion Conversion
+ * The conversion digital value written to the DATA register will be converted
+ * to an analog value. Writing the DATA register will start a new conversion.
+ * It is also possible to write the conversion value to the DATABUF register,
+ * the writing of the DATA register can then be triggered from the event
+ * system, which will load the value from DATABUF to DATA.
+ *
+ * \subsection asfdoc_sam0_dac_analog_output Analog Output
+ * The analog output value can be output to the VOUTx converted by DACx, and
+ * each data conversion can be started independently.
+ *
+ * In differential mode, DAC0 and DAC1 are operating synchronously to convert
+ * value. VOUT0 is the positive output and VOUT1 the negative output.
+ *
+ * VOUT0 signal is internally connected so that it can be used as input for
+ * AC, ADC, or OPAMP modules when DAC0 is enabled.
+ * \note The pin VOUT0 will be dedicated to internal input and cannot be
+ * configured as alternate function.
+ *
+ * \subsection asfdoc_sam0_dac_events Events
+ * Events generation and event actions are configurable in the DAC.
+ * The DAC has one event line input and one event output: <i>Start Conversion</i>
+ * and <i>Data Buffer Empty</i>.
+ *
+ * If the Start Conversion input event is enabled in the module configuration,
+ * an incoming event will load data from the data buffer to the data register
+ * and start a new conversion. This method synchronizes conversions with
+ * external events (such as those from a timer module) and ensures regular and
+ * fixed conversion intervals.
+ *
+ * If the Data Buffer Empty output event is enabled in the module configuration,
+ * events will be generated when the DAC data buffer register becomes empty and
+ * new data can be loaded to the buffer.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * \subsection asfdoc_sam0_dac_data_adjust Left and Right Adjusted Values
+ * The 12-bit input value to the DAC is contained in a 16-bit register. This
+ * can be configured to be either left or right adjusted. In
+ * \ref asfdoc_sam0_dac_module_adj_modes "the figure below" both options are
+ * shown, and the position of the most (MSB) and the least (LSB) significant bits
+ * are indicated. The unused bits should always be written to zero.
+ *
+ * \anchor asfdoc_sam0_dac_module_adj_modes
+ * \dot
+ * digraph {
+ *   subgraph cluster_right {
+ *      msbl [label="MSB", shape=none, group="msbl"];
+ *      lsbl [label="LSB", shape=none];
+ *      node [shape=none];
+ *      color="white";
+ *      reg_left [label=<
+ *        <table cellspacing="0" cellpadding="2" width="100%">
+ *          <tr>
+ *            <td port="msb">15</td>
+ *            <td>14</td>
+ *            <td>13</td>
+ *            <td>12</td>
+ *            <td>11</td>
+ *            <td>10</td>
+ *            <td>9</td>
+ *            <td>8</td>
+ *            <td>7</td>
+ *            <td>6</td>
+ *            <td>5</td>
+ *            <td port="lsb">4</td>
+ *            <td>3</td>
+ *            <td>2</td>
+ *            <td>1</td>
+ *            <td>0</td>
+ *          </tr>
+ *          <tr>
+ *            <td COLSPAN="12"> DATA[11:0] </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *            <td BGCOLOR="lightgray"> </td>
+ *          </tr>
+ *        </table>
+ *      >];
+ *      msbl -> reg_left:msb:n;
+ *      lsbl -> reg_left:lsb;
+ *      label ="Left adjusted.\n";
+ *   }
+ *   subgraph cluster_left {
+ *      rankdir=TB;
+ *      msb [label="MSB", shape=none];
+ *      lsb [label="LSB", shape=none];
+ *      color="white";
+ *      node [shape=none];
+ *      reg_right [label=<
+ *        <table cellspacing="0" cellpadding="2">
+ *          <tr>
+ *            <td>15</td>
+ *            <td>14</td>
+ *            <td>13</td>
+ *            <td>12</td>
+ *            <td port="msb">11</td>
+ *            <td>10</td>
+ *            <td>9</td>
+ *            <td>8</td>
+ *            <td>7</td>
+ *            <td>6</td>
+ *            <td>5</td>
+ *            <td>4</td>
+ *            <td>3</td>
+ *            <td>2</td>
+ *            <td>1</td>
+ *            <td port="lsb">0</td>
+ *          </tr>
+ *          <tr>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td BGCOLOR="lightgray"></td>
+ *            <td COLSPAN="12"> DATA[11:0] </td>
+ *          </tr>
+ *        </table>
+ *      >];
+ *      msb -> reg_right:msb;
+ *      lsb -> reg_right:lsb:n;
+ *      label = "Right adjusted.\n";
+ *      graph [shape=none];
+ *  }
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_dac_clk_sources Clock Sources
+ * The clock for the DAC interface (CLK_DAC) is generated by the Power Manager.
+ * This clock is turned on by default, and can be enabled and disabled in the
+ * Power Manager.
+ *
+ * Additionally, an asynchronous clock source (GCLK_DAC) is required.
+ * These clocks are normally disabled by default. The selected clock source
+ * must be enabled in the Power Manager before it can be used by the DAC.
+ * The DAC core operates asynchronously from the user interface and
+ * peripheral bus. As a consequence, the DAC needs two clock cycles of both
+ * CLK_DAC and GCLK_DAC to synchronize the values written to some of the
+ * control and data registers.
+ * The oscillator source for the GCLK_DAC clock is selected in the Supply
+ * Control Interface (SUPC).
+ *
+ * \section asfdoc_sam0_dac_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_dac_special_considerations_sleep Sleep Mode
+ * The DAC can do conversions in Active or Idle modes, and will continue the
+ * conversions in standby sleep mode if the RUNSTDBY bit in the DACCTRLx
+ * register is set. Otherwise, the DACx will stop conversions.
+ *
+ * If DACx conversion is stopped in standby sleep mode, DACx is disabled to
+ * reduce power consumption. When exiting standby sleep mode, DACx is enabled
+ * therefore startup time is required before starting a new conversion.
+ *
+ * \subsection asfdoc_sam0_dac_special_considerations_conversion_time Conversion Time
+ * DAC conversion time is approximately 2.85碌s. The user must ensure that new
+ * data is not written to the DAC before the last conversion is complete.
+ * Conversions should be triggered by a periodic event from a Timer/Counter or
+ * another peripheral.
+ *
+ *
+ * \section asfdoc_sam0_dac_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_dac_extra. This includes:
+ *  - \ref asfdoc_sam0_dac_extra_acronyms
+ *  - \ref asfdoc_sam0_dac_extra_dependencies
+ *  - \ref asfdoc_sam0_dac_extra_errata
+ *  - \ref asfdoc_sam0_dac_extra_history
+ *
+ *
+ * \section asfdoc_sam0_dac_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_dac_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_dac_api_overview API Overview
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+
+
+/**
+ * \name DAC Status Flags
+ *
+ * DAC status flags, returned by \ref dac_get_status() and cleared by
+ * \ref dac_clear_status().
+ * @{
+ */
+
+/** Data Buffer Empty Channel 0 - Set when data is transferred from DATABUF
+ *  to DATA by a start conversion event and DATABUF is ready for new data.
+ */
+#define DAC_STATUS_CHANNEL_0_EMPTY     (1UL << 0)
+
+/** Data Buffer Empty Channel 1 - Set when data is transferred from DATABUF
+ *  to DATA by a start conversion event and DATABUF is ready for new data.
+ */
+#define DAC_STATUS_CHANNEL_1_EMPTY     (1UL << 1)
+
+/** Underrun Channel 0 - Set when a start conversion event occurs when
+ *  DATABUF is empty.
+ */
+#define DAC_STATUS_CHANNEL_0_UNDERRUN  (1UL << 2)
+
+/** Underrun Channel 1 - Set when a start conversion event occurs when
+ *  DATABUF is empty.
+ */
+#define DAC_STATUS_CHANNEL_1_UNDERRUN  (1UL << 3)
+
+/** @} */
+
+/**
+ * \brief DAC reference voltage enum.
+ *
+ * Enum for the possible reference voltages for the DAC.
+ */
+enum dac_reference {
+	/** Unbuffered external voltage reference */
+	DAC_REFERENCE_VREFPU = DAC_CTRLB_REFSEL(0),
+	/** Analog VCC as reference */
+	DAC_REFERENCE_VDDANA = DAC_CTRLB_REFSEL(1),
+	/** Buffered external voltage reference */
+	DAC_REFERENCE_VREFPB = DAC_CTRLB_REFSEL(2),
+	/** Internal bandgap reference */
+	DAC_REFERENCE_INTREF = DAC_CTRLB_REFSEL(3),
+};
+
+/**
+ * \brief DAC current control enum.
+ *
+ * Enum for the current in output buffer according the conversion rate.
+ */
+enum dac_current_ctrl {
+	/** GCLK_DAC <= 1.2MHz */
+	DAC_CURRENT_100K  = DAC_DACCTRL_CCTRL(0),
+	/** 1.2MHz < GCLK_DAC <= 6MHz */
+	DAC_CURRENT_1M   = DAC_DACCTRL_CCTRL(1),
+	/** 6MHz < GCLK_DAC <= 12MHz */
+	DAC_CURRENT_12M = DAC_DACCTRL_CCTRL(2),
+	/** Reserved */
+	DAC_CURRENT_RESERVED  = DAC_DACCTRL_CCTRL(3),
+};
+
+/**
+ * \brief DAC channel selection enum.
+ *
+ * Enum for the DAC channel selection.
+ */
+enum dac_channel {
+	/** DAC output channel 0 */
+	DAC_CHANNEL_0,
+	/** DAC output channel 1 */
+	DAC_CHANNEL_1,
+#if !defined(__DOXYGEN__)
+	DAC_CHANNEL_N,
+#endif
+};
+
+/**
+ * \brief DAC software device instance structure.
+ *
+ * DAC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct dac_module {
+#if !defined(__DOXYGEN__)
+	/** DAC hardware module */
+	Dac *hw;
+	/** Reference selection */
+	enum dac_reference reference;
+	/** DAC event selection */
+	bool start_on_event[DAC_CHANNEL_N];
+#  if DAC_CALLBACK_MODE == true
+	/** Pointer to buffer used for ADC results */
+	volatile uint16_t *job_buffer[DAC_CHANNEL_N];
+	/** Remaining number of conversions in current job */
+	volatile uint16_t remaining_conversions[DAC_CHANNEL_N];
+	/** Transferred number of conversions in current job */
+	volatile uint16_t transferred_conversions[DAC_CHANNEL_N];
+	/** DAC callback enable */
+	bool callback_enable[DAC_CHANNEL_N][DAC_CALLBACK_N];
+	/** DAC registered callback functions */
+	dac_callback_t callback[DAC_CHANNEL_N][DAC_CALLBACK_N];
+	/** Holds the status of the ongoing or last conversion job */
+	volatile enum status_code job_status[DAC_CHANNEL_N];
+#  endif
+#endif
+};
+
+/**
+ * \brief DAC configuration structure.
+ *
+ * Configuration structure for a DAC instance. This structure should be
+ * initialized by the \ref dac_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct dac_config {
+	/** Differential mode enable data */
+	bool differential_mode;
+	/** Reference voltage */
+	enum dac_reference reference;
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+};
+
+/**
+ * \brief DAC channel configuration structure.
+ *
+ * Configuration for a DAC channel. This structure should be initialized by the
+ * \ref dac_chan_get_config_defaults() function before being modified by the
+ * user application.
+ */
+struct dac_chan_config {
+	/** Left adjusted data */
+	bool left_adjust;
+	/** Current control data */
+	enum dac_current_ctrl current;
+	/**
+	 * The DAC behaves as in normal mode when the chip enters STANDBY sleep
+	 * mode
+	 */
+	bool run_in_standby;
+	/** Dither mode enable data */
+	bool dither_mode;
+	/**
+	 * The DAC conversion refreshed periodically when used to generate a static
+	 * voltage
+	 */
+	uint8_t refresh_period;
+};
+
+/**
+ * \brief DAC event enable/disable structure.
+ *
+ * Event flags for the DAC module. This is used to enable and
+ * disable events via \ref dac_enable_events() and \ref dac_disable_events().
+ */
+struct dac_events {
+	/** Start a new DAC0 conversion */
+	bool on_event_chan0_start_conversion;
+	/** Start a new DAC1 conversion */
+	bool on_event_chan1_start_conversion;
+	/** Enable event generation on DAC0 data buffer empty */
+	bool generate_event_on_chan0_buffer_empty;
+	/** Enable event generation on DAC1 data buffer empty */
+	bool generate_event_on_chan1_buffer_empty;
+	/** Enable the falling edge of the input event for DAC0 */
+	bool generate_event_on_chan0_falling_edge;
+	/** Enable the falling edge of the input event for DAC1 */
+	bool generate_event_on_chan1_falling_edge;
+};
+
+/**
+ * \name Status Management (Channel)
+ * @{
+ */
+bool dac_chan_is_end_of_conversion(
+		struct dac_module *const module_inst,
+		enum dac_channel channel);
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_dac_extra Extra Information for DAC Driver
+ *
+ * \section asfdoc_sam0_dac_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>ADC</td>
+ *		<td>Analog-to-Digital Converter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>AC</td>
+ *		<td>Analog Comparator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DAC</td>
+ *		<td>Digital-to-Analog Converter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>LSB</td>
+ *		<td>Least Significant Bit</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MSB</td>
+ *		<td>Most Significant Bit</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DMA</td>
+ *		<td>Direct Memory Access</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_dac_extra_dependencies Dependencies
+ * This driver has the following dependency:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_dac_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_dac_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_dac_exqsg Examples for DAC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_dac_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_dac_basic_use_case
+ * \if DAC_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_dac_basic_use_case_callback
+ * \endif
+ * \if DAC_DMA_USE_MODE_SELECTION
+ *  - \subpage asfdoc_sam0_adc_dma_use_case_dac_in_dma
+ * \endif
+ *
+ * \if DAC_DMA_USE_MODE_SELECTION
+ * \page asfdoc_sam0_adc_dma_use_case_dac_in_dma Quick Start Guide for Using DMA with ADC/DAC
+ * For this examples, see
+ * \ref asfdoc_sam0_adc_dma_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_dac_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42450A</td>
+ *		<td>07/2015</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* DAC_FEATURE_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.c
new file mode 100644
index 0000000000..9cbfbd78c3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.c
@@ -0,0 +1,473 @@
+/**
+ * \file
+ *
+ * \brief SAM Divide and Square Root Accelerator (DIVAS) Driver
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "divas.h"
+
+/**
+ * \internal
+ * \brief Initializes and enables the Divide and Square Root Accelerator (DIVAS) Driver.
+ *
+ * Enable the clocks used by Divide and Square Root Accelerator (DIVAS) Driver.
+ * Enable leading zero optimization.
+ *
+ * \note When SYSTEM module is used, this function will be invoked by
+ * \ref system_init() automatically if the module is included.
+ */
+void _system_divas_init(void);
+void _system_divas_init(void)
+{
+	/* Turn on the digital interface clock. */
+	system_ahb_clock_set_mask(MCLK_AHBMASK_DIVAS);
+
+	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_DLZ;
+}
+
+/**
+ * \brief Signed division operation
+ *
+ * Run the signed division operation and return the quotient.
+ *
+ * \param[in]  numerator   The dividend of the signed division operation
+ * \param[in]  denominator The divisor of the signed division operation
+ *
+ * \return The quotient of the DIVAS signed division operation.
+ */
+int32_t divas_idiv(int32_t numerator, int32_t denominator)
+{
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Signed division. */
+	DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
+
+	/* Write the dividend to DIVIDEND register. */
+	DIVAS->DIVIDEND.reg = numerator;
+	/* Write the divisor to DIVISOR register. */
+	DIVAS->DIVISOR.reg = denominator;
+
+	while(DIVAS->STATUS.bit.BUSY){
+		/* Wait the division is complete. */
+	}
+
+	int32_t quotient = DIVAS->RESULT.reg;
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return quotient;
+}
+
+/**
+ * \brief Unsigned division operation
+ *
+ * Run the unsigned division operation and return the results.
+ *
+ * \param[in]  numerator   The dividend of the unsigned division operation
+ * \param[in]  denominator The divisor of the unsigned division operation
+ *
+ * \return The quotient of the DIVAS unsigned division operation.
+ */
+uint32_t divas_uidiv(uint32_t numerator, uint32_t denominator)
+{
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Unsigned division. */
+	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
+
+	/* Write the dividend to DIVIDEND register. */
+	DIVAS->DIVIDEND.reg = numerator;
+	/* Write the divisor to DIVISOR register. */
+	DIVAS->DIVISOR.reg = denominator;
+
+	while(DIVAS->STATUS.bit.BUSY){
+		/* Wait the division is complete. */
+	}
+
+	uint32_t quotient = DIVAS->RESULT.reg;
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return quotient;
+}
+
+/**
+ * \brief Signed division remainder operation
+ *
+ * Run the signed division operation and return the remainder.
+ *
+ * \param[in]  numerator   The dividend of the signed division operation
+ * \param[in]  denominator The divisor of the signed division operation
+ *
+ * \return The remainder of the DIVAS signed division operation.
+ */
+int32_t divas_idivmod(int32_t numerator, int32_t denominator)
+{
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Signed division. */
+	DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
+
+	/* Write the dividend to DIVIDEND register. */
+	DIVAS->DIVIDEND.reg = numerator;
+	/* Write the divisor to DIVISOR register. */
+	DIVAS->DIVISOR.reg = denominator;
+
+	while(DIVAS->STATUS.bit.BUSY){
+		/* Wait the division is complete. */
+	}
+
+	int32_t remainder = DIVAS->REM.reg;
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return remainder;
+}
+
+/**
+ * \brief Unsigned division remainder operation
+ *
+ * Run the unsigned division operation and return the remainder.
+ *
+ * \param[in]  numerator   The dividend of the unsigned division operation
+ * \param[in]  denominator The divisor of the unsigned division operation
+ *
+ * \return The remainder of the DIVAS unsigned division operation.
+ */
+uint32_t divas_uidivmod(uint32_t numerator, uint32_t denominator)
+{
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Unsigned division. */
+	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
+
+	/* Write the dividend to DIVIDEND register. */
+	DIVAS->DIVIDEND.reg = numerator;
+	/* Write the divisor to DIVISOR register. */
+	DIVAS->DIVISOR.reg = denominator;
+
+	while(DIVAS->STATUS.bit.BUSY){
+		/* Wait the division is complete. */
+	}
+
+	uint32_t remainder = DIVAS->REM.reg;
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return remainder;
+}
+
+/**
+ * \brief Square root operation
+ *
+ * Run the square root operation and return the results.
+ *
+ * \param[in]  radicand  The radicand of the square root operation
+ *
+ * \return The result of the DIVAS square root operation.
+ */
+uint32_t  divas_sqrt(uint32_t radicand)
+{
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Write the radicand to DIVIDEND register. */
+	DIVAS->SQRNUM.reg = radicand;
+
+	while(DIVAS->STATUS.bit.BUSY){
+		/* Wait the square root is complete. */
+	}
+
+	uint32_t result_sqrt = DIVAS->RESULT.reg;
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return result_sqrt;
+}
+
+/**
+ * \name DIVAS Operation Overloading
+ * @{
+ */
+
+#if DIVAS_OVERLOAD_MODE == true
+#  if defined ( __GNUC__ )
+
+/**
+ * \brief Signed division operation overload
+ *
+ * Run the signed division operation and return the results.
+ *
+ * \param[in]  numerator   The dividend of the signed division operation
+ * \param[in]  denominator The divisor of the signed division operation
+ *
+ * \return The quotient of the DIVAS signed division operation.
+ */
+int32_t __aeabi_idiv(int32_t numerator, int32_t denominator)
+{
+	return divas_idiv(numerator, denominator);
+}
+
+/**
+ * \brief Unsigned division operation overload
+ *
+ * Run the unsigned division operation and return the results.
+ *
+ * \param[in]  numerator   The dividend of the unsigned division operation
+ * \param[in]  denominator The divisor of the unsigned division operation
+ *
+ * \return The quotient of the DIVAS unsigned division operation.
+ */
+uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator)
+{
+	return divas_uidiv(numerator, denominator);
+}
+
+/**
+ * \brief Signed division remainder operation overload
+ *
+ * Run the signed division operation and return the remainder.
+ *
+ * \param[in]  numerator   The dividend of the signed division operation
+ * \param[in]  denominator The divisor of the signed division operation
+ *
+ * \return The remainder of the DIVAS signed division operation.
+ */
+uint64_t __aeabi_idivmod(int32_t numerator, int32_t denominator)
+{
+	uint64_t uret;
+	int32_t quotient, remainder;
+
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Signed division. */
+	DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
+
+	/* Write the dividend to DIVIDEND register. */
+	DIVAS->DIVIDEND.reg = numerator;
+	/* Write the divisor to DIVISOR register. */
+	DIVAS->DIVISOR.reg = denominator;
+
+	while(DIVAS->STATUS.bit.BUSY){
+		/* Wait the division is complete. */
+	}
+
+	/* Read out the result. */
+	quotient = DIVAS->RESULT.reg;
+	remainder = DIVAS->REM.reg;
+
+	/* quotient in r0, remainder in r1 */
+	uret = ((uint64_t)quotient & 0x00000000FFFFFFFF ) |
+			(((uint64_t)remainder ) << 32);
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return uret;
+}
+
+/**
+ * \brief Unsigned division remainder operation overload
+ *
+ * Run the unsigned division operation and return the remainder.
+ *
+ * \param[in]  numerator   The dividend of the unsigned division operation
+ * \param[in]  denominator The divisor of the unsigned division operation
+ *
+ * \return The remainder of the DIVAS unsigned division operation.
+ */
+uint64_t __aeabi_uidivmod(uint32_t numerator, uint32_t denominator)
+{
+	uint64_t uret;
+	uint32_t quotient, remainder;
+
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Unsigned division. */
+	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
+
+	/* Write the dividend to DIVIDEND register. */
+	DIVAS->DIVIDEND.reg = numerator;
+	/* Write the divisor to DIVISOR register. */
+	DIVAS->DIVISOR.reg = denominator;
+
+	while(DIVAS->STATUS.bit.BUSY){
+	/* Wait the division is complete. */
+	}
+
+	/* Read out the result. */
+	quotient = DIVAS->RESULT.reg;
+	remainder = DIVAS->REM.reg;
+
+	/* quotient in r0, remainder in r1 */
+	uret = quotient | (((uint64_t)remainder) << 32);
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return uret;
+}
+
+#  elif defined ( __ICCARM__ )
+/**
+ * \brief Signed division operation overload
+ *
+ * Run the signed division operation and return the results.
+ *
+ * \param[in]  numerator   The dividend of the signed division operation
+ * \param[in]  denominator The divisor of the signed division operation
+ *
+ * \return The quotient of the DIVAS signed division operation.
+ */
+int32_t __aeabi_idiv(int32_t numerator, int32_t denominator)
+{
+	return divas_idiv(numerator, denominator);
+}
+
+/**
+ * \brief Unsigned division operation overload
+ *
+ * Run the unsigned division operation and return the results.
+ *
+ * \param[in]  numerator   The dividend of the unsigned division operation
+ * \param[in]  denominator The divisor of the unsigned division operation
+ *
+ * \return The quotient of the DIVAS unsigned division operation.
+ */
+uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator)
+{
+	return divas_uidiv(numerator, denominator);
+}
+
+/**
+ * \brief Signed division remainder operation overload
+ *
+ * Run the signed division operation and return the remainder.
+ * \param[in]  numerator   The dividend of the signed division operation
+ * \param[in]  denominator The divisor of the signed division operation
+ *
+ * \return The remainder of the DIVAS signed division operation.
+ */
+__value_in_regs idiv_return __aeabi_idivmod(int numerator, int denominator)
+{
+	idiv_return result;
+
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Signed division. */
+	DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
+
+	/* Write the dividend to DIVIDEND register. */
+	DIVAS->DIVIDEND.reg = numerator;
+	/* Write the divisor to DIVISOR register. */
+	DIVAS->DIVISOR.reg = denominator;
+
+	while(DIVAS->STATUS.bit.BUSY){
+		/* Wait the division is complete. */
+	}
+
+	/* Read out the result. */
+	result.quotient = DIVAS->RESULT.reg;
+	result.remainder = DIVAS->REM.reg;
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return result;
+}
+
+/**
+ * \brief Unsigned division remainder operation overload
+ *
+ * Run the unsigned division operation and return the remainder.
+ * \param[in]  numerator   The dividend of the unsigned division operation
+ * \param[in]  denominator The divisor of the unsigned division operation
+ *
+ * \return The remainder of the DIVAS unsigned division operation.
+ */
+__value_in_regs uidiv_return __aeabi_uidivmod(unsigned numerator, unsigned denominator)
+{
+	uidiv_return result;
+
+	/* Disable interrupt. */
+	cpu_irq_enter_critical();
+
+	/* Unsigned division. */
+	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
+
+	/* Write the dividend to DIVIDEND register. */
+	DIVAS->DIVIDEND.reg = numerator;
+	/* Write the divisor to DIVISOR register. */
+	DIVAS->DIVISOR.reg = denominator;
+
+	while(DIVAS->STATUS.bit.BUSY){
+		/* Wait the division is complete. */
+	}
+
+	/* Read out the result. */
+	result.quotient = DIVAS->RESULT.reg;
+	result.remainder = DIVAS->REM.reg;
+
+	/* Enable interrupt. */
+	cpu_irq_leave_critical();
+
+	return result;
+}
+
+#  endif
+#endif
+
+/** @} */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.h
new file mode 100644
index 0000000000..c2d9dd7492
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.h
@@ -0,0 +1,357 @@
+/**
+ * \file
+ *
+ * \brief SAM Divide and Square Root Accelerator (DIVAS) Driver
+ *
+ * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef DIVAS_H_INCLUDED
+#define DIVAS_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_divas_group SAM Divide and Square Root Accelerator (DIVAS) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an
+ * interface for the configuration and management of the device's Divide and
+ * Square Root Accelerator functionality.
+ *
+ * The following peripherals are used by this module:
+ *  - DIVAS (Divide and Square Root Accelerator)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM C20/C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_divas_prerequisites
+ *  - \ref asfdoc_sam0_divas_module_overview
+ *  - \ref asfdoc_sam0_divas_special_considerations
+ *  - \ref asfdoc_sam0_divas_extra_info
+ *  - \ref asfdoc_sam0_divas_examples
+ *  - \ref asfdoc_sam0_divas_api_overview
+ *
+ *
+ * \section asfdoc_sam0_divas_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_divas_module_overview Module Overview
+ *
+ * This driver provides an interface for the Divide and Square Root Accelerator
+ * on the device.
+ *
+ * The DIVAS is a programmable 32-bit signed or unsigned hardware divider and a 
+ * 32-bit unsigned square root hardware engine. When running signed division, 
+ * both the input and the result will be in two's complement format. The result of
+ * signed division is that the remainder has the same sign as the dividend and 
+ * the quotient is negative if the dividend and divisor have opposite signs.
+ * When the square root input register is programmed, the square root function 
+ * starts and the result will be stored in the Remainder register.
+ *
+ * There are two ways to calculate the results:
+ * - Call the DIVAS API
+ * - Overload "/" and "%" operation
+ * \note Square root operation can't implement overload operation.
+ 
+ * \subsection asfdoc_sam0_divas_module_overview_overload Overload Operation
+ * The operation is implemented automatically by EABI (Enhanced Application Binary 
+ * Interface). EABI is a standard calling convention, which is defined by ARM. 
+ * The four functions interface can implement division and mod operation in EABI.
+ *
+ * The following prototypes for EABI division operation in ICCARM tool chain:
+ * \code
+    int __aeabi_idiv(int numerator, int denominator);
+    unsigned __aeabi_uidiv(unsigned numerator, unsigned denominator);
+    __value_in_regs idiv_return __aeabi_idivmod( int numerator, int denominator);
+    __value_in_regs uidiv_return __aeabi_uidivmod( unsigned numerator, 
+												unsigned denominator);
+   \endcode
+ * The following prototypes for EABI division operation in GNUC tool chain:
+ * \code
+    int __aeabi_idiv(int numerator, int denominator);
+    unsigned __aeabi_uidiv(unsigned numerator, unsigned denominator);
+    uint64_t __aeabi_idivmod( int numerator, int denominator);
+    uint64_t uidiv_return __aeabi_uidivmod( unsigned numerator, 
+											unsigned denominator);
+   \endcode
+ * No matter what kind of tool chain, by using DIVAS module in the four functions 
+ * body, the user can transparently access the DIVAS module when writing normal C 
+ * code. For example:
+ * \code
+    void division(int32_t b, int32_t c)
+    {
+        int32_t a;
+        a = b / c;
+        return a;
+    }
+   \endcode
+ * Similarly, the user can use the "a = b % c;" symbol to implement the operation with 
+ * DIVAS, and needn't to care about the internal operation process.
+ * 
+ * \subsection asfdoc_sam0_divas_module_overview_operand Operand Size
+ *  - Divide: The DIVAS can perform 32-bit signed and unsigned division.
+ *  - Square Root: The DIVAS can perform 32-bit unsigned division.
+ 
+ * \subsection asfdoc_sam0_divas_module_overview_Signed Signed Division
+ *  When the signed flag is one, both the input and the result will be in two's 
+ *  complement format. The result of signed division is that the remainder has 
+ *  the same sign as the dividend and the quotient is negative if the dividend 
+ *  and divisor have opposite signs.
+ *  \note When the maximum negative number is divided by the minimum negative 
+ *  number, the resulting quotient overflows the signed integer range and will 
+ *  return the maximum negative number with no indication of the overflow. This 
+ *  occurs for 0x80000000 / 0xFFFFFFFF in 32-bit operation and 0x8000 / 0xFFFF 
+ *  in 16-bit operation.
+ *
+ * \subsection asfdoc_sam0_divas_module_overview_zero Divide By Zero
+ *  A divide by zero will cause a fault if the DIVISOR is programmed to zero. The 
+ *  result is that the quotient is zero and the reminder is equal to the dividend.
+ *
+ * \subsection asfdoc_sam0_divas_module_overview_square Unsigned Square Root
+ *  When the square root input register is programmed, the square root function 
+ *  starts and the result will be stored in the Result and Remainder registers.
+ * \note The square root function can't overload.
+ *
+ * \section asfdoc_sam0_divas_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_sam0_divas_extra_info Extra Information
+ *
+ *
+ * For extra information, see \ref asfdoc_sam0_divas_extra. This includes:
+ *  - \ref asfdoc_sam0_divas_extra_acronyms
+ *  - \ref asfdoc_sam0_divas_extra_dependencies
+ *  - \ref asfdoc_sam0_divas_extra_errata
+ *  - \ref asfdoc_sam0_divas_extra_history
+ *
+ *
+ * \section asfdoc_sam0_divas_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_divas_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_divas_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief DIVAS signed division operator result output structure.
+ *
+ *  DIVAS signed division operator output data structure.
+ */
+typedef struct {
+	/** Signed division operator result: quotient */
+	int32_t quotient; 
+	/** Signed division operator result: remainder */
+	int32_t remainder;
+} idiv_return;
+
+/**
+ * \brief DIVAS unsigned division operator result output structure.
+ *
+ *  DIVAS unsigned division operator output data structure.
+ */
+typedef struct {
+	/** Unsigned division operator result: quotient */
+	uint32_t quotient; 
+	/** Unsigned division operator result: remainder */
+	uint32_t remainder;
+} uidiv_return; 
+
+/**
+ * \brief Enables DIVAS leading zero optimization.
+ *
+ *  Enable leading zero optimization from the Divide and Square Root Accelerator
+ *  module. When leading zero optimization is enable, 16-bit division completes 
+ *  in 2-8 cycles and 32-bit division completes in 2-16 cycles.
+ *
+ */
+static inline void divas_enable_dlz(void)
+{
+	/* Enable DLZ. */
+	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_DLZ;
+}
+
+/**
+ * \brief Disables DIVAS leading zero optimization.
+ *
+ *  Disable leading zero optimization from the Divide and Square Root Accelerator
+ *  module. When leading zero optimization is disable, 16-bit division completes 
+ *  in 8 cycles and 32-bit division completes in 16 cycles.
+ *
+ */
+static inline void divas_disable_dlz(void)
+{
+	/* Disable DLZ. */
+	DIVAS->CTRLA.reg |= DIVAS_CTRLA_DLZ;
+}
+
+/**
+ * \name Call the DIVAS API Operation
+ * @{
+ * In this mode, the way that directly call the DIVAS API implement division or 
+ * mod operation. 
+ */
+
+int32_t divas_idiv(int32_t numerator, int32_t denominator);
+uint32_t divas_uidiv(uint32_t numerator, uint32_t denominator);
+int32_t divas_idivmod(int32_t numerator, int32_t denominator);
+uint32_t divas_uidivmod(uint32_t numerator, uint32_t denominator);
+uint32_t divas_sqrt(uint32_t radicand);
+
+/** @} */
+
+/**
+ * \name DIVAS Overload '/' and '%' Operation
+ * @{
+ * In this mode, the user can transparently access the DIVAS module when writing 
+ * normal C code. E.g. "a = b / c;" or "a = b % c;" will be translated to a 
+ * subroutine call, which uses the DIVAS.
+ */
+
+#if DIVAS_OVERLOAD_MODE == true
+#  if defined ( __GNUC__ )
+int32_t __aeabi_idiv(int32_t numerator, int32_t denominator);
+uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator);
+uint64_t __aeabi_idivmod(int32_t numerator, int32_t denominator);
+uint64_t __aeabi_uidivmod(uint32_t numerator, uint32_t denominator);
+
+#  elif defined ( __ICCARM__ )
+int32_t __aeabi_idiv(int32_t numerator, int32_t denominator);
+uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator);
+__value_in_regs idiv_return __aeabi_idivmod(int numerator, int denominator);
+__value_in_regs uidiv_return __aeabi_uidivmod(unsigned numerator, unsigned denominator); 
+#  endif
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_divas_extra Extra Information for DIVAS Driver
+ *
+ * \section asfdoc_sam0_divas_extra_acronyms Acronyms
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>DIVAS</td>
+ *		<td>Divide and Square Root Accelerator</td>
+ *	</tr>
+ *  <tr>
+ *		<td>EABI</td>
+ *		<td>Enhanced Application Binary Interface</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_divas_extra_dependencies Dependencies
+ * This driver has no dependencies.
+ *
+ *
+ * \section asfdoc_sam0_divas_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_divas_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+  *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_divas_exqsg Examples for DIVAS Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_divas_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_divas_basic_use_case
+ *  - \subpage asfdoc_sam0_divas_overload_use_case
+ *
+ * \page asfdoc_sam0_divas_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42644A</td>
+ *		<td>01/2016</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* DIVAS_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.c
new file mode 100644
index 0000000000..23592cda31
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.c
@@ -0,0 +1,654 @@
+/*
+ * \file
+ *
+ * \brief SAM Direct Memory Access Controller Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <string.h>
+#include "dma.h"
+#include "clock.h"
+#include "system_interrupt.h"
+
+struct _dma_module {
+	volatile bool _dma_init;
+	volatile uint32_t allocated_channels;
+	uint8_t free_channels;
+};
+
+struct _dma_module _dma_inst = {
+	._dma_init = false,
+	.allocated_channels = 0,
+	.free_channels = CONF_MAX_USED_CHANNEL_NUM,
+};
+
+/** Maximum retry counter for resuming a job transfer. */
+#define MAX_JOB_RESUME_COUNT    10000
+
+/** DMA channel mask. */
+#define DMA_CHANNEL_MASK   (0x1f)
+
+COMPILER_ALIGNED(16)
+DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
+
+/** Initial write back memory section. */
+COMPILER_ALIGNED(16)
+static DmacDescriptor _write_back_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
+
+/** Internal DMA resource pool. */
+static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
+
+/* DMA channel interrup flag. */
+uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]={0};
+
+/**
+ * \brief Find a free channel for a DMA resource.
+ *
+ * Find a channel for the requested DMA resource.
+ *
+ * \return Status of channel allocation.
+ * \retval DMA_INVALID_CHANNEL  No channel available
+ * \retval count          Allocated channel for the DMA resource
+ */
+static uint8_t _dma_find_first_free_channel_and_allocate(void)
+{
+	uint8_t count;
+	uint32_t tmp;
+	bool allocated = false;
+
+	system_interrupt_enter_critical_section();
+
+	tmp = _dma_inst.allocated_channels;
+
+	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
+		if (!(tmp & 0x00000001)) {
+			/* If free channel found, set as allocated and return
+			 *number */
+
+			_dma_inst.allocated_channels |= 1 << count;
+			_dma_inst.free_channels--;
+			allocated = true;
+
+			break;
+		}
+
+		tmp = tmp >> 1;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	if (!allocated) {
+		return DMA_INVALID_CHANNEL;
+	} else {
+		return count;
+	}
+}
+
+/**
+ * \brief Release an allocated DMA channel.
+ *
+ * \param[in]  channel  Channel id to be released
+ *
+ */
+static void _dma_release_channel(uint8_t channel)
+{
+	_dma_inst.allocated_channels &= ~(1 << channel);
+	_dma_inst.free_channels++;
+}
+
+/**
+ * \brief Configure the DMA resource.
+ *
+ * \param[in]  dma_resource Pointer to a DMA resource instance
+ * \param[out] resource_config Configurations of the DMA resource
+ *
+ */
+static void _dma_set_config(struct dma_resource *resource,
+		struct dma_resource_config *resource_config)
+{
+	Assert(resource);
+	Assert(resource_config);
+	uint32_t temp_CHCTRLB_reg;
+	system_interrupt_enter_critical_section();
+
+	/** Select the DMA channel and clear software trigger */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
+
+	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
+			DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
+			DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
+
+
+	if(resource_config->event_config.input_action){
+	temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
+				resource_config->event_config.input_action);
+	}
+
+	/** Enable event output, the event output selection is configured in
+	 * each transfer descriptor  */
+	if (resource_config->event_config.event_output_enable) {
+		temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
+	}
+
+	/* Write config to CTRLB register */
+	DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
+
+
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief DMA interrupt service routine.
+ *
+ */
+void DMAC_Handler( void )
+{
+	uint8_t active_channel;
+	struct dma_resource *resource;
+	uint8_t isr;
+	uint32_t write_size;
+	uint32_t total_size;
+
+	system_interrupt_enter_critical_section();
+
+	/* Get Pending channel */
+	active_channel =  DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
+
+	Assert(_dma_active_resource[active_channel]);
+
+	/* Get active DMA resource based on channel */
+	resource = _dma_active_resource[active_channel];
+
+	/* Select the active channel */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	isr = DMAC->CHINTFLAG.reg;
+
+	/* Calculate block transfer size of the DMA transfer */
+	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+	resource->transfered_size = total_size - write_size;
+
+	/* DMA channel interrupt handler */
+	if (isr & DMAC_CHINTENCLR_TERR) {
+		/* Clear transfer error flag */
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
+
+		/* Set I/O ERROR status */
+		resource->job_status = STATUS_ERR_IO;
+
+		/* Execute the callback function */
+		if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
+				(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
+			resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
+		}
+	} else if (isr & DMAC_CHINTENCLR_TCMPL) {
+		/* Clear the transfer complete flag */
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
+
+		/* Set job status */
+		resource->job_status = STATUS_OK;
+
+		/* Execute the callback function */
+		if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
+				(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
+			resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
+		}
+	} else if (isr & DMAC_CHINTENCLR_SUSP) {
+		/* Clear channel suspend flag */
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
+
+		/* Set job status */
+		resource->job_status = STATUS_SUSPEND;
+
+		/* Execute the callback function */
+		if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
+			(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
+			resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
+		}
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given DMA configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structure before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Software trigger is used as the transfer trigger
+ *  \li Priority level 0
+ *  \li Only software/event trigger
+ *  \li Requires a trigger for each transaction
+ *  \li No event input /output
+ *  \li DMA channel is disabled during sleep mode (if has the feature)
+ * \param[out] config Pointer to the configuration
+ *
+ */
+void dma_get_config_defaults(struct dma_resource_config *config)
+{
+	Assert(config);
+	/* Set as priority 0 */
+	config->priority = DMA_PRIORITY_LEVEL_0;
+	/* Only software/event trigger */
+	config->peripheral_trigger = 0;
+	/* Transaction trigger */
+	config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
+
+	/* Event configurations, no event input/output */
+	config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
+	config->event_config.event_output_enable = false;
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+	config->run_in_standby = false;
+#endif
+}
+
+/**
+ * \brief Allocate a DMA with configurations.
+ *
+ * This function will allocate a proper channel for a DMA transfer request.
+ *
+ * \param[in,out]  dma_resource Pointer to a DMA resource instance
+ * \param[in] transfer_config Configurations of the DMA transfer
+ *
+ * \return Status of the allocation procedure.
+ *
+ * \retval STATUS_OK The DMA resource was allocated successfully
+ * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
+ */
+enum status_code dma_allocate(struct dma_resource *resource,
+		struct dma_resource_config *config)
+{
+	uint8_t new_channel;
+
+	Assert(resource);
+
+	system_interrupt_enter_critical_section();
+
+	if (!_dma_inst._dma_init) {
+		/* Initialize clocks for DMA */
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+		system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
+#else
+		system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
+				PM_APBBMASK_DMAC);
+#endif
+
+		/* Perform a software reset before enable DMA controller */
+		DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+		DMAC->CTRL.reg = DMAC_CTRL_SWRST;
+
+		/* Setup descriptor base address and write back section base
+		 * address */
+		DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
+		DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
+
+		/* Enable all priority level at the same time */
+		DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
+
+		_dma_inst._dma_init = true;
+	}
+
+	/* Find the proper channel */
+	new_channel = _dma_find_first_free_channel_and_allocate();
+
+	/* If no channel available, return not found */
+	if (new_channel == DMA_INVALID_CHANNEL) {
+		system_interrupt_leave_critical_section();
+
+		return STATUS_ERR_NOT_FOUND;
+	}
+
+	/* Set the channel */
+	resource->channel_id = new_channel;
+
+	/** Perform a reset for the allocated channel */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+	if(config->run_in_standby){
+		DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	}
+#endif
+
+	/** Configure the DMA control,channel registers and descriptors here */
+	_dma_set_config(resource, config);
+
+	resource->descriptor = NULL;
+
+	/* Log the DMA resource into the internal DMA resource pool */
+	_dma_active_resource[resource->channel_id] = resource;
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Free an allocated DMA resource.
+ *
+ * This function will free an allocated DMA resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ * \return Status of the free procedure.
+ *
+ * \retval STATUS_OK The DMA resource was freed successfully
+ * \retval STATUS_BUSY The DMA resource was busy and can't be freed
+ * \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized
+ */
+enum status_code dma_free(struct dma_resource *resource)
+{
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if channel is busy */
+	if (dma_is_busy(resource)) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Check if DMA resource was not allocated */
+	if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
+		system_interrupt_leave_critical_section();
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* Release the DMA resource */
+	_dma_release_channel(resource->channel_id);
+
+	/* Reset the item in the DMA resource pool */
+	_dma_active_resource[resource->channel_id] = NULL;
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Start a DMA transfer.
+ *
+ * This function will start a DMA transfer through an allocated DMA resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ * \return Status of the transfer start procedure.
+ *
+ * \retval STATUS_OK The transfer was started successfully
+ * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
+ * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
+ */
+enum status_code dma_start_transfer_job(struct dma_resource *resource)
+{
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if resource was busy */
+	if (resource->job_status == STATUS_BUSY) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Check if transfer size is valid */
+	if (resource->descriptor->BTCNT.reg == 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Enable DMA interrupt */
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
+
+	/* Set the interrupt flag */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
+	/* Set job status */
+	resource->job_status = STATUS_BUSY;
+
+	/* Set channel x descriptor 0 to the descriptor base address */
+	memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
+						sizeof(DmacDescriptor));
+
+	/* Enable the transfer channel */
+	DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Abort a DMA transfer.
+ *
+ * This function will abort a DMA transfer. The DMA channel used for the DMA
+ * resource will be disabled.
+ * The block transfer count will also be calculated and written to the DMA
+ * resource structure.
+ *
+ * \note The DMA resource will not be freed after calling this function.
+ *       The function \ref dma_free() can be used to free an allocated resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ */
+void dma_abort_job(struct dma_resource *resource)
+{
+	uint32_t write_size;
+	uint32_t total_size;
+
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->CHCTRLA.reg = 0;
+
+	system_interrupt_leave_critical_section();
+
+	/* Get transferred size */
+	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+	resource->transfered_size = total_size - write_size;
+
+	resource->job_status = STATUS_ABORTED;
+}
+
+/**
+ * \brief Suspend a DMA transfer.
+ *
+ * This function will request to suspend the transfer of the DMA resource.
+ * The channel is kept enabled, can receive transfer triggers (the transfer
+ * pending bit will be set), but will be removed from the arbitration scheme.
+ * The channel operation can be resumed by calling \ref dma_resume_job().
+ *
+ * \note This function sets the command to suspend the DMA channel
+ * associated with a DMA resource. The channel suspend interrupt flag
+ * indicates whether the transfer is truly suspended.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ */
+void dma_suspend_job(struct dma_resource *resource)
+{
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the channel */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+
+	/* Send the suspend request */
+	DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Resume a suspended DMA transfer.
+ *
+ * This function try to resume a suspended transfer of a DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ */
+void dma_resume_job(struct dma_resource *resource)
+{
+	uint32_t bitmap_channel;
+	uint32_t count = 0;
+
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	/* Get bitmap of the allocated DMA channel */
+	bitmap_channel = (1 << resource->channel_id);
+
+	/* Check if channel was suspended */
+	if (resource->job_status != STATUS_SUSPEND) {
+		return;
+	}
+
+	system_interrupt_enter_critical_section();
+
+	/* Send resume request */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+
+	system_interrupt_leave_critical_section();
+
+	/* Check if transfer job resumed */
+	for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
+		if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
+			break;
+		}
+	}
+
+	if (count < MAX_JOB_RESUME_COUNT) {
+		/* Job resumed */
+		resource->job_status = STATUS_BUSY;
+	} else {
+		/* Job resume timeout */
+		resource->job_status = STATUS_ERR_TIMEOUT;
+	}
+}
+
+/**
+ * \brief Create a DMA transfer descriptor with configurations.
+ *
+ * This function will set the transfer configurations to the DMA transfer
+ * descriptor.
+ *
+ * \param[in] descriptor Pointer to the DMA transfer descriptor
+ * \param[in] config Pointer to the descriptor configuration structure
+ *
+ */
+void dma_descriptor_create(DmacDescriptor* descriptor,
+	struct dma_descriptor_config *config)
+{
+	/* Set block transfer control */
+	descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
+	descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
+	descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
+	descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
+	descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
+	descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
+	descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
+	descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
+
+	/* Set transfer size, source address and destination address */
+	descriptor->BTCNT.reg = config->block_transfer_count;
+	descriptor->SRCADDR.reg = config->source_address;
+	descriptor->DSTADDR.reg = config->destination_address;
+
+	/* Set next transfer descriptor address */
+	descriptor->DESCADDR.reg = config->next_descriptor_address;
+}
+
+/**
+ * \brief Add a DMA transfer descriptor to a DMA resource.
+ *
+ * This function will add a DMA transfer descriptor to a DMA resource.
+ * If there was a transfer descriptor already allocated to the DMA resource,
+ * the descriptor will be linked to the next descriptor address.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] descriptor Pointer to the transfer descriptor
+ *
+ * \retval STATUS_OK The descriptor is added to the DMA resource
+ * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
+ */
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+		DmacDescriptor* descriptor)
+{
+	DmacDescriptor* desc = resource->descriptor;
+
+	if (resource->job_status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Look up for an empty space for the descriptor */
+	if (desc == NULL) {
+		resource->descriptor = descriptor;
+	} else {
+		/* Looking for end of descriptor link */
+		while(desc->DESCADDR.reg != 0) {
+			desc = (DmacDescriptor*)(desc->DESCADDR.reg);
+		}
+
+		/* Set to the end of descriptor list */
+		desc->DESCADDR.reg = (uint32_t)descriptor;
+	}
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.h
new file mode 100644
index 0000000000..6aea77a9d0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.h
@@ -0,0 +1,883 @@
+/**
+ * \file
+ *
+ * \brief SAM Direct Memory Access Controller Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DMA_H_INCLUDED
+#define DMA_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_dma_group SAM Direct Memory Access Controller (DMAC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM庐-based microcontrollers provides an interface for the configuration
+ * and management of the Direct Memory Access Controller(DMAC) module within
+ * the device. The DMAC can transfer data between memories and peripherals, and
+ * thus off-load these tasks from the CPU. The module supports peripheral to
+ * peripheral, peripheral to memory, memory to peripheral, and memory to memory
+ * transfers.
+ *
+ * The following peripheral is used by the DMAC Driver:
+ * - DMAC (Direct Memory Access Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_dma_prerequisites
+ * - \ref asfdoc_sam0_dma_module_overview
+ * - \ref asfdoc_sam0_dma_special_considerations
+ * - \ref asfdoc_sam0_dma_extra_info
+ * - \ref asfdoc_sam0_dma_examples
+ * - \ref asfdoc_sam0_dma_api_overview
+ *
+ *
+ * \section asfdoc_sam0_dma_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_dma_module_overview Module Overview
+ *
+ * SAM devices with DMAC enables high data transfer rates with minimum
+ * CPU intervention and frees up CPU time. With access to all peripherals,
+ * the DMAC can handle automatic transfer of data to/from modules.
+ * It supports static and incremental addressing for both source and
+ * destination.
+ *
+ * The DMAC when used with Event System or peripheral triggers, provides a
+ * considerable advantage by reducing the power consumption and performing
+ * data transfer in the background.
+ * For example, if the ADC is configured to generate an event, it can trigger
+ * the DMAC to transfer the data into another peripheral or SRAM.
+ * The CPU can remain in sleep during this time to reduce the power consumption.
+ *
+ * <table>
+ *    <tr>
+ *      <th>Device</th>
+ *      <th>Dma channel number</th>
+ *    </tr>
+ *    <tr>
+ *      <td>SAM D21/R21/C20/C21</td>
+ *      <td>12</td>
+ *    </tr>
+ *    <tr>
+ *      <td>SAM D09/D10/D11</td>
+ *      <td>6</td>
+ *    </tr>
+ *    <tr>
+ *      <td>SAM L21,SAMR30</td>
+ *      <td>16</td>
+ *    </tr>
+ * </table>
+ * The DMA channel operation can be suspended at any time by software, by events
+ * from event system, or after selectable descriptor execution. The operation
+ * can be resumed by software or by events from the event system.
+ * The DMAC driver for SAM supports four types of transfers such as
+ * peripheral to peripheral, peripheral to memory, memory to peripheral, and
+ * memory to memory.
+ *
+ * The basic transfer unit is a beat, which is defined as a single bus access.
+ * There can be multiple beats in a single block transfer and multiple block
+ * transfers in a DMA transaction.
+ * DMA transfer is based on descriptors, which holds transfer properties
+ * such as the source and destination addresses, transfer counter, and other
+ * additional transfer control information.
+ * The descriptors can be static or linked. When static, a single block transfer
+ * is performed. When linked, a number of transfer descriptors can be used to
+ * enable multiple block transfers within a single DMA transaction.
+ *
+ * The implementation of the DMA driver is based on the idea that the DMA channel
+ * is a finite resource of entities with the same abilities. A DMA channel resource
+ * is able to move a defined set of data from a source address to destination
+ * address triggered by a transfer trigger. On the SAM devices there are 12
+ * DMA resources available for allocation. Each of these DMA resources can trigger
+ * interrupt callback routines and peripheral events.
+ * The other main features are:
+ *
+ * - Selectable transfer trigger source
+ *  - Software
+ *  - Event System
+ *  - Peripheral
+ * - Event input and output is supported for the four lower channels
+ * - Four level channel priority
+ * - Optional interrupt generation on transfer complete, channel error, or channel suspend
+ * - Supports multi-buffer or circular buffer mode by linking multiple descriptors
+ * - Beat size configurable as 8-bit, 16-bit, or 32-bit
+ *
+ * A simplified block diagram of the DMA Resource can be seen in
+ * \ref asfdoc_sam0_dma_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_dma_module_block_diagram
+ * \dot
+ * digraph overview {
+ * splines = false;
+ * rankdir=LR;
+ *
+ * mux1 [label="Transfer Trigger", shape=box];
+ *
+ * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * mux1 -> dma;
+ * descriptor -> dma;
+ *
+ * interrupt [label="Interrupt", shape=box];
+ * events [label="Events", shape=box];
+ *
+ * dma:e -> interrupt:w;
+ * dma:e -> events:w;
+ *
+ * {rank=same; descriptor dma}
+ *
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_dma_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_DMA_CHANNEL_STANDBY</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_transf_term Terminology Used in DMAC Transfers
+ *
+ *   <table border="0" cellborder="1" cellspacing="0" >
+ *    <tr>
+ *        <th> Name </th> <th> Description </th>
+ *    </tr>
+ *    <tr>
+ *     <td > Beat </td>
+ *     <td > It is a single bus access by the DMAC.
+ *           Configurable as 8-bit, 16-bit, or 32-bit.
+ *     </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Burst </td>
+ *     <td> It is a transfer of n-beats (n=1,4,8,16).
+ *          For the DMAC module in SAM, the burst size is one beat.
+ *          Arbitration takes place each time a burst transfer is completed.
+ *     </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Block transfer </td>
+ *     <td>  A single block transfer is a configurable number of (1 to 64k)
+ *           beat transfers
+ *     </td>
+ *    </tr>
+ *   </table>
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_channels DMA Channels
+ * The DMAC in each device consists of several DMA channels, which
+ * along with the transfer descriptors defines the data transfer properties.
+ * - The transfer control descriptor defines the source and destination
+ * addresses, source and destination address increment settings, the
+ * block transfer count, and event output condition selection
+ * - Dedicated channel registers control the peripheral trigger source,
+ * trigger mode settings, event input actions, and channel priority level
+ * settings
+ *
+ * With a successful DMA resource allocation, a dedicated
+ * DMA channel will be assigned. The channel will be occupied until the
+ * DMA resource is freed. A DMA resource handle is used to identify the specific
+ * DMA resource.
+ * When there are multiple channels with active requests, the arbiter prioritizes
+ * the channels requesting access to the bus.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_trigger DMA Triggers
+ * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A
+ * transfer request can be triggered from software, peripheral, or an event. There
+ * are dedicated source trigger selections for each DMA channel usage.
+
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor
+ * The transfer descriptor resides in the SRAM and
+ * defines these channel properties.
+ *   <table border="0" cellborder="1" cellspacing="0" >
+ *    <tr>
+ *        <th> Field name </th> <th> Field width </th>
+ *    </tr>
+ *    <tr>
+ *     <td > Descriptor Next Address </td> <td > 32 bits </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Destination Address </td> <td> 32 bits </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Source Address </td> <td> 32 bits </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Block Transfer Counter </td> <td> 16 bits </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Block Transfer Control </td> <td> 16 bits </td>
+ *    </tr>
+ *   </table>
+ *
+ * Before starting a transfer, at least one descriptor should be configured.
+ * After a successful allocation of a DMA channel, the transfer descriptor can
+ * be added with a call to \ref dma_add_descriptor(). If there is a transfer
+ * descriptor already allocated to the DMA resource, the descriptor will
+ * be linked to the next descriptor address.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_output DMA Interrupts/Events
+ * Both an interrupt callback and an peripheral event can be triggered by the
+ * DMA transfer. Three types of callbacks are supported by the DMA driver:
+ * transfer complete, channel suspend, and transfer error. Each of these callback
+ * types can be registered and enabled for each channel independently through
+ * the DMA driver API.
+ *
+ * The DMAC module can also generate events on transfer complete. Event
+ * generation is enabled through the DMA channel, event channel configuration,
+ * and event user multiplexing is done through the events driver.
+ *
+ * The DMAC can generate events in the below cases:
+ *
+ * - When a block transfer is complete
+ *
+ * - When each beat transfer within a block transfer is complete
+ *
+ * \section asfdoc_sam0_dma_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_dma_extra. This includes:
+ * - \ref asfdoc_sam0_dma_extra_acronyms
+ * - \ref asfdoc_sam0_dma_extra_dependencies
+ * - \ref asfdoc_sam0_dma_extra_errata
+ * - \ref asfdoc_sam0_dma_extra_history
+ *
+ *
+ * \section asfdoc_sam0_dma_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_dma_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_dma_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include "conf_dma.h"
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+#define FEATURE_DMA_CHANNEL_STANDBY
+#endif
+
+/** DMA invalid channel number. */
+#define DMA_INVALID_CHANNEL        0xff
+
+/** ExInitial description section. */
+extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM];
+
+/* DMA channel interrup flag. */
+extern uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM];
+
+/** DMA priority level. */
+enum dma_priority_level {
+	/** Priority level 0. */
+	DMA_PRIORITY_LEVEL_0,
+	/** Priority level 1. */
+	DMA_PRIORITY_LEVEL_1,
+	/** Priority level 2. */
+	DMA_PRIORITY_LEVEL_2,
+	/** Priority level 3. */
+	DMA_PRIORITY_LEVEL_3,
+};
+
+/** DMA input actions. */
+enum dma_event_input_action {
+	/** No action. */
+	DMA_EVENT_INPUT_NOACT,
+	/** Normal transfer and periodic transfer trigger. */
+	DMA_EVENT_INPUT_TRIG,
+	/** Conditional transfer trigger. */
+	DMA_EVENT_INPUT_CTRIG,
+	/** Conditional block transfer. */
+	DMA_EVENT_INPUT_CBLOCK,
+	/** Channel suspend operation. */
+	DMA_EVENT_INPUT_SUSPEND,
+	/** Channel resume operation. */
+	DMA_EVENT_INPUT_RESUME,
+	/** Skip next block suspend action. */
+	DMA_EVENT_INPUT_SSKIP,
+};
+
+/**
+ * Address increment step size. These bits select the address increment step
+ * size. The setting apply to source or destination address, depending on
+ * STEPSEL setting.
+ */
+enum dma_address_increment_stepsize {
+	/** The address is incremented by (beat size * 1). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
+	/** The address is incremented by (beat size * 2). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
+	/** The address is incremented by (beat size * 4). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
+	/** The address is incremented by (beat size * 8). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
+	/** The address is incremented by (beat size * 16). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
+	/** The address is incremented by (beat size * 32). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
+	/** The address is incremented by (beat size * 64). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
+	/** The address is incremented by (beat size * 128). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
+};
+
+/**
+ * DMA step selection. This bit determines whether the step size setting
+ * is applied to source or destination address.
+ */
+enum dma_step_selection {
+	/** Step size settings apply to the destination address. */
+	DMA_STEPSEL_DST = 0,
+	/** Step size settings apply to the source address. */
+	DMA_STEPSEL_SRC,
+};
+
+/** The basic transfer unit in DMAC is a beat, which is defined as a
+ *  single bus access. Its size is configurable and applies to both read
+ *  and write. */
+enum dma_beat_size {
+	/** 8-bit access. */
+	DMA_BEAT_SIZE_BYTE = 0,
+	/** 16-bit access. */
+	DMA_BEAT_SIZE_HWORD,
+	/** 32-bit access. */
+	DMA_BEAT_SIZE_WORD,
+};
+
+/**
+ * Block action definitions.
+ */
+enum dma_block_action {
+	/** No action. */
+	DMA_BLOCK_ACTION_NOACT = 0,
+	/** Channel in normal operation and sets transfer complete interrupt flag
+	 *  after block transfer. */
+	DMA_BLOCK_ACTION_INT,
+	/** Trigger channel suspend after block transfer and sets channel
+	 *  suspend interrupt flag once the channel is suspended. */
+	DMA_BLOCK_ACTION_SUSPEND,
+	/** Sets transfer complete interrupt flag after a block transfer and
+	 *  trigger channel suspend. The channel suspend interrupt flag will be set
+	 *  once the channel is suspended. */
+	DMA_BLOCK_ACTION_BOTH,
+};
+
+/** Event output selection. */
+enum dma_event_output_selection {
+	/** Event generation disable. */
+	DMA_EVENT_OUTPUT_DISABLE = 0,
+	/** Event strobe when block transfer complete. */
+	DMA_EVENT_OUTPUT_BLOCK,
+	/** Event output reserved. */
+	DMA_EVENT_OUTPUT_RESERVED,
+	/** Event strobe when beat transfer complete. */
+	DMA_EVENT_OUTPUT_BEAT,
+};
+
+/** DMA trigger action type. */
+enum dma_transfer_trigger_action{
+	/** Perform a block transfer when triggered. */
+	DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
+	/** Perform a beat transfer when triggered. */
+	DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
+	/** Perform a transaction when triggered. */
+	DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
+};
+
+/**
+ * Callback types for DMA callback driver.
+ */
+enum dma_callback_type {
+	/** Callback for any of transfer errors. A transfer error is flagged
+     *	if a bus error is detected during an AHB access or when the DMAC
+	 *  fetches an invalid descriptor. */
+	DMA_CALLBACK_TRANSFER_ERROR,
+	/** Callback for transfer complete. */
+	DMA_CALLBACK_TRANSFER_DONE,
+	/** Callback for channel suspend. */
+	DMA_CALLBACK_CHANNEL_SUSPEND,
+	/** Number of available callbacks. */
+	DMA_CALLBACK_N,
+};
+
+/**
+ * DMA transfer descriptor configuration. When the source or destination address
+ * increment is enabled, the addresses stored into the configuration structure
+ * must correspond to the end of the transfer.
+ *
+ */
+struct dma_descriptor_config {
+	/** Descriptor valid flag used to identify whether a descriptor is
+	    valid or not */
+	bool descriptor_valid;
+	/** This is used to generate an event on specific transfer action in
+	    a channel. Supported only in four lower channels. */
+	enum dma_event_output_selection event_output_selection;
+	/** Action taken when a block transfer is completed */
+	enum dma_block_action block_action;
+	/** Beat size is configurable as 8-bit, 16-bit, or 32-bit */
+	enum dma_beat_size beat_size;
+	/** Used for enabling the source address increment */
+	bool src_increment_enable;
+	/** Used for enabling the destination address increment */
+	bool dst_increment_enable;
+	/** This bit selects whether the source or destination address is
+	    using the step size settings */
+	enum dma_step_selection step_selection;
+	/** The step size for source/destination address increment.
+	    The next address is calculated
+	    as next_addr = addr + (2^step_size * beat size). */
+	enum dma_address_increment_stepsize step_size;
+	/** It is the number of beats in a block. This count value is
+	 * decremented by one after each beat data transfer. */
+	uint16_t block_transfer_count;
+	/** Transfer source address */
+	uint32_t source_address;
+	/** Transfer destination address */
+	uint32_t destination_address;
+	/** Set to zero for static descriptors. This must have a valid memory
+	    address for linked descriptors. */
+	uint32_t next_descriptor_address;
+};
+
+/** Configurations for DMA events. */
+struct dma_events_config {
+	/** Event input actions */
+	enum dma_event_input_action input_action;
+	/** Enable DMA event output */
+	bool event_output_enable;
+};
+
+/** DMA configurations for transfer. */
+struct dma_resource_config {
+	/** DMA transfer priority */
+	enum dma_priority_level priority;
+	/**DMA peripheral trigger index */
+	uint8_t peripheral_trigger;
+	/** DMA trigger action */
+	enum dma_transfer_trigger_action trigger_action;
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+	/** Keep DMA channel enabled in standby sleep mode if true */
+	bool run_in_standby;
+#endif
+	/** DMA events configurations */
+	struct dma_events_config event_config;
+};
+
+/** Forward definition of the DMA resource. */
+struct dma_resource;
+/** Type definition for a DMA resource callback function. */
+typedef void (*dma_callback_t)(struct dma_resource *const resource);
+
+/** Structure for DMA transfer resource. */
+struct dma_resource {
+	/** Allocated DMA channel ID */
+	uint8_t channel_id;
+	/** Array of callback functions for DMA transfer job */
+	dma_callback_t callback[DMA_CALLBACK_N];
+	/** Bit mask for enabled callbacks */
+	uint8_t callback_enable;
+	/** Status of the last job */
+	volatile enum status_code job_status;
+	/** Transferred data size */
+	uint32_t transfered_size;
+	/** DMA transfer descriptor */
+	DmacDescriptor* descriptor;
+};
+
+/**
+ * \brief Get DMA resource status.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ * \return Status of the DMA resource.
+ */
+static inline enum status_code dma_get_job_status(struct dma_resource *resource)
+{
+	Assert(resource);
+
+	return resource->job_status;
+}
+
+/**
+ * \brief Check if the given DMA resource is busy.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ * \return Status which indicates whether the DMA resource is busy.
+ *
+ * \retval true The DMA resource has an on-going transfer
+ * \retval false The DMA resource is not busy
+ */
+static inline bool dma_is_busy(struct dma_resource *resource)
+{
+	Assert(resource);
+
+	return (resource->job_status == STATUS_BUSY);
+}
+
+/**
+ * \brief Enable a callback function for a dedicated DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_enable_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	Assert(resource);
+
+	resource->callback_enable |= 1 << type;
+	g_chan_interrupt_flag[resource->channel_id] |= (1UL << type);
+}
+
+/**
+ * \brief Disable a callback function for a dedicated DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_disable_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	Assert(resource);
+
+	resource->callback_enable &= ~(1 << type);
+	g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK);
+	DMAC->CHINTENCLR.reg = (1UL << type);
+}
+
+/**
+ * \brief Register a callback function for a dedicated DMA resource.
+ *
+ * There are three types of callback functions, which can be registered:
+ * - Callback for transfer complete
+ * - Callback for transfer error
+ * - Callback for channel suspend
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] callback Pointer to the callback function
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_register_callback(struct dma_resource *resource,
+		dma_callback_t callback, enum dma_callback_type type)
+{
+	Assert(resource);
+
+	resource->callback[type] = callback;
+}
+
+/**
+ * \brief Unregister a callback function for a dedicated DMA resource.
+ *
+ * There are three types of callback functions:
+ * - Callback for transfer complete
+ * - Callback for transfer error
+ * - Callback for channel suspend
+ *
+ * The application can unregister any of the callback functions which
+ * are already registered and are no longer needed.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_unregister_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	Assert(resource);
+
+	resource->callback[type] = NULL;
+}
+
+/**
+ * \brief Will set a software trigger for resource.
+ *
+ * This function is used to set a software trigger on the DMA channel
+ * associated with resource. If a trigger is already pending no new trigger
+ * will be generated for the channel.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ */
+static inline void dma_trigger_transfer(struct dma_resource *resource) {
+	Assert(resource);
+
+	DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
+}
+
+/**
+ * \brief Initializes DMA transfer configuration with predefined default values.
+ *
+ * This function will initialize a given DMA descriptor configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structure before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Set the descriptor as valid
+ *  \li Disable event output
+ *  \li No block action
+ *  \li Set beat size as byte
+ *  \li Enable source increment
+ *  \li Enable destination increment
+ *  \li Step size is applied to the destination address
+ *  \li Address increment is beat size multiplied by 1
+ *  \li Default transfer size is set to 0
+ *  \li Default source address is set to NULL
+ *  \li Default destination address is set to NULL
+ *  \li Default next descriptor not available
+ * \param[out] config Pointer to the configuration
+ *
+ */
+static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
+{
+	Assert(config);
+
+	/* Set descriptor as valid */
+	config->descriptor_valid = true;
+	/* Disable event output */
+	config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
+	/* No block action */
+	config->block_action = DMA_BLOCK_ACTION_NOACT;
+	/* Set beat size to one byte */
+	config->beat_size = DMA_BEAT_SIZE_BYTE;
+	/* Enable source increment */
+	config->src_increment_enable = true;
+	/* Enable destination increment */
+	config->dst_increment_enable = true;
+	/* Step size is applied to the destination address */
+	config->step_selection = DMA_STEPSEL_DST;
+	/* Address increment is beat size multiplied by 1*/
+	config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
+	/* Default transfer size is set to 0 */
+	config->block_transfer_count = 0;
+	/* Default source address is set to NULL */
+	config->source_address = (uint32_t)NULL;
+	/* Default destination address is set to NULL */
+	config->destination_address = (uint32_t)NULL;
+	/** Next descriptor address set to 0 */
+	config->next_descriptor_address = 0;
+}
+
+/**
+ * \brief Update DMA descriptor.
+ *
+ * This function can update the descriptor of an allocated DMA resource.
+ *
+ */
+static inline void dma_update_descriptor(struct dma_resource *resource,
+		DmacDescriptor* descriptor)
+{
+	Assert(resource);
+
+	resource->descriptor = descriptor;
+}
+
+/**
+ * \brief Reset DMA descriptor.
+ *
+ * This function will clear the DESCADDR register of an allocated DMA resource.
+ *
+ */
+static inline void dma_reset_descriptor(struct dma_resource *resource)
+{
+	Assert(resource);
+
+	resource->descriptor = NULL;
+}
+
+void dma_get_config_defaults(struct dma_resource_config *config);
+enum status_code dma_allocate(struct dma_resource *resource,
+		struct dma_resource_config *config);
+enum status_code dma_free(struct dma_resource *resource);
+enum status_code dma_start_transfer_job(struct dma_resource *resource);
+void dma_abort_job(struct dma_resource *resource);
+void dma_suspend_job(struct dma_resource *resource);
+void dma_resume_job(struct dma_resource *resource);
+void dma_descriptor_create(DmacDescriptor* descriptor,
+	struct dma_descriptor_config *config);
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+		DmacDescriptor* descriptor);
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_dma_extra Extra Information for DMAC Driver
+ *
+ * \section asfdoc_sam0_dma_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Acronym</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>DMA</td>
+ *     <td>Direct Memory Access</td>
+ *   </tr>
+ *   <tr>
+ *     <td>DMAC</td>
+ *     <td>Direct Memory Access Controller </td>
+ *   </tr>
+ *   <tr>
+ *     <td>CPU</td>
+ *     <td>Central Processing Unit</td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Driver"
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Changelog</th>
+ *   </tr>
+ *   <tr>
+ *     <td>Add SAM C21 support</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Add SAM L21 support</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Add SAM R30 support</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Initial Release</td>
+ *   </tr>
+ * </table>
+ */
+
+ /**
+ * \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_dma_basic_use_case
+ *
+ * \note More DMA usage examples are available in peripheral QSGs.
+ * A quick start guide for TC/TCC
+ * shows the usage of DMA event trigger; SERCOM SPI/USART/I<SUP>2</SUP>C has example for
+ * DMA transfer from peripheral to memory or from memory to peripheral;
+ * ADC/DAC shows peripheral to peripheral transfer.
+ *
+ * \page asfdoc_sam0_dma_document_revision_history Document Revision History
+ *
+ * <table>
+ *    <tr>
+ *        <th>Doc. Rev.</th>
+ *        <th>Date</th>
+ *        <th>Comments</th>
+ *    </tr>
+ *    <tr>
+ *        <td>42257C</td>
+ *        <td>12/2015</td>
+ *        <td>Added suppport for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1</td>
+ *    </tr>
+ *    <tr>
+ *        <td>42257B</td>
+ *        <td>12/2014</td>
+ *        <td>Added support for SAM R21 and SAM D10/D11</td>
+ *    </tr>
+ *    <tr>
+ *        <td>42257A</td>
+ *        <td>02/2014</td>
+ *        <td>Initial release</td>
+ *    </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DMA_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_crc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_crc.h
new file mode 100644
index 0000000000..3d8c27c197
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_crc.h
@@ -0,0 +1,230 @@
+/**
+ * \file
+ *
+ * \brief SAM DMA cyclic redundancy check (CRC) Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DMA_CRC_H_INCLUDED
+#define DMA_CRC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DMA channel n offset. */
+#define DMA_CRC_CHANNEL_N_OFFSET 0x20
+
+/** CRC Polynomial Type. */
+enum crc_polynomial_type {
+	/** CRC16 (CRC-CCITT). */
+	CRC_TYPE_16,
+	/** CRC32 (IEEE 802.3). */
+	CRC_TYPE_32,
+};
+
+/** CRC Beat Type. */
+enum crc_beat_size {
+	/** Byte bus access. */
+	CRC_BEAT_SIZE_BYTE,
+	/** Half-word bus access. */
+	CRC_BEAT_SIZE_HWORD,
+	/** Word bus access. */
+	CRC_BEAT_SIZE_WORD,
+};
+
+/** Configurations for CRC calculation. */
+struct dma_crc_config {
+	/** CRC polynomial type. */
+	enum crc_polynomial_type type;
+	/** CRC beat size. */
+	enum crc_beat_size size;
+};
+
+/**
+ * \brief Get DMA CRC default configurations.
+ *
+ * The default configuration is as follows:
+ *  \li Polynomial type is set to CRC-16(CRC-CCITT)
+ *  \li CRC Beat size: BYTE
+ *
+ * \param[in] config default configurations
+ */
+static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
+{
+	Assert(config);
+
+	config->type = CRC_TYPE_16;
+	config->size = CRC_BEAT_SIZE_BYTE;
+}
+
+/**
+ * \brief Enable DMA CRC module with an DMA channel.
+ *
+ * This function enables a CRC calculation with an allocated DMA channel. This channel ID
+ * can be gotten from a successful \ref dma_allocate.
+ *
+ * \param[in] channel_id DMA channel expected with CRC calculation
+ * \param[in] config CRC calculation configurations
+ *
+ * \return Status of the DMC CRC.
+ * \retval STATUS_OK Get the DMA CRC module
+ * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
+ */
+static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
+		struct dma_crc_config *config)
+{
+	if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
+		return STATUS_BUSY;
+	}
+
+	DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
+		DMAC_CRCCTRL_CRCPOLY(config->type) |
+		DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
+
+	DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disable DMA CRC module.
+ *
+ */
+static inline void dma_crc_disable(void)
+{
+	DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
+	DMAC->CRCCTRL.reg = 0;
+}
+
+/**
+ * \brief Get DMA CRC checksum value.
+ *
+ * \return Calculated CRC checksum.
+ */
+static inline uint32_t dma_crc_get_checksum(void)
+{
+	if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) {
+		DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+	}
+
+	return DMAC->CRCCHKSUM.reg;
+}
+
+/**
+ * \brief Enable DMA CRC module with I/O.
+ *
+ * This function enables a CRC calculation with I/O mode.
+ *
+ * \param[in] config CRC calculation configurations.
+ *
+ * \return Status of the DMC CRC.
+ * \retval STATUS_OK Get the DMA CRC module
+ * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
+ */
+static inline enum status_code dma_crc_io_enable(
+		struct dma_crc_config *config)
+{
+	if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
+		return STATUS_BUSY;
+	}
+
+	if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) {
+		return STATUS_BUSY;
+	}
+
+	DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
+		DMAC_CRCCTRL_CRCPOLY(config->type) |
+		DMAC_CRCCTRL_CRCSRC_IO;
+
+	if (config->type == CRC_TYPE_32) {
+		DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
+	}
+
+	DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Calculate CRC with I/O.
+ *
+ * This function calculate the CRC of the input data buffer.
+ *
+ * \param[in] buffer CRC Pointer to calculation buffer
+ * \param[in] total_beat_size Total beat size to be calculated
+ *
+ * \return Calculated CRC checksum value.
+ */
+static inline void dma_crc_io_calculation(void *buffer,
+		 uint32_t total_beat_size)
+{
+	uint32_t counter = total_beat_size;
+	uint8_t *buffer_8;
+	uint16_t *buffer_16;
+	uint32_t *buffer_32;
+
+	for (counter=0; counter<total_beat_size; counter++) {
+		if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) {
+			buffer_8 = buffer;
+			DMAC->CRCDATAIN.reg = buffer_8[counter];
+		} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) {
+			buffer_16 = buffer;
+			DMAC->CRCDATAIN.reg = buffer_16[counter];
+		} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) {
+			buffer_32 = buffer;
+			DMAC->CRCDATAIN.reg = buffer_32[counter];
+		}
+		/* Wait several cycle to make sure CRC complete */
+		nop();
+		nop();
+		nop();
+		nop();
+	}
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DMA_CRC_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.c
new file mode 100644
index 0000000000..d14f0e5ee2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.c
@@ -0,0 +1,557 @@
+/*
+ * \file
+ *
+ * \brief Direct Memory Access Controller Driver for SAMB
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <string.h>
+#include "dma_sam_b.h"
+
+struct _dma_module {
+	volatile bool _dma_init;
+	volatile uint32_t allocated_channels;
+	uint8_t free_channels;
+};
+
+struct _dma_module _dma_inst = {
+	._dma_init = false,
+	.allocated_channels = 0,
+	.free_channels = CONF_MAX_USED_CHANNEL_NUM,
+};
+
+/** Internal DMA resource pool. */
+static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
+
+/**
+ * \brief Get the assigned channel DMA value.
+ *
+ * \param[in] channel DMA channel index
+ * \param[in] DMA register address
+ *
+ * \return The value of DMA register.
+ */
+static uint32_t get_channel_reg_val(uint8_t channel, uint32_t reg)
+{
+	return *(uint32_t*)(reg + 0x100*channel);
+}
+
+/**
+ * \brief Set the assigned channel DMA value.
+ *
+ * \param[in] channel DMA channel index
+ * \param[in] DMA register address
+ * \param[in] The value to be set
+ *
+ */
+static void set_channel_reg_val(uint8_t channel, uint32_t reg, uint32_t val)
+{
+	*(uint32_t*)(reg + 0x100*channel) = val;
+}
+
+/**
+ * \brief Get the DMA status.
+ *
+ * \param[in]  channel  DMA channel index
+ *
+ * \return The status of DMA
+ */
+uint8_t dma_get_status(uint8_t channel)
+{
+	return (uint8_t)get_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_RAWSTAT_REG.reg);
+}
+
+/**
+ * \brief Get the DMA interrupt status.
+ *
+ * \param[in]  channel  DMA channel index
+ *
+ * \return The interrupt of status DMA
+ */
+uint8_t dma_get_interrupt_status(uint8_t channel)
+{
+	return get_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
+}
+
+/**
+ * \brief Get the DMA interrupt status.
+ *
+ * \param[in]  channel  DMA channel index
+ * \param[in]  flag     The interrupt flag want to clear
+ *
+ */
+void dma_clear_interrupt_status(uint8_t channel, uint8_t flag)
+{
+	set_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, 1 << flag);
+}
+
+/**
+ * \brief Find a free channel for a DMA resource.
+ *
+ * Find a channel for the requested DMA resource.
+ *
+ * \return Status of channel allocation.
+ * \retval DMA_INVALID_CHANNEL  No channel available
+ * \retval count          Allocated channel for the DMA resource
+ */
+static uint8_t _dma_find_first_free_channel_and_allocate(void)
+{
+	uint8_t count;
+	uint32_t tmp;
+	bool allocated = false;
+
+	tmp = _dma_inst.allocated_channels;
+
+	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
+		if (!(tmp & 0x00000001)) {
+			/* If free channel found, set as allocated and return
+			 *number */
+
+			_dma_inst.allocated_channels |= 1 << count;
+			_dma_inst.free_channels--;
+			allocated = true;
+
+			break;
+		}
+
+		tmp = tmp >> 1;
+	}
+
+	if (!allocated) {
+		return DMA_INVALID_CHANNEL;
+	} else {
+		return count;
+	}
+}
+
+/**
+ * \brief Release an allocated DMA channel.
+ *
+ * \param[in]  channel  Channel id to be released
+ *
+ */
+static void _dma_release_channel(uint8_t channel)
+{
+	_dma_inst.allocated_channels &= ~(1 << channel);
+	_dma_inst.free_channels++;
+}
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given DMA configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structure before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Set source max burst number as 1
+ *  \li Set source tokens as 1
+ *  \li Set source peripheral as memory
+ *  \li Set source peripheral delay as 0
+ *  \li Disable source top priority
+ *  \li Set source top priority channel as 0
+ *  \li Disable source high priority
+ *  \li Set source high priority channel as 0
+ *  \li Set destination max burst number as 1
+ *  \li Set destination tokens as 1
+ *  \li Set destination peripheral as memory
+ *  \li Set destination peripheral delay as 0
+ *  \li Disable destination top priority
+ *  \li Set destination top priority channel as 0
+ *  \li Disable destination high priority
+ *  \li Set destination high priority channel as 0
+ *  \li Disable the joint mode
+ *  \li Disable the endian swap
+ * \param[out] config Pointer to the configuration
+ *
+ */
+void dma_get_config_defaults(struct dma_resource_config *config)
+{
+	/* DMA source configuration */
+	config->src.max_burst = 1;
+	config->src.tokens = 1;
+	config->src.enable_inc_addr = true;
+	config->src.periph = MEMORY_DMA_PERIPHERAL;
+	config->src.periph_delay = 0;
+	config->src.enable_proi_top = false;
+	config->src.proi_top_index = 0;
+	config->src.enable_proi_high = false;
+	config->src.proi_high_index = 0;
+	/* DMA destination configuration */
+	config->des.max_burst = 1;
+	config->des.tokens = 1;
+	config->des.enable_inc_addr = true;
+	config->des.periph = MEMORY_DMA_PERIPHERAL;
+	config->des.periph_delay = 0;
+	config->des.enable_proi_top = false;
+	config->des.proi_top_index = 0;
+	config->des.enable_proi_high = false;
+	config->des.proi_high_index = 0;
+	/* DMA channel configuration */
+	config->enable_joint_mode = false;
+	config->swap = DMA_ENDIAN_NO_SWAP;
+}
+
+/**
+ * \brief Configure the DMA resource.
+ *
+ * \param[in]  dma_resource Pointer to a DMA resource instance
+ * \param[out] config Configurations of the DMA resource
+ *
+ */
+static void _dma_set_config(struct dma_resource *resource,
+		struct dma_resource_config *config)
+{
+	uint32_t regval = 0;
+
+	/* Static register configuration */
+	regval = PROV_DMA_CTRL_CH0_STATIC_REG0_RD_BURST_MAX_SIZE(config->src.max_burst)|
+			PROV_DMA_CTRL_CH0_STATIC_REG0_RD_TOKENS(config->src.tokens) |
+			(config->src.enable_inc_addr << PROV_DMA_CTRL_CH0_STATIC_REG0_RD_INCR_Pos);
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG0.reg, regval);
+	/* Static register1 configuration */
+	regval = PROV_DMA_CTRL_CH0_STATIC_REG1_WR_BURST_MAX_SIZE(config->des.max_burst) |
+			PROV_DMA_CTRL_CH0_STATIC_REG1_WR_TOKENS(config->des.tokens) | 
+			(config->des.enable_inc_addr << PROV_DMA_CTRL_CH0_STATIC_REG0_RD_INCR_Pos);
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG1.reg, regval);
+	/* Static register2 configuration */
+	regval = (config->enable_joint_mode << PROV_DMA_CTRL_CH0_STATIC_REG2_JOINT_Pos) |
+			PROV_DMA_CTRL_CH0_STATIC_REG2_END_SWAP(config->swap);
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG2.reg, regval);
+	/* Static register4 configuration */
+	regval = PROV_DMA_CTRL_CH0_STATIC_REG4_RD_PERIPH_NUM(config->src.periph) |
+			PROV_DMA_CTRL_CH0_STATIC_REG4_RD_PERIPH_DELAY(config->src.periph_delay) |
+			PROV_DMA_CTRL_CH0_STATIC_REG4_WR_PERIPH_NUM(config->des.periph) |
+			PROV_DMA_CTRL_CH0_STATIC_REG4_WR_PERIPH_DELAY(config->des.periph_delay);
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG4.reg, regval);
+	/* Priority channels configuration */
+	regval = PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_TOP_NUM(config->src.proi_top_index) |
+			(PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_TOP << config->src.enable_proi_top) |
+			PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_HIGH_NUM(config->src.proi_high_index) |
+			(PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_HIGH << config->src.enable_proi_high) |
+			PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_TOP_NUM(config->des.proi_top_index) |
+			(PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_TOP << config->des.enable_proi_top) |
+			PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_HIGH_NUM(config->des.proi_high_index) |
+			(PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_HIGH << config->des.enable_proi_high);
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CORE_PRIORITY.reg, regval);
+	/* Initial the global variety */
+	for (int i = 0; i < DMA_CALLBACK_N; i++) {
+		resource->callback[i] = NULL;
+	}
+	resource->callback_enable = 0;
+}
+
+/**
+ * \brief Free an allocated DMA resource.
+ *
+ * This function will free an allocated DMA resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ * \return Status of the free procedure.
+ *
+ * \retval STATUS_OK The DMA resource was freed successfully
+ * \retval STATUS_BUSY The DMA resource was busy and can't be freed
+ * \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized
+ */
+enum status_code dma_free(struct dma_resource *resource)
+{
+	/* Check if channel is busy */
+	if (dma_get_job_status(resource) == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Check if DMA resource was not allocated */
+	if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* Release the DMA resource */
+	_dma_release_channel(resource->channel_id);
+
+	/* Reset the item in the DMA resource pool */
+	_dma_active_resource[resource->channel_id] = NULL;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Add a DMA transfer descriptor to a DMA resource.
+ *
+ * This function will add a DMA transfer descriptor to a DMA resource.
+ * If there was a transfer descriptor already allocated to the DMA resource,
+ * the descriptor will be linked to the next descriptor address.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] descriptor Pointer to the transfer descriptor
+ *
+ * \retval STATUS_OK The descriptor is added to the DMA resource
+ * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
+ */
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+		struct dma_descriptor *descriptor)
+{
+	struct dma_descriptor *desc = resource->descriptor;
+
+	/* Check if channel is busy */
+	if (dma_get_job_status(resource) == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Look up for an empty space for the descriptor */
+	if (desc == NULL) {
+		resource->descriptor = descriptor;
+		set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG0.reg, descriptor->read_start_addr);
+		set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG1.reg, descriptor->write_start_addr);
+		set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG2.reg, descriptor->buffer_size);
+		set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG3.reg, 3);
+	} else {
+		/* Looking for end of descriptor link */
+		while(((uint32_t)desc->cmd.next_addr) != 0) {
+			desc = (struct dma_descriptor*)((uint32_t)desc->next);
+		}
+		if (resource->descriptor->cmd.next_addr == 0x0) {
+			set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG3.reg, ((uint32_t)descriptor & (~0x3)));
+		}
+		/* Set to the end of descriptor list */
+		desc->next = (uint32_t)descriptor;
+		/* The end of list should point to 0 */
+		if (descriptor->cmd.next_addr != 0) {
+			/* Enable transferred interrupt, and channel stops when buffer done */
+			descriptor->next = 0x3;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Start a DMA transfer.
+ *
+ * This function will start a DMA transfer through an allocated DMA resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ * \return Status of the transfer start procedure.
+ *
+ * \retval STATUS_OK The transfer was started successfully
+ * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
+ * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
+ */
+enum status_code dma_start_transfer_job(struct dma_resource *resource)
+{
+	volatile uint32_t regval;
+
+	/* Check if resource was busy */
+	if (resource->job_status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Check if transfer size is valid */
+	if (resource->descriptor->buffer_size == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+	
+	/* Clear the interrupt flag */
+	regval = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, regval);
+	/* Set the interrupt flag */
+	regval = PROV_DMA_CTRL_CH0_INT_ENABLE_REG_MASK & resource->callback_enable;
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_ENABLE_REG.reg, regval);
+	/* Set job status */
+	resource->job_status = STATUS_BUSY;
+
+	/* Enable the transfer channel */
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CH_ENABLE_REG.reg, 1);
+	/* Start the transfer channel */
+	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CH_START_REG.reg, 1);
+
+	return STATUS_OK;
+}
+/**
+ * \brief Get the channel index
+ *
+ * \param[in]  channel  Channel active
+ *
+ */
+static uint8_t get_channel_index(uint8_t channel)
+{
+	uint8_t index = 0;
+
+	channel = channel & 0x0f;
+	do {
+		channel = channel >> 1;
+		index++;
+	} while (channel);
+	
+	return (index - 1);
+}
+
+/**
+ * \brief DMA interrupt service routine.
+ *
+ */
+static void dma_isr_handler( void )
+{
+	uint8_t active_channel;
+	static uint8_t channel_index; //
+	struct dma_resource *resource;
+	uint8_t isr;
+	uint8_t isr_flag = 0;
+
+	/* Get active channel */
+	active_channel =  PROV_DMA_CTRL0->CORE_INT_STATUS.reg & 
+			PROV_DMA_CTRL_CORE_INT_STATUS_CHANNEL__Msk;
+				
+	do {
+		channel_index = get_channel_index(active_channel);
+		/* Get active DMA resource based on channel */
+		resource = _dma_active_resource[channel_index];
+		isr = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
+		/* Calculate block transfer size of the DMA transfer */
+		resource->transfered_size = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_COUNT_REG.reg);
+
+		/* DMA channel interrupt handler */
+		if (isr & (1 << DMA_CALLBACK_TRANSFER_DONE)) {
+			/* Transfer complete flag */
+			isr_flag = DMA_CALLBACK_TRANSFER_DONE;
+			/* Set job status */
+			resource->job_status = STATUS_OK;
+		} else if (isr & (1 << DMA_CALLBACK_READ_ERR)) {
+			/* Read error flag */
+			isr_flag = DMA_CALLBACK_READ_ERR;
+			/* Set I/O ERROR status */
+			resource->job_status = STATUS_ERR_IO;
+		} else if (isr & (1 << DMA_CALLBACK_WRITE_ERR)) {
+			/* Write error flag */
+			isr_flag = DMA_CALLBACK_WRITE_ERR;
+			/* Set I/O ERROR status */
+			resource->job_status = STATUS_ERR_IO;
+		} else if (isr & (1 << DMA_CALLBACK_FIFO_OVERFLOW)) {
+			/* Overflow flag */
+			isr_flag = DMA_CALLBACK_FIFO_OVERFLOW;
+			/* Set I/O ERROR status */
+			resource->job_status = STATUS_ERR_IO;
+		} else if (isr & (1 << DMA_CALLBACK_FIFO_UNDERFLOW)) {
+			/* Underflow flag */
+			isr_flag = DMA_CALLBACK_FIFO_UNDERFLOW;
+			/* Set I/O ERROR status */
+			resource->job_status = STATUS_ERR_IO;
+		} else if (isr & (1 << DMA_CALLBACK_READ_TIMEOUT)) {
+			/* Read timeout flag */
+			isr_flag = DMA_CALLBACK_READ_TIMEOUT;
+			/* Set I/O ERROR status */
+			resource->job_status = STATUS_ERR_IO;
+		} else if (isr & (1 << DMA_CALLBACK_WRITE_TIMEOUT)) {
+			/* Write timeout flag */
+			isr_flag = DMA_CALLBACK_WRITE_TIMEOUT;
+			/* Set I/O ERROR status */
+			resource->job_status = STATUS_ERR_IO;
+		} else if (isr & (1 << DMA_CALLBACK_WDT_TRIGGER)) {
+			/* Watchdog error flag */
+			isr_flag = DMA_CALLBACK_WDT_TRIGGER;
+			/* Set I/O ERROR status */
+			resource->job_status = STATUS_ERR_IO;
+		}
+		
+		if (isr) {
+			/* Clear the watch dog error flag */
+			set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, 1<<isr_flag);
+			/* Execute the callback function */
+			if ((resource->callback_enable & (1<<isr_flag)) &&
+					(resource->callback[isr_flag])) {
+				resource->callback[isr_flag](resource);
+			}
+		}
+		isr &= ~(1<<isr_flag);
+	} while (isr);
+
+	NVIC_ClearPendingIRQ(PROV_DMA_CTRL0_IRQn);
+}
+
+/**
+ * \brief Allocate a DMA with configurations.
+ *
+ * This function will allocate a proper channel for a DMA transfer request.
+ *
+ * \param[in,out]  dma_resource Pointer to a DMA resource instance
+ * \param[in] transfer_config Configurations of the DMA transfer
+ *
+ * \return Status of the allocation procedure.
+ *
+ * \retval STATUS_OK The DMA resource was allocated successfully
+ * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
+ */
+enum status_code dma_allocate(struct dma_resource *resource,
+		struct dma_resource_config *config)
+{
+	uint8_t new_channel;
+
+	if (!_dma_inst._dma_init) {
+		/* Perform a reset before enable DMA controller */
+		system_peripheral_reset(PERIPHERAL_DMA);
+		/* Select Mux 15 as PROV_DMA_CTRL0 interrupt source */
+		LPMCU_MISC_REGS0->IRQ_MUX_IO_SEL_3.bit.MUX_15 = LPMCU_MISC_REGS_IRQ_MUX_IO_SEL_3_MUX_15_16_Val;
+		system_register_isr(31, (uint32_t)dma_isr_handler);
+		
+		_dma_inst._dma_init = true;
+	}
+
+	new_channel = _dma_find_first_free_channel_and_allocate();
+	/* If no channel available, return not found */
+	if (new_channel == DMA_INVALID_CHANNEL) {
+		return STATUS_ERR_NOT_FOUND;
+	}
+	
+	/* Set the channel */
+	resource->channel_id = new_channel;
+	/* Configure the DMA control,channel registers and descriptors here */
+	_dma_set_config(resource, config);
+	
+	resource->descriptor = NULL;
+
+	/* Log the DMA resource into the internal DMA resource pool */
+	_dma_active_resource[resource->channel_id] = resource;
+
+	return STATUS_OK;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.h
new file mode 100644
index 0000000000..ae3ecede85
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.h
@@ -0,0 +1,650 @@
+/**
+ * \file
+ *
+ * \brief Direct Memory Access Controller Driver for SAMB
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DMA_H_INCLUDED
+#define DMA_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_samb_dma_group SAM Direct Memory Access Controller Driver (DMAC)
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the configuration
+ * and management of the Direct Memory Access Controller(DMAC) module within
+ * the device. The DMAC can transfer data between memories and peripherals, and
+ * thus off-load these tasks from the CPU. The module supports peripheral to
+ * peripheral, peripheral to memory, memory to peripheral, and memory to memory
+ * transfers.
+ *
+ * The following peripherals are used by the DMAC Driver:
+ * - DMAC (Direct Memory Access Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_samb_dma_prerequisites
+ * - \ref asfdoc_samb_dma_module_overview
+ * - \ref asfdoc_samb_dma_special_considerations
+ * - \ref asfdoc_samb_dma_extra_info
+ * - \ref asfdoc_samb_dma_examples
+ * - \ref asfdoc_samb_dma_api_overview
+ *
+ *
+ * \section asfdoc_samb_dma_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_dma_module_overview Module Overview
+ *
+ * SAM devices with DMAC enables high data transfer rates with minimum
+ * CPU intervention and frees up CPU time. With access to all peripherals,
+ * the DMAC can handle automatic transfer of data to/from modules.
+ * It supports static and incremental addressing for both source and
+ * destination.
+ *
+ * The DMAC when used with peripheral triggers, provides a
+ * considerable advantage by reducing the power consumption and performing
+ * data transfer in the background.
+ * The CPU can remain in sleep during this time to reduce power consumption.
+ *
+ * <table>
+ *    <tr>
+ *      <th>Device</th>
+ *      <th>Dma channel number</th>
+ *    </tr>
+ *    <tr>
+ *      <td>SAMB11</td>
+ *      <td>4</td>
+ *    </tr>
+ * </table>
+ * The DMA channel operation can be suspended at any time by software, 
+ * or after selectable descriptor execution. The DMAC driver for SAM 
+ * supports four types of transfers such as peripheral to peripheral,
+ * peripheral to memory, memory to peripheral, and memory to memory.
+ *
+ * The basic transfer unit is a beat which is defined as a single bus access.
+ * There can be multiple beats in a single block transfer and multiple block
+ * transfers in a DMA transaction.
+ * DMA transfer is based on descriptors, which holds transfer properties
+ * such as the source and destination addresses, transfer counter, and other
+ * additional transfer control information.
+ * The descriptors can be static or linked. When static, a single block transfer
+ * is performed. When linked, a number of transfer descriptors can be used to
+ * enable multiple block transfers within a single DMA transaction.
+ *
+ * The implementation of the DMA driver is based on the idea that DMA channel
+ * is a finite resource of entities with the same abilities. A DMA channel resource
+ * is able to move a defined set of data from a source address to destination
+ * address triggered by a transfer trigger. On the SAM devices there are 12
+ * DMA resources available for allocation. Each of these DMA resources can trigger
+ * interrupt callback routines.
+ * The other main features are:
+ *
+ * - Selectable transfer trigger source
+ *  - Software
+ *  - Peripheral
+ * - Tree level channel priority
+ *  - Normal level
+ *  - High level
+ *  - Top level
+ * - Optional interrupt generation on transfer complete, channel error
+ * - Supports multi-buffer or circular buffer mode by linking multiple descriptors
+ * - Beat size configurable as 8-bit, 16-bit, or 32-bit
+ *
+ * A simplified block diagram of the DMA Resource can be seen in
+ * \ref asfdoc_samb_dma_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_samb_dma_module_block_diagram
+ * \dot
+ * digraph overview {
+ * splines = false;
+ * rankdir=LR;
+ *
+ * mux1 [label="Transfer Trigger", shape=box];
+ *
+ * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * mux1 -> dma;
+ * descriptor -> dma;
+ *
+ * interrupt [label="Interrupt", shape=box];
+ * events [label="Events", shape=box];
+ *
+ * dma:e -> interrupt:w;
+ * dma:e -> events:w;
+ *
+ * {rank=same; descriptor dma}
+ *
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_samb_dma_module_overview_dma_channels DMA Channels
+ * The DMAC in each device consists of several DMA channels, which
+ * along with the transfer descriptors defines the data transfer properties.
+ * - The transfer control descriptor defines the source and destination
+ * addresses, source and destination address increment settings, the
+ * block transfer count
+ * - Dedicated channel registers control the peripheral trigger source,
+ * trigger mode settings, and channel priority level settings
+ *
+ * With a successful DMA resource allocation, a dedicated
+ * DMA channel will be assigned. The channel will be occupied until the
+ * DMA resource is freed. A DMA resource handle is used to identify the specific
+ * DMA resource.
+ * When there are multiple channels with active requests, the arbiter prioritizes
+ * the channels requesting access to the bus.
+ *
+ * \subsection asfdoc_samb_dma_module_overview_dma_trigger DMA Triggers
+ * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A
+ * transfer request can be triggered from software, peripheral. There
+ * are dedicated source trigger selections for each DMA channel usage.
+ *
+ * \subsection asfdoc_samb_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor
+ * The transfer descriptor resides in the SRAM and
+ * defines these channel properties.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Field name</th>
+ *     <th>Field width</th>
+ *   </tr>
+ *   <tr>
+ *     <td>Source Address</td>
+ *     <td>32 bits</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Destination Address</td>
+ *     <td>32 bits</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Block Transfer Counter</td>
+ *     <td>32 bits</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Descriptor Next Address</td>
+ *     <td>30 bits</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Block Transfer Interrupt</td>
+ *     <td>1 bit</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Block Transfer Stop Control</td>
+ *     <td>1 bit</td>
+ *   </tr>
+ * </table>
+ *
+ * Before starting a transfer, at least one descriptor should be configured.
+ * After a successful allocation of a DMA channel, the transfer descriptor can
+ * be added with a call to \ref dma_add_descriptor(). If there is a transfer
+ * descriptor already allocated to the DMA resource, the descriptor will
+ * be linked to the next descriptor address.
+ *
+ * \subsection asfdoc_samb_dma_module_overview_dma_output DMA Interrupts
+ * Both an interrupt callback and an peripheral can be triggered by the
+ * DMA transfer. Three types of callbacks are supported by the DMA driver:
+ * transfer complete, channel suspend, and transfer error. Each of these callback
+ * types can be registered and enabled for each channel independently through
+ * the DMA driver API.
+ *
+ *
+ * \section asfdoc_samb_dma_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_samb_dma_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_dma_extra. This includes:
+ * - \ref asfdoc_samb_dma_extra_acronyms
+ * - \ref asfdoc_samb_dma_extra_dependencies
+ * - \ref asfdoc_samb_dma_extra_errata
+ * - \ref asfdoc_samb_dma_extra_history
+ *
+ *
+ * \section asfdoc_samb_dma_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_dma_exqsg.
+ *
+ *
+ * \section asfdoc_samb_dma_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system_sam_b.h>
+#include "conf_dma.h"
+
+/** DMA IRQn number. */
+#define PROV_DMA_CTRL0_IRQn		15
+
+/** DMA invalid channel number. */
+#define DMA_INVALID_CHANNEL        0xff
+
+/** DMA peripheral index */
+enum dma_peripheral_index {
+	MEMORY_DMA_PERIPHERAL = 0,
+	UART0RX_DMA_PERIPHERAL,
+	UART0TX_DMA_PERIPHERAL,
+	UART1RX_DMA_PERIPHERAL,
+	UART1TX_DMA_PERIPHERAL,
+	SPI0RX_DMA_PERIPHERAL,
+	SPI0TX_DMA_PERIPHERAL,
+	SPI1RX_DMA_PERIPHERAL,
+	SPI1TX_DMA_PERIPHERAL,
+	I2C0RX_DMA_PERIPHERAL,
+	I2C0TX_DMA_PERIPHERAL,
+	I2C1RX_DMA_PERIPHERAL,
+	I2C1TX_DMA_PERIPHERAL,
+	DUALTIMER0_DMA_PERIPHERAL = 15,
+	TIMER0_DMA_PERIPHERAL,
+};
+
+/** DMA channel index */
+enum dma_ch_index {
+	/** DMA channel 0 */
+	DMA_CHANNEL_0 = 0,
+	/** DMA channel 1 */
+	DMA_CHANNEL_1,
+	/** DMA channel 2 */
+	DMA_CHANNEL_2,
+	/** DMA channel 3 */
+	DMA_CHANNEL_3,
+};
+
+enum dma_endian_swap {
+	/** DMA endian no swap */
+	DMA_ENDIAN_NO_SWAP,
+	/** DMA endian 16-bit */
+	DMA_ENDIAN_SIZE_16,
+	/** DMA endian 32-bit */
+	DMA_ENDIAN_SIZE_32,
+	/** DMA endian 64-bit */
+	DMA_ENDIAN_SIZE_64,
+};
+
+/**
+ * Callback types for DMA callback driver.
+ */
+enum dma_callback_type {
+	/** Callback for transfer complete */
+	DMA_CALLBACK_TRANSFER_DONE,
+	/** AHB read slave error */
+	DMA_CALLBACK_READ_ERR,
+	/**  AHB write slave error */
+	DMA_CALLBACK_WRITE_ERR,
+	/** FIFO has been overflown */
+	DMA_CALLBACK_FIFO_OVERFLOW,
+	/** FIFO has been underflows */
+	DMA_CALLBACK_FIFO_UNDERFLOW,
+	/** Read timeout on AHB bus (timeout value fixed at 1024 cycles) */
+	DMA_CALLBACK_READ_TIMEOUT,
+	/** Write timeout on AHB bus (timeout value fixed at 1024 cycles) */
+	DMA_CALLBACK_WRITE_TIMEOUT,
+	/** Channel active but did not start a burst for 2048 cycles */
+	DMA_CALLBACK_WDT_TRIGGER,
+	/** Number of available callbacks */
+	DMA_CALLBACK_N,
+};
+
+/**
+ * DMA transfer descriptor configuration. When the source or destination address
+ * increment is enabled, the addresses stored into the configuration structure
+ * must correspond to the end of the transfer.
+ */
+struct dma_descriptor {
+	/** Start address of read buffer */
+	uint32_t read_start_addr;
+	/** Start address of write buffer */
+	uint32_t write_start_addr;
+	/** Size (in bytes) of buffer to transfer */
+	uint32_t buffer_size;
+	union {
+		struct {
+			/** Active high interrupt enable once buffer has been transferred */
+			uint32_t set_interrupt:1;
+			/** If set, channel stops when buffer done, otherwise load from cmd_next_addr */
+			uint32_t last:1;
+			/** Address of next command if cmd_last is not set */
+			uint32_t next_addr:30;
+		} cmd;
+		uint32_t next;
+	};
+};
+/** Structure for DMA source/description */
+struct dma_config {
+	/** Maximum number of bytes of an AHB read/write burst */
+	uint8_t max_burst;
+	/** Number of AHB read/write commands to issue before channel is released */
+	uint8_t tokens;
+	/** If true, the controller will increment the next burst address */
+	bool enable_inc_addr;
+	/** Index of peripheral to read/write from (0 if memory or no peripheral flow control) */
+	enum dma_peripheral_index periph;
+	/** 
+	 * Number of cycles to wait for read/write request signal to update 
+	 * after issuing the read/write clear signal
+	 */
+	uint8_t periph_delay;
+	/** Top priority enable */
+	bool enable_proi_top;
+	/** Top priority channel index */
+	uint8_t proi_top_index;
+	/** High priority enable */
+	bool enable_proi_high;
+	/** High priority channel index */
+	uint8_t proi_high_index;
+};
+
+/** Structure for DMA transfer resource */
+struct dma_resource_config {
+	struct dma_config src;
+	struct dma_config des;
+	/** If true, channel will work in joint mode */
+	bool enable_joint_mode;
+	/** Endian Byte Swapping */
+	enum dma_endian_swap swap;
+};
+
+/** Forward definition of the DMA resource */
+struct dma_resource;
+/** Type definition for a DMA resource callback function */
+typedef void (*dma_callback_t)(struct dma_resource *const resource);
+
+/** Structure for DMA transfer resource */
+struct dma_resource {
+	/** Allocated DMA channel ID */
+	uint8_t channel_id;
+	/** Array of callback functions for DMA transfer job */
+	dma_callback_t callback[DMA_CALLBACK_N];
+	/** Bit mask for enabled callbacks */
+	uint8_t callback_enable;
+	/** Status of the last job */
+	volatile enum status_code job_status;
+	/** Transferred data size */
+	uint32_t transfered_size;
+	/** DMA transfer descriptor */
+	struct dma_descriptor* descriptor;
+};
+
+/**
+ * \brief Get DMA resource status.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ * \return Status of the DMA resource.
+ */
+static inline enum status_code dma_get_job_status(struct dma_resource *resource)
+{
+	return resource->job_status;
+}
+
+/**
+ * \brief Enable a callback function for a dedicated DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_enable_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	resource->callback_enable |= 1 << type;
+}
+
+/**
+ * \brief Disable a callback function for a dedicated DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_disable_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	resource->callback_enable &= ~(1 << type);
+}
+
+/**
+ * \brief Register a callback function for a dedicated DMA resource.
+ *
+ * There are three types of callback functions, which can be registered:
+ * - Callback for transfer complete
+ * - Callback for transfer error
+ * - Callback for channel suspend
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] callback Pointer to the callback function
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_register_callback(struct dma_resource *resource,
+		dma_callback_t callback, enum dma_callback_type type)
+{
+	resource->callback[type] = callback;
+}
+
+/**
+ * \brief Unregister a callback function for a dedicated DMA resource.
+ *
+ * There are three types of callback functions:
+ * - Callback for transfer complete
+ * - Callback for transfer error
+ * - Callback for channel suspend
+ *
+ * The application can unregister any of the callback functions which
+ * are already registered and are no longer needed.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_unregister_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	resource->callback[type] = NULL;
+}
+
+/**
+ * \brief Initializes DMA transfer configuration with predefined default values.
+ *
+ * This function will initialize a given DMA descriptor configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structure before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Set the read start address as 0
+ *  \li Set the write start address as 0
+ *  \li Set buffer size as 1
+ *  \li Set beat size as byte
+ *  \li Enable the interrupt
+ *  \li Enable the channel stops when buffer done
+ *  \li Set next command address to 0
+ * \param[out] config Pointer to the configuration
+ *
+ */
+static inline void dma_descriptor_get_config_defaults(struct dma_descriptor *config)
+{
+	/* Default read buffer size is set to 0 */
+	config->read_start_addr = 0;
+	/* Default write buffer size is set to 0 */
+	config->write_start_addr = 0;
+	/* Set beat size to one byte */
+	config->buffer_size = 1;
+	/* Enable transferred interrupt */
+	config->cmd.set_interrupt = 1;
+	/* Channel stops when buffer done */
+	config->cmd.last = 1;
+	/* Set next command to 0 */
+	config->cmd.next_addr = 0;
+}
+
+/**
+ * \brief Update DMA descriptor.
+ *
+ * This function can update the descriptor of an allocated DMA resource.
+ *
+ */
+static inline void dma_update_descriptor(struct dma_resource *resource,
+		struct dma_descriptor* descriptor)
+{
+	resource->descriptor = descriptor;
+}
+
+/**
+ * \brief Reset DMA descriptor.
+ *
+ * This function will clear the DESCADDR register of an allocated DMA resource.
+ *
+ */
+static inline void dma_reset_descriptor(struct dma_resource *resource)
+{
+	resource->descriptor = NULL;
+}
+
+void dma_get_config_defaults(struct dma_resource_config *config);
+enum status_code dma_allocate(struct dma_resource *resource,
+		struct dma_resource_config *config);
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+		struct dma_descriptor* descriptor);
+enum status_code dma_start_transfer_job(struct dma_resource *resource);
+enum status_code dma_free(struct dma_resource *resource);
+uint8_t dma_get_status(uint8_t channel);
+uint8_t dma_get_interrupt_status(uint8_t channel);
+void dma_clear_interrupt_status(uint8_t channel, uint8_t flag);
+/** @} */
+
+/**
+ * \page asfdoc_samb_dma_extra Extra Information for DMAC Driver
+ *
+ * \section asfdoc_samb_dma_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Acronym</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>DMA</td>
+ *     <td>Direct Memory Access</td>
+ *   </tr>
+ *   <tr>
+ *     <td>DMAC</td>
+ *     <td>Direct Memory Access Controller </td>
+ *   </tr>
+ *   <tr>
+ *     <td>CPU</td>
+ *     <td>Central Processing Unit</td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_samb_dma_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_dma_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_dma_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Changelog</th>
+ *   </tr>
+ *   <tr>
+ *     <td>Initial Release</td>
+ *   </tr>
+ * </table>
+ */
+
+ /**
+ * \page asfdoc_samb_dma_exqsg Examples for DMAC Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_samb_dma_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_samb_dma_basic_use_case
+ *
+ * \note More DMA usage examples are available in peripheral QSGs.
+ *
+ * \page asfdoc_samb_dma_document_revision_history Document Revision History
+ *
+ * <table>
+ *    <tr>
+ *        <th>Doc. Rev.</td>
+ *        <th>Date</td>
+ *        <th>Comments</td>
+ *    </tr>
+ *    <tr>
+ *        <td>A</td>
+ *        <td>09/2015</td>
+ *        <td>Initial release</td>
+ *    </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DMA_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/module_config/conf_dma.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/module_config/conf_dma.h
new file mode 100644
index 0000000000..fff0a2c816
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/module_config/conf_dma.h
@@ -0,0 +1,51 @@
+/**
+ * \file
+ *
+ * \brief SAM Direct Memory Access Driver Configuration Header
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_DMA_H_INCLUDED
+#define CONF_DMA_H_INCLUDED
+
+#  define CONF_MAX_USED_CHANNEL_NUM     5
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.c
new file mode 100644
index 0000000000..6c37d26cd7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.c
@@ -0,0 +1,102 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM DSU CRC32 driver.
+ *
+ * This file defines a useful set of functions for DSU CRC32 on SAM devices.
+ *
+ * Copyright (c) 2016-2017 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <system_interrupt.h>
+#include <pac.h>
+#include <crc32.h>
+
+/**
+ * \brief Calculate CRC32 value of the input memory
+ *
+ * Calculate CRC32 value of the input memory.
+ *
+ * The read value must be complemented to match standard CRC32 implementations
+ * or kept non-inverted if used as starting point for subsequent CRC32 calculations.
+ *
+ * \param[in] addr    Memory address to calculate CRC32
+ * \param[in] len     Memory length to calculate CRC32
+ * \param[in,out] pcrc32 Initial value used for the CRC32 calculation, and CRC32 result after calculation
+ *
+ * \return Status of the configuration procedure.
+ *
+ * \retval STATUS_OK      If CRC32 calculation OK
+ * \retval STATUS_ERR_BAD_ADDRESS  The address was not aligned with 4 bytes.
+ 
+ * \retval STATUS_ERR_IO  A bus error is detected
+ */
+enum status_code dsu_crc32_cal(const uint32_t addr, const uint32_t len, uint32_t *pcrc32)
+{
+	if (addr & 0x00000003) {
+		return STATUS_ERR_BAD_ADDRESS;
+	}
+
+	system_interrupt_disable_global();
+	system_peripheral_unlock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
+
+	DSU->DATA.reg = *pcrc32;
+	DSU->ADDR.reg = addr;
+	DSU->LENGTH.reg = len;
+
+	DSU->CTRL.bit.CRC = 1;
+	while ((DSU->STATUSA.reg & DSU_STATUSA_DONE) != 1) {	
+	}
+
+	if (DSU->STATUSA.reg & DSU_STATUSA_BERR) {
+		system_peripheral_lock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
+		system_interrupt_enable_global();
+		return STATUS_ERR_IO;
+	}
+
+	*pcrc32 = DSU->DATA.reg;
+	DSU->STATUSA.reg = DSU_STATUSA_DONE;
+
+	system_peripheral_lock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
+	system_interrupt_enable_global();
+	return STATUS_OK;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.h
new file mode 100644
index 0000000000..5f4625052e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.h
@@ -0,0 +1,217 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM DSU CRC32 driver.
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef DSU_CRC32_H_INCLUDED
+#define DSU_CRC32_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_drivers_crc32_group SAM 32-bit cyclic redundancy check (CRC32) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's CRC32 (via DSU) functionality. The following
+ * driver API modes are covered by this manual:
+ *
+ *  - Polled APIs
+ *
+ * The following peripheral is used by this module:
+ *  - DSU (Device Service Unit)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_drivers_crc32_prerequisites
+ *  - \ref asfdoc_sam0_drivers_crc32_module_overview
+ *  - \ref asfdoc_sam0_drivers_crc32_special_considerations
+ *  - \ref asfdoc_sam0_drivers_crc32_api_overview
+ *
+ *
+ * \section asfdoc_sam0_drivers_crc32_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_drivers_crc32_module_overview Module Overview
+ *
+ * A cyclic redundancy check (CRC) is an error detection technique used to find accidental
+ * errors in data. It is commonly used to determine whether the data during a transmission,
+ * or data present in data and programme memories has been corrupted or not. A CRC takes a data
+ * stream or a block of data as input and generates a 16- or 32-bit output that can be appended
+ * to the data and used as a checksum. When the same data are later received or read, the device
+ * or application repeats the calculation.
+ * If the new CRC result does not match the one calculated earlier, the block contains a data error.
+ * The application will then detect this and may take a corrective action, such as requesting the data
+ * to be sent again or simply not using the incorrect data.
+ *
+ * The DSU unit provides support for calculating a 32-bit cyclic redundancy check (CRC32)
+ * value for a memory area (including flash and AHB RAM).
+ *
+ * \section asfdoc_sam0_drivers_crc32_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_sam0_drivers_crc32_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief CRC initialization function
+ *
+ * Enables CRC peripheral, clocks and initializes CRC driver.
+ */
+static inline void dsu_crc32_init(void)
+{
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+		/* Turn on the digital interface clock */
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_DSU);
+#else
+		/* Turn on the digital interface clock */
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_DSU);
+#endif
+
+}
+
+enum status_code dsu_crc32_cal(const uint32_t addr, const uint32_t len, uint32_t *pcrc32);
+
+#ifdef __cplusplus
+}
+#endif
+
+ /** @} */
+
+/**
+ * \page asfdoc_sam0_drivers_crc32_extra Extra Information for CRC32
+ *
+ * \section asfdoc_sam0_drivers_crc32_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>DSU</td>
+ *      <td>Device Service Unit</td>
+ * </tr>
+ *  <tr>
+ *      <td>CRC32</td>
+ *      <td>32-bit cyclic redundancy check</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_drivers_crc32_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - DSU
+ *
+ *
+ * \section asfdoc_sam0_drivers_crc32_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_drivers_crc32_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_drivers_crc32_exqsg Examples for CRC32
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_drivers_crc32_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_crc32_basic_use_case
+ *
+ * \page asfdoc_sam0_drivers_crc32_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *      <th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>06/2016</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ *
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif  /* DSU_CRC32_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.c
new file mode 100644
index 0000000000..9e235d6542
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.c
@@ -0,0 +1,323 @@
+/**
+ * \file
+ *
+ * \brief SAM DUALTIMER Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "dualtimer.h"
+
+static dualtimer_callback_t dualtimer_callback_timer1 = NULL;
+static dualtimer_callback_t dualtimer_callback_timer2 = NULL;
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given Dualtimer configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structures before being
+ * modified by the user application.
+ *
+ * \param[out]  config  Pointer to a DUALTIMER module configuration structure to set
+ */
+void dualtimer_get_config_defaults(struct dualtimer_config *config)
+{
+	config->timer1.timer_enable = true;
+	config->timer2.timer_enable = true;
+
+	config->timer1.counter_mode = DUALTIMER_PERIODIC_MODE;
+	config->timer2.counter_mode = DUALTIMER_PERIODIC_MODE;
+
+	config->timer1.counter_size = DUALTIMER_COUNTER_SIZE_32BIT;
+	config->timer2.counter_size = DUALTIMER_COUNTER_SIZE_32BIT;
+
+	config->timer1.clock_prescaler = DUALTIMER_CLOCK_PRESCALER_DIV1;
+	config->timer2.clock_prescaler = DUALTIMER_CLOCK_PRESCALER_DIV1;
+
+	config->timer1.interrup_enable = true;
+	config->timer2.interrup_enable = true;
+
+	config->timer1.load_value = 0;
+	config->timer2.load_value = 0;
+
+	config->clock_source = DUALTIMER_CLK_INPUT_0;
+}
+
+
+/**
+ * \brief Get Dualtimer module timer1/timer2 current value.
+ *
+ * \param[in]     timer        Timer1/Timer2
+ *
+ * \retval Timer1/Timer2 current value
+ */
+uint32_t dualtimer_get_value(enum dualtimer_timer timer)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		return DUALTIMER0->TIMER1VALUE.reg;
+	} else {
+		return DUALTIMER0->TIMER2VALUE.reg;
+	}
+}
+
+/**
+ * \brief Set Dualtimer module timer1/timer2 load value.
+ *
+ * \param[in]     timer        Timer1/Timer2
+ * \param[in]     cur_bg       Current/Background
+ * \param[in]     value        Load value
+ */
+void dualtimer_set_counter(enum dualtimer_timer timer,
+		enum dualtimer_set_register cur_bg, uint32_t value)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		if (cur_bg == DUALTIMER_SET_CURRUNT_REG) {
+			DUALTIMER0->TIMER1LOAD.reg = value;
+		} else {
+			DUALTIMER0->TIMER1BGLOAD.reg = value;
+		}
+	} else {
+		if (cur_bg == DUALTIMER_SET_CURRUNT_REG) {
+			DUALTIMER0->TIMER2LOAD.reg = value;
+			} else {
+			DUALTIMER0->TIMER2BGLOAD.reg = value;
+		}
+	}
+}
+
+/**
+ * \brief Get Dualtimer module timer1/timer2 raw interrupt status
+ *
+ * \param[in]     timer        Timer1/Timer2
+ *
+ * \retval The raw interrupt status of timer1/timer2
+ */
+uint8_t dualtimer_get_status(enum dualtimer_timer timer)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		return DUALTIMER0->TIMER1RIS.reg;
+	} else {
+		return DUALTIMER0->TIMER2RIS.reg;
+	}
+}
+
+/**
+ * \brief Get Dualtimer module timer1/timer2 interrupt status
+ *
+ * \param[in]     timer        Timer1/Timer2
+ *
+ * \retval The interrupt status of timer1/timer2
+ */
+uint8_t dualtimer_get_interrupt_status(enum dualtimer_timer timer)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		return DUALTIMER0->TIMER1MIS.reg;
+	} else {
+		return DUALTIMER0->TIMER2MIS.reg;
+	}
+}
+
+/**
+ * \brief Clear Dualtimer module timer1/timer2 interrupt status
+ *
+ * Clear the Dualtimer module timer1/timer2 interrupt status
+ *
+ * \param[in]     timer        Timer1/Timer2
+ */
+void dualtimer_clear_interrupt_status(enum dualtimer_timer timer)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		DUALTIMER0->TIMER1INTCLR.reg = 1;
+	} else {
+		DUALTIMER0->TIMER2INTCLR.reg = 1;
+	}
+}
+
+/**
+ * \brief Set Dualtimer module timer1/timer2 enable
+ *
+ * Enable the Dualtimer module timer1/timer2
+ *
+ * \param[in]     timer        Timer1/Timer2
+ */
+void dualtimer_enable(enum dualtimer_timer timer)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		DUALTIMER0->TIMER1CONTROL.reg |= DUALTIMER_TIMER1CONTROL_TIMER_ENABLE;
+	} else {
+		DUALTIMER0->TIMER2CONTROL.reg |= DUALTIMER_TIMER2CONTROL_TIMER_ENABLE;
+	}
+}
+
+/**
+ * \brief Set Dualtimer module timer1/timer2 disable
+ *
+ * Disable the Dualtimer module timer1/timer2
+ *
+ * \param[in]     timer        Timer1/Timer2
+ */
+void dualtimer_disable(enum dualtimer_timer timer)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		DUALTIMER0->TIMER1CONTROL.reg &= ~DUALTIMER_TIMER1CONTROL_TIMER_ENABLE;
+	} else {
+		DUALTIMER0->TIMER2CONTROL.reg &= ~DUALTIMER_TIMER2CONTROL_TIMER_ENABLE;
+	}
+}
+
+/**
+ * \brief Dualtimer ISR handler.
+ *
+ * Dualtimer ISR handler.
+ *
+ */
+static void dualtimer_isr_handler(void)
+{
+	if (dualtimer_get_interrupt_status(DUALTIMER_TIMER1)) {
+		dualtimer_clear_interrupt_status(DUALTIMER_TIMER1);
+		if (dualtimer_callback_timer1)
+			dualtimer_callback_timer1();
+	}
+	if (dualtimer_get_interrupt_status(DUALTIMER_TIMER2)) {
+		dualtimer_clear_interrupt_status(DUALTIMER_TIMER2);
+		if (dualtimer_callback_timer2)
+			dualtimer_callback_timer2();
+	}
+}
+
+/**
+ * \brief Initializes Dualtimer module instance.
+ *
+ * Initializes the Dualtimer module, based on the given
+ * configuration values.
+ *
+ * \param[in]     config       Pointer to the Dualtimer configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ */
+void dualtimer_init(const struct dualtimer_config *config)
+{
+	uint8_t regval = 0;
+
+	/* Global reset */
+	system_peripheral_reset(PERIPHERAL_DUALT_TIMER);
+
+	/* Common config */
+	if (config->timer1.timer_enable || config->timer2.timer_enable) {
+		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
+		LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
+		LPMCU_MISC_REGS0->LPMCU_CTRL.bit.DUALTIMER0_CLK_SEL = config->clock_source;
+	}
+	
+	/* Timer1 config */
+	if (config->timer1.timer_enable) {
+		if (config->timer1.counter_mode == DUALTIMER_ONE_SHOT_MODE) {
+			regval = DUALTIMER_TIMER1CONTROL_ONE_SHOT_COUNT_1;
+		} else if (config->timer1.counter_mode == DUALTIMER_FREE_RUNNING_MODE) {
+			regval = DUALTIMER_TIMER1CONTROL_TIMER_MODE_0;
+		} else if (config->timer1.counter_mode == DUALTIMER_PERIODIC_MODE) {
+			regval = DUALTIMER_TIMER1CONTROL_TIMER_MODE_1;
+		}
+		regval |= (DUALTIMER_TIMER1CONTROL_TIMER_SIZE &
+				((config->timer1.counter_size) << DUALTIMER_TIMER1CONTROL_TIMER_SIZE_Pos)) |
+				DUALTIMER_TIMER1CONTROL_TIMERPRE(config->timer1.clock_prescaler);
+		if (config->timer1.interrup_enable) {
+			regval |= DUALTIMER_TIMER1CONTROL_INTERRUPT_ENABLE;
+		}
+		DUALTIMER0->TIMER1LOAD.reg = config->timer1.load_value;
+		DUALTIMER0->TIMER1CONTROL.reg = regval;
+		LPMCU_MISC_REGS0->DUALTIMER0_CTRL.reg |= LPMCU_MISC_REGS_DUALTIMER0_CTRL_CNTR_1_ENABLE;
+		dualtimer_enable(DUALTIMER_TIMER1);
+	}
+
+	/* Timer2 config */
+	if (config->timer2.timer_enable) {
+		if (config->timer2.counter_mode == DUALTIMER_ONE_SHOT_MODE) {
+			regval = DUALTIMER_TIMER2CONTROL_ONE_SHOT_COUNT_1;
+		} else if (config->timer2.counter_mode == DUALTIMER_FREE_RUNNING_MODE) {
+			regval = DUALTIMER_TIMER2CONTROL_TIMER_MODE_0;
+		} else if (config->timer2.counter_mode == DUALTIMER_PERIODIC_MODE) {
+			regval = DUALTIMER_TIMER2CONTROL_TIMER_MODE_1;
+		}
+		regval |= (DUALTIMER_TIMER2CONTROL_TIMER_SIZE &
+				((config->timer2.counter_size) << DUALTIMER_TIMER2CONTROL_TIMER_SIZE_Pos)) |
+				DUALTIMER_TIMER2CONTROL_TIMERPRE(config->timer2.clock_prescaler);
+		if (config->timer2.interrup_enable) {
+			regval |= DUALTIMER_TIMER2CONTROL_INTERRUPT_ENABLE;
+		}
+		DUALTIMER0->TIMER2LOAD.reg = config->timer2.load_value;
+		DUALTIMER0->TIMER2CONTROL.reg = regval;
+		LPMCU_MISC_REGS0->DUALTIMER0_CTRL.reg |= LPMCU_MISC_REGS_DUALTIMER0_CTRL_CNTR_2_ENABLE;
+		dualtimer_enable(DUALTIMER_TIMER2);
+	}
+
+	system_register_isr(RAM_ISR_TABLE_DUALTIMER_INDEX, (uint32_t)dualtimer_isr_handler);
+}
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers and enable a callback function which is implemented by the user.
+ *
+ * \param[in]     callback_func Pointer to callback function
+ */
+void dualtimer_register_callback(enum dualtimer_timer timer, dualtimer_callback_t fun)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		dualtimer_callback_timer1 = fun;
+	} else {
+		dualtimer_callback_timer2 = fun;
+	}
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters and disable a callback function implemented by the user.
+ *
+ */
+void dualtimer_unregister_callback(enum dualtimer_timer timer)
+{
+	if (timer == DUALTIMER_TIMER1) {
+		dualtimer_callback_timer1 = NULL;
+	} else {
+		dualtimer_callback_timer2 = NULL;
+	}
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.h
new file mode 100644
index 0000000000..6d6c7784db
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.h
@@ -0,0 +1,416 @@
+/**
+ * \file
+ *
+ * \brief SAM DUALTIMER Driver for SAMB11
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef DUALTIMER_H_INCLUDED
+#define DUALTIMER_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_dualtimer_group SAM DUALTIMER
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's DUALTIMER functionality.
+ *
+ * The following peripherals are used by this module:
+ *  - DUALTIMER
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_dualtimer_prerequisites
+ *  - \ref asfdoc_samb_dualtimer_module_overview
+ *  - \ref asfdoc_samb_dualtimer_special_considerations
+ *  - \ref asfdoc_samb_dualtimer_extra_info
+ *  - \ref asfdoc_samb_dualtimer_examples
+ *  - \ref asfdoc_samb_dualtimer_api_overview
+ *
+ *
+ * \section asfdoc_samb_dualtimer_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_dualtimer_module_overview Module Overview
+ *  The dual-input timers module provides a set of timing and counting related functionality,
+ * and each timer could setup respective. The module can be configured to use an 16-,
+ * or 32-bit down-counter that can generate interrupts when they reach 0.
+ *
+ * \subsection asfdoc_samb_dual_timer_module_overview_counter_mode Counter Mode
+ * For each timer, the following modes of operation are available:
+ * - One-shot timer mode
+ *
+ *   The counter generates an interrupt once. When the counter reaches 0,
+ *   it halts until you reprogram it. You can do this using one of the following:
+ *
+ *   1. Clearing the one-shot count bit in the control register, in which case the
+ *     count proceeds according to the selection of Free-running or Periodic mode.
+ *   
+ *   2. Writing a new value to the Load Value register.
+ * - Free-running Mode
+ *
+ *   The counter wraps after reaching its zero value, and continues to count down from
+ *   the maximum value. This is the default mode.
+ * - Periodic Mode
+ *
+ *   The counter generates an interrupt at a constant interval, reloading the original
+ *   value after wrapping past zero.
+ *
+ * \subsection asfdoc_samb_dual_timer_module_overview_counter_size Counter Size
+ * Each timer module can be configured in one of two different counter
+ * sizes; 16-, and 32-bit. The size of the counter determines the maximum
+ * value it can count to before an overflow occurs and the count is reset back
+ * to zero. \ref asfdoc_sam0_count_size_vs_top "The table below" shows the
+ * maximum values for each of the possible counter sizes.
+ *
+ * \anchor asfdoc_sam0_count_size_vs_top
+ * <table>
+ *  <caption>Timer Counter Sizes and Their Maximum Count Values</caption>
+ *  <tr>
+ *    <th>Counter size</th>
+ *    <th>Max. (hexadecimal)</th>
+ *    <th>Max. (decimal)</th>
+ *  </tr>
+ *  <tr>
+ *    <td>16-bit</td>
+ *    <td>0xFFFF</td>
+ *    <td>65,535</td>
+ *  </tr>
+ *  <tr>
+ *    <td>32-bit</td>
+ *    <td>0xFFFFFFFF</td>
+ *    <td>4,294,967,295</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_samb_dual_timer_module_overview_clock Clock Settings
+ *
+ * \subsubsection asfdoc_sam0_dual_timer_module_overview_clock_selection Clock Selection
+ * The timers contain the PCLK and TIMCLK clock inputs. PCLK is the main APB system
+ * clock, and is used by the register interface. TIMCLK is the input to the prescale
+ * units and the decrementing counters.
+ *
+ * This provision of two clock inputs enables the counters to continue to run while 
+ * the APB system is in a sleep state when PCLK is disabled. External system control
+ * logic must handle the changeover periods when PCLK is disabled and enabled to ensure
+ * that the PCLK and TIMCLK inputs are fed with synchronous signals when any register
+ * access is to occur.
+ *
+ * \subsubsection asfdoc_sam0_dual_timer_module_overview_clock_prescaler Prescaler
+ * Each timer module in the SAM B11 has its own individual clock prescaler, which can
+ * be used to divide the input clock frequency used in the counter. This prescaler
+ * only scales the clock used to provide clock pulses for the counter to count, the clock
+ * can be divide to 1, 16, or 256.
+ *
+ * \section asfdoc_samb_dualtimer_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_samb_dualtimer_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_dualtimer_extra. This includes:
+ *  - \ref asfdoc_samb_dualtimer_extra_acronyms
+ *  - \ref asfdoc_samb_dualtimer_extra_dependencies
+ *  - \ref asfdoc_samb_dualtimer_extra_errata
+ *  - \ref asfdoc_samb_dualtimer_extra_history
+ *
+ *
+ * \section asfdoc_samb_dualtimer_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_dualtimer_exqsg.
+ *
+ *
+ * \section asfdoc_samb_dualtimer_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system_sam_b.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Type definition for a DUALTIMER module callback function. */
+typedef void (*dualtimer_callback_t)(void);
+
+/**
+ * \brief Specifies the timer1 or timer2.
+ *
+ * This enum specifies duatimer timer1 or timer2.
+ */
+enum dualtimer_timer {
+	/** Dualtimer timer1 */
+	DUALTIMER_TIMER1 = 0,
+	/** Dualtimer timer2 */
+	DUALTIMER_TIMER2,
+};
+
+/**
+ * \brief DUALTIMER module clock input.
+ *
+ * DUALTIMER module clock.
+ */
+enum dualtimer_clock_input {
+	/** source from clock input 0: 26MHz */
+	DUALTIMER_CLK_INPUT_0 = 0,
+	/** source from clock input 1: 13MHz */
+	DUALTIMER_CLK_INPUT_1,
+	/** source from clock input 2: 6.5MHz */
+	DUALTIMER_CLK_INPUT_2,
+	/** source from clock input 3: 3MHz*/
+	DUALTIMER_CLK_INPUT_3,
+};
+
+/**
+ * \brief Specifies if the counter is 16-bit, or 32-bit.
+ *
+ * This enum specifies counter with one-shot, free running or periodic counter mode.
+ */
+enum dualtimer_counter_mode {
+	/** Counter in one-shot mode */
+	DUALTIMER_ONE_SHOT_MODE = 0,
+	/** Counter is in free-running mode */
+	DUALTIMER_FREE_RUNNING_MODE,
+	/** Counter is in periodic mode */
+	DUALTIMER_PERIODIC_MODE,
+};
+
+/**
+ * \brief Dualtimer counter mode enum.
+ *
+ * This enum specify the maximum value it is possible to count to.
+ */
+enum dualtimer_counter_size {
+	/** 16-bit counter */
+	DUALTIMER_COUNTER_SIZE_16BIT = 0,
+	/** 32-bit counter */
+	DUALTIMER_COUNTER_SIZE_32BIT,
+};
+
+/**
+ * \brief Dualtimer clock prescaler values.
+ *
+ * This enum is used to choose the clock prescaler
+ * configuration. The prescaler divides the clock frequency of the
+ * Dual Timer module to make the counter count slower.
+ */
+enum dualtimer_clock_prescaler {
+	/** Divide clock by 1 */
+	DUALTIMER_CLOCK_PRESCALER_DIV1 = 0,
+	/** Divide clock by 16 */
+	DUALTIMER_CLOCK_PRESCALER_DIV16,
+	/** Divide clock by 256 */
+	DUALTIMER_CLOCK_PRESCALER_DIV256,
+};
+
+/**
+ * \brief Dualtimer set counter.
+ *
+ * This enum is used to choose set the load register or
+ * background load register. The difference to set load
+ * register is that writes to background register do not
+ * cause the counter to immediately restart from the new value.
+ */
+enum dualtimer_set_register {
+	/** Set current counter */
+	DUALTIMER_SET_CURRUNT_REG = 0,
+	/** Set background counter */
+	DUALTIMER_SET_BG_REG,
+};
+
+/**
+ * \brief Dualtimer private configuration structure.
+ *
+ * Private configuration struct for Dualtimer instance.
+ */
+struct dualtimer_private_config {
+	/** Enable timer */
+	bool timer_enable;
+	/** Selects one-shot or wrapping counter mode */
+	enum dualtimer_counter_mode counter_mode;
+	/** Selects 16-bit or 32- bit counter size */
+	enum dualtimer_counter_size counter_size;
+	/** Selects the prescaler value */
+	enum dualtimer_clock_prescaler clock_prescaler;
+	/** Enable the interrupt */
+	bool interrup_enable;
+	/** Counter load value */
+	uint32_t load_value;
+};
+
+/**
+ * \brief Dualtimer configuration structure.
+ *
+ * Configuration struct for Dualtimer instance. This structure should be
+ * initialized by the \ref dualtimer_get_config_defaults function before being
+ * modified by the user application.
+ */
+struct dualtimer_config {
+	/** Timer1 private configuration */
+	struct dualtimer_private_config timer1;
+	/** Timer2 private configuration */
+	struct dualtimer_private_config timer2;
+	/** Selects Dualtimer clock frequency */
+	enum dualtimer_clock_input clock_source;
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+void dualtimer_get_config_defaults(struct dualtimer_config *config);
+void dualtimer_init(const struct dualtimer_config *config);
+/** @} */
+
+/**
+ * \name Get and set value
+ * @{
+ */
+uint32_t dualtimer_get_value(enum dualtimer_timer timer);
+void dualtimer_set_counter(enum dualtimer_timer timer,
+		enum dualtimer_set_register cur_bg, uint32_t value);
+/** @} */
+
+/**
+ * \name Get and Clear status
+ * @{
+ */
+uint8_t dualtimer_get_status(enum dualtimer_timer timer);
+uint8_t dualtimer_get_interrupt_status(enum dualtimer_timer timer);
+void dualtimer_clear_interrupt_status(enum dualtimer_timer timer);
+/** @} */
+
+/**
+ * \name Enable and disable module
+ * @{
+ */
+void dualtimer_enable(enum dualtimer_timer timer);
+void dualtimer_disable(enum dualtimer_timer timer);
+/** @} */
+
+/**
+ * \name Callback
+ * @{
+ */
+void dualtimer_register_callback(enum dualtimer_timer timer, dualtimer_callback_t fun);
+void dualtimer_unregister_callback(enum dualtimer_timer timer);
+/** @} */
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_samb_dualtimer_extra Extra Information for DUALTIMER Driver
+ *
+ * \section asfdoc_samb_dualtimer_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>DUALTIMER</td>
+ *		<td>Dualtimer</td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_samb_dualtimer_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_dualtimer_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_dualtimer_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_dualtimer_exqsg Examples for DUALTIMER Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_dualtimer_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_dualtimer_basic_use_case
+ *
+ * \page asfdoc_samb_dualtimer_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *    <th>Doc. Rev.</td>
+ *    <th>Date</td>
+ *    <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *    <td>A</td>
+ *    <td>09/2015</td>
+ *    <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events.h
new file mode 100644
index 0000000000..78ee2bd4bc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events.h
@@ -0,0 +1,730 @@
+/**
+ * \file
+ *
+ * \brief SAM Event System Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef EVENTS_H_INCLUDED
+#define EVENTS_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_events_group SAM Event System (EVENTS) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's peripheral
+ * event resources and users within the device, including enabling and disabling
+ * of peripheral source selection and synchronization of clock domains between
+ * various modules. The following API modes is covered by this manual:
+ *  - Polled API
+ * \if EVENTS_INTERRUPT_HOOK_MODE
+ *  - Interrupt hook API
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - EVSYS (Event System Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_events_prerequisites
+ * - \ref asfdoc_sam0_events_module_overview
+ * - \ref asfdoc_sam0_events_special_considerations
+ * - \ref asfdoc_sam0_events_extra_info
+ * - \ref asfdoc_sam0_events_examples
+ * - \ref asfdoc_sam0_events_api_overview
+ *
+ *
+ * \section asfdoc_sam0_events_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_events_module_overview Module Overview
+ *
+ * Peripherals within the SAM devices are capable of generating two types of
+ * actions in response to given stimulus; set a register flag for later
+ * intervention by the CPU (using interrupt or polling methods), or generate
+ * event signals, which can be internally routed directly to other
+ * peripherals within the device. The use of events allows for direct actions
+ * to be performed in one peripheral in response to a stimulus in another
+ * without CPU intervention. This can lower the overall power consumption of the
+ * system if the CPU is able to remain in sleep modes for longer periods
+ * (SleepWalking), and lowers the latency of the system response.
+ *
+ * The event system is comprised of a number of freely configurable Event
+ * resources, plus a number of fixed Event Users. Each Event resource can be
+ * configured to select the input peripheral that will generate the events
+ * signal, as well as the synchronization path and edge detection mode.
+ * The fixed-function Event Users, connected to peripherals within the device,
+ * can then subscribe to an Event resource in a one-to-many relationship in order
+ * to receive events as they are generated. An overview of the event system
+ * chain is shown in
+ * \ref asfdoc_sam0_events_module_overview_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_events_module_overview_fig
+ * \dot
+ * digraph overview {
+ * rankdir=LR;
+ * node [label="Source\nPeripheral\n(Generator)" shape=ellipse style=filled fillcolor=lightgray] src_peripheral;
+ * node [label="Event\nResource A" shape=square style=""] event_gen0;
+ * node [label="Event\nUser X" shape=square style=""] event_user0;
+ * node [label="Event\nUser Y" shape=square style=""] event_user1;
+ * node [label="Destination\nPeripheral\n(User)" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral0;
+ * node [label="Destination\nPeripheral\n(User)" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral1;
+ *
+ * src_peripheral -> event_gen0;
+ * event_gen0 -> event_user0;
+ * event_gen0 -> event_user1;
+ * event_user0 -> dst_peripheral0;
+ * event_user1 -> dst_peripheral1;
+ * }
+ * \enddot
+ *
+ * There are many different events that can be routed in the device, which can
+ * then trigger many different actions. For example, an Analog Comparator module
+ * could be configured to generate an event when the input signal rises above
+ * the compare threshold, which then triggers a Timer Counter module to capture
+ * the current count value for later use.
+ *
+ * \subsection asfdoc_sam0_events_module_overview_event_channels Event Channels
+ * The Event module in each device consists of several channels, which can be
+ * freely linked to an event generator (i.e. a peripheral within the device
+ * that is capable of generating events). Each channel can be individually
+ * configured to select the generator peripheral, signal path, and edge detection
+ * applied to the input event signal, before being passed to any event user(s).
+ *
+ * Event channels can support multiple users within the device in a standardized
+ * manner. When an Event User is linked to an Event Channel, the channel will
+ * automatically handshake with all attached users to ensure that all modules
+ * correctly receive and acknowledge the event.
+ *
+ * \subsection asfdoc_sam0_events_module_overview_event_users Event Users
+ * Event Users are able to subscribe to an Event Channel, once it has been
+ * configured. Each Event User consists of a fixed connection to one of the
+ * peripherals within the device (for example, an ADC module, or Timer module)
+ * and is capable of being connected to a single Event Channel.
+ *
+ * \subsection asfdoc_sam0_events_module_overview_edge_detection Edge Detection
+ * For asynchronous events, edge detection on the event input is not possible,
+ * and the event signal must be passed directly between the event generator and
+ * event user. For synchronous and re-synchronous events, the input signal from
+ * the event generator must pass through an edge detection unit, so that only
+ * the rising, falling, or both edges of the event signal triggers an action in
+ * the event user.
+ *
+ * \subsection asfdoc_sam0_events_module_overview_path_selection Path Selection
+ * The event system in the SAM devices supports three signal path types from
+ * the event generator to Event Users: asynchronous, synchronous, and
+ * re-synchronous events.
+ *
+ * \subsubsection asfdoc_sam0_events_module_overview_path_selection_async Asynchronous Paths
+ * Asynchronous event paths allow for an asynchronous connection between the
+ * event generator and Event Users, when the source and destination
+ * peripherals share the same \ref asfdoc_sam0_system_clock_group "Generic Clock"
+ * channel. In this mode the event is propagated between the source and
+ * destination directly to reduce the event latency, thus no edge detection is
+ * possible. The asynchronous event chain is shown in
+ * \ref asfdoc_sam0_events_module_async_path_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_events_module_async_path_fig
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="Source\nPeripheral" shape=ellipse style=filled fillcolor=lightgray] src_peripheral;
+ *   node [label="<f0> EVSYS | <f1> Event\nChannel/User" fillcolor=white style="dashed" shape=record] events_chan;
+ *   node [label="Destination\nPeripheral" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral;
+ *
+ *   src_peripheral -> events_chan;
+ *   events_chan    -> dst_peripheral;
+ *
+ * }
+ * \enddot
+ * \note Identically shaped borders in the diagram indicate a shared generic clock channel.
+ *
+ * \subsubsection asfdoc_sam0_events_module_overview_path_selection_sync Synchronous Paths
+ * The Synchronous event path should be used when edge detection or interrupts
+ * from the event channel are required, and the source event generator and the
+ * event channel shares the same Generic Clock channel. The synchronous event
+ * chain is shown in
+ * \ref asfdoc_sam0_events_module_sync_path_fig "the figure below".
+ *
+ * Not all peripherals support Synchronous event paths; refer to the device datasheet.
+ *
+ * \anchor asfdoc_sam0_events_module_sync_path_fig
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="Source\nPeripheral" shape=ellipse style="filled, dashed" fillcolor=lightgray] src_peripheral;
+ *   node [label="<f0> EVSYS | <f1> Event\nChannel/User" fillcolor=white shape=record style="dashed"] events_chan;
+ *   node [label="Destination\nPeripheral" shape=ellipse style="filled, solid" fillcolor=lightgray] dst_peripheral;
+ *
+ *   src_peripheral -> events_chan;
+ *   events_chan    -> dst_peripheral;
+ *
+ * }
+ * \enddot
+ * \note Identically shaped borders in the diagram indicate a shared generic clock channel.
+ *
+ * \subsubsection asfdoc_sam0_events_module_overview_path_selection_resync Re-synchronous Paths
+ * Re-synchronous event paths are a special form of synchronous events, where
+ * when edge detection or interrupts from the event channel are required, but
+ * the event generator and the event channel use different Generic Clock
+ * channels. The re-synchronous path allows the Event System to synchronize the
+ * incoming event signal from the Event Generator to the clock of the Event
+ * System module to avoid missed events, at the cost of a higher latency due to
+ * the re-synchronization process. The re-synchronous event chain is shown in
+ * \ref asfdoc_sam0_events_module_resync_path_fig "the figure below".
+ *
+ * Not all peripherals support re-synchronous event paths; refer to the device datasheet.
+ * \anchor asfdoc_sam0_events_module_resync_path_fig
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="Source\nPeripheral" shape=ellipse style="filled, dotted" fillcolor=lightgray] src_peripheral;
+ *   node [label="<f0> EVSYS | <f1> Event\nChannel/User" fillcolor=white shape=record style="dashed"] events_chan;
+ *   node [label="Destination\nPeripheral" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral;
+ *
+ *   src_peripheral -> events_chan;
+ *   events_chan    -> dst_peripheral;
+ *
+ * }
+ * \enddot
+ * \note Identically shaped borders in the diagram indicate a shared generic clock channel.
+ *
+ * \subsection asfdoc_sam0_events_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_events_module_int_connections_fig "The diagram below"
+ * shows how this module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_events_module_int_connections_fig
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="Source\nPeripherals" shape=ellipse style=filled fillcolor=lightgray] src_peripheral;
+ *
+ *   subgraph driver {
+ *     node [label="<f0> EVSYS | <f1> Event Channels" fillcolor=white shape=record] events_chan;
+ *     node [label="<f0> EVSYS | <f1> Event Users" fillcolor=white shape=record] events_user;
+ *   }
+ *
+ *   node [label="Destination\nPeripherals" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral;
+ *
+ *   src_peripheral -> events_chan:f1 [label="Source\nMUXs"];
+ *   events_chan:f1 -> events_user:f1 [label="Channel\nMUXs"];
+ *   events_user:f1 -> dst_peripheral;
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_events_module_overview_config Configuring Events
+ * For SAM devices, several steps are required to properly configure an
+ * event chain, so that hardware peripherals can respond to events generated by
+ * each other, as listed below.
+ *
+ * \subsubsection asfdoc_sam0_events_module_overview_config_src Source Peripheral
+ *  -# The source peripheral (that will generate events) must be configured and
+ *     enabled.
+ *  -# The source peripheral (that will generate events) must have an output
+ *     event enabled.
+
+ * \subsubsection asfdoc_sam0_events_module_overview_config_evsys Event System
+ *  -# An event system channel must be allocated and configured with the
+ *     correct source peripheral selected as the channel's event generator.
+ *  -# The event system user must be configured and enabled, and attached to
+ #     event channel previously allocated.
+
+ * \subsubsection asfdoc_sam0_events_module_overview_config_dst Destination Peripheral
+ *  -# The destination peripheral (that will receive events) must be configured
+ *     and enabled.
+ *  -# The destination peripheral (that will receive events) must have an input
+ *     event enabled.
+ *
+ *
+ * \section asfdoc_sam0_events_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_events_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_events_extra. This includes:
+ * - \ref asfdoc_sam0_events_extra_acronyms
+ * - \ref asfdoc_sam0_events_extra_dependencies
+ * - \ref asfdoc_sam0_events_extra_errata
+ * - \ref asfdoc_sam0_events_extra_history
+ *
+ *
+ * \section asfdoc_sam0_events_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_events_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_events_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include "events_common.h"
+
+/**
+ * \brief Edge detect enum.
+ *
+ * Event channel edge detect setting.
+ *
+ */
+enum events_edge_detect {
+	/** No event output */
+	EVENTS_EDGE_DETECT_NONE,
+	/** Event on rising edge */
+	EVENTS_EDGE_DETECT_RISING,
+	/** Event on falling edge */
+	EVENTS_EDGE_DETECT_FALLING,
+	/** Event on both edges */
+	EVENTS_EDGE_DETECT_BOTH,
+};
+
+/**
+ * \brief Path selection enum.
+ *
+ * Event channel path selection.
+ *
+ */
+enum events_path_selection {
+	/** Select the synchronous path for this event channel */
+	EVENTS_PATH_SYNCHRONOUS,
+	/** Select the resynchronizer path for this event channel */
+	EVENTS_PATH_RESYNCHRONIZED,
+	/** Select the asynchronous path for this event channel */
+	EVENTS_PATH_ASYNCHRONOUS,
+};
+
+/**
+ * \brief Events configuration struct.
+ *
+ * This event configuration struct is used to configure each of the channels.
+ *
+ */
+struct events_config {
+	/** Select edge detection mode */
+	enum events_edge_detect    edge_detect;
+	/** Select events channel path */
+	enum events_path_selection path;
+	/** Set event generator for the channel */
+	uint8_t                    generator;
+	/** Clock source for the event channel */
+	uint8_t                    clock_source;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/** Run in standby mode for the channel */
+	bool                       run_in_standby;
+	/** Run On Demand */
+	bool                       on_demand;
+#endif
+};
+
+/**
+ * \brief No event generator definition.
+ *
+ * Use this to disable any peripheral event input to a channel. This can be useful
+ * if you only want to use a channel for software generated events.
+ *
+ */
+
+///@cond INTERNAL
+/**
+ * \internal
+ * Status bit offsets in the status register/interrupt register.
+ *
+ * @{
+ */
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+#  define _EVENTS_START_OFFSET_BUSY_BITS           16
+#  define _EVENTS_START_OFFSET_USER_READY_BIT      0
+#  define _EVENTS_START_OFFSET_DETECTION_BIT       16
+#  define _EVENTS_START_OFFSET_OVERRUN_BIT         0
+#else /* SAM D/R */
+#  define _EVENTS_START_OFFSET_BUSY_BITS           8
+#  define _EVENTS_START_OFFSET_USER_READY_BIT      0
+#  define _EVENTS_START_OFFSET_DETECTION_BIT       8
+#  define _EVENTS_START_OFFSET_OVERRUN_BIT         0
+#endif
+/** @} */
+///@endcond
+
+/**
+*  Definition for no generator selection.
+*/
+#define EVSYS_ID_GEN_NONE   0
+
+/**
+ * \brief Event channel resource.
+ *
+ * Event resource structure.
+ *
+ * \note The fields in this structure should not be altered by the user application;
+ *       they are reserved for driver internals only.
+ */
+struct events_resource {
+#if !defined(__DOXYGEN__)
+	/** Channel allocated for the event resource */
+	uint8_t channel;
+	/** Channel setting in CHANNEL register */
+	uint32_t channel_reg;
+#endif
+};
+
+#if EVENTS_INTERRUPT_HOOKS_MODE == true
+typedef void (*events_interrupt_hook)(struct events_resource *resource);
+
+/**
+ * \brief Event hook.
+ *
+ * Event hook structure.
+ *
+ */
+struct events_hook {
+	/** Event resource */
+	struct events_resource *resource;
+	/** Event hook function */
+	events_interrupt_hook hook_func;
+	/** Next event hook */
+	struct events_hook *next;
+};
+#endif
+
+/**
+ * \brief Initializes an event configurations struct to defaults.
+ *
+ * Initailizes an event configuration struct to predefined safe default settings.
+ *
+ * \param[in] config Pointer to an instance of \ref struct events_config
+ *
+ */
+void events_get_config_defaults(struct events_config *config);
+
+/**
+ * \brief Allocate an event channel and set configuration.
+ *
+ * Allocates an event channel from the event channel pool and sets
+ * the channel configuration.
+ *
+ * \param[out] resource Pointer to a \ref events_resource struct instance
+ * \param[in]  config   Pointer to a \ref events_config struct
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK            Allocation and configuration went successful
+ * \retval STATUS_ERR_NOT_FOUND No free event channel found
+ *
+ */
+enum status_code events_allocate(struct events_resource *resource, struct events_config *config);
+
+/**
+ * \brief Attach user to the event channel.
+ *
+ * Attach a user peripheral to the event channel to receive events.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct instance
+ * \param[in] user_id  A number identifying the user peripheral found in the device header file
+ *
+ * \return Status of the user attach procedure.
+ * \retval STATUS_OK No errors detected when attaching the event user
+ */
+enum status_code events_attach_user(struct events_resource *resource, uint8_t user_id);
+
+/**
+ * \brief Detach a user peripheral from the event channel.
+ *
+ * Deattach a user peripheral from the event channels so it does not receive any more events.
+ *
+ * \param[in] resource Pointer to an \ref event_resource struct instance
+ * \param[in] user_id  A number identifying the user peripheral found in the device header file
+ *
+ * \return Status of the user detach procedure.
+ * \retval STATUS_OK No errors detected when detaching the event user
+ */
+enum status_code events_detach_user(struct events_resource *resource, uint8_t user_id);
+
+/**
+ * \brief Check if a channel is busy.
+ *
+ * Check if a channel is busy, a channel stays busy until all users connected to the channel
+ * has handled an event.
+ *
+ * \param[in] resource Pointer to a \ref events_resource struct instance
+ *
+ * \return Status of the channels busy state.
+ * \retval true   One or more users connected to the channel has not handled the last event
+ * \retval false  All users are ready to handle new events
+ */
+bool events_is_busy(struct events_resource *resource);
+
+/**
+ * \brief Trigger software event.
+ *
+ * Trigger an event by software.
+ *
+ * \note Software event works on either a synchronous path or resynchronized path, and
+ * edge detection must be configured to rising-edge detection.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct
+ *
+ * \return Status of the event software procedure.
+ * \retval STATUS_OK No error was detected when the software tigger signal was issued
+ * \retval STATUS_ERR_UNSUPPORTED_DEV If the channel path is asynchronous and/or the
+ *                                    edge detection is not set to RISING
+ */
+enum status_code events_trigger(struct events_resource *resource);
+
+/**
+ * \brief Check if all users connected to the channel are ready.
+ *
+ * Check if all users connected to the channel are ready to handle incoming events.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct
+ *
+ * \return The ready status of users connected to an event channel.
+ * \retval true  All the users connected to the event channel are ready to handle incoming events
+ * \retval false One or more users connected to the event channel are not ready to handle incoming events
+ */
+bool events_is_users_ready(struct events_resource *resource);
+
+/**
+ * \brief Check if an event is detected on the event channel.
+ *
+ * Check if an event has been detected on the channel.
+ *
+ * \note This function will clear the event detected interrupt flag.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct
+ *
+ * \return Status of the event detection interrupt flag.
+ * \retval true  Event has been detected
+ * \retval false Event has not been detected
+ */
+bool events_is_detected(struct events_resource *resource);
+
+/**
+ * \brief Check if there has been an overrun situation on this channel.
+ *
+ * \note This function will clear the event overrun detected interrupt flag.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct
+ *
+ * \return Status of the event overrun interrupt flag.
+ * \retval true  Event overrun has been detected
+ * \retval false Event overrun has not been detected
+ */
+bool events_is_overrun(struct events_resource *resource);
+
+/**
+ * \brief Release allocated channel back the the resource pool.
+ *
+ * Release an allocated channel back to the resource pool to make it available for other purposes.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct
+ *
+ * \return Status of the channel release procedure.
+ * \retval STATUS_OK                  No error was detected when the channel was released
+ * \retval STATUS_BUSY                One or more event users have not processed the last event
+ * \retval STATUS_ERR_NOT_INITIALIZED Channel not allocated, and can therefore not be released
+ */
+enum status_code events_release(struct events_resource *resource);
+
+/**
+ * \brief Get the number of free channels.
+ *
+ * Get the number of allocatable channels in the events system resource pool.
+ *
+ * \return The number of free channels in the event system.
+ *
+ */
+uint8_t events_get_free_channels(void);
+
+
+///@cond INTERNAL
+/**
+ * \internal
+ * Function to find bit position in the CHSTATUS and INTFLAG register,
+ * and return bit mask of this position.
+ *
+ * @{
+ */
+uint32_t _events_find_bit_position(uint8_t channel, uint8_t start_offset);
+/** @} */
+///@endcond
+
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_events_extra Extra Information for EVENTS Driver
+ *
+ * \section asfdoc_sam0_events_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Acronym</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>CPU</td>
+ *     <td>Central Processing Unit</td>
+ *   </tr>
+ *   <tr>
+ *     <td>MUX</td>
+ *     <td>Multiplexer</td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_events_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Driver"
+ *
+ *
+ * \section asfdoc_sam0_events_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_events_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Changelog</th>
+ *   </tr>
+ *   <tr>
+ *     <td>Fix a bug in internal function _events_find_bit_position()</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Rewrite of events driver</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Initial Release</td>
+ *   </tr>
+ * </table>
+ */
+
+ /**
+ * \page asfdoc_sam0_events_exqsg Examples for EVENTS Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_events_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_events_basic_use_case
+ * \if EVENTS_INTERRUPT_HOOK_MODE
+ * - \subpage asfdoc_sam0_events_interrupt_hook_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_events_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42108G</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM D09 and SAM L22</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42108F</td>
+ *      <td>08/2015</td>
+ *      <td>Added support for SAM L21, SAM DA1, SAMR30 and SAM C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42108E</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for interrupt hook mode.
+ *         Added support for SAM R21 and SAM D10/D11.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42108D</td>
+ *      <td>01/2014</td>
+ *      <td>Update to support SAM D21 and corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42108C</td>
+ *      <td>11/2013</td>
+ *      <td>Fixed incorrect documentation for the event signal paths. Added
+ *          configuration steps overview to the documentation.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42108B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42108A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENTS_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_common.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_common.h
new file mode 100644
index 0000000000..b40db7cec8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_common.h
@@ -0,0 +1,71 @@
+/*
+ * \file
+ *
+ * \brief SAM Event System Controller Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _EVENTS_COMMON_H_INCLUDED_
+#define _EVENTS_COMMON_H_INCLUDED_
+
+/**
+ * \internal Internal module structure to manage necessary globals
+ *
+ *
+ */
+struct _events_module {
+	/* Allocated channels bitmask where 1 means allocated */
+	volatile uint32_t allocated_channels;
+	/* Free channels */
+	uint8_t           free_channels;
+
+#if EVENTS_INTERRUPT_HOOKS_MODE == true
+	/* Buffer to store a copy of the current interrupt flags */
+	volatile uint32_t interrupt_flag_buffer;
+	/* Buffer to store acknowledged interrupt sources */
+	volatile uint32_t interrupt_flag_ack_buffer;
+
+	/* Interrup hook linked list start pointer */
+	struct events_hook *hook_list;
+#endif
+};
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.c
new file mode 100644
index 0000000000..ee912b060e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.c
@@ -0,0 +1,235 @@
+/*
+ * \file
+ *
+ * \brief SAM Event System Controller Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "events.h"
+#include "events_hooks.h"
+#include "system_interrupt.h"
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+#  define _EVENTS_INTFLAGS_DETECT  0x0fff0000
+#  define _EVENTS_INTFLAGS_OVERRUN 0x00000fff
+#else
+#  define _EVENTS_INTFLAGS_DETECT  0x0f00ff00
+#  define _EVENTS_INTFLAGS_OVERRUN 0x000f00ff
+#endif
+#define _EVENTS_INTFLAGS_MASK (_EVENTS_INTFLAGS_DETECT | _EVENTS_INTFLAGS_OVERRUN)
+
+extern struct _events_module _events_inst;
+
+enum status_code events_create_hook(struct events_hook *hook, events_interrupt_hook func)
+{
+	/* Initialize the hook struct members */
+	hook->next      = NULL;
+	hook->resource  = NULL;
+	hook->hook_func = func;
+
+	return STATUS_OK;
+}
+
+enum status_code events_add_hook(struct events_resource *resource, struct events_hook *hook)
+{
+	struct events_hook *tmp_hook = NULL;
+
+	/* Associate the hook with the resource */
+	hook->resource = resource;
+
+	/* Check if this is the first hook in the list */
+	if (_events_inst.hook_list == NULL) {
+		_events_inst.hook_list = hook;
+	} else {
+		tmp_hook = _events_inst.hook_list;
+
+		/* Find the first free place in the list */
+		while (tmp_hook->next != NULL) {
+			tmp_hook = tmp_hook->next;
+		}
+
+		/* Put the hook into the next free place in the list */
+		tmp_hook->next = hook;
+	}
+
+	/* Check if interrupts from the EVSYS module is enabled in the interrupt controller */
+	if (!system_interrupt_is_enabled(SYSTEM_INTERRUPT_MODULE_EVSYS)) {
+		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EVSYS);
+	}
+
+	return STATUS_OK;
+}
+
+enum status_code events_del_hook(struct events_resource *resource, struct events_hook *hook)
+{
+	struct events_hook *tmp_hook = _events_inst.hook_list;
+	struct events_hook *last_hook = NULL;
+
+	if (tmp_hook != NULL) {
+		/* Check if the first hook in the list is the one we are looking for */
+		if (tmp_hook != hook) {
+			/* Don't double check the first hook */
+			tmp_hook = tmp_hook->next;
+
+			/* Check if the current hook is the one we are looking for */
+			while (tmp_hook != hook) {
+
+				/* If the current hook pointer is NULL the hook is not found in the list */
+				if(tmp_hook == NULL) {
+					return STATUS_ERR_NOT_FOUND;
+				}
+
+				last_hook = tmp_hook;
+				tmp_hook = tmp_hook->next;
+
+			}
+			/* Remove the current hook from the list */
+			last_hook->next = tmp_hook->next;
+		} else {
+			_events_inst.hook_list = tmp_hook->next;
+		}
+	} else {
+		/* No hooks where found in the list */
+		return STATUS_ERR_NO_MEMORY;
+	}
+
+	return STATUS_OK;
+}
+
+enum status_code events_enable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source)
+{
+	Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
+
+	if (source == EVENTS_INTERRUPT_DETECT) {
+		EVSYS->INTENSET.reg = _events_find_bit_position(resource->channel,
+				_EVENTS_START_OFFSET_DETECTION_BIT);
+	} else if (source == EVENTS_INTERRUPT_OVERRUN) {
+		EVSYS->INTENSET.reg = _events_find_bit_position(resource->channel,
+				_EVENTS_START_OFFSET_OVERRUN_BIT);
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+enum status_code events_disable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source)
+{
+	Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
+
+	if (source == EVENTS_INTERRUPT_DETECT) {
+		EVSYS->INTENCLR.reg = _events_find_bit_position(resource->channel,
+				_EVENTS_START_OFFSET_DETECTION_BIT);
+	} else if (source == EVENTS_INTERRUPT_OVERRUN) {
+		EVSYS->INTENCLR.reg = _events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_OVERRUN_BIT);
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+
+bool events_is_interrupt_set(struct events_resource *resource, enum events_interrupt_source source)
+{
+	Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
+
+	uint32_t bitpos;
+
+	if (source == EVENTS_INTERRUPT_DETECT) {
+		bitpos = _events_find_bit_position(resource->channel,
+				_EVENTS_START_OFFSET_DETECTION_BIT);
+	} else if (source == EVENTS_INTERRUPT_OVERRUN) {
+		bitpos = _events_find_bit_position(resource->channel,
+				_EVENTS_START_OFFSET_OVERRUN_BIT);
+	} else {
+		return false;
+	}
+
+	return (bool)(_events_inst.interrupt_flag_buffer & bitpos);
+}
+
+enum status_code events_ack_interrupt(struct events_resource *resource, enum events_interrupt_source source)
+{
+	Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
+
+	uint32_t bitpos;
+
+	if (source == EVENTS_INTERRUPT_DETECT) {
+		bitpos = _events_find_bit_position(resource->channel,
+				_EVENTS_START_OFFSET_DETECTION_BIT);
+	} else if (source == EVENTS_INTERRUPT_OVERRUN) {
+		bitpos = _events_find_bit_position(resource->channel,
+				_EVENTS_START_OFFSET_OVERRUN_BIT);
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	_events_inst.interrupt_flag_ack_buffer |= bitpos;
+
+	return STATUS_OK;
+}
+
+void EVSYS_Handler(void)
+{
+	struct events_hook *current_hook = _events_inst.hook_list;
+	uint32_t flag;
+
+	/* Synch the interrupt flag buffer with the hardware register */
+	flag = EVSYS->INTFLAG.reg;
+	_events_inst.interrupt_flag_buffer |= flag;
+	/* Clear all hardware interrupt flags */
+	EVSYS->INTFLAG.reg = _EVENTS_INTFLAGS_MASK;
+
+	/* Traverse the linked list */
+	while (current_hook != NULL) {
+		current_hook->hook_func(current_hook->resource);
+		current_hook = current_hook->next;
+	}
+
+	/* Clear acknowledged interrupt sources from the interrupt flag buffer */
+	flag = _events_inst.interrupt_flag_ack_buffer;
+	_events_inst.interrupt_flag_buffer &= ~flag;
+}
+
+
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.h
new file mode 100644
index 0000000000..f16e5e3363
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.h
@@ -0,0 +1,182 @@
+/**
+ * \file
+ *
+ * \brief SAM Event System Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "events.h"
+
+#ifndef _EVENTS_HOOKS_H_INCLUDED_
+#define _EVENTS_HOOKS_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_events_group
+ * @{
+ *
+ */
+
+/**
+ * \brief Interrupt source enumerator.
+ *
+ * Interrupt source selector definitions.
+ *
+ */
+enum events_interrupt_source {
+	/** Overrun in event channel detected interrupt */
+	EVENTS_INTERRUPT_OVERRUN,
+	/** Event signal propagation in event channel detected interrupt */
+	EVENTS_INTERRUPT_DETECT,
+};
+
+/**
+ * \brief Initializes an interrupt hook for insertion in the event interrupt hook queue.
+ *
+ * Initializes a hook structure so it is ready for insertion in the interrupt hook queue.
+ *
+ * \param[out] hook Pointer to an \ref events_hook struct instance
+ * \param[in]  hook_func Pointer to a function containing the interrupt hook code
+ *
+ * \return Status of the hook creation procedure.
+ * \retval STATUS_OK Creation and initialization of interrupt hook went successful
+ *
+ */
+enum status_code events_create_hook(struct events_hook *hook, events_interrupt_hook hook_func);
+
+/**
+ * \brief Insert hook into the event drivers interrupt hook queue.
+ *
+ * Inserts a hook into the event drivers interrupt hook queue.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct instance
+ * \param[in] hook     Pointer to an \ref events_hook struct instance
+ *
+ * \return Status of the insertion procedure.
+ * \retval STATUS_OK Insertion of hook went successful
+ *
+ */
+enum status_code events_add_hook(struct events_resource *resource, struct events_hook *hook);
+
+/**
+ * \brief Remove hook from the event drivers interrupt hook queue.
+ *
+ * Removes a hook from the event drivers interrupt hook queue.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct instance
+ * \param[in] hook     Pointer to an \ref events_hook struct instance
+ *
+ * \return Status of the removal procedure.
+ * \retval STATUS_OK Removal of hook went successful
+ * \retval STATUS_ERR_NO_MEMORY There are no hooks instances in the event driver interrupt hook list
+ * \retval STATUS_ERR_NOT_FOUND Interrupt hook not found in the event drivers interrupt hook list
+ *
+ */
+enum status_code events_del_hook(struct events_resource *resource, struct events_hook *hook);
+
+/**
+ * \brief Enable interrupt source.
+ *
+ * Enable an interrupt source so can trigger execution of an interrupt hook.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct instance
+ * \param[in] source   One of the members in the \ref events_interrupt_source enumerator
+ *
+ * \return Status of the interrupt source enable procedure.
+ * \retval STATUS_OK              Enabling of the interrupt source was successful
+ * \retval STATUS_ERR_INVALID_ARG Interrupt source does not exist
+ *
+ */
+enum status_code events_enable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source);
+
+/**
+ * \brief Disable interrupt source.
+ *
+ * Disable an interrupt source so can trigger execution of an interrupt hook.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct instance
+ * \param[in] source   One of the members in the \ref events_interrupt_source enumerator
+ *
+ * \return Status of the interrupt source enable procedure.
+ * \retval STATUS_OK              Enabling of the interrupt source went successful
+ * \retval STATUS_ERR_INVALID_ARG Interrupt source does not exist
+ *
+ */
+enum status_code events_disable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source);
+
+/**
+ * \brief Check if interrupt source is set.
+ *
+ * Check if an interrupt source is set and should be processed.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct instance
+ * \param[in] source   One of the members in the \ref events_interrupt_source enumerator
+ *
+ * \return Status of the interrupt source.
+ * \retval true  Interrupt source is set
+ * \retval false Interrupt source is not set
+ *
+ */
+bool events_is_interrupt_set(struct events_resource *resource, enum events_interrupt_source source);
+
+/**
+ * \brief Acknowledge an interrupt source.
+ *
+ * Acknowledge an interrupt source so the interrupt state is cleared in hardware.
+ *
+ * \param[in] resource Pointer to an \ref events_resource struct instance
+ * \param[in] source   One of the members in the \ref events_interrupt_source enumerator
+ *
+ * \return Status of the interrupt source.
+ * \retval STATUS_OK Interrupt source was acknowledged successfully
+ *
+ */
+enum status_code events_ack_interrupt(struct events_resource *resource, enum events_interrupt_source source);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_d_r_h/events.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_d_r_h/events.c
new file mode 100644
index 0000000000..ed8784417e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_d_r_h/events.c
@@ -0,0 +1,328 @@
+/*
+ * \file
+ *
+ * \brief SAM Event System Controller Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <events.h>
+#include <system.h>
+#include <system_interrupt.h>
+#include <status_codes.h>
+
+#define EVENTS_INVALID_CHANNEL                  0xff
+
+struct _events_module _events_inst = {
+		.allocated_channels = 0,
+		.free_channels      = EVSYS_CHANNELS,
+
+#if EVENTS_INTERRUPT_HOOKS_MODE == true
+		.interrupt_flag_buffer     = 0,
+		.interrupt_flag_ack_buffer = 0,
+
+		.hook_list                 = NULL,
+#endif
+};
+
+/**
+ * \internal
+ *
+ */
+uint32_t _events_find_bit_position(uint8_t channel, uint8_t start_offset)
+{
+	uint32_t pos;
+
+	if (channel < _EVENTS_START_OFFSET_BUSY_BITS) {
+		pos = 0x01UL << (start_offset + channel);
+	} else {
+		pos = 0x01UL << (start_offset + channel + _EVENTS_START_OFFSET_BUSY_BITS);
+	}
+
+	return pos;
+}
+
+static uint8_t _events_find_first_free_channel_and_allocate(void)
+{
+	uint8_t count;
+	uint32_t tmp;
+	bool allocated = false;
+
+	system_interrupt_enter_critical_section();
+
+	tmp = _events_inst.allocated_channels;
+
+	for(count = 0; count < EVSYS_CHANNELS; ++count) {
+
+		if(!(tmp & 0x00000001)) {
+			/* If free channel found, set as allocated and return number */
+
+			_events_inst.allocated_channels |= 1 << count;
+			_events_inst.free_channels--;
+			allocated = true;
+
+			break;
+
+		}
+
+		tmp = tmp >> 1;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	if(!allocated) {
+		return EVENTS_INVALID_CHANNEL;
+	} else {
+		return count;
+	}
+}
+
+static void _events_release_channel(uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	_events_inst.allocated_channels &= ~(1 << channel);
+	_events_inst.free_channels++;
+
+	system_interrupt_leave_critical_section();
+}
+
+
+/* This function is called by the system_init function, but should not be a public API call */
+#if defined(__GNUC__)
+#  pragma GCC diagnostic push
+#  pragma GCC diagnostic ignored "-Wmissing-prototypes"
+#endif
+void _system_events_init(void)
+{
+	/* Enable EVSYS register interface */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_EVSYS);
+
+	/* Make sure the EVSYS module is properly reset */
+	EVSYS->CTRL.reg = EVSYS_CTRL_SWRST;
+
+	while (EVSYS->CTRL.reg & EVSYS_CTRL_SWRST) {
+	}
+}
+#if defined(__GNUC__)
+#  pragma GCC diagnostic pop
+#endif
+
+void events_get_config_defaults(struct events_config *config)
+{
+	/* Check that config is something other than NULL */
+	Assert(config);
+
+	config->edge_detect  = EVENTS_EDGE_DETECT_RISING;
+	config->path         = EVENTS_PATH_SYNCHRONOUS;
+	config->generator    = EVSYS_ID_GEN_NONE;
+	config->clock_source = GCLK_GENERATOR_0;
+}
+
+enum status_code events_allocate(
+		struct events_resource *resource,
+		struct events_config *config)
+{
+	uint8_t new_channel;
+
+	Assert(resource);
+
+	new_channel = _events_find_first_free_channel_and_allocate();
+
+	if(new_channel == EVENTS_INVALID_CHANNEL) {
+		return STATUS_ERR_NOT_FOUND;
+	}
+
+	resource->channel = new_channel;
+
+	if (config->path != EVENTS_PATH_ASYNCHRONOUS) {
+		/* Set up a GLCK channel to use with the specific channel */
+		struct system_gclk_chan_config gclk_chan_conf;
+
+		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+		gclk_chan_conf.source_generator =
+				(enum gclk_generator)config->clock_source;
+		system_gclk_chan_set_config(EVSYS_GCLK_ID_0 + new_channel, &gclk_chan_conf);
+		system_gclk_chan_enable(EVSYS_GCLK_ID_0 + new_channel);
+	}
+
+	/* Save channel setting and configure it after user multiplexer */
+	resource->channel_reg = EVSYS_CHANNEL_CHANNEL(new_channel)       |
+			     EVSYS_CHANNEL_EVGEN(config->generator)   |
+			     EVSYS_CHANNEL_PATH(config->path)         |
+			     EVSYS_CHANNEL_EDGSEL(config->edge_detect);
+
+
+	return STATUS_OK;
+}
+
+
+enum status_code events_release(struct events_resource *resource)
+{
+	enum status_code err = STATUS_OK;
+
+	Assert(resource);
+
+	/* Check if channel is busy */
+	if(events_is_busy(resource)) {
+		return STATUS_BUSY;
+	}
+
+	if (!(_events_inst.allocated_channels & (1<<resource->channel))) {
+		err = STATUS_ERR_NOT_INITIALIZED;
+	} else {
+		_events_release_channel(resource->channel);
+	}
+
+	return err;
+}
+
+enum status_code events_trigger(struct events_resource *resource)
+{
+
+	Assert(resource);
+
+	system_interrupt_enter_critical_section();
+
+	/* Because of indirect access the channel must be set first */
+	((uint8_t*)&EVSYS->CHANNEL)[0] = EVSYS_CHANNEL_CHANNEL(resource->channel);
+
+	/* Assert if event path is asynchronous */
+	if (EVSYS->CHANNEL.reg & EVSYS_CHANNEL_PATH(EVENTS_PATH_ASYNCHRONOUS)) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Assert if event edge detection is not set to RISING */
+	if (!(EVSYS->CHANNEL.reg & EVSYS_CHANNEL_EDGSEL(EVENTS_EDGE_DETECT_RISING))) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+
+	/* The GCLKREQ bit has to be set while triggering the software event */
+	EVSYS->CTRL.reg = EVSYS_CTRL_GCLKREQ;
+
+	((uint16_t*)&EVSYS->CHANNEL)[0] = EVSYS_CHANNEL_CHANNEL(resource->channel) |
+					  EVSYS_CHANNEL_SWEVT;
+
+	EVSYS->CTRL.reg &= ~EVSYS_CTRL_GCLKREQ;
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+
+bool events_is_busy(struct events_resource *resource)
+{
+	Assert(resource);
+
+	return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_BUSY_BITS));
+}
+
+bool events_is_users_ready(struct events_resource *resource)
+{
+	Assert(resource);
+
+	return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_USER_READY_BIT));
+}
+
+bool events_is_detected(struct events_resource *resource)
+{
+	Assert(resource);
+
+	uint32_t flag = _events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_DETECTION_BIT);
+
+	/* Clear flag when read */
+	if (EVSYS->INTFLAG.reg & flag) {
+		EVSYS->INTFLAG.reg = flag;
+		return true;
+	}
+
+	return false;
+}
+
+bool events_is_overrun(struct events_resource *resource)
+{
+	Assert(resource);
+
+	uint32_t flag = _events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_OVERRUN_BIT);
+
+	/* Clear flag when read */
+	if (EVSYS->INTFLAG.reg & flag) {
+		EVSYS->INTFLAG.reg = flag;
+		return true;
+	}
+
+	return false;
+}
+
+enum status_code events_attach_user(struct events_resource *resource, uint8_t user_id)
+{
+	Assert(resource);
+
+	/* First configure user multiplexer: channel number is n + 1 */
+	EVSYS->USER.reg = EVSYS_USER_CHANNEL(resource->channel + 1) |
+			  EVSYS_USER_USER(user_id);
+
+	/* Then configure the channel */
+	EVSYS->CHANNEL.reg = resource->channel_reg;
+
+	return STATUS_OK;
+}
+
+enum status_code events_detach_user(struct events_resource *resource, uint8_t user_id)
+{
+
+	Assert(resource);
+
+	/* Write 0 to the channel bit field to select no input */
+	EVSYS->USER.reg = EVSYS_USER_USER(user_id);
+
+	return STATUS_OK;
+}
+
+uint8_t events_get_free_channels()
+{
+	return _events_inst.free_channels;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_l_c/events.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_l_c/events.c
new file mode 100644
index 0000000000..5c8e876ccf
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_l_c/events.c
@@ -0,0 +1,321 @@
+/*
+ * \file
+ *
+ * \brief SAM Event System Controller Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <events.h>
+#include <system.h>
+#include <system_interrupt.h>
+#include <status_codes.h>
+
+#define EVENTS_INVALID_CHANNEL                  0xff
+
+struct _events_module _events_inst = {
+		.allocated_channels = 0,
+		.free_channels      = EVSYS_CHANNELS,
+
+#if EVENTS_INTERRUPT_HOOKS_MODE == true
+		.interrupt_flag_buffer     = 0,
+		.interrupt_flag_ack_buffer = 0,
+
+		.hook_list                 = NULL,
+#endif
+};
+
+/**
+ * \internal
+ *
+ */
+uint32_t _events_find_bit_position(uint8_t channel, uint8_t start_offset)
+{
+	uint32_t pos;
+
+	pos = 0x01UL << (start_offset + channel);
+
+	return pos;
+}
+
+static uint8_t _events_find_first_free_channel_and_allocate(void)
+{
+	uint8_t count;
+	uint32_t tmp;
+	bool allocated = false;
+
+	system_interrupt_enter_critical_section();
+
+	tmp = _events_inst.allocated_channels;
+
+	for(count = 0; count < EVSYS_CHANNELS; ++count) {
+
+		if(!(tmp & 0x00000001)) {
+			/* If free channel found, set as allocated and return number */
+
+			_events_inst.allocated_channels |= 1 << count;
+			_events_inst.free_channels--;
+			allocated = true;
+
+			break;
+
+		}
+
+		tmp = tmp >> 1;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	if(!allocated) {
+		return EVENTS_INVALID_CHANNEL;
+	} else {
+		return count;
+	}
+}
+
+static void _events_release_channel(uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	_events_inst.allocated_channels &= ~(1 << channel);
+	_events_inst.free_channels++;
+
+	system_interrupt_leave_critical_section();
+}
+
+
+/* This function is called by the system_init function, but should not be a public API call */
+#if defined(__GNUC__)
+#  pragma GCC diagnostic push
+#  pragma GCC diagnostic ignored "-Wmissing-prototypes"
+#endif
+void _system_events_init(void)
+{
+#if (SAML22) || (SAMC20) || (SAMC21)
+	/* Enable EVSYS register interface */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_EVSYS);
+#else
+	/* Enable EVSYS register interface */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_EVSYS);
+#endif
+
+	/* Make sure the EVSYS module is properly reset */
+	EVSYS->CTRLA.reg = EVSYS_CTRLA_SWRST;
+
+	while (EVSYS->CTRLA.reg & EVSYS_CTRLA_SWRST) {
+	}
+}
+#if defined(__GNUC__)
+#  pragma GCC diagnostic pop
+#endif
+
+void events_get_config_defaults(struct events_config *config)
+{
+	/* Check that config is something other than NULL */
+	Assert(config);
+
+	config->edge_detect  = EVENTS_EDGE_DETECT_RISING;
+	config->path         = EVENTS_PATH_SYNCHRONOUS;
+	config->generator    = EVSYS_ID_GEN_NONE;
+	config->clock_source = GCLK_GENERATOR_0;
+	config->run_in_standby = false;
+	config->on_demand    = false;
+}
+
+enum status_code events_allocate(
+		struct events_resource *resource,
+		struct events_config *config)
+{
+	uint8_t new_channel;
+
+	Assert(resource);
+
+	new_channel = _events_find_first_free_channel_and_allocate();
+
+	if(new_channel == EVENTS_INVALID_CHANNEL) {
+		return STATUS_ERR_NOT_FOUND;
+	}
+
+	resource->channel = new_channel;
+
+	if (config->path != EVENTS_PATH_ASYNCHRONOUS) {
+		/* Set up a GLCK channel to use with the specific channel */
+		struct system_gclk_chan_config gclk_chan_conf;
+
+		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+		gclk_chan_conf.source_generator =
+				(enum gclk_generator)config->clock_source;
+		system_gclk_chan_set_config(EVSYS_GCLK_ID_0 + new_channel, &gclk_chan_conf);
+		system_gclk_chan_enable(EVSYS_GCLK_ID_0 + new_channel);
+	}
+
+	/* Save channel setting and configure it after user multiplexer */
+	resource->channel_reg = EVSYS_CHANNEL_EVGEN(config->generator)           |
+			EVSYS_CHANNEL_PATH(config->path)                                 |
+			((uint32_t)config->run_in_standby << EVSYS_CHANNEL_RUNSTDBY_Pos) |
+			((uint32_t)config->on_demand << EVSYS_CHANNEL_ONDEMAND_Pos) |
+			EVSYS_CHANNEL_EDGSEL(config->edge_detect);
+
+	return STATUS_OK;
+}
+
+
+enum status_code events_release(struct events_resource *resource)
+{
+	enum status_code err = STATUS_OK;
+
+	Assert(resource);
+
+	/* Check if channel is busy */
+	if(events_is_busy(resource)) {
+		return STATUS_BUSY;
+	}
+
+	if (!(_events_inst.allocated_channels & (1<<resource->channel))) {
+		err = STATUS_ERR_NOT_INITIALIZED;
+	} else {
+		_events_release_channel(resource->channel);
+	}
+
+	return err;
+}
+
+enum status_code events_trigger(struct events_resource *resource)
+{
+	Assert(resource);
+
+	system_interrupt_enter_critical_section();
+
+	/* Assert if event path is asynchronous */
+	if (EVSYS->CHANNEL[resource->channel].reg &
+			EVSYS_CHANNEL_PATH(EVENTS_PATH_ASYNCHRONOUS)) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Assert if event edge detection is not set to RISING */
+	if (!(EVSYS->CHANNEL[resource->channel].reg &
+			EVSYS_CHANNEL_EDGSEL(EVENTS_EDGE_DETECT_RISING))) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	EVSYS->SWEVT.reg = (0x01UL << resource->channel);
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+
+bool events_is_busy(struct events_resource *resource)
+{
+	Assert(resource);
+
+	return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_BUSY_BITS));
+}
+
+bool events_is_users_ready(struct events_resource *resource)
+{
+	Assert(resource);
+
+	return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_USER_READY_BIT));
+}
+
+bool events_is_detected(struct events_resource *resource)
+{
+	Assert(resource);
+
+	uint32_t flag = _events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_DETECTION_BIT);
+
+	/* Clear flag when read */
+	if (EVSYS->INTFLAG.reg & flag) {
+		EVSYS->INTFLAG.reg = flag;
+		return true;
+	}
+
+	return false;
+}
+
+bool events_is_overrun(struct events_resource *resource)
+{
+	Assert(resource);
+
+	uint32_t flag = _events_find_bit_position(resource->channel,
+			_EVENTS_START_OFFSET_OVERRUN_BIT);
+
+	/* Clear flag when read */
+	if (EVSYS->INTFLAG.reg & flag) {
+		EVSYS->INTFLAG.reg = flag;
+		return true;
+	}
+
+	return false;
+}
+
+enum status_code events_attach_user(struct events_resource *resource, uint8_t user_id)
+{
+	Assert(resource);
+
+	/* First configure user multiplexer: channel number is n + 1 */
+	EVSYS->USER[user_id].reg = EVSYS_USER_CHANNEL(resource->channel + 1);
+
+	/* Then configure the channel */
+	EVSYS->CHANNEL[resource->channel].reg = resource->channel_reg;
+
+	return STATUS_OK;
+}
+
+enum status_code events_detach_user(struct events_resource *resource, uint8_t user_id)
+{
+
+	Assert(resource);
+
+	/* Write 0 to the channel bit field to select no input */
+	EVSYS->USER[user_id].reg = 0;
+
+	return STATUS_OK;
+}
+
+uint8_t events_get_free_channels()
+{
+	return _events_inst.free_channels;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint.h
new file mode 100644
index 0000000000..1225881c3b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint.h
@@ -0,0 +1,708 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef EXTINT_H_INCLUDED
+#define EXTINT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_extint_group SAM External Interrupt (EXTINT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of external interrupts
+ * generated by the physical device pins, including edge detection.
+ * The following driver API modes are covered by this
+ * manual:
+ *
+ *  - Polled APIs
+ * \if EXTINT_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - EIC (External Interrupt Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_extint_prerequisites
+ *  - \ref asfdoc_sam0_extint_module_overview
+ *  - \ref asfdoc_sam0_extint_special_considerations
+ *  - \ref asfdoc_sam0_extint_extra_info
+ *  - \ref asfdoc_sam0_extint_examples
+ *  - \ref asfdoc_sam0_extint_api_overview
+ *
+ *
+ * \section asfdoc_sam0_extint_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_extint_module_overview Module Overview
+ *
+ * The External Interrupt (EXTINT) module provides a method of asynchronously
+ * detecting rising edge, falling edge, or specific level detection on individual
+ * I/O pins of a device. This detection can then be used to trigger a software
+ * interrupt or event, or polled for later use if required. External interrupts
+ * can also optionally be used to automatically wake up the device from sleep
+ * mode, allowing the device to conserve power while still being able to react
+ * to an external stimulus in a timely manner.
+ *
+ * \subsection asfdoc_sam0_extint_logical_channels Logical Channels
+ * The External Interrupt module contains a number of logical channels, each of
+ * which is capable of being individually configured for a given pin routing,
+ * detection mode, and filtering/wake up characteristics.
+ *
+ * Each individual logical external interrupt channel may be routed to a single
+ * physical device I/O pin in order to detect a particular edge or level of the
+ * incoming signal.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_nmi_chanel NMI Channels
+ *
+ * One or more Non Maskable Interrupt (NMI) channels are provided within each
+ * physical External Interrupt Controller module, allowing a single physical pin
+ * of the device to fire a single NMI interrupt in response to a particular
+ * edge or level stimulus. An NMI cannot, as the name suggests, be disabled in
+ * firmware and will take precedence over any in-progress interrupt sources.
+ *
+ * NMIs can be used to implement critical device features such as forced
+ * software reset or other functionality where the action should be executed in
+ * preference to all other running code with a minimum amount of latency.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_filtering Input Filtering and Detection
+ *
+ * To reduce the possibility of noise or other transient signals causing
+ * unwanted device wake-ups, interrupts, and/or events via an external interrupt
+ * channel. A hardware signal filter can be enabled on individual channels. This
+ * filter provides a Majority-of-Three voter filter on the incoming signal, so
+ * that the input state is considered to be the majority vote of three
+ * subsequent samples of the pin input buffer. The possible sampled input and
+ * resulting filtered output when the filter is enabled is shown in
+ * \ref asfdoc_sam0_extint_filter_table "the table below".
+ *
+ * \anchor asfdoc_sam0_extint_filter_table
+ * <table>
+ *  <caption>Sampled Input and Resulting Filtered Output</caption>
+ *  <tr>
+ *      <th>Input Sample 1</th>
+ *      <th>Input Sample 2</th>
+ *      <th>Input Sample 3</th>
+ *      <th>Filtered Output</th>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>0</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>0</td> <td>1</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>1</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>1</td> <td>1</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>0</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>0</td> <td>1</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>1</td> <td>0</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>1</td> <td>1</td> <td>1</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_events Events and Interrupts
+ *
+ * Channel detection states may be polled inside the application for synchronous
+ * detection, or events and interrupts may be used for asynchronous behavior.
+ * Each channel can be configured to give an asynchronous hardware event (which
+ * may in turn trigger actions in other hardware modules) or an asynchronous
+ * software interrupt.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_extint_int_connections "The diagram below" shows how this
+ * module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_extint_int_connections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="EIC Module" shape=ellipse] eic;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> eic;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_extint_special_considerations Special Considerations
+ *
+ * Not all devices support disabling of the NMI channel(s) detection mode - see
+ * your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_extint_extra. This includes:
+ *  - \ref asfdoc_sam0_extint_extra_acronyms
+ *  - \ref asfdoc_sam0_extint_extra_dependencies
+ *  - \ref asfdoc_sam0_extint_extra_errata
+ *  - \ref asfdoc_sam0_extint_extra_history
+ *
+ *
+ * \section asfdoc_sam0_extint_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_extint_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_extint_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief External interrupt edge detection configuration enum.
+ *
+ * Enum for the possible signal edge detection modes of the External
+ * Interrupt Controller module.
+ */
+enum extint_detect {
+	/** No edge detection. Not allowed as a NMI detection mode on some
+	 *  devices. */
+	EXTINT_DETECT_NONE    = 0,
+	/** Detect rising signal edges */
+	EXTINT_DETECT_RISING  = 1,
+	/** Detect falling signal edges */
+	EXTINT_DETECT_FALLING = 2,
+	/** Detect both signal edges */
+	EXTINT_DETECT_BOTH    = 3,
+	/** Detect high signal levels */
+	EXTINT_DETECT_HIGH    = 4,
+	/** Detect low signal levels */
+	EXTINT_DETECT_LOW     = 5,
+};
+
+/**
+ * \brief External interrupt internal pull configuration enum.
+ *
+ * Enum for the possible pin internal pull configurations.
+ *
+ * \note Disabling the internal pull resistor is not recommended if the driver
+ *       is used in interrupt (callback) mode, due the possibility of floating
+ *       inputs generating continuous interrupts.
+ */
+enum extint_pull {
+	/** Internal pull-up resistor is enabled on the pin */
+	EXTINT_PULL_UP        = SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Internal pull-down resistor is enabled on the pin */
+	EXTINT_PULL_DOWN      = SYSTEM_PINMUX_PIN_PULL_DOWN,
+	/** Internal pull resistor is disconnected from the pin */
+	EXTINT_PULL_NONE      = SYSTEM_PINMUX_PIN_PULL_NONE,
+};
+
+/** The EIC is clocked by GCLK_EIC. */
+#define EXTINT_CLK_GCLK   0
+/** The EIC is clocked by CLK_ULP32K. */
+#define EXTINT_CLK_ULP32K 1
+
+/**
+ * \brief External Interrupt Controller channel configuration structure.
+ *
+ *  Configuration structure for the edge detection mode of an external
+ *  interrupt channel.
+ */
+struct extint_chan_conf {
+	/** GPIO pin the NMI should be connected to */
+	uint32_t gpio_pin;
+	/** MUX position the GPIO pin should be configured to */
+	uint32_t gpio_pin_mux;
+	/** Internal pull to enable on the input pin */
+	enum extint_pull gpio_pin_pull;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/** Enable asynchronous edge detection. */
+	bool enable_async_edge_detection;
+#else
+	/** Wake up the device if the channel interrupt fires during sleep mode */
+	bool wake_if_sleeping;
+#endif
+	/** Filter the raw input signal to prevent noise from triggering an
+	 *  interrupt accidentally, using a three sample majority filter */
+	bool filter_input_signal;
+	/** Edge detection mode to use */
+	enum extint_detect detection_criteria;
+};
+
+/**
+ * \brief External Interrupt event enable/disable structure.
+ *
+ * Event flags for the \ref extint_enable_events() and
+ * \ref extint_disable_events().
+ */
+struct extint_events {
+	/** If \c true, an event will be generated when an external interrupt
+	 *  channel detection state changes */
+	bool generate_event_on_detect[32 * EIC_INST_NUM];
+};
+
+/**
+ * \brief External Interrupt Controller NMI configuration structure.
+ *
+ *  Configuration structure for the edge detection mode of an external
+ *  interrupt NMI channel.
+ */
+struct extint_nmi_conf {
+	/** GPIO pin the NMI should be connected to */
+	uint32_t gpio_pin;
+	/** MUX position the GPIO pin should be configured to */
+	uint32_t gpio_pin_mux;
+	/** Internal pull to enable on the input pin */
+	enum extint_pull gpio_pin_pull;
+	/** Filter the raw input signal to prevent noise from triggering an
+	 *  interrupt accidentally, using a three sample majority filter */
+	bool filter_input_signal;
+	/** Edge detection mode to use. Not all devices support all possible
+	 *  detection modes for NMIs.
+	 */
+	enum extint_detect detection_criteria;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/** Enable asynchronous edge detection. */
+	bool enable_async_edge_detection;
+#endif
+};
+
+#if EXTINT_CALLBACK_MODE == true
+/** Type definition for an EXTINT module callback function */
+typedef void (*extint_callback_t)(void);
+
+#ifndef EIC_NUMBER_OF_INTERRUPTS
+#  define EIC_NUMBER_OF_INTERRUPTS 16
+#endif
+#endif
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ *  Internal EXTINT module device instance structure definition.
+ */
+struct _extint_module
+{
+#  if EXTINT_CALLBACK_MODE == true
+	/** Asynchronous channel callback table, for user-registered handlers */
+	extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
+#  else
+	/** Dummy value to ensure the struct has at least one member */
+	uint8_t _dummy;
+#  endif
+};
+
+/**
+ * \brief Retrieves the base EIC module address from a given channel number.
+ *
+ * Retrieves the base address of a EIC hardware module associated with the
+ * given external interrupt channel.
+ *
+ * \param[in] channel  External interrupt channel index to convert
+ *
+ * \return Base address of the associated EIC module.
+ */
+static inline Eic * _extint_get_eic_from_channel(
+		const uint8_t channel)
+{
+	uint8_t eic_index = (channel / 32);
+
+	if (eic_index < EIC_INST_NUM) {
+		/* Array of available EICs */
+		Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+		return eics[eic_index];
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+
+/**
+ * \brief Retrieves the base EIC module address from a given NMI channel number.
+ *
+ * Retrieves the base address of a EIC hardware module associated with the
+ * given non-maskable external interrupt channel.
+ *
+ * \param[in] nmi_channel  Non-Maskable interrupt channel index to convert
+ *
+ * \return Base address of the associated EIC module.
+ */
+static inline Eic * _extint_get_eic_from_nmi(
+		const uint8_t nmi_channel)
+{
+	uint8_t eic_index = nmi_channel;
+
+	if (eic_index < EIC_INST_NUM) {
+		/* Array of available EICs */
+		Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+		return eics[eic_index];
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+#endif
+
+/** \name Event Management
+ * @{
+ */
+
+void extint_enable_events(
+		struct extint_events *const events);
+
+void extint_disable_events(
+		struct extint_events *const events);
+
+/** @} */
+
+/** \name Configuration and Initialization (Channel)
+ * @{
+ */
+
+void extint_chan_get_config_defaults(
+		struct extint_chan_conf *const config);
+
+void extint_chan_set_config(
+		const uint8_t channel,
+		const struct extint_chan_conf *const config);
+
+/** @} */
+
+/** \name Configuration and Initialization (NMI)
+ * @{
+ */
+
+/**
+ * \brief Initializes an External Interrupt NMI channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt NMI channel configuration structure
+ * to a set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Input filtering disabled
+ * \li Detect falling edges of a signal
+ * \li Asynchronous edge detection is disabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void extint_nmi_get_config_defaults(
+		struct extint_nmi_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->gpio_pin            = 0;
+	config->gpio_pin_mux        = 0;
+	config->gpio_pin_pull       = EXTINT_PULL_UP;
+	config->filter_input_signal = false;
+	config->detection_criteria  = EXTINT_DETECT_FALLING;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	 config->enable_async_edge_detection = false;
+#endif
+
+}
+
+enum status_code extint_nmi_set_config(
+		const uint8_t nmi_channel,
+		const struct extint_nmi_conf *const config);
+
+/** @} */
+
+/** \name Detection testing and clearing (channel)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the edge detection state of a configured channel.
+ *
+ *  Reads the current state of a configured channel, and determines
+ *  if the detection criteria of the channel has been met.
+ *
+ *  \param[in] channel  External Interrupt channel index to check
+ *
+ *  \return Status of the requested channel's edge detection state.
+ *  \retval true   If the channel's edge/level detection criteria was met
+ *  \retval false  If the channel has not detected its configured criteria
+ */
+static inline bool extint_chan_is_detected(
+		const uint8_t channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_channel(channel);
+	uint32_t eic_mask   = (1UL << (channel % 32));
+
+	return (eic_module->INTFLAG.reg & eic_mask);
+}
+
+/**
+ * \brief Clears the edge detection state of a configured channel.
+ *
+ *  Clears the current state of a configured channel, readying it for
+ *  the next level or edge detection.
+ *
+ *  \param[in] channel  External Interrupt channel index to check
+ */
+static inline void extint_chan_clear_detected(
+		const uint8_t channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_channel(channel);
+	uint32_t eic_mask   = (1UL << (channel % 32));
+
+	eic_module->INTFLAG.reg = eic_mask;
+}
+
+/** @} */
+
+/** \name Detection Testing and Clearing (NMI)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the edge detection state of a configured NMI channel.
+ *
+ *  Reads the current state of a configured NMI channel, and determines
+ *  if the detection criteria of the NMI channel has been met.
+ *
+ *  \param[in] nmi_channel  External Interrupt NMI channel index to check
+ *
+ *  \return Status of the requested NMI channel's edge detection state.
+ *  \retval true   If the NMI channel's edge/level detection criteria was met
+ *  \retval false  If the NMI channel has not detected its configured criteria
+ */
+static inline bool extint_nmi_is_detected(
+		const uint8_t nmi_channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+
+	return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
+}
+
+/**
+ * \brief Clears the edge detection state of a configured NMI channel.
+ *
+ *  Clears the current state of a configured NMI channel, readying it for
+ *  the next level or edge detection.
+ *
+ *  \param[in] nmi_channel  External Interrupt NMI channel index to check
+ */
+static inline void extint_nmi_clear_detected(
+		const uint8_t nmi_channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+
+	eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#if EXTINT_CALLBACK_MODE == true
+#  include "extint_callback.h"
+#endif
+
+/**
+ * \page asfdoc_sam0_extint_extra Extra Information for EXTINT Driver
+ *
+ * \section asfdoc_sam0_extint_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>EIC</td>
+ *      <td>External Interrupt Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MUX</td>
+ *      <td>Multiplexer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>NMI</td>
+ *      <td>Non-Maskable Interrupt</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *      \li Driver updated to follow driver type convention
+ *      \li Removed \c %extint_reset(), \c %extint_disable() and
+ *          \c extint_enable() functions. Added internal function
+ *          \c %_system_extint_init().
+ *      \li Added configuration EXTINT_CLOCK_SOURCE in conf_extint.h
+ *      \li Removed configuration EXTINT_CALLBACKS_MAX in conf_extint.h, and
+ *          added channel parameter in the register functions
+ *         \c %extint_register_callback() and \c %extint_unregister_callback()
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>Updated interrupt handler to clear interrupt flag before calling
+ *          callback function</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Updated initialization function to also enable the digital interface
+ *          clock to the module if it is disabled</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_extint_exqsg Examples for EXTINT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_extint_group.
+ * QSGs are simple examples with step-by-step instructions to configure and
+ * use this driver in a selection of use cases. Note that a QSG can be compiled
+ * as a standalone application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_extint_basic_use_case
+ * \if EXTINT_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_extint_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_extint_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42112E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM C21, SAM D09, and SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112B</td>
+ *      <td>06/2013</td>
+ *      <td>Added additional documentation on the event system. Corrected
+ *          documentation typos.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.c
new file mode 100644
index 0000000000..52424d7863
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.c
@@ -0,0 +1,232 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "extint.h"
+#include "extint_callback.h"
+
+/**
+ * \internal
+ * Internal driver device instance struct, declared in the main module driver.
+ */
+extern struct _extint_module _extint_dev;
+
+/**
+ * \internal
+ * This is the number of the channel whose callback is currently running.
+ */
+uint8_t _current_channel;
+
+/**
+ * \brief Registers an asynchronous callback function with the driver.
+ *
+ * Registers an asynchronous callback with the EXTINT driver, fired when a
+ * channel detects the configured channel detection criteria
+ * (e.g. edge or level). Callbacks are fired once for each detected channel.
+ *
+ * \note NMI channel callbacks cannot be registered via this function; the
+ *       device's NMI interrupt should be hooked directly in the user
+ *       application and the NMI flags manually cleared via
+ *       \ref extint_nmi_clear_detected().
+ *
+ * \param[in] callback  Pointer to the callback function to register
+ * \param[in] channel   Logical channel to register callback for
+ * \param[in] type      Type of callback function to register
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK               The callback was registered successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ * \retval STATUS_ERR_ALREADY_INITIALIZED    Callback function has been
+ *                                  registered, need unregister first
+ */
+enum status_code extint_register_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	/* Sanity check arguments */
+	Assert(callback);
+
+	if (type != EXTINT_CALLBACK_TYPE_DETECT) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (_extint_dev.callbacks[channel] == NULL) {
+		_extint_dev.callbacks[channel] = callback;
+		return STATUS_OK;
+	} else if (_extint_dev.callbacks[channel] == callback) {
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/**
+ * \brief Unregisters an asynchronous callback function with the driver.
+ *
+ * Unregisters an asynchronous callback with the EXTINT driver, removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] callback  Pointer to the callback function to unregister
+ * \param[in] channel   Logical channel to unregister callback for
+ * \param[in] type      Type of callback function to unregister
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK               The callback was unregistered successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ * \retval STATUS_ERR_BAD_ADDRESS  No matching entry was found in the
+ *                                 registration table
+ */
+enum status_code extint_unregister_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	/* Sanity check arguments */
+	Assert(callback);
+
+	if (type != EXTINT_CALLBACK_TYPE_DETECT) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (_extint_dev.callbacks[channel] == callback) {
+		_extint_dev.callbacks[channel] = NULL;
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_BAD_ADDRESS;
+}
+
+/**
+ * \brief Enables asynchronous callback generation for a given channel and type.
+ *
+ * Enables asynchronous callbacks for a given logical external interrupt channel
+ * and type. This must be called before an external interrupt channel will
+ * generate callback events.
+ *
+ * \param[in] channel  Logical channel to enable callback generation for
+ * \param[in] type     Type of callback function callbacks to enable
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK               The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code extint_chan_enable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	if (type == EXTINT_CALLBACK_TYPE_DETECT) {
+		Eic *const eic = _extint_get_eic_from_channel(channel);
+
+		eic->INTENSET.reg = (1UL << channel);
+	}
+	else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables asynchronous callback generation for a given channel and type.
+ *
+ * Disables asynchronous callbacks for a given logical external interrupt
+ * channel and type.
+ *
+ * \param[in] channel  Logical channel to disable callback generation for
+ * \param[in] type     Type of callback function callbacks to disable
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK               The callback was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code extint_chan_disable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	if (type == EXTINT_CALLBACK_TYPE_DETECT) {
+		Eic *const eic = _extint_get_eic_from_channel(channel);
+
+		eic->INTENCLR.reg = (1UL << channel);
+	}
+	else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Find what channel caused the callback.
+ *
+ * Can be used in an EXTINT callback function to find what channel caused
+ * the callback in case the same callback is used by multiple channels.
+ *
+ * \return Channel number.
+ */
+uint8_t extint_get_current_channel(void)
+{
+	return _current_channel;
+}
+
+/** Handler for the EXTINT hardware module interrupt. */
+void EIC_Handler(void)
+{
+	/* Find any triggered channels, run associated callback handlers */
+	for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) {
+		if (extint_chan_is_detected(_current_channel)) {
+			/* Clear flag */
+			extint_chan_clear_detected(_current_channel);
+			/* Find any associated callback entries in the callback table */
+			if (_extint_dev.callbacks[_current_channel] != NULL) {
+				/* Run the registered callback */
+				_extint_dev.callbacks[_current_channel]();
+			}
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.h
new file mode 100644
index 0000000000..35cf230185
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef EXTINT_CALLBACK_H_INCLUDED
+#define EXTINT_CALLBACK_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_extint_group
+ *
+ * @{
+ */
+
+/** \name Callback Configuration and Initialization
+ * @{
+ */
+
+/** Enum for the possible callback types for the EXTINT module. */
+enum extint_callback_type
+{
+	/** Callback type for when an external interrupt detects the configured
+	 *  channel criteria (i.e. edge or level detection)
+	 */
+	EXTINT_CALLBACK_TYPE_DETECT,
+};
+
+enum status_code extint_register_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+enum status_code extint_unregister_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+uint8_t extint_get_current_channel(void);
+
+/** @} */
+
+/** \name Callback Enabling and Disabling (Channel)
+ * @{
+ */
+
+enum status_code extint_chan_enable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+enum status_code extint_chan_disable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_d_r_h/extint.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_d_r_h/extint.c
new file mode 100644
index 0000000000..4fe9e8e695
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_d_r_h/extint.c
@@ -0,0 +1,425 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <system.h>
+#include <system_interrupt.h>
+#include <extint.h>
+#include <conf_extint.h>
+
+#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__)
+#  warning  EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0.
+
+/** Configuration option, setting the EIC clock source which can be used for
+ *  EIC edge detection or filtering. This option may be overridden in the module
+ *  configuration header file \c conf_extint.h.
+ */
+#  define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
+#endif
+
+/**
+ * \internal
+ * Internal driver device instance struct.
+ */
+struct _extint_module _extint_dev;
+
+/**
+ * \brief Determin if the general clock is required
+ *
+ * \param[in] filter_input_signal Filter the raw input signal to prevent noise
+ * \param[in] detection_criteria  Edge detection mode to use (\ref extint_detect)
+ */
+#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \
+		((filter_input_signal) ? true : (\
+			(EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
+			(EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
+			(EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
+
+static void _extint_enable(void);
+static void _extint_disable(void);
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+static inline bool extint_is_syncing(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) {
+			return true;
+		}
+	}
+	return false;
+}
+/**
+ * \internal
+ * \brief Initializes and enables the External Interrupt driver.
+ *
+ * Enable the clocks used by External Interrupt driver.
+ *
+ * Resets the External Interrupt driver, resetting all hardware
+ * module registers to their power-on defaults, then enable it for further use.
+ *
+ * Reset the callback list if callback mode is used.
+ *
+ * This function must be called before attempting to use any NMI or standard
+ * external interrupt channel functions.
+ *
+ * \note When SYSTEM module is used, this function will be invoked by
+ * \ref system_init() automatically if the module is included.
+ */
+void _system_extint_init(void);
+void _system_extint_init(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC);
+
+	/* Configure the generic clock for the module and enable it */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
+	system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
+
+	/* Enable the clock anyway, since when needed it will be requested
+	 * by External Interrupt driver */
+	system_gclk_chan_enable(EIC_GCLK_ID);
+
+	/* Reset all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRL.reg |= EIC_CTRL_SWRST;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	/* Reset the software module */
+#if EXTINT_CALLBACK_MODE == true
+	/* Clear callback registration table */
+	for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) {
+		_extint_dev.callbacks[j] = NULL;
+	}
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
+#endif
+
+	/* Enables the driver for further use */
+	_extint_enable();
+}
+
+/**
+ * \internal
+ * \brief Enables the External Interrupt driver.
+ *
+ * Enables EIC modules.
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_enable(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Enable all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRL.reg |= EIC_CTRL_ENABLE;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \internal
+ * \brief Disables the External Interrupt driver.
+ *
+ * Disables EIC modules that were previously started via a call to
+ * \ref _extint_enable().
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_disable(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Disable all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \brief Initializes an External Interrupt channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt channel configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Wake the device if an edge detection occurs whilst in sleep
+ * \li Input filtering disabled
+ * \li Internal pull-up enabled
+ * \li Detect falling edges of a signal
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void extint_chan_get_config_defaults(
+		struct extint_chan_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->gpio_pin            = 0;
+	config->gpio_pin_mux        = 0;
+	config->gpio_pin_pull       = EXTINT_PULL_UP;
+	config->wake_if_sleeping    = true;
+	config->filter_input_signal = false;
+	config->detection_criteria  = EXTINT_DETECT_FALLING;
+}
+
+/**
+ * \brief Writes an External Interrupt channel configuration to the hardware module.
+ *
+ * Writes out a given configuration of an External Interrupt channel
+ * configuration to the hardware module. If the channel is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] channel   External Interrupt channel to configure
+ * \param[in] config    Configuration settings for the channel
+
+ */
+void extint_chan_set_config(
+		const uint8_t channel,
+		const struct extint_chan_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+	/* Sanity check clock requirements */
+	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+		_extint_is_gclk_required(config->filter_input_signal,
+			config->detection_criteria)));
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = config->gpio_pin_mux;
+	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+	/* Get a pointer to the module hardware instance */
+	Eic *const EIC_module = _extint_get_eic_from_channel(channel);
+
+	uint32_t config_pos = (4 * (channel % 8));
+	uint32_t new_config;
+
+	/* Determine the channel's new edge detection configuration */
+	new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
+
+	/* Enable the hardware signal filter if requested in the config */
+	if (config->filter_input_signal) {
+		new_config |= EIC_CONFIG_FILTEN0;
+	}
+
+	/* Clear the existing and set the new channel configuration */
+	EIC_module->CONFIG[channel / 8].reg
+		= (EIC_module->CONFIG[channel / 8].reg &
+			~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
+			(new_config << config_pos);
+
+	/* Set the channel's new wake up mode setting */
+	if (config->wake_if_sleeping) {
+		EIC_module->WAKEUP.reg |=  (1UL << channel);
+	} else {
+		EIC_module->WAKEUP.reg &= ~(1UL << channel);
+	}
+}
+
+/**
+ * \brief Writes an External Interrupt NMI channel configuration to the hardware module.
+ *
+ *  Writes out a given configuration of an External Interrupt NMI channel
+ *  configuration to the hardware module. If the channel is already configured,
+ *  the new configuration will replace the existing one.
+ *
+ *  \param[in] nmi_channel   External Interrupt NMI channel to configure
+ *  \param[in] config        Configuration settings for the channel
+ *
+ * \returns Status code indicating the success or failure of the request.
+ * \retval  STATUS_OK                   Configuration succeeded
+ * \retval  STATUS_ERR_PIN_MUX_INVALID  An invalid pinmux value was supplied
+ * \retval  STATUS_ERR_BAD_FORMAT       An invalid detection mode was requested
+ */
+enum status_code extint_nmi_set_config(
+		const uint8_t nmi_channel,
+		const struct extint_nmi_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+	/* Sanity check clock requirements */
+	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+		_extint_is_gclk_required(config->filter_input_signal,
+			config->detection_criteria)));
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = config->gpio_pin_mux;
+	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pinmux_config.input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+	/* Get a pointer to the module hardware instance */
+	Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
+
+	uint32_t new_config;
+
+	/* Determine the NMI's new edge detection configuration */
+	new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
+
+	/* Enable the hardware signal filter if requested in the config */
+	if (config->filter_input_signal) {
+		new_config |= EIC_NMICTRL_NMIFILTEN;
+	}
+
+	/* Disable EIC and general clock to configure NMI */
+	_extint_disable();
+	system_gclk_chan_disable(EIC_GCLK_ID);
+
+	EIC_module->NMICTRL.reg = new_config;
+
+	/* Enable the general clock and EIC after configure NMI */
+	system_gclk_chan_enable(EIC_GCLK_ID);
+	_extint_enable();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables an External Interrupt event output.
+ *
+ *  Enables one or more output events from the External Interrupt module. See
+ *  \ref extint_events "here" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events    Struct containing flags of events to enable
+ */
+void extint_enable_events(
+		struct extint_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	/* Array of available EICs. */
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Update the event control register for each physical EIC instance */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		uint32_t event_mask = 0;
+
+		/* Create an enable mask for the current EIC module */
+		for (uint32_t j = 0; j < 32; j++) {
+			if (events->generate_event_on_detect[(32 * i) + j]) {
+				event_mask |= (1UL << j);
+			}
+		}
+
+		/* Enable the masked events */
+		eics[i]->EVCTRL.reg |= event_mask;
+	}
+}
+
+/**
+ * \brief Disables an External Interrupt event output.
+ *
+ *  Disables one or more output events from the External Interrupt module. See
+ *  \ref extint_events "here" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events    Struct containing flags of events to disable
+ */
+void extint_disable_events(
+		struct extint_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	/* Array of available EICs. */
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Update the event control register for each physical EIC instance */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		uint32_t event_mask = 0;
+
+		/* Create a disable mask for the current EIC module */
+		for (uint32_t j = 0; j < 32; j++) {
+			if (events->generate_event_on_detect[(32 * i) + j]) {
+				event_mask |= (1UL << j);
+			}
+		}
+
+		/* Disable the masked events */
+		eics[i]->EVCTRL.reg &= ~event_mask;
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_l_c/extint.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_l_c/extint.c
new file mode 100644
index 0000000000..1f5236222e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_l_c/extint.c
@@ -0,0 +1,491 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <system.h>
+#include <system_interrupt.h>
+#include <extint.h>
+#include <conf_extint.h>
+
+#if !defined(EXTINT_CLOCK_SELECTION) || defined(__DOXYGEN__)
+#  warning  EXTINT_CLOCK_SELECTION is not defined, assuming EXTINT_CLK_GCLK.
+
+/** Configuration option, setting the EIC clock source which can be used for
+ *  EIC edge detection or filtering. This option may be overridden in the module
+ *  configuration header file \c conf_extint.h.
+ */
+#  define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK
+#endif
+
+#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__)
+#  warning  EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0.
+
+/** Configuration option, setting the EIC clock source which can be used for
+ *  EIC edge detection or filtering. This option may be overridden in the module
+ *  configuration header file \c conf_extint.h.
+ */
+#  define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
+#endif
+#endif
+
+/**
+ * \internal
+ * Internal driver device instance struct.
+ */
+struct _extint_module _extint_dev;
+
+/**
+ * \brief Determin if the general clock is required.
+ *
+ * \param[in] filter_input_signal Filter the raw input signal to prevent noise
+ * \param[in] detection_criteria  Edge detection mode to use (\ref extint_detect)
+ */
+#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \
+		((filter_input_signal) ? true : (\
+			(EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
+			(EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
+			(EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
+
+static void _extint_enable(void);
+static void _extint_disable(void);
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+static inline bool extint_is_syncing(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		if((eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE)
+		 || (eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST)){
+			return true;
+		}
+	}
+	return false;
+}
+
+/**
+ * \internal
+ * \brief Initializes and enables the External Interrupt driver.
+ *
+ * Enable the clocks used by External Interrupt driver.
+ *
+ * Resets the External Interrupt driver, resetting all hardware
+ * module registers to their power-on defaults, then enable it for further use.
+ *
+ * Reset the callback list if callback mode is used.
+ *
+ * This function must be called before attempting to use any NMI or standard
+ * external interrupt channel functions.
+ *
+ * \note When SYSTEM module is used, this function will be invoked by
+ * \ref system_init() automatically if the module is included.
+ */
+void _system_extint_init(void);
+void _system_extint_init(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_EIC);
+
+#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	/* Configure the generic clock for the module and enable it */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
+	system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
+
+	/* Enable the clock anyway, since when needed it will be requested
+	 * by External Interrupt driver */
+	system_gclk_chan_enable(EIC_GCLK_ID);
+#endif
+
+	/* Reset all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.reg |= EIC_CTRLA_SWRST;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK;
+	}
+#else
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K;
+	}
+#endif
+
+	/* Reset the software module */
+#if EXTINT_CALLBACK_MODE == true
+	/* Clear callback registration table */
+	for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) {
+		_extint_dev.callbacks[j] = NULL;
+	}
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
+#endif
+
+	/* Enables the driver for further use */
+	_extint_enable();
+}
+
+/**
+ * \internal
+ * \brief Enables the External Interrupt driver.
+ *
+ * Enables EIC modules.
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_enable(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Enable all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.reg |= EIC_CTRLA_ENABLE;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \internal
+ * \brief Disables the External Interrupt driver.
+ *
+ * Disables EIC modules that were previously started via a call to
+ * \ref _extint_enable().
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_disable(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Disable all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \brief Initializes an External Interrupt channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt channel configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Input filtering disabled
+ * \li Internal pull-up enabled
+ * \li Detect falling edges of a signal
+ * \li Asynchronous edge detection is disabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void extint_chan_get_config_defaults(
+		struct extint_chan_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->gpio_pin            = 0;
+	config->gpio_pin_mux        = 0;
+	config->gpio_pin_pull       = EXTINT_PULL_UP;
+	config->filter_input_signal = false;
+	config->detection_criteria  = EXTINT_DETECT_FALLING;
+	config->enable_async_edge_detection = false;
+}
+
+/**
+ * \brief Writes an External Interrupt channel configuration to the hardware module.
+ *
+ * Writes out a given configuration of an External Interrupt channel
+ * configuration to the hardware module. If the channel is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] channel   External Interrupt channel to configure
+ * \param[in] config    Configuration settings for the channel
+
+ */
+void extint_chan_set_config(
+		const uint8_t channel,
+		const struct extint_chan_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+	_extint_disable();
+#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	/* Sanity check clock requirements */
+	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+		_extint_is_gclk_required(config->filter_input_signal,
+			config->detection_criteria)));
+#endif
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = config->gpio_pin_mux;
+	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+	/* Get a pointer to the module hardware instance */
+	Eic *const EIC_module = _extint_get_eic_from_channel(channel);
+
+	uint32_t config_pos = (4 * (channel % 8));
+	uint32_t new_config;
+
+	/* Determine the channel's new edge detection configuration */
+	new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
+
+	/* Enable the hardware signal filter if requested in the config */
+	if (config->filter_input_signal) {
+		new_config |= EIC_CONFIG_FILTEN0;
+	}
+
+	/* Clear the existing and set the new channel configuration */
+	EIC_module->CONFIG[channel / 8].reg
+		= (EIC_module->CONFIG[channel / 8].reg &
+			~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
+			(new_config << config_pos);
+#if (SAML22) || (SAML21XXXB) || (SAMC20) || (SAMR30)
+	/* Config asynchronous edge detection */
+	if (config->enable_async_edge_detection) {
+		EIC_module->ASYNCH.reg |= (1UL << channel);
+	} else {
+		EIC_module->ASYNCH.reg &= (EIC_ASYNCH_MASK & (~(1UL << channel)));
+	}
+#endif
+#if (SAMC21)
+	/* Config asynchronous edge detection */
+	if (config->enable_async_edge_detection) {
+		EIC_module->EIC_ASYNCH.reg |= (1UL << channel);
+	} else {
+		EIC_module->EIC_ASYNCH.reg &= (EIC_EIC_ASYNCH_MASK & (~(1UL << channel)));
+	}
+#endif
+	_extint_enable();
+}
+
+/**
+ * \brief Writes an External Interrupt NMI channel configuration to the hardware module.
+ *
+ *  Writes out a given configuration of an External Interrupt NMI channel
+ *  configuration to the hardware module. If the channel is already configured,
+ *  the new configuration will replace the existing one.
+ *
+ *  \param[in] nmi_channel   External Interrupt NMI channel to configure
+ *  \param[in] config        Configuration settings for the channel
+ *
+ * \returns Status code indicating the success or failure of the request.
+ * \retval  STATUS_OK                   Configuration succeeded
+ * \retval  STATUS_ERR_PIN_MUX_INVALID  An invalid pin mux value was supplied
+ * \retval  STATUS_ERR_BAD_FORMAT       An invalid detection mode was requested
+ */
+enum status_code extint_nmi_set_config(
+		const uint8_t nmi_channel,
+		const struct extint_nmi_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Sanity check clock requirements */
+	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+		_extint_is_gclk_required(config->filter_input_signal,
+			config->detection_criteria)));
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = config->gpio_pin_mux;
+	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pinmux_config.input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+	/* Get a pointer to the module hardware instance */
+	Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
+
+	uint32_t new_config;
+
+	/* Determine the NMI's new edge detection configuration */
+	new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
+
+	/* Enable the hardware signal filter if requested in the config */
+	if (config->filter_input_signal) {
+		new_config |= EIC_NMICTRL_NMIFILTEN;
+	}
+
+#if (SAML21XXXB) || (SAML22) || (SAMC21) || (SAMR30)
+	/* Enable asynchronous edge detection if requested in the config */
+	if (config->enable_async_edge_detection) {
+		new_config |= EIC_NMICTRL_NMIASYNCH;
+	}
+#endif
+	
+	/* Disable EIC and general clock to configure NMI */
+	_extint_disable();
+#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	system_gclk_chan_disable(EIC_GCLK_ID);
+#else
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++){
+		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK;
+		system_gclk_chan_disable(EIC_GCLK_ID);
+	}
+#endif
+
+	EIC_module->NMICTRL.reg = new_config;
+
+	/* Enable the EIC clock and EIC after configure NMI */
+#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	system_gclk_chan_enable(EIC_GCLK_ID);
+#else
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++){
+		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K;
+	}
+#endif
+	_extint_enable();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables an External Interrupt event output.
+ *
+ *  Enables one or more output events from the External Interrupt module. See
+ *  \ref extint_events "here" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events    Struct containing flags of events to enable
+ */
+void extint_enable_events(
+		struct extint_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	/* Array of available EICs. */
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	_extint_disable();
+
+	/* Update the event control register for each physical EIC instance */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		uint32_t event_mask = 0;
+
+		/* Create an enable mask for the current EIC module */
+		for (uint32_t j = 0; j < 32; j++) {
+			if (events->generate_event_on_detect[(32 * i) + j]) {
+				event_mask |= (1UL << j);
+			}
+		}
+
+		/* Enable the masked events */
+		eics[i]->EVCTRL.reg |= event_mask;
+	}
+	_extint_enable();
+}
+
+/**
+ * \brief Disables an External Interrupt event output.
+ *
+ *  Disables one or more output events from the External Interrupt module. See
+ *  \ref extint_events "here" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events    Struct containing flags of events to disable
+ */
+void extint_disable_events(
+		struct extint_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	/* Array of available EICs. */
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	_extint_disable();
+
+	/* Update the event control register for each physical EIC instance */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		uint32_t event_mask = 0;
+
+		/* Create a disable mask for the current EIC module */
+		for (uint32_t j = 0; j < 32; j++) {
+			if (events->generate_event_on_detect[(32 * i) + j]) {
+				event_mask |= (1UL << j);
+			}
+		}
+
+		/* Disable the masked events */
+		eics[i]->EVCTRL.reg &= ~event_mask;
+	}
+	_extint_enable();
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/module_config/conf_extint.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/module_config/conf_extint.h
new file mode 100644
index 0000000000..fd8611ec1a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/module_config/conf_extint.h
@@ -0,0 +1,65 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver Configuration Header
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_EXTINT_H_INCLUDED
+#define CONF_EXTINT_H_INCLUDED
+
+/** 
+ * Define which clock type is used to clock EIC peripheral:
+ *     - EXTINT_CLK_GCLK
+ *     - EXTINT_CLK_ULP32K
+ *
+ * EXTINT_CLK_ULP32K is available for SAM L21/C21.
+ */
+#define EXTINT_CLOCK_SELECTION   EXTINT_CLK_GCLK
+ 
+/**
+ * Define which GCLK source is used when selecting EXTINT_CLK_GCLK type.
+ */
+#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+#  define EXTINT_CLOCK_SOURCE      GCLK_GENERATOR_0
+#endif
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.c
new file mode 100644
index 0000000000..7eb58f4818
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.c
@@ -0,0 +1,163 @@
+/**
+ * \file
+ *
+ * \brief SAM Frequency Meter (FREQM) Driver
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "freqm.h"
+#include <gclk.h>
+
+#ifndef FREQM_GCLK_ID_REF
+#define FREQM_GCLK_ID_REF (FREQM_GCLK_ID_MSR + 1)
+#endif
+
+/**
+ * \brief Initializes a hardware FREQM module instance.
+ *
+ * Enables the clock and initializes the FREQM module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     hw           Pointer to the FREQM hardware module
+ * \param[in]     config       Pointer to the FREQM configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ */
+enum status_code freqm_init(
+		struct freqm_module *const module_inst,
+		Freqm *const hw,
+		struct freqm_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+	Assert(config->ref_clock_circles);
+
+	/* Initialize device instance */
+	module_inst->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_FREQM);
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->msr_clock_source;
+	system_gclk_chan_set_config(FREQM_GCLK_ID_MSR, &gclk_chan_conf);
+	system_gclk_chan_enable(FREQM_GCLK_ID_MSR);
+
+	gclk_chan_conf.source_generator = config->ref_clock_source;
+	system_gclk_chan_set_config(FREQM_GCLK_ID_REF, &gclk_chan_conf);
+	system_gclk_chan_enable(FREQM_GCLK_ID_REF);
+	
+	module_inst->ref_clock_freq = system_gclk_gen_get_hz(config->ref_clock_source);
+
+	/* Perform a software reset */
+	hw->CTRLA.reg = FREQM_CTRLA_SWRST;
+
+	while (freqm_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	/* Initialize the FREQM with new configurations */
+	hw->CFGA.reg = config->ref_clock_circles;
+
+#if FREQM_CALLBACK_MODE == true
+	/* Initialize parameters */
+	for (uint8_t i = 0; i < FREQM_CALLBACK_N; i++) {
+		module_inst->callback[i] = NULL;
+	}
+	/* Register this instance for callbacks*/
+	_freqm_instance = module_inst;
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Read the measurement data result
+ *
+ * Reads the measurement data result.
+ *
+ * \param[in]  module_inst  Pointer to the FREQM software instance struct
+ * \param[out] result       Pointer to store the result value in
+ *
+ * \return Status of the FREQM read request.
+ * \retval FREQM_STATUS_MEASURE_DONE   Measurement result was retrieved successfully
+ * \retval FREQM_STATUS_MEASURE_BUSY   Measurement result was not ready
+ * \retval FREQM_STATUS_CNT_OVERFLOW   Measurement result was overflow
+ *                              
+ * \note If overflow occurred, configure faster reference clock or reduce reference clock cycles.
+ */
+enum freqm_status freqm_get_result_value(
+		struct freqm_module *const module_inst, uint32_t *result)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(result);
+
+	Freqm *const freqm_hw = module_inst->hw;
+	uint32_t result_cal;
+	*result = result_cal= 0;
+
+	if (freqm_hw->STATUS.reg & FREQM_STATUS_BUSY) {
+		/* Result not ready */
+		return FREQM_STATUS_MEASURE_BUSY;
+	} else {
+		if (freqm_hw->STATUS.reg & FREQM_STATUS_OVF) {
+			/* Overflow */
+			return FREQM_STATUS_CNT_OVERFLOW;
+		} else {
+			/* Get measurement output data (it will clear data done flag) */
+			result_cal = freqm_hw->VALUE.reg;
+			freqm_hw->INTFLAG.reg = FREQM_INTFLAG_DONE;
+
+			*result = result_cal * module_inst->ref_clock_freq / freqm_hw->CFGA.reg;
+			return FREQM_STATUS_MEASURE_DONE;
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.h
new file mode 100644
index 0000000000..de97b00973
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.h
@@ -0,0 +1,436 @@
+/**
+ * \file
+ *
+ * \brief SAM Frequency Meter (FREQM) Driver
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef FREQM_H_INCLUDED
+#define FREQM_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_freqm_group SAM Frequency Meter (FREQM) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Frequency Meter functionality.
+ *
+ * The following driver API modes are covered by this manual:
+ * - Polled APIs
+ * \if FREQM_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - FREQM (Frequency Meter)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L22
+ *  - Atmel | SMART SAM C20
+ *  - Atmel | SMART SAM C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_freqm_prerequisites
+ *  - \ref asfdoc_sam0_freqm_module_overview
+ *  - \ref asfdoc_sam0_freqm_special_considerations
+ *  - \ref asfdoc_sam0_freqm_extra_info
+ *  - \ref asfdoc_sam0_freqm_examples
+ *  - \ref asfdoc_sam0_freqm_api_overview
+ *
+ *
+ * \section asfdoc_sam0_freqm_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_freqm_module_overview Module Overview
+ *
+ * The module accurately measures the frequency of a clock by comparing it to a
+ * known reference clock as soon as the FREQM is enabled. Two generic clocks are
+ * used by the FREQM. The frequency of the measured clock is:
+ * \f[
+ *    f_{CLK\_MSR} = \frac{VALUE}{REFNUM} \times f_{CLK\_REF}
+ * \f]
+ * Ratio can be measured with 24-bit accuracy.
+ *
+ * The FREQM has one interrupt source, which generates when a frequency measurement
+ * is done. It can be used to wake up the device from sleep modes.
+ *
+ * This driver provides an interface for the FREQM functions on the device.
+ *
+ * \section asfdoc_sam0_freqm_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_freqm_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_freqm_extra. This includes:
+ *  - \ref asfdoc_sam0_freqm_extra_acronyms
+ *  - \ref asfdoc_sam0_freqm_extra_dependencies
+ *  - \ref asfdoc_sam0_freqm_extra_errata
+ *  - \ref asfdoc_sam0_freqm_extra_history
+ *
+ *
+ * \section asfdoc_sam0_freqm_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_freqm_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_freqm_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if FREQM_CALLBACK_MODE == true
+/** Forward declaration of struct */
+struct freqm_module;
+
+extern struct freqm_module *_freqm_instance;
+
+/** Type definition for a FREQM module callback function. */
+typedef void (*freqm_callback_t)(void);
+
+/** Enum for possible callback types for the FREQM module. */
+enum freqm_callback {
+	/** Callback for measurement done */
+	FREQM_CALLBACK_DONE = 0,
+	/** Number of available callbacks */
+#if !defined(__DOXYGEN__)
+	FREQM_CALLBACK_N,
+#endif
+};
+#endif
+
+/**
+ * \brief FREQM software device instance structure.
+ *
+ * FREQM software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct freqm_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware module pointer of the associated FREQM peripheral */
+	Freqm *hw;
+	/** The frequency of reference clock in Hz*/
+	uint32_t ref_clock_freq;
+#  if FREQM_CALLBACK_MODE == true
+	/** Array of callbacks */
+	freqm_callback_t callback[FREQM_CALLBACK_N];
+#  endif
+#endif
+};
+
+/** Enum for the possible status types for the FREQM module. */
+enum freqm_status {
+	/** FREQM measurement is finish */
+	FREQM_STATUS_MEASURE_DONE =  0,
+	/** FREQM measurement is ongoing or not */
+	FREQM_STATUS_MEASURE_BUSY =  1,
+	/** FREQM sticky count value overflow */
+	FREQM_STATUS_CNT_OVERFLOW =  2,
+};
+
+/**
+ * \brief FREQM module configuration structure.
+ *
+ *  Configuration structure for a Frequency Meter.
+ */
+struct freqm_config {
+	/** GCLK source select for measurement */
+	enum gclk_generator msr_clock_source;
+	/** GCLK source select for reference */
+	enum gclk_generator ref_clock_source;
+	/** Measurement duration in number of reference clock cycles. Range 1~255 */
+	uint16_t ref_clock_circles;
+};
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false If the module has completed synchronization
+ * \retval true If the module synchronization is ongoing
+ */
+static inline bool freqm_is_syncing(void)
+{
+	Freqm *const freqm_module = FREQM;
+
+	if (freqm_module->SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+enum status_code freqm_init(
+		struct freqm_module *const module_inst,
+		Freqm *const hw,
+		struct freqm_config *const config);
+
+/**
+ * \brief Initializes all members of a FREQM configuration structure
+ *  to safe defaults.
+ *
+ *  Initializes all members of a given Frequency Meter configuration
+ *  structure to safe known default values. This function should be called on
+ *  all new instances of these configuration structures before being modified
+ *  by the user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Measurement clock source is GCLK0
+ *   \li Reference clock source is GCLK1
+ *   \li Frequency Meter Reference Clock Cycles 127
+ *
+ *  \param[in] config  Configuration structure to initialize to default values
+ */
+static inline void freqm_get_config_defaults(
+		struct freqm_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->msr_clock_source = GCLK_GENERATOR_0;
+	config->ref_clock_source = GCLK_GENERATOR_1;
+	config->ref_clock_circles = 127;
+}
+
+/**
+ * \brief Enables a FREQM that was previously configured.
+ *
+ * Enables Frequency Meter that was previously configured via a
+ * call to \ref freqm_init().
+ *
+ * \param[in] module_inst  Software instance for the Frequency Meter peripheral
+ */
+static inline void freqm_enable(
+		struct freqm_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Freqm *const freqm_module = module_inst->hw;
+
+	/* Enable FREQM */
+	freqm_module->CTRLA.reg |= FREQM_CTRLA_ENABLE;
+
+	while (freqm_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \brief Disables a FREQM that was previously enabled.
+ *
+ * Disables Frequency Meter that was previously started via a call
+ * to \ref freqm_enable().
+ *
+ * \param[in] module_inst  Software instance for the Frequency Meter peripheral
+ */
+static inline void freqm_disable(
+		struct freqm_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Freqm *const freqm_module = module_inst->hw;
+
+	/* Disbale interrupt */
+	freqm_module->INTENCLR.reg = FREQM_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	freqm_module->INTFLAG.reg = FREQM_INTFLAG_MASK;
+
+	/* Disable FREQM */
+	freqm_module->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
+
+	while (freqm_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/** @} */
+
+/**
+ * \name Read FREQM Result
+ * @{
+ */
+/**
+ * \brief Start a manual measurement process.
+ *
+ * \param[in] module Pointer to the FREQM software instance struct
+ */
+static inline void freqm_start_measure(struct freqm_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Trigger measurement */
+	module->hw->CTRLB.reg |= FREQM_CTRLB_START;
+}
+
+/**
+ * \brief Clears module overflow flag.
+ *
+ * Clears the overflow flag of the module.
+ *
+ * \param[in] module Pointer to the FREQM software instance struct
+ */
+static inline void freqm_clear_overflow(struct freqm_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Clear overflow flag */
+	module->hw->STATUS.reg = FREQM_STATUS_OVF;
+}
+
+enum freqm_status freqm_get_result_value(
+		struct freqm_module *const module_inst, uint32_t *result);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+/** @} */
+
+
+/**
+ * \page asfdoc_sam0_freqm_extra Extra Information for FREQM Driver
+ *
+ * \section asfdoc_sam0_freqm_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>FREQM</td>
+ *		<td>Frequency Meter</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_freqm_extra_dependencies Dependencies
+ * This driver has no dependencies.
+ *
+ *
+ * \section asfdoc_sam0_freqm_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_freqm_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+  *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_freqm_exqsg Examples for FREQM Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_freqm_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_freqm_basic_use_case
+ * \if FREQM_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_freqm_basic_use_case_callback
+ * \endif
+ *
+ * \page asfdoc_sam0_freqm_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42506A</td>
+ *		<td>08/2015</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* FREQM_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.c
new file mode 100644
index 0000000000..7de2ee3215
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.c
@@ -0,0 +1,142 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Frequency Meter driver.
+ *
+ * This file defines a useful set of functions for the FREQM on SAM devices.
+ *
+ * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "freqm.h"
+#include "freqm_callback.h"
+
+/** \internal Max number of callback type. */
+#define FREQM_CALLBACK_TYPE_NUM 1
+
+struct freqm_module *_freqm_instance;
+
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref freqm_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module        Pointer to FREQM software instance struct
+ * \param[in]     callback_func Pointer to callback function
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \retval STATUS_OK  The function exited successfully
+ */
+enum status_code freqm_register_callback(
+		struct freqm_module *const module,
+		freqm_callback_t callback_func,
+		enum freqm_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	if (callback_type >= FREQM_CALLBACK_TYPE_NUM) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function implemented by the user. The callback should be
+ * disabled before it is unregistered.
+ *
+ * \param[in]     module        Pointer to FREQM software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \retval STATUS_OK  The function exited successfully
+ */
+enum status_code freqm_unregister_callback(
+		struct freqm_module *module,
+		enum freqm_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	if (callback_type >= FREQM_CALLBACK_TYPE_NUM) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	return STATUS_OK;
+}
+
+
+
+/**
+* \internal The FREQM interrupt handler.
+*/
+void FREQM_Handler(void)
+{
+	/* Get device instance from the look-up table */
+	struct freqm_module *module = _freqm_instance;
+
+	/* Read and mask interrupt flag register */
+	uint32_t status = FREQM->INTFLAG.reg;
+
+	/* Check if data ready needs to be serviced */
+	if (status & FREQM_INTFLAG_DONE) {
+		if (module->callback[FREQM_CALLBACK_MEASURE_DONE]) {
+			FREQM->INTFLAG.reg = FREQM_INTFLAG_DONE;
+			module->callback[FREQM_CALLBACK_MEASURE_DONE]();
+		}
+	}
+
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.h
new file mode 100644
index 0000000000..0fe46e05d7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.h
@@ -0,0 +1,153 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Frequency Meter driver.
+ *
+ * This file defines a useful set of functions for the FREQM on SAM devices.
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef FREQM_CALLBACK_H_INCLUDED
+#define FREQM_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system_interrupt.h>
+/**
+ * \addtogroup asfdoc_sam0_freqm_group
+ *
+ * @{
+ */
+
+/** FREQM callback type. */
+enum freqm_callback_type {
+	/** Measurement done callback.*/
+	FREQM_CALLBACK_MEASURE_DONE = 0,
+};
+ 
+/** \name Callback Configuration and Initialization
+ * @{
+ */
+ 
+enum status_code freqm_register_callback(
+		struct freqm_module *const module,
+		freqm_callback_t callback_func,
+		enum freqm_callback callback_type);
+
+enum status_code freqm_unregister_callback(
+		struct freqm_module *module,
+		enum freqm_callback callback_type);
+
+/** @} */
+
+
+/** \name Callback Enabling and Disabling
+ * @{
+ */
+
+/**
+ * \brief Enable an FREQM callback.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] type Callback source type
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
+ */
+static inline enum status_code freqm_enable_callback(struct freqm_module *const module,
+		const enum freqm_callback_type type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	if (type == FREQM_CALLBACK_MEASURE_DONE){
+		module->hw->INTENSET.reg = FREQM_INTENSET_DONE;
+	} else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_FREQM);
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disable an FREQM callback.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in]  type Callback source type
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
+ */
+static inline enum status_code freqm_disable_callback(struct freqm_module *const module,
+		 const enum freqm_callback_type type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	if (type == FREQM_CALLBACK_MEASURE_DONE){
+		module->hw->INTENCLR.reg = FREQM_INTENCLR_DONE;
+	} else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_FREQM);
+	return STATUS_OK;
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* FREQM_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.c
new file mode 100644
index 0000000000..7c871f4eb9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.c
@@ -0,0 +1,588 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <gpio.h>
+
+/**
+ * \internal
+ * Internal driver device instance struct.
+ */
+struct gpio_module _gpio_instances[3];
+static void (*aon_handle_ext_wakeup_isr)(void) = (void (*)(void))0x1bc51;
+
+/**
+ *  \brief Initializes a gpio pin/group configuration structure to defaults.
+ *
+ *  Initializes a given gpio pin/group configuration structure to a set of
+ *  known default values. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Input mode with internal pullup enabled
+ *
+ *  \param[out] config  Configuration structure to initialize to default values.
+ */
+void gpio_get_config_defaults(struct gpio_config *const config)
+{
+	/* Default configuration values */
+	config->direction  = GPIO_PIN_DIR_INPUT;
+	config->input_pull = GPIO_PIN_PULL_UP;
+	config->powersave  = false;
+	config->aon_wakeup = false;
+}
+
+/**
+ *  \brief Writes a gpio pin configuration to the hardware module.
+ *
+ *  Writes out a given configuration of a gpio pin configuration to the hardware
+ *  module. If the configuration is NULL then it releases the gpio pin.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored. Also certain gpio pin is used by
+ *        FW and not available for user application. Please \ref gpio_pin
+ *        for list of gpio_pin available.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to configure.
+ *  \param[in] config    Configuration settings for the pin.
+ *
+ *  \return Status of initialization.
+ *  \retval STATUS_OK                       gpio configured correctly
+ *  \retval STATUS_ERR_INVALID_ARG          Invalid gpio number, Certain gpios
+ *                                          are used by FW and not allowed to change.
+ *  \retval STATUS_RESOURCE_NOT_AVAILABLE   Requested gpio is already in use.
+ *
+ */
+enum status_code gpio_pin_set_config(const uint8_t gpio_pin,
+		const struct gpio_config *config)
+{
+	enum status_code status = STATUS_OK;
+
+	/* Following GPIO's should never be modified by user.
+	* GPIO_0 & GPIO_1 are used for SWD.
+	*/
+	if ((gpio_pin == PIN_LP_GPIO_0) || \
+		(gpio_pin == PIN_LP_GPIO_1))
+	{
+		status = STATUS_ERR_INVALID_ARG;
+	} else {
+		if (gpio_pin <= 7) {
+			LPMCU_MISC_REGS0->PINMUX_SEL_0.reg &= ~(7 << ((gpio_pin % 8) * 4));
+		} else if (gpio_pin <= 15) {
+			LPMCU_MISC_REGS0->PINMUX_SEL_1.reg &= ~(7 << ((gpio_pin % 8) * 4));
+		} else if (gpio_pin <= 23) {
+			LPMCU_MISC_REGS0->PINMUX_SEL_2.reg &= ~(7 << ((gpio_pin % 8) * 4));
+		} else if (44 <= gpio_pin  && gpio_pin < 48) {
+			/* Set GPIO_MSx as digital mode */
+			AON_GP_REGS0->MS_GPIO_MODE.vec.ANALOG_ENABLE_ &= ~(1 << (gpio_pin - PIN_GPIO_MS4));
+		}
+	
+		if ((gpio_pin == PIN_AO_GPIO_0) || (gpio_pin == PIN_AO_GPIO_1) ||
+				(gpio_pin == PIN_AO_GPIO_2)) {
+			/* Active Low, Always On Pull Enable Control */
+			if (config->input_pull == GPIO_PIN_PULL_UP) {
+				AON_GP_REGS0->AON_PULL_ENABLE.reg &= ~(1 << (31 - gpio_pin));
+			} else {
+				AON_GP_REGS0->AON_PULL_ENABLE.reg |= 1 << (31 - gpio_pin);
+			}
+			if (config->aon_wakeup) {
+				/* Enable AON_GPIO_x to be a wakeup MCU from sleep mode */
+				AON_GP_REGS0->AON_PINMUX_SEL.reg |= 1 << (4 * (31 - gpio_pin));
+				/* Enable AON_GPIO_x to wake up the BLE domain from sleep mode */
+				AON_PWR_SEQ0->GPIO_WAKEUP_CTRL.bit.BLE_ENABLE = 1;
+			}
+		} else {
+			if(config->direction == GPIO_PIN_DIR_INPUT) {
+				if(gpio_pin < 16) {
+					GPIO0->OUTENCLR.reg = (1 << gpio_pin);
+				} else if (gpio_pin < 32){
+					GPIO1->OUTENCLR.reg = (1 << (gpio_pin % 16));
+				} else {
+					GPIO2->OUTENCLR.reg = (1 << (gpio_pin % 16));
+				}
+				/* pull_enable. */
+				if (gpio_pin < 32) {
+					switch(config->input_pull) {
+						case GPIO_PIN_PULL_NONE:
+							LPMCU_MISC_REGS0->PULL_ENABLE.reg |= (1 << gpio_pin);
+							break;
+						case GPIO_PIN_PULL_UP:
+							LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~(1 << gpio_pin);
+							break;
+						case GPIO_PIN_PULL_DOWN:
+							/* Set R-Type */
+							LPMCU_MISC_REGS0->RTYPE_PAD_0.reg |= (1 << gpio_pin);
+							/* Set REN */
+							LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~(1 << gpio_pin);
+							break;
+						default:
+							status = STATUS_ERR_INVALID_ARG;
+							break;
+					}
+				}
+			} else if(config->direction == GPIO_PIN_DIR_OUTPUT) {
+				if (gpio_pin < 16) {
+					GPIO0->OUTENSET.reg = (1 << gpio_pin);
+				} else if (gpio_pin < 32) {
+					GPIO1->OUTENSET.reg = (1 << (gpio_pin % 16));
+				} else {
+					GPIO2->OUTENSET.reg = (1 << (gpio_pin % 16));
+				}
+			}
+		}
+	}
+	return status;
+}
+
+/**
+ *  \brief Retrieves the state of a gpio pin that is configured as an input.
+ *
+ *  Reads the current logic level of a gpio pin and returns the current
+ *  level as a boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read.
+ *
+ *  \return Status of the gpio pin's input buffer.
+ */
+bool gpio_pin_get_input_level(const uint8_t gpio_pin)
+{
+	uint32_t regval = 0;
+
+	if (gpio_pin < 16) {
+		regval = GPIO0->DATA.reg;
+		regval &= (1 << gpio_pin);
+	} else if (gpio_pin < 32) {
+		regval = GPIO1->DATA.reg;
+		regval &= (1 << (gpio_pin % 16));
+	} else {
+		regval = GPIO2->DATA.reg;
+		regval &= (1 << (gpio_pin % 16));
+	}
+
+	return regval;
+}
+
+/**
+ *  \brief Retrieves the state of a gpio pin that is configured as an output.
+ *
+ *  Reads the current logical output level of a gpio pin and returns the current
+ *  level as a boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read.
+ *
+ *  \return Status of the gpio pin's output buffer.
+ */
+bool gpio_pin_get_output_level(const uint8_t gpio_pin)
+{
+	uint32_t regval = 0;
+
+	if (gpio_pin < 16) {
+		regval = GPIO0->DATAOUT.reg;
+		regval &= (1 << gpio_pin);
+	} else if (gpio_pin < 32) {
+		regval = GPIO1->DATAOUT.reg;
+		regval &= (1 << (gpio_pin % 16));
+	} else {
+		regval = GPIO2->DATAOUT.reg;
+		regval &= (1 << (gpio_pin % 16));
+	}
+
+	return regval;
+}
+
+/**
+ *  \brief Sets the state of a gpio pin that is configured as an output.
+ *
+ *  Sets the current output level of a gpio pin to a given logic level.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to write to.
+ *  \param[in] level     Logical level to set the given pin to.
+ */
+void gpio_pin_set_output_level(const uint8_t gpio_pin, const bool level)
+{
+	if (gpio_pin < 16) {
+		if(level) {
+			GPIO0->DATAOUT.reg |= (1 << gpio_pin);
+		} else {
+			GPIO0->DATAOUT.reg &= ~(1 << gpio_pin);
+		}
+	} else if (gpio_pin < 32) {
+		if(level) {
+			GPIO1->DATAOUT.reg |= (1 << (gpio_pin % 16));
+		} else {
+			GPIO1->DATAOUT.reg &= ~(1 << (gpio_pin % 16));
+		}
+	} else {
+		if(level) {
+			GPIO2->DATAOUT.reg |= (1 << (gpio_pin % 16));
+		} else {
+			GPIO2->DATAOUT.reg &= ~(1 << (gpio_pin % 16));
+		}
+	}
+}
+
+/**
+ *  \brief Toggles the state of a gpio pin that is configured as an output.
+ *
+ *  Toggles the current output level of a gpio pin.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to toggle.
+ */
+void gpio_pin_toggle_output_level(const uint8_t gpio_pin)
+{
+	if (gpio_pin < 16) {
+		GPIO0->DATAOUT.reg ^= (1 << gpio_pin);
+	} else if (gpio_pin < 32) {
+		GPIO1->DATAOUT.reg ^= (1 << (gpio_pin % 16));
+	} else {
+		GPIO2->DATAOUT.reg ^= (1 << (gpio_pin % 16));
+	}
+}
+
+/**
+ *  \brief Writes a GPIO pin configuration to the hardware module.
+ *
+ *  Writes out a given configuration of a GPIO pin configuration to the hardware
+ *  module.
+ *
+ *  \param[in] gpio_pin   Index of the GPIO pin to toggle.
+ *  \param[in] pinmux_sel PINMUX selection.
+ */
+void gpio_pinmux_cofiguration(const uint8_t gpio_pin, uint16_t pinmux_sel)
+{
+	uint8_t megamux_sel = (pinmux_sel >> 8) & 0xFF;
+
+	pinmux_sel &= 0xFF;
+
+	if (gpio_pin <= 7) {
+		LPMCU_MISC_REGS0->PINMUX_SEL_0.reg &= ~(7 << ((gpio_pin % 8) * 4));
+		LPMCU_MISC_REGS0->PINMUX_SEL_0.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
+		if (pinmux_sel == 0x01) {
+			if (gpio_pin <= 3) {
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_0.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_0.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+			} else if (gpio_pin <= 7) {
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_1.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_1.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+			}
+		}
+	} else if (gpio_pin <= 15) {
+		LPMCU_MISC_REGS0->PINMUX_SEL_1.reg &= ~(7 << ((gpio_pin % 8) * 4));
+		LPMCU_MISC_REGS0->PINMUX_SEL_1.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
+		if (pinmux_sel == 0x01) {
+			if (gpio_pin <= 11) {
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_2.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_2.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+			} else if (gpio_pin <= 15) {
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_3.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_3.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+			}
+		}
+	} else if (gpio_pin <= 23) {
+		LPMCU_MISC_REGS0->PINMUX_SEL_2.reg &= ~(7 << ((gpio_pin % 8) * 4));
+		LPMCU_MISC_REGS0->PINMUX_SEL_2.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
+		if (pinmux_sel == 0x01) {
+			if (gpio_pin <= 19) {
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_4.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_4.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+			} else if (gpio_pin <= 23) {
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_5.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_5.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+			}
+		}
+	}
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref gpio_enable_callback,
+ *       in order for the interrupt handler to call it when the conditions for
+ *       the callback type are met.
+ *
+ * \param[in]  gpio_pin       GPIO pin number
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void gpio_register_callback(uint8_t gpio_pin, gpio_callback_t callback_func,
+				enum gpio_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(callback_func);
+	Assert(gpio_pin < 48);
+
+	uint8_t gpio_port = 0;
+
+	if (gpio_pin < 16) {
+		gpio_port = 0;
+	} else if (gpio_pin < 32) {
+		gpio_port = 1;
+	} else {
+		gpio_port = 2;
+	}
+	switch (callback_type) {
+	case GPIO_CALLBACK_LOW:
+		_gpio_instances[gpio_port].hw->INTTYPECLR.reg = 1 << (gpio_pin % 16);
+		_gpio_instances[gpio_port].hw->INTPOLCLR.reg = 1 << (gpio_pin % 16);
+		break;
+
+	case GPIO_CALLBACK_HIGH:
+		_gpio_instances[gpio_port].hw->INTTYPECLR.reg = 1 << (gpio_pin % 16);
+		_gpio_instances[gpio_port].hw->INTPOLSET.reg = 1 << (gpio_pin % 16);
+		break;
+
+	case GPIO_CALLBACK_RISING:
+		_gpio_instances[gpio_port].hw->INTTYPESET.reg = 1 << (gpio_pin % 16);
+		_gpio_instances[gpio_port].hw->INTPOLSET.reg = 1 << (gpio_pin % 16);
+		break;
+
+	case GPIO_CALLBACK_FALLING:
+		_gpio_instances[gpio_port].hw->INTTYPESET.reg = 1 << (gpio_pin % 16);
+		_gpio_instances[gpio_port].hw->INTPOLCLR.reg = (1 << (gpio_pin % 16));
+		break;
+
+	case GPIO_CALLBACK_N:
+		break;
+	}
+	/* Register callback function */
+	_gpio_instances[gpio_port].callback[gpio_pin % 16] = callback_func;
+	/* Set the bit corresponding to the gpio pin */
+	_gpio_instances[gpio_port].callback_reg_mask |= (1 << (gpio_pin % 16));
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ *
+ * \param[in]  gpio_pin       GPIO pin number
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void gpio_unregister_callback(uint8_t gpio_pin,
+				enum gpio_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(callback_func);
+	Assert(gpio_pin < 48);
+
+	uint8_t gpio_port = 0;
+
+	if (gpio_pin < 16) {
+		gpio_port = 0;
+	} else if (gpio_pin < 32) {
+		gpio_port = 1;
+	} else {
+		gpio_port = 2;
+	}
+
+	/* Unregister callback function */
+	_gpio_instances[gpio_port].callback[gpio_pin % 16] = NULL;
+	/* Set the bit corresponding to the gpio pin */
+	_gpio_instances[gpio_port].callback_reg_mask &= ~(1 << (gpio_pin % 16));
+}
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref gpio_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in]  gpio_pin   GPIO pin
+ */
+void gpio_enable_callback(uint8_t gpio_pin)
+{
+	Assert(gpio_pin < 48);
+
+	uint8_t gpio_port = 0;
+
+	if (gpio_pin < 16) {
+		gpio_port = 0;
+		NVIC_EnableIRQ(GPIO0_IRQn);
+	} else if (gpio_pin < 32) {
+		gpio_port = 1;
+		NVIC_EnableIRQ(GPIO1_IRQn);
+	} else {
+		gpio_port = 2;
+		NVIC_EnableIRQ(GPIO2_IRQn);
+	}
+
+	/* Enable callback */
+	_gpio_instances[gpio_port].callback_enable_mask |= (1 << (gpio_pin % 16));
+	_gpio_instances[gpio_port].hw->INTENSET.reg = (1 << (gpio_pin % 16));
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback function registered by the \ref usart_register_callback.
+ * The callback function will not be called from the interrupt handler.
+ *
+ * \param[in]  gpio_pin   GPIO pin
+ */
+void gpio_disable_callback(uint8_t gpio_pin)
+{
+	Assert(gpio_pin < 48);
+
+	uint8_t gpio_port = 0;
+
+	if (gpio_pin < 16) {
+		gpio_port = 0;
+	} else if (gpio_pin < 32) {
+		gpio_port = 1;
+	} else {
+		gpio_port = 2;
+	}
+
+	/* Enable callback */
+	_gpio_instances[gpio_port].callback_enable_mask &= ~(1 << (gpio_pin % 16));
+	_gpio_instances[gpio_port].hw->INTENCLR.reg = (1 << (gpio_pin % 16));
+}
+
+/**
+ * \internal GPIO port0 isr handler.
+ *
+ * This function will enter interrupt.
+ *
+ */
+static void gpio_port0_isr_handler(void)
+{
+	uint32_t flag = _gpio_instances[0].hw->INTSTATUSCLEAR.reg;
+
+	for (uint8_t i = 0; i < 16; i++){
+		if (flag & (1 << i)) {
+			/* Clear interrupt flag */
+			_gpio_instances[0].hw->INTSTATUSCLEAR.reg = (1 << i);
+			if ((_gpio_instances[0].callback_enable_mask & (1 << i)) && \
+                    (_gpio_instances[0].callback_reg_mask & (1 << i)))
+                _gpio_instances[0].callback[i]();
+			break;
+		}
+	}
+	NVIC_ClearPendingIRQ(GPIO0_IRQn);
+}
+
+/**
+ * \internal GPIO port1 isr handler.
+ *
+ * This function will enter interrupt.
+ *
+ */
+static void gpio_port1_isr_handler(void)
+{
+	uint32_t flag = _gpio_instances[1].hw->INTSTATUSCLEAR.reg;
+
+	for (uint8_t i = 0; i < 16; i++){
+		/* For AON wakeup pin clear interrupt */
+		if (flag & ((1<<15) | (1<<14) | (1<<13))) {
+			aon_handle_ext_wakeup_isr();
+		}
+
+		if (flag & (1 << i)) {
+			/* Clear interrupt flag */
+			_gpio_instances[1].hw->INTSTATUSCLEAR.reg = (1 << i);
+			if ((_gpio_instances[1].callback_enable_mask & (1 << i)) && \
+			(_gpio_instances[1].callback_reg_mask & (1 << i))) {
+				_gpio_instances[1].callback[i]();
+				break;
+			}
+		}
+	}
+	NVIC_ClearPendingIRQ(GPIO1_IRQn);
+}
+
+/**
+ * \internal GPIO port2 isr handler.
+ *
+ * This function will enter interrupt.
+ *
+ */
+static void gpio_port2_isr_handler(void)
+{
+	uint32_t flag = _gpio_instances[2].hw->INTSTATUSCLEAR.reg;
+
+	for (uint8_t i = 12; i < 16; i++){
+		if (flag & (1 << i)) {
+			/* Clear interrupt flag */
+			_gpio_instances[2].hw->INTSTATUSCLEAR.reg = (1 << i);
+			if ((_gpio_instances[2].callback_enable_mask & (1 << i)) && \
+                    (_gpio_instances[2].callback_reg_mask & (1 << i)))
+                _gpio_instances[2].callback[i]();
+			break;
+		}
+	}
+	NVIC_ClearPendingIRQ(GPIO2_IRQn);
+}
+
+/**
+ * \internal GPIO callback init.
+ *
+ * This function will init GPIO callback.
+ *
+ */
+void gpio_init(void)
+{
+	uint8_t i, j;
+
+	for(i = 0; i < 3; i++) {
+		for(j = 0; j < 16; j++) {
+			_gpio_instances[i].callback[j] = NULL;
+		}
+		_gpio_instances[i].callback_enable_mask = 0;
+		_gpio_instances[i].callback_reg_mask = 0;
+	}
+	_gpio_instances[0].hw = (void *)GPIO0;
+	_gpio_instances[1].hw = (void *)GPIO1;
+	_gpio_instances[2].hw = (void *)GPIO2;
+	system_register_isr(RAM_ISR_TABLE_PORT0_COMB_INDEX, (uint32_t)gpio_port0_isr_handler);
+	system_register_isr(RAM_ISR_TABLE_PORT1_COMB_INDEX, (uint32_t)gpio_port1_isr_handler);
+	system_register_isr(RAM_ISR_TABLE_PORT2_COMB_INDEX, (uint32_t)gpio_port2_isr_handler);
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.h
new file mode 100644
index 0000000000..dbb020b9d2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.h
@@ -0,0 +1,389 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef GPIO_H_INCLUDED
+#define GPIO_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_gpio_group SAM GPIO Driver (GPIO)
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's General Purpose Input/Output
+ * (GPIO) pin functionality, for manual pin state reading and writing.
+ *
+ * The following peripherals are used by this module:
+ *  - GPIO (GPIO Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_gpio_prerequisites
+ *  - \ref asfdoc_samb_gpio_module_overview
+ *  - \ref asfdoc_samb_gpio_special_considerations
+ *  - \ref asfdoc_samb_gpio_extra_info
+ *  - \ref asfdoc_samb_gpio_examples
+ *  - \ref asfdoc_samb_gpio_api_overview
+ *
+ *
+ * \section asfdoc_samb_gpio_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_gpio_module_overview Module Overview
+ *
+ * The device GPIO module provides an interface between the user application
+ * logic and external hardware peripherals, when general pin state manipulation
+ * is required. This driver provides an easy-to-use interface to the physical
+ * pin input samplers and output drivers, so that pins can be read from or
+ * written to for general purpose external hardware control.
+ *
+ * There are the different peripheral functions that are Software selectable
+ * on a per pin basis. This allows for maximum flexibility of mapping desired
+ * interfaces on GPIO pins. MUX1 option allows for any MEGAMUX option to be
+ * assigned to a GPIO.
+ *
+ * An example is to illustrate the available options for pin LP_GPIO_3, depending
+ * on the pin-MUX option selected:
+ * - MUX0: the pin will function as bit 3 of the GPIO bus and is controlled by
+ *         the GPIO controller in the ARM subsystem
+ * - MUX1: any option from the MEGAMUX table can be selected, for example it
+ *         can be a quad_dec, pwm, or any of the other functions listed in the
+ *         MEGAMUX table
+ * - MUX2: the pin will function as UART1 TXD; this can be also achieved with
+ *         the MUX1 option via MEGAMUX, but the MUX2 option allows a shortcut
+ *         for the recommended pinout
+ * - MUX3: this option is not used and thus defaults to the GPIO option (same
+ *         as MUX0)
+ * - MUX4: the pin will function as SPI1 MOSI (this option is not available
+ *         through MEGAMUX)
+ * - MUX5: the pin will function as SPI0 MOSI (this option is not available
+ *         through MEGAMUX)
+ * - MUX6: the pin will function as SPI FLASH SCK (this option is not available
+ *         through MEGAMUX)
+ * - MUX7: the pin will function as bit 3 of the test output bus, giving access
+ *         to various debug signals
+ *
+ * \section asfdoc_samb_gpio_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_samb_gpio_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_gpio_extra. This includes:
+ *  - \ref asfdoc_samb_gpio_extra_acronyms
+ *  - \ref asfdoc_samb_gpio_extra_dependencies
+ *  - \ref asfdoc_samb_gpio_extra_errata
+ *  - \ref asfdoc_samb_gpio_extra_history
+ *
+ *
+ * \section asfdoc_samb_gpio_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_gpio_exqsg.
+ *
+ *
+ * \section asfdoc_samb_gpio_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system_sam_b.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  \brief GPIO pin direction configuration enum.
+ *
+ *  Enum for the possible pin direction settings of the gpio pin configuration
+ *  structure, to indicate the direction the pin should use.
+ */
+enum gpio_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read. */
+	GPIO_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set. */
+	GPIO_PIN_DIR_OUTPUT,
+};
+
+/**
+ *  \brief GPIO pin input pull configuration enum.
+ *
+ *  Enum for the possible pin pull settings of the GPIO pin configuration
+ *  structure, to indicate the type of logic level pull the pin should use.
+ */
+enum gpio_pin_pull {
+	/** No logical pull should be applied to the pin */
+	GPIO_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	GPIO_PIN_PULL_UP ,
+	/** Pin should be pulled down when idle */
+	GPIO_PIN_PULL_DOWN,
+};
+
+/**
+ *  \brief GPIO pinmux selection enum.
+ *
+ *  Enum for the pinmux settings of the GPIO pin configuration.
+ */
+enum gpio_pinmux_sel {
+	/** PINMUX selection 0 */
+	GPIO_PINMUX_SEL_0 = 0,
+	/** PINMUX selection 1 */
+	GPIO_PINMUX_SEL_1,
+	/** PINMUX selection 2 */
+	GPIO_PINMUX_SEL_2,
+	/** PINMUX selection 3 */
+	GPIO_PINMUX_SEL_3,
+	/** PINMUX selection 4 */
+	GPIO_PINMUX_SEL_4,
+	/** PINMUX selection 5 */
+	GPIO_PINMUX_SEL_5,
+	/** PINMUX selection 6 */
+	GPIO_PINMUX_SEL_6,
+	/** PINMUX selection 7 */
+	GPIO_PINMUX_SEL_7,
+};
+
+/**
+ * \brief GPIO module instance
+ *
+ * Forward Declaration for the device instance.
+ */
+struct gpio_module;
+
+/**
+ * \brief GPIO callback type
+ *
+ * Type of the callback functions.
+ */
+typedef void (*gpio_callback_t)(void);
+
+/**
+ * \brief GPIO Callback enum
+ *
+ * Callbacks for the GPIO driver.
+ */
+enum gpio_callback {
+	/** Callback for low level */
+	GPIO_CALLBACK_LOW,
+	/** Callback for high level */
+	GPIO_CALLBACK_HIGH,
+	/** Callback for rising edge */
+	GPIO_CALLBACK_RISING,
+	/** Callback for falling edge */
+	GPIO_CALLBACK_FALLING,
+	/** Number of available callbacks */
+	GPIO_CALLBACK_N,
+};
+
+/**
+ *  \brief GPIO pin configuration structure.
+ *
+ *  Configuration structure for a GPIO pin instance. This structure should be
+ *  initialized by the \ref GPIO_get_config_defaults() function before being
+ *  modified by the user application.
+ */
+struct gpio_config {
+	/** GPIO buffer input/output direction */
+	enum gpio_pin_dir  direction;
+
+	/** GPIO pull-up/pull-down for input pins */
+	enum gpio_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled
+	 */
+	bool powersave;
+	/** Enable AON_GPIOs to wakeup MCU from ULP mode 
+	 *
+	 *  \note Only AON_GPIO_0, AON_GPIO_1, and AON_GPIO_2 could enable this feature
+	 */
+	bool aon_wakeup;
+};
+
+/**
+ * \brief GPIO driver software device instance structure.
+ *
+ * GPIO driver software instance structure, used to retain software
+ * state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct gpio_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to the hardware instance */
+	Gpio *hw;
+	/** Array to store callback function pointers in */
+	gpio_callback_t callback[16];
+	/** Bit mask for callbacks registered */
+	uint16_t callback_reg_mask;
+	/** Bit mask for callbacks enabled */
+	uint16_t callback_enable_mask;
+#endif
+};
+
+/** \name Configuration and initialization
+ * @{
+ */
+
+void gpio_get_config_defaults(struct gpio_config *const config);
+enum status_code gpio_pin_set_config(const uint8_t gpio_pin,
+		const struct gpio_config *config);
+
+/** @} */
+
+/** \name State reading/writing (logical pin orientated)
+ * @{
+ */
+
+bool gpio_pin_get_input_level(const uint8_t gpio_pin);
+bool gpio_pin_get_output_level(const uint8_t gpio_pin);
+void gpio_pin_set_output_level(const uint8_t gpio_pin, const bool level);
+void gpio_pin_toggle_output_level(const uint8_t gpio_pin);
+/** @} */
+
+/** \name PINMUX selection configuration
+ * @{
+ */
+void gpio_pinmux_cofiguration(const uint8_t gpio_pin, uint16_t pinmux_sel);
+/** @}*/
+
+/** \name GPIO callback config
+ * @{
+ */
+void gpio_register_callback(uint8_t gpio_pin, gpio_callback_t callback_func,
+				enum gpio_callback callback_type);
+void gpio_unregister_callback(uint8_t gpio_pin,
+				enum gpio_callback callback_type);
+void gpio_enable_callback(uint8_t gpio_pin);
+void gpio_disable_callback(uint8_t gpio_pin);
+void gpio_init(void);
+/** @}*/
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \page asfdoc_samb_gpio_extra Extra Information for GPIO Driver
+ *
+ * \section asfdoc_samb_gpio_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_samb_gpio_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_gpio_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_gpio_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_gpio_exqsg Examples for GPIO Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_gpio_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_gpio_basic_use_case
+ *
+ * \page asfdoc_samb_gpio_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>A</td>
+ *		<td>09/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_common.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_common.h
new file mode 100644
index 0000000000..fb40afda69
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_common.h
@@ -0,0 +1,488 @@
+/**
+ * \file
+ *
+ * \brief I2C Common Driver for SAMB
+ *
+ * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef I2C_COMMON_H_INCLUDED
+#define I2C_COMMON_H_INCLUDED
+
+#include <compiler.h>
+#include <system_sam_b.h>
+#include <gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \if (I2C_MASTER_MODE && I2C_SLAVE_MODE)
+ *   \defgroup asfdoc_samb_i2c_group SAM I2C Driver (I2C)
+ * \elseif I2C_MASTER_MODE
+ *   \defgroup asfdoc_samb_i2c_group SAM I2C Master Mode Driver (I2C)
+ * \elseif I2C_SLAVE_MODE
+ *   \defgroup asfdoc_samb_i2c_group SAM I2C Slave Mode Driver (I2C)
+ * \endif
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the configuration
+ * and management of the device's I<SUP>2</SUP>C module, for the transfer
+ * of data via an I<SUP>2</SUP>C bus. The following driver API modes are covered
+ * by this manual:
+ *
+ * \if I2C_MASTER_MODE
+ * - Master Mode Polled APIs
+ * \endif
+ * \if I2C_MASTER_CALLBACK_MODE
+ * - Master Mode Callback APIs
+ * \endif
+ * \if I2C_SLAVE_MODE
+ * - Slave Mode Polled APIs
+ * \endif
+ * \if I2C_SLAVE_CALLBACK_MODE
+ * - Slave Mode Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - Serial Communication Interface
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_samb_i2c_prerequisites
+ * - \ref asfdoc_samb_i2c_overview
+ * - \ref asfdoc_samb_i2c_special_considerations
+ * - \ref asfdoc_samb_i2c_extra
+ * - \ref asfdoc_samb_i2c_examples
+ * - \ref asfdoc_samb_i2c_api_overview
+ *
+ * \section asfdoc_samb_i2c_prerequisites Prerequisites
+ * There are no prerequisites.
+ *
+ * \section asfdoc_samb_i2c_overview Module Overview
+ *
+ * The outline of this section is as follows:
+ * - \ref asfdoc_samb_i2c_functional_desc
+ * - \ref asfdoc_samb_i2c_bus_topology
+ * - \ref asfdoc_samb_i2c_transactions
+ * - \ref asfdoc_samb_i2c_multi_master
+ * - \ref asfdoc_samb_i2c_bus_states
+ *
+ * \subsection asfdoc_samb_i2c_functional_desc Functional Description
+ * The I<SUP>2</SUP>C provides a simple two-wire bidirectional bus consisting of a
+ * wired-AND type serial clock line (SCL) and a wired-AND type serial data line
+ * (SDA).
+ *
+ * The I<SUP>2</SUP>C bus provides a simple, but efficient method of interconnecting
+ * multiple master and slave devices. An arbitration mechanism is provided for
+ * resolving bus ownership between masters, as only one master device may own
+ * the bus at any given time. The arbitration mechanism relies on the wired-AND
+ * connections to avoid bus drivers short-circuiting.
+ *
+ * A unique address is assigned to all slave devices connected to the bus. A
+ * device can contain both master and slave logic, and can emulate multiple
+ * slave devices by responding to more than one address.
+ *
+ * \subsection asfdoc_samb_i2c_bus_topology Bus Topology
+ * The I<SUP>2</SUP>C bus topology is illustrated in
+ * \ref asfdoc_samb_i2c_bus_topology_figure "the figure below". The pull-up
+ * resistors (Rs) will provide a high level on the bus lines when none of the
+ * I<SUP>2</SUP>C devices are driving the bus. These are optional, and can be
+ * replaced with a constant current source.
+ *
+ * \anchor asfdoc_samb_i2c_bus_topology_figure
+ * \image html bus_topology.svg "I2C Bus Topology" Width=100%
+ *
+ * \subsection asfdoc_samb_i2c_transactions Transactions
+ * The I<SUP>2</SUP>C standard defines three fundamental transaction formats:
+ * - Master Write
+ *   - The master transmits data packets to the slave after addressing it
+ * - Master Read
+ *   - The slave transmits data packets to the master after being addressed
+ * - Combined Read/Write
+ *   - A combined transaction consists of several write and read transactions
+ *
+ * A data transfer starts with the master issuing a \b Start condition on the
+ * bus, followed by the address of the slave together with a bit to indicate
+ * whether the master wants to read from or write to the slave.
+ * The addressed slave must respond to this by sending an \b ACK back to the
+ * master.
+ *
+ * After this, data packets are sent from the master or slave, according to the
+ * read/write bit. Each packet must be acknowledged (ACK) or not
+ * acknowledged (NACK) by the receiver.
+ *
+ * If a slave responds with a NACK, the master must assume that the slave
+ * cannot receive any more data and cancel the write operation.
+ *
+ * The master completes a transaction by issuing a \b Stop condition.
+ *
+ * A master can issue multiple \b Start conditions during a transaction; this
+ * is then called a \b Repeated \b Start condition.
+ *
+ * \subsubsection asfdoc_samb_i2c_address_packets Address Packets
+ * The slave address consists of seven bits. The 8<SUP>th</SUP> bit in the transfer
+ * determines the data direction (read or write). An address packet always
+ * succeeds a \b Start or \b Repeated \b Start condition. The 8<SUP>th</SUP> bit is handled
+ * in the driver, and the user will only have to provide the 7-bit address.
+ *
+ * \subsubsection asfdoc_samb_i2c_data_packets Data Packets
+ * Data packets are nine bits long, consisting of one 8-bit data byte, and an
+ * acknowledgement bit. Data packets follow either an address packet or another
+ * data packet on the bus.
+ *
+ * \subsubsection asfdoc_samb_i2c_trans_examples Transaction Examples
+ * The gray bits in the following examples are sent from master to slave, and
+ * the white bits are sent from slave to master.
+ * Example of a read transaction is shown in
+ * \ref asfdoc_samb_i2c_trans_examples_i2c_read "the figure below". Here, the
+ * master first issues a \b Start condition and gets ownership of the bus. An
+ * address packet with the direction flag set to read is then sent and
+ * acknowledged by the slave. Then the slave sends one data packet which is
+ * acknowledged by the master. The slave sends another packet, which is not
+ * acknowledged by the master and indicates that the master will terminate the
+ * transaction. In the end, the transaction is terminated by the master issuing
+ * a \b Stop condition.
+ *
+ * \anchor asfdoc_samb_i2c_trans_examples_i2c_read
+ * \image html i2c_read.svg "I2C Packet Read" Width=100%
+ *
+ * Example of a write transaction is shown in
+ * \ref asfdoc_samb_i2c_trans_examples_i2c_write "the figure below". Here, the
+ * master first issues a \b Start condition and gets ownership of the bus. An
+ * address packet with the dir flag set to write is then sent and acknowledged
+ * by the slave. Then the master sends two data packets, each acknowledged by
+ * the slave. In the end, the transaction is terminated by the master issuing
+ * a \b Stop condition.
+ *
+ * \anchor asfdoc_samb_i2c_trans_examples_i2c_write
+ * \image html i2c_write.svg "I2C Packet Write" Width=100%
+ *
+ * \subsubsection asfdoc_samb_i2c_repeated_start Repeated Start
+ * To issue a \b Repeated \b Start, the functions postfixed \c _no_stop must be
+ * used.
+ * These functions will not send a \b Stop condition when the transfer is done,
+ * thus the next transfer will start with a \b Repeated \b Start. To end the
+ * transaction, the functions without the \c _no_stop postfix must be used
+ * for the last read/write.
+ *
+ * \subsection asfdoc_samb_i2c_multi_master Multi Master
+ * In a multi master environment, arbitration of the bus is important, as only
+ * one master can own the bus at any point.
+ *
+ * \subsubsection asfdoc_samb_i2c_arbitration Arbitration
+ *
+ * \par Clock stretching
+ * The serial clock line is always driven by a master device. However, all
+ * devices connected to the bus are allowed stretch the low period of the clock
+ * to slow down the overall clock frequency or to insert wait states while
+ * processing data.
+ * Both master and slave can randomly stretch the clock, which will force the
+ * other device into a wait-state until the clock line goes high again.
+ *
+ * \par Arbitration on the data line
+ * If two masters start transmitting at the same time, they will both transmit
+ * until one master detects that the other master is pulling the data line low.
+ * When this is detected, the master not pulling the line low, will stop the
+ * transmission and wait until the bus is idle.
+ * As it is the master trying to contact the slave with the lowest address that
+ * will get the bus ownership, this will create an arbitration scheme always
+ * prioritizing the slaves with the lowest address in case of a bus collision.
+ *
+ * \subsubsection asfdoc_samb_i2c_clock_sync Clock Synchronization
+ * In situations where more than one master is trying to control the bus clock
+ * line at the same time, a clock synchronization algorithm based on the same
+ * principles used for clock stretching is necessary.
+ *
+ *
+ * \subsection asfdoc_samb_i2c_bus_states Bus States
+ * As the I<SUP>2</SUP>C bus is limited to one transaction at the time,
+ * a master that wants to perform a bus transaction must wait until the bus is
+ * free.
+ * Because of this, it is necessary for all masters in a multi-master system to
+ * know the current status of the bus to be able to avoid conflicts and to
+ * ensure data integrity.
+ * \li \b IDLE No activity on the bus (between a \b Stop and a new \b Start
+ * condition)
+ * \li \b BUSY If another master is driving the bus
+ *
+ * \section asfdoc_samb_i2c_special_considerations Special Considerations
+ * There are no special considerations related to this driver.
+ *
+ *
+ * \section asfdoc_samb_i2c_extra Extra Information
+ * For extra information, see \ref asfdoc_samb_i2c_extra_info_page.
+ * This includes:
+ *  - \ref asfdoc_samb_i2c_acronyms
+ *  - \ref asfdoc_samb_i2c_extra_dependencies
+ *  - \ref asfdoc_samb_i2c_extra_errata
+ *  - \ref asfdoc_samb_i2c_extra_history
+ *
+ * \section asfdoc_samb_i2c_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_i2c_exqsg.
+ *
+ * \section asfdoc_samb_i2c_api_overview API Overview
+ * @{
+ */
+
+
+/** \brief Transfer direction
+ *
+ * For master: transfer direction or setting direction bit in address.
+ * For slave: direction of request from master.
+ */
+enum i2c_transfer_direction {
+	/** Master write operation is in progress */
+	I2C_TRANSFER_WRITE = 0,
+	/** Master read operation is in progress */
+	I2C_TRANSFER_READ  = 1,
+};
+
+/**
+ * \brief I2C module clock input 
+ *
+ * I2C module clock.
+ *
+ */
+enum i2c_clock_input {
+	/** source from clock input 0: 26MHz */
+	I2C_CLK_INPUT_0 = 0,
+	/** source from clock input 1: 13MHz */
+	I2C_CLK_INPUT_1,
+	/** source from clock input 2: 6.5MHz */
+	I2C_CLK_INPUT_2,
+	/** source from clock input 3: 3MHz */
+	I2C_CLK_INPUT_3,
+};
+
+/**
+ * \brief Wait for idle
+ *
+ * Wait for hardware module to sync
+ *
+ * \param[in]  i2c_module  Pointer to software module structure
+ */
+static inline void i2c_wait_for_idle(I2c *const i2c_module)
+{
+	while (i2c_module->I2C_STATUS.bit.I2C_ACTIVE) {
+		/* Wait for I2C module to sync. */
+	}
+}
+
+/**
+ * \brief Enable driver instance
+ *
+ * This function enable driver instance
+ *
+ * \param[in,out] module Pointer to the driver instance to enable
+ *
+ */
+static inline void i2c_enable(I2c *const i2c_module)
+{
+	/* Wait for module to sync. */
+	i2c_wait_for_idle(i2c_module);
+	/* Enable module. */
+	i2c_module->I2C_MODULE_ENABLE.reg = (1 << I2C_MODULE_ENABLE_ENABLE_Pos);
+}
+
+/**
+ * \brief Disable driver instance
+ *
+ * This function disable driver instance
+ *
+ * \param[in,out] i2c_module Pointer to the driver instance to disable
+ *
+ */
+static inline void i2c_disable(I2c *const i2c_module)
+{
+	i2c_wait_for_idle(i2c_module);
+	i2c_module->I2C_MODULE_ENABLE.reg = 0;
+}
+
+/**
+ * \brief Flush the contents of both the Tx and Rx FIFOs
+ *
+ * This function flushes the contents of both the Tx and Rx FIFOs.
+ *
+ * \param[in,out] i2c_module Pointer to the driver instance
+ *
+ */
+static inline void i2c_slave_flush_fifo(I2c *const i2c_module)
+{
+	i2c_wait_for_idle(i2c_module);
+	i2c_module->I2C_FLUSH.reg = 1;
+}
+
+/**
+ * \brief Enable or Disable slave rx interrupt
+ *
+ * This function enables or disables slave rx interrupt.
+ *
+ * \param[in,out] i2c_module Pointer to the driver
+ * \param[in]     enable     Enable or Disable
+ *
+ */
+static inline void i2c_slave_rx_interrupt(I2c *const i2c_module, bool enable)
+{
+	if (enable) {
+		i2c_module->RX_INTERRUPT_MASK.bit.RX_FIFO_NOT_EMPTY_MASK = 1;
+	} else {
+		i2c_module->RX_INTERRUPT_MASK.bit.RX_FIFO_NOT_EMPTY_MASK = 0;
+	}
+}
+
+/**
+ * \brief Enable or Disable slave tx interrupt
+ *
+ * This function enables or disables slave tx interrupt.
+ *
+ * \param[in,out] i2c_module Pointer to the driver
+ * \param[in]     enable     Enable or Disable
+ *
+ */
+static inline void i2c_slave_tx_interrupt(I2c *const i2c_module, bool enable)
+{
+	if (enable) {
+		i2c_module->TX_INTERRUPT_MASK.bit.TX_FIFO_NOT_FULL_MASK = 1;
+		i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 1;
+	} else {
+		i2c_module->TX_INTERRUPT_MASK.bit.TX_FIFO_NOT_FULL_MASK = 0;
+		i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
+	}
+}
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_samb_i2c_extra_info_page  Extra Information for I2C Driver
+ *
+ * \section asfdoc_samb_i2c_acronyms Acronyms
+ * \ref asfdoc_samb_i2c_acronyms_table "Below" is a table listing the acronyms
+ * used in this module, along with their intended meanings.
+ *
+ * \anchor asfdoc_samb_i2c_acronyms_table
+ * <table>
+ *  <caption>Acronyms</caption>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>SDA</td>
+ *		<td>Serial Data Line</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SCL</td>
+ *		<td>Serial Clock Line</td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_samb_i2c_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_i2c_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ * \section asfdoc_samb_i2c_extra_history Module History
+ * \ref asfdoc_samb_i2c_extra_history_table "Below" is an overview of the
+ * module history, detailing enhancements and fixes made to the module since
+ * its first release. The current version of this corresponds to the newest
+ * version listed in
+ * \ref asfdoc_samb_i2c_extra_history_table "the table below".
+ *
+ * \anchor asfdoc_samb_i2c_extra_history_table
+ * <table>
+ *  <caption>Module History</caption>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_i2c_exqsg Examples for I2C Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_i2c_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * \if I2C_MASTER_MODE
+ * - \subpage asfdoc_samb_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case"
+ * \endif
+ * \if I2C_MASTER_CALLBACK_MODE
+ * - \subpage asfdoc_samb_i2c_master_callback_use_case "Quick Start Guide for the I2C Master module - Callback Use Case"
+ * \endif
+ * \if I2C_SLAVE_MODE
+ * - \subpage asfdoc_samb_i2c_slave_basic_use_case "Quick Start Guide for the I2C Slave module - Basic Use Case"
+ * \endif
+ * \if I2C_SLAVE_CALLBACK_MODE
+ * - \subpage asfdoc_samb_i2c_slave_callback_use_case "Quick Start Guide for the I2C Slave module - Callback Use Case"
+ * \endif
+ *
+ * \page asfdoc_samb_i2c_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>A</td>
+ *		<td>09/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* I2C_COMMON_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.c
new file mode 100644
index 0000000000..1f8d59dd05
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.c
@@ -0,0 +1,594 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Driver for SAMB
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_master.h"
+#if I2C_MASTER_CALLBACK_MODE == true
+#  include "i2c_master_interrupt.h"
+#endif
+
+/**
+ * \brief Gets the I<SUP>2</SUP>C master default configurations
+ *
+ * Use to initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Baudrate 100KHz
+ * - Clock sourc I2C_CLK_INPUT_3
+ * - Clock divider = 0x10
+ * - Pinmux pad0 PINMUX_LP_GPIO_8_MUX2_I2C0_SDA
+ * - Pinmux pad1 PINMUX_LP_GPIO_9_MUX2_I2C0_SCK
+ *
+ * \param[out] config  Pointer to configuration structure to be initiated
+ */
+void i2c_master_get_config_defaults(
+		struct i2c_master_config *const config)
+{
+	/* Sanity check */
+	Assert(config);
+	
+	config->clock_source    = I2C_CLK_INPUT_3;
+	config->clock_divider   = 0x10;
+	config->pin_number_pad0 = PIN_LP_GPIO_8;
+	config->pin_number_pad1 = PIN_LP_GPIO_9;
+	config->pinmux_sel_pad0 = MUX_LP_GPIO_8_I2C0_SDA;
+	config->pinmux_sel_pad1 = MUX_LP_GPIO_9_I2C0_SCL;
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Sets configurations to module
+ *
+ * \param[out] module  Pointer to software module structure
+ * \param[in]  config  Configuration structure with configurations to set
+ *
+ */
+static void _i2c_master_set_config(
+		struct i2c_master_module *const module,
+		const struct i2c_master_config *const config)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+
+	I2c *const i2c_module = (module->hw);
+
+	/* Set the pinmux for this i2c module. */
+	gpio_pinmux_cofiguration(config->pin_number_pad0, (uint16_t)(config->pinmux_sel_pad0));
+	gpio_pinmux_cofiguration(config->pin_number_pad1, (uint16_t)(config->pinmux_sel_pad1));
+	/* Set clock. */
+	i2c_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
+	i2c_module->I2C_CLK_DIVIDER.reg = I2C_CLK_DIVIDER_I2C_DIVIDE_RATIO(config->clock_divider);
+	/* Enable master mode. */
+	i2c_module->I2C_MASTER_MODE.reg = I2C_MASTER_MODE_MASTER_ENABLE_1;
+}
+#endif /* __DOXYGEN__ */
+
+/**
+ * \brief Initializes the requested I<SUP>2</SUP>C hardware module
+ *
+ * Initializes the I<SUP>2</SUP>C master device requested and sets the provided
+ * software module struct. Run this function before any further use of
+ * the driver.
+ *
+ * \param[out] module  Pointer to software module struct
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK                        Module initiated correctly
+ * \retval STATUS_ERR_INVALID_ARG           Invalid argument in module or config structure.
+ * \retval STATUS_ERR_ALREADY_INITIALIZED   If the Pinmux is not a valid one for I2C signals.
+ *
+ */
+enum status_code i2c_master_init(
+		struct i2c_master_module *const module,
+		I2c *const hw,
+		const struct i2c_master_config *const config)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+	
+	module->hw = hw;
+
+	/* Sanity check arguments. */
+	if ((module == NULL) || (config == NULL))
+		return STATUS_ERR_INVALID_ARG;
+
+	i2c_disable(module->hw);
+	if (module->hw == I2C0) {
+		system_peripheral_reset(PERIPHERAL_I2C0_CORE);
+	} else if (module->hw == I2C1) {
+		system_peripheral_reset(PERIPHERAL_I2C1_CORE);
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Initialize values in module. */
+	module->registered_callback = 0;
+	module->enabled_callback    = 0;
+	module->buffer_length       = 0;
+	module->buffer_remaining    = 0;
+	module->status              = STATUS_OK;
+	module->buffer              = NULL;
+
+	_i2c_instances = (void*)module;
+	if (module->hw == I2C0) {
+		system_register_isr(RAM_ISR_TABLE_I2CRX0_INDEX, (uint32_t)_i2c_master_isr_handler);
+		system_register_isr(RAM_ISR_TABLE_I2CTX0_INDEX, (uint32_t)_i2c_master_isr_handler);
+		NVIC_EnableIRQ(I2C0_RX_IRQn);
+		NVIC_EnableIRQ(I2C0_TX_IRQn);
+	} else if (module->hw == I2C1) {
+		system_register_isr(RAM_ISR_TABLE_I2CRX1_INDEX, (uint32_t)_i2c_master_isr_handler);
+		system_register_isr(RAM_ISR_TABLE_I2CTX1_INDEX, (uint32_t)_i2c_master_isr_handler);
+		NVIC_EnableIRQ(I2C1_RX_IRQn);
+		NVIC_EnableIRQ(I2C1_TX_IRQn);
+	}
+#endif
+
+	/* Set config and return status. */
+	_i2c_master_set_config(module, config);
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Starts blocking read operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+static enum status_code _i2c_master_read_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+	
+	uint16_t counter = 0;
+	uint32_t status  = 0;
+	I2c *const i2c_module    = (module->hw);
+	uint16_t length = packet->data_length;
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	i2c_wait_for_idle(i2c_module);
+
+	/* Flush the FIFO */
+	i2c_module->I2C_FLUSH.reg = 1;
+
+	/* Enable I2C on bus (start condition). */
+	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+	/* Address I2C slave in case of Master mode enabled. */
+	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
+			(packet->address << 1) | I2C_TRANSFER_READ;
+
+	/* Now check whether the core has sent the data out and free the bus. */
+	while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY)) {
+		status = i2c_module->TRANSMIT_STATUS.reg;
+	}
+
+	do {
+		/* Send stop condition. */
+		if ((!module->no_stop) && (counter == (length - 1))) {
+			i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+		}
+
+		status = i2c_module->RECEIVE_STATUS.reg;
+		if (status & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+			packet->data[counter++] = i2c_module->RECEIVE_DATA.reg;
+	} while (counter < length);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Reads data packet from slave
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus and sends a stop condition when finished.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_INVALID_ARG       Invalid argument in module or config strucuture
+ *                                      specified timeout period
+ * \retval STATUS_BUSY                  If module has a pending request.
+ */
+enum status_code i2c_master_read_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	if((module == NULL) || (packet == NULL))
+		return STATUS_ERR_INVALID_ARG;
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->no_stop = false;
+
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Reads data packet from slave without sending a stop condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus without sending a stop condition when done, thus retaining ownership of
+ * the bus when done. To end the transaction, a
+ * \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_INVALID_ARG       Invalid argument in module or config strucuture
+ *                                      specified timeout period
+ * \retval STATUS_BUSY                  If module has a pending request.
+ */
+enum status_code i2c_master_read_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	if((module == NULL) || (packet == NULL))
+		return STATUS_ERR_INVALID_ARG;
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->no_stop = true;
+
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts blocking write operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    The packet was write successfully
+ */
+static enum status_code _i2c_master_write_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+	
+	I2c *const i2c_module = (module->hw);
+	uint16_t counter = 0;
+	uint32_t status  = 0;
+
+	uint16_t length = packet->data_length;
+
+	i2c_wait_for_idle(i2c_module);
+
+	/* Flush the FIFO */
+	i2c_module->I2C_FLUSH.reg = 1;
+
+	/* Enable I2C on bus (start condition) */
+	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+
+	/* Address I2C slave in case of Master mode enabled */
+	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 | 
+			((packet->address) << 1) | I2C_TRANSFER_WRITE;
+	do {
+		status = i2c_module->TRANSMIT_STATUS.reg;
+		if (status & I2C_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_Msk) {
+			i2c_module->TRANSMIT_DATA.reg = packet->data[counter++];
+		}
+	} while (counter < length); 
+
+	/* Now check whether the core has sent the data out and free the bus */
+	while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY)) {
+			status = i2c_module->TRANSMIT_STATUS.reg;
+	}
+
+	/* Send stop condition */
+	if (!module->no_stop) {
+		i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Writes data packet to slave
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * and sends a stop condition when finished.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    The packet was written successfully
+ * \retval STATUS_ERR_INVALID_ARG       Invalid argument in module or packet structure
+ *                                      specified timeout period
+ * \retval STATUS_BUSY                  If module has a pending request.
+ */
+enum status_code i2c_master_write_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	if ((module == NULL) || (packet == NULL)) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->no_stop = false;
+
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Writes data packet to slave without sending a stop condition when done
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * without sending a stop condition, thus retaining ownership of the bus when
+ * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition or sending a
+ * stop with the \ref i2c_master_send_stop function must be performed.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    The packet was written successfully
+ * \retval STATUS_ERR_INVALID_ARG       Invalid argument in module or config structure
+ *                                      specified timeout period
+ * \retval STATUS_BUSY                  If module has a pending request.
+ */
+enum status_code i2c_master_write_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	if((module == NULL) || (packet == NULL)) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->no_stop = true;
+
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Sends stop condition on bus
+ *
+ * Sends a stop condition on bus.
+ *
+ * \note This function can only be used after the
+ *       \ref i2c_master_write_packet_wait_no_stop function. If a stop condition
+ *       is to be sent after a read, the \ref i2c_master_read_packet_wait
+ *       function must be used.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void i2c_master_send_stop(struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	
+	I2c *const i2c_module = (module->hw);
+
+	/* Send stop command */
+	i2c_wait_for_idle(i2c_module);
+
+	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+}
+
+/**
+ * \brief Sends start condition on bus
+ *
+ * Sends a start condition on bus.
+ *
+ * \note This function can only be used after the
+ * \ref i2c_master_write_packet_wait_no_stop function. If a stop condition
+ * is to be sent after a read, the \ref i2c_master_read_packet_wait
+ * function must be used.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void i2c_master_send_start(struct i2c_master_module *const module)
+{
+	I2c *const i2c_module = (module->hw);
+
+	i2c_wait_for_idle(i2c_module);
+
+	/* Send start command */
+	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+}
+
+/**
+ * \brief Reads one byte data from slave
+ *
+ * \param[in,out]  module  Pointer to software module struct
+ * \param[out]     byte    Read one byte data to slave
+ *
+ * \return Status of reading byte.
+ * \retval STATUS_OK                    The packet was read successfully
+ */
+enum status_code i2c_master_read_byte(
+		struct i2c_master_module *const module,
+		uint8_t *byte)
+{
+	I2c *const i2c_module = (module->hw);
+
+	/* Read a byte from slave. */
+	i2c_wait_for_idle(i2c_module);
+
+	*byte = i2c_module->RECEIVE_DATA.bit.RX_BYTE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Write Address & command to slave
+ *
+ * \param[in,out]  module  Pointer to software module struct
+ * \param[in]      byte    Address of slave
+ * \param[in]      byte    command 0 - Write, 1 - Read
+ *
+ * \return Status of writing byte.
+ * \retval STATUS_OK   The Address and command was written successfully
+ */
+enum status_code i2c_master_write_address(
+		struct i2c_master_module *const module,
+		uint8_t address,
+		uint8_t command)
+{
+	I2c *const i2c_module = (module->hw);
+
+	/* Write byte to slave. */
+	i2c_wait_for_idle(i2c_module);
+
+	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 | 
+			(address << 1) | command;
+
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Write one byte data to slave
+ *
+ * \param[in,out]  module  Pointer to software module struct
+ * \param[in]      byte    Send one byte data to slave
+ *
+ * \return Status of writing byte.
+ * \retval STATUS_OK   One byte was written successfully
+ */
+enum status_code i2c_master_write_byte(
+		struct i2c_master_module *const module,
+		uint8_t byte)
+{
+	I2c *const i2c_module = (module->hw);
+
+	/* Write byte to slave. */
+	i2c_wait_for_idle(i2c_module);
+
+	i2c_module->TRANSMIT_DATA.reg = (uint16_t)I2C_TRANSMIT_DATA_TX_DATA(byte);
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.h
new file mode 100644
index 0000000000..223da345e0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.h
@@ -0,0 +1,244 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Driver for SAMB
+ *
+ * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2C_MASTER_H_INCLUDED
+#define I2C_MASTER_H_INCLUDED
+
+#include <compiler.h>
+#include "i2c_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_samb_i2c_group
+ *
+ * @{
+ */
+
+
+/**
+ * \brief I<SUP>2</SUP>C master packet for read/write
+ *
+ * Structure to be used when transferring I<SUP>2</SUP>C master packets.
+ */
+struct i2c_master_packet {
+	/** Address to slave device */
+	uint16_t address;
+	/** Length of data array */
+	uint16_t data_length;
+	/** Data array containing all data to be transferred */
+	uint8_t *data;
+};
+
+/** \brief Interrupt flags
+ *
+ * Flags used when reading or setting interrupt flags.
+ */
+enum i2c_master_interrupt_flag {
+	/** Interrupt flag used for write */
+	I2C_MASTER_INTERRUPT_WRITE = 0,
+	/** Interrupt flag used for read */
+	I2C_MASTER_INTERRUPT_READ  = 1,
+};
+
+/**
+ * \brief I<SUP>2</SUP>C frequencies
+ *
+ * Values for I<SUP>2</SUP>C speeds supported by the module. 
+ *
+ */
+enum i2c_master_baud_rate {
+	/** Baud rate at 100KHz (Standard-mode) */
+	I2C_MASTER_BAUD_RATE_100KHZ = 100,
+	/** Baud rate at 400KHz (Fast-mode) */
+	I2C_MASTER_BAUD_RATE_400KHZ = 400,
+};
+
+
+#if I2C_MASTER_CALLBACK_MODE == true
+/**
+ * \brief Callback types
+ *
+ * The available callback types for the I<SUP>2</SUP>C master module.
+ */
+enum i2c_master_callback {
+	/** Callback for packet write complete */
+	I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
+	/** Callback for packet read complete */
+	I2C_MASTER_CALLBACK_READ_COMPLETE  = 1,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_I2C_MASTER_CALLBACK_N             = 2,
+#  endif
+};
+
+#  if !defined(__DOXYGEN__)
+/** Prototype for software module. */
+struct i2c_master_module;
+
+/** Prototype for I2C Callback function */
+typedef void (*i2c_master_callback_t)(
+		struct i2c_master_module *const module);
+#  endif
+#endif
+
+/**
+ * \brief  I<SUP>2</SUP>C driver software device instance structure.
+ *
+ *  I<SUP>2</SUP>C driver software instance structure, used to
+ * retain software state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct i2c_master_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware instance initialized for the struct */
+	I2c *hw;
+	/** Module lock */
+	volatile bool locked;
+	/** If true, stop condition will be sent after a read/write */
+	bool no_stop;
+#  if I2C_MASTER_CALLBACK_MODE == true
+	/** Pointers to callback functions */
+	volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
+	/** Mask for registered callbacks */
+	volatile uint8_t registered_callback;
+	/** Mask for enabled callbacks */
+	volatile uint8_t enabled_callback;
+	/** The total number of bytes to transfer */
+	volatile uint16_t buffer_length;
+	/**
+	 * Counter used for bytes left to send in write and to count number of
+	 * obtained bytes in read
+	 */
+	volatile uint16_t buffer_remaining;
+	/** Data buffer for packet write and read */
+	volatile uint8_t *buffer;
+	/** Save direction of async request. 1 = read, 0 = write */
+	volatile enum i2c_transfer_direction transfer_direction;
+	/** Status for status read back in error callback */
+	volatile enum status_code status;
+#  endif
+#endif
+};
+
+/**
+ * \brief Configuration structure for the I<SUP>2</SUP>C Master device
+ *
+ * This is the configuration structure for the I<SUP>2</SUP>C Master device. It
+ * is used as an argument for \ref i2c_master_init to provide the desired
+ * configurations for the module. The structure should be initialized using the
+ * \ref i2c_master_get_config_defaults .
+ */
+struct i2c_master_config {
+	/** CLOCK INPUT to use as clock source */
+	enum i2c_clock_input clock_source;
+	/** Divide ratio used to generate the sck clock */
+	uint16_t clock_divider;
+	/** PAD0 (SDA) pin number */
+	uint32_t pin_number_pad0;
+	/** PAD0 (SDA) pinmux selection */
+	uint32_t pinmux_sel_pad0;
+	/** PAD1 (SCL) pin numer */
+	uint32_t pin_number_pad1;
+	/** PAD1 (SCL) pinmux selection */
+	uint32_t pinmux_sel_pad1;
+};
+
+void i2c_master_get_config_defaults(
+		struct i2c_master_config *const config);
+
+ enum status_code i2c_master_init(
+		struct i2c_master_module *const module,
+		I2c *const hw,
+		const struct i2c_master_config *const config);
+
+void i2c_master_reset(struct i2c_master_module *const module);
+
+enum status_code i2c_master_write_address(
+		struct i2c_master_module *const module,
+		uint8_t address,
+		uint8_t command);
+
+enum status_code i2c_master_read_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+void i2c_master_send_stop(struct i2c_master_module *const module);
+
+void i2c_master_send_start(struct i2c_master_module *const module);
+
+enum status_code i2c_master_read_byte(
+		struct i2c_master_module *const module,
+		uint8_t *byte);
+
+enum status_code i2c_master_write_byte(
+		struct i2c_master_module *const module,
+		uint8_t byte);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_MASTER_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.c
new file mode 100644
index 0000000000..5a00d942cf
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.c
@@ -0,0 +1,461 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Interrupt Driver for SAMB
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_master_interrupt.h"
+
+void *_i2c_instances;
+
+/**
+ * \internal
+ * Read next data. Used by interrupt handler to get next data byte from slave.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_read(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	I2c *const i2c_module = module->hw;
+
+	/* Find index to save next value in buffer */
+	uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
+
+	module->buffer_remaining--;
+
+	module->buffer[buffer_index] = i2c_module->RECEIVE_DATA.reg;
+}
+
+/**
+ * \internal
+ *
+ * Write next data. Used by interrupt handler to send next data byte to slave.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_write(struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	I2c *const i2c_module = module->hw;
+
+	/* Find index to get next byte in buffer */
+	volatile uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
+
+	module->buffer_remaining--;
+
+	/* Write byte from buffer to slave */
+	i2c_module->TRANSMIT_DATA.reg = module->buffer[buffer_index];
+	
+	if (module->buffer_remaining <= 0) {
+		i2c_module->TX_INTERRUPT_MASK.reg = I2C_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+	}
+}
+
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ *
+ * To enable the callback, the \ref i2c_master_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback       Pointer to the function desired for the
+ *                                specified callback
+ * \param[in]      callback_type  Callback type to register
+ */
+void i2c_master_register_callback(
+		struct i2c_master_module *const module,
+		const i2c_master_callback_t callback,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(callback);
+
+	/* Register callback */
+	module->callbacks[callback_type] = callback;
+
+	/* Set corresponding bit to set callback as registered */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ */
+void i2c_master_unregister_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	
+	/* Register callback */
+	module->callbacks[callback_type] = NULL;
+
+	/* Clear corresponding bit to set callback as unregistered */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal
+ * Starts a read packet operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+static enum status_code _i2c_master_read_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	I2c *const i2c_module = module->hw;
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_READ;
+	module->status             = STATUS_BUSY;
+	
+	i2c_wait_for_idle(i2c_module);
+	/* Flush the FIFO */
+	i2c_module->I2C_FLUSH.reg = 1;
+	/* Enable I2C on bus (start condition) */
+	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+	/* Set address and direction bit. Will send start command on bus */
+	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
+			(packet->address << 1) | module->transfer_direction;
+	/* Enable interrupts */
+	i2c_module->RX_INTERRUPT_MASK.reg = I2C_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+	
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a read packet operation
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus. This is the non-blocking equivalent of \ref i2c_master_read_packet_wait.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_read_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we send STOP */
+	module->no_stop = false;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a read packet operation without sending a STOP condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
+ * sending a stop condition, thus retaining ownership of the bus when done.
+ * To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If reading was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another operation
+ */
+enum status_code i2c_master_read_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we don't send STOP */
+	module->no_stop = true;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+
+/**
+ * \internal Initiates a write packet operation
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK   If writing was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another transfer
+ */
+static enum status_code _i2c_master_write_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	I2c *const i2c_module = module->hw;
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_WRITE;
+	module->status             = STATUS_BUSY;
+
+	/* Enable I2C on bus (start condition) */
+	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+	/* Set address and direction bit, will send start command on bus */
+	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
+			(packet->address << 1) | module->transfer_direction;
+	/* Enable interrupts */
+	i2c_module->TX_INTERRUPT_MASK.reg = I2C_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a write packet operation
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C
+ * bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_write_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with another job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we send STOP at end*/
+	module->no_stop = false;
+	/* Start write operation */
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a write packet operation without sending a STOP condition when done
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * without sending a stop condition, thus retaining ownership of the bus when
+ * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition or sending
+ * a stop with the \ref i2c_master_send_stop function must be performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another
+ */
+enum status_code i2c_master_write_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with another job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Do not send stop condition when done */
+	module->no_stop = true;
+	/* Start write operation */
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * Interrupt handler for I<SUP>2</SUP>C master.
+ */
+void _i2c_master_isr_handler(void)
+{
+	/* Get software module for callback handling */
+	struct i2c_master_module *module =
+			(struct i2c_master_module*)_i2c_instances;
+
+	Assert(module);
+
+	I2c *const i2c_module = module->hw;
+
+	/* Combine callback registered and enabled masks */
+	uint8_t callback_mask = module->enabled_callback &
+			module->registered_callback;
+
+	if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
+		module->buffer_length = module->buffer_remaining;
+	/* Check if buffer write is done */
+	} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+			(module->status == STATUS_BUSY) &&
+			(module->transfer_direction == I2C_TRANSFER_WRITE)) {
+		/* Disable write interrupt flag */
+		i2c_module->TX_INTERRUPT_MASK.reg = 0;
+
+		module->buffer_length = 0;
+		module->status        = STATUS_OK;
+
+		if (!module->no_stop) {
+			/* Send stop condition */
+			i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+		} 
+
+		if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
+			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+		}
+
+	/* Continue buffer write/read */
+	} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
+		if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+			_i2c_master_write(module);
+		} else {
+			_i2c_master_read(module);
+		}
+	}
+
+	/* Check if read buffer transfer is complete */
+	if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+			(module->status == STATUS_BUSY) &&
+			(module->transfer_direction == I2C_TRANSFER_READ)) {
+		/* Disable read interrupt flag */
+		i2c_module->RX_INTERRUPT_MASK.reg = 0;
+
+		module->buffer_length = 0;
+		module->status        = STATUS_OK;
+
+		if (!module->no_stop) {
+			/* Send stop condition */
+			i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+		}
+		
+		if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
+				&& (module->transfer_direction == I2C_TRANSFER_READ)) {
+			module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
+		}
+	}
+	if (module->transfer_direction == I2C_TRANSFER_READ) {
+		if (module->hw == I2C0) {
+			NVIC_ClearPendingIRQ(I2C0_RX_IRQn);
+		} else if (module->hw == I2C1) {
+			NVIC_ClearPendingIRQ(I2C1_RX_IRQn);
+		} 
+	} else {
+		if (module->hw == I2C0) {
+			NVIC_ClearPendingIRQ(I2C0_TX_IRQn);
+		} else if (module->hw == I2C1) {
+			NVIC_ClearPendingIRQ(I2C1_TX_IRQn);
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.h
new file mode 100644
index 0000000000..c814f4c8ad
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.h
@@ -0,0 +1,152 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Interrupt Driver for SAMB
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2C_MASTER_INTERRUPT_H_INCLUDED
+#define I2C_MASTER_INTERRUPT_H_INCLUDED
+
+#include "i2c_master.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_samb_i2c_group
+ * @{
+ *
+ */
+
+/**
+ * \name Callbacks
+ * @{
+ */
+#if !defined(__DOXYGEN__)
+extern void *_i2c_instances;
+void _i2c_master_isr_handler(void);
+#endif
+
+void i2c_master_register_callback(
+		struct i2c_master_module *const module,
+		i2c_master_callback_t callback,
+		enum i2c_master_callback callback_type);
+
+void i2c_master_unregister_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Callback type to enable
+ */
+static inline void i2c_master_enable_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as enabled. */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Callback type to disable
+ */
+static inline void i2c_master_disable_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as disabled. */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/** @} */
+
+
+/**
+ * \name Read and Write, Interrupt-Driven
+ * @{
+ */
+ 
+enum status_code i2c_master_read_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_MASTER_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.c
new file mode 100644
index 0000000000..8e6125a05f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.c
@@ -0,0 +1,280 @@
+/**
+ * \file
+ *
+ * \brief I2C Slave Interrupt Driver for SAMB
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_slave.h"
+#if I2C_SLAVE_CALLBACK_MODE == true
+#include "i2c_slave_interrupt.h"
+#endif
+
+/**
+ * \brief Gets the I<SUP>2</SUP>C master default configurations
+ *
+ * Use to initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - I2C core I2C_CORE1
+ * - Clock sourc I2C_CLK_INPUT_3
+ * - Clock divider = 0x10
+ * - Pinmux pad0 PINMUX_LP_GPIO_8_MUX2_I2C0_SDA
+ * - Pinmux pad1 PINMUX_LP_GPIO_9_MUX2_I2C0_SCK
+ *
+ * \param[out] config  Pointer to configuration structure to be initiated
+ */
+void i2c_slave_get_config_defaults(
+		struct i2c_slave_config *const config)
+{
+	/* Sanity check */
+	Assert(config);
+	
+	config->clock_source    = I2C_CLK_INPUT_3;
+	config->clock_divider   = 0x10;
+	config->pin_number_pad0 = PIN_LP_GPIO_8;
+	config->pin_number_pad1 = PIN_LP_GPIO_9;
+	config->pinmux_sel_pad0 = ((PIN_LP_GPIO_8 << 16) | MUX_LP_GPIO_8_I2C0_SDA);
+	config->pinmux_sel_pad1 = ((PIN_LP_GPIO_9 << 16) | MUX_LP_GPIO_9_I2C0_SCL);
+}
+
+/**
+ * \internal Sets configurations to module
+ *
+ * \param[out] module  Pointer to software module structure
+ * \param[in]  config  Configuration structure with configurations to set
+ *
+ * \return Status of setting configuration.
+ * \retval STATUS_OK                        If module was configured correctly
+ * \retval STATUS_ERR_ALREADY_INITIALIZED   If setting other GCLK generator than
+ *                                          previously set
+ * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE  If given baud rate is not compatible
+ *                                          with set GCLK frequency
+ */
+static enum status_code _i2c_slave_set_config(
+		struct i2c_slave_module *const module,
+		const struct i2c_slave_config *const config)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+
+	enum status_code status = STATUS_OK;
+	I2c *const i2c_module = (module->hw);
+
+	/* Set the pinmux for this i2c module. */
+	gpio_pinmux_cofiguration(config->pin_number_pad0, (uint16_t)(config->pinmux_sel_pad0));
+	gpio_pinmux_cofiguration(config->pin_number_pad1, (uint16_t)(config->pinmux_sel_pad1));
+
+	/* Find and set baudrate. */
+	i2c_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
+	i2c_module->I2C_CLK_DIVIDER.reg = I2C_CLK_DIVIDER_I2C_DIVIDE_RATIO(config->clock_divider);
+	/* I2C slave address */
+	i2c_module->I2C_SLAVE_ADDRESS.reg = I2C_SLAVE_ADDRESS_ADDRESS(config->address);
+	/* I2C slave mode */
+	i2c_module->I2C_MASTER_MODE.reg = I2C_MASTER_MODE_MASTER_ENABLE_0;
+	return status;
+}
+
+/**
+ * \brief Initializes the requested I<SUP>2</SUP>C hardware module
+ *
+ * Initializes the I<SUP>2</SUP>C slave device requested and sets the provided
+ * software module struct. Run this function before any further use of
+ * the driver.
+ *
+ * \param[out] module  Pointer to software module struct
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK                        Module initiated correctly
+ * \retval STATUS_ERR_INVALID_ARG           Invalid argument in module or config structure.
+ * \retval STATUS_ERR_ALREADY_INITIALIZED   If the Pinmux is not a valid one for I2C signals.
+ *
+ */
+enum status_code i2c_slave_init(
+		struct i2c_slave_module *const module,
+		I2c *const hw,
+		const struct i2c_slave_config *const config)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+
+	module->hw = hw;
+	
+	/* Sanity check arguments. */
+	if ((module == NULL) || (config == NULL))
+		return STATUS_ERR_INVALID_ARG;
+
+	i2c_disable(module->hw);
+	
+	if (module->hw == I2C0)
+		system_peripheral_reset(PERIPHERAL_I2C0_CORE);
+	else if (module->hw == I2C1) {
+		system_peripheral_reset(PERIPHERAL_I2C1_CORE);
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Initialize values in module. */
+	module->registered_callback = 0;
+	module->enabled_callback    = 0;
+	module->buffer_length       = 0;
+	module->buffer_remaining    = 0;
+	module->buffer              = NULL;
+	module->status              = STATUS_OK;
+
+	_i2c_instances = (void*)module;
+	if (module->hw == I2C0) {
+		system_register_isr(RAM_ISR_TABLE_I2CRX0_INDEX, (uint32_t)_i2c_slave_rx_isr_handler);
+		system_register_isr(RAM_ISR_TABLE_I2CTX0_INDEX, (uint32_t)_i2c_slave_tx_isr_handler);
+		NVIC_EnableIRQ(I2C0_RX_IRQn);
+		NVIC_EnableIRQ(I2C0_TX_IRQn);
+	} else if (module->hw == I2C1) {
+		system_register_isr(RAM_ISR_TABLE_I2CRX1_INDEX, (uint32_t)_i2c_slave_rx_isr_handler);
+		system_register_isr(RAM_ISR_TABLE_I2CTX1_INDEX, (uint32_t)_i2c_slave_tx_isr_handler);
+		NVIC_EnableIRQ(I2C1_RX_IRQn);
+		NVIC_EnableIRQ(I2C1_TX_IRQn);
+	}
+#endif
+
+	/* Set config and return status. */
+	if(_i2c_slave_set_config(module, config) != STATUS_OK)
+		return STATUS_ERR_NOT_INITIALIZED;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Reads a packet from the master
+ *
+ * Reads a packet from the master. This will wait for the master to issue a
+ * request.
+ *
+ * \param[in]  module  Pointer to software module structure
+ * \param[out] packet  Packet to read from master
+ *
+ * \return Status of packet read.
+ * \retval STATUS_OK                Packet was read successfully
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) was provided
+ */
+enum status_code i2c_slave_read_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	I2c *const i2c_module = (module->hw);
+	uint16_t counter = 0;
+	uint32_t status  = 0;
+	uint16_t length  = packet->data_length;
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	do {
+		status = i2c_module->RECEIVE_STATUS.reg;
+		if (status & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+			packet->data[counter++] = i2c_module->RECEIVE_DATA.reg;
+	} while (counter < length);
+
+	/* Now check whether the core has sent the data out and free the bus. */
+	while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY)) {
+		status = i2c_module->TRANSMIT_STATUS.reg;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Writes a packet to the master
+ *
+ * Writes a packet to the master. This will wait for the master to issue
+ * a request.
+ *
+ * \param[in]  module  Pointer to software module structure
+ * \param[in]  packet  Packet to write to master
+ *
+ * \return Status of packet write.
+ * \retval STATUS_OK                Packet was written successfully
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) was provided
+ */
+enum status_code i2c_slave_write_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	I2c *const i2c_module = (module->hw);
+	uint16_t i = 0;
+	uint32_t status = 0;
+	uint16_t length = packet->data_length;
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	i2c_wait_for_idle(i2c_module);
+	
+	/* Flush the FIFO */
+	i2c_module->I2C_FLUSH.reg = 1;
+
+	do {
+		status = i2c_module->TRANSMIT_STATUS.reg;
+		if (status & I2C_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_Msk) {
+			i2c_module->TRANSMIT_DATA.reg = packet->data[i++];
+		}
+	} while (i < length);
+
+	/* Now check whether the core has sent the data out and its good to free the bus */
+	while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY)) {
+		status = i2c_module->TRANSMIT_STATUS.reg;
+	}
+
+	return STATUS_OK;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.h
new file mode 100644
index 0000000000..6a5faa9193
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.h
@@ -0,0 +1,231 @@
+/**
+ * \file
+ *
+ * \brief I2C Slave Driver for SAMB
+ *
+ * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2C_SLAVE_H_INCLUDED
+#define I2C_SLAVE_H_INCLUDED
+
+#include "i2c_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_samb_i2c_group
+ *
+ * @{
+ *
+ */
+
+/**
+ * \brief I<SUP>2</SUP>C slave packet for read/write
+ *
+ * Structure to be used when transferring I<SUP>2</SUP>C slave packets.
+ */
+struct i2c_slave_packet {
+	/** Length of data array */
+	uint16_t data_length;
+	/** Data array containing all data to be transferred */
+	uint8_t *data;
+};
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /**
+ * \brief Callback types
+ *
+ * The available callback types for the I<SUP>2</SUP>C slave.
+ */
+enum i2c_slave_callback {
+	/** Callback for packet write complete */
+	I2C_SLAVE_CALLBACK_WRITE_COMPLETE,
+	/** Callback for packet read complete */
+	I2C_SLAVE_CALLBACK_READ_COMPLETE,
+	/**
+	 * Callback for read request from master - can be used to
+	 * issue a write
+	 */
+	I2C_SLAVE_CALLBACK_READ_REQUEST,
+	/**
+	 * Callback for write request from master - can be used to issue a read
+	 */
+	I2C_SLAVE_CALLBACK_WRITE_REQUEST,
+	/** Callback for error */
+	I2C_SLAVE_CALLBACK_ERROR,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_I2C_SLAVE_CALLBACK_N,
+#  endif
+};
+
+#  if !defined(__DOXYGEN__)
+/** Software module prototype. */
+struct i2c_slave_module;
+
+/** Callback type. */
+typedef void (*i2c_slave_callback_t)(
+		struct i2c_slave_module *const module);
+#  endif
+#endif
+
+/**
+ * \brief Enum for the direction of a request
+ *
+ * Enum for the direction of a request.
+ */
+enum i2c_slave_direction {
+	/** Read */
+	I2C_SLAVE_DIRECTION_READ,
+	/** Write */
+	I2C_SLAVE_DIRECTION_WRITE,
+	/** No direction */
+	I2C_SLAVE_DIRECTION_NONE,
+};
+
+/**
+ * \brief I<SUP>2</SUP>C Slave driver software device instance structure.
+ *
+ * I<SUP>2</SUP>C Slave driver software instance structure, used to
+ * retain software state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct i2c_slave_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware instance initialized for the struct */
+	I2c *hw;
+	/** Module lock */
+	volatile bool locked;
+	/** Timeout value for polled functions */
+	uint16_t buffer_timeout;
+#  if I2C_SLAVE_CALLBACK_MODE == true
+	/** Pointers to callback functions */
+	volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N];
+	/** Mask for registered callbacks */
+	volatile uint8_t registered_callback;
+	/** Mask for enabled callbacks */
+	volatile uint8_t enabled_callback;
+	/** The total number of bytes to transfer */
+	volatile uint16_t buffer_length;
+	/**
+	 * Counter used for bytes left to send in write and to count number of
+	 * obtained bytes in read
+	 */
+	uint16_t buffer_remaining;
+	/** Data buffer for packet write and read */
+	volatile uint8_t *buffer;
+	/** Save direction of request from master. 1 = read, 0 = write. */
+	volatile enum i2c_transfer_direction transfer_direction;
+	/** Status for status read back in error callback */
+	volatile enum status_code status;
+#  endif
+#endif
+};
+
+/**
+ * \brief Configuration structure for the I<SUP>2</SUP>C Slave device
+ *
+ * This is the configuration structure for the I<SUP>2</SUP>C Slave device. It is used
+ * as an argument for \ref i2c_slave_init to provide the desired
+ * configurations for the module. The structure should be initialized using the
+ * \ref i2c_slave_get_config_defaults.
+ */
+struct i2c_slave_config {
+	/** Timeout to wait for master in polled functions */
+	uint16_t buffer_timeout;
+	/** Address or upper limit of address range */
+	uint16_t address;
+	/** CLOCK INPUT to use as clock source */
+	enum i2c_clock_input clock_source;
+	/** Divide ratio used to generate the sck clock */
+	uint16_t clock_divider;
+	/** PAD0 (SDA) pin number */
+	uint32_t pin_number_pad0;
+	/** PAD0 (SDA) pinmux selection */
+	uint32_t pinmux_sel_pad0;
+	/** PAD1 (SCL) pin numer */
+	uint32_t pin_number_pad1;
+	/** PAD1 (SCL) pinmux selection */
+	uint32_t pinmux_sel_pad1;
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+void i2c_slave_get_config_defaults(
+		struct i2c_slave_config *const config);
+enum status_code i2c_slave_init(struct i2c_slave_module *const module,
+		I2c *const hw,
+		const struct i2c_slave_config *const config);
+enum status_code i2c_slave_write_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet);
+enum status_code i2c_slave_read_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet);
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+uint32_t i2c_slave_get_status(
+		struct i2c_slave_module *const module);
+void i2c_slave_clear_status(
+		struct i2c_slave_module *const module,
+		uint32_t status_flags);
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_SLAVE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.c
new file mode 100644
index 0000000000..510af6f7c6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.c
@@ -0,0 +1,330 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Interrupt Driver for SAMB
+ *
+ * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_slave_interrupt.h"
+
+void *_i2c_instances;
+
+/**
+ * \internal
+ * Reads next data. Used by interrupt handler to get next data byte from master.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_slave_read(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	
+	I2c *const i2c_module = module->hw;
+
+	/* Read byte from master and put in buffer. */
+	*(module->buffer++) = i2c_module->RECEIVE_DATA.reg;
+
+	/*Decrement remaining buffer length */
+	module->buffer_remaining--;
+}
+
+/**
+ * \internal
+ * Writes next data. Used by interrupt handler to send next data byte to master.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_slave_write(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	
+	I2c *const i2c_module = module->hw;
+
+	/* Write byte from buffer to master */
+	i2c_module->TRANSMIT_DATA.reg = *(module->buffer++);
+
+	/*Decrement remaining buffer length */
+	module->buffer_remaining--;
+}
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type. To enable the callback, the
+ * \ref i2c_slave_enable_callback function must be used.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback       Pointer to the function desired for the
+ *                               specified callback
+ * \param[in]     callback_type  Callback type to register
+ */
+void i2c_slave_register_callback(
+		struct i2c_slave_module *const module,
+		i2c_slave_callback_t callback,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(callback);
+
+	/* Register callback. */
+	module->callbacks[callback_type] = callback;
+
+	/* Set corresponding bit to set callback as initiated. */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * Removes the currently registered callback for the given callback
+ * type.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback_type  Callback type to unregister
+ */
+void i2c_slave_unregister_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Register callback. */
+	module->callbacks[callback_type] = NULL;
+
+	/* Set corresponding bit to set callback as initiated. */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Initiates a reads packet operation
+ *
+ * Reads a data packet from the master. A write request must be initiated by
+ * the master before the packet can be read.
+ *
+ * The \ref I2C_SLAVE_CALLBACK_WRITE_REQUEST callback can be used to call this
+ * function.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting asynchronously reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_slave_read_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	I2c *const i2c_module = module->hw;
+	
+	/* Check if the I2C module is busy doing async operation. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Save packet to software module. */
+	module->buffer           = packet->data;
+	module->buffer_remaining = packet->data_length;
+	module->buffer_length    = packet->data_length;
+	module->status           = STATUS_BUSY;
+
+	/* Enable interrupts */
+	i2c_slave_rx_interrupt(i2c_module, true);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a write packet operation
+ *
+ * Writes a data packet to the master. A read request must be initiated by
+ * the master before the packet can be written.
+ *
+ * The \ref I2C_SLAVE_CALLBACK_READ_REQUEST callback can be used to call this
+ * function.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If writing was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another transfer
+ */
+enum status_code i2c_slave_write_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+	
+	I2c *const i2c_module = module->hw;
+	
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Save packet to software module. */
+	module->buffer           = packet->data;
+	module->buffer_remaining = packet->data_length;
+	module->buffer_length    = packet->data_length;
+	module->status			 = STATUS_BUSY;
+
+	/* Enable interrupts */
+	i2c_slave_tx_interrupt(i2c_module, true);
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal Interrupt handler for I<SUP>2</SUP>C slave
+ *
+ * \param[in] instance  I2C instance that triggered the interrupt
+ */
+void _i2c_slave_rx_isr_handler(void)
+{
+	/* Get software module for callback handling. */
+	struct i2c_slave_module *module =
+			(struct i2c_slave_module*)_i2c_instances;
+
+	Assert(module);
+
+	I2c *const i2c_module = module->hw;
+
+	/* Combine callback registered and enabled masks. */
+	uint8_t callback_mask =
+			module->enabled_callback & module->registered_callback;
+
+	if (i2c_module->RECEIVE_STATUS.reg & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
+		if (!module->buffer_length && (module->buffer_length == module->buffer_remaining)) {
+			module->transfer_direction = I2C_TRANSFER_WRITE;
+			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)) {
+				/* Write to master complete */
+				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
+			}
+		} 
+		/* Continue buffer write/read */
+		if (module->buffer_length > 0 && module->buffer_remaining > 0) {
+				_i2c_slave_read(module);
+		}
+		if (!module->buffer_remaining) {
+			module->status = STATUS_OK;
+			module->buffer_length = 0;
+			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE)) {
+				/* Write to master complete */
+				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+			}
+		}
+	}
+	if ((i2c_module->RECEIVE_STATUS.reg & I2C_RECEIVE_STATUS_NAK)) { //&&
+			//module->transfer_direction == I2C_TRANSFER_READ) {
+		/* Received NAK, master received completed. */
+		i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
+		if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE)) {
+			module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+		}
+	}
+	
+	if (module->hw == I2C0) {
+		NVIC_ClearPendingIRQ(I2C0_RX_IRQn);
+	} else if (module->hw == I2C1) {
+		NVIC_ClearPendingIRQ(I2C1_RX_IRQn);
+	}
+}
+
+void _i2c_slave_tx_isr_handler(void)
+{
+	/* Get software module for callback handling. */
+	struct i2c_slave_module *module =
+			(struct i2c_slave_module*)_i2c_instances;
+
+	Assert(module);
+
+	I2c *const i2c_module = module->hw;
+
+	/* Combine callback registered and enabled masks. */
+	uint8_t callback_mask =
+			module->enabled_callback & module->registered_callback;
+	
+	if (!module->buffer_length && (module->buffer_length == module->buffer_remaining)) {
+		/* First timer interrupt */
+		module->transfer_direction = I2C_TRANSFER_READ;
+		if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) {
+			/* Write to master complete */
+			module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
+		}
+	} 
+	if (module->buffer_length > 0 && module->buffer_remaining > 0) {
+		_i2c_slave_write(module);
+	}
+	if (!module->buffer_remaining) {
+		module->status = STATUS_OK;
+		module->buffer_length = 0;
+		i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
+		if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE)) {
+			module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+		}
+	}
+	
+	if (module->hw == I2C0) {
+		NVIC_ClearPendingIRQ(I2C0_TX_IRQn);
+	} else if (module->hw == I2C1) {
+		NVIC_ClearPendingIRQ(I2C1_TX_IRQn);
+	}
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.h
new file mode 100644
index 0000000000..aade2ecab3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.h
@@ -0,0 +1,146 @@
+/**
+ * \file
+ *
+ * \brief I2C Slave Interrupt Driver for SAMB
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2C_SLAVE_INTERRUPT_H_INCLUDED
+#define I2C_SLAVE_INTERRUPT_H_INCLUDED
+
+#include "i2c_slave.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_samb_i2c_group
+ * @{
+ *
+ */
+
+/**
+ * \name Callbacks
+ * @{
+ */
+#if !defined(__DOXYGEN__)
+extern void *_i2c_instances;
+void _i2c_slave_rx_isr_handler(void);
+void _i2c_slave_tx_isr_handler(void);
+#endif
+
+void i2c_slave_register_callback(
+		struct i2c_slave_module *const module,
+		i2c_slave_callback_t callback,
+		enum i2c_slave_callback callback_type);
+
+void i2c_slave_unregister_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback_type  Callback type to enable
+ */
+static inline void i2c_slave_enable_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as enabled */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback_type  Callback type to disable
+ */
+static inline void i2c_slave_disable_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as disabled */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/** @} */
+
+/**
+ * \name Read and Write, Interrupt-Driven
+ * @{
+ */
+
+
+enum status_code i2c_slave_read_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet);
+
+enum status_code i2c_slave_write_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet);
+
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_SLAVE_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.c
new file mode 100644
index 0000000000..bbf04620bb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.c
@@ -0,0 +1,750 @@
+/**
+ * \file
+ *
+ * \brief SAM I2S - Inter-IC Sound Controller
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2s.h"
+
+/**
+ * \brief Initializes a hardware I<SUP>2</SUP>S module instance
+ *
+ * Enables the clock and initialize the I<SUP>2</SUP>S module.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     hw           Pointer to the TCC hardware module
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_BUSY         Hardware module was busy when the
+ *                             initialization procedure was attempted
+ * \retval STATUS_ERR_DENIED   Hardware module was already enabled
+ */
+enum status_code i2s_init(
+		struct i2s_module *const module_inst,
+		I2s *hw)
+{
+	Assert(module_inst);
+	Assert(hw);
+
+	/* Enable the user interface clock in the PM */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_I2S);
+
+	/* Status check */
+	uint32_t ctrla;
+	ctrla = module_inst->hw->CTRLA.reg;
+	if (ctrla & I2S_CTRLA_ENABLE) {
+		if (ctrla & (I2S_CTRLA_SEREN1 |
+				I2S_CTRLA_SEREN0 | I2S_CTRLA_CKEN1 | I2S_CTRLA_CKEN0)) {
+			return STATUS_BUSY;
+		} else {
+			return STATUS_ERR_DENIED;
+		}
+	}
+
+	/* Initialize module */
+	module_inst->hw = hw;
+
+	/* Initialize serializers */
+#if I2S_CALLBACK_MODE == true
+	int i, j;
+	for (i = 0; i < 2; i ++) {
+		for (j = 0; j < I2S_SERIALIZER_CALLBACK_N; j ++) {
+			module_inst->serializer[i].callback[j] = NULL;
+		}
+		module_inst->serializer[i].registered_callback_mask = 0;
+		module_inst->serializer[i].enabled_callback_mask = 0;
+
+		module_inst->serializer[i].job_buffer = NULL;
+		module_inst->serializer[i].job_status = STATUS_OK;
+		module_inst->serializer[i].requested_words = 0;
+		module_inst->serializer[i].transferred_words = 0;
+
+		module_inst->serializer[i].mode = I2S_SERIALIZER_RECEIVE;
+		module_inst->serializer[i].data_size = I2S_DATA_SIZE_32BIT;
+	}
+
+	_i2s_instances[0] = module_inst;
+
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_I2S);
+#endif
+
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Configure specified I<SUP>2</SUP>S clock unit
+ *
+ * Enables the clock and initialize the clock unit, based on the given
+ * configurations.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     clock_unit   I<SUP>2</SUP>S clock unit to initialize and configure
+ * \param[in]     config       Pointer to the I<SUP>2</SUP>S clock unit configuration
+ *                             options struct
+ *
+ * \return Status of the configuration procedure.
+ *
+ * \retval STATUS_OK              The module was initialized successfully
+ * \retval STATUS_BUSY            Hardware module was busy when the
+ *                                configuration procedure was attempted
+ * \retval STATUS_ERR_DENIED      Hardware module was already enabled
+ * \retval STATUS_ERR_INVALID_ARG Invalid divider value or
+ *                                MCK direction setting conflict
+ */
+enum status_code i2s_clock_unit_set_config(
+		struct i2s_module *const module_inst,
+		const enum i2s_clock_unit clock_unit,
+		const struct i2s_clock_unit_config *config)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(clock_unit < I2S_CLOCK_UNIT_N);
+	Assert(config);
+
+	/* Status check */
+	uint32_t ctrla, syncbusy;
+	syncbusy = module_inst->hw->SYNCBUSY.reg;
+	ctrla = module_inst->hw->CTRLA.reg;
+
+	/* Busy ? */
+	if (syncbusy & (I2S_SYNCBUSY_CKEN0 << clock_unit)) {
+		return STATUS_BUSY;
+	}
+	/* Already enabled ? */
+	if (ctrla & (I2S_CTRLA_CKEN0 << clock_unit)) {
+		return STATUS_ERR_DENIED;
+	}
+	/* Parameter check */
+	if (config->clock.mck_src && config->clock.mck_out_enable) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Initialize Clock Unit */
+	uint32_t clkctrl =
+		(config->clock.mck_out_invert ? I2S_CLKCTRL_MCKOUTINV : 0) |
+		(config->clock.sck_out_invert ? I2S_CLKCTRL_SCKOUTINV : 0) |
+		(config->frame.frame_sync.invert_out ? I2S_CLKCTRL_FSOUTINV : 0) |
+		(config->clock.mck_out_enable ? I2S_CLKCTRL_MCKEN : 0) |
+		(config->clock.mck_src ? I2S_CLKCTRL_MCKSEL : 0) |
+		(config->clock.sck_src ? I2S_CLKCTRL_SCKSEL : 0) |
+		(config->frame.frame_sync.invert_use ? I2S_CLKCTRL_FSINV : 0) |
+		(config->frame.frame_sync.source ? I2S_CLKCTRL_FSSEL : 0) |
+		(config->frame.data_delay ? I2S_CLKCTRL_BITDELAY : 0);
+
+	uint8_t div_val = config->clock.mck_out_div;
+	if ((div_val > 0x21) || (div_val == 0)) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		div_val --;
+	}
+	clkctrl |= I2S_CLKCTRL_MCKOUTDIV(div_val);
+
+	div_val = config->clock.sck_div;
+	if ((div_val > 0x21) || (div_val == 0)) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		div_val --;
+	}
+	clkctrl |= I2S_CLKCTRL_MCKDIV(div_val);
+
+	uint8_t number_slots = config->frame.number_slots;
+	if (number_slots > 8) {
+		return STATUS_ERR_INVALID_ARG;
+	} else if (number_slots > 0) {
+		number_slots --;
+	}
+	clkctrl |=
+			I2S_CLKCTRL_NBSLOTS(number_slots) |
+			I2S_CLKCTRL_FSWIDTH(config->frame.frame_sync.width) |
+			I2S_CLKCTRL_SLOTSIZE(config->frame.slot_size);
+
+	/* Write clock unit configurations */
+	module_inst->hw->CLKCTRL[clock_unit].reg = clkctrl;
+
+	/* Select general clock source */
+	const uint8_t i2s_gclk_ids[2] = {I2S_GCLK_ID_0, I2S_GCLK_ID_1};
+	struct system_gclk_chan_config gclk_chan_config;
+	system_gclk_chan_get_config_defaults(&gclk_chan_config);
+	gclk_chan_config.source_generator = config->clock.gclk_src;
+	system_gclk_chan_set_config(i2s_gclk_ids[clock_unit], &gclk_chan_config);
+	system_gclk_chan_enable(i2s_gclk_ids[clock_unit]);
+
+	/* Initialize pins */
+	struct system_pinmux_config pin_config;
+	system_pinmux_get_config_defaults(&pin_config);
+	if (config->mck_pin.enable) {
+		pin_config.mux_position = config->mck_pin.mux;
+		system_pinmux_pin_set_config(config->mck_pin.gpio, &pin_config);
+	}
+	if (config->sck_pin.enable) {
+		pin_config.mux_position = config->sck_pin.mux;
+		system_pinmux_pin_set_config(config->sck_pin.gpio, &pin_config);
+	}
+	if (config->fs_pin.enable) {
+		pin_config.mux_position = config->fs_pin.mux;
+		system_pinmux_pin_set_config(config->fs_pin.gpio, &pin_config);
+	}
+
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Configure specified I<SUP>2</SUP>S serializer
+ *
+ * Enables the clock and initialize the serializer, based on the given
+ * configurations.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     serializer   I<SUP>2</SUP>S serializer to initialize and configure
+ * \param[in]     config       Pointer to the I<SUP>2</SUP>S serializer configuration
+ *                             options struct
+ *
+ * \return Status of the configuration procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_BUSY         Hardware module was busy when the
+ *                             configuration procedure was attempted
+ * \retval STATUS_ERR_DENIED   Hardware module was already enabled
+ */
+enum status_code i2s_serializer_set_config(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const struct i2s_serializer_config *config)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(serializer < I2S_SERIALIZER_N);
+	Assert(config);
+
+	/* Status check */
+	uint32_t ctrla, syncbusy;
+	syncbusy = module_inst->hw->SYNCBUSY.reg;
+	ctrla = module_inst->hw->CTRLA.reg;
+
+	/* Busy ? */
+	if (syncbusy & ((I2S_SYNCBUSY_SEREN0 | I2S_SYNCBUSY_DATA0) << serializer)) {
+		return STATUS_BUSY;
+	}
+	/* Already enabled ? */
+	if (ctrla & (I2S_CTRLA_CKEN0 << serializer)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Initialize Serializer */
+	uint32_t serctrl =
+			(config->loop_back ? I2S_SERCTRL_RXLOOP : 0) |
+			(config->dma_usage ? I2S_SERCTRL_DMA : 0) |
+			(config->mono_mode ? I2S_SERCTRL_MONO : 0) |
+			(config->disable_data_slot[7] ? I2S_SERCTRL_SLOTDIS7 : 0) |
+			(config->disable_data_slot[6] ? I2S_SERCTRL_SLOTDIS6 : 0) |
+			(config->disable_data_slot[5] ? I2S_SERCTRL_SLOTDIS5 : 0) |
+			(config->disable_data_slot[4] ? I2S_SERCTRL_SLOTDIS4 : 0) |
+			(config->disable_data_slot[3] ? I2S_SERCTRL_SLOTDIS3 : 0) |
+			(config->disable_data_slot[2] ? I2S_SERCTRL_SLOTDIS2 : 0) |
+			(config->disable_data_slot[1] ? I2S_SERCTRL_SLOTDIS1 : 0) |
+			(config->disable_data_slot[0] ? I2S_SERCTRL_SLOTDIS0 : 0) |
+			(config->transfer_lsb_first ? I2S_SERCTRL_BITREV : 0) |
+			(config->data_adjust_left_in_word ? I2S_SERCTRL_WORDADJ : 0) |
+			(config->data_adjust_left_in_slot ? I2S_SERCTRL_SLOTADJ : 0) |
+			(config->data_padding ? I2S_SERCTRL_TXSAME : 0);
+
+	if (config->clock_unit < I2S_CLOCK_UNIT_N) {
+		serctrl |= (config->clock_unit ? I2S_SERCTRL_CLKSEL : 0);
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	serctrl |=
+			I2S_SERCTRL_SERMODE(config->mode) |
+			I2S_SERCTRL_TXDEFAULT(config->line_default_state) |
+			I2S_SERCTRL_DATASIZE(config->data_size) |
+			I2S_SERCTRL_EXTEND(config->bit_padding);
+
+	/* Write Serializer configuration */
+	module_inst->hw->SERCTRL[serializer].reg = serctrl;
+
+	/* Initialize pins */
+	struct system_pinmux_config pin_config;
+	system_pinmux_get_config_defaults(&pin_config);
+	if (config->data_pin.enable) {
+		pin_config.mux_position = config->data_pin.mux;
+		system_pinmux_pin_set_config(config->data_pin.gpio, &pin_config);
+	}
+
+	/* Save configure */
+	module_inst->serializer[serializer].mode = config->mode;
+	module_inst->serializer[serializer].data_size = config->data_size;
+
+	return STATUS_OK;
+}
+
+
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module_inst  Pointer to the I<SUP>2</SUP>S software instance struct
+ *
+ * \return Bitmask of \c I2S_STATUS_* flags.
+ *
+ * \retval I2S_STATUS_SYNC_BUSY            Module is busy synchronization
+ * \retval I2S_STATUS_TRANSMIT_UNDERRUN(x) Serializer x (0~1) is underrun
+ * \retval I2S_STATUS_TRANSMIT_READY(x)    Serializer x (0~1) is ready to
+ *                                         transmit new data word
+ * \retval I2S_STATUS_RECEIVE_OVERRUN(x)   Serializer x (0~1) is overrun
+ * \retval I2S_STATUS_RECEIVE_READY(x)     Serializer x (0~1) has data ready to
+ *                                         read
+ */
+uint32_t i2s_get_status(
+		const struct i2s_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint32_t intflag = module_inst->hw->INTFLAG.reg;
+	uint32_t status;
+	if (module_inst->hw->SYNCBUSY.reg) {
+		status = I2S_STATUS_SYNC_BUSY;
+	} else {
+		status = 0;
+	}
+	if (intflag & I2S_INTFLAG_TXUR0) {
+		status |= I2S_STATUS_TRANSMIT_UNDERRUN(0);
+	}
+	if (intflag & I2S_INTFLAG_TXUR1) {
+		status |= I2S_STATUS_TRANSMIT_UNDERRUN(1);
+	}
+	if ((intflag & I2S_INTFLAG_TXRDY0) &&
+		!module_inst->hw->SYNCBUSY.bit.DATA0) {
+		status |= I2S_STATUS_TRANSMIT_READY(0);
+	}
+	if ((intflag & I2S_INTFLAG_TXRDY1) &&
+		!module_inst->hw->SYNCBUSY.bit.DATA1) {
+		status |= I2S_STATUS_TRANSMIT_READY(1);
+	}
+	if (intflag & I2S_INTFLAG_RXOR0) {
+		status |= I2S_STATUS_RECEIVE_OVERRUN(0);
+	}
+	if (intflag & I2S_INTFLAG_RXOR1) {
+		status |= I2S_STATUS_RECEIVE_OVERRUN(1);
+	}
+	if (intflag & I2S_INTFLAG_RXRDY0) {
+		status |= I2S_STATUS_RECEIVE_READY(0);
+	}
+	if (intflag & I2S_INTFLAG_RXRDY1) {
+		status |= I2S_STATUS_RECEIVE_READY(1);
+	}
+	return status;
+}
+
+/**
+ * \brief Clears a module status flags.
+ *
+ * Clears the given status flags of the module.
+ *
+ * \param[in] module_inst   Pointer to the I<SUP>2</SUP>S software instance struct
+ * \param[in] status        Bitmask of \c I2S_STATUS_* flags to clear
+ */
+void i2s_clear_status(
+		const struct i2s_module *const module_inst,
+		uint32_t status)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint32_t intflag = 0;
+
+	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
+		intflag = I2S_INTFLAG_TXUR0;
+	}
+	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
+		intflag = I2S_INTFLAG_TXUR1;
+	}
+	if (status & I2S_STATUS_TRANSMIT_READY(0)) {
+		intflag = I2S_INTFLAG_TXRDY0;
+	}
+	if (status & I2S_STATUS_TRANSMIT_READY(1)) {
+		intflag = I2S_INTFLAG_TXRDY1;
+	}
+	if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
+		intflag = I2S_INTFLAG_RXOR0;
+	}
+	if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
+		intflag = I2S_INTFLAG_RXOR1;
+	}
+	if (status & I2S_STATUS_RECEIVE_READY(0)) {
+		intflag = I2S_INTFLAG_RXRDY0;
+	}
+	if (status & I2S_STATUS_RECEIVE_READY(1)) {
+		intflag = I2S_INTFLAG_RXRDY1;
+	}
+	module_inst->hw->INTFLAG.reg = intflag;
+}
+
+/**
+ * \brief Enable interrupts on status set
+ *
+ * Enable the given status interrupt request from the I<SUP>2</SUP>S module.
+ *
+ * \param[in] module_inst Pointer to the I<SUP>2</SUP>S software instance struct
+ * \param[in] status Status interrupts to enable
+ *
+ * \return Status of enable procedure.
+ *
+ * \retval STATUS_OK              Interrupt is enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG Status with no interrupt is passed
+ */
+enum status_code i2s_enable_status_interrupt(
+		struct i2s_module *const module_inst,
+		uint32_t status)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	/* No sync busy interrupt */
+	if (status & I2S_STATUS_SYNC_BUSY) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+	Assert(module_inst->hw);
+
+	uint32_t intflag = 0;
+	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
+		intflag = I2S_INTFLAG_TXUR0;
+	}
+	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
+		intflag = I2S_INTFLAG_TXUR1;
+	}
+	if (status & I2S_STATUS_TRANSMIT_READY(0)) {
+		intflag = I2S_INTFLAG_TXRDY0;
+	}
+	if (status & I2S_STATUS_TRANSMIT_READY(1)) {
+		intflag = I2S_INTFLAG_TXRDY1;
+	}
+	if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
+		intflag = I2S_INTFLAG_RXOR0;
+	}
+	if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
+		intflag = I2S_INTFLAG_RXOR1;
+	}
+	if (status & I2S_STATUS_RECEIVE_READY(0)) {
+		intflag = I2S_INTFLAG_RXRDY0;
+	}
+	if (status & I2S_STATUS_RECEIVE_READY(1)) {
+		intflag = I2S_INTFLAG_RXRDY1;
+	}
+	module_inst->hw->INTENSET.reg = intflag;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disable interrupts on status set
+ *
+ * Disable the given status interrupt request from the I<SUP>2</SUP>S module.
+ *
+ * \param[in] module_inst Pointer to the I<SUP>2</SUP>S software instance struct
+ * \param[in] status Status interrupts to disable
+ */
+void i2s_disable_status_interrupt(
+		struct i2s_module *const module_inst,
+		uint32_t status)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint32_t intflag = 0;
+	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
+		intflag = I2S_INTFLAG_TXUR0;
+	}
+	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
+		intflag = I2S_INTFLAG_TXUR1;
+	}
+	if (status & I2S_STATUS_TRANSMIT_READY(0)) {
+		intflag = I2S_INTFLAG_TXRDY0;
+	}
+	if (status & I2S_STATUS_TRANSMIT_READY(1)) {
+		intflag = I2S_INTFLAG_TXRDY1;
+	}
+	if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
+		intflag = I2S_INTFLAG_RXOR0;
+	}
+	if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
+		intflag = I2S_INTFLAG_RXOR1;
+	}
+	if (status & I2S_STATUS_RECEIVE_READY(0)) {
+		intflag = I2S_INTFLAG_RXRDY0;
+	}
+	if (status & I2S_STATUS_RECEIVE_READY(1)) {
+		intflag = I2S_INTFLAG_RXRDY1;
+	}
+	module_inst->hw->INTENCLR.reg = intflag;
+}
+
+
+/**
+ * \brief Write buffer to the specified Serializer of I<SUP>2</SUP>S module
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    The serializer to write to
+ * \param[in]  buffer        The data buffer to write
+ * \param[in]  size          Number of data words to write
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK               The data was sent successfully
+ * \retval STATUS_ERR_DENIED       The module or serializer is disabled
+ * \retval STATUS_ERR_INVALID_ARG  An invalid buffer pointer was supplied
+ */
+enum status_code i2s_serializer_write_buffer_wait(
+		const struct i2s_module *const module_inst,
+		enum i2s_serializer serializer,
+		void *buffer, uint32_t size)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(serializer < I2S_SERIALIZER_N);
+	Assert(buffer);
+
+	if (size == 0) {
+		return STATUS_OK;
+	}
+
+	uint8_t data_size = 1; /* number of bytes */
+	struct i2s_serializer_module *data_module = (struct i2s_serializer_module *)
+			&module_inst->serializer[serializer];
+
+	/* Check buffer */
+	switch(data_module->data_size) {
+	case I2S_DATA_SIZE_32BIT:
+	case I2S_DATA_SIZE_24BIT:
+	case I2S_DATA_SIZE_20BIT:
+	case I2S_DATA_SIZE_18BIT:
+		if ((uint32_t)buffer & 0x3) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		data_size = 4;
+		break;
+	case I2S_DATA_SIZE_16BIT:
+	case I2S_DATA_SIZE_16BIT_COMPACT:
+		if ((uint32_t)buffer & 0x1) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		data_size = 2;
+		break;
+	default:
+		break;
+	}
+
+	/* Check status */
+	if (!(module_inst->hw->CTRLA.reg &
+		(I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer)))) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Write */
+	uint32_t i;
+	uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
+	uint32_t ready_bit = I2S_INTFLAG_TXRDY0 << serializer;
+	if (4 == data_size) {
+		uint32_t *p32 = (uint32_t*)buffer;
+		for (i = 0; i < size; i ++) {
+			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+				/* Wait Tx ready */
+			}
+			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
+				/* Wait Sync */
+			}
+			module_inst->hw->DATA[serializer].reg = p32[i];
+			module_inst->hw->INTFLAG.reg = ready_bit;
+		}
+	} else if (2 == data_size) {
+		uint16_t *p16 = (uint16_t*)buffer;
+		for (i = 0; i < size; i ++) {
+			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+				/* Wait Tx ready */
+			}
+			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
+				/* Wait Sync */
+			}
+			module_inst->hw->DATA[serializer].reg = p16[i];
+			module_inst->hw->INTFLAG.reg = ready_bit;
+		}
+	} else {
+		uint8_t *p8 = (uint8_t*)buffer;
+		for (i = 0; i < size; i ++) {
+			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+				/* Wait Tx ready */
+			}
+			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
+				/* Wait Sync */
+			}
+			module_inst->hw->DATA[serializer].reg = p8[i];
+			module_inst->hw->INTFLAG.reg = ready_bit;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Read from the specified Serializer of I<SUP>2</SUP>S module to a buffer
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    The serializer to write to
+ * \param[in]  buffer        The buffer to fill read data (NULL to discard)
+ * \param[in]  size          Number of data words to read
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK               The data was sent successfully
+ * \retval STATUS_ERR_DENIED       The module or serializer is disabled
+ * \retval STATUS_ERR_INVALID_ARG  An invalid buffer pointer was supplied
+ */
+enum status_code i2s_serializer_read_buffer_wait(
+		const struct i2s_module *const module_inst,
+		enum i2s_serializer serializer,
+		void *buffer, uint32_t size)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	if (size == 0) {
+		return STATUS_OK;
+	}
+
+	uint8_t data_size = 1; /* number of bytes */
+	struct i2s_serializer_module *data_module = (struct i2s_serializer_module *)
+			&module_inst->serializer[serializer];
+
+	/* Check buffer */
+	switch(data_module->data_size) {
+		case I2S_DATA_SIZE_32BIT:
+		case I2S_DATA_SIZE_24BIT:
+		case I2S_DATA_SIZE_20BIT:
+		case I2S_DATA_SIZE_18BIT:
+		if ((uint32_t)buffer & 0x3) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		data_size = 4;
+		break;
+		case I2S_DATA_SIZE_16BIT:
+		case I2S_DATA_SIZE_16BIT_COMPACT:
+		if ((uint32_t)buffer & 0x1) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		data_size = 2;
+		break;
+	default:
+		break;
+	}
+
+	/* Check status */
+	if (!(module_inst->hw->CTRLA.reg &
+		(I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer)))) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Read */
+	uint32_t i;
+	uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
+	uint32_t ready_bit = I2S_INTFLAG_RXRDY0 << serializer;
+	if (buffer == NULL) {
+		for (i = 0; i < size; i ++) {
+			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+				/* Wait Rx ready */
+			}
+			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
+				/* Wait Sync */
+			}
+			module_inst->hw->DATA[serializer].reg;
+			module_inst->hw->INTFLAG.reg = ready_bit;
+		}
+	}
+	else if (4 == data_size) {
+		uint32_t *p32 = (uint32_t*)buffer;
+		for (i = 0; i < size; i ++) {
+			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+				/* Wait Rx ready */
+			}
+			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
+				/* Wait Sync */
+			}
+			p32[i] = module_inst->hw->DATA[serializer].reg;
+			module_inst->hw->INTFLAG.reg = ready_bit;
+		}
+	} else if (2 == data_size) {
+		uint16_t *p16 = (uint16_t*)buffer;
+		for (i = 0; i < size; i ++) {
+			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+				/* Wait Rx ready */
+			}
+			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
+				/* Wait Sync */
+			}
+			p16[i] = module_inst->hw->DATA[serializer].reg;
+			module_inst->hw->INTFLAG.reg = ready_bit;
+		}
+	} else {
+		uint8_t *p8 = (uint8_t*)buffer;
+		for (i = 0; i < size; i ++) {
+			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+				/* Wait Tx ready */
+			}
+			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
+				/* Wait Sync */
+			}
+			p8[i] = module_inst->hw->DATA[serializer].reg;
+			module_inst->hw->INTFLAG.reg = ready_bit;
+		}
+	}
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.h
new file mode 100644
index 0000000000..0e965d8d3a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.h
@@ -0,0 +1,1386 @@
+/**
+ * \file
+ *
+ * \brief SAM I2S - Inter-IC Sound Controller
+ *
+ * Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2S_H_INCLUDED
+#define I2S_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_i2s_group SAM Inter-IC Sound Controller (I2S) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's Inter-IC
+ * Sound Controller functionality.
+ *
+ * The following driver API modes are covered by this manual:
+ * - Polled APIs
+ * \if I2S_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - I<SUP>2</SUP>S (Inter-IC Sound Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D21
+ *  - Atmel | SMART SAM DA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_i2s_prerequisites
+ *  - \ref asfdoc_sam0_i2s_module_overview
+ *  - \ref asfdoc_sam0_i2s_special_considerations
+ *  - \ref asfdoc_sam0_i2s_extra_info
+ *  - \ref asfdoc_sam0_i2s_examples
+ *  - \ref asfdoc_sam0_i2s_api_overview
+ *
+ * \section asfdoc_sam0_i2s_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ * \section asfdoc_sam0_i2s_module_overview Module Overview
+ *
+ * The I<SUP>2</SUP>S provides bidirectional, synchronous, digital audio link with
+ * external audio devices through these signal pins:
+ *  - Serial Data (SDm)
+ *  - Frame Sync (FSn)
+ *  - Serial Clock (SCKn)
+ *  - Master Clock (MCKn)
+ *
+ * The I<SUP>2</SUP>S consists of two Clock Units and two Serializers, which can be
+ * separately configured and enabled, to provide varies functionalities as follow:
+ *  - Communicate to Audio CODECs as Master or Slave, or provides clock and
+ *    frame sync signals as Controller
+ *  - Communicate to DAC or ADC through dedicated I<SUP>2</SUP>S serial interface
+ *  - Communicate to multi-slot or multiple stereo DACs or ADCs, via
+ *    Time Division Multiplexed (TDM) format
+ *  - Reading mono or stereo MEMS microphones, using the Pulse Density
+ *    Modulation (PDM) interface
+ *
+ * The I<SUP>2</SUP>S supports compact stereo data word, where left channel data bits are
+ * in lower half and right channel data bits are in upper half. It reduces the
+ * number of data words for stereo audio data and the DMA bandwidth.
+ *
+ * In master mode, the frame is configured by number of slots and slot size, and
+ * allows range covering 16fs to 1024fs MCK, to provide oversampling clock to an
+ * external audio CODEC or digital signal processor (DSP).
+ *
+ * A block diagram of the I<SUP>2</SUP>S can be seen in
+ * \ref asfdoc_sam0_i2s_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_i2s_module_block_diagram
+ * \image html i2s_blocks.svg "I2S Block Diagram"
+ *
+ * This driver for I<SUP>2</SUP>S module provides an interface to:
+ *  - Initialize and control I<SUP>2</SUP>S module
+ *  - Configure and control the I<SUP>2</SUP>S Clock Unit and Serializer
+ *  - Transmit/receive data through I<SUP>2</SUP>S Serializer
+ *
+ * \subsection asfdoc_sam0_i2s_module_overview_clocks Clocks
+ *
+ * To use I<SUP>2</SUP>S module, the I<SUP>2</SUP>S bus interface clock (clk_i2s)
+ * must be enabled via Power Manager.
+ *
+ * For each I<SUP>2</SUP>S Clock Unit, a generic clock (gclk_i2s_n) is connnected.
+ * When I<SUP>2</SUP>S works in master mode the generic clock is used. It should
+ * be prepared before clock unit is used. In master mode the input generic clock
+ * will be used as MCK for SCKn and FSn generation, in addition, the MCK could be
+ * devided and output to I<SUP>2</SUP>S MCKn pin, as oversampling clock to
+ * external audio device.
+ *
+ * The I<SUP>2</SUP>S Serializer uses clock and control signal from Clock Unit to handle
+ * transfer. Select different clock unit with different configurations allows
+ * the I<SUP>2</SUP>S to work as master or slave, to work on non-related clocks.
+ *
+ * When using the driver with ASF, enabling the register interface is normally
+ * done by the \c init function.
+ * The Generic Clock Controller (GCLK) source for the asynchronous domain is
+ * normally configured and set through the _configuration
+ * struct_ / _init_ function.
+ * If GCLK source != 0 is used, this source has to be configured and enabled
+ * through invoking the system_gclk driver function when needed, or modifying
+ * conf_clock.h to enable it at the beginning.
+ *
+ * \subsection asfdoc_sam0_i2s_module_overview_frame Audio Frame Generation
+ *
+ * Audio sample data for all channels are sent in frames, one frame can consist
+ * 1 - 8 slots where each slot can be configured to a size 8-bit, 16-bit, 24-bit,
+ * or 32-bit. The audio frame synch clock is generated by the I<SUP>2</SUP>S
+ * Clock unit in the master/controller mode. The frame rate (or frame sync
+ * frequency) is calculated as follows:
+ *
+ * FS = SCK / number_of_slots / number_of_bits_in_slot
+ *
+ * The serial clock (SCK) source is either an external source (slave mode) or
+ * generated by the I<SUP>2</SUP>S clock unit (controller or master mode) using
+ * the MCK as source.
+ *
+ * SCK = MCK / sck_div
+ * \note SCK generation division value is MCKDIV in register.
+ *
+ * MCK is either an external source or generated using the GCLK input from a
+ * generic clock generator.
+ *
+ * \subsection asfdoc_sam0_i2s_module_overview_mode Master, Controller, and Slave Modes
+ *
+ * The I<SUP>2</SUP>S module has three modes: master, controller, and slave.
+ *
+ * \subsubsection asfdoc_sam0_i2s_module_overview_mode_mst Master
+ * In master mode the module will control the data flow on the I<SUP>2</SUP>S bus and can
+ * be responsible for clock generation. The Serializers are enabled and will
+ * transmit/receive data. On a bus with only master and slave the SCK, and FS
+ * clock signal will be outputted on the SCK and FS pin on the master module.
+ * MCK can optionally be outputted on the MCK pin, if there is a controller
+ * module on the bus the SCK, FS, and optionally the MCK clock is sourced from
+ * the same pins. Serial data will be trancieved on the SD pin in both
+ * scenarios.
+ *
+ * \subsubsection asfdoc_sam0_i2s_module_overview_mode_ctl Controller
+ * In controller mode the module will generate the clock signals, but the
+ * Serializers are disabled and no data will be transmitted/received by the
+ * module in this mode. The clock signals is outputted on the SCK, FS and
+ * optionally the MCK pin.
+ *
+ * \subsubsection asfdoc_sam0_i2s_module_overview_mode_slv Slave
+ * In slave mode the module will use the SCK and FS clock source from the master
+ * or the controller which is received on the SCK and FS pin. The MCK can
+ * optionally be sourced externally on the MCK pin. The Serializers are enabled
+ * and will tranceive data on the SD pin. All data flow is controlled by the
+ * master.
+ *
+ * \subsubsection asfdoc_sam0_i2s_module_overview_mode_chg Switch Modes
+ * The mode switching between master, controller, and slave modes are actually
+ * done by modifying the source mode of I<SUP>2</SUP>S pins.
+ * The source mode of I<SUP>2</SUP>S pins are selected by writing corresponding
+ * bits in CLKCTRLn.
+ * Since source mode switching changes the direction of pin, the mode must be
+ * changed when the I<SUP>2</SUP>S Clock Unit is stopped.
+ *
+ * \subsection asfdoc_sam0_i2s_module_overview_data Data Stream Reception/Transmission
+ *
+ * The I<SUP>2</SUP>S module support several data stream formats:
+ * - I<SUP>2</SUP>S format
+ * - Time Division Multiplexed (TDM) format
+ * - Pulse Density Modulation (PDM) format (reception only)
+ *
+ * Basically the I<SUP>2</SUP>S module can send several words within each frame,
+ * it's more like TDM format. With adjust to the number of data words in a frame,
+ * the FS width, the FS to data bits delay, etc., the module is able to handle
+ * I<SUP>2</SUP>S compliant data stream.
+ *
+ * Also the Serializer can receive PDM format data stream, which allows the 
+ * I<SUP>2</SUP>S module receive 1 PDM data on each SCK edge.
+ *
+ * \subsubsection asfdoc_sam0_i2s_module_overview_data_i2s I2S Stream Reception/Transmission
+ *
+ * For 2-channel I<SUP>2</SUP>S compliant data stream format the I<SUP>2</SUP>S 
+ * module uses the FS line as word select (WS) signal and will send left channel
+ * data word on low WS level and right channel data word on high WS level as
+ * specified in the I<SUP>2</SUP>S standard. The supported word sizes are 8-,
+ * 16-, 18-, 20-, 24-, and 32- bit.
+ *
+ * Thus for I<SUP>2</SUP>S stream, the following settings should be applied to the module:
+ *  - Data starting delay after FS transition : one SCK period
+ *  - FS width : half of frame
+ *  - Data bits adjust in word : left-adjusted
+ *  - Bit transmitting order : MSB first
+ *
+ * Following is an example for I<SUP>2</SUP>S application connections and waveforms. See
+ * the figure below.
+ *
+ * \anchor asfdoc_sam0_i2s_module_i2s_example_diagram
+ * \image html i2s_example.svg "I2S Example Diagram"
+ *
+ * \subsubsection asfdoc_sam0_i2s_module_overview_data_tdm TDM Stream Reception/Transmission
+ * In TDM format, the module sends several data words in each frame. For this
+ * data stream format most of the configurations could be adjusted:
+ *  - Main Frame related settings are as follow:
+ *   - Frame Sync (FS) options:
+ *    - The active edge of the FS (or if FS is inverted before use)
+ *    - The width of the FS
+ *   - The delay between FS to first data bit
+ *  - Data alignment in slot
+ *  - The number of slots and slot size can be adjusted, it has been mentioned
+ *    in \ref asfdoc_sam0_i2s_module_overview_frame
+ *  - The data word size is controlled by Serializer, it can be chosen among
+ *    8, 16, 18, 20, 24, and 32 bits.
+ *
+ * The general TDM waveform generation is as follows:
+ *
+ * \anchor asfdoc_sam0_i2s_module_tdm_wave_diagram
+ * \image html tdm_wave.svg "TDM Waveform Generation"
+ *
+ * Some other settings could also be found to set up clock, data formatting and
+ * pin multiplexer (MUX).
+ * Refer to \ref i2s_clock_unit_config "Clock Unit Configurations"
+ * and \ref i2s_serializer_config "Serializer Configurations" for more
+ * details.
+ *
+ * Following is examples for different application use cases.
+ *
+ * See \ref asfdoc_sam0_i2s_module_tdm_timeslot_example_diagram "here" for
+ * the Time Slot Application connection and waveform example.
+ *
+ * \anchor asfdoc_sam0_i2s_module_tdm_timeslot_example_diagram
+ * \image html tdm_timeslot_example.svg "Codec Example Diagram"
+ *
+ * See \ref asfdoc_sam0_i2s_module_tdm_codec_example_diagram "here" for the
+ * Codec Application connection and waveform example.
+ *
+ * \anchor asfdoc_sam0_i2s_module_tdm_codec_example_diagram
+ * \image html tdm_codec_example.svg "Time Slot Example Diagram"
+ *
+ * \subsubsection asfdoc_sam0_i2s_module_overview_data_pdm PDM Reception
+ * The I<SUP>2</SUP>S Serializer integrates PDM reception feature, to use this feature,
+ * simply select PDM2 mode in Serializer configuration. In PDM2 mode, it assumes
+ * two microphones are input for stereo stream. The left microphone bits will
+ * be stored in lower half and right microphone bits in upper half of the data
+ * word, like in compact stereo format.
+ *
+ * See \ref asfdoc_sam0_i2s_module_pdm_example_diagram "following figure" for an
+ * example of PDM Microphones Application with both left and right channel
+ * microphone connected.
+ *
+ * \anchor asfdoc_sam0_i2s_module_pdm_example_diagram
+ * \image html pdm_example.svg "Time PDM2 Example Diagram"
+ *
+ * \subsubsection asfdoc_sam0_i2s_module_overview_data_fmt MONO and Compact Data
+ * The I<SUP>2</SUP>S Serializer can accept some pre-defined data format and generates
+ * the data stream in specified way.
+ *
+ * When transmitting data, the Serializer can work in MONO mode: assum input
+ * is single channel mono data on left channel and copy it to right channel
+ * automatically.
+ *
+ * Also the I<SUP>2</SUP>S Serializer can support compact stereo data word. The data word
+ * size of the Serializer can be set to \ref I2S_DATA_SIZE_16BIT_COMPACT
+ * "16-bit compact" or \ref I2S_DATA_SIZE_8BIT_COMPACT "8-bit compact", with
+ * these option I<SUP>2</SUP>S Serializer will compact left channel data and right channel
+ * data together, the left channel data will take lower bytes and right channel
+ * data take higher bytes.
+ *
+ * \subsection asfdoc_sam0_i2s_module_overview_loop Loop-back Mode
+ * The I<SUP>2</SUP>S can be configured to loop back the Transmitter to Receiver. In this
+ * mode Serializer's input will be connected to another Serializer's output
+ * internally.
+ *
+ * \subsection asfdoc_sam0_i2s_module_overview_sleep Sleep Modes
+ * The I<SUP>2</SUP>S will continue to operate in any sleep mode, where the selected source
+ * clocks are running.
+ *
+ * \section asfdoc_sam0_i2s_special_considerations Special Considerations
+ *
+ * There is no special considerations for I<SUP>2</SUP>S module.
+ *
+ * \section asfdoc_sam0_i2s_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_i2s_extra. This includes:
+ *  - \ref asfdoc_sam0_i2s_extra_acronyms
+ *  - \ref asfdoc_sam0_i2s_extra_dependencies
+ *  - \ref asfdoc_sam0_i2s_extra_errata
+ *  - \ref asfdoc_sam0_i2s_extra_history
+ *
+ * \section asfdoc_sam0_i2s_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_i2s_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_i2s_api_overview API Overview
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system.h>
+
+#if I2S_CALLBACK_MODE == true
+#  include <system_interrupt.h>
+
+#if !defined(__DOXYGEN__)
+extern struct i2s_module *_i2s_instances[I2S_INST_NUM];
+#endif
+
+/** Forward definition of the device instance */
+struct i2s_module;
+
+/** Type of the callback functions. */
+typedef void (*i2s_serializer_callback_t)
+		(struct i2s_module *const module);
+
+/**
+ * \brief I<SUP>2</SUP>S Serializer Callback enum
+ */
+enum i2s_serializer_callback {
+	/** Callback for buffer read/write finished */
+	I2S_SERIALIZER_CALLBACK_BUFFER_DONE,
+	/** Callback for Serializer overrun/underrun */
+	I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN,
+#  if !defined(__DOXYGEN__)
+	I2S_SERIALIZER_CALLBACK_N
+#  endif
+};
+
+#endif /* #if I2S_CALLBACK_MODE == true */
+
+/**
+ * \name Module Status Flags
+ *
+ * I<SUP>2</SUP>S status flags, returned by \ref i2s_get_status() and cleared by
+ * \ref i2s_clear_status().
+ *
+ * @{
+ */
+
+/** Module Serializer x (0~1) Transmit Underrun. */
+#define I2S_STATUS_TRANSMIT_UNDERRUN(x)     (1u << ((x)+0))
+/** Module Serializer x (0~1) is ready to accept new data to be transmitted. */
+#define I2S_STATUS_TRANSMIT_READY(x)        (1u << ((x)+2))
+/** Module Serializer x (0~1) Receive Overrun. */
+#define I2S_STATUS_RECEIVE_OVERRUN(x)       (1u << ((x)+4))
+/** Module Serializer x (0~1) has received a new data. */
+#define I2S_STATUS_RECEIVE_READY(x)         (1u << ((x)+6))
+/** Module is busy on synchronization. */
+#define I2S_STATUS_SYNC_BUSY                (1u << 8)
+
+/** @} */
+
+/**
+ * Master Clock (MCK) source selection.
+ */
+enum i2s_master_clock_source {
+	/** Master Clock (MCK) is from general clock */
+	I2S_MASTER_CLOCK_SOURCE_GCLK,
+	/** Master Clock (MCK) is from MCK input pin */
+	I2S_MASTER_CLOCK_SOURCE_MCKPIN
+};
+
+/**
+ * Serial Clock (SCK) source selection.
+ */
+enum i2s_serial_clock_source {
+	/** Serial Clock (SCK) is divided from Master Clock */
+	I2S_SERIAL_CLOCK_SOURCE_MCKDIV,
+	/** Serial Clock (SCK) is input from SCK input pin */
+	I2S_SERIAL_CLOCK_SOURCE_SCKPIN
+};
+
+/**
+ * Data delay from Frame Sync (FS).
+ */
+enum i2s_data_delay {
+	/** Left Justified (no delay) */
+	I2S_DATA_DELAY_0,
+	/** I<SUP>2</SUP>S data delay (1-bit delay) */
+	I2S_DATA_DELAY_1,
+	/** Left Justified (no delay) */
+	I2S_DATA_DELAY_LEFT_JUSTIFIED = I2S_DATA_DELAY_0,
+	/** I<SUP>2</SUP>S data delay (1-bit delay) */
+	I2S_DATA_DELAY_I2S = I2S_DATA_DELAY_1
+};
+
+/**
+ * Frame Sync (FS) source.
+ */
+enum i2s_frame_sync_source {
+	/** Frame Sync (FS) is divided from I<SUP>2</SUP>S Serial Clock */
+	I2S_FRAME_SYNC_SOURCE_SCKDIV,
+	/** Frame Sync (FS) is input from FS input pin */
+	I2S_FRAME_SYNC_SOURCE_FSPIN
+};
+
+/**
+ * Frame Sync (FS) output pulse width.
+ */
+enum i2s_frame_sync_width {
+	/** Frame Sync (FS) Pulse is one slot width */
+	I2S_FRAME_SYNC_WIDTH_SLOT,
+	/** Frame Sync (FS) Pulse is half a frame width */
+	I2S_FRAME_SYNC_WIDTH_HALF_FRAME,
+	/** Frame Sync (FS) Pulse is one bit width */
+	I2S_FRAME_SYNC_WIDTH_BIT,
+	/** 1-bit wide Frame Sync (FS) per Data sample, only used when Data transfer
+	 *  is requested */
+	I2S_FRAME_SYNC_WIDTH_BURST
+};
+
+/**
+ * Time Slot Size in number of I<SUP>2</SUP>S serial clocks (bits).
+ */
+enum i2s_slot_size {
+	/** 8-bit slot */
+	I2S_SLOT_SIZE_8_BIT,
+	/** 16-bit slot */
+	I2S_SLOT_SIZE_16_BIT,
+	/** 24-bit slot */
+	I2S_SLOT_SIZE_24_BIT,
+	/** 32-bit slot */
+	I2S_SLOT_SIZE_32_BIT
+};
+
+/**
+ * DMA channels usage for I<SUP>2</SUP>S.
+ */
+enum i2s_dma_usage {
+	/** Single DMA channel for all I<SUP>2</SUP>S channels */
+	I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL,
+	/** One DMA channel per data channel */
+	I2S_DMA_USE_ONE_CHANNEL_PER_DATA_CHANNEL
+};
+
+/**
+ * I<SUP>2</SUP>S data format, to extend mono data to two channels.
+ */
+enum i2s_data_format {
+	/** Normal mode, keep data to its right channel */
+	I2S_DATA_FORMAT_STEREO,
+	/** Assume input is mono data for left channel, the data is duplicated to
+	 *  right channel */
+	I2S_DATA_FORMAT_MONO
+};
+
+/**
+ * I<SUP>2</SUP>S data bit order.
+ */
+enum i2s_bit_order {
+	/** Transfer Data Most Significant Bit first 
+	 * (Default for I<SUP>2</SUP>S protocol) 
+	 */
+	I2S_BIT_ORDER_MSB_FIRST,
+	/** Transfer Data Least Significant Bit first */
+	I2S_BIT_ORDER_LSB_FIRST
+};
+
+/**
+ * I<SUP>2</SUP>S data bit padding.
+ */
+enum i2s_bit_padding {
+	/** Padding with 0 */
+	I2S_BIT_PADDING_0,
+	/** Padding with 1 */
+	I2S_BIT_PADDING_1,
+	/** Padding with MSBit */
+	I2S_BIT_PADDING_MSB,
+	/** Padding with LSBit */
+	I2S_BIT_PADDING_LSB,
+};
+
+/**
+ * I<SUP>2</SUP>S data word adjust.
+ */
+enum i2s_data_adjust {
+	/** Data is right adjusted in word */
+	I2S_DATA_ADJUST_RIGHT,
+	/** Data is left adjusted in word */
+	I2S_DATA_ADJUST_LEFT
+};
+
+/**
+ * I<SUP>2</SUP>S data word size.
+ */
+enum i2s_data_size {
+	/** 32-bit */
+	I2S_DATA_SIZE_32BIT,
+	/** 24-bit */
+	I2S_DATA_SIZE_24BIT,
+	/** 20-bit */
+	I2S_DATA_SIZE_20BIT,
+	/** 18-bit */
+	I2S_DATA_SIZE_18BIT,
+	/** 16-bit */
+	I2S_DATA_SIZE_16BIT,
+	/** 16-bit compact stereo */
+	I2S_DATA_SIZE_16BIT_COMPACT,
+	/** 8-bit */
+	I2S_DATA_SIZE_8BIT,
+	/** 8-bit compact stereo */
+	I2S_DATA_SIZE_8BIT_COMPACT
+};
+
+/**
+ * I<SUP>2</SUP>S data slot adjust.
+ */
+enum i2s_slot_adjust {
+	/** Data is right adjusted in slot */
+	I2S_SLOT_ADJUST_RIGHT,
+	/** Data is left adjusted in slot */
+	I2S_SLOT_ADJUST_LEFT
+};
+
+/**
+ * I<SUP>2</SUP>S data padding.
+ */
+enum i2s_data_padding {
+	/** Padding 0 in case of under-run */
+	I2S_DATA_PADDING_0,
+	/** Padding last data in case of under-run */
+	I2S_DATA_PADDING_SAME_AS_LAST,
+	/** Padding last data in case of under-run
+	 *  (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */
+	I2S_DATA_PADDING_LAST = I2S_DATA_PADDING_SAME_AS_LAST,
+	/** Padding last data in case of under-run
+	 *  (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */
+	I2S_DATA_PADDING_SAME = I2S_DATA_PADDING_SAME_AS_LAST
+};
+
+/**
+ * I<SUP>2</SUP>S line default value when slot disabled.
+ */
+enum i2s_line_default_state {
+	/** Output default value is 0 */
+	I2S_LINE_DEFAULT_0,
+	/** Output default value is 1 */
+	I2S_LINE_DEFAULT_1,
+	/** Output default value is high impedance */
+	I2S_LINE_DEFAULT_HIGH_IMPEDANCE = 3,
+	/** Output default value is high impedance
+	 *  (abbr. \c I2S_LINE_DEFAULT_HIGH_IMPEDANCE) */
+	I2S_LINE_DEFAULT_HIZ = I2S_LINE_DEFAULT_HIGH_IMPEDANCE
+};
+
+/**
+ * I<SUP>2</SUP>S Serializer mode.
+ */
+enum i2s_serializer_mode {
+	/** Serializer is used to receive data */
+	I2S_SERIALIZER_RECEIVE,
+	/** Serializer is used to transmit data */
+	I2S_SERIALIZER_TRANSMIT,
+	/** Serializer is used to receive PDM data on each clock edge */
+	I2S_SERIALIZER_PDM2
+};
+
+/**
+ * I<SUP>2</SUP>S clock unit selection.
+ */
+enum i2s_clock_unit {
+	/** Clock Unit channel 0 */
+	I2S_CLOCK_UNIT_0,
+	/** Clock Unit channel 1 */
+	I2S_CLOCK_UNIT_1,
+	/** Number of Clock Unit channels */
+	I2S_CLOCK_UNIT_N
+};
+
+/**
+ * I<SUP>2</SUP>S Serializer selection.
+ */
+enum i2s_serializer {
+	/** Serializer channel 0 */
+	I2S_SERIALIZER_0,
+	/** Serializer channel 1 */
+	I2S_SERIALIZER_1,
+	/** Number of Serializer channels */
+	I2S_SERIALIZER_N
+};
+
+
+/**
+ * Configure for I<SUP>2</SUP>S pin.
+ */
+struct i2s_pin_config {
+	/** GPIO index to access the pin */
+	uint8_t gpio;
+	/** Pin function MUX */
+	uint8_t mux;
+	/** Enable this pin for I<SUP>2</SUP>S module */
+	bool enable;
+};
+
+/**
+ * Configure for I<SUP>2</SUP>S clock (SCK).
+ */
+struct i2s_clock_config {
+	/** Divide generic clock to master clock output (1~32, 0,1 means no div) */
+	uint8_t mck_out_div;
+	/** Divide generic clock to serial clock (1~32, 0,1 means no div) */
+	uint8_t sck_div;
+	/** Clock source selection */
+	enum gclk_generator gclk_src;
+	/** Master clock source selection: generated or input from pin */
+	enum i2s_master_clock_source mck_src;
+	/** Serial clock source selection: generated or input from pin */
+	enum i2s_serial_clock_source sck_src;
+	/** Invert master clock output */
+	bool mck_out_invert;
+	/** Invert serial clock output */
+	bool sck_out_invert;
+	/** Generate MCK clock output */
+	bool mck_out_enable;
+};
+
+/**
+ * Configure for I<SUP>2</SUP>S frame sync (FS).
+ */
+struct i2s_frame_sync_config {
+	/** Frame Sync (FS) generated or input from pin */
+	enum i2s_frame_sync_source source;
+	/** Frame Sync (FS) width */
+	enum i2s_frame_sync_width width;
+	/** Invert Frame Sync (FS) signal before use */
+	bool invert_use;
+	/** Invert Frame Sync (FS) signal before output */
+	bool invert_out;
+};
+
+/**
+ * Configure for I<SUP>2</SUP>S frame.
+ */
+struct i2s_frame_config {
+	/** Number of slots in a frame (1~8, 0,1 means minimum 1) */
+	uint8_t number_slots;
+	/** Size of each slot in frame */
+	enum i2s_slot_size slot_size;
+	/** Data delay from Frame Sync (FS) to first data bit */
+	enum i2s_data_delay data_delay;
+	/** Frame sync (FS) */
+	struct i2s_frame_sync_config frame_sync;
+};
+
+/**
+ * Configure for I<SUP>2</SUP>S clock unit.
+ */
+struct i2s_clock_unit_config {
+	/** Configure clock generation */
+	struct i2s_clock_config clock;
+	/** Configure frame generation */
+	struct i2s_frame_config frame;
+
+	/** Configure master clock pin */
+	struct i2s_pin_config mck_pin;
+	/** Configure serial clock pin */
+	struct i2s_pin_config sck_pin;
+	/** Configure frame sync pin */
+	struct i2s_pin_config fs_pin;
+};
+
+/**
+ * Configure for I<SUP>2</SUP>S Serializer.
+ */
+struct i2s_serializer_config {
+	/** Configure Serializer data pin */
+	struct i2s_pin_config data_pin;
+
+	/** Set to \c true to loop-back output to input pin for test */
+	bool loop_back;
+
+	/** Set to \c true to assumes mono input and duplicate it (left channel) to
+	 *  right channel */
+	bool mono_mode;
+
+	/** Disable data slot */
+	bool disable_data_slot[8];
+
+	/** Set to \c true to transfer LSB first, \c false to transfer MSB first */
+	bool transfer_lsb_first;
+	/** Data Word Formatting Adjust,
+	 *  set to \c true to adjust bits in word to left */
+	bool data_adjust_left_in_word;
+	/** Data Slot Formatting Adjust,
+	 *  set to \c true to adjust words in slot to left */
+	bool data_adjust_left_in_slot;
+
+	/** Data Word Size */
+	enum i2s_data_size data_size;
+	/** Data Formatting Bit Extension */
+	enum i2s_bit_padding bit_padding;
+	/** Data padding when under-run */
+	enum i2s_data_padding data_padding;
+
+	/** DMA usage */
+	enum i2s_dma_usage dma_usage;
+
+	/** Clock unit selection */
+	enum i2s_clock_unit clock_unit;
+
+	/** Line default state where slot is disabled */
+	enum i2s_line_default_state line_default_state;
+
+	/** Serializer Mode */
+	enum i2s_serializer_mode mode;
+};
+
+/**
+ * \brief I<SUP>2</SUP>S Serializer instance struct.
+ */
+struct i2s_serializer_module {
+
+#if I2S_CALLBACK_MODE == true
+	/** Callbacks list for Serializer */
+	i2s_serializer_callback_t callback[I2S_SERIALIZER_CALLBACK_N];
+
+	/** Job buffer */
+	void *job_buffer;
+	/** Requested data words to read/write */
+	uint32_t requested_words;
+	/** Transferred data words for read/write */
+	uint32_t transferred_words;
+
+	/** Callback mask for registered callbacks */
+	uint8_t registered_callback_mask;
+	/** Callback mask for enabled callbacks */
+	uint8_t enabled_callback_mask;
+
+	/** Status of the ongoing or last transfer job */
+	enum status_code job_status;
+#endif
+
+	/** Serializer mode */
+	enum i2s_serializer_mode mode;
+	/** Serializer data word size */
+	enum i2s_data_size data_size;
+};
+
+/**
+ * \brief I<SUP>2</SUP>S Software Module instance struct.
+ */
+struct i2s_module {
+	/** Module HW register access base */
+	I2s *hw;
+
+	/** Module Serializer used */
+	struct i2s_serializer_module serializer[2];
+};
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false If the module has completed synchronization
+ * \retval true If the module synchronization is ongoing
+ */
+static inline bool i2s_is_syncing(
+		const struct i2s_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return (module_inst->hw->SYNCBUSY.reg > 0);
+}
+
+/**
+ * \name Driver Initialization
+ * @{
+ */
+
+enum status_code i2s_init(
+		struct i2s_module *const module_inst,
+		I2s *hw);
+
+/** @} */
+
+/**
+ * \name Enable/Disable/Reset
+ * @{
+ */
+
+/**
+ * \brief Enable the I<SUP>2</SUP>S module.
+ *
+ * Enables a I<SUP>2</SUP>S module that has been previously initialized.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void i2s_enable(const struct i2s_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) {
+		/* Sync wait */
+	}
+	module_inst->hw->CTRLA.reg |= I2S_SYNCBUSY_ENABLE;
+}
+
+/**
+ * \brief Disables the I<SUP>2</SUP>S module.
+ *
+ * Disables a I<SUP>2</SUP>S module.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void i2s_disable(const struct i2s_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) {
+		/* Sync wait */
+	}
+
+	module_inst->hw->INTENCLR.reg = I2S_INTENCLR_MASK;
+	module_inst->hw->INTFLAG.reg = I2S_INTFLAG_MASK;
+	module_inst->hw->CTRLA.reg &= ~I2S_SYNCBUSY_ENABLE;
+}
+
+/**
+ * \brief Resets the I<SUP>2</SUP>S module.
+ *
+ * Resets the I<SUP>2</SUP>S module, restoring all hardware module registers to their
+ * default values and disabling the module. The I<SUP>2</SUP>S module will not be
+ * accessible while the reset is being performed.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ */
+static inline void i2s_reset(const struct i2s_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Disable the module if it is running */
+	if (module_inst->hw->CTRLA.reg & I2S_CTRLA_ENABLE) {
+		i2s_disable(module_inst);
+		while (i2s_is_syncing(module_inst)) {
+			/* Sync wait */
+		}
+	}
+	/* Reset the HW module */
+	module_inst->hw->CTRLA.reg = I2S_CTRLA_SWRST;
+}
+
+/** @} */
+
+/**
+ * \name Clock Unit Initialization and Configuration
+ * @{
+ */
+
+/**
+ * \brief Initializes config with predefined default values for I<SUP>2</SUP>S clock unit.
+ *
+ * This function will initialize a given I<SUP>2</SUP>S Clock Unit configuration structure
+ * to a set of known default values. This function should be called on any new
+ * instance of the configuration structures before being modified by the user
+ * application.
+ *
+ * The default configuration is as follows:
+ * - The clock unit does not generate output clocks (MCK, SCK, and FS)
+ * - The pins (MCK, SCK, and FS) and MUX configurations are not set
+ *
+ * \param[out]  config  Pointer to a I<SUP>2</SUP>S module clock unit configuration struct
+ *                      to set
+ */
+static inline void i2s_clock_unit_get_config_defaults(
+		struct i2s_clock_unit_config *const config)
+{
+	Assert(config);
+
+	config->clock.mck_out_enable = false;
+	config->clock.gclk_src = GCLK_GENERATOR_0;
+
+	config->clock.mck_src = I2S_MASTER_CLOCK_SOURCE_GCLK;
+	config->clock.mck_out_div = 1;
+	config->clock.mck_out_invert = false;
+
+	config->clock.sck_src = I2S_SERIAL_CLOCK_SOURCE_MCKDIV;
+	config->clock.sck_div = 1;
+	config->clock.sck_out_invert = false;
+
+	config->frame.number_slots = 1;
+	config->frame.slot_size = I2S_SLOT_SIZE_32_BIT;
+	config->frame.data_delay = I2S_DATA_DELAY_I2S;
+
+	config->frame.frame_sync.source = I2S_FRAME_SYNC_SOURCE_SCKDIV;
+	config->frame.frame_sync.width = I2S_FRAME_SYNC_WIDTH_HALF_FRAME;
+	config->frame.frame_sync.invert_use = false;
+	config->frame.frame_sync.invert_out = false;
+
+	config->mck_pin.enable = false;
+	config->mck_pin.mux = 0;
+	config->mck_pin.gpio = 0;
+
+	config->sck_pin.enable = false;
+	config->sck_pin.mux = 0;
+	config->sck_pin.gpio = 0;
+
+	config->fs_pin.enable = false;
+	config->fs_pin.mux = 0;
+	config->fs_pin.gpio = 0;
+}
+
+enum status_code i2s_clock_unit_set_config(
+		struct i2s_module *const module_inst,
+		const enum i2s_clock_unit clock_unit,
+		const struct i2s_clock_unit_config *config);
+
+/** @} */
+
+
+/**
+ * \name Clock Unit Enable/Disable
+ * @{
+ */
+
+/**
+ * \brief Enable the Specified Clock Unit of I<SUP>2</SUP>S module.
+ *
+ * Enables a Clock Unit in I<SUP>2</SUP>S module that has been previously initialized.
+ *
+ * \param[in] module_inst   Pointer to the software module instance struct
+ * \param[in] clock_unit    I<SUP>2</SUP>S Clock Unit to enable
+ */
+static inline void i2s_clock_unit_enable(
+		const struct i2s_module *const module_inst,
+		const enum i2s_clock_unit clock_unit)
+{
+	uint32_t cken_bit;
+
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	cken_bit = I2S_CTRLA_CKEN0 << clock_unit;
+
+	while (module_inst->hw->SYNCBUSY.reg & cken_bit) {
+		/* Sync wait */
+	}
+	module_inst->hw->CTRLA.reg |= cken_bit;
+}
+
+/**
+ * \brief Disable the Specified Clock Unit of I<SUP>2</SUP>S module.
+ *
+ * Disables a Clock Unit in I<SUP>2</SUP>S module that has been previously initialized.
+ *
+ * \param[in]  module_inst  Pointer to the software module instance struct
+ * \param[in] clock_unit    I<SUP>2</SUP>S Clock Unit to disable
+ */
+static inline void i2s_clock_unit_disable(
+		const struct i2s_module *const module_inst,
+		const enum i2s_clock_unit clock_unit)
+{
+	uint32_t cken_bit;
+
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	cken_bit = I2S_CTRLA_CKEN0 << clock_unit;
+
+	while (module_inst->hw->SYNCBUSY.reg & cken_bit) {
+		/* Sync wait */
+	}
+	module_inst->hw->CTRLA.reg &= ~cken_bit;
+}
+
+/** @} */
+
+
+/**
+ * \name Serializer Initialization and Configuration
+ * @{
+ */
+
+/**
+ * \brief Initializes config with predefined default values for I<SUP>2</SUP>S Serializer.
+ *
+ * This function will initialize a given I<SUP>2</SUP>S Clock Unit configuration structure
+ * to a set of known default values. This function should be called on any new
+ * instance of the configuration structures before being modified by the user
+ * application.
+ *
+ * The default configuration is as follows:
+ * - Output data does not internally loopback to input line
+ * - Does not extend mono data (left channel) to right channel
+ * - None of the data slot is disabled
+ * - MSB of I<SUP>2</SUP>S data is transferred first
+ * - In data word data is adjusted right
+ * - In slot data word is adjusted left
+ * - The data size is 16-bit width
+ * - I<SUP>2</SUP>S will padd 0 to not defined bits
+ * - I<SUP>2</SUP>S will padd 0 to not defined words
+ * - I<SUP>2</SUP>S will use single DMA channel for all data channels
+ * - I<SUP>2</SUP>S will use clock unit 0 to serve as clock
+ * - The default data line state is 0, when there is no data
+ * - I<SUP>2</SUP>S will transmit data to output line
+ * - The data pin and MUX configuration are not set
+ *
+ * \param[out]  config  Pointer to a I<SUP>2</SUP>S module Serializer configuration struct
+ *                      to set
+ */
+static inline void i2s_serializer_get_config_defaults(
+		struct i2s_serializer_config *const config)
+{
+	config->loop_back = false;
+
+	config->mono_mode = false;
+
+	config->disable_data_slot[0] = false;
+	config->disable_data_slot[1] = false;
+	config->disable_data_slot[2] = false;
+	config->disable_data_slot[3] = false;
+	config->disable_data_slot[4] = false;
+	config->disable_data_slot[5] = false;
+	config->disable_data_slot[6] = false;
+	config->disable_data_slot[7] = false;
+
+	config->transfer_lsb_first = false;
+	config->data_adjust_left_in_word = false;
+	config->data_adjust_left_in_slot = true;
+
+	config->data_size = I2S_DATA_SIZE_16BIT;
+
+	config->bit_padding = I2S_BIT_PADDING_0;
+	config->data_padding = I2S_DATA_PADDING_0;
+
+	config->dma_usage = I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL;
+
+	config->clock_unit = I2S_CLOCK_UNIT_0;
+
+	config->line_default_state = I2S_LINE_DEFAULT_0;
+
+	config->mode = I2S_SERIALIZER_TRANSMIT;
+
+	config->data_pin.enable = false;
+	config->data_pin.gpio = 0;
+	config->data_pin.mux = 0;
+}
+
+enum status_code i2s_serializer_set_config(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const struct i2s_serializer_config *config);
+/** @} */
+
+/**
+ * \name Serializer Enable/Disable
+ * @{
+ */
+
+/**
+ * \brief Enable the Specified Serializer of I<SUP>2</SUP>S module.
+ *
+ * Enables a Serializer in I<SUP>2</SUP>S module that has been previously initialized.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    I<SUP>2</SUP>S Serializer to enable
+ */
+static inline void i2s_serializer_enable(
+		const struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer)
+{
+	uint32_t seren_bit;
+
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	seren_bit = I2S_CTRLA_SEREN0 << serializer;
+
+	while (module_inst->hw->SYNCBUSY.reg & seren_bit) {
+		/* Sync wait */
+	}
+	module_inst->hw->CTRLA.reg |= seren_bit;
+}
+
+/**
+ * \brief Disable the Specified Serializer of I<SUP>2</SUP>S module.
+ *
+ * Disables a Serializer in I<SUP>2</SUP>S module that has been previously initialized.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    I<SUP>2</SUP>S Serializer to disable
+ */
+static inline void i2s_serializer_disable(
+		const struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer)
+{
+	uint32_t seren_bit;
+
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	seren_bit = I2S_CTRLA_SEREN0 << serializer;
+
+	while (module_inst->hw->SYNCBUSY.reg & seren_bit) {
+		/* Sync wait */
+	}
+	module_inst->hw->CTRLA.reg &= ~seren_bit;
+}
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+uint32_t i2s_get_status(
+		const struct i2s_module *const module_inst);
+
+void i2s_clear_status(
+		const struct i2s_module *const module_inst,
+		uint32_t status);
+
+
+enum status_code i2s_enable_status_interrupt(
+		struct i2s_module *const module_inst,
+		uint32_t status);
+
+void i2s_disable_status_interrupt(
+		struct i2s_module *const module_inst,
+		uint32_t status);
+
+/** @}*/
+
+/**
+ * \name Data Read/Write
+ * @{
+ */
+
+/**
+ * \brief Write a data word to the specified Serializer of I<SUP>2</SUP>S module
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    The Serializer to write to
+ * \param[in]  data          The data to write
+ *
+ */
+static inline void i2s_serializer_write_wait(
+		const struct i2s_module *const module_inst,
+		enum i2s_serializer serializer,
+		uint32_t data)
+{
+	uint32_t sync_bit, ready_bit;
+
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	ready_bit = I2S_INTFLAG_TXRDY0 << serializer;
+	while (!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+		/* Wait until ready to transmit */
+	}
+	sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
+	while (module_inst->hw->SYNCBUSY.reg & sync_bit) {
+		/* Wait sync */
+	}
+	/* Write data */
+	module_inst->hw->DATA[serializer].reg = data;
+	module_inst->hw->INTFLAG.reg = ready_bit;
+}
+
+/**
+ * \brief Read a data word from the specified Serializer of I<SUP>2</SUP>S module
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    The Serializer to read
+ */
+static inline uint32_t i2s_serializer_read_wait(
+		const struct i2s_module *const module_inst,
+		enum i2s_serializer serializer)
+{
+	uint32_t sync_bit, ready_bit;
+	uint32_t data;
+
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	ready_bit = I2S_INTFLAG_RXRDY0 << serializer;
+	while (!(module_inst->hw->INTFLAG.reg & ready_bit)) {
+		/* Wait until ready to transmit */
+	}
+	sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
+	while (module_inst->hw->SYNCBUSY.reg & sync_bit) {
+		/* Wait sync */
+	}
+	/* Read data */
+	data = module_inst->hw->DATA[serializer].reg;
+	module_inst->hw->INTFLAG.reg = ready_bit;
+	return data;
+}
+
+enum status_code i2s_serializer_write_buffer_wait(
+		const struct i2s_module *const module_inst,
+		enum i2s_serializer serializer,
+		void *buffer, uint32_t size);
+
+enum status_code i2s_serializer_read_buffer_wait(
+		const struct i2s_module *const module_inst,
+		enum i2s_serializer serializer,
+		void *buffer, uint32_t size);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+
+/**
+ * \page asfdoc_sam0_i2s_extra Extra Information for I2S Driver
+ *
+ * \section asfdoc_sam0_i2s_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>I<SUP>2</SUP>S, IIS</td>
+ *      <td>Inter-IC Sound Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MCK</td>
+ *      <td>Master Clock</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SCK</td>
+ *      <td>Serial Clock</td>
+ *  </tr>
+ *  <tr>
+ *      <td>FS</td>
+ *      <td>Frame Sync</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SD</td>
+ *      <td>Serial Data</td>
+ *  </tr>
+ *  <tr>
+ *      <td>ADC</td>
+ *      <td>Analog-to-Digital Converter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DAC</td>
+ *      <td>Digital-to-Analog Converter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>TDM</td>
+ *      <td>Time Division Multiplexed</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PDM</td>
+ *      <td>Pulse Density Modulation</td>
+ *  </tr>
+ *  <tr>
+ *      <td>LSB</td>
+ *      <td>Least Significant Bit</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MSB</td>
+ *      <td>Most Significant Bit</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DSP</td>
+ *      <td>Digital Signal Processor</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_i2s_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_i2s_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_i2s_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_i2s_exqsg Examples for I2S Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_i2s_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_i2s_basic_use_case
+ * \if I2S_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_i2s_callback_use_case
+ * \endif
+ *  - \subpage asfdoc_sam0_i2s_dma_use_case
+ *
+ * \page asfdoc_sam0_i2s_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42255B</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM DA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42255A</td>
+ *		<td>01/2014</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* #ifndef I2S_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.c
new file mode 100644
index 0000000000..fae543c119
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.c
@@ -0,0 +1,392 @@
+/**
+ * \file
+ *
+ * \brief SAM I<SUP>2</SUP>S - Inter-IC Sound Controller
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2s_callback.h"
+
+struct i2s_module *_i2s_instances[I2S_INST_NUM];
+
+static void _i2s_interrupt_handler(const uint8_t instance)
+{
+	struct i2s_module *module = _i2s_instances[instance];
+	struct i2s_serializer_module *data_module;
+
+	/* Get interrupt flags */
+	uint32_t intflag = module->hw->INTFLAG.reg;
+	uint32_t inten = intflag & module->hw->INTENSET.reg;
+	uint32_t run_flags = (I2S_INTFLAG_TXUR0 | I2S_INTFLAG_RXOR0);
+	uint32_t ready_flags = (I2S_INTFLAG_TXRDY0 | I2S_INTFLAG_RXRDY0);
+	uint32_t call_mask;
+	uint8_t serializer;
+
+	for (serializer = 0; serializer < 2; serializer ++) {
+		data_module = &module->serializer[serializer];
+		call_mask = data_module->registered_callback_mask &
+				data_module->enabled_callback_mask;
+
+		if (intflag & (run_flags | ready_flags)) {
+			/* Serializer Tx ready */
+			if ((I2S_INTFLAG_TXRDY0 << serializer) & inten) {
+
+				if (data_module->transferred_words <
+					data_module->requested_words) {
+
+					/* Write data word */
+					while (module->hw->SYNCBUSY.reg &
+						(I2S_SYNCBUSY_DATA0 << serializer)) {
+						/* Wait sync */
+					}
+					switch(data_module->data_size) {
+					case I2S_DATA_SIZE_32BIT:
+					case I2S_DATA_SIZE_24BIT:
+					case I2S_DATA_SIZE_20BIT:
+					case I2S_DATA_SIZE_18BIT:
+						module->hw->DATA[serializer].reg =
+							((uint32_t*)data_module->job_buffer) \
+								[data_module->transferred_words];
+						break;
+					case I2S_DATA_SIZE_16BIT:
+					case I2S_DATA_SIZE_16BIT_COMPACT:
+						module->hw->DATA[serializer].reg =
+							((uint16_t*)data_module->job_buffer) \
+								[data_module->transferred_words];
+						break;
+					default:
+						module->hw->DATA[serializer].reg =
+							((uint8_t*)data_module->job_buffer) \
+								[data_module->transferred_words];
+					}
+					/* Clear interrupt status */
+					module->hw->INTFLAG.reg = I2S_INTFLAG_TXRDY0 << serializer;
+
+					/* Count data */
+					data_module->transferred_words ++;
+				}
+
+				/* Check if the buffer is done */
+				if (data_module->transferred_words >=
+					data_module->requested_words) {
+					/* It's done */
+					data_module->job_status = STATUS_OK;
+					/* Disable interrupt */
+					module->hw->INTENCLR.reg =
+							I2S_INTFLAG_TXRDY0 << serializer;
+					/* Invoke callback */
+					if ((1 << I2S_SERIALIZER_CALLBACK_BUFFER_DONE) &
+						call_mask) {
+						(data_module->callback \
+							[I2S_SERIALIZER_CALLBACK_BUFFER_DONE])(module);
+					}
+				}
+				return;
+			}
+			/* Serializer Rx ready */
+			if ((I2S_INTFLAG_RXRDY0 << serializer) & inten) {
+				/* Read data word */
+				switch(data_module->data_size) {
+				case I2S_DATA_SIZE_32BIT:
+				case I2S_DATA_SIZE_24BIT:
+				case I2S_DATA_SIZE_20BIT:
+				case I2S_DATA_SIZE_18BIT:
+					((uint32_t*)data_module->job_buffer) \
+							[data_module->transferred_words] =
+									module->hw->DATA[serializer].reg;
+					break;
+				case I2S_DATA_SIZE_16BIT:
+				case I2S_DATA_SIZE_16BIT_COMPACT:
+					((uint16_t*)data_module->job_buffer) \
+							[data_module->transferred_words] =
+									(uint16_t)module->hw->DATA[serializer].reg;
+					break;
+				default:
+					((uint8_t*)data_module->job_buffer) \
+							[data_module->transferred_words] =
+									(uint8_t)module->hw->DATA[serializer].reg;
+
+				}
+				/* Clear interrupt status */
+				module->hw->INTFLAG.reg = I2S_INTFLAG_RXRDY0 << serializer;
+
+				/* Count data */
+				data_module->transferred_words ++;
+
+				/* Check if the buffer is done */
+				if (data_module->transferred_words >=
+					data_module->requested_words) {
+					if (data_module->job_status == STATUS_BUSY) {
+						data_module->job_status = STATUS_OK;
+						/* Disable interrupt */
+						module->hw->INTENCLR.reg =
+								I2S_INTFLAG_RXRDY0 << serializer;
+						/* Invoke callback */
+						if ((1 << I2S_SERIALIZER_CALLBACK_BUFFER_DONE) &
+							call_mask) {
+							(data_module->callback \
+								[I2S_SERIALIZER_CALLBACK_BUFFER_DONE])(module);
+						}
+					}
+				}
+				return;
+			}
+			/* Serializer Tx undrerun or Rx overrun */
+			if (run_flags & inten) {
+				module->hw->INTFLAG.reg = I2S_INTFLAG_TXUR0 << serializer;
+				if ((1 << I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN) &
+					call_mask) {
+					(data_module->callback \
+						[I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN])(module);
+				}
+				return;
+			}
+		}
+		run_flags <<= 1;
+		ready_flags <<= 1;
+	}
+
+}
+
+/** Interrupt handler for the I<SUP>2</SUP>S module */
+void I2S_Handler(void)
+{
+	_i2s_interrupt_handler(0);
+}
+
+/**
+ * \brief Write buffer to the specified Serializer of I<SUP>2</SUP>S module
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    The serializer to write to
+ * \param[in]  buffer        The data buffer to write
+ * \param[in]  size          Number of data words to write
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The data was sent successfully
+ * \retval STATUS_ERR_DENIED   The serializer is not in transmit mode
+ * \retval STATUS_ERR_INVALID_ARG  An invalid buffer pointer was supplied
+ */
+enum status_code i2s_serializer_write_buffer_job(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const void *buffer,
+		const uint32_t size)
+{
+	struct i2s_serializer_module *data_module;
+
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(serializer < I2S_SERIALIZER_N);
+	
+	data_module = &module_inst->serializer[serializer];
+
+	/* Serializer must in transmit mode */
+	if (data_module->mode != I2S_SERIALIZER_TRANSMIT) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Buffer should be aligned */
+	switch(data_module->data_size) {
+	case I2S_DATA_SIZE_32BIT:
+	case I2S_DATA_SIZE_24BIT:
+	case I2S_DATA_SIZE_20BIT:
+	case I2S_DATA_SIZE_18BIT:
+		if ((uint32_t)buffer & 0x3) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		break;
+	case I2S_DATA_SIZE_16BIT:
+	case I2S_DATA_SIZE_16BIT_COMPACT:
+		if ((uint32_t)buffer & 0x1) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		break;
+	default:
+		break;
+	}
+
+	data_module = &module_inst->serializer[serializer];
+	if (data_module->job_status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	data_module->job_status = STATUS_BUSY;
+	data_module->requested_words = size;
+	data_module->transferred_words = 0;
+	data_module->job_buffer = (void*)buffer;
+
+	module_inst->hw->INTENSET.reg = (I2S_INTENSET_TXRDY0 << serializer);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Read from the specified Serializer of I<SUP>2</SUP>S module to a buffer
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    The serializer to write to
+ * \param[out] buffer        The buffer to fill read data
+ * \param[in]  size          Number of data words to read
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The data was sent successfully
+ * \retval STATUS_ERR_DENIED   The serializer is not in receive mode
+ * \retval STATUS_ERR_INVALID_ARG  An invalid buffer pointer was supplied
+ */
+enum status_code i2s_serializer_read_buffer_job(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		void *buffer,
+		const uint32_t size)
+{
+	struct i2s_serializer_module *data_module;
+
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(serializer < I2S_SERIALIZER_N);
+
+	data_module = &module_inst->serializer[serializer];
+
+	/* Serializer must in receive mode */
+	if (data_module->mode == I2S_SERIALIZER_TRANSMIT) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Data buffer must be aligned */
+	switch(data_module->data_size) {
+	case I2S_DATA_SIZE_32BIT:
+	case I2S_DATA_SIZE_24BIT:
+	case I2S_DATA_SIZE_20BIT:
+	case I2S_DATA_SIZE_18BIT:
+		if ((uint32_t)buffer & 0x3) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		break;
+	case I2S_DATA_SIZE_16BIT:
+	case I2S_DATA_SIZE_16BIT_COMPACT:
+		if ((uint32_t)buffer & 0x1) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		break;
+	default:
+		break;
+	}
+
+	data_module = &module_inst->serializer[serializer];
+	if (data_module->job_status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	data_module->job_status = STATUS_BUSY;
+	data_module->requested_words = size;
+	data_module->transferred_words = 0;
+	data_module->job_buffer = (void*)buffer;
+
+	module_inst->hw->INTENCLR.reg = (I2S_INTENSET_RXRDY0 << serializer);
+	module_inst->hw->INTENSET.reg = (I2S_INTENSET_RXRDY0 << serializer);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Aborts an ongoing job running on serializer
+ *
+ * Aborts an ongoing job.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    The serializer which runs the job
+ * \param[in]  job_type      Type of job to abort
+ */
+void i2s_serializer_abort_job(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const enum i2s_job_type job_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(serializer < I2S_SERIALIZER_N);
+
+	if (job_type == I2S_JOB_WRITE_BUFFER) {
+		/* Disable interrupt */
+		module_inst->hw->INTENCLR.reg = (I2S_INTENCLR_TXRDY0 << serializer);
+		/* Mark job as aborted */
+		module_inst->serializer[serializer].job_status = STATUS_ABORTED;
+	} else if (job_type == I2S_JOB_READ_BUFFER) {
+		/* Disable interrupt */
+		module_inst->hw->INTENCLR.reg = (I2S_INTENCLR_RXRDY0 << serializer);
+		/* Mark job as aborted */
+		module_inst->serializer[serializer].job_status = STATUS_ABORTED;
+	}
+}
+
+/**
+ * \brief Gets the status of a job running on serializer
+ *
+ * Gets the status of an ongoing or the last job.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  serializer    The serializer which runs the job
+ * \param[in]  job_type      Type of job to abort
+ *
+ * \return Status of the job.
+ */
+enum status_code i2s_serializer_get_job_status(
+		const struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const enum i2s_job_type job_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(serializer < I2S_SERIALIZER_N);
+
+	if (job_type == I2S_JOB_WRITE_BUFFER || job_type == I2S_JOB_READ_BUFFER) {
+		return module_inst->serializer[serializer].job_status;
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.h
new file mode 100644
index 0000000000..6fa98f3e17
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.h
@@ -0,0 +1,234 @@
+/**
+ * \file
+ *
+ * \brief SAM I2S - Inter-IC Sound Controller
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2S_CALLBACK_H_INCLUDED
+#define I2S_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_i2s_group
+ *
+ * @{
+ */
+
+#include <i2s.h>
+
+/**
+ * Enum for the possible types of I<SUP>2</SUP>S asynchronous jobs that may be issued to
+ * the driver.
+ */
+enum i2s_job_type {
+	/** Asynchronous I<SUP>2</SUP>S write from a user provided buffer */
+	I2S_JOB_WRITE_BUFFER,
+	/** Asynchronous I<SUP>2</SUP>S read into a user provided buffer */
+	I2S_JOB_READ_BUFFER
+};
+
+/**
+ * \name Callback Management
+ * @{
+ */
+
+/**
+ * \brief Registers a callback for serializer
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by for the interrupt handler to call it
+ * when the condition for the callback is met.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] serializer     The serializer that generates callback
+ * \param[in] callback_func  Pointer to callback function
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+static inline void i2s_serializer_register_callback(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const i2s_serializer_callback_t callback_func,
+		const enum i2s_serializer_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(serializer < I2S_SERIALIZER_N);
+
+	module_inst->serializer[serializer].callback[callback_type] = callback_func;
+	module_inst->serializer[serializer].registered_callback_mask |=
+			(1u << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback for serializer
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] serializer     The serializer that generates callback
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+static inline void i2s_serializer_unregister_callback(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const enum i2s_serializer_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(serializer < I2S_SERIALIZER_N);
+
+	module_inst->serializer[serializer].callback[callback_type] = NULL;
+	module_inst->serializer[serializer].registered_callback_mask &=
+			~(1u << callback_type);
+}
+
+/**
+ * \brief Enables callback for serializer
+ *
+ * Enables the callback function registered by \ref
+ * i2s_serializer_register_callback. The callback function will be called from
+ * the interrupt handler when the conditions for the callback type are met.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] serializer     The serializer that generates callback
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+static inline void i2s_serializer_enable_callback(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const enum i2s_serializer_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(serializer < I2S_SERIALIZER_N);
+
+	module_inst->serializer[serializer].enabled_callback_mask |=
+			(1u << callback_type);
+	if (I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN != callback_type) {
+		return;
+	}
+	module_inst->hw->INTENSET.reg =
+		(module_inst->serializer[serializer].mode == I2S_SERIALIZER_TRANSMIT) ?
+			(I2S_INTFLAG_TXUR0 << serializer) :
+			(I2S_INTFLAG_RXOR0 << serializer);
+}
+
+/**
+ * \brief Disables callback for Serializer
+ *
+ * Disables the callback function registered by the \ref
+ * i2s_serializer_register_callback.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] serializer     The serializer that generates callback
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+static inline void i2s_serializer_disable_callback(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const enum i2s_serializer_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(serializer < I2S_SERIALIZER_N);
+
+	module_inst->serializer[serializer].enabled_callback_mask &=
+			~(1u << callback_type);
+	if (I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN != callback_type) {
+		return;
+	}
+	module_inst->hw->INTENCLR.reg =
+		(module_inst->serializer[serializer].mode == I2S_SERIALIZER_TRANSMIT) ?
+			(I2S_INTFLAG_TXUR0 << serializer) :
+			(I2S_INTFLAG_RXOR0 << serializer);
+}
+
+/** @} */
+
+/**
+ * \name Job Management
+ *
+ * @{
+ */
+
+enum status_code i2s_serializer_write_buffer_job(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const void *buffer,
+		const uint32_t size);
+
+enum status_code i2s_serializer_read_buffer_job(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		void *buffer,
+		const uint32_t size);
+
+void i2s_serializer_abort_job(
+		struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const enum i2s_job_type job_type);
+
+enum status_code i2s_serializer_get_job_status(
+		const struct i2s_module *const module_inst,
+		const enum i2s_serializer serializer,
+		const enum i2s_job_type job_type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef I2S_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.c
new file mode 100644
index 0000000000..2a34ab1b69
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.c
@@ -0,0 +1,1116 @@
+/**
+ * \file
+ *
+ * \brief SAM Non Volatile Memory driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "nvm.h"
+#include <system.h>
+#include <system_interrupt.h>
+#include <string.h>
+
+/**
+ * \internal Internal device instance struct
+ *
+ * This struct contains information about the NVM module which is
+ * often used by the different functions. The information is loaded
+ * into the struct in the nvm_init() function.
+ */
+struct _nvm_module {
+	/** Number of bytes contained per page. */
+	uint16_t page_size;
+	/** Total number of pages in the NVM memory. */
+	uint16_t number_of_pages;
+	/** If \c false, a page write command will be issued automatically when the
+	 *  page buffer is full. */
+	bool manual_page_write;
+};
+
+/**
+ * \internal Instance of the internal device struct
+ */
+static struct _nvm_module _nvm_dev;
+
+/**
+ * \internal Pointer to the NVM MEMORY region start address
+ */
+#define NVM_MEMORY        ((volatile uint16_t *)FLASH_ADDR)
+
+/**
+ * \internal Pointer to the NVM USER MEMORY region start address
+ */
+#define NVM_USER_MEMORY   ((volatile uint16_t *)NVMCTRL_USER)
+
+
+/**
+ * \brief Sets the up the NVM hardware module based on the configuration.
+ *
+ * Writes a given configuration of an NVM controller configuration to the
+ * hardware module, and initializes the internal device struct.
+ *
+ * \param[in] config    Configuration settings for the NVM controller
+ *
+ * \note The security bit must be cleared in order successfully use this
+ *       function. This can only be done by a chip erase.
+ *
+ * \return Status of the configuration procedure.
+ *
+ * \retval STATUS_OK      If the initialization was a success
+ * \retval STATUS_BUSY    If the module was busy when the operation was attempted
+ * \retval STATUS_ERR_IO  If the security bit has been set, preventing the
+ *                        EEPROM and/or auxiliary space configuration from being
+ *                        altered
+ */
+enum status_code nvm_set_config(
+		const struct nvm_config *const config)
+{
+	/* Sanity check argument */
+	Assert(config);
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_NVMCTRL);
+#else
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_NVMCTRL);
+#endif
+
+	/* Clear error flags */
+	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+	/* Check if the module is busy */
+	if (!nvm_is_ready()) {
+		return STATUS_BUSY;
+	}
+
+#if (!SAMC20) && (!SAMC21)
+	/* Writing configuration to the CTRLB register */
+	nvm_module->CTRLB.reg =
+			NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) |
+			((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) |
+			NVMCTRL_CTRLB_RWS(config->wait_states) |
+			((config->disable_cache & 0x01) << NVMCTRL_CTRLB_CACHEDIS_Pos) |
+			NVMCTRL_CTRLB_READMODE(config->cache_readmode);
+#else
+	uint8_t cache_disable_value =  0;
+	if (config->disable_rww_cache == false) {
+		cache_disable_value = 0x02;
+	} else {
+		cache_disable_value = (config->disable_cache & 0x01);
+	}
+	/* Writing configuration to the CTRLB register */
+	nvm_module->CTRLB.reg =
+			NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) |
+			((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) |
+			NVMCTRL_CTRLB_RWS(config->wait_states) |
+			(cache_disable_value << NVMCTRL_CTRLB_CACHEDIS_Pos) |
+			NVMCTRL_CTRLB_READMODE(config->cache_readmode);
+#endif
+
+	/* Initialize the internal device struct */
+	_nvm_dev.page_size         = (8 << nvm_module->PARAM.bit.PSZ);
+	_nvm_dev.number_of_pages   = nvm_module->PARAM.bit.NVMP;
+	_nvm_dev.manual_page_write = config->manual_page_write;
+
+	/* If the security bit is set, the auxiliary space cannot be written */
+	if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB) {
+		return STATUS_ERR_IO;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Executes a command on the NVM controller.
+ *
+ * Executes an asynchronous command on the NVM controller, to perform a requested
+ * action such as an NVM page read or write operation.
+ *
+ * \note The function will return before the execution of the given command is
+ *       completed.
+ *
+ * \param[in] command    Command to issue to the NVM controller
+ * \param[in] address    Address to pass to the NVM controller in NVM memory
+ *                       space
+ * \param[in] parameter  Parameter to pass to the NVM controller, not used
+ *                       for this driver
+ *
+ * \return Status of the attempt to execute a command.
+ *
+ * \retval STATUS_OK               If the command was accepted and execution
+ *                                 is now in progress
+ * \retval STATUS_BUSY             If the NVM controller was already busy
+ *                                 executing a command when the new command
+ *                                 was issued
+ * \retval STATUS_ERR_IO           If the command was invalid due to memory or
+ *                                 security locking
+ * \retval STATUS_ERR_INVALID_ARG  If the given command was invalid or
+ *                                 unsupported
+ * \retval STATUS_ERR_BAD_ADDRESS  If the given address was invalid
+ */
+enum status_code nvm_execute_command(
+		const enum nvm_command command,
+		const uint32_t address,
+		const uint32_t parameter)
+{
+	uint32_t ctrlb_bak;
+
+	/* Check that the address given is valid  */
+	if (address > ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)
+		&& !(address >= NVMCTRL_AUX0_ADDRESS && address <= NVMCTRL_AUX1_ADDRESS )){
+#ifdef FEATURE_NVM_RWWEE
+		if (address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
+			|| address < NVMCTRL_RWW_EEPROM_ADDR){
+			return STATUS_ERR_BAD_ADDRESS;
+		}
+#else
+		return STATUS_ERR_BAD_ADDRESS;
+#endif
+	}
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	/* Turn off cache before issuing flash commands */
+	ctrlb_bak = nvm_module->CTRLB.reg;
+#if (SAMC20) || (SAMC21)
+	nvm_module->CTRLB.reg = ((ctrlb_bak &(~(NVMCTRL_CTRLB_CACHEDIS(0x2)))) 
+							| NVMCTRL_CTRLB_CACHEDIS(0x1));
+#else
+	nvm_module->CTRLB.reg = ctrlb_bak | NVMCTRL_CTRLB_CACHEDIS;
+#endif
+
+	/* Clear error flags */
+	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+	/* Check if the module is busy */
+	if (!nvm_is_ready()) {
+		/* Restore the setting */
+		nvm_module->CTRLB.reg = ctrlb_bak;
+		return STATUS_BUSY;
+	}
+
+	switch (command) {
+
+		/* Commands requiring address (protected) */
+		case NVM_COMMAND_ERASE_AUX_ROW:
+		case NVM_COMMAND_WRITE_AUX_ROW:
+
+			/* Auxiliary space cannot be accessed if the security bit is set */
+			if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB) {
+				/* Restore the setting */
+				nvm_module->CTRLB.reg = ctrlb_bak;
+				return STATUS_ERR_IO;
+			}
+
+			/* Set address, command will be issued elsewhere */
+			nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[address / 4];
+			break;
+
+		/* Commands requiring address (unprotected) */
+		case NVM_COMMAND_ERASE_ROW:
+		case NVM_COMMAND_WRITE_PAGE:
+		case NVM_COMMAND_LOCK_REGION:
+		case NVM_COMMAND_UNLOCK_REGION:
+#ifdef FEATURE_NVM_RWWEE
+		case NVM_COMMAND_RWWEE_ERASE_ROW:
+		case NVM_COMMAND_RWWEE_WRITE_PAGE:
+#endif
+
+			/* Set address, command will be issued elsewhere */
+			nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[address / 4];
+			break;
+
+		/* Commands not requiring address */
+		case NVM_COMMAND_PAGE_BUFFER_CLEAR:
+		case NVM_COMMAND_SET_SECURITY_BIT:
+		case NVM_COMMAND_ENTER_LOW_POWER_MODE:
+		case NVM_COMMAND_EXIT_LOW_POWER_MODE:
+			break;
+
+		default:
+			/* Restore the setting */
+			nvm_module->CTRLB.reg = ctrlb_bak;
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Set command */
+	nvm_module->CTRLA.reg = command | NVMCTRL_CTRLA_CMDEX_KEY;
+
+	/* Wait for the NVM controller to become ready */
+	while (!nvm_is_ready()) {
+	}
+
+	/* Restore the setting */
+	nvm_module->CTRLB.reg = ctrlb_bak;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Updates an arbitrary section of a page with new data.
+ *
+ * Writes from a buffer to a given page in the NVM memory, retaining any
+ * unmodified data already stored in the page.
+ *
+ * \note If manual write mode is enable, the write command must be executed after
+ * this function, otherwise the data will not write to NVM from page buffer.
+ *
+ * \warning This routine is unsafe if data integrity is critical; a system reset
+ *          during the update process will result in up to one row of data being
+ *          lost. If corruption must be avoided in all circumstances (including
+ *          power loss or system reset) this function should not be used.
+ *
+ * \param[in]  destination_address  Destination page address to write to
+ * \param[in]  buffer               Pointer to buffer where the data to write is
+ *                                  stored
+ * \param[in]  offset               Number of bytes to offset the data write in
+ *                                  the page
+ * \param[in]  length               Number of bytes in the page to update
+ *
+ * \return Status of the attempt to update a page.
+ *
+ * \retval STATUS_OK               Requested NVM memory page was successfully
+ *                                 read
+ * \retval STATUS_BUSY             NVM controller was busy when the operation
+ *                                 was attempted
+ * \retval STATUS_ERR_BAD_ADDRESS  The requested address was outside the
+ *                                 acceptable range of the NVM memory region
+ * \retval STATUS_ERR_INVALID_ARG  The supplied length and offset was invalid
+ */
+enum status_code nvm_update_buffer(
+		const uint32_t destination_address,
+		uint8_t *const buffer,
+		uint16_t offset,
+		uint16_t length)
+{
+	enum status_code error_code = STATUS_OK;
+	uint8_t row_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE];
+
+	/* Ensure the read does not overflow the page size */
+	if ((offset + length) > _nvm_dev.page_size) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Calculate the starting row address of the page to update */
+	uint32_t row_start_address =
+			destination_address & ~((_nvm_dev.page_size * NVMCTRL_ROW_PAGES) - 1);
+
+	/* Read in the current row contents */
+	for (uint32_t i = 0; i < NVMCTRL_ROW_PAGES; i++) {
+		do
+		{
+			error_code = nvm_read_buffer(
+					row_start_address + (i * _nvm_dev.page_size),
+					row_buffer[i], _nvm_dev.page_size);
+		} while (error_code == STATUS_BUSY);
+
+		if (error_code != STATUS_OK) {
+			return error_code;
+		}
+	}
+
+	/* Calculate the starting page in the row that is to be updated */
+	uint8_t page_in_row =
+			(destination_address % (_nvm_dev.page_size * NVMCTRL_ROW_PAGES)) /
+			_nvm_dev.page_size;
+
+	/* Update the specified bytes in the page buffer */
+	for (uint32_t i = 0; i < length; i++) {
+		row_buffer[page_in_row][offset + i] = buffer[i];
+	}
+
+	system_interrupt_enter_critical_section();
+
+	/* Erase the row */
+	do
+	{
+		error_code = nvm_erase_row(row_start_address);
+	} while (error_code == STATUS_BUSY);
+
+	if (error_code != STATUS_OK) {
+		system_interrupt_leave_critical_section();
+		return error_code;
+	}
+
+	/* Write the updated row contents to the erased row */
+	for (uint32_t i = 0; i < NVMCTRL_ROW_PAGES; i++) {
+		do
+		{
+			error_code = nvm_write_buffer(
+					row_start_address + (i * _nvm_dev.page_size),
+					row_buffer[i], _nvm_dev.page_size);
+		} while (error_code == STATUS_BUSY);
+
+		if (error_code != STATUS_OK) {
+			system_interrupt_leave_critical_section();
+			return error_code;
+		}
+	}
+
+	system_interrupt_leave_critical_section();
+
+	return error_code;
+}
+
+/**
+ * \brief Writes a number of bytes to a page in the NVM memory region.
+ *
+ * Writes from a buffer to a given page address in the NVM memory.
+ *
+ * \param[in]  destination_address  Destination page address to write to
+ * \param[in]  buffer               Pointer to buffer where the data to write is
+ *                                  stored
+ * \param[in]  length               Number of bytes in the page to write
+ *
+ * \note If writing to a page that has previously been written to, the page's
+ *       row should be erased (via \ref nvm_erase_row()) before attempting to
+ *       write new data to the page.
+ *
+ * \note For SAM D21 RWW devices, see \c SAMD21_64K, command \c NVM_COMMAND_RWWEE_WRITE_PAGE
+ * must be executed before any other commands after writing a page,
+ * refer to errata 13588.
+ *
+ * \note If manual write mode is enabled, the write command must be executed after
+ * this function, otherwise the data will not write to NVM from page buffer.
+ *
+ * \return Status of the attempt to write a page.
+ *
+ * \retval STATUS_OK               Requested NVM memory page was successfully
+ *                                 read
+ * \retval STATUS_BUSY             NVM controller was busy when the operation
+ *                                 was attempted
+ * \retval STATUS_ERR_BAD_ADDRESS  The requested address was outside the
+ *                                 acceptable range of the NVM memory region or
+ *                                 not aligned to the start of a page
+ * \retval STATUS_ERR_INVALID_ARG  The supplied write length was invalid
+ */
+enum status_code nvm_write_buffer(
+		const uint32_t destination_address,
+		const uint8_t *buffer,
+		uint16_t length)
+{
+#ifdef FEATURE_NVM_RWWEE
+	bool is_rww_eeprom = false;
+#endif
+
+	/* Check if the destination address is valid */
+	if (destination_address >
+			((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) {
+#ifdef FEATURE_NVM_RWWEE
+		if (destination_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
+			|| destination_address < NVMCTRL_RWW_EEPROM_ADDR){
+			return STATUS_ERR_BAD_ADDRESS;
+		}
+		is_rww_eeprom = true;
+#else
+		return STATUS_ERR_BAD_ADDRESS;
+#endif
+	}
+
+	/* Check if the write address not aligned to the start of a page */
+	if (destination_address & (_nvm_dev.page_size - 1)) {
+		return STATUS_ERR_BAD_ADDRESS;
+	}
+
+	/* Check if the write length is longer than an NVM page */
+	if (length > _nvm_dev.page_size) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	/* Check if the module is busy */
+	if (!nvm_is_ready()) {
+		return STATUS_BUSY;
+	}
+
+	/* Erase the page buffer before buffering new data */
+	nvm_module->CTRLA.reg = NVM_COMMAND_PAGE_BUFFER_CLEAR | NVMCTRL_CTRLA_CMDEX_KEY;
+
+	/* Check if the module is busy */
+	while (!nvm_is_ready()) {
+		/* Force-wait for the buffer clear to complete */
+	}
+
+	/* Clear error flags */
+	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+	uint32_t nvm_address = destination_address / 2;
+
+	/* NVM _must_ be accessed as a series of 16-bit words, perform manual copy
+	 * to ensure alignment */
+	for (uint16_t i = 0; i < length; i += 2) {
+		uint16_t data;
+
+		/* Copy first byte of the 16-bit chunk to the temporary buffer */
+		data = buffer[i];
+
+		/* If we are not at the end of a write request with an odd byte count,
+		 * store the next byte of data as well */
+		if (i < (length - 1)) {
+			data |= (buffer[i + 1] << 8);
+		}
+
+		/* Store next 16-bit chunk to the NVM memory space */
+		NVM_MEMORY[nvm_address++] = data;
+	}
+
+	/* If automatic page write mode is enable, then perform a manual NVM
+	 * write when the length of data to be programmed is less than page size
+	 */
+	if ((_nvm_dev.manual_page_write == false) && (length < NVMCTRL_PAGE_SIZE)) {
+#ifdef FEATURE_NVM_RWWEE
+	 return ((is_rww_eeprom) ?
+				(nvm_execute_command(NVM_COMMAND_RWWEE_WRITE_PAGE,destination_address, 0)):
+	 			(nvm_execute_command(NVM_COMMAND_WRITE_PAGE,destination_address, 0)));
+#else
+		return nvm_execute_command(NVM_COMMAND_WRITE_PAGE,
+				destination_address, 0);
+#endif
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Reads a number of bytes from a page in the NVM memory region.
+ *
+ * Reads a given number of bytes from a given page address in the NVM memory
+ * space into a buffer.
+ *
+ * \param[in]  source_address  Source page address to read from
+ * \param[out] buffer          Pointer to a buffer where the content of the read
+ *                             page will be stored
+ * \param[in]  length          Number of bytes in the page to read
+ *
+ * \return Status of the page read attempt.
+ *
+ * \retval STATUS_OK               Requested NVM memory page was successfully
+ *                                 read
+ * \retval STATUS_BUSY             NVM controller was busy when the operation
+ *                                 was attempted
+ * \retval STATUS_ERR_BAD_ADDRESS  The requested address was outside the
+ *                                 acceptable range of the NVM memory region or
+ *                                 not aligned to the start of a page
+ * \retval STATUS_ERR_INVALID_ARG  The supplied read length was invalid
+ */
+enum status_code nvm_read_buffer(
+		const uint32_t source_address,
+		uint8_t *const buffer,
+		uint16_t length)
+{
+	/* Check if the source address is valid */
+	if (source_address >
+			((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) {
+#ifdef FEATURE_NVM_RWWEE
+		if (source_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
+			|| source_address < NVMCTRL_RWW_EEPROM_ADDR){
+			return STATUS_ERR_BAD_ADDRESS;
+		}
+#else
+		return STATUS_ERR_BAD_ADDRESS;
+#endif
+	}
+
+	/* Check if the read address is not aligned to the start of a page */
+	if (source_address & (_nvm_dev.page_size - 1)) {
+		return STATUS_ERR_BAD_ADDRESS;
+	}
+
+	/* Check if the write length is longer than an NVM page */
+	if (length > _nvm_dev.page_size) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	/* Check if the module is busy */
+	if (!nvm_is_ready()) {
+		return STATUS_BUSY;
+	}
+
+	/* Clear error flags */
+	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+	uint32_t page_address = source_address / 2;
+
+	/* NVM _must_ be accessed as a series of 16-bit words, perform manual copy
+	 * to ensure alignment */
+	for (uint16_t i = 0; i < length; i += 2) {
+		/* Fetch next 16-bit chunk from the NVM memory space */
+		uint16_t data = NVM_MEMORY[page_address++];
+
+		/* Copy first byte of the 16-bit chunk to the destination buffer */
+		buffer[i] = (data & 0xFF);
+
+		/* If we are not at the end of a read request with an odd byte count,
+		 * store the next byte of data as well */
+		if (i < (length - 1)) {
+			buffer[i + 1] = (data >> 8);
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Erases a row in the NVM memory space.
+ *
+ * Erases a given row in the NVM memory region.
+ *
+ * \param[in] row_address  Address of the row to erase
+ *
+ * \return Status of the NVM row erase attempt.
+ *
+ * \retval STATUS_OK               Requested NVM memory row was successfully
+ *                                 erased
+ * \retval STATUS_BUSY             NVM controller was busy when the operation
+ *                                 was attempted
+ * \retval STATUS_ERR_BAD_ADDRESS  The requested row address was outside the
+ *                                 acceptable range of the NVM memory region or
+ *                                 not aligned to the start of a row
+ * \retval STATUS_ABORTED          NVM erased error
+ */
+enum status_code nvm_erase_row(
+		const uint32_t row_address)
+{
+#ifdef FEATURE_NVM_RWWEE
+		bool is_rww_eeprom = false;
+#endif
+
+	/* Check if the row address is valid */
+	if (row_address >
+			((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) {
+#ifdef FEATURE_NVM_RWWEE
+		if (row_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
+			|| row_address < NVMCTRL_RWW_EEPROM_ADDR){
+			return STATUS_ERR_BAD_ADDRESS;
+		}
+		is_rww_eeprom = true;
+#else
+		return STATUS_ERR_BAD_ADDRESS;
+#endif
+	}
+
+	/* Check if the address to erase is not aligned to the start of a row */
+	if (row_address & ((_nvm_dev.page_size * NVMCTRL_ROW_PAGES) - 1)) {
+		return STATUS_ERR_BAD_ADDRESS;
+	}
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	/* Check if the module is busy */
+	if (!nvm_is_ready()) {
+		return STATUS_BUSY;
+	}
+
+	/* Clear error flags */
+	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+	/* Set address and command */
+	nvm_module->ADDR.reg  = (uintptr_t)&NVM_MEMORY[row_address / 4];
+
+#ifdef SAMD21_64K
+	if (is_rww_eeprom) {
+		NVM_MEMORY[row_address / 2] = 0x0;
+	}
+#endif
+
+#ifdef FEATURE_NVM_RWWEE
+	nvm_module->CTRLA.reg = ((is_rww_eeprom) ?
+								(NVM_COMMAND_RWWEE_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY):
+								(NVM_COMMAND_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY));
+#else
+	nvm_module->CTRLA.reg = NVM_COMMAND_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY;
+#endif
+
+	while (!nvm_is_ready()) {
+	}
+
+	/* There existed error in NVM erase operation */
+	if ((enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK) != NVM_ERROR_NONE) {
+		return STATUS_ABORTED;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Reads the parameters of the NVM controller.
+ *
+ * Retrieves the page size, number of pages, and other configuration settings
+ * of the NVM region.
+ *
+ * \param[out] parameters    Parameter structure, which holds page size and
+ *                           number of pages in the NVM memory
+ */
+void nvm_get_parameters(
+		struct nvm_parameters *const parameters)
+{
+	/* Sanity check parameters */
+	Assert(parameters);
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	/* Clear error flags */
+	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+	/* Read out from the PARAM register */
+	uint32_t param_reg = nvm_module->PARAM.reg;
+
+	/* Mask out page size exponent and convert to a number of bytes */
+	parameters->page_size =
+			8 << ((param_reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos);
+
+	/* Mask out number of pages count */
+	parameters->nvm_number_of_pages =
+			(param_reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
+
+#ifdef FEATURE_NVM_RWWEE
+	/* Mask out rwwee number of pages count */
+	parameters->rww_eeprom_number_of_pages =
+			(param_reg & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos;
+#endif
+
+	/* Read the current EEPROM fuse value from the USER row */
+	uint16_t eeprom_fuse_value =
+			(NVM_USER_MEMORY[NVMCTRL_FUSES_EEPROM_SIZE_Pos / 16] &
+			NVMCTRL_FUSES_EEPROM_SIZE_Msk) >> NVMCTRL_FUSES_EEPROM_SIZE_Pos;
+
+	/* Translate the EEPROM fuse byte value to a number of NVM pages */
+	if (eeprom_fuse_value == 7) {
+		parameters->eeprom_number_of_pages = 0;
+	}
+	else {
+		parameters->eeprom_number_of_pages =
+				NVMCTRL_ROW_PAGES << (6 - eeprom_fuse_value);
+	}
+
+	/* Read the current BOOTSZ fuse value from the USER row */
+	uint16_t boot_fuse_value =
+			(NVM_USER_MEMORY[NVMCTRL_FUSES_BOOTPROT_Pos / 16] &
+			NVMCTRL_FUSES_BOOTPROT_Msk) >> NVMCTRL_FUSES_BOOTPROT_Pos;
+
+	/* Translate the BOOTSZ fuse byte value to a number of NVM pages */
+	if (boot_fuse_value == 7) {
+		parameters->bootloader_number_of_pages = 0;
+	}
+	else {
+		parameters->bootloader_number_of_pages =
+				NVMCTRL_ROW_PAGES << (7 - boot_fuse_value);
+	}
+}
+
+/**
+ * \brief Checks whether the page region is locked.
+ *
+ * Extracts the region to which the given page belongs and checks whether
+ * that region is locked.
+ *
+ * \param[in] page_number    Page number to be checked
+ *
+ * \return Page lock status.
+ *
+ * \retval true              Page is locked
+ * \retval false             Page is not locked
+ *
+ */
+bool nvm_is_page_locked(uint16_t page_number)
+{
+	uint16_t pages_in_region;
+	uint16_t region_number;
+
+#ifdef FEATURE_NVM_RWWEE
+	Assert(page_number < _nvm_dev.number_of_pages);
+#endif
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	/* Get number of pages in a region */
+	pages_in_region = _nvm_dev.number_of_pages / 16;
+
+	/* Get region for given page */
+	region_number = page_number / pages_in_region;
+
+	return !(nvm_module->LOCK.reg & (1 << region_number));
+}
+
+///@cond INTERNAL
+
+/**
+ * \internal
+ *
+ * \brief Translate fusebit words into struct content.
+ *
+ */
+static void _nvm_translate_raw_fusebits_to_struct (
+		uint32_t *raw_user_row,
+		struct nvm_fusebits *fusebits)
+{
+
+	fusebits->bootloader_size = (enum nvm_bootloader_size)
+			((raw_user_row[0] & NVMCTRL_FUSES_BOOTPROT_Msk)
+			>> NVMCTRL_FUSES_BOOTPROT_Pos);
+
+	fusebits->eeprom_size = (enum nvm_eeprom_emulator_size)
+			((raw_user_row[0] & NVMCTRL_FUSES_EEPROM_SIZE_Msk)
+			>> NVMCTRL_FUSES_EEPROM_SIZE_Pos);
+
+#if (SAML21) || (SAML22) || (SAMR30)
+	fusebits->bod33_level = (uint8_t)
+			((raw_user_row[0] & FUSES_BOD33USERLEVEL_Msk)
+			>> FUSES_BOD33USERLEVEL_Pos);
+
+	fusebits->bod33_enable = (bool)
+			(!((raw_user_row[0] & FUSES_BOD33_DIS_Msk)
+			>> FUSES_BOD33_DIS_Pos));
+
+	fusebits->bod33_action = (enum nvm_bod33_action)
+			((raw_user_row[0] & FUSES_BOD33_ACTION_Msk)
+			>> FUSES_BOD33_ACTION_Pos);
+
+	fusebits->bod33_hysteresis = (bool)
+			((raw_user_row[1] & FUSES_BOD33_HYST_Msk)
+			>> FUSES_BOD33_HYST_Pos);
+
+#elif (SAMD20) || (SAMD21) || (SAMR21)|| (SAMDA1) || (SAMD09) || (SAMD10) || (SAMD11) || (SAMHA1)
+	fusebits->bod33_level = (uint8_t)
+			((raw_user_row[0] & FUSES_BOD33USERLEVEL_Msk)
+			>> FUSES_BOD33USERLEVEL_Pos);
+
+	fusebits->bod33_enable = (bool)
+			((raw_user_row[0] & FUSES_BOD33_EN_Msk)
+			>> FUSES_BOD33_EN_Pos);
+
+	fusebits->bod33_action = (enum nvm_bod33_action)
+			((raw_user_row[0] & FUSES_BOD33_ACTION_Msk)
+			>> FUSES_BOD33_ACTION_Pos);
+	fusebits->bod33_hysteresis = (bool)
+			((raw_user_row[1] & FUSES_BOD33_HYST_Msk)
+			>> FUSES_BOD33_HYST_Pos);
+#elif (SAMC20) || (SAMC21)
+	fusebits->bodvdd_level = (uint8_t)
+			((raw_user_row[0] & FUSES_BODVDDUSERLEVEL_Msk)
+			>> FUSES_BODVDDUSERLEVEL_Pos);
+
+	fusebits->bodvdd_enable = (bool)
+			(!((raw_user_row[0] & FUSES_BODVDD_DIS_Msk)
+			>> FUSES_BODVDD_DIS_Pos));
+
+	fusebits->bodvdd_action = (enum nvm_bod33_action)
+			((raw_user_row[0] & FUSES_BODVDD_ACTION_Msk)
+			>> FUSES_BODVDD_ACTION_Pos);
+
+	fusebits->bodvdd_hysteresis = (raw_user_row[1] & FUSES_BODVDD_HYST_Msk)
+									>> FUSES_BODVDD_HYST_Pos;
+#endif
+
+#ifdef FEATURE_BOD12
+
+#ifndef FUSES_BOD12USERLEVEL_Pos
+#define FUSES_BOD12USERLEVEL_Pos 17
+#define FUSES_BOD12USERLEVEL_Msk (0x3Ful << FUSES_BOD12USERLEVEL_Pos)
+#endif
+#ifndef FUSES_BOD12_DIS_Pos
+#define FUSES_BOD12_DIS_Pos 23
+#define FUSES_BOD12_DIS_Msk (0x1ul << FUSES_BOD12_DIS_Pos)
+#endif
+#ifndef FUSES_BOD12_ACTION_Pos
+#define FUSES_BOD12_ACTION_Pos 24
+#define FUSES_BOD12_ACTION_Msk (0x3ul << FUSES_BOD12_ACTION_Pos)
+#endif
+	
+	fusebits->bod12_level = (uint8_t)
+			((raw_user_row[0] & FUSES_BOD12USERLEVEL_Msk)
+			>> FUSES_BOD12USERLEVEL_Pos);
+
+	fusebits->bod12_enable = (bool)
+			(!((raw_user_row[0] & FUSES_BOD12_DIS_Msk)
+			>> FUSES_BOD12_DIS_Pos));
+
+	fusebits->bod12_action = (enum nvm_bod12_action)
+			((raw_user_row[0] & FUSES_BOD12_ACTION_Msk)
+			>> FUSES_BOD33_ACTION_Pos);
+
+	fusebits->bod12_hysteresis = (bool)
+			((raw_user_row[1] & FUSES_BOD12_HYST_Msk)
+			>> FUSES_BOD12_HYST_Pos);
+#endif
+
+	fusebits->wdt_enable = (bool)
+			((raw_user_row[0] & WDT_FUSES_ENABLE_Msk) >> WDT_FUSES_ENABLE_Pos);
+
+	fusebits->wdt_always_on = (bool)
+			((raw_user_row[0] & WDT_FUSES_ALWAYSON_Msk) >> WDT_FUSES_ALWAYSON_Pos);
+
+	fusebits->wdt_timeout_period = (uint8_t)
+			((raw_user_row[0] & WDT_FUSES_PER_Msk) >> WDT_FUSES_PER_Pos);
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	fusebits->wdt_window_timeout = (enum nvm_wdt_window_timeout)
+			((raw_user_row[1] & WDT_FUSES_WINDOW_Msk) >> WDT_FUSES_WINDOW_Pos);
+#else
+	/* WDT Windows timout lay between two 32-bit words in the user row. Because only one bit lays in word[0],
+	   bits in word[1] must be left sifted by one to make the correct number */
+	fusebits->wdt_window_timeout = (enum nvm_wdt_window_timeout)
+			(((raw_user_row[0] & WDT_FUSES_WINDOW_0_Msk) >> WDT_FUSES_WINDOW_0_Pos) |
+			((raw_user_row[1] & WDT_FUSES_WINDOW_1_Msk) << 1));
+#endif
+	fusebits->wdt_early_warning_offset = (enum nvm_wdt_early_warning_offset)
+			((raw_user_row[1] & WDT_FUSES_EWOFFSET_Msk) >> WDT_FUSES_EWOFFSET_Pos);
+
+	fusebits->wdt_window_mode_enable_at_poweron = (bool)
+			((raw_user_row[1] & WDT_FUSES_WEN_Msk) >> WDT_FUSES_WEN_Pos);
+
+	fusebits->lockbits = (uint16_t)
+			((raw_user_row[1] & NVMCTRL_FUSES_REGION_LOCKS_Msk)
+			>> NVMCTRL_FUSES_REGION_LOCKS_Pos);
+
+}
+
+///@endcond
+
+/**
+ * \brief Get fuses from user row.
+ *
+ * Read out the fuse settings from the user row.
+ *
+ * \param[in] fusebits Pointer to a 64-bit wide memory buffer of type struct nvm_fusebits
+ *
+ * \return             Status of read fuses attempt.
+ *
+ * \retval STATUS_OK   This function will always return STATUS_OK
+ */
+enum status_code nvm_get_fuses (
+		struct nvm_fusebits *fusebits)
+{
+	enum status_code error_code = STATUS_OK;
+	uint32_t raw_fusebits[2];
+
+	/* Make sure the module is ready */
+	while (!nvm_is_ready()) {
+	}
+
+	/* Read the fuse settings in the user row, 64 bit */
+	((uint16_t*)&raw_fusebits)[0] = (uint16_t)NVM_MEMORY[NVMCTRL_USER / 2];
+	((uint16_t*)&raw_fusebits)[1] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 1];
+	((uint16_t*)&raw_fusebits)[2] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 2];
+	((uint16_t*)&raw_fusebits)[3] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 3];
+
+	_nvm_translate_raw_fusebits_to_struct(raw_fusebits, fusebits);
+
+	return error_code;
+}
+
+/**
+ * \brief Set fuses from user row.
+ *
+ * Set fuse settings from the user row.
+ *
+ * \note When writing to the user row, the values do not get loaded by the
+ * other modules on the device until a device reset occurs.
+ *
+ * \param[in] fusebits Pointer to a 64-bit wide memory buffer of type struct nvm_fusebits
+ *
+ * \return             Status of read fuses attempt.
+ *
+ * \retval STATUS_OK   This function will always return STATUS_OK
+ *
+ * \retval STATUS_BUSY             If the NVM controller was already busy
+ *                                 executing a command when the new command
+ *                                 was issued
+ * \retval STATUS_ERR_IO           If the command was invalid due to memory or
+ *                                 security locking
+ * \retval STATUS_ERR_INVALID_ARG  If the given command was invalid or
+ *                                 unsupported
+ * \retval STATUS_ERR_BAD_ADDRESS  If the given address was invalid
+ */
+
+enum status_code nvm_set_fuses(struct nvm_fusebits *fb)
+{
+    uint32_t fusebits[2];
+	enum status_code error_code = STATUS_OK;
+
+	if (fb == NULL) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+    /* Read the fuse settings in the user row, 64 bit */
+    fusebits[0] = *((uint32_t *)NVMCTRL_AUX0_ADDRESS);
+    fusebits[1] = *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1);
+
+	/* Set user fuses bit */
+	fusebits[0] &= (~NVMCTRL_FUSES_BOOTPROT_Msk);
+	fusebits[0] |= NVMCTRL_FUSES_BOOTPROT(fb->bootloader_size);
+
+	fusebits[0] &= (~NVMCTRL_FUSES_EEPROM_SIZE_Msk);
+	fusebits[0] |= NVMCTRL_FUSES_EEPROM_SIZE(fb->eeprom_size);
+
+#if (SAML21) || (SAML22) || (SAMR30)
+	fusebits[0] &= (~FUSES_BOD33USERLEVEL_Msk);
+	fusebits[0] |= FUSES_BOD33USERLEVEL(fb->bod33_level);
+
+	fusebits[0] &= (~FUSES_BOD33_DIS_Msk);
+	fusebits[0] |= (!fb->bod33_enable) << FUSES_BOD33_DIS_Pos;
+
+	fusebits[0] &= (~FUSES_BOD33_ACTION_Msk);
+	fusebits[0] |= fb->bod33_action << FUSES_BOD33_ACTION_Pos;
+
+	fusebits[1] &= (~FUSES_BOD33_HYST_Msk);
+	fusebits[1] |= fb->bod33_hysteresis << FUSES_BOD33_HYST_Pos;
+
+#elif (SAMD20) || (SAMD21) || (SAMR21) || (SAMDA1) || (SAMD09) || (SAMD10) || (SAMD11) || (SAMHA1)
+	fusebits[0] &= (~FUSES_BOD33USERLEVEL_Msk);
+	fusebits[0] |= FUSES_BOD33USERLEVEL(fb->bod33_level);
+
+	fusebits[0] &= (~FUSES_BOD33_EN_Msk);
+	fusebits[0] |= (fb->bod33_enable) << FUSES_BOD33_EN_Pos;
+
+	fusebits[0] &= (~FUSES_BOD33_ACTION_Msk);
+	fusebits[0] |= fb->bod33_action << FUSES_BOD33_ACTION_Pos;
+
+	fusebits[1] &= (~FUSES_BOD33_HYST_Msk);
+	fusebits[1] |= fb->bod33_hysteresis << FUSES_BOD33_HYST_Pos;
+
+#elif (SAMC20) || (SAMC21)
+	fusebits[0] &= (~FUSES_BODVDDUSERLEVEL_Msk);
+	fusebits[0] |= FUSES_BODVDDUSERLEVEL(fb->bodvdd_level);
+
+	fusebits[0] &= (~FUSES_BODVDD_DIS_Msk);
+	fusebits[0] |= (!fb->bodvdd_enable) << FUSES_BODVDD_DIS_Pos;
+
+	fusebits[0] &= (~FUSES_BODVDD_ACTION_Msk);
+	fusebits[0] |= fb->bodvdd_action << FUSES_BODVDD_ACTION_Pos;
+
+	fusebits[1] &= (~FUSES_BODVDD_HYST_Msk);
+	fusebits[1] |= fb->bodvdd_hysteresis << FUSES_BODVDD_HYST_Pos;
+
+#endif
+
+	fusebits[0] &= (~WDT_FUSES_ENABLE_Msk);
+	fusebits[0] |= fb->wdt_enable << WDT_FUSES_ENABLE_Pos;
+
+	fusebits[0] &= (~WDT_FUSES_ALWAYSON_Msk);
+	fusebits[0] |= (fb->wdt_always_on) << WDT_FUSES_ALWAYSON_Pos;
+
+	fusebits[0] &= (~WDT_FUSES_PER_Msk);
+	fusebits[0] |= fb->wdt_timeout_period << WDT_FUSES_PER_Pos;
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	fusebits[1] &= (~WDT_FUSES_WINDOW_Msk);
+	fusebits[1] |= fb->wdt_window_timeout << WDT_FUSES_WINDOW_Pos;
+#else
+   /* WDT Windows timout lay between two 32-bit words in the user row. the last one bit lays in word[0],
+	   and the other bits in word[1] */
+	fusebits[0] &= (~WDT_FUSES_WINDOW_0_Msk);
+	fusebits[0] |= (fb->wdt_window_timeout & 0x1) << WDT_FUSES_WINDOW_0_Pos;
+
+	fusebits[1] &= (~WDT_FUSES_WINDOW_1_Msk);
+	fusebits[1] |= (fb->wdt_window_timeout >> 1) << WDT_FUSES_WINDOW_1_Pos;
+
+#endif
+	fusebits[1] &= (~WDT_FUSES_EWOFFSET_Msk);
+	fusebits[1] |= fb->wdt_early_warning_offset << WDT_FUSES_EWOFFSET_Pos;
+
+	fusebits[1] &= (~WDT_FUSES_WEN_Msk);
+	fusebits[1] |= fb->wdt_window_mode_enable_at_poweron << WDT_FUSES_WEN_Pos;
+
+	fusebits[1] &= (~NVMCTRL_FUSES_REGION_LOCKS_Msk);
+	fusebits[1] |= fb->lockbits << NVMCTRL_FUSES_REGION_LOCKS_Pos;
+
+#ifdef FEATURE_BOD12
+	
+#ifndef FUSES_BOD12USERLEVEL_Pos
+#define FUSES_BOD12USERLEVEL_Pos 17
+#define FUSES_BOD12USERLEVEL_Msk (0x3Ful << FUSES_BOD12USERLEVEL_Pos)
+#endif
+#ifndef FUSES_BOD12_DIS_Pos
+#define FUSES_BOD12_DIS_Pos 23
+#define FUSES_BOD12_DIS_Msk (0x1ul << FUSES_BOD12_DIS_Pos)
+#endif
+#ifndef FUSES_BOD12_ACTION_Pos
+#define FUSES_BOD12_ACTION_Pos 24
+#define FUSES_BOD12_ACTION_Msk (0x3ul << FUSES_BOD12_ACTION_Pos)
+#endif
+		
+	fusebits[0] &= (~FUSES_BOD12USERLEVEL_Msk);
+	fusebits[0] |= ((FUSES_BOD12USERLEVEL_Msk & ((fb->bod12_level) << 
+						FUSES_BOD12USERLEVEL_Pos)));
+
+	fusebits[0] &= (~FUSES_BOD12_DIS_Msk);
+	fusebits[0] |= (!fb->bod12_enable) << FUSES_BOD12_DIS_Pos;
+
+	fusebits[0] &= (~FUSES_BOD12_ACTION_Msk);
+	fusebits[0] |= fb->bod12_action << FUSES_BOD12_ACTION_Pos;
+
+	fusebits[1] &= (~FUSES_BOD12_HYST_Msk);
+	fusebits[1] |= fb->bod12_hysteresis << FUSES_BOD12_HYST_Pos;
+#endif
+
+	error_code = nvm_execute_command(NVM_COMMAND_ERASE_AUX_ROW,NVMCTRL_AUX0_ADDRESS,0);
+	if (error_code != STATUS_OK) {
+		return error_code;
+	}
+
+	error_code = nvm_execute_command(NVM_COMMAND_PAGE_BUFFER_CLEAR,NVMCTRL_AUX0_ADDRESS,0);
+	if (error_code != STATUS_OK) {
+		return error_code;
+	}
+
+	*((uint32_t *)NVMCTRL_AUX0_ADDRESS) = fusebits[0];
+    *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = fusebits[1];
+
+	error_code = nvm_execute_command(NVM_COMMAND_WRITE_AUX_ROW,NVMCTRL_AUX0_ADDRESS,0);
+	if (error_code != STATUS_OK) {
+		return error_code;
+	}
+
+	return error_code;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.h
new file mode 100644
index 0000000000..73b127d517
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.h
@@ -0,0 +1,946 @@
+/**
+ * \file
+ *
+ * \brief SAM Non-Volatile Memory driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef NVM_H_INCLUDED
+#define NVM_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_nvm_group SAM Non-Volatile Memory (NVM) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of non-volatile memories
+ * within the device, for partitioning, erasing, reading, and writing of data.
+ *
+ * The following peripheral is used by this module:
+ *  - NVM (Non-Volatile Memory)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_nvm_prerequisites
+ *  - \ref asfdoc_sam0_nvm_module_overview
+ *  - \ref asfdoc_sam0_nvm_special_considerations
+ *  - \ref asfdoc_sam0_nvm_extra_info
+ *  - \ref asfdoc_sam0_nvm_examples
+ *  - \ref asfdoc_sam0_nvm_api_overview
+ *
+ *
+ * \section asfdoc_sam0_nvm_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_nvm_module_overview Module Overview
+ *
+ * The Non-Volatile Memory (NVM) module provides an interface to the device's
+ * Non-Volatile Memory controller, so that memory pages can be written, read,
+ * erased, and reconfigured in a standardized manner.
+ *
+ * \subsection asfdoc_sam0_nvm_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver feature macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_NVM_RWWEE</td>
+ *    <td>SAM L21/L22, SAM D21-64K, SAM DA1, SAM C20/C21, SAM R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_BOD12</td>
+ *    <td>SAM L21, SAMR30</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_nvm_module_overview_regions Memory Regions
+ * The NVM memory space of the SAM devices is divided into two sections:
+ * a Main Array section, and an Auxiliary space section. The Main Array space
+ * can be configured to have an (emulated) EEPROM and/or boot loader section.
+ * The memory layout with the EEPROM and bootloader partitions is shown in
+ * \ref asfdoc_sam0_nvm_module_mem_layout "the figure below".
+ *
+ * \anchor asfdoc_sam0_nvm_module_mem_layout
+ * \dot
+ * digraph memory_layout {
+ *  size="5,5"
+ *  node [shape=plaintext, fontname=arial]
+ *  memory [label=<
+ *   <table border="0" cellborder="1" cellspacing="0" >
+ *    <tr>
+ *     <td align="right" border="0"> End of NVM Memory </td>
+ *     <td rowspan="3" align="center"> Reserved EEPROM Section </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> Start of EEPROM Memory </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> End of Application Memory </td>
+ *     <td rowspan="3" align="center"> Application Section </td>
+ *    </tr>
+ *    <tr>
+ *     <td height="300" align="right" border="0"> </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> Start of Application Memory </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> End of Bootloader Memory </td>
+ *     <td rowspan="3" align="center"> BOOT Section </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> Start of NVM Memory</td>
+ *    </tr>
+ *   </table>
+ *  >]
+ * }
+ * \enddot
+ *
+ * The Main Array is divided into rows and pages, where each row contains four
+ * pages. The size of each page may vary from 8-1024 bytes dependent of the
+ * device. Device specific parameters such as the page size and total number of
+ * pages in the NVM memory space are available via the \ref nvm_get_parameters()
+ * function.
+ *
+ * An NVM page number and address can be computed via the following equations:
+ *
+ * \f[ PageNum = (RowNum \times 4) + PagePosInRow \f]
+ * \f[ PageAddr = PageNum \times PageSize \f]
+ *
+ * \ref asfdoc_sam0_nvm_module_row_layout "The figure below" shows an example
+ * of the memory page and address values associated with logical row 7 of the
+ * NVM memory space.
+ *
+ * \anchor asfdoc_sam0_nvm_module_row_layout
+ * \dot
+ * digraph row_layout {
+ *  size="4,4"
+ *  node [shape=plaintext, fontname=arial]
+ *  row [label=<
+ *   <table border="0" cellborder="1" cellspacing="0">
+ *    <tr>
+ *     <td align="right" border ="0"> Row 0x07 </td>
+ *     <td > Page 0x1F </td>
+ *     <td > Page 0x1E </td>
+ *     <td > Page 0x1D </td>
+ *     <td > Page 0x1C </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border ="0"> Address </td>
+ *     <td border="0"> 0x7C0 </td>
+ *     <td border="0"> 0x780 </td>
+ *     <td border="0"> 0x740 </td>
+ *     <td border="0"> 0x700 </td>
+ *    </tr>
+ *   </table>
+ *  >]
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_nvm_module_overview_locking_regions Region Lock Bits
+ * As mentioned in \ref asfdoc_sam0_nvm_module_overview_regions, the main
+ * block of the NVM memory is divided into a number of individually addressable
+ * pages. These pages are grouped into 16 equal sized regions, where each region
+ * can be locked separately issuing an \ref NVM_COMMAND_LOCK_REGION command or
+ * by writing the LOCK bits in the User Row. Rows reserved for the EEPROM
+ * section are not affected by the lock bits or commands.
+ *
+ * \note By using the \ref NVM_COMMAND_LOCK_REGION or
+ *       \ref NVM_COMMAND_UNLOCK_REGION commands the settings will remain in
+ *       effect until the next device reset. By changing the default lock
+ *       setting for the regions, the auxiliary space must to be written,
+ *       however the adjusted configuration will not take effect until the next
+ *       device reset.
+ *
+ * \note If the \ref asfdoc_sam0_nvm_special_consideration_security_bit is
+ *       set, the auxiliary space cannot be written to. Clearing of the security
+ *       bit can only be performed by a full chip erase.
+ *
+ * \subsection asfdoc_sam0_nvm_module_overview_sub_rw Read/Write
+ * Reading from the NVM memory can be performed using direct addressing into the
+ * NVM memory space, or by calling the \ref nvm_read_buffer() function.
+ *
+ * Writing to the NVM memory must be performed by the \ref nvm_write_buffer()
+ * function - additionally, a manual page program command must be issued if
+ * the NVM controller is configured in manual page writing mode.
+ *
+ * Before a page can be updated, the associated NVM memory row must be erased
+ * first via the \ref nvm_erase_row() function. Writing to a non-erased page
+ * will result in corrupt data being stored in the NVM memory space.
+ *
+ * \section asfdoc_sam0_nvm_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_nvm_special_consideration_pageerase Page Erasure
+ * The granularity of an erase is per row, while the granularity of a write is
+ * per page. Thus, if the user application is modifying only one page of a row,
+ * the remaining pages in the row must be buffered and the row erased, as an
+ * erase is mandatory before writing to a page.
+ *
+ * \subsection asfdoc_sam0_nvm_special_consideration_clocks Clocks
+ * The user must ensure that the driver is configured with a proper number of
+ * wait states when the CPU is running at high frequencies.
+ *
+ * \subsection asfdoc_sam0_nvm_special_consideration_security_bit Security Bit
+ * The User Row in the Auxiliary Space cannot be read or written when
+ * the Security Bit is set. The Security Bit can be set by using passing
+ * \ref NVM_COMMAND_SET_SECURITY_BIT to the \ref nvm_execute_command() function,
+ * or it will be set if one tries to access a locked region. See
+ * \ref asfdoc_sam0_nvm_module_overview_locking_regions.
+ *
+ * The Security Bit can only be cleared by performing a chip erase.
+ *
+ *
+ * \section asfdoc_sam0_nvm_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_nvm_extra. This includes:
+ *  - \ref asfdoc_sam0_nvm_extra_acronyms
+ *  - \ref asfdoc_sam0_nvm_extra_dependencies
+ *  - \ref asfdoc_sam0_nvm_extra_errata
+ *  - \ref asfdoc_sam0_nvm_extra_history
+ *
+ *
+ * \section asfdoc_sam0_nvm_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_nvm_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_nvm_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <status_codes.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define SAMD21-64K devices */
+#if defined(SAMD21E15L) || defined(SAMD21E16L) || defined(__SAMD21E15L__) || defined(__SAMD21E16L__) \
+	|| defined(SAMD21E15B) || defined(SAMD21E16B) || defined(__SAMD21E15B__) || defined(__SAMD21E16B__) \
+	|| defined(SAMD21E15BU) || defined(SAMD21E16BU) || defined(__SAMD21E15BU__) || defined(__SAMD21E16BU__) \
+	|| defined(SAMD21G15L) || defined(SAMD21G16L) || defined(__SAMD21G15L__) || defined(__SAMD21G16L__) \
+	|| defined(SAMD21G15B) || defined(SAMD21G16B) || defined(__SAMD21G15B__) || defined(__SAMD21G16B__) \
+	|| defined(SAMD21J15B) || defined(SAMD21J16B) || defined(__SAMD21J15B__) || defined(__SAMD21J16B__)
+
+#  define SAMD21_64K
+
+#endif
+
+/**
+ * \name Driver Feature Definition
+ *
+ * Define NVM features set according to the different device families.
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || (SAMR30) || defined(SAMD21_64K) || (SAMHA1) \
+	|| defined(__DOXYGEN__)
+/** Read while write EEPROM emulation feature. */
+#  define FEATURE_NVM_RWWEE
+#endif
+#if (SAML21) || (SAMR30) || defined(__DOXYGEN__)
+/** Brown-out detector internal to the voltage regulator for VDDCORE. */
+#define FEATURE_BOD12
+#endif
+/*@}*/
+
+#if !defined(__DOXYGEN__)
+/**
+ * \brief Mask for the error flags in the status register.
+ */
+#  define NVM_ERRORS_MASK (NVMCTRL_STATUS_PROGE | \
+                           NVMCTRL_STATUS_LOCKE | \
+                           NVMCTRL_STATUS_NVME)
+#endif
+
+/**
+ * \brief NVM error flags.
+ *
+ * Possible NVM controller error codes, which can be returned by the NVM
+ * controller after a command is issued.
+ */
+enum nvm_error {
+	/** No errors */
+	NVM_ERROR_NONE = 0,
+	/** Lock error, a locked region was attempted accessed */
+	NVM_ERROR_LOCK = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_LOCKE,
+	/** Program error, invalid command was executed */
+	NVM_ERROR_PROG = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_PROGE,
+};
+
+/**
+ * \brief NVM controller commands.
+ */
+enum nvm_command {
+	/** Erases the addressed memory row */
+	NVM_COMMAND_ERASE_ROW                  = NVMCTRL_CTRLA_CMD_ER,
+
+	/** Write the contents of the page buffer to the addressed memory page */
+	NVM_COMMAND_WRITE_PAGE                 = NVMCTRL_CTRLA_CMD_WP,
+
+	/** Erases the addressed auxiliary memory row.
+	 *
+	 *  \note This command can only be given when the security bit is not set.
+	 */
+	NVM_COMMAND_ERASE_AUX_ROW              = NVMCTRL_CTRLA_CMD_EAR,
+
+	/** Write the contents of the page buffer to the addressed auxiliary memory
+	 *  row.
+	 *
+	 *  \note This command can only be given when the security bit is not set.
+	 */
+	NVM_COMMAND_WRITE_AUX_ROW              = NVMCTRL_CTRLA_CMD_WAP,
+
+	/** Locks the addressed memory region, preventing further modifications
+	 *  until the region is unlocked or the device is erased
+	 */
+	NVM_COMMAND_LOCK_REGION                = NVMCTRL_CTRLA_CMD_LR,
+
+	/** Unlocks the addressed memory region, allowing the region contents to be
+	 *  modified
+	 */
+	NVM_COMMAND_UNLOCK_REGION              = NVMCTRL_CTRLA_CMD_UR,
+
+	/** Clears the page buffer of the NVM controller, resetting the contents to
+	 *  all zero values
+	 */
+	NVM_COMMAND_PAGE_BUFFER_CLEAR          = NVMCTRL_CTRLA_CMD_PBC,
+
+	/** Sets the device security bit, disallowing the changing of lock bits and
+	 *  auxiliary row data until a chip erase has been performed
+	 */
+	NVM_COMMAND_SET_SECURITY_BIT           = NVMCTRL_CTRLA_CMD_SSB,
+
+	/** Enter power reduction mode in the NVM controller to reduce the power
+	 *  consumption of the system
+	 */
+	NVM_COMMAND_ENTER_LOW_POWER_MODE       = NVMCTRL_CTRLA_CMD_SPRM,
+
+	/** Exit power reduction mode in the NVM controller to allow other NVM
+	 *  commands to be issued
+	 */
+	NVM_COMMAND_EXIT_LOW_POWER_MODE        = NVMCTRL_CTRLA_CMD_CPRM,
+#ifdef FEATURE_NVM_RWWEE
+	/** Read while write (RWW) EEPROM area erase row */
+	NVM_COMMAND_RWWEE_ERASE_ROW            = NVMCTRL_CTRLA_CMD_RWWEEER,
+	/** RWW EEPROM write page */
+	NVM_COMMAND_RWWEE_WRITE_PAGE           = NVMCTRL_CTRLA_CMD_RWWEEWP,
+#endif
+};
+
+/**
+ * \brief NVM controller power reduction mode configurations.
+ *
+ * Power reduction modes of the NVM controller, to conserve power while the
+ * device is in sleep.
+ */
+enum nvm_sleep_power_mode {
+	/** NVM controller exits low-power mode on first access after sleep */
+	NVM_SLEEP_POWER_MODE_WAKEONACCESS  = NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val,
+	/** NVM controller exits low-power mode when the device exits sleep mode */
+	NVM_SLEEP_POWER_MODE_WAKEUPINSTANT = NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val,
+	/** Power reduction mode in the NVM controller disabled */
+	NVM_SLEEP_POWER_MODE_ALWAYS_AWAKE  = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val,
+};
+
+/**
+ * \brief NVM controller cache readmode configuration.
+ *
+ * Control how the NVM cache prefetch data from flash.
+ *
+ */
+enum nvm_cache_readmode {
+	/** The NVM Controller (cache system) does not insert wait states on
+	 *  a cache miss. Gives the best system performance.
+	 */
+	NVM_CACHE_READMODE_NO_MISS_PENALTY,
+	/** Reduces power consumption of the cache system, but inserts a
+	 *  wait state each time there is a cache miss
+	 */
+	NVM_CACHE_READMODE_LOW_POWER,
+	/** The cache system ensures that a cache hit or miss takes the same
+	 *  amount of time, determined by the number of programmed flash
+	 *  wait states
+	 */
+	NVM_CACHE_READMODE_DETERMINISTIC,
+};
+
+/**
+ * \brief NVM controller configuration structure.
+ *
+ * Configuration structure for the NVM controller within the device.
+ */
+struct nvm_config {
+	/** Power reduction mode during device sleep */
+	enum nvm_sleep_power_mode sleep_power_mode;
+	/** Manual write mode; if enabled, pages loaded into the NVM buffer will
+	 *  not be written until a separate write command is issued. If disabled,
+	 *  writing to the last byte in the NVM page buffer will trigger an automatic
+	 *  write.
+	 *
+	 *  \note If a partial page is to be written, a manual write command must be
+	 *        executed in either mode.
+	 */
+	bool manual_page_write;
+	/** Number of wait states to insert when reading from flash, to prevent
+	 *  invalid data from being read at high clock frequencies
+	 */
+	uint8_t wait_states;
+
+	/**
+	 * Setting this to true will disable the pre-fetch cache in front of the
+	 * NVM controller
+	 */
+	bool disable_cache;
+#if (SAMC20) || (SAMC21)
+	/**
+	 * Setting this to true will disable the pre-fetch RWW cache in front of the
+	 * NVM controller.
+	 * If RWW cache is enabled, NVM cache will also be enabled.
+	 */
+	bool disable_rww_cache;
+#endif
+	/**
+	 * Select the mode for  how the cache will pre-fetch data from the flash
+	 */
+	enum nvm_cache_readmode cache_readmode;
+};
+
+/**
+ * \brief NVM memory parameter structure.
+ *
+ * Structure containing the memory layout parameters of the NVM module.
+ */
+struct nvm_parameters {
+	/** Number of bytes per page */
+	uint8_t  page_size;
+	/** Number of pages in the main array */
+	uint16_t nvm_number_of_pages;
+	/** Size of the emulated EEPROM memory section configured in the NVM
+	 *  auxiliary memory space */
+	uint32_t eeprom_number_of_pages;
+	/** Size of the Bootloader memory section configured in the NVM auxiliary
+	 *  memory space */
+	uint32_t bootloader_number_of_pages;
+#ifdef FEATURE_NVM_RWWEE
+	/** Number of pages in read while write EEPROM (RWWEE) emulation area */
+	uint16_t rww_eeprom_number_of_pages;
+#endif
+};
+
+/**
+ * \brief Bootloader size.
+ *
+ * Available bootloader protection sizes in kilobytes.
+ *
+ */
+enum nvm_bootloader_size {
+	/** Boot Loader Size is 32768 bytes */
+	NVM_BOOTLOADER_SIZE_128,
+	/** Boot Loader Size is 16384 bytes */
+	NVM_BOOTLOADER_SIZE_64,
+	/** Boot Loader Size is 8192 bytes */
+	NVM_BOOTLOADER_SIZE_32,
+	/** Boot Loader Size is 4096 bytes */
+	NVM_BOOTLOADER_SIZE_16,
+	/** Boot Loader Size is 2048 bytes */
+	NVM_BOOTLOADER_SIZE_8,
+	/** Boot Loader Size is 1024 bytes */
+	NVM_BOOTLOADER_SIZE_4,
+	/** Boot Loader Size is 512 bytes */
+	NVM_BOOTLOADER_SIZE_2,
+	/** Boot Loader Size is 0 bytes */
+	NVM_BOOTLOADER_SIZE_0,
+};
+
+/**
+ * \brief EEPROM emulator size.
+ *
+ * Available space in flash dedicated for EEPROM emulator in bytes.
+ *
+ */
+enum nvm_eeprom_emulator_size {
+	/** EEPROM Size for EEPROM emulation is 16384 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_16384,
+	/** EEPROM Size for EEPROM emulation is 8192 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_8192,
+	/** EEPROM Size for EEPROM emulation is 4096 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_4096,
+	/** EEPROM Size for EEPROM emulation is 2048 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_2048,
+	/** EEPROM Size for EEPROM emulation is 1024 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_1024,
+	/** EEPROM Size for EEPROM emulation is 512 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_512,
+	/** EEPROM Size for EEPROM emulation is 256 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_256,
+	/** EEPROM Size for EEPROM emulation is 0 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_0,
+};
+
+/**
+ * \brief BOD33 Action.
+ *
+ * What action should be triggered when BOD33 is detected.
+ *
+ */
+enum nvm_bod33_action {
+	/** No action */
+	NVM_BOD33_ACTION_NONE,
+	/** The BOD33 generates a reset */
+	NVM_BOD33_ACTION_RESET,
+	/** The BOD33 generates an interrupt */
+	NVM_BOD33_ACTION_INTERRUPT,
+};
+
+#ifdef FEATURE_BOD12
+/**
+ * \brief BOD12 Action.
+ *
+ * What action should be triggered when BOD12 is detected.
+ *
+ */
+enum nvm_bod12_action {
+	/** No action */
+	NVM_BOD12_ACTION_NONE,
+	/** The BOD12 generates a reset */
+	NVM_BOD12_ACTION_RESET,
+	/** The BOD12 generates an interrupt */
+	NVM_BOD12_ACTION_INTERRUPT,
+};
+#endif
+
+/**
+ * \brief WDT Window time-out period.
+ *
+ * Window mode time-out period in clock cycles.
+ *
+ */
+enum nvm_wdt_window_timeout {
+	/** 8 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_8,
+	/** 16 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_16,
+	/** 32 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_32,
+	/** 64 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_64,
+	/** 128 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_128,
+	/** 256 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_256,
+	/** 512 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_512,
+	/** 1024 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_1024,
+	/** 2048 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_2048,
+	/** 4096 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_4096,
+	/** 8192 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_8192,
+	/** 16384 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_16384,
+};
+
+/**
+ * \brief WDT Early warning offset.
+ *
+ * This setting determine how many GCLK_WDT cycles before a watchdog time-out period
+ * an early warning interrupt should be triggered.
+ *
+ */
+enum nvm_wdt_early_warning_offset {
+	/** 8 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_8,
+	/** 16 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_16,
+	/** 32 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_32,
+	/** 64 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_64,
+	/** 128 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_128,
+	/** 256 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_256,
+	/** 512 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_512,
+	/** 1024 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_1024,
+	/** 2048 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_2048,
+	/** 4096 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_4096,
+	/** 8192 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_8192,
+	/** 16384 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_16384,
+};
+
+/**
+ * \brief NVM user row fuse setting structure.
+ *
+ * This structure contain the layout of the first 64 bits of the user row
+ * which contain the fuse settings.
+ */
+struct nvm_fusebits {
+	/** Bootloader size */
+	enum nvm_bootloader_size          bootloader_size;
+	/** EEPROM emulation area size */
+	enum nvm_eeprom_emulator_size     eeprom_size;
+#if (SAMC20) || (SAMC21)
+	/** BODVDD Threshold level at power on */
+	uint8_t                           bodvdd_level;
+	/** BODVDD Enable at power on */
+	bool                              bodvdd_enable;
+	/** BODVDD Action at power on */
+	enum nvm_bod33_action             bodvdd_action;
+	/* BODVDD Hysteresis at power on */
+	bool                              bodvdd_hysteresis;
+#else
+	/** BOD33 Threshold level at power on */
+	uint8_t                           bod33_level;
+	/** BOD33 Enable at power on */
+	bool                              bod33_enable;
+	/** BOD33 Action at power on */
+	enum nvm_bod33_action             bod33_action;
+	/* BOD33 Hysteresis at power on */
+	bool                              bod33_hysteresis;
+#endif
+	/** WDT Enable at power on */
+	bool                              wdt_enable;
+	/** WDT Always-on at power on */
+	bool                              wdt_always_on;
+	/** WDT Period at power on */
+	uint8_t                           wdt_timeout_period;
+	/** WDT Window mode time-out at power on */
+	enum nvm_wdt_window_timeout       wdt_window_timeout;
+	/** WDT Early warning interrupt time offset at power on */
+	enum nvm_wdt_early_warning_offset wdt_early_warning_offset;
+	/** WDT Window mode enabled at power on */
+	bool                              wdt_window_mode_enable_at_poweron;
+	/** NVM Lock bits */
+	uint16_t                          lockbits;
+#ifdef FEATURE_BOD12
+	/** BOD12 Threshold level at power on */
+	uint8_t                           bod12_level;
+	/** BOD12 Enable at power on */
+	bool                              bod12_enable;
+	/** BOD12 Action at power on */
+	enum nvm_bod12_action             bod12_action;
+	/* BOD12 Hysteresis at power on */
+	bool                              bod12_hysteresis;
+#endif
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes an NVM controller configuration structure to defaults.
+ *
+ * Initializes a given NVM controller configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Power reduction mode enabled after sleep mode until first NVM access
+ *  \li Automatic page write mode disabled
+ *  \li Number of FLASH wait states left unchanged
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ *
+ */
+static inline void nvm_get_config_defaults(
+		struct nvm_config *const config)
+{
+	/* Sanity check the parameters */
+	Assert(config);
+
+	/* Write the default configuration for the NVM configuration */
+	config->sleep_power_mode  = NVM_SLEEP_POWER_MODE_WAKEONACCESS;
+	config->manual_page_write = true;
+	config->wait_states       = NVMCTRL->CTRLB.bit.RWS;
+	config->disable_cache     = false;
+#if (SAMC20) || (SAMC21)
+	config->disable_rww_cache = false;
+#endif
+	config->cache_readmode    = NVM_CACHE_READMODE_NO_MISS_PENALTY;
+}
+
+enum status_code nvm_set_config(
+		const struct nvm_config *const config);
+
+/**
+ * \brief Checks if the NVM controller is ready to accept a new command.
+ *
+ * Checks the NVM controller to determine if it is currently busy execution an
+ * operation, or ready for a new command.
+ *
+ * \return Busy state of the NVM controller.
+ *
+ * \retval true   If the hardware module is ready for a new command
+ * \retval false  If the hardware module is busy executing a command
+ *
+ */
+static inline bool nvm_is_ready(void)
+{
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	return nvm_module->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
+}
+
+/** @} */
+
+/**
+ * \name NVM Access Management
+ * @{
+ */
+
+void nvm_get_parameters(
+		struct nvm_parameters *const parameters);
+
+enum status_code nvm_write_buffer(
+		const uint32_t destination_address,
+		const uint8_t *buffer,
+		uint16_t length);
+
+enum status_code nvm_read_buffer(
+		const uint32_t source_address,
+		uint8_t *const buffer,
+		uint16_t length);
+
+enum status_code nvm_update_buffer(
+		const uint32_t destination_address,
+		uint8_t *const buffer,
+		uint16_t offset,
+		uint16_t length);
+
+enum status_code nvm_erase_row(
+		const uint32_t row_address);
+
+enum status_code nvm_execute_command(
+		const enum nvm_command command,
+		const uint32_t address,
+		const uint32_t parameter);
+
+enum status_code nvm_get_fuses(struct nvm_fusebits *fusebits);
+enum status_code nvm_set_fuses(struct nvm_fusebits *fb);
+
+bool nvm_is_page_locked(uint16_t page_number);
+
+/**
+ * \brief Retrieves the error code of the last issued NVM operation.
+ *
+ * Retrieves the error code from the last executed NVM operation. Once
+ * retrieved, any error state flags in the controller are cleared.
+ *
+ * \note The \ref nvm_is_ready() function is an exception. Thus, errors
+ *       retrieved after running this function should be valid for the function
+ *       executed before \ref nvm_is_ready().
+ *
+ * \return Error caused by the last NVM operation.
+ *
+ * \retval NVM_ERROR_NONE  No error occurred in the last NVM operation
+ *
+ * \retval NVM_ERROR_LOCK  The last NVM operation attempted to access a locked
+ *                         region
+ * \retval NVM_ERROR_PROG  An invalid NVM command was issued
+ */
+static inline enum nvm_error nvm_get_error(void)
+{
+	enum nvm_error ret_val;
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	/* Mask out non-error bits */
+	ret_val = (enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK);
+
+	/* Clear error flags */
+	nvm_module->STATUS.reg = NVM_ERRORS_MASK;
+
+	/* Return error code from the NVM controller */
+	return ret_val;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_nvm_extra Extra Information for NVM Driver
+ *
+ * \section asfdoc_sam0_nvm_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *  <tr>
+ *   <th>Acronym</th>
+ *   <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *   <td>NVM</td>
+ *   <td>Non-Volatile Memory</td>
+ *  </tr>
+ *  <tr>
+ *   <td>EEPROM</td>
+ *   <td>Electrically Erasable Programmable Read-Only Memory</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_nvm_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_nvm_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_nvm_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Removed BOD12 reference, removed nvm_set_fuses() API</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added functions to read/write fuse settings</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for NVM cache configuration</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Updated initialization function to also enable the digital interface
+ *          clock to the module if it is disabled</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_nvm_exqsg Examples for NVM Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_nvm_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_nvm_basic_use_case
+ *
+ * \page asfdoc_sam0_nvm_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42114E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42114D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42114C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42114B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42114A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* NVM_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.c
new file mode 100644
index 0000000000..96fb85e11c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.c
@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief SAM Operational Amplifier Controller (OPAMP) Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "opamp.h"
+
+void opamp_module_init(void)
+{
+	struct system_clock_source_osculp32k_config config;
+
+	/* Enable the OSCULP32K clock. */
+	system_clock_source_osculp32k_get_config_defaults(&config);
+	system_clock_source_osculp32k_set_config(&config);
+
+	/* Turn on the digital interface clock. */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_OPAMP);
+
+	/* Reset module. */
+	opamp_module_reset();
+
+	/* Enable module. */
+	opamp_module_enable();
+}
+
+static inline void _opamp_get_config_common_defaults(
+		struct opamp_config_common *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->potentiometer_selection = OPAMP_POT_MUX_8R_8R;
+	config->r1_enable = false;
+	config->r2_vcc = false;
+	config->r2_out = false;
+	config->on_demand = false;
+	config->run_in_standby = false;
+	config->bias_value = OPAMP_BIAS_MODE_0;
+	config->analog_out = false;
+}
+
+void opamp0_get_config_defaults(struct opamp0_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	_opamp_get_config_common_defaults(&(config->config_common));
+
+	/* Default configuration values */
+	config->negative_input = OPAMP0_NEG_MUX_OUT0;
+	config->positive_input = OPAMP0_POS_MUX_PIN0;
+	config->r1_connection = OPAMP0_RES1_MUX_GND;
+}
+
+void opamp1_get_config_defaults(struct opamp1_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	_opamp_get_config_common_defaults(&(config->config_common));
+
+	/* Default configuration values */
+	config->negative_input = OPAMP1_NEG_MUX_OUT1;
+	config->positive_input = OPAMP1_POS_MUX_PIN1;
+	config->r1_connection = OPAMP1_RES1_MUX_GND;
+}
+
+void opamp2_get_config_defaults(struct opamp2_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	_opamp_get_config_common_defaults(&(config->config_common));
+
+	/* Default configuration values */
+	config->negative_input = OPAMP2_NEG_MUX_OUT2;
+	config->positive_input = OPAMP2_POS_MUX_PIN2;
+	config->r1_connection = OPAMP2_RES1_MUX_GND;
+}
+
+void opamp0_set_config(struct opamp0_config *const config)
+{
+	uint32_t temp = 0;
+
+	if (config->config_common.r1_enable) {
+		temp |= OPAMP_OPAMPCTRL_RES1EN;
+	}
+
+	if (config->config_common.r2_vcc) {
+		temp |= OPAMP_OPAMPCTRL_RES2VCC;
+	}
+
+	if (config->config_common.r2_out) {
+		temp |= OPAMP_OPAMPCTRL_RES2OUT;
+	}
+
+	if (config->config_common.on_demand) {
+		temp |= OPAMP_OPAMPCTRL_ONDEMAND;
+	}
+
+	if (config->config_common.run_in_standby) {
+		temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
+	}
+
+	if (config->config_common.analog_out) {
+		temp |= OPAMP_OPAMPCTRL_ANAOUT;
+	}
+
+	OPAMP->OPAMPCTRL[0].reg = temp |
+		config->config_common.potentiometer_selection |
+		config->config_common.bias_value |
+		config->negative_input |
+		config->positive_input|
+		config->r1_connection;
+}
+
+void opamp1_set_config(struct opamp1_config *const config)
+{
+	uint32_t temp = 0;
+
+	if (config->config_common.r1_enable) {
+		temp |= OPAMP_OPAMPCTRL_RES1EN;
+	}
+
+	if (config->config_common.r2_vcc) {
+		temp |= OPAMP_OPAMPCTRL_RES2VCC;
+	}
+
+	if (config->config_common.r2_out) {
+		temp |= OPAMP_OPAMPCTRL_RES2OUT;
+	}
+
+	if (config->config_common.on_demand) {
+		temp |= OPAMP_OPAMPCTRL_ONDEMAND;
+	}
+
+	if (config->config_common.run_in_standby) {
+		temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
+	}
+
+	if (config->config_common.analog_out) {
+		temp |= OPAMP_OPAMPCTRL_ANAOUT;
+	}
+
+	OPAMP->OPAMPCTRL[1].reg = temp |
+		config->config_common.potentiometer_selection |
+		config->config_common.bias_value |
+		config->negative_input |
+		config->positive_input|
+		config->r1_connection;
+}
+
+void opamp2_set_config(struct opamp2_config *const config)
+{
+	uint32_t temp = 0;
+
+	if (config->config_common.r1_enable) {
+		temp |= OPAMP_OPAMPCTRL_RES1EN;
+	}
+
+	if (config->config_common.r2_vcc) {
+		temp |= OPAMP_OPAMPCTRL_RES2VCC;
+	}
+
+	if (config->config_common.r2_out) {
+		temp |= OPAMP_OPAMPCTRL_RES2OUT;
+	}
+
+	if (config->config_common.on_demand) {
+		temp |= OPAMP_OPAMPCTRL_ONDEMAND;
+	}
+
+	if (config->config_common.run_in_standby) {
+		temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
+	}
+
+	if (config->config_common.analog_out) {
+		temp |= OPAMP_OPAMPCTRL_ANAOUT;
+	}
+
+	OPAMP->OPAMPCTRL[2].reg = temp |
+		config->config_common.potentiometer_selection |
+		config->config_common.bias_value |
+		config->negative_input |
+		config->positive_input|
+		config->r1_connection;
+}
+
+void opamp_enable(const enum opamp_id number)
+{
+	/* Sanity check arguments */
+	Assert(number);
+
+	/* Enable the OPAMP */
+	if (number == OPAMP_0) {
+		OPAMP->OPAMPCTRL[0].reg |= OPAMP_OPAMPCTRL_ENABLE;
+	} else if (number == OPAMP_1) {
+		OPAMP->OPAMPCTRL[1].reg |= OPAMP_OPAMPCTRL_ENABLE;
+	} else if (number == OPAMP_2) {
+		OPAMP->OPAMPCTRL[2].reg |= OPAMP_OPAMPCTRL_ENABLE;
+	}
+}
+
+void opamp_disable(const enum opamp_id number)
+{
+	/* Sanity check arguments */
+	Assert(number);
+
+	/* Disable the OPAMP */
+	if (number == OPAMP_0) {
+		OPAMP->OPAMPCTRL[0].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
+	} else if (number == OPAMP_1) {
+		OPAMP->OPAMPCTRL[1].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
+	} else if (number == OPAMP_2) {
+		OPAMP->OPAMPCTRL[2].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
+	}
+}
+
+bool opamp_is_ready(const enum opamp_id number)
+{
+	/* Sanity check arguments */
+	Assert(number);
+
+	/* Get the OPAMP output ready status*/
+	if (number == OPAMP_0) {
+		return OPAMP->STATUS.bit.READY0;
+	} else if (number == OPAMP_1) {
+		return OPAMP->STATUS.bit.READY1;
+	} else if (number == OPAMP_2) {
+		return OPAMP->STATUS.bit.READY2;
+	}
+
+	return false;
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.h
new file mode 100644
index 0000000000..7178ff7525
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.h
@@ -0,0 +1,678 @@
+/**
+ * \file
+ *
+ * \brief SAM Operational Amplifier Controller (OPAMP) Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef OPAMP_H_INCLUDED
+#define OPAMP_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_opamp_group SAM Operational Amplifier Controller (OPAMP) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Operational Amplifier Controller functionality.
+ *
+ * The following peripheral is used by this module:
+ *  - OPAMP (Operational Amplifier Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_opamp_prerequisites
+ *  - \ref asfdoc_sam0_opamp_module_overview
+ *  - \ref asfdoc_sam0_opamp_special_considerations
+ *  - \ref asfdoc_sam0_opamp_extra_info
+ *  - \ref asfdoc_sam0_opamp_examples
+ *  - \ref asfdoc_sam0_opamp_api_overview
+ *
+ *
+ * \section asfdoc_sam0_opamp_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_opamp_module_overview Module Overview
+ *
+ * The OPAMP is an individually configurable low power, general purpose operational
+ * amplifier offering a high degree of flexibility and rail-to-rail inputs.
+ *
+ * Each operational amplifier can be configured in standalone operational amplifier
+ * and operational amplifier with built-in feedback. All OPAMPs can be cascaded
+ * to support circuits such as differential amplifiers.
+ * \note For more detail configuration reference, refer to the "Built-in Modes"
+ * section in the device datasheet.
+ *
+ * Each OPAMP has one positive and one negative input which can be flexible chosen
+ * from analog input pins including the output of another OPAMP, internal inputs
+ * such as the DAC or the resistor ladder, and the ground.
+ *
+ * Each OPAMP output can be selected as input for AC or ADC, also available
+ * on I/O pins.
+ *
+ * Four modes are available to select the trade-off between speed and power
+ * consumption to best fit the application requirements and optimize the power
+ * consumption.
+ *
+ * \section asfdoc_sam0_opamp_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_opamp_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_opamp_extra. This includes:
+ *  - \ref asfdoc_sam0_opamp_extra_acronyms
+ *  - \ref asfdoc_sam0_opamp_extra_dependencies
+ *  - \ref asfdoc_sam0_opamp_extra_errata
+ *  - \ref asfdoc_sam0_opamp_extra_history
+ *
+ *
+ * \section asfdoc_sam0_opamp_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_opamp_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_opamp_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief OPAMP ID number enum.
+ */
+enum opamp_id {
+	/** OPAMP 0  */
+	OPAMP_0 = 0,
+	/** OPAMP 1  */
+	OPAMP_1 = 1,
+	/** OPAMP 2  */
+	OPAMP_2 = 2,
+	/** OPAMP number  */
+	OPAMP_NUM,
+};
+
+/**
+ * \brief Negative input MUX selection configuration enum.
+ *
+ * Enum for the negative input of OPAMP0.
+ */
+enum opamp0_neg_mux {
+	/** Negative I/O pin 0 */
+	OPAMP0_NEG_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXNEG(0),
+	/** Resistor ladder 0 taps */
+	OPAMP0_NEG_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXNEG(1),
+	/** OPAMP output */
+	OPAMP0_NEG_MUX_OUT0 = OPAMP_OPAMPCTRL_MUXNEG(2),
+	/** DAC output */
+	OPAMP0_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(3),
+};
+
+/**
+ * \brief Negative input MUX selection configuration enum.
+ *
+ * Enum for the negative input of OPAMP1.
+ */
+enum opamp1_neg_mux {
+	/** Negative I/O pin 1 */
+	OPAMP1_NEG_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXNEG(0),
+	/** Resistor ladder 1 taps */
+	OPAMP1_NEG_MUX_TAP1 = OPAMP_OPAMPCTRL_MUXNEG(1),
+	/** OPAMP output */
+	OPAMP1_NEG_MUX_OUT1 = OPAMP_OPAMPCTRL_MUXNEG(2),
+	/** DAC output */
+	OPAMP1_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(3),
+};
+
+/**
+ * \brief Negative input MUX selection configuration enum.
+ *
+ * Enum for the negative input of OPAMP2.
+ */
+enum opamp2_neg_mux {
+	/** Negative I/O pin 2 */
+	OPAMP2_NEG_MUX_PIN2 = OPAMP_OPAMPCTRL_MUXNEG(0),
+	/** Resistor ladder 2 taps */
+	OPAMP2_NEG_MUX_TAP2 = OPAMP_OPAMPCTRL_MUXNEG(1),
+	/** OPAMP output */
+	OPAMP2_NEG_MUX_OUT2 = OPAMP_OPAMPCTRL_MUXNEG(2),
+	/** Negative I/O pin 0 */
+	OPAMP2_NEG_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXNEG(3),
+	/** Negative I/O pin 1 */
+	OPAMP2_NEG_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXNEG(4),
+	/** DAC output */
+	OPAMP2_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(5),
+};
+
+/**
+ * \brief Positive input MUX selection configuration enum.
+ *
+ * Enum for the positive input of OPAMP0.
+ */
+enum opamp0_pos_mux {
+	/** Positive I/O pin 0 */
+	OPAMP0_POS_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXPOS(0),
+	/** Resistor ladder 0 taps */
+	OPAMP0_POS_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXPOS(1),
+	/** DAC output */
+	OPAMP0_POS_MUX_DAC = OPAMP_OPAMPCTRL_MUXPOS(2),
+	/** Ground */
+	OPAMP0_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
+};
+
+/**
+ * \brief Positive input MUX selection configuration enum.
+ *
+ * Enum for the positive input of OPAMP1.
+ */
+enum opamp1_pos_mux {
+	/** Positive I/O pin 1 */
+	OPAMP1_POS_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXPOS(0),
+	/** Resistor ladder 1 taps */
+	OPAMP1_POS_MUX_TAP1 = OPAMP_OPAMPCTRL_MUXPOS(1),
+	/** OPAMP0 output */
+	OPAMP1_POS_MUX_OUT0 = OPAMP_OPAMPCTRL_MUXPOS(2),
+	/** Ground */
+	OPAMP1_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
+};
+
+/**
+ * \brief Positive input MUX selection configuration enum.
+ *
+ * Enum for the positive input of OPAMP2.
+ */
+enum opamp2_pos_mux {
+	/** Positive I/O pin 2 */
+	OPAMP2_POS_MUX_PIN2 = OPAMP_OPAMPCTRL_MUXPOS(0),
+	/** Resistor ladder 2 taps */
+	OPAMP2_POS_MUX_TAP2 = OPAMP_OPAMPCTRL_MUXPOS(1),
+	/** OPAMP1 output */
+	OPAMP2_POS_MUX_OUT1 = OPAMP_OPAMPCTRL_MUXPOS(2),
+	/** Ground */
+	OPAMP2_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
+	/** Positive I/O pin 0 */
+	OPAMP2_POS_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXPOS(4),
+	/** Positive I/O pin 1 */
+	OPAMP2_POS_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXPOS(5),
+	/** Resistor ladder 0 taps */
+	OPAMP2_POS_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXPOS(6),
+};
+
+/**
+ * \brief Potentiometer selection MUX configuration enum.
+ *
+ * Enum for the potentiometer selection of OPAMP 0 to 2.
+ */
+enum opamp_pot_mux {
+	/** Gain = R2/R1 = 1/7 */
+	OPAMP_POT_MUX_14R_2R = OPAMP_OPAMPCTRL_POTMUX(0),
+	/** Gain = R2/R1 = 1/3 */
+	OPAMP_POT_MUX_12R_4R = OPAMP_OPAMPCTRL_POTMUX(1),
+	/** Gain = R2/R1 = 1 */
+	OPAMP_POT_MUX_8R_8R = OPAMP_OPAMPCTRL_POTMUX(2),
+	/** Gain = R2/R1 = 1 + 2/3 */
+	OPAMP_POT_MUX_6R_10R = OPAMP_OPAMPCTRL_POTMUX(3),
+	/** Gain = R2/R1 = 3 */
+	OPAMP_POT_MUX_4R_12R = OPAMP_OPAMPCTRL_POTMUX(4),
+	/** Gain = R2/R1 = 4 + 1/3 */
+	OPAMP_POT_MUX_3R_13R = OPAMP_OPAMPCTRL_POTMUX(5),
+	/** Gain = R2/R1 = 7 */
+	OPAMP_POT_MUX_2R_14R = OPAMP_OPAMPCTRL_POTMUX(6),
+	/** Gain = R2/R1 = 15 */
+	OPAMP_POT_MUX_R_15R = OPAMP_OPAMPCTRL_POTMUX(7),
+};
+
+/**
+ * \brief Resistor 1 MUX selection configuration enum.
+ *
+ * Enum for the Resistor 1 of OPAMP0.
+ */
+enum opamp0_res1_mux {
+	/** Positive input of OPAMP0 */
+	OPAMP0_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
+	/** Negative input of OPAMP0 */
+	OPAMP0_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
+	/** DAC output */
+	OPAMP0_RES1_MUX_DAC = OPAMP_OPAMPCTRL_RES1MUX(2),
+	/** Ground */
+	OPAMP0_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
+};
+
+/**
+ * \brief Resistor 1 MUX selection configuration enum.
+ *
+ * Enum for the Resistor 1 of OPAMP1.
+ */
+enum opamp1_res1_mux {
+	/** Positive input of OPAMP1 */
+	OPAMP1_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
+	/** Negative input of OPAMP1 */
+	OPAMP1_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
+	/** OPAMP0 output */
+	OPAMP1_RES1_MUX_OUT0 = OPAMP_OPAMPCTRL_RES1MUX(2),
+	/** Ground */
+	OPAMP1_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
+};
+
+/**
+ * \brief Resistor 1 MUX selection configuration enum.
+ *
+ * Enum for the Resistor 1 of OPAMP2.
+ */
+enum opamp2_res1_mux {
+	/** Positive input of OPAMP2 */
+	OPAMP2_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
+	/** Negative input of OPAMP2 */
+	OPAMP2_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
+	/** OPAMP1 output */
+	OPAMP2_RES1_MUX_OUT1 = OPAMP_OPAMPCTRL_RES1MUX(2),
+	/** Ground */
+	OPAMP2_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
+};
+
+/**
+ * \brief Bias mode selection MUX configuration enum.
+ *
+ * Enum for the Bias mode selection of OPAMP 0 to 2.
+ */
+enum opamp_bias_selection {
+	/** Minimum current consumption but the slowest mode */
+	OPAMP_BIAS_MODE_0 = OPAMP_OPAMPCTRL_BIAS(0),
+	/** Low current consumption, slow speed */
+	OPAMP_BIAS_MODE_1 = OPAMP_OPAMPCTRL_BIAS(1),
+	/** High current consumption, fast speed */
+	OPAMP_BIAS_MODE_2 = OPAMP_OPAMPCTRL_BIAS(2),
+	/** Maximum current consumption but the fastest mode */
+	OPAMP_BIAS_MODE_3 = OPAMP_OPAMPCTRL_BIAS(3),
+};
+
+/**
+ * \brief OPAMP 0 to 2 common configuration structure.
+ *
+ *  Common configuration structure for OPAMP 0 to 2.
+ */
+struct opamp_config_common {
+	/**  Potentiometer selection */
+	enum opamp_pot_mux potentiometer_selection;
+	/** If \c true, R1 connected to RES1MUX */
+	bool r1_enable;
+	/** If \c true, resistor ladder to V<SUB>CC</SUB> */
+	bool r2_vcc;
+	/** If \c true, resistor ladder to output */
+	bool r2_out;
+	/** If \c true, the OPAMPx is enabled when a peripheral is requesting
+	 * the OPAMPx to be used as an input. The OPAMPx is
+        * disabled if no peripheral is requesting it as an input. */
+	bool on_demand;
+	/** If \c true, the OPAMPx is not stopped during sleep
+	 *  mode when triggered */
+	bool run_in_standby;
+	/**  Bias mode selection */
+	enum opamp_bias_selection bias_value;
+	/** If \c true, OPAMP output is connected to the ADC or AC input */
+	bool analog_out;
+};
+
+/**
+ * \brief OPAMP 0 configuration structure.
+ *
+ *  Configuration structure for OPAMP 0.
+ */
+struct opamp0_config {
+	/** Negative input MUX selection */
+	enum opamp0_neg_mux negative_input;
+	/** Positive input MUX selection */
+	enum opamp0_pos_mux positive_input;
+	/** Resistor 1 MUX selection */
+	enum opamp0_res1_mux r1_connection;
+	/** If \c true, the comparator will continue to sample during sleep
+	 *  mode when triggered */
+	struct opamp_config_common config_common;
+};
+
+/**
+ * \brief OPAMP 1 configuration structure.
+ *
+ *  Configuration structure for OPAMP 1.
+ */
+struct opamp1_config {
+	/** Negative input MUX selection */
+	enum opamp1_neg_mux negative_input;
+	/** Positive input MUX selection */
+	enum opamp1_pos_mux positive_input;
+	/** Resistor 1 MUX selection */
+	enum opamp1_res1_mux r1_connection;
+	/** If \c true, the comparator will continue to sample during sleep
+	 *  mode when triggered */
+	struct opamp_config_common config_common;
+};
+
+/**
+ * \brief OPAMP 2 configuration structure.
+ *
+ *  Configuration structure for OPAMP 2.
+ */
+struct opamp2_config {
+	/** Negative input MUX selection */
+	enum opamp2_neg_mux negative_input;
+	/** Positive input MUX selection */
+	enum opamp2_pos_mux positive_input;
+	/** Resistor 1 MUX selection */
+	enum opamp2_res1_mux r1_connection;
+	/** If \c true, the comparator will continue to sample during sleep
+	 *  mode when triggered */
+	struct opamp_config_common config_common;
+};
+
+/**
+ * \brief Initializes OPAMP module.
+ *
+ * Resets all registers in the MODULE to their initial state,
+ * and then enable the module.
+ */
+void opamp_module_init(void);
+
+/**
+ * \brief Resets OPAMP module.
+ *
+ * Resets all registers in the MODULE to their initial state,
+ * and the OPAMP will be disabled.
+ */
+static inline void opamp_module_reset(void)
+{
+	/* Reset OPAMP. */
+	OPAMP->CTRLA.reg |= OPAMP_CTRLA_SWRST;
+}
+
+/**
+ * \brief Enables OPAMP module.
+ *
+ * Enable the peripheral. Each OPAMP must also be enabled individually
+ * by the Enable bit in the corresponding OPAMP Control register.
+ *
+ */
+static inline void opamp_module_enable(void)
+{
+	/* Enable OPAMP. */
+	OPAMP->CTRLA.reg |= OPAMP_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disables OPAMP module.
+ *
+ * Disables the peripheral.
+ */
+static inline void opamp_module_disable(void)
+{
+	/* Disable OPAMP. */
+	OPAMP->CTRLA.reg &= ~OPAMP_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Enables OPAMP voltage doubler.
+ *
+ * The analog input MUXes have low resistance, but consume more
+ * power at lower voltages (e.g., driven by the voltage doubler).
+ *
+ */
+static inline void opamp_voltage_doubler_enable(void)
+{
+	struct system_clock_source_osculp32k_config config;
+
+	/* Enable the OSCULP32K clock. */
+	system_clock_source_osculp32k_get_config_defaults(&config);
+	system_clock_source_osculp32k_set_config(&config);
+
+	/* Enable Voltage Doubler. */
+	OPAMP->CTRLA.reg &= ~ OPAMP_CTRLA_LPMUX;
+}
+
+/**
+ * \brief Disables OPAMP voltage doubler.
+ *
+ * The analog input MUXes have high resistance, but consume less power
+ * at lower voltages (e.g., the voltage doubler is disabled).
+ */
+static inline void opamp_voltage_doubler_disable(void)
+{
+	/* Disable Voltage Doubler. */
+	OPAMP->CTRLA.reg |= OPAMP_CTRLA_LPMUX;
+}
+
+/**
+ * \brief Initializes all members of OPAMP0 configuration
+ * structure to safe defaults.
+ *
+ *  Initializes all members of OPAMP0 configuration
+ *  structure to safe defaults. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is setting OPAMP0 as "Voltage Follower", refer to
+ *  the first mode of "Built-in Modes" in the device datasheet.
+ *
+ *  \param[out] config  OPAMP0 configuration structure to initialize to
+ *                       default values
+ */
+void opamp0_get_config_defaults(struct opamp0_config *const config);
+
+/**
+ * \brief Initializes all members of OPAMP1 configuration
+ * structure to safe defaults.
+ *
+ *  Initializes all members of OPAMP1 configuration
+ *  structure to safe defaults. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is setting OPAMP1 as "Voltage Follower", refer to
+ *  the first mode of "Built-in Modes" in the device datasheet.
+ *
+ *  \param[out] config  OPAMP1 configuration structure to initialize to
+ *                       default values
+ */
+void opamp1_get_config_defaults(struct opamp1_config *const config);
+
+/**
+ * \brief Initializes all members of OPAMP2 configuration
+ * structure to safe defaults.
+ *
+ *  Initializes all members of OPAMP2 configuration
+ *  structure to safe defaults. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is setting OPAMP2 as "Voltage Follower", refer to
+ *  the first mode of "Built-in Modes" in the device datasheet.
+ *
+ *  \param[out] config  OPAMP2 configuration structure to initialize to
+ *                       default values
+ */
+void opamp2_get_config_defaults(struct opamp2_config *const config);
+
+/** \brief Writes OPAMP0 configuration to the hardware module.
+ *
+ *  Writes a given OPAMP0 configuration to the hardware  module.
+ *
+ *  \param[in] config       Pointer to the OPAMP0 configuration struct
+ */
+void opamp0_set_config(struct opamp0_config *const config);
+
+/** \brief Writes OPAMP1 configuration to the hardware module.
+ *
+ *  Writes a given OPAMP1 configuration to the hardware  module.
+ *
+ *  \param[in] config       Pointer to the OPAMP1 configuration struct
+ */
+void opamp1_set_config(struct opamp1_config *const config);
+
+/** \brief Writes OPAMP2 configuration to the hardware module.
+ *
+ *  Writes a given OPAMP2 configuration to the hardware  module.
+ *
+ *  \param[in] config       Pointer to the OPAMP2 configuration struct
+ */
+void opamp2_set_config(struct opamp2_config *const config);
+
+/**
+ * \brief Enables an OPAMP that was previously configured.
+ *
+ *  Enables an OPAMP that was previously  configured via a call to
+ *  the set configuration function.
+ *
+ *  \param[in] number      OPAMP number to enable
+ */
+void opamp_enable(const enum opamp_id number);
+
+/**
+ * \brief Disables an OPAMP that was previously enabled.
+ *
+ *  Disables an OPAMP that was previously enabled via a call to
+ *  \ref opamp_enable().
+ *
+ *  \param[in] number      OPAMP number to disable
+ */
+void opamp_disable(const enum opamp_id number);
+
+/**
+ * \brief Checks an OPAMP output ready status.
+ *
+ *  Checks if an OPAMP output is ready.
+ *
+ *  \param[in] number      OPAMP number to check
+ *
+ * \return Ready status of the select OPAMP.
+ *
+ * \retval false If the select OPAMP output is not ready
+ * \retval ture If the select OPAMP output is ready
+
+ */
+bool opamp_is_ready(const enum opamp_id number);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_opamp_extra Extra Information for OPAMP Driver
+ *
+ * \section asfdoc_sam0_opamp_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>OPAMP</td>
+ *		<td>Operational Amplifier Controller</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_opamp_extra_dependencies Dependencies
+ * This driver has no dependencies.
+ *
+ *
+ * \section asfdoc_sam0_opamp_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_opamp_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+  *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_opamp_exqsg Examples for OPAMP Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_opamp_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_opamp_basic_use_case
+ *
+ * \page asfdoc_sam0_opamp_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42446A</td>
+ *		<td>07/2015</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* OPAMP_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac.h
new file mode 100644
index 0000000000..701acf6621
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac.h
@@ -0,0 +1,1017 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Access Controller Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef PAC_H_INCLUDED
+#define PAC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_pac_group SAM Peripheral Access Controller (PAC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontroller provides
+ * an interface for the locking and unlocking of peripheral registers within
+ * the device. When a peripheral is locked, accidental writes to the peripheral
+ * will be blocked and a CPU exception will be raised.
+ *
+ * The following peripherals are used by this module:
+ *  - PAC (Peripheral Access Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_pac_prerequisites
+ *  - \ref asfdoc_sam0_pac_module_overview
+ *  - \ref asfdoc_sam0_pac_special_considerations
+ *  - \ref asfdoc_sam0_pac_extra_info
+ *  - \ref asfdoc_sam0_pac_examples
+ *  - \ref asfdoc_sam0_pac_api_overview
+ *
+ *
+ * \section asfdoc_sam0_pac_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_pac_module_overview Module Overview
+ *
+ * The SAM devices are fitted with a Peripheral Access Controller (PAC)
+ * that can be used to lock and unlock write access to a peripheral's
+ * registers (see \ref asfdoc_sam0_pac_non_write_protected). Locking a
+ * peripheral minimizes the risk of unintended configuration changes to a
+ * peripheral as a consequence of \ref asfdoc_sam0_pac_code_run_away
+ * or use of a \ref asfdoc_sam0_pac_module_pointer.
+ *
+ * Physically, the PAC restricts write access through the AHB bus to registers
+ * used by the peripheral, making the register non-writable. PAC locking of
+ * modules should be implemented in configuration critical applications where
+ * avoiding unintended peripheral configuration changes are to be regarded in
+ * the highest of priorities.
+ *
+ * All interrupt must be disabled while a peripheral is unlocked to make sure
+ * correct lock/unlock scheme is upheld.
+ *
+ * \subsection asfdoc_sam0_pac_locking_scheme Locking Scheme
+ * The module has a built in safety feature requiring that an already locked
+ * peripheral is not relocked, and that already unlocked peripherals are not
+ * unlocked again. Attempting to unlock and already unlocked peripheral, or
+ * attempting to lock a peripheral that is currently locked will generate a
+ * CPU exception. This implies that the implementer must keep
+ * strict control over the peripheral's lock-state before modifying them. With
+ * this added safety, the probability of stopping runaway code increases as
+ * the program pointer can be caught inside the exception handler, and necessary
+ * countermeasures can be initiated. The implementer should also consider using
+ * sanity checks after an unlock has been performed to further increase the
+ * security.
+ *
+ * \subsection asfdoc_sam0_pac_correct_implementation Recommended Implementation
+ * A recommended implementation of the PAC can be seen in
+ * \ref asfdoc_sam0_pac_rec_imp_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_pac_rec_imp_diagram
+ * \dot
+ *	digraph correct {
+ *		subgraph cluster_a {
+ *			style="filled, dotted";
+ *			coler=lightgray;
+ *			init [label="Initialize Peripheral", shape=box];
+ *			lock [label="Lock peripheral", shape=box];
+ *			label="Initialization and code";
+ *			init -> lock;
+ *		}
+ *		subgraph cluster_b {
+ *			cli [label="Disable global interrupts", shape=box,
+ *				style=dotted];
+ *			unlock [label="Unlock peripheral", shape=box];
+ *			sanity [label="Sanity Check", shape=box, style=dotted];
+ *			modify [label="Modify peripheral", shape=box];
+ *			lock2 [label="Lock peripheral", shape=box];
+ *			sei [label="Enable global interrupts", shape=box
+ *				style=dotted];
+*
+ *			label="Peripheral Modification";
+ *			cli -> unlock;
+ *			unlock -> sanity
+ *			sanity -> modify;
+ *			modify -> lock2;
+ *			lock2 -> sei;
+ *		}
+ *		lock -> cli [label=
+ *			"Other initialization\n and enable interrupts if applicable"
+ *				, style=dotted];
+ *	}
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_pac_enabled_interrupt Why Disable Interrupts
+ * Global interrupts must be disabled while a peripheral is unlocked as an
+ * interrupt handler would not know the current state of the peripheral lock. If
+ * the interrupt tries to alter the lock state, it can cause an exception as it
+ * potentially tries to unlock an already unlocked peripheral. Reading current
+ * lock state is to be avoided as it removes the security provided by the PAC
+ * (\ref asfdoc_sam0_pac_check_lock).
+ *
+ * \note Global interrupts should also be disabled when a peripheral is unlocked
+ *       inside an interrupt handler.
+ *
+ * An example to illustrate the potential hazard of not disabling interrupts is
+ * shown in \ref asfdoc_sam0_pac_int_hazard_diagram "the diagram below".
+ *
+ * \anchor asfdoc_sam0_pac_int_hazard_diagram
+ * \dot
+ *	digraph enabled_interrupt {
+ *		subgraph cluster_0{
+ *			label="Main routine";
+ *			{node [style="filled", color=black, fillcolor=white]
+ *			init [label="Initialize and lock peripherals", shape=box];
+ *			main_unlock [label="Unlock peripheral",	shape=box,
+ *				fillcolor=green];
+ *			main_modify [label="Modify peripheral", shape=box];}
+ *			main_lock [label="Lock peripheral", shape=box];
+ *			init -> main_unlock [label="User code"];
+ *			main_unlock -> main_modify;
+ *			main_modify -> main_lock [style=dotted];
+ *		}
+ *		subgraph cluster_1 {
+ *			label="Interrupt handler";
+ *			int_unlock [label="Unlock peripheral", shape=box,
+ *				style=filled, fillcolor=red];
+ *			int_modify [label="Modify peripheral", shape=box];
+ *			int_lock [label="Lock peripheral", shape=box];
+ *			int_unlock -> int_modify [style=dotted];
+ *			int_modify -> int_lock [style=dotted];
+ *		}
+ *		exception [label="Exception", shape=box, style=filled, fillcolor=red];
+ *		main_modify -> int_unlock [label=" Interrupt"];
+ *		int_unlock -> exception;
+ *		exception -> exception;
+ *	}
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_pac_code_run_away Run-away Code
+ * Run-away code can be caused by the MCU being operated outside its
+ * specification, faulty code, or EMI issues. If a runaway code occurs, it is
+ * favorable to catch the issue as soon as possible. With a correct
+ * implementation of the PAC, the runaway code can potentially be stopped.
+ *
+ * A graphical example showing how a PAC implementation will behave for
+ * different circumstances of runaway code in shown in
+ * \ref asfdoc_sam0_pac_code_runaway_diagram "the first" and
+ * \ref asfdoc_sam0_pac_code_runaway_diagram2 "second figures below".
+ *
+ * \anchor asfdoc_sam0_pac_code_runaway_diagram
+ * \dot
+ *	digraph run_away {
+ *	   subgraph cluster_away1{
+ *		rankdir=TB;
+ *		color=white;
+ *		runaway1 [label="Run-away code", shape=box];
+ *		node [shape=plaintext];
+ *		program1 [label=<
+ *			<table>
+ *				<tr>
+ *					<td>PC#</td>
+ *					<td>Code</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0020</td>
+ *					<td>initialize peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0025</td>
+ *					<td>lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>...</td>
+ *					<td>...</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0080</td>
+ *					<td>set sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td port="f0" BGCOLOR="green">...</td>
+ *					<td BGCOLOR="green">...</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0115</td>
+ *					<td BGCOLOR="green">disable interrupts</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0120</td>
+ *					<td BGCOLOR="green">unlock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="red">0x0125</td>
+ *					<td BGCOLOR="red">check sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0130</td>
+ *					<td>modify peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0140</td>
+ *					<td>lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0145</td>
+ *					<td>disable interrupts</td>
+ *				</tr>
+ *			</table>
+ *			>]
+ *			runaway1 -> program1:f0;
+ *			label="1. Run-away code is caught in sanity check.\nA CPU exception is executed."
+ *		}
+ *	   subgraph cluster_away2{
+ *		rankdir=TB;
+ *		runaway2 [label="Run-away code", shape=box];
+ *		color=white;
+ *		node [shape=plaintext];
+ *		program2 [label=<
+ *			<table>
+ *				<tr>
+ *					<td>PC#</td>
+ *					<td>Code</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0020</td>
+ *					<td>initialize peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0025</td>
+ *					<td>lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>...</td>
+ *					<td>...</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0080</td>
+ *					<td>set sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td >...</td>
+ *					<td >...</td>
+ *				</tr>
+ *				<tr>
+ *					<td >0x0115</td>
+ *					<td >disable interrupts</td>
+ *				</tr>
+ *				<tr>
+ *					<td >0x0120</td>
+ *					<td >unlock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td >0x0125</td>
+ *					<td >check sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td port="f0" BGCOLOR="red">0x0130</td>
+ *					<td BGCOLOR="red">modify peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0140</td>
+ *					<td>lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0145</td>
+ *					<td>disable interrupts</td>
+ *				</tr>
+ *			</table>
+ *			>]
+ *			runaway2 -> program2:f0;
+ *			label="2. Run-away code is caught when modifying\nlocked peripheral. A CPU exception is executed."
+ *		}
+ *	}
+ * \enddot
+ *
+ * \anchor asfdoc_sam0_pac_code_runaway_diagram2
+ * \dot
+ *	digraph run_away2 {
+ *	   subgraph cluster_away3{
+ *		rankdir=TB;
+ *		runaway3 [label="Run-away code", shape=box];
+ *		color=white;
+ *		node [shape=plaintext];
+ *		program3 [label=<
+ *			<table>
+ *				<tr>
+ *					<td>PC#</td>
+ *					<td>Code</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0020</td>
+ *					<td>initialize peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0025</td>
+ *					<td>lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>...</td>
+ *					<td>...</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0080</td>
+ *					<td>set sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td >...</td>
+ *					<td >...</td>
+ *				</tr>
+ *				<tr>
+ *					<td >0x0115</td>
+ *					<td >disable interrupts</td>
+ *				</tr>
+ *				<tr>
+ *					<td >0x0120</td>
+ *					<td >unlock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td >0x0125</td>
+ *					<td >check sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td >0x0130</td>
+ *					<td >modify peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td port="f0" BGCOLOR="red">0x0140</td>
+ *					<td BGCOLOR="red">lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0145</td>
+ *					<td>disable interrupts</td>
+ *				</tr>
+ *			</table>
+ *			>]
+ *			runaway3 -> program3:f0;
+ *			label="3. Run-away code is caught when locking\nlocked peripheral. A CPU exception is executed."
+ *		}
+ *	subgraph cluster_away4 {
+ *		rankdir=TB;
+ *		runaway4 [label="Run-away code", shape=box];
+ *		color=white;
+ *		node [shape=plaintext];
+ *		program4 [label=<
+ *			<table>
+ *				<tr>
+ *					<td>PC#</td>
+ *					<td>Code</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0020</td>
+ *					<td>initialize peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0025</td>
+ *					<td>lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td port="f0" BGCOLOR="green">...</td>
+ *					<td BGCOLOR="green">...</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0080</td>
+ *					<td BGCOLOR="green">set sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">...</td>
+ *					<td BGCOLOR="green">...</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0115</td>
+ *					<td BGCOLOR="green">disable interrupts</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0120</td>
+ *					<td BGCOLOR="green">unlock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0125</td>
+ *					<td BGCOLOR="green">check sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0130</td>
+ *					<td BGCOLOR="green">modify peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0140</td>
+ *					<td BGCOLOR="green">lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0145</td>
+ *					<td BGCOLOR="green">disable interrupts</td>
+ *				</tr>
+ *			</table>
+ *			>]
+ *			runaway4 -> program4:f0;
+ *			label="4. Run-away code is not caught.\n "
+ *		}
+ *	}
+ * \enddot
+ *
+ * In the example, green indicates that the command is allowed, red indicates
+ * where the runaway code will be caught, and the arrow where the runaway
+ * code enters the application. In special circumstances, like example 4
+ * above, the runaway code will not be caught. However, the protection scheme
+ * will greatly enhance peripheral configuration security from being affected by
+ * runaway code.
+ *
+ * \subsubsection asfdoc_sam0_pac_bitwise_code Key-Argument
+ * To protect the module functions against runaway code themselves, a key
+ * is required as one of the input arguments. The key-argument will make sure
+ * that runaway code entering the function without a function call will be
+ * rejected before inflicting any damage. The argument is simply set to be
+ * the bitwise inverse of the module flag, i.e.
+ *
+ * \code
+	system_peripheral_<lock_state>(SYSTEM_PERIPHERAL_<module>,
+			~SYSTEM_PERIPHERAL_<module>);
+\endcode
+ *
+ * Where the lock state can be either lock or unlock, and module refer to the
+ * peripheral that is to be locked/unlocked.
+ *
+ * \subsection asfdoc_sam0_pac_module_pointer Faulty Module Pointer
+ * The PAC also protects the application from user errors such as the use of
+ * incorrect module pointers in function arguments, given that the module is
+ * locked. It is therefore recommended that any unused peripheral is locked
+ * during application initialization.
+ *
+ * \subsection asfdoc_sam0_pac_no_inline Use of __no_inline
+ * Using the function attribute \c __no_inline will ensure that there will only be
+ * one copy of each functions in the PAC driver API in the application. This will
+ * lower the likelihood that runaway code will hit any of these functions.
+ *
+ * \subsection asfdoc_sam0_pac_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_pac_int_connections "The diagram below" shows how this
+ * module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_pac_int_connections
+ * \dot
+ * digraph overview {
+ *	nodesep = .05;
+ *	rankdir=LR;
+ *
+ *	ahb [label="Peripheral bus", shape=ellipse, style=filled, fillcolor=lightgray];
+ *	pac [label="<f0>PAC|<f1>Lock|<f2>Open|<f3>Open",
+ *		 height=2.5, shape=record, width=.1];
+ *	per1 [label="Peripheral1", shape=ellipse, style=filled, fillcolor=lightgray];
+ *	per2 [label="Peripheral2", shape=ellipse, style=filled, fillcolor=lightgray];
+ *	per3 [label="Peripheral3", shape=ellipse, style=filled, fillcolor=lightgray];
+ *	edge [dir="both"];
+ *	ahb -> pac:f1 [label="Read/Write"];
+ *	ahb -> pac:f2 [label="Read/Write"];
+ *	ahb -> pac:f3 [label="Read/Write"];
+ *	edge [dir="back"];
+ *	pac:f1 -> per1 [label="Read"];
+ *	edge [dir="both"];
+ *	pac:f2 -> per2 [label="Read/Write"];
+ *	pac:f3 -> per3 [label="Read/Write"];
+ *	{rank=same; per1 per2 per3 }
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_pac_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_pac_non_write_protected Non-Writable Registers
+ * Not all registers in a given peripheral can be set non-writable. Which
+ * registers this applies to is showed in \ref asfdoc_sam0_pac_non_write_list
+ * and the peripheral's subsection "Register Access Protection" in the device
+ * datasheet.
+ *
+ * \subsection asfdoc_sam0_pac_check_lock Reading Lock State
+ * Reading the state of the peripheral lock is to be avoided as it greatly
+ * compromises the protection initially provided by the PAC. If a lock/unlock
+ * is implemented conditionally, there is a risk that eventual errors are not
+ * caught in the protection scheme. Examples indicating the issue are shown
+ * in \ref asfdoc_sam0_pac_lock_errors_diagram "the diagram below".
+ *
+ * \anchor asfdoc_sam0_pac_lock_errors_diagram
+ * \dot
+ *	digraph read_lock {
+ *	   subgraph cluster_read1{
+ *		rankdir=TB;
+ *		color=white;
+ *		runaway1 [label="Run-away code\nwith peripheral unlocked", shape=box];
+ *		node [shape=plaintext];
+ *		program1 [label=<
+ *			<table>
+ *				<tr>
+ *					<td>PC#</td>
+ *					<td>Code</td>
+ *				</tr>
+ *				<tr>
+ *					<td port="f0" BGCOLOR="green">...</td>
+ *					<td BGCOLOR="green">...</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0100</td>
+ *					<td BGCOLOR="green">check if locked</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0102</td>
+ *					<td BGCOLOR="green">disable interrupts</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0105</td>
+ *					<td BGCOLOR="green">unlock if locked</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0110</td>
+ *					<td BGCOLOR="green">check sanity</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0115</td>
+ *					<td BGCOLOR="green">modify peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0120</td>
+ *					<td BGCOLOR="green">lock if previously locked</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0125</td>
+ *					<td BGCOLOR="green">enable interrupts</td>
+ *				</tr>
+ *			</table>
+ *			>]
+ *			runaway1 -> program1:f0;
+ *			label="1. Wrong implementation.\n "
+ *		}
+ *	   subgraph cluster_read2{
+ *		rankdir=TB;
+ *		color=white;
+ *		runaway2 [label="Run-away code\nwith peripheral unlocked", shape=box];
+ *		node [shape=plaintext];
+ *		program2 [label=<
+ *			<table>
+ *				<tr>
+ *					<td>PC#</td>
+ *					<td>Code</td>
+ *				</tr>
+ *				<tr>
+ *					<td port="f0" BGCOLOR="green">...</td>
+ *					<td BGCOLOR="green">...</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="green">0x0100</td>
+ *					<td BGCOLOR="green">disable interrupts</td>
+ *				</tr>
+ *				<tr>
+ *					<td BGCOLOR="red">0x0120</td>
+ *					<td BGCOLOR="red">unlock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0125</td>
+ *					<td>check sanity argument</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0130</td>
+ *					<td>modify peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0140</td>
+ *					<td>lock peripheral</td>
+ *				</tr>
+ *				<tr>
+ *					<td>0x0145</td>
+ *					<td>disable interrupts</td>
+ *				</tr>
+ *			</table>
+ *			>]
+ *			runaway2 -> program2:f0;
+ *
+ *			label="2. Correct implementation.\n "
+ *		}
+ *	}
+ * \enddot
+ *
+ * In the left figure above, one can see the runaway code continues as all
+ * illegal operations are conditional. On the right side figure, the runaway
+ * code is caught as it tries to unlock the peripheral.
+ *
+ * \section asfdoc_sam0_pac_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_pac_extra. This includes:
+ *  - \ref asfdoc_sam0_pac_extra_acronyms
+ *  - \ref asfdoc_sam0_pac_extra_dependencies
+ *  - \ref asfdoc_sam0_pac_extra_errata
+ *  - \ref asfdoc_sam0_pac_extra_history
+ *
+ *
+ * \section asfdoc_sam0_pac_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_pac_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_pac_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Retrieves the ID of a specified peripheral name, giving its peripheral bus
+ * location.
+ *
+ * \param[in] peripheral  Name of the peripheral instance
+ *
+ * \returns Bus ID of the specified peripheral instance.
+ */
+#define SYSTEM_PERIPHERAL_ID(peripheral)    ID_##peripheral
+
+/** \name Peripheral Lock and Unlock
+ * @{
+ */
+__no_inline enum status_code system_peripheral_lock(
+		const uint32_t peripheral_id,
+		const uint32_t key);
+
+__no_inline enum status_code system_peripheral_unlock(
+		const uint32_t peripheral_id,
+		const uint32_t key);
+/** @}  */
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+/** \name APIs available for SAM L21/L22/C20/C21.
+ * @{
+ */
+__no_inline enum status_code system_peripheral_lock_always(
+		const uint32_t peripheral_id,
+		const uint32_t key);
+
+/**
+ * \brief Enable PAC interrupt.
+ *
+ * Enable PAC interrupt so can trigger execution on peripheral access error,
+ * see \ref SYSTEM_Handler().
+ *
+ */
+static inline void system_pac_enable_interrupt(void)
+{
+	PAC->INTENSET.reg = PAC_INTENSET_ERR;
+}
+
+/**
+ * \brief Disable PAC interrupt.
+ *
+ * Disable PAC interrupt on peripheral access error.
+ *
+ */
+static inline void system_pac_disable_interrupt(void)
+{
+	PAC->INTENCLR.reg = PAC_INTENCLR_ERR;
+}
+
+/**
+ * \brief Enable PAC event output.
+ *
+ * Enable PAC event output on peripheral access error.
+ *
+ */
+static inline void system_pac_enable_event(void)
+{
+	PAC->EVCTRL.reg = PAC_EVCTRL_ERREO;
+}
+
+/**
+ * \brief Disable PAC event output.
+ *
+ * Disable PAC event output on peripheral access error.
+ *
+ */
+static inline void system_pac_disable_event(void)
+{
+	PAC->EVCTRL.reg &= (~PAC_EVCTRL_ERREO);
+}
+
+/** @}  */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}  */
+
+/**
+ * \page asfdoc_sam0_pac_extra Extra Information for PAC Driver
+ *
+ * \section asfdoc_sam0_pac_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</td>
+ *		<th>Description</td>
+ *	</tr>
+ *  <tr>
+ *		<td>AC</td>
+ *		<td>Analog Comparator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>ADC</td>
+ *		<td>Analog-to-Digital Converter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>EVSYS</td>
+ *		<td>Event System</td>
+ *	</tr>
+ *	<tr>
+ *		<td>NMI</td>
+ *		<td>Non-Maskable Interrupt</td>
+ *	</tr>
+ *	<tr>
+ *		<td>NVMCTRL</td>
+ *		<td>Non-Volatile Memory Controller</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PAC</td>
+ *		<td>Peripheral Access Controller</td>
+ *	</tr>
+  *	<tr>
+ *		<td>PM</td>
+ *		<td>Power Manager</td>
+ *	</tr>
+ *	<tr>
+ *		<td>RTC</td>
+ *		<td>Real-Time Counter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>Serial Communication Interface</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SYSCTRL</td>
+ *		<td>System Controller</td>
+ *	</tr>
+ *	<tr>
+ *		<td>TC</td>
+ *		<td>Timer/Counter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>WDT</td>
+ *		<td>Watch Dog Timer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_pac_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_pac_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_pac_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_pac_exqsg Examples for PAC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_pac_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_pac_basic_use_case
+ */
+
+/**
+ * \page asfdoc_sam0_pac_non_write_list List of Non-Write Protected Registers
+ *
+ * Look in device datasheet peripheral's subsection "Register Access
+ * Protection" to see which is actually available for your device.
+ * <table>
+ *	<tr>
+ *		<th>Module</th>
+ *		<th>Non-write protected register</th>
+ *	</tr>
+ *	<tr>
+ *		<td>AC</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUSA</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUSB</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUSC</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>ADC</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUS</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>RESULT</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>EVSYS</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>CHSTATUS</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>NVMCTRL</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUS</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>PM</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>PORT</td>
+ *		<td>N/A</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>RTC</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>READREQ</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUS</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>SYSCTRL</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>INTFALG</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUS</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>DATA</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>TC</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUS</td>
+ *	</tr>
+ *	<tr><td colspan="2"/></tr>
+ *	<tr>
+ *		<td>WDT</td>
+ *		<td>INTFLAG</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>STATUS</td>
+ *	</tr>
+ *	<tr>
+ *		<td></td>
+ *		<td>(CLEAR)</td>
+ *	</tr>
+ * </table>
+ *
+ * \page asfdoc_sam0_pac_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42107F</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM C20/C21, SAM D09, and SAM DA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42107E</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42107D</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42107C</td>
+ *		<td>10/2013</td>
+ *		<td>Extended acronyms list</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42107B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42107A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* PAC_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_d_r_h/pac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_d_r_h/pac.c
new file mode 100644
index 0000000000..71c2e2bc0d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_d_r_h/pac.c
@@ -0,0 +1,171 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Access Controller Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "pac.h"
+
+/**
+ * \brief Lock a given peripheral's control registers.
+ *
+ * Locks a given peripheral's control registers, to deny write access to the
+ * peripheral to prevent accidental changes to the module's configuration.
+ *
+ * \warning Locking an already locked peripheral will cause a hard fault
+ *          exception, and terminate program execution.
+ *
+ * \param[in] peripheral_id  ID for the peripheral to be locked, sourced via the
+ *                           \ref SYSTEM_PERIPHERAL_ID macro.
+ * \param[in] key  Bitwise inverse of peripheral ID, used as key to
+ *                 reduce the chance of accidental locking. See
+ *                 \ref asfdoc_sam0_pac_bitwise_code.
+ *
+ * \return Status of the peripheral lock procedure.
+ * \retval STATUS_OK                If the peripheral was successfully locked.
+ * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied.
+ */
+__no_inline enum status_code system_peripheral_lock(
+		const uint32_t peripheral_id,
+		const uint32_t key)
+{
+	/* Bit to be set in desired register is given by bit 5:0 */
+	uint8_t register_bit_pos = peripheral_id % 32;
+	UNUSED(register_bit_pos);
+
+	/* Value of which PAC register to use is given by bit 31:6 */
+	uint8_t register_pos = peripheral_id / 32;
+
+	/* Check if key is correct. */
+	if (~peripheral_id != key) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	switch (register_pos) {
+#ifdef PAC0
+		case 0:
+			PAC0->WPSET.reg = (1 << register_bit_pos);
+			break;
+#endif
+#ifdef PAC1
+		case 1:
+			PAC1->WPSET.reg = (1 << register_bit_pos);
+			break;
+#endif
+#ifdef PAC2
+		case 2:
+			/* Turn on the digital interface clock */
+			system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_PAC2);
+			PAC2->WPSET.reg = (1 << register_bit_pos);
+			break;
+#endif
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unlock a given peripheral's control registers.
+ *
+ * Unlocks a given peripheral's control registers, allowing write access to the
+ * peripheral so that changes can be made to the module's configuration.
+ *
+ * \warning Unlocking an already locked peripheral will cause a hard fault
+ *          exception, and terminate program execution.
+ *
+ * \param[in] peripheral_id  ID for the peripheral to be unlocked, sourced via the
+ *                          \ref SYSTEM_PERIPHERAL_ID macro.
+ * \param[in] key  Bitwise inverse of peripheral ID, used as key to
+ *                 reduce the chance of accidental unlocking. See
+ *                 \ref asfdoc_sam0_pac_bitwise_code.
+ *
+ * \return Status of the peripheral unlock procedure.
+ * \retval STATUS_OK                If the peripheral was successfully locked.
+ * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied.
+ */
+__no_inline enum status_code system_peripheral_unlock(
+		const uint32_t peripheral_id,
+		const uint32_t key)
+{
+	/* Bit to be set in desired register is given by bit 5:0 */
+	uint8_t register_bit_pos = peripheral_id % 32;
+	UNUSED(register_bit_pos);
+
+	/* Value of which PAC register to use is given by bit 31:6 */
+	uint8_t register_pos = peripheral_id / 32;
+
+	/* Check if key is correct. */
+	if (~peripheral_id != key) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	switch (register_pos) {
+#ifdef PAC0
+		case 0:
+			PAC0->WPCLR.reg = (1 << register_bit_pos);
+			break;
+#endif
+#ifdef PAC1
+		case 1:
+			PAC1->WPCLR.reg = (1 << register_bit_pos);
+			break;
+#endif
+#ifdef PAC2
+		case 2:
+			/* Turn on the digital interface clock */
+			system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_PAC2);
+			PAC2->WPCLR.reg = (1 << register_bit_pos);
+			break;
+#endif
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_l_c/pac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_l_c/pac.c
new file mode 100644
index 0000000000..4e61cd53d5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_l_c/pac.c
@@ -0,0 +1,150 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Access Controller Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "pac.h"
+
+/**
+ * \brief Lock a given peripheral's control registers.
+ *
+ * Locks a given peripheral's control registers, to deny write access to the
+ * peripheral to prevent accidental changes to the module's configuration.
+ *
+ * \warning Locking an already locked peripheral will cause a CPU
+ *          exception, and terminate program execution.
+ *
+ * \param[in] peripheral_id  ID for the peripheral to be locked, sourced via the
+ *                           \ref SYSTEM_PERIPHERAL_ID macro
+ * \param[in] key  Bitwise inverse of peripheral ID, used as key to
+ *                 reduce the chance of accidental locking. See
+ *                 \ref asfdoc_sam0_pac_bitwise_code
+ *
+ * \return Status of the peripheral lock procedure.
+ * \retval STATUS_OK                If the peripheral was successfully locked
+ * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied
+ */
+__no_inline enum status_code system_peripheral_lock(
+		const uint32_t peripheral_id,
+		const uint32_t key)
+{
+	/* Check if key is correct. */
+	if (~peripheral_id != key) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_SET_Val);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Lock a given peripheral's control registers until hardware reset.
+ *
+ * Locks a given peripheral's control registers, to deny write access to the
+ * peripheral to prevent accidental changes to the module's configuration.
+ * After lock, the only way to unlock is hardware reset.
+ *
+ * \warning Locking an already locked peripheral will cause a CPU
+ *          exception, and terminate program execution.
+ *
+ * \param[in] peripheral_id  ID for the peripheral to be locked, sourced via the
+ *                           \ref SYSTEM_PERIPHERAL_ID macro
+ * \param[in] key  Bitwise inverse of peripheral ID, used as key to
+ *                 reduce the chance of accidental locking. See
+ *                 \ref asfdoc_sam0_pac_bitwise_code
+ *
+ * \return Status of the peripheral lock procedure.
+ * \retval STATUS_OK                If the peripheral was successfully locked
+ * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied
+ */
+__no_inline enum status_code system_peripheral_lock_always(
+		const uint32_t peripheral_id,
+		const uint32_t key)
+{
+	/* Check if key is correct. */
+	if (~peripheral_id != key) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_SETLCK_Val);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unlock a given peripheral's control registers.
+ *
+ * Unlocks a given peripheral's control registers, allowing write access to the
+ * peripheral so that changes can be made to the module's configuration.
+ *
+ * \warning Unlocking an already locked peripheral will cause a CUP
+ *          exception, and terminate program execution.
+ *
+ * \param[in] peripheral_id  ID for the peripheral to be unlocked, sourced via the
+ *                          \ref SYSTEM_PERIPHERAL_ID macro
+ * \param[in] key  Bitwise inverse of peripheral ID, used as key to
+ *                 reduce the chance of accidental unlocking. See
+ *                 \ref asfdoc_sam0_pac_bitwise_code
+ *
+ * \return Status of the peripheral unlock procedure.
+ * \retval STATUS_OK                If the peripheral was successfully locked
+ * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied
+ */
+__no_inline enum status_code system_peripheral_unlock(
+		const uint32_t peripheral_id,
+		const uint32_t key)
+{
+	/* Check if key is correct. */
+	if (~peripheral_id != key) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_CLR_Val);
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.c
new file mode 100644
index 0000000000..64787c6e54
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.c
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <port.h>
+
+/**
+ *  \brief Writes a Port pin configuration to the hardware module.
+ *
+ *  Writes out a given configuration of a Port pin configuration to the hardware
+ *  module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to configure
+ *  \param[in] config    Configuration settings for the pin
+ */
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+}
+
+/**
+ *  \brief Writes a Port group configuration group to the hardware module.
+ *
+ *  Writes out a given configuration of a Port group configuration to the
+ *  hardware module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[out] port    Base of the PORT module to write to
+ *  \param[in]  mask    Mask of the port pin(s) to configure
+ *  \param[in]  config  Configuration settings for the pin group
+ */
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(port);
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_group_set_config(port, mask, &pinmux_config);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.h
new file mode 100644
index 0000000000..cdb342ec95
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.h
@@ -0,0 +1,793 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef PORT_H_INCLUDED
+#define PORT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_port_group SAM Port (PORT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's General
+ * Purpose Input/Output (GPIO) pin functionality, for manual pin state reading
+ * and writing.
+ *
+ * The following peripheral is used by this module:
+ *  - PORT (GPIO Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_port_prerequisites
+ *  - \ref asfdoc_sam0_port_module_overview
+ *  - \ref asfdoc_sam0_port_special_considerations
+ *  - \ref asfdoc_sam0_port_extra_info
+ *  - \ref asfdoc_sam0_port_examples
+ *  - \ref asfdoc_sam0_port_api_overview
+ *
+ *
+ * \section asfdoc_sam0_port_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_port_module_overview Module Overview
+ *
+ * The device GPIO (PORT) module provides an interface between the user
+ * application logic and external hardware peripherals, when general pin state
+ * manipulation is required. This driver provides an easy-to-use interface to
+ * the physical pin input samplers and output drivers, so that pins can be read
+ * from or written to for general purpose external hardware control.
+ *
+ * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_PORT_INPUT_EVENT</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
+ * this module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_port_module_int_connections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="GPIO Module" shape=ellipse] gpio;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> gpio;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_port_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampler can be disabled when the pin is configured
+ * in pure output mode to save power; reading the pin state of a pin configured
+ * in output-only mode will read the logical output state that was last set.
+ *
+ * \section asfdoc_sam0_port_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_port_extra. This includes:
+ *  - \ref asfdoc_sam0_port_extra_acronyms
+ *  - \ref asfdoc_sam0_port_extra_dependencies
+ *  - \ref asfdoc_sam0_port_extra_errata
+ *  - \ref asfdoc_sam0_port_extra_history
+ *
+ *
+ * \section asfdoc_sam0_port_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_port_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_port_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define port features set according to different device family.
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+/** Event input control feature support for PORT group. */
+#  define FEATURE_PORT_INPUT_EVENT
+#endif
+/*@}*/
+
+/** \name PORT Alias Macros
+ * @{
+ */
+
+/** Convenience definition for GPIO module group A on the device (if
+ *  available). */
+#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
+#  define PORTA             PORT->Group[0]
+#endif
+
+#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group B on the device (if
+ *  available). */
+#  define PORTB             PORT->Group[1]
+#endif
+
+#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group C on the device (if
+ *  available). */
+#  define PORTC             PORT->Group[2]
+#endif
+
+#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group D on the device (if
+ *  available). */
+#  define PORTD             PORT->Group[3]
+#endif
+
+/** @} */
+
+/**
+ *  \brief Port pin direction configuration enum.
+ *
+ *  Enum for the possible pin direction settings of the port pin configuration
+ *  structure, to indicate the direction the pin should use.
+ */
+enum port_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read */
+	PORT_PIN_DIR_INPUT               = SYSTEM_PINMUX_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set */
+	PORT_PIN_DIR_OUTPUT              = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+	/** The pin's output and input buffers should be enabled, so that the pin
+	 *  state can be set and read back */
+	PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ *  \brief Port pin input pull configuration enum.
+ *
+ *  Enum for the possible pin pull settings of the port pin configuration
+ *  structure, to indicate the type of logic level pull the pin should use.
+ */
+enum port_pin_pull {
+	/** No logical pull should be applied to the pin */
+	PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	PORT_PIN_PULL_UP   = SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Pin should be pulled down when idle */
+	PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+/**
+ *  \brief Port input event action.
+ *
+ *  List of port input events action on pin.
+ */
+enum port_input_event_action {
+	/** Event out to pin */
+	PORT_INPUT_EVENT_ACTION_OUT = 0,
+	/** Set output register of pin on event */
+	PORT_INPUT_EVENT_ACTION_SET,
+	/** Clear output register pin on event */
+	PORT_INPUT_EVENT_ACTION_CLR,
+	/** Toggle output register pin on event */
+	PORT_INPUT_EVENT_ACTION_TGL,
+};
+
+/**
+ *  \brief Port input event.
+ *
+ *  List of port input events.
+ */
+enum port_input_event{
+	/** Port input event 0 */
+	PORT_INPUT_EVENT_0 = 0,
+	/** Port input event 1 */
+	PORT_INPUT_EVENT_1 = 1,
+	/** Port input event 2 */
+	PORT_INPUT_EVENT_2 = 2,
+	/** Port input event 3 */
+	PORT_INPUT_EVENT_3 = 3,
+};
+
+/**
+ *  \brief Port input event configuration structure.
+ *
+ *  Configuration structure for a port input event.
+ */
+struct port_input_event_config{
+	/** Port input event action */
+	enum port_input_event_action  action;
+	/** GPIO pin */
+	uint8_t gpio_pin;
+};
+#endif
+
+/**
+ *  \brief Port pin configuration structure.
+ *
+ *  Configuration structure for a port pin instance. This structure should be
+ *  initialized by the \ref port_get_config_defaults() function before being
+ *  modified by the user application.
+ */
+struct port_config {
+	/** Port buffer input/output direction */
+	enum port_pin_dir  direction;
+
+	/** Port pull-up/pull-down for input pins */
+	enum port_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled.
+	 */
+	bool powersave;
+};
+
+/** \name State Reading/Writing (Physical Group Orientated)
+ * @{
+ */
+
+/**
+ *  \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ *  Retrieves the PORT module group instance associated with a given logical
+ *  GPIO pin number.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to convert
+ *
+ *  \return Base address of the associated PORT module.
+ */
+static inline PortGroup* port_get_group_from_gpio_pin(
+		const uint8_t gpio_pin)
+{
+	return system_pinmux_get_group_from_gpio_pin(gpio_pin);
+}
+
+/**
+ *  \brief Retrieves the state of a group of port pins that are configured as inputs.
+ *
+ *  Reads the current logic level of a port module's pins and returns the
+ *  current levels as a bitmask.
+ *
+ *  \param[in] port  Base of the PORT module to read from
+ *  \param[in] mask  Mask of the port pin(s) to read
+ *
+ *  \return Status of the port pin(s) input buffers.
+ */
+static inline uint32_t port_group_get_input_level(
+		const PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	return (port->IN.reg & mask);
+}
+
+/**
+ *  \brief Retrieves the state of a group of port pins that are configured as outputs.
+ *
+ *  Reads the current logical output level of a port module's pins and returns
+ *  the current levels as a bitmask.
+ *
+ *  \param[in] port  Base of the PORT module to read from
+ *  \param[in] mask  Mask of the port pin(s) to read
+ *
+ *  \return Status of the port pin(s) output buffers.
+ */
+static inline uint32_t port_group_get_output_level(
+		const PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	return (port->OUT.reg & mask);
+}
+
+/**
+ *  \brief Sets the state of a group of port pins that are configured as outputs.
+ *
+ *  Sets the current output level of a port module's pins to a given logic
+ *  level.
+ *
+ *  \param[out] port        Base of the PORT module to write to
+ *  \param[in]  mask        Mask of the port pin(s) to change
+ *  \param[in]  level_mask  Mask of the port level(s) to set
+ */
+static inline void port_group_set_output_level(
+		PortGroup *const port,
+		const uint32_t mask,
+		const uint32_t level_mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	port->OUTSET.reg = (mask &  level_mask);
+	port->OUTCLR.reg = (mask & ~level_mask);
+}
+
+/**
+ *  \brief Toggles the state of a group of port pins that are configured as an outputs.
+ *
+ *  Toggles the current output levels of a port module's pins.
+ *
+ *  \param[out] port  Base of the PORT module to write to
+ *  \param[in]  mask  Mask of the port pin(s) to toggle
+ */
+static inline void port_group_toggle_output_level(
+		PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	port->OUTTGL.reg = mask;
+}
+
+/** @} */
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ *  \brief Initializes a Port pin/group configuration structure to defaults.
+ *
+ *  Initializes a given Port pin/group configuration structure to a set of
+ *  known default values. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Input mode with internal pull-up enabled
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void port_get_config_defaults(
+		struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->direction  = PORT_PIN_DIR_INPUT;
+	config->input_pull = PORT_PIN_PULL_UP;
+	config->powersave  = false;
+}
+
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config);
+
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config);
+
+/** @} */
+
+/** \name State Reading/Writing (Logical Pin Orientated)
+ * @{
+ */
+
+/**
+ *  \brief Retrieves the state of a port pin that is configured as an input.
+ *
+ *  Reads the current logic level of a port pin and returns the current
+ *  level as a Boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read
+ *
+ *  \return Status of the port pin's input buffer.
+ */
+static inline bool port_pin_get_input_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	return (port_base->IN.reg & pin_mask);
+}
+
+/**
+ *  \brief Retrieves the state of a port pin that is configured as an output.
+ *
+ *  Reads the current logical output level of a port pin and returns the current
+ *  level as a Boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read
+ *
+ *  \return Status of the port pin's output buffer.
+ */
+static inline bool port_pin_get_output_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	return (port_base->OUT.reg & pin_mask);
+}
+
+/**
+ *  \brief Sets the state of a port pin that is configured as an output.
+ *
+ *  Sets the current output level of a port pin to a given logic level.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to write to
+ *  \param[in] level     Logical level to set the given pin to
+ */
+static inline void port_pin_set_output_level(
+		const uint8_t gpio_pin,
+		const bool level)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Set the pin to high or low atomically based on the requested level */
+	if (level) {
+		port_base->OUTSET.reg = pin_mask;
+	} else {
+		port_base->OUTCLR.reg = pin_mask;
+	}
+}
+
+/**
+ *  \brief Toggles the state of a port pin that is configured as an output.
+ *
+ *  Toggles the current output level of a port pin.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to toggle
+ */
+static inline void port_pin_toggle_output_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Toggle pin output level */
+	port_base->OUTTGL.reg = pin_mask;
+}
+
+/** @} */
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+
+/** \name Port Input Event
+ * @{
+ */
+
+/**
+ *  \brief Enable the port event input.
+ *
+ *  Enable the port event input with the given pin and event.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin
+ *  \param[in] n  Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code port_enable_input_event(
+		const uint8_t gpio_pin,
+		const enum port_input_event n)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ *  \brief Disable the port event input.
+ *
+ *  Disable the port event input with the given pin and event.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin
+ *  \param[in] gpio_pin  Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code port_disable_input_event(
+		const uint8_t gpio_pin,
+		const enum port_input_event n)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieve the default configuration for port input event.
+ *
+ * Fills a configuration structure with the default configuration for port input event:
+ *   - Event output to pin
+ *   - Event action to be executed on PIN 0
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void port_input_event_get_config_defaults(
+		struct port_input_event_config *const config)
+{
+	Assert(config);
+	config->action   = PORT_INPUT_EVENT_ACTION_OUT;
+	config->gpio_pin = 0;
+}
+
+/**
+ * \brief Configure port input event.
+ *
+ * Configures port input event with the given configuration settings.
+ *
+ * \param[in] config  Port input even configuration structure containing the new config
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+
+static inline enum status_code port_input_event_set_config(
+		const enum port_input_event n,
+		struct port_input_event_config *const config)
+{
+	Assert(config);
+	PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
+	uint8_t pin_index = config->gpio_pin % 32;
+	struct port_config pin_conf;
+
+	port_get_config_defaults(&pin_conf);
+	/* Configure the GPIO pin as outputs*/
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(config->gpio_pin, &pin_conf);
+
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+									| PORT_EVCTRL_PID0(pin_index);
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
+						   		   | PORT_EVCTRL_PID1(pin_index);
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
+						   		   | PORT_EVCTRL_PID2(pin_index);
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
+						   		   | PORT_EVCTRL_PID3(pin_index);
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/** @} */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_port_extra Extra Information for PORT Driver
+ *
+ * \section asfdoc_sam0_port_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_port_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_port_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_port_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added input event feature</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_port_exqsg Examples for PORT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_port_basic_use_case
+ *
+ * \page asfdoc_sam0_port_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113E</td>
+ *		<td>12/2015</td>
+ *		<td>Added input event feature.
+ *			Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.c
new file mode 100644
index 0000000000..05ebbad5a1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.c
@@ -0,0 +1,476 @@
+/**
+ * \file
+ *
+ * \brief SAM PWM Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "pwm.h"
+#include "system_sam_b.h"
+
+/**
+ * \internal Get the register configuration values by PWM device
+ */
+static uint32_t _pwm_reg_output_polarity(enum pwm_device_select device_select)
+{
+	switch (device_select) {
+		case PWM0:
+			return LPMCU_MISC_REGS_PWM0_CTRL_OUTPUT_POLARITY;
+		case PWM1:
+			return LPMCU_MISC_REGS_PWM1_CTRL_OUTPUT_POLARITY;
+		case PWM2:
+			return LPMCU_MISC_REGS_PWM2_CTRL_OUTPUT_POLARITY;
+		case PWM3:
+			return LPMCU_MISC_REGS_PWM3_CTRL_OUTPUT_POLARITY;
+
+		default:
+			return 0;
+	}
+}
+
+/**
+ * \internal Get the register configuration values by PWM device
+ */
+static uint32_t _pwm_reg_agcdata_fmt(enum pwm_device_select device_select)
+{
+	switch (device_select) {
+		case PWM0:
+			return LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_FMT;
+		case PWM1:
+			return LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_FMT;
+		case PWM2:
+			return LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_FMT;
+		case PWM3:
+			return LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_FMT;
+
+		default:
+			return 0;
+	}
+}
+
+/**
+ * \internal Get the register configuration values by PWM device
+ */
+static uint32_t _pwm_reg_sample_method(enum pwm_device_select device_select, bool value)
+{
+	switch (device_select) {
+		case PWM0:
+			return (LPMCU_MISC_REGS_PWM0_CTRL_SAMPLE_METHOD &
+					((value) << LPMCU_MISC_REGS_PWM0_CTRL_SAMPLE_METHOD_Pos));
+		case PWM1:
+			return (LPMCU_MISC_REGS_PWM1_CTRL_SAMPLE_METHOD &
+					((value) << LPMCU_MISC_REGS_PWM1_CTRL_SAMPLE_METHOD_Pos));
+		case PWM2:
+			return (LPMCU_MISC_REGS_PWM2_CTRL_SAMPLE_METHOD &
+					((value) << LPMCU_MISC_REGS_PWM2_CTRL_SAMPLE_METHOD_Pos));
+		case PWM3:
+			return (LPMCU_MISC_REGS_PWM3_CTRL_SAMPLE_METHOD & 
+					((value) << LPMCU_MISC_REGS_PWM3_CTRL_SAMPLE_METHOD_Pos));
+
+		default:
+			return 0;
+	}
+}
+
+/**
+ * \internal Get the register configuration values by PWM device
+ */
+static uint32_t _pwm_reg_period(enum pwm_device_select device_select, enum pwm_period value)
+{
+	switch (device_select) {
+		case PWM0:
+			return LPMCU_MISC_REGS_PWM0_CTRL_PWM_PERIOD(value);
+		case PWM1:
+			return LPMCU_MISC_REGS_PWM1_CTRL_PWM_PERIOD(value);
+		case PWM2:
+			return LPMCU_MISC_REGS_PWM2_CTRL_PWM_PERIOD(value);
+		case PWM3:
+			return LPMCU_MISC_REGS_PWM3_CTRL_PWM_PERIOD(value);
+
+		default:
+			return 0;
+	}
+}
+
+/**
+ * \internal Get the register configuration values by PWM device
+ */
+static uint32_t _pwm_reg_agcdata_in(
+				enum pwm_device_select device_select, \
+				bool agcdata_format, \
+				uint8_t duty_cycle)
+{
+	int32_t agcdata_in;
+
+	if (agcdata_format) {
+		agcdata_in = (uint16_t)((1024 * duty_cycle) / 100);
+	} else {
+		agcdata_in = (int16_t)((1024 * duty_cycle) / 100 - 512);
+	}
+	switch (device_select) {
+		case PWM0:
+			return LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_IN(agcdata_in);
+		case PWM1:
+			return LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_IN(agcdata_in);
+		case PWM2:
+			return LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_IN(agcdata_in);
+		case PWM3:
+			return LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_IN(agcdata_in);
+
+		default:
+			return 0;
+	}
+}
+
+/**
+ * \internal Get the register configuration values by PWM device
+ */
+static uint32_t _pwm_reg_clock_sel(enum pwm_device_select device_select, enum pwm_clock_select value)
+{
+	switch (device_select) {
+		case PWM0:
+			return LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL(value);
+		case PWM1:
+			return LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL(value);
+		case PWM2:
+			return LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL(value);
+		case PWM3:
+			return LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL(value);
+
+		default:
+			return 0;
+	}
+}
+
+/**
+ *  \brief Initializes a pwm configuration structure to defaults.
+ *
+ *  Initializes a given pwm configuration structure to a set of
+ *  known default values. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Not to inverse the polarity
+ *   \li Sample method 0
+ *   \li PWM period is 4
+ *   \li Duty cycle is 50%
+ *   \li Clock is 26MHz
+ *   \li Output frequency is 25.4KHz
+ *   \li Pinmux pad
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+void pwm_get_config_defaults(struct pwm_config *const config)
+{
+	config->output_polarity = false;
+	config->agcdata_format = false;
+	config->sample_method = PWM_SAMPLE_METHOD_0;
+	config->period = PWM_PERIOD_4;
+	config->duty_cycle = 50;
+	config->clock_select = PWM_CLOCK_SELECT_26_0;
+	config->pin_number_pad = 0;
+	config->pinmux_sel_pad = 0;
+}
+
+/**
+ * \brief Set the duty cycle of the PWM module.
+ *
+ * This function will set the duty cycle of the PWM module, based on the values
+ * of setting.
+ *
+ * \param[in]   device_select   PWM device
+ * \param[in]   duty_cycle      This value specifies the duty cycle(%)
+ */
+void pwm_set_duty_cycle(enum pwm_device_select device_select, \
+					uint8_t duty_cycle)
+{
+	bool agcdata_format;
+	uint32_t temp;
+
+	switch(device_select) {
+		case PWM0:
+			agcdata_format = LPMCU_MISC_REGS0->PWM0_CTRL.bit.AGCDATA_FMT;
+			temp = LPMCU_MISC_REGS0->PWM0_CTRL.reg;
+			temp &= ~LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_IN_Msk;
+			temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
+			LPMCU_MISC_REGS0->PWM0_CTRL.reg = temp;
+			break;
+
+		case PWM1:
+			agcdata_format = LPMCU_MISC_REGS0->PWM1_CTRL.bit.AGCDATA_FMT;
+			temp = LPMCU_MISC_REGS0->PWM1_CTRL.reg;
+			temp &= ~LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_IN_Msk;
+			temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
+			LPMCU_MISC_REGS0->PWM1_CTRL.reg = temp;
+			break;
+
+		case PWM2:
+			agcdata_format = LPMCU_MISC_REGS0->PWM2_CTRL.bit.AGCDATA_FMT;
+			temp = LPMCU_MISC_REGS0->PWM2_CTRL.reg;
+			temp &= ~LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_IN_Msk;
+			temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
+			LPMCU_MISC_REGS0->PWM2_CTRL.reg = temp;
+			break;
+
+		case PWM3:
+			agcdata_format = LPMCU_MISC_REGS0->PWM3_CTRL.bit.AGCDATA_FMT;
+			temp = LPMCU_MISC_REGS0->PWM3_CTRL.reg;
+			temp &= ~LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_IN_Msk;
+			temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
+			LPMCU_MISC_REGS0->PWM3_CTRL.reg = temp;
+			break;
+	}
+}
+
+/**
+ * \brief Set the period of the PWM module.
+ *
+ * This function will set the frequence of the PWM module, based on the values
+ * of setting period.
+ *
+ * \param[in]   device_select   PWM device
+ * \param[in]   period          Programmable PWM update period
+ */
+void pwm_set_period(enum pwm_device_select device_select, \
+					enum pwm_period period)
+{
+	uint32_t reg_value;
+	uint32_t temp;
+
+	if (period > PWM_PERIOD_8) {
+		reg_value = PWM_PERIOD_4;
+	}
+	reg_value = _pwm_reg_period(device_select, period);
+
+	switch(device_select) {
+		case PWM0:
+			temp = LPMCU_MISC_REGS0->PWM0_CTRL.reg;
+			temp &= ~LPMCU_MISC_REGS_PWM0_CTRL_PWM_PERIOD_Msk;
+			temp |= reg_value;
+			LPMCU_MISC_REGS0->PWM0_CTRL.reg = temp;
+			break;
+
+		case PWM1:
+			temp = LPMCU_MISC_REGS0->PWM1_CTRL.reg;
+			temp &= ~LPMCU_MISC_REGS_PWM1_CTRL_PWM_PERIOD_Msk;
+			temp |= reg_value;
+			LPMCU_MISC_REGS0->PWM1_CTRL.reg = temp;
+			break;
+
+		case PWM2:
+			temp = LPMCU_MISC_REGS0->PWM2_CTRL.reg;
+			temp &= ~LPMCU_MISC_REGS_PWM2_CTRL_PWM_PERIOD_Msk;
+			temp |= reg_value;
+			LPMCU_MISC_REGS0->PWM2_CTRL.reg = temp;
+			break;
+
+		case PWM3:
+			temp = LPMCU_MISC_REGS0->PWM3_CTRL.reg;
+			temp &= ~LPMCU_MISC_REGS_PWM3_CTRL_PWM_PERIOD_Msk;
+			temp |= reg_value;
+			LPMCU_MISC_REGS0->PWM3_CTRL.reg = temp;
+			break;
+	}
+}
+
+/**
+ * \brief Initializes the PWM module
+ *
+ * This function will initialize the PWM module, based on the values
+ * of the config struct.
+ *
+ * \param[in]   device_select   PWM device
+ * \param[in]   config          Pointer to the config struct
+ *
+ * \return The status of the configuration.
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If unsupported device were provided
+ * \retval STATUS_OK                   If the configuration was written
+ */
+enum status_code pwm_init(enum pwm_device_select device_select, \
+		const struct pwm_config *const config)
+{
+	uint32_t reg_value = 0;
+
+	if (device_select > PWM3) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	if (config->output_polarity) {
+		reg_value |= _pwm_reg_output_polarity(device_select);
+	}
+
+	if (config->agcdata_format) {
+		reg_value |= _pwm_reg_agcdata_fmt(device_select);
+	}
+
+	reg_value |= _pwm_reg_sample_method(device_select, config->sample_method);
+
+	/* If period > 8 will be set to 4 as default. */
+	if (config->period > PWM_PERIOD_8) {
+		reg_value |= _pwm_reg_period(device_select, PWM_PERIOD_4);
+	} else {
+		reg_value |= _pwm_reg_period(device_select, config->period);
+	}
+	reg_value |= _pwm_reg_agcdata_in(device_select, config->agcdata_format, \
+									config->duty_cycle);
+
+	reg_value |= _pwm_reg_clock_sel(device_select, config->clock_select);
+
+	switch(device_select) {
+		case PWM0:
+			LPMCU_MISC_REGS0->PWM0_CTRL.reg = reg_value;
+			break;
+
+		case PWM1:
+			LPMCU_MISC_REGS0->PWM1_CTRL.reg = reg_value;
+			break;
+
+		case PWM2:
+			LPMCU_MISC_REGS0->PWM2_CTRL.reg = reg_value;
+			break;
+
+		case PWM3:
+			LPMCU_MISC_REGS0->PWM3_CTRL.reg = reg_value;
+			break;
+	}
+
+	struct gpio_config config_gpio;
+	gpio_get_config_defaults(&config_gpio);
+	config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
+	gpio_pin_set_config(config->pin_number_pad, &config_gpio);
+	gpio_pinmux_cofiguration(config->pin_number_pad, \
+							(uint16_t)(config->pinmux_sel_pad));
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables the PWM module
+ *
+ * This function will enable the PWM module.
+ *
+ * \param[in] device_select  PWM device
+ */
+void pwm_enable(enum pwm_device_select device_select)
+{
+	switch (device_select) {
+		case PWM0:
+			system_clock_peripheral_enable(PERIPHERAL_PWM0);
+			LPMCU_MISC_REGS0->PWM0_CTRL.reg |= LPMCU_MISC_REGS_PWM0_CTRL_PWM_EN;
+			break;
+
+		case PWM1:
+			system_clock_peripheral_enable(PERIPHERAL_PWM1);
+			LPMCU_MISC_REGS0->PWM1_CTRL.reg |= LPMCU_MISC_REGS_PWM1_CTRL_PWM_EN;
+			break;
+
+		case PWM2:
+			system_clock_peripheral_enable(PERIPHERAL_PWM2);
+			LPMCU_MISC_REGS0->PWM2_CTRL.reg |= LPMCU_MISC_REGS_PWM2_CTRL_PWM_EN;
+			break;
+
+		case PWM3:
+			system_clock_peripheral_enable(PERIPHERAL_PWM3);
+			LPMCU_MISC_REGS0->PWM3_CTRL.reg |= LPMCU_MISC_REGS_PWM3_CTRL_PWM_EN;
+			break;
+	}
+}
+
+/**
+ * \brief Disable the PWM module
+ *
+ * This function will disable the PWM module.
+ *
+ * \param[in] device_select  PWM device
+ */
+void pwm_disable(enum pwm_device_select device_select)
+{
+	switch (device_select) {
+		case PWM0:
+			system_clock_peripheral_disable(PERIPHERAL_PWM0);
+			LPMCU_MISC_REGS0->PWM0_CTRL.reg &= ~LPMCU_MISC_REGS_PWM0_CTRL_PWM_EN;
+			break;
+
+		case PWM1:
+			system_clock_peripheral_disable(PERIPHERAL_PWM1);
+			LPMCU_MISC_REGS0->PWM1_CTRL.reg &= ~LPMCU_MISC_REGS_PWM1_CTRL_PWM_EN;
+			break;
+
+		case PWM2:
+			system_clock_peripheral_disable(PERIPHERAL_PWM2);
+			LPMCU_MISC_REGS0->PWM2_CTRL.reg &= ~LPMCU_MISC_REGS_PWM2_CTRL_PWM_EN;
+			break;
+
+		case PWM3:
+			system_clock_peripheral_disable(PERIPHERAL_PWM3);
+			LPMCU_MISC_REGS0->PWM3_CTRL.reg &= ~LPMCU_MISC_REGS_PWM3_CTRL_PWM_EN;
+			break;
+	}
+}
+
+/**
+ * \brief Reset the PWM module
+ *
+ * This function will reset the PWM module.
+ *
+ * \param[in] device_select  PWM device
+ */
+void pwm_reset(enum pwm_device_select device_select)
+{
+	switch (device_select) {
+		case PWM0:
+			system_peripheral_reset(PERIPHERAL_PWM0);
+			break;
+
+		case PWM1:
+			system_peripheral_reset(PERIPHERAL_PWM1);
+			break;
+
+		case PWM2:
+			system_peripheral_reset(PERIPHERAL_PWM2);
+			break;
+
+		case PWM3:
+			system_peripheral_reset(PERIPHERAL_PWM3);
+			break;
+	}
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.h
new file mode 100644
index 0000000000..366c1b32b9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.h
@@ -0,0 +1,354 @@
+/**
+ * \file
+ *
+ * \brief SAM PWM Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef PWM_H_INCLUDED
+#define PWM_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_pwm_group SAM Pulse Width Modulation Driver (PWM)
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's Pulse Width Modulation Module
+ * (PWM) functionality for waveform generation operations.
+ *
+ * The following peripherals are used by this module:
+ *  - PWM (Pulse Width Modulation)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_pwm_prerequisites
+ *  - \ref asfdoc_samb_pwm_module_overview
+ *  - \ref asfdoc_samb_pwm_special_considerations
+ *  - \ref asfdoc_samb_pwm_extra_info
+ *  - \ref asfdoc_samb_pwm_examples
+ *  - \ref asfdoc_samb_pwm_api_overview
+ *
+ *
+ * \section asfdoc_samb_pwm_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_pwm_module_overview Module Overview
+ *
+ * PWM is a flexible fully configurable module which has the following features:
+ *  - 4 independent configurable pulse width modulator (PWM) blocks.
+ *  - It can be connected to an external on board low pass filter to produce
+ *    different analog control voltages depending on the configured duty cycle.
+ *  - The base frequency of PWM block is the XO clock (26MHz) or the RC oscillator.
+ *  - Different duty cycles could be obtained
+ *  - The frequency of the PWM pulse is programmable in steps according
+ *    to the following relation:
+ * \f[
+ *    f_{PWM} = \frac{f_{PWM_{base}}} {64 \times 2^i}
+ * \f]
+ * \f[
+ *   i = 0 - 8
+ * \f]
+ *
+ * f<SUB>PWM</SUB><SUB>base</SUB> can be selected to have different values
+ * according to the following table. Minimum and maximum fre-quencies supported
+ * for each clock selection is listed in the table as well.
+ *
+ * <table>
+ *  <caption>Frequency support</caption>
+ *  <tr>
+ *    <th>f<SUB>PWM</SUB><SUB>base</SUB></th>
+ *    <th>Maximum frequency</th>
+ *    <th>Minimum frequency</th>
+ *  </tr>
+ *  <tr>
+ *    <td>26 MHz</td>
+ *    <td>406.25 KHz</td>
+ *    <td>1.586 KHz</td>
+ *  </tr>
+ *  <tr>
+ *    <td>13 MHz</td>
+ *    <td>203.125 KHz</td>
+ *    <td>793.45 Hz</td>
+ *  </tr>
+  *  <tr>
+ *    <td>6.5 MHz</td>
+ *    <td>101.562 KHz</td>
+ *    <td>396.72 Hz</td>
+ *  </tr>
+  *  <tr>
+ *    <td>3.25 MHz</td>
+ *    <td>50.781 KHz</td>
+ *    <td>198.36 Hz</td>
+ *  </tr>
+ * </table>
+ *
+ * \section asfdoc_samb_pwm_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_samb_pwm_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_pwm_extra. This includes:
+ *  - \ref asfdoc_samb_pwm_extra_acronyms
+ *  - \ref asfdoc_samb_pwm_extra_dependencies
+ *  - \ref asfdoc_samb_pwm_extra_errata
+ *  - \ref asfdoc_samb_pwm_extra_history
+ *
+ *
+ * \section asfdoc_samb_pwm_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_pwm_exqsg.
+ *
+ *
+ * \section asfdoc_samb_pwm_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include "gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  \brief PWM device configuration enum.
+ *
+ *  Enum for the possible settings of pwm device configuration.
+ */
+enum pwm_device_select {
+	/** PWM module 0 */
+	PWM0 = 0,
+	/** PWM module 1 */
+	PWM1,
+	/** PWM module 2 */
+	PWM2,
+	/** PWM module 3 */
+	PWM3,
+};
+
+/**
+ *  \brief PWM sample method configuration enum.
+ *
+ *  Enum for the possible settings of pwm sample method configuration.
+ */
+enum pwm_sample_method {
+	/** Samples agcdata at >= 1024 cycles and does not lose precision */
+	PWM_SAMPLE_METHOD_0 = 0,
+	/** Samples at PWM period but will lose LSBs if less than 1024 */
+	PWM_SAMPLE_METHOD_1,
+};
+
+/**
+ *  \brief PWM period configuration enum.
+ *
+ *  Enum for the possible settings of pwm period configuration.
+ */
+enum pwm_period {
+	/** PWM perid 0 */
+	PWM_PERIOD_0 = 0,
+	/** PWM perid 1 */
+	PWM_PERIOD_1,
+	/** PWM perid 2 */
+	PWM_PERIOD_2,
+	/** PWM perid 3 */
+	PWM_PERIOD_3,
+	/** PWM perid 4 */
+	PWM_PERIOD_4,
+	/** PWM perid 5 */
+	PWM_PERIOD_5,
+	/** PWM perid 6 */
+	PWM_PERIOD_6,
+	/** PWM perid 7 */
+	PWM_PERIOD_7,
+	/** PWM perid 8 */
+	PWM_PERIOD_8,
+};
+
+/**
+ *  \brief PWM clock select configuration enum.
+ *
+ *  Enum for the possible settings of pwm clock select configuration.
+ */
+enum pwm_clock_select {
+	/** Clock 26MHz */
+	PWM_CLOCK_SELECT_26_0 = 0,
+	/** Clock 13MHz */
+	PWM_CLOCK_SELECT_13_0,
+	/** Clock 6.5MHz */
+	PWM_CLOCK_SELECT_6_5,
+	/** Clock 3.25MHz */
+	PWM_CLOCK_SELECT_3_25,
+};
+
+/**
+ *  \brief PWM configuration structure.
+ *
+ *  Configuration structure for a PWM instance. This structure should be
+ *  initialized by the \ref pwm_get_config_defaults() function before being
+ *  modified by the user application.
+ */
+struct pwm_config {
+	/** 1 to inverse the polarity */
+	bool output_polarity;
+	/** AGC data format */
+	bool agcdata_format;
+	/** Sample method */
+	enum pwm_sample_method sample_method;
+	/** Programmable PWM update period */
+	enum pwm_period period;
+	/** This value specifies the duty cycle(%) */
+	uint8_t duty_cycle;
+	/** PWM Source Clock Frequency Select */
+	enum pwm_clock_select clock_select;
+	/** PWM PAD pin number */
+	uint32_t pin_number_pad;
+	/** PWM PAD pinmux selection */
+	uint32_t pinmux_sel_pad;
+};
+
+/** \name Configuration and initialization
+ * @{
+ */
+
+void pwm_get_config_defaults(struct pwm_config *const config);
+void pwm_set_duty_cycle(enum pwm_device_select device_select, \
+					uint8_t duty_cycle);
+void pwm_set_period(enum pwm_device_select device_select, \
+					enum pwm_period period);
+enum status_code pwm_init(enum pwm_device_select device_select, \
+					const struct pwm_config *const config);
+
+/** @} */
+
+/**
+ * \name Enable/Disable and Reset
+ * @{
+ */
+
+void pwm_enable(enum pwm_device_select device_select);
+void pwm_disable(enum pwm_device_select device_select);
+void pwm_reset(enum pwm_device_select device_select);
+
+/** @} */
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \page asfdoc_samb_pwm_extra Extra Information for PWM Driver
+ *
+ * \section asfdoc_samb_pwm_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>PWM</td>
+ *		<td>Pulse Width Modulation</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_samb_pwm_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_pwm_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_pwm_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_pwm_exqsg Examples for PWM Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_pwm_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_pwm_basic_use_case
+ *
+ * \page asfdoc_samb_pwm_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *    <th>Doc. Rev.</td>
+ *    <th>Date</td>
+ *    <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *    <td>A</td>
+ *    <td>09/2015</td>
+ *    <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.c
new file mode 100644
index 0000000000..3b023db12c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.c
@@ -0,0 +1,308 @@
+/**
+ * \file
+ *
+ * \brief SAM QUAD DECODER Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "quad_decoder.h"
+
+static quad_decoder_callback_t quad_decoder0_callback = NULL;
+static quad_decoder_callback_t quad_decoder1_callback = NULL;
+static quad_decoder_callback_t quad_decoder2_callback = NULL;
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given QUAD DECODER configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structures before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Select input clock as 26MHz
+ *  \li Set counter upper threshold as 32767
+ *  \li Set counter lower threshold as -32768
+ *  \li Set pinmux_pad[0] as 0
+ *  \li Set pinmux_pad[1] as 0
+ *
+ * \param[out]  config  Pointer to a QUAD DECODER module configuration structure to set
+ */
+void quad_decoder_get_config_defaults(struct quad_decoder_config *config)
+{
+	/* Axis X */
+	config->qdec0.clock_sel = QDEC_CLK_INPUT_0;
+	config->qdec0.threshold_upper = 32767;
+	config->qdec0.threshold_lower = -32768;
+	config->qdec0.pin_number_pad[0] = 0;
+	config->qdec0.pin_number_pad[1] = 0;
+	config->qdec0.pinmux_sel_pad[0] = 0;
+	config->qdec0.pinmux_sel_pad[1] = 0;
+	config->qdec_enalbe = (1 << QDEC_AXIS_X);
+	/* Axis Y */
+	config->qdec1.clock_sel = QDEC_CLK_INPUT_0;
+	config->qdec1.threshold_upper = 32767;
+	config->qdec1.threshold_lower = -32768;
+	config->qdec1.pin_number_pad[0] = 0;
+	config->qdec1.pin_number_pad[1] = 0;
+	config->qdec1.pinmux_sel_pad[0] = 0;
+	config->qdec1.pinmux_sel_pad[1] = 0;
+	config->qdec_enalbe |= (1 << QDEC_AXIS_Y);
+	/* Axis Z */
+	config->qdec2.clock_sel = QDEC_CLK_INPUT_0;
+	config->qdec2.threshold_upper = 32767;
+	config->qdec2.threshold_lower = -32768;
+	config->qdec2.pin_number_pad[0] = 0;
+	config->qdec2.pin_number_pad[1] = 0;
+	config->qdec2.pinmux_sel_pad[0] = 0;
+	config->qdec2.pinmux_sel_pad[1] = 0;
+	config->qdec_enalbe |= (1 << QDEC_AXIS_Z);
+}
+
+/**
+ * \brief Quad Decoder ISR handler.
+ *
+ * Quad Decoder ISR handler.
+ *
+ */
+static void quad_decoder_isr_handler(void)
+{
+	uint8_t status = LPMCU_MISC_REGS0->QUAD_DEC_IRQS.reg;
+	
+	if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC0_IRQ) {
+		LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |=
+				LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLR_IRQ;
+		if (quad_decoder0_callback) {
+			quad_decoder0_callback();
+		}
+	}
+	
+	if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC1_IRQ) {
+		LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |=
+				LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLR_IRQ;
+		if (quad_decoder1_callback) {
+			quad_decoder1_callback();
+		}
+	}
+
+	if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC2_IRQ) {
+		LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |=
+				LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLR_IRQ;
+		if (quad_decoder2_callback) {
+			quad_decoder2_callback();
+		}
+	}
+}
+
+/**
+ * \brief Initializes QUAD DECODER module instance.
+ *
+ * Initializes the QUAD DECODER module, based on the given
+ * configuration values.
+ *
+ * \param[in]     qdec         Axis(x,y,z) of QUAD DECODER instance
+ * \param[in]     config       Pointer to the QAUD DECODER configuration options struct
+ */
+void quad_decoder_init(const struct quad_decoder_config *config)
+{
+	if (config->qdec_enalbe & (1 << QDEC_AXIS_X)) {
+		system_peripheral_reset(PERIPHERAL_QDEC0);
+		LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.bit.CLOCK_SEL  = config->qdec0.clock_sel;
+		LPMCU_MISC_REGS0->QUAD_DEC0_THRESHOLD.bit.UPPER = config->qdec0.threshold_upper;
+		LPMCU_MISC_REGS0->QUAD_DEC0_THRESHOLD.bit.LOWER = config->qdec0.threshold_lower;
+		gpio_pinmux_cofiguration(config->qdec0.pin_number_pad[0],
+				(uint16_t)(config->qdec0.pinmux_sel_pad[0]));
+		gpio_pinmux_cofiguration(config->qdec0.pin_number_pad[1],
+				(uint16_t)(config->qdec0.pinmux_sel_pad[1]));
+		quad_decoder_enable(QDEC_AXIS_X);
+	}
+	if (config->qdec_enalbe & (1 << QDEC_AXIS_Y)) {
+		system_peripheral_reset(PERIPHERAL_QDEC1);
+		LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.bit.CLOCK_SEL  = config->qdec1.clock_sel;
+		LPMCU_MISC_REGS0->QUAD_DEC1_THRESHOLD.bit.UPPER = config->qdec1.threshold_upper;
+		LPMCU_MISC_REGS0->QUAD_DEC1_THRESHOLD.bit.LOWER = config->qdec1.threshold_lower;
+		gpio_pinmux_cofiguration(config->qdec1.pin_number_pad[0],
+				(uint16_t)(config->qdec1.pinmux_sel_pad[0]));
+		gpio_pinmux_cofiguration(config->qdec1.pin_number_pad[1],
+				(uint16_t)(config->qdec1.pinmux_sel_pad[1]));
+		quad_decoder_enable(QDEC_AXIS_Y);
+	}
+	if (config->qdec_enalbe & (1 << QDEC_AXIS_Z)) {
+		system_peripheral_reset(PERIPHERAL_QDEC2);
+		LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.bit.CLOCK_SEL  = config->qdec2.clock_sel;
+		LPMCU_MISC_REGS0->QUAD_DEC2_THRESHOLD.bit.UPPER = config->qdec2.threshold_upper;
+		LPMCU_MISC_REGS0->QUAD_DEC2_THRESHOLD.bit.LOWER = config->qdec2.threshold_lower;
+		gpio_pinmux_cofiguration(config->qdec2.pin_number_pad[0],
+				(uint16_t)(config->qdec2.pinmux_sel_pad[0]));
+		gpio_pinmux_cofiguration(config->qdec2.pinmux_sel_pad[1],
+				(uint16_t)(config->qdec2.pinmux_sel_pad[1]));
+		quad_decoder_enable(QDEC_AXIS_Z);
+	}
+	LPMCU_MISC_REGS0->IRQ_MUX_IO_SEL_4.bit.MUX_18 =  LPMCU_MISC_REGS_IRQ_MUX_IO_SEL_4_MUX_18_19_Val;
+	system_register_isr(33, (uint32_t)quad_decoder_isr_handler);
+}
+
+/**
+ * \brief Enable QUAD DECODER module instance.
+ *
+ * Enable the QUAD DECODER module instance, based on the given axis
+ *
+ * \param[in]     qdec         Axis(x,y,z) of QUAD DECODER instance
+ */
+void quad_decoder_enable(enum quad_decoder_axis qdec)
+{
+	switch (qdec) {
+	case QDEC_AXIS_X:
+		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
+		LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |=
+				LPMCU_MISC_REGS_QUAD_DEC0_CTRL_ENABLE;
+		break;
+	case QDEC_AXIS_Y:
+		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
+		LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |=
+				LPMCU_MISC_REGS_QUAD_DEC1_CTRL_ENABLE;
+		break;
+	case QDEC_AXIS_Z:
+		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
+		LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |=
+				LPMCU_MISC_REGS_QUAD_DEC2_CTRL_ENABLE;
+		break;
+	}
+}
+
+/**
+ * \brief Disable QUAD DECODER module instance.
+ *
+ * Disable the QUAD DECODER module instance, based on the given axis
+ *
+ * \param[in]     qdec         Axis(x,y,z) of QUAD DECODER instance
+ */
+void quad_decoder_disable(enum quad_decoder_axis qdec)
+{
+	switch (qdec) {
+	case QDEC_AXIS_X:
+		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
+		LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg &=
+				~LPMCU_MISC_REGS_QUAD_DEC0_CTRL_ENABLE;
+		break;
+	case QDEC_AXIS_Y:
+		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
+		LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg &=
+				~LPMCU_MISC_REGS_QUAD_DEC1_CTRL_ENABLE;
+		break;
+	case QDEC_AXIS_Z:
+		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
+		LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg &=
+				~LPMCU_MISC_REGS_QUAD_DEC2_CTRL_ENABLE;
+		break;
+	}
+}
+
+/**
+ * \brief Get QUAD DECODER current counter
+ *
+ * Get the current counter of quad decoder, based on the given axis
+ *
+ * \param[in]     qdec         Axis(x,y,z) of QUAD DECODER instance
+ *
+ * \return The current counter of quad decoder instance
+ */
+int16_t quad_decoder_get_counter(enum quad_decoder_axis qdec)
+{
+	switch (qdec) {
+	case QDEC_AXIS_X:
+		return LPMCU_MISC_REGS0->QUAD_DEC0_STATUS.bit.COUNT;
+	case QDEC_AXIS_Y:
+		return LPMCU_MISC_REGS0->QUAD_DEC1_STATUS.bit.COUNT;
+	case QDEC_AXIS_Z:
+		return LPMCU_MISC_REGS0->QUAD_DEC2_STATUS.bit.COUNT;
+	}
+	return 0;
+}
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers and enable a callback function which is implemented by the user.
+ *
+ * \param[in]     callback_func Pointer to callback function
+ */
+void quad_decoder_register_callback(enum quad_decoder_axis qdec, quad_decoder_callback_t fun)
+{
+	switch (qdec) {
+	case QDEC_AXIS_X:
+		quad_decoder0_callback = fun;
+		break;
+	case QDEC_AXIS_Y:
+		quad_decoder1_callback = fun;
+		break;
+	case QDEC_AXIS_Z:
+		quad_decoder2_callback = fun;
+		break;
+	}
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters and disable a callback function implemented by the user.
+ *
+ */
+void quad_decoder_unregister_callback(enum quad_decoder_axis qdec)
+{
+	switch (qdec) {
+	case QDEC_AXIS_X:
+		quad_decoder0_callback = NULL;
+		break;
+	case QDEC_AXIS_Y:
+		quad_decoder1_callback = NULL;
+		break;
+	case QDEC_AXIS_Z:
+		quad_decoder2_callback = NULL;
+		break;
+	}
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.h
new file mode 100644
index 0000000000..74927445da
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.h
@@ -0,0 +1,327 @@
+/**
+ * \file
+ *
+ * \brief SAM QUAD DECODER Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef QUAD_DECODER_H_INCLUDED
+#define QUAD_DECODER_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_quad_decoder_group SAM Quadrature Decoder
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's Quadrature Decoder functionality.
+ *
+ * The following peripherals are used by this module:
+ *  - Quadrature Decoder
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_quad_decoder_prerequisites
+ *  - \ref asfdoc_samb_quad_decoder_module_overview
+ *  - \ref asfdoc_samb_quad_decoder_special_considerations
+ *  - \ref asfdoc_samb_quad_decoder_extra_info
+ *  - \ref asfdoc_samb_quad_decoder_examples
+ *  - \ref asfdoc_samb_quad_decoder_api_overview
+ *
+ *
+ * \section asfdoc_samb_quad_decoder_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_quad_decoder_module_overview Module Overview
+ * A Quadrature Decoder is used to decode the output of a Quadrature Encoder,
+ * it can be used for precision measurement of speed, acceleration, and position
+ * of a motor's rotor and with rotary knobs to determine user input. The SAMB11
+ * contains 3 Quadrature Decoder. Each one may be programmed independently.
+ * The Quadrature Decoder require initialization prior to being enabled. 
+ * Quadrature Decoder is a flexible fully configurable module which has the following features:
+ *
+ *   - 3 independent configurable Quadrature Decoder blocks.
+ *
+ *   - 16-bits resolution counters.
+ *
+ *   - 16-bits resolution Lower and Upper threshold control values.
+ *
+ *   - Input clock selection (only for MP).
+ *
+ * \subsection asfdoc_samb_quad_decoder_module_overview_thresholds Setting Thresholds
+ * The Quadrature Decoder have lower and upper thresholds. These are used for interrupt
+ * generation. The interrupt is generated whenever the counter is greater than or equal
+ * to the higher threshold and less than or equal to the lower threshold. Setting each
+ * module Higher and Lower threshold values as described below:
+ *
+ * \anchor asfdoc_sam0_quad_decoder_thresholds
+ * <table>
+ *  <caption>Quad-Decoder Register Thresholds</caption>
+ *  <tr>
+ *    <th>Filed name</th>
+ *    <th>Bits range</th>
+ *    <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *    <td>Upper</td>
+ *    <td>[15 : 0]</td>
+ *    <td>Upper threshold value</td>
+ *  </tr>
+ *  <tr>
+ *    <td>Lower</td>
+ *    <td>[31 : 16]</td>
+ *    <td>Lower threshold value</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_samb_quad_decoder_module_overview_clock Setting Clock
+ * The Quadrature Decoder have 4 different clock options to support different
+ * application requirements. The possible options are 26 MHz, 13 MHz, 6.5 MHz
+ * and 3.25 MHz This clock is used to sample the incoming Quad Decoder inputs.
+ *
+ * \section asfdoc_samb_quad_decoder_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_samb_quad_decoder_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_quad_decoder_extra. This includes:
+ *  - \ref asfdoc_samb_quad_decoder_extra_acronyms
+ *  - \ref asfdoc_samb_quad_decoder_extra_dependencies
+ *  - \ref asfdoc_samb_quad_decoder_extra_errata
+ *  - \ref asfdoc_samb_quad_decoder_extra_history
+ *
+ *
+ * \section asfdoc_samb_quad_decoder_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_quad_decoder_exqsg.
+ *
+ *
+ * \section asfdoc_samb_quad_decoder_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include "gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Type definition for a DUALTIMER module callback function. */
+typedef void (*quad_decoder_callback_t)(void);
+
+/**
+ * \brief QUAD DECODER index number
+ *
+ * Values is the axis(x,y,z) of QUAD DECODER instance.
+ */
+enum quad_decoder_axis {
+	/** AXIS X */
+	QDEC_AXIS_X = 0,
+	/** AXIS Y */
+	QDEC_AXIS_Y,
+	/** AXIS Z */
+	QDEC_AXIS_Z,
+};
+
+/**
+ * \brief QUAD DECODER module clock input
+ *
+ * QUAD DECODER module clock.
+ *
+ */
+enum quad_decoder_clock_input {
+	/** Source from clock input 0: 26MHz */
+	QDEC_CLK_INPUT_0 = 0,
+	/** Source from clock input 1: 13MHz */
+	QDEC_CLK_INPUT_1,
+	/** Source from clock input 2: 6.5MHz */
+	QDEC_CLK_INPUT_2,
+	/** Source from clock input 3: 3MHz */
+	QDEC_CLK_INPUT_3,
+};
+
+/**
+ * \brief Quad Decoder private configuration structure.
+ *
+ * Private configuration struct for Quad Decoder instance.
+ */
+struct quad_decoder_private_config {
+	/** Quad Decoder Source Clock Frequency Select */
+	enum quad_decoder_clock_input clock_sel;
+	/** Upper Threshold of counter for Quad Decoder */
+	int16_t threshold_upper;
+	/** Lower Threshold of counter for Quad Decoder */
+	int16_t threshold_lower;
+	/** Dec_in_a pin number */
+	/** Dec_in_b pin number */
+	uint32_t pin_number_pad[2];
+	/** Dec_in_a pinmux selection */
+	/** Dec_in_b pinmux selection */
+	uint32_t pinmux_sel_pad[2];
+};
+
+/**
+ * \brief QUAD DECODER configuration structure.
+ *
+ * Configuration struct for a QUAD DECODER instance.
+ * This structure should be initialized by the
+ * \ref quad_decoder_get_config_defaults function
+ * before being modified by the user application.
+ */
+struct quad_decoder_config {
+	uint8_t qdec_enalbe;
+	struct quad_decoder_private_config qdec0;
+	struct quad_decoder_private_config qdec1;
+	struct quad_decoder_private_config qdec2;
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+void quad_decoder_get_config_defaults(
+		struct quad_decoder_config *config);
+void quad_decoder_init(const struct quad_decoder_config *config);
+/** @} */
+
+/**
+ * \name Enable and disable module
+ * @{
+ */
+void quad_decoder_enable(enum quad_decoder_axis qdec);
+void quad_decoder_disable(enum quad_decoder_axis qdec);
+/** @} */
+
+/**
+ * \name Get value
+ * @{
+ */
+int16_t quad_decoder_get_counter(enum quad_decoder_axis qdec);
+/** @} */
+
+/**
+ * \name Callback register/unregister
+ * @{
+ */
+void quad_decoder_register_callback(enum quad_decoder_axis qdec,
+		quad_decoder_callback_t fun);
+void quad_decoder_unregister_callback(enum quad_decoder_axis qdec);
+/** @} */
+
+/** @}*/
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_samb_quad_decoder_extra Extra Information for Quadrature Decoder Driver
+ *
+ * \section asfdoc_samb_quad_decoder_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Quadrature Decoder</td>
+ *		<td>Quadrature Decoder</td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_samb_quad_decoder_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_quad_decoder_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_quad_decoder_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_quad_decoder_exqsg Examples for Quadrature Decoder Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_quad_decoder_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_quad_decoder_basic_use_case
+ *
+ * \page asfdoc_samb_quad_decoder_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *    <th>Doc. Rev.</td>
+ *    <th>Date</td>
+ *    <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *    <td>A</td>
+ *    <td>09/2015</td>
+ *    <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar.h
new file mode 100644
index 0000000000..339535bd5f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar.h
@@ -0,0 +1,1414 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Calendar Mode)
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef RTC_CALENDAR_H_INCLUDED
+#define RTC_CALENDAR_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_rtc_calendar_group SAM RTC Calendar (RTC CAL) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's Real Time
+ * Clock functionality in Calendar operating mode, for the configuration and
+ * retrieval of the current time and date as maintained by the RTC module.
+  The following driver API modes are covered by this manual:
+ *
+ *  - Polled APIs
+ * \if RTC_CALENDAR_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - RTC (Real Time Clock)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_rtc_calendar_prerequisites
+ *  - \ref asfdoc_sam0_rtc_calendar_module_overview
+ *  - \ref asfdoc_sam0_rtc_calendar_special_considerations
+ *  - \ref asfdoc_sam0_rtc_calendar_extra_info
+ *  - \ref asfdoc_sam0_rtc_calendar_examples
+ *  - \ref asfdoc_sam0_rtc_calendar_api_overview
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_module_overview Module Overview
+ *
+ * The RTC module in the SAM devices is a 32-bit counter, with a 10-bit
+ * programmable prescaler. Typically, the RTC clock is run continuously,
+ * including in the device's low-power sleep modes, to track the current time
+ * and date information. The RTC can be used as a source to wake up the system
+ * at a scheduled time or periodically using the alarm functions.
+ *
+ * In this driver, the RTC is operated in Calendar mode. This allows for an
+ * easy integration of a real time clock and calendar into a user application
+ * to track the passing of time and/or perform scheduled tasks.
+ *
+ * Whilst operating in Calendar mode, the RTC features:
+ *  - Time tracking in seconds, minutes, and hours
+ *  - 12 or 24 hour mode
+ *  - Date tracking in day, month, and year
+ *  - Automatic leap year correction
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_PERIODIC_INT</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_PRESCALER_OFF</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_CLOCK_SELECTION</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_GENERAL_PURPOSE_REG</td>
+ *    <td>SAM L21/L22/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_CONTINUOUSLY_UPDATED</td>
+ *    <td>SAM D20, SAM D21, SAM R21, SAM D10, SAM D11, SAM DA1, SAM HA1</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_TAMPER_DETECTION</td>
+ *    <td>SAM L22</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_module_overview_alarms Alarms and Overflow
+ * The RTC has up to four independent hardware alarms that can be configured by the user
+ * application. These alarms will be triggered on match with the current
+ * clock value, and can be set up to trigger an interrupt, event, or both. The
+ * RTC can also be configured to clear the clock value on alarm match, resetting
+ * the clock to the original start time.
+ *
+ * If the RTC is operated in clock-only mode (i.e. with calendar disabled), the
+ * RTC counter value will instead be cleared on overflow once the maximum count
+ * value has been reached:
+ *
+ * \f[ COUNT_{MAX} = 2^{32}-1 \f]
+ *
+ * When the RTC is operated with the calendar enabled and run using a nominal
+ * 1Hz input clock frequency, a register overflow will occur after 64 years.
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_module_overview_periodic Periodic Events
+ * The RTC can generate events at periodic intervals, allowing for direct
+ * peripheral actions without CPU intervention. The periodic events can be
+ * generated on the upper eight bits of the RTC prescaler, and will be generated on
+ * the rising edge transition of the specified bit. The resulting periodic
+ * frequency can be calculated by the following formula:
+ *
+ * \f[ f_{PERIODIC}=\frac{f_{ASY}}{2^{n+3}} \f]
+ *
+ * Where \f$f_{ASY}\f$ refers to the \e asynchronous clock set up in the RTC
+ * module configuration. For the RTC to operate correctly in calendar mode, this
+ * frequency must be 1KHz, while the RTC's internal prescaler should be set to
+ * divide by 1024. The \b n parameter is the event source generator index of the
+ * RTC module. If the asynchronous clock is operated at the recommended 1KHz,
+ * the formula results in the values shown in
+ * \ref asfdoc_sam0_rtc_calendar_module_rtc_hz "the table below".
+ *
+ * \anchor asfdoc_sam0_rtc_calendar_module_rtc_hz
+ * <table>
+ *   <caption>RTC Event Frequencies for Each Prescaler Bit Using a 1KHz Clock</caption>
+ *   <tr>
+ *      <th>n</th> <th>Periodic event</th>
+ *   </tr>
+ *   <tr>
+ *      <td>7</td> <td>1Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>6</td> <td>2Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>5</td> <td>4Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>4</td> <td>8Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>3</td> <td>16Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>2</td> <td>32Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>1</td> <td>64Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>0</td> <td>128Hz</td>
+ *   </tr>
+ * </table>
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_module_overview_correction Digital Frequency Correction
+ * The RTC module contains Digital Frequency Correction logic to compensate for
+ * inaccurate source clock frequencies which would otherwise result in skewed
+ * time measurements. The correction scheme requires that at least two bits
+ * in the RTC module prescaler are reserved by the correction logic. As a
+ * result of this implementation, frequency correction is only available when
+ * the RTC is running from a 1Hz reference clock.
+ *
+ * The correction procedure is implemented by subtracting or adding a single
+ * cycle from the RTC prescaler every 1024 RTC Generic Clock (GCLK) cycles. The adjustment is
+ * applied the specified number of time (maximum 127) over 976 of these periods. The
+ * corresponding correction in parts per million (PPM) will be given by:
+ *
+ * \f[ Correction(PPM) = \frac{VALUE}{999424}10^6 \f]
+ *
+ * The RTC clock will tick faster if provided with a positive correction value,
+ * and slower when given a negative correction value.
+ *
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_module_overview_tamper_detect RTC Tamper Detect
+ * See \ref asfdoc_sam0_rtc_tamper_detect.
+ *
+ * \section asfdoc_sam0_rtc_calendar_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_special_considerations_year Year Limit
+ * The RTC module has a year range of 63 years from the starting year configured
+ * when the module is initialized. Dates outside the start to end year range
+ * described below will need software adjustment:
+ *
+ * \f[ [YEAR_{START}, YEAR_{START}+64] \f]
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_special_considerations_clock Clock Setup
+ * \subsubsection asfdoc_sam0_rtc_calendar_clock_samd_r SAM D20/D21/R21/D10/D11/DA1/HA1 Clock Setup.
+ * The RTC is typically clocked by a specialized GCLK generator that has a
+ * smaller prescaler than the others. By default the RTC clock is on, selected
+ * to use the internal 32KHz Resistor/Capacitor (RC)-oscillator with a prescaler
+ * of 32, giving a resulting clock frequency of 1024Hz to the RTC. When the
+ * internal RTC prescaler is set to 1024, this yields an end-frequency of 1Hz
+ * for correct time keeping operations.
+ *
+ * The implementer also has the option to set other end-frequencies.
+ * \ref asfdoc_sam0_rtc_calendar_rtc_out_freq "The table below" lists the
+ * available RTC frequencies for each possible GCLK and RTC input prescaler
+ * options.
+ *
+ * \anchor asfdoc_sam0_rtc_calendar_rtc_out_freq
+ * <table>
+ *   <caption>RTC Output Frequencies from Allowable Input Clocks</caption>
+ *   <tr>
+ *     <th>End-frequency</th>
+ *     <th>GCLK prescaler</th>
+ *     <th>RTC prescaler</th>
+ *   </tr>
+ *   <tr>
+ *     <td>32KHz</td>
+ *     <td>1</td>
+ *     <td>1</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1KHz</td>
+ *     <td>32</td>
+ *     <td>1</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1Hz</td>
+ *     <td>32</td>
+ *     <td>1024</td>
+ *   </tr>
+ * </table>
+ *
+ * The overall RTC module clocking scheme is shown in
+ * \ref asfdoc_sam0_rtc_calendar_rtc_clock_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_rtc_calendar_rtc_clock_fig
+ * \dot
+ * digraph clocking_scheme {
+ *     rankdir=LR;
+ *     GCLK [shape="record", label="<f0> GCLK | <f1> RTC_GCLK",
+ *         bgcolor="lightgray", style="filled"];
+ *     RTCPRE [shape="record" label="<f0> RTC | <f1> RTC PRESCALER"];
+ *     RTC [shape="record", label="<f0> RTC | <f1> RTC CLOCK"];
+ *
+ *     GCLK:f1 -> RTCPRE:f1;
+ *     RTCPRE:f1 -> RTC:f1;
+ * }
+ * \enddot
+ *
+ * \note For the calendar to operate correctly, an asynchronous clock of 1Hz
+ *       should be used.
+ *
+ * \subsubsection asfdoc_sam0_rtc_calendar_clock_saml SAM L21/C20/C21/R30 Clock Setup
+ * The RTC clock can be selected from OSC32K, XOSC32K, or OSCULP32K. A 32KHz
+ * or 1KHz oscillator clock frequency is required. This clock must be
+ * configured and enabled in the 32KHz oscillator controller before using the RTC.
+ *
+ * \ref asfdoc_sam0_rtc_calendar_rtc_clk lists the available RTC clock.
+ *
+ * \anchor asfdoc_sam0_rtc_calendar_rtc_clk
+ * <table>
+ *   <caption>RTC Clocks Source</caption>
+ *   <tr>
+ *     <th>RTC clock frequency</th>
+ *     <th>Clock source</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>1.024kHz</td>
+ *     <td>ULP1K</td>
+ *     <td>1.024kHz from 32KHz internal ULP oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>32.768kHz</td>
+ *     <td>ULP32K</td>
+ *     <td>32.768kHz from 32KHz internal ULP oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1.024kHz</td>
+ *     <td>OSC1K</td>
+ *     <td>1.024kHz from 32KHz internal oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>32.768kHz</td>
+ *     <td>OSC32K</td>
+ *     <td>32.768kHz from 3KkHz internal oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1.024kHz</td>
+ *     <td>XOSC1K</td>
+ *     <td>1.024kHz from 32KHz internal oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>32.768kHz</td>
+ *     <td>XOSC32K</td>
+ *     <td>32.768kHz from 32KHz external crystal oscillator</td>
+ *   </tr>
+ * </table>
+ *
+ * \note For the calendar to operate correctly, an asynchronous clock of 1Hz
+ *       should be used.
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_rtc_calendar_extra. This includes:
+ *  - \ref asfdoc_sam0_rtc_calendar_extra_acronyms
+ *  - \ref asfdoc_sam0_rtc_calendar_extra_dependencies
+ *  - \ref asfdoc_sam0_rtc_calendar_extra_errata
+ *  - \ref asfdoc_sam0_rtc_calendar_extra_history
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_rtc_calendar_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_api_overview API Overview
+ * @{
+ */
+
+#include <conf_clocks.h>
+
+#if RTC_CALENDAR_ASYNC == true
+#  include <system_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Define port features set according to different device family
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+/** RTC periodic interval interrupt. */
+#  define FEATURE_RTC_PERIODIC_INT
+/** RTC prescaler is off. */
+#  define FEATURE_RTC_PRESCALER_OFF
+/** RTC clock selection. */
+#  define FEATURE_RTC_CLOCK_SELECTION
+#  if !(SAMC20) && !(SAMC21)
+/** General purpose registers. */
+#  define FEATURE_RTC_GENERAL_PURPOSE_REG
+#  endif
+#else
+/** RTC continuously updated. */
+#  define FEATURE_RTC_CONTINUOUSLY_UPDATED
+#endif
+
+#if (SAML22) || defined(__DOXYGEN__)
+/** RTC tamper detection. */
+#  define FEATURE_RTC_TAMPER_DETECTION
+#endif
+
+/*@}*/
+
+#ifdef FEATURE_RTC_CLOCK_SELECTION
+/**
+ * \brief Available clock source for RTC.
+ * RTC clock source.
+ */
+enum rtc_clock_sel {
+	/** 1.024kHz from 32KHz internal ULP oscillator */
+	RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val,
+	/** 32.768kHz from 32KHz internal ULP oscillator */
+	RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val,
+#if !(SAML22)
+	/** 1.024kHz from 32KHz internal oscillator */
+	RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val,
+	/** 32.768kHz from 32KHz internal oscillator */
+	RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val,
+#endif
+	/** 1.024kHz from 32KHz internal oscillator */
+	RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val,
+	/** 32.768kHz from 32.768kHz external crystal oscillator */
+	RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val,
+};
+#endif
+
+#if !defined (RTC_NUM_OF_ALARMS) && defined(RTC_ALARM_NUM)
+#define RTC_NUM_OF_ALARMS RTC_ALARM_NUM
+#endif
+
+/**
+ * \brief Available alarm channels.
+ *
+ * Available alarm channels.
+ *
+ * \note Not all alarm channels are available on all devices.
+ */
+enum rtc_calendar_alarm {
+	/** Alarm channel 0 */
+	RTC_CALENDAR_ALARM_0 = 0,
+#if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+	/** Alarm channel 1 */
+	RTC_CALENDAR_ALARM_1 = 1,
+#endif
+#if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
+	/** Alarm channel 2 */
+	RTC_CALENDAR_ALARM_2 = 2,
+#endif
+#if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
+	/** Alarm channel 3 */
+	RTC_CALENDAR_ALARM_3 = 3,
+#endif
+};
+
+#ifdef FEATURE_RTC_PERIODIC_INT
+/**
+ * \brief Available periodic interval source.
+ */
+enum rtc_calendar_periodic_interval{
+	/** Periodic interval 0 */
+	RTC_CALENDAR_PERIODIC_INTERVAL_0 = 0,
+	/** Periodic interval 1 */
+	RTC_CALENDAR_PERIODIC_INTERVAL_1 = 1,
+	/** Periodic interval 2 */
+	RTC_CALENDAR_PERIODIC_INTERVAL_2 = 2,
+	/** Periodic interval 3 */
+	RTC_CALENDAR_PERIODIC_INTERVAL_3 = 3,
+	/** Periodic interval 4 */
+	RTC_CALENDAR_PERIODIC_INTERVAL_4 = 4,
+	/** Periodic interval 5 */
+	RTC_CALENDAR_PERIODIC_INTERVAL_5 = 5,
+	/** Periodic interval 6 */
+	RTC_CALENDAR_PERIODIC_INTERVAL_6 = 6,
+	/** Periodic interval 7 */
+	RTC_CALENDAR_PERIODIC_INTERVAL_7 = 7,
+};
+#endif
+
+#if RTC_CALENDAR_ASYNC == true
+#ifdef FEATURE_RTC_PERIODIC_INT
+/**
+ * \brief Callback types.
+ *
+ * The available callback types for the RTC calendar module.
+ */
+enum rtc_calendar_callback {
+	/** Callback for Periodic Interval 0 Interrupt */
+	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0 = 0,
+	/** Callback for Periodic Interval 1 Interrupt */
+	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_1,
+	/** Callback for Periodic Interval 2 Interrupt */
+	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_2,
+	/** Callback for Periodic Interval 3 Interrupt */
+	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_3,
+	/** Callback for Periodic Interval 4 Interrupt */
+	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_4,
+	/** Callback for Periodic Interval 5 Interrupt */
+	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_5,
+	/** Callback for Periodic Interval 6 Interrupt */
+	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_6,
+	/** Callback for Periodic Interval 7 Interrupt */
+	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7,
+	/** Callback for alarm 0 */
+	RTC_CALENDAR_CALLBACK_ALARM_0,
+#  if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+	/** Callback for alarm 1 */
+	RTC_CALENDAR_CALLBACK_ALARM_1,
+#  endif
+#  if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
+	/** Callback for alarm 2 */
+	RTC_CALENDAR_CALLBACK_ALARM_2,
+#  endif
+#  if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
+	/** Callback for alarm 3 */
+	RTC_CALENDAR_CALLBACK_ALARM_3,
+#  endif
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/** Callback for tamper */
+	RTC_CALENDAR_CALLBACK_TAMPER,
+#endif
+	/** Callback for  overflow */
+	RTC_CALENDAR_CALLBACK_OVERFLOW,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_RTC_CALENDAR_CALLBACK_N
+#  endif
+};
+#else
+/**
+ * \brief Callback types.
+ *
+ * The available callback types for the RTC calendar module.
+ */
+enum rtc_calendar_callback {
+	/** Callback for alarm 0 */
+	RTC_CALENDAR_CALLBACK_ALARM_0 = 0,
+#  if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+	/** Callback for alarm 1 */
+	RTC_CALENDAR_CALLBACK_ALARM_1,
+#  endif
+#  if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
+	/** Callback for alarm 2 */
+	RTC_CALENDAR_CALLBACK_ALARM_2,
+#  endif
+#  if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
+	/** Callback for alarm 3 */
+	RTC_CALENDAR_CALLBACK_ALARM_3,
+#  endif
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/** Callback for tamper */
+	RTC_CALENDAR_CALLBACK_TAMPER,
+#endif
+	/** Callback for  overflow */
+	RTC_CALENDAR_CALLBACK_OVERFLOW,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_RTC_CALENDAR_CALLBACK_N
+#  endif
+};
+#endif
+
+#  if !defined(__DOXYGEN__)
+typedef void (*rtc_calendar_callback_t)(void);
+#  endif
+#endif
+
+#ifdef FEATURE_RTC_PRESCALER_OFF
+/**
+ * \brief RTC input clock prescaler settings.
+ *
+ * The available input clock prescaler values for the RTC calendar module.
+ */
+enum rtc_calendar_prescaler {
+	/** RTC prescaler is off, and the input clock frequency is
+	prescaled by a factor of 1 */
+	RTC_CALENDAR_PRESCALER_OFF      = RTC_MODE2_CTRLA_PRESCALER_OFF,
+	/** RTC input clock frequency is prescaled by a factor of 1 */
+	RTC_CALENDAR_PRESCALER_DIV_1    = RTC_MODE2_CTRLA_PRESCALER_DIV1,
+	/** RTC input clock frequency is prescaled by a factor of 2 */
+	RTC_CALENDAR_PRESCALER_DIV_2    = RTC_MODE2_CTRLA_PRESCALER_DIV2,
+	/** RTC input clock frequency is prescaled by a factor of 4 */
+	RTC_CALENDAR_PRESCALER_DIV_4    = RTC_MODE2_CTRLA_PRESCALER_DIV4,
+	/** RTC input clock frequency is prescaled by a factor of 8 */
+	RTC_CALENDAR_PRESCALER_DIV_8    = RTC_MODE2_CTRLA_PRESCALER_DIV8,
+	/** RTC input clock frequency is prescaled by a factor of 16 */
+	RTC_CALENDAR_PRESCALER_DIV_16   = RTC_MODE2_CTRLA_PRESCALER_DIV16,
+	/** RTC input clock frequency is prescaled by a factor of 32 */
+	RTC_CALENDAR_PRESCALER_DIV_32   = RTC_MODE2_CTRLA_PRESCALER_DIV32,
+	/** RTC input clock frequency is prescaled by a factor of 64 */
+	RTC_CALENDAR_PRESCALER_DIV_64   = RTC_MODE2_CTRLA_PRESCALER_DIV64,
+	/** RTC input clock frequency is prescaled by a factor of 128 */
+	RTC_CALENDAR_PRESCALER_DIV_128  = RTC_MODE2_CTRLA_PRESCALER_DIV128,
+	/** RTC input clock frequency is prescaled by a factor of 256 */
+	RTC_CALENDAR_PRESCALER_DIV_256  = RTC_MODE2_CTRLA_PRESCALER_DIV256,
+	/** RTC input clock frequency is prescaled by a factor of 512 */
+	RTC_CALENDAR_PRESCALER_DIV_512  = RTC_MODE2_CTRLA_PRESCALER_DIV512,
+	/** RTC input clock frequency is prescaled by a factor of 1024 */
+	RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRLA_PRESCALER_DIV1024,
+};
+
+#else
+/**
+ * \brief RTC input clock prescaler settings.
+ *
+ * The available input clock prescaler values for the RTC calendar module.
+ */
+enum rtc_calendar_prescaler {
+	/** RTC input clock frequency is prescaled by a factor of 1 */
+	RTC_CALENDAR_PRESCALER_DIV_1    = RTC_MODE2_CTRL_PRESCALER_DIV1,
+	/** RTC input clock frequency is prescaled by a factor of 2 */
+	RTC_CALENDAR_PRESCALER_DIV_2    = RTC_MODE2_CTRL_PRESCALER_DIV2,
+	/** RTC input clock frequency is prescaled by a factor of 4 */
+	RTC_CALENDAR_PRESCALER_DIV_4    = RTC_MODE2_CTRL_PRESCALER_DIV4,
+	/** RTC input clock frequency is prescaled by a factor of 8 */
+	RTC_CALENDAR_PRESCALER_DIV_8    = RTC_MODE2_CTRL_PRESCALER_DIV8,
+	/** RTC input clock frequency is prescaled by a factor of 16 */
+	RTC_CALENDAR_PRESCALER_DIV_16   = RTC_MODE2_CTRL_PRESCALER_DIV16,
+	/** RTC input clock frequency is prescaled by a factor of 32 */
+	RTC_CALENDAR_PRESCALER_DIV_32   = RTC_MODE2_CTRL_PRESCALER_DIV32,
+	/** RTC input clock frequency is prescaled by a factor of 64 */
+	RTC_CALENDAR_PRESCALER_DIV_64   = RTC_MODE2_CTRL_PRESCALER_DIV64,
+	/** RTC input clock frequency is prescaled by a factor of 128 */
+	RTC_CALENDAR_PRESCALER_DIV_128  = RTC_MODE2_CTRL_PRESCALER_DIV128,
+	/** RTC input clock frequency is prescaled by a factor of 256 */
+	RTC_CALENDAR_PRESCALER_DIV_256  = RTC_MODE2_CTRL_PRESCALER_DIV256,
+	/** RTC input clock frequency is prescaled by a factor of 512 */
+	RTC_CALENDAR_PRESCALER_DIV_512  = RTC_MODE2_CTRL_PRESCALER_DIV512,
+	/** RTC input clock frequency is prescaled by a factor of 1024 */
+	RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRL_PRESCALER_DIV1024,
+};
+#endif
+
+#if !defined(__DOXYGEN__)
+/**
+ * \brief Device structure.
+ */
+struct rtc_module {
+	/** RTC hardware module */
+	Rtc *hw;
+	/** If clock mode 24h */
+	bool clock_24h;
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+	/** If continuously update clock register */
+	bool continuously_update;
+#endif
+	/** Initial year for counter value 0 */
+	uint16_t year_init_value;
+#  if RTC_CALENDAR_ASYNC == true
+	/** Pointers to callback functions */
+	volatile rtc_calendar_callback_t callbacks[_RTC_CALENDAR_CALLBACK_N];
+	/** Mask for registered callbacks */
+	volatile uint16_t registered_callback;
+	/** Mask for enabled callbacks */
+	volatile uint16_t enabled_callback;
+#  endif
+};
+#endif
+
+/**
+ * \brief Available mask options for alarms.
+ *
+ * Available mask options for alarms.
+ */
+enum rtc_calendar_alarm_mask {
+	/** Alarm disabled */
+	RTC_CALENDAR_ALARM_MASK_DISABLED = RTC_MODE2_MASK_SEL_OFF,
+	/** Alarm match on second */
+	RTC_CALENDAR_ALARM_MASK_SEC      = RTC_MODE2_MASK_SEL_SS,
+	/** Alarm match on second and minute */
+	RTC_CALENDAR_ALARM_MASK_MIN      = RTC_MODE2_MASK_SEL_MMSS,
+	/** Alarm match on second, minute, and hour */
+	RTC_CALENDAR_ALARM_MASK_HOUR     = RTC_MODE2_MASK_SEL_HHMMSS,
+	/** Alarm match on second, minute, hour, and day */
+	RTC_CALENDAR_ALARM_MASK_DAY      = RTC_MODE2_MASK_SEL_DDHHMMSS,
+	/** Alarm match on second, minute, hour, day, and month */
+	RTC_CALENDAR_ALARM_MASK_MONTH    = RTC_MODE2_MASK_SEL_MMDDHHMMSS,
+	/** Alarm match on second, minute, hour, day, month, and year */
+	RTC_CALENDAR_ALARM_MASK_YEAR     = RTC_MODE2_MASK_SEL_YYMMDDHHMMSS,
+};
+
+/**
+ * \brief RTC Calendar event enable/disable structure.
+ *
+ * Event flags for the \ref rtc_calendar_enable_events() and
+ * \ref rtc_calendar_disable_events().
+ */
+struct rtc_calendar_events {
+	/** Generate an output event on each overflow of the RTC count */
+	bool generate_event_on_overflow;
+	/** Generate an output event on an alarm channel match against the RTC
+	 *  count */
+	bool generate_event_on_alarm[RTC_NUM_OF_ALARMS];
+	/** Generate an output event periodically at a binary division of the RTC
+	 *  counter frequency
+	 */
+	bool generate_event_on_periodic[8];
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/** Generate an output event on every tamper input */
+	bool generate_event_on_tamper;
+	/** Tamper input event and capture the CLOCK value */
+	bool on_event_to_tamper;
+#endif
+};
+
+/**
+ * \brief Time structure.
+ *
+ * Time structure containing the time given by or set to the RTC calendar.
+ * The structure uses seven values to give second, minute, hour, PM/AM, day,
+ * month, and year. It should be initialized via the
+ * \ref rtc_calendar_get_time_defaults() function before use.
+ */
+struct rtc_calendar_time {
+	/** Second value */
+	uint8_t  second;
+	/** Minute value */
+	uint8_t  minute;
+	/** Hour value */
+	uint8_t  hour;
+	/** PM/AM value, \c true for PM, or \c false for AM */
+	bool     pm;
+	/** Day value, where day 1 is the first day of the month */
+	uint8_t  day;
+	/** Month value, where month 1 is January */
+	uint8_t  month;
+	/** Year value */
+	uint16_t year;
+};
+
+/**
+ * \brief Alarm structure.
+ *
+ * Alarm structure containing time of the alarm and a mask to determine when
+ * the alarm will trigger.
+ */
+struct rtc_calendar_alarm_time {
+	/** Alarm time */
+	struct rtc_calendar_time time;
+	/** Alarm mask to determine on what precision the alarm will match */
+	enum rtc_calendar_alarm_mask mask;
+};
+
+/**
+ * \brief RTC configuration structure.
+ *
+ * Configuration structure for the RTC instance. This structure should
+ * be initialized using the \ref rtc_calendar_get_config_defaults() before any
+ * user configurations are set.
+ */
+struct rtc_calendar_config {
+	/** Input clock prescaler for the RTC module */
+	enum rtc_calendar_prescaler prescaler;
+	/** If \c true, clears the clock on alarm match */
+	bool clear_on_match;
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+	/** If \c true, the digital counter registers will be continuously updated
+	 *  so that internal synchronization is not needed when reading the current
+	 *  count */
+	bool continuously_update;
+#endif
+	/** If \c true, time is represented in 24 hour mode */
+	bool clock_24h;
+	/** Initial year for counter value 0 */
+	uint16_t year_init_value;
+#if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/** Enable count read synchronization. The CLOCK value requires
+	 * synchronization when reading. Disabling the synchronization
+	 * will prevent the CLOCK value from displaying the current value. */
+	bool enable_read_sync;
+#endif
+	/** Alarm values */
+	struct rtc_calendar_alarm_time alarm[RTC_NUM_OF_ALARMS];
+};
+
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initialize a \c time structure.
+ *
+ * This will initialize a given time structure to the time 00:00:00 (hh:mm:ss)
+ * and date 2000-01-01 (YYYY-MM-DD).
+ *
+ * \param[out] time  Time structure to initialize
+ */
+static inline void rtc_calendar_get_time_defaults(
+		struct rtc_calendar_time *const time)
+{
+	time->second = 0;
+	time->minute = 0;
+	time->hour   = 0;
+	time->pm     = 0;
+	time->day    = 1;
+	time->month  = 1;
+	time->year   = 2000;
+}
+
+/**
+ * \brief Gets the RTC default settings.
+ *
+ * Initializes the configuration structure to the known default values. This
+ * function should be called at the start of any RTC initiation.
+ *
+ * The default configuration is as follows:
+ *  - Input clock divided by a factor of 1024
+ *  - Clear on alarm match off
+ *  - Continuously sync clock off
+ *  - 12 hour calendar
+ *  - Start year 2000 (Year 0 in the counter will be year 2000)
+ *  - Events off
+ *  - Alarms set to January 1. 2000, 00:00:00
+ *  - Alarm will match on second, minute, hour, day, month, and year
+ *  - Clock read synchronization is enabled for SAM L22
+ *
+ *  \param[out] config  Configuration structure to be initialized to default
+ *                      values
+ */
+static inline void rtc_calendar_get_config_defaults(
+		struct rtc_calendar_config *const config)
+{
+	/* Sanity check argument */
+	Assert(config);
+
+	/* Initialize and set time structure to default */
+	struct rtc_calendar_time time;
+	rtc_calendar_get_time_defaults(&time);
+
+	/* Set defaults into configuration structure */
+	config->prescaler           = RTC_CALENDAR_PRESCALER_DIV_1024;
+	config->clear_on_match      = false;
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+	config->continuously_update = false;
+#endif
+	config->clock_24h           = false;
+	config->year_init_value     = 2000;
+#if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	config->enable_read_sync    = true;
+#endif
+	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+		config->alarm[i].time = time;
+		config->alarm[i].mask = RTC_CALENDAR_ALARM_MASK_YEAR;
+	}
+}
+
+void rtc_calendar_reset(struct rtc_module *const module);
+void rtc_calendar_enable(struct rtc_module *const module);
+void rtc_calendar_disable(struct rtc_module *const module);
+
+#if (RTC_INST_NUM > 1) && !defined(__DOXYGEN__)
+/**
+ * \internal Find the index of given RTC module instance.
+ *
+ * \param[in] hw  RTC module instance pointer
+ *
+ * \return Index of the given RTC module instance.
+ */
+uint8_t _rtc_get_inst_index(
+		Rtc *const hw)
+{
+	/* List of available RTC modules */
+	static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
+
+	/* Find index for RTC instance */
+	for (uint32_t i = 0; i < RTC_INST_NUM; i++) {
+		if (hw == rtc_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given */
+	Assert(false);
+	return 0;
+}
+#endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */
+
+void rtc_calendar_init(
+		struct rtc_module *const module,
+		Rtc *const hw,
+		const struct rtc_calendar_config *const config);
+
+void rtc_calendar_swap_time_mode(struct rtc_module *const module);
+
+enum status_code rtc_calendar_frequency_correction(
+		struct rtc_module *const module,
+		const int8_t value);
+
+/** @} */
+
+
+/** \name Time and Alarm Management
+ * @{
+ */
+uint32_t rtc_calendar_time_to_register_value(
+		struct rtc_module *const module,
+		const struct rtc_calendar_time *const time);
+void rtc_calendar_register_value_to_time(
+		struct rtc_module *const module,
+		const uint32_t register_value,
+		struct rtc_calendar_time *const time);
+
+void rtc_calendar_set_time(
+		struct rtc_module *const module,
+		const struct rtc_calendar_time *const time);
+
+void rtc_calendar_get_time(
+		struct rtc_module *const module,
+		struct rtc_calendar_time *const time);
+
+enum status_code rtc_calendar_set_alarm(
+		struct rtc_module *const module,
+		const struct rtc_calendar_alarm_time *const alarm,
+		const enum rtc_calendar_alarm alarm_index);
+
+enum status_code rtc_calendar_get_alarm(
+		struct rtc_module *const module,
+		struct rtc_calendar_alarm_time *const alarm,
+		const enum rtc_calendar_alarm alarm_index);
+
+/** @} */
+
+
+/** \name Status Flag Management
+ * @{
+ */
+
+/**
+ * \brief Check if an RTC overflow has occurred.
+ *
+ * Checks the overflow flag in the RTC. The flag is set when there
+ * is an overflow in the clock.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ *
+ * \return Overflow state of the RTC module.
+ *
+ * \retval true   If the RTC count value has overflowed
+ * \retval false  If the RTC count value has not overflowed
+ */
+static inline bool rtc_calendar_is_overflow(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Return status of flag */
+	return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF);
+}
+
+/**
+ * \brief Clears the RTC overflow flag.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ *
+ * Clears the RTC module counter overflow flag, so that new overflow conditions
+ * can be detected.
+ */
+static inline void rtc_calendar_clear_overflow(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Clear flag */
+	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+#ifdef FEATURE_RTC_PERIODIC_INT
+/**
+ * \brief Check if an RTC periodic interval interrupt has occurred.
+ *
+ * Checks the periodic interval flag in the RTC.
+ *
+ * \param[in,out]  module  RTC hardware module
+ * \param[in]  n  RTC periodic interval interrupt
+ *
+ * \return Periodic interval interrupt state of the RTC module.
+ *
+ * \retval true   RTC periodic interval interrupt occur
+ * \retval false  RTC periodic interval interrupt doesn't occur
+ */
+static inline bool rtc_calendar_is_periodic_interval(struct rtc_module *const module,
+										enum rtc_calendar_periodic_interval n)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Return status of flag */
+	return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER(1 << n));
+}
+
+/**
+ * \brief Clears the RTC periodic interval flag.
+ *
+ * Clears the RTC module counter periodic interval flag, so that new periodic
+ *  interval conditions can be detected.
+ *
+ * \param[in,out]  module  RTC hardware module
+ * \param[in]  n  RTC periodic interval interrupt
+ */
+static inline void rtc_calendar_clear_periodic_interval(struct rtc_module *const module,
+											enum rtc_calendar_periodic_interval n)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Clear periodic interval flag */
+	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER(1 << n);
+}
+#endif
+
+/**
+ * \brief Check the RTC alarm flag.
+ *
+ * Check if the specified alarm flag is set. The flag is set when there
+ * is a compare match between the alarm value and the clock.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] alarm_index  Index of the alarm to check
+ *
+ * \returns Match status of the specified alarm.
+ *
+ * \retval true   If the specified alarm has matched the current time
+ * \retval false  If the specified alarm has not matched the current time
+ */
+static inline bool rtc_calendar_is_alarm_match(
+		struct rtc_module *const module,
+		const enum rtc_calendar_alarm alarm_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Sanity check */
+	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+		Assert(false);
+		return false;
+	}
+
+	/* Return int flag status */
+	return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM(1 << alarm_index));
+}
+
+/**
+ * \brief Clears the RTC alarm match flag.
+ *
+ * Clear the requested alarm match flag, so that future alarm matches can be
+ * determined.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] alarm_index  The index of the alarm match to clear
+ *
+ * \return Status of the alarm match clear operation.
+ *
+ * \retval STATUS_OK               If flag was cleared correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+static inline enum status_code rtc_calendar_clear_alarm_match(
+		struct rtc_module *const module,
+		const enum rtc_calendar_alarm alarm_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Sanity check */
+	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Clear flag */
+	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << alarm_index);
+
+	return STATUS_OK;
+}
+
+/** @} */
+
+
+/**
+ * \name Event Management
+ * @{
+ */
+
+/**
+ * \brief Enables an RTC event output.
+ *
+ *  Enables one or more output events from the RTC module. See
+ *  \ref rtc_calendar_events for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in,out] module  Pointer to the software instance struct
+ *  \param[in] events    Struct containing flags of events to enable
+ */
+static inline void rtc_calendar_enable_events(
+		struct rtc_module *const module,
+		struct rtc_calendar_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Check if the user has requested an overflow event */
+	if (events->generate_event_on_overflow) {
+		event_mask |= RTC_MODE2_EVCTRL_OVFEO;
+	}
+
+	/* Check if the user has requested any alarm events */
+	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+		if (events->generate_event_on_alarm[i]) {
+			event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i);
+		}
+	}
+
+	/* Check if the user has requested any periodic events */
+	for (uint8_t i = 0; i < 8; i++) {
+		if (events->generate_event_on_periodic[i]) {
+			event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i);
+		}
+	}
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/* Check if the user has requested a tamper event output */
+	if (events->generate_event_on_tamper) {
+		event_mask |= RTC_MODE2_EVCTRL_TAMPEREO;
+	}
+
+	/* Check if the user has requested a tamper event input */
+	if (events->on_event_to_tamper) {
+		event_mask |= RTC_MODE2_EVCTRL_TAMPEVEI;
+	}
+#endif
+
+	/* Enable given event(s) */
+	rtc_module->MODE2.EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables an RTC event output.
+ *
+ *  Disabled one or more output events from the RTC module. See
+ *  \ref rtc_calendar_events for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in,out] module  Pointer to the software instance struct
+ *  \param[in] events    Struct containing flags of events to disable
+ */
+static inline void rtc_calendar_disable_events(
+		struct rtc_module *const module,
+		struct rtc_calendar_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Check if the user has requested an overflow event */
+	if (events->generate_event_on_overflow) {
+		event_mask |= RTC_MODE2_EVCTRL_OVFEO;
+	}
+
+	/* Check if the user has requested any alarm events */
+	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+		if (events->generate_event_on_alarm[i]) {
+			event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i);
+		}
+	}
+
+	/* Check if the user has requested any periodic events */
+	for (uint8_t i = 0; i < 8; i++) {
+		if (events->generate_event_on_periodic[i]) {
+			event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i);
+		}
+	}
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/* Check if the user has requested a tamper event output */
+	if (events->generate_event_on_tamper) {
+		event_mask |= RTC_MODE2_EVCTRL_TAMPEREO;
+	}
+
+	/* Check if the user has requested a tamper event input */
+	if (events->on_event_to_tamper) {
+		event_mask |= RTC_MODE2_EVCTRL_TAMPEVEI;
+	}
+#endif
+
+	/* Disable given event(s) */
+	rtc_module->MODE2.EVCTRL.reg &= ~event_mask;
+}
+
+/** @} */
+
+#ifdef FEATURE_RTC_GENERAL_PURPOSE_REG
+/**
+ * \name RTC General Purpose Registers
+ * @{
+ */
+
+/**
+ * \brief Write a value into general purpose register.
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] n  General purpose type
+ * \param[in] index General purpose register index (0..3)
+ *
+ */
+static inline void rtc_write_general_purpose_reg(
+	struct rtc_module *const module,
+	const  uint8_t index,
+	uint32_t value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(index <= 3);
+
+	Rtc *const rtc_module = module->hw;
+
+	rtc_module->MODE0.GP[index].reg = value;
+}
+
+/**
+ * \brief Read the value from general purpose register.
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] index General purpose register index (0..3)
+ *
+ * \return Value of general purpose register.
+ */
+static inline uint32_t rtc_read_general_purpose_reg(
+	struct rtc_module *const module,
+	const  uint8_t index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(index <= 3);
+
+	Rtc *const rtc_module = module->hw;
+
+	return rtc_module->MODE0.GP[index].reg;
+}
+
+/** @} */
+#endif
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+#include "rtc_tamper.h"
+/**
+ * \brief Get the tamper stamp value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[out] time  Pointer to value that filled with tamper stamp time
+ */
+void rtc_tamper_get_stamp (struct rtc_module *const module,
+		struct rtc_calendar_time *const time);
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \page asfdoc_sam0_rtc_calendar_extra Extra Information for RTC (CAL) Driver
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</td>
+ *		<th>Description</td>
+ *	</tr>
+ *	<tr>
+ *		<td>RTC</td>
+ *		<td>Real Time Counter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PPM</td>
+ *		<td>Part Per Million</td>
+ *	</tr>
+ *	<tr>
+ *		<td>RC</td>
+ *		<td>Resistor/Capacitor</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for RTC tamper feature</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added driver instance parameter to all API function calls, except
+ *          get_config_defaults</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Updated initialization function to also enable the digital interface
+ *          clock to the module if it is disabled</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_rtc_calendar_exqsg Examples for RTC CAL Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_rtc_calendar_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that a QSG can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_rtc_calendar_basic_use_case
+ * \if RTC_CALENDAR_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_rtc_calendar_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_rtc_calendar_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42126E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAMR30, SAM C21, SAM D09, and SAM DA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42126D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42126C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42126B</td>
+ *		<td>06/2013</td>
+ *		<td>Added additional documentation on the event system. Corrected
+ *          documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42126A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* RTC_CALENDAR_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar_interrupt.h
new file mode 100644
index 0000000000..21615b0f31
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar_interrupt.h
@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Calendar Interrupt Mode)
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef RTC_CALENDAR_INTERRUPT_H_INCLUDED
+#define RTC_CALENDAR_INTERRUPT_H_INCLUDED
+
+#include "rtc_calendar.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_rtc_calendar_group
+ * @{
+ */
+
+ /**
+ * \name Callbacks
+ * @{
+ */
+enum status_code rtc_calendar_register_callback(
+		struct rtc_module *const module,
+		rtc_calendar_callback_t callback,
+		enum rtc_calendar_callback callback_type);
+
+enum status_code rtc_calendar_unregister_callback(
+		struct rtc_module *const module,
+		enum rtc_calendar_callback callback_type);
+
+void rtc_calendar_enable_callback(
+		struct rtc_module *const module,
+		enum rtc_calendar_callback callback_type);
+
+void rtc_calendar_disable_callback(
+	struct rtc_module *const module,
+	enum rtc_calendar_callback callback_type);
+
+/** @} */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTC_CALENDAR_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count.h
new file mode 100644
index 0000000000..e1c7a651e7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count.h
@@ -0,0 +1,1301 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Mode)
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef RTC_COUNT_H_INCLUDED
+#define RTC_COUNT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_rtc_count_group SAM RTC Count (RTC COUNT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's Real Time
+ * Clock functionality in Count operating mode, for the configuration and
+ * retrieval of the current RTC counter value. The following driver API modes
+ * are covered by this manual:
+ *
+ *  - Polled APIs
+ * \if RTC_COUNT_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - RTC (Real Time Clock)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_rtc_count_prerequisites
+ *  - \ref asfdoc_sam0_rtc_count_module_overview
+ *  - \ref asfdoc_sam0_rtc_count_special_considerations
+ *  - \ref asfdoc_sam0_rtc_count_extra_info
+ *  - \ref asfdoc_sam0_rtc_count_examples
+ *  - \ref asfdoc_sam0_rtc_count_api_overview
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_module_overview Module Overview
+ *
+ * The RTC module in the SAM devices is a 32-bit counter, with a 10-bit
+ * programmable prescaler. Typically, the RTC clock is run continuously,
+ * including in the device's low-power sleep modes, to track the current time
+ * and date information. The RTC can be used as a source to wake up the system
+ * at a scheduled time or periodically using the alarm functions.
+ *
+ * In this driver, the RTC is operated in Count mode. This allows for an
+ * easy integration of an asynchronous counter into a user application, which is
+ * capable of operating while the device is in sleep mode.
+ *
+ * Whilst operating in Count mode, the RTC features:
+ *  - 16-bit counter mode
+ *   - Selectable counter period
+ *   - Up to six configurable compare values
+ *  - 32-bit counter mode
+ *   - Clear counter value on match
+ *   - Up to four configurable compare values
+ *
+ * \subsection asfdoc_sam0_rtc_count_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_PERIODIC_INT</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_PRESCALER_OFF</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_CLOCK_SELECTION</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_GENERAL_PURPOSE_REG</td>
+ *    <td>SAM L21/L22/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_CONTINUOUSLY_UPDATED</td>
+ *    <td>SAM D20, SAM D21, SAM R21, SAM D10, SAM D11, SAM DA1, SAM HA1</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_RTC_TAMPER_DETECTION</td>
+ *    <td>SAM L22</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \section asfdoc_sam0_rtc_count_module_overview_compares Compare and Overflow
+ * The RTC can be used with up to 4/6 compare values (depending on selected
+ * operation mode). These compare values will trigger on match with the current
+ * RTC counter value, and can be set up to trigger an interrupt, event, or both.
+ * The RTC can also be configured to clear the counter value on compare match
+ * in 32-bit mode, resetting the count value back to zero.
+ *
+ * If the RTC is operated without the Clear on Match option enabled, or in
+ * 16-bit mode, the RTC counter value will instead be cleared on overflow once
+ * the maximum count value has been reached:
+ *
+ * \f[ COUNT_{MAX} = 2^{32}-1 \f] for 32-bit counter mode, and
+ * \f[ COUNT_{MAX} = 2^{16}-1 \f] for 16-bit counter mode.
+ *
+ * When running in 16-bit mode, the overflow value is selectable with a period
+ * value. The counter overflow will then occur when the counter value reaches
+ * the specified period value.
+ *
+ * \subsection asfdoc_sam0_rtc_count_module_overview_periodic Periodic Events
+ * The RTC can generate events at periodic intervals, allowing for direct
+ * peripheral actions without CPU intervention. The periodic events can be
+ * generated on the upper eight bits of the RTC prescaler, and will be generated on
+ * the rising edge transition of the specified bit. The resulting periodic
+ * frequency can be calculated by the following formula:
+ *
+ * \f[ f_{PERIODIC}=\frac{f_{ASY}}{2^{n+3}} \f]
+ *
+ * Where \f$f_{ASY}\f$ refers to the \e asynchronous clock is set up in the RTC
+ * module configuration. The \b n parameter is the event source generator index
+ * of the RTC module. If the asynchronous clock is operated at the recommended
+ * frequency of 1KHz, the formula results in the values shown in
+ * \ref asfdoc_sam0_rtc_count_module_rtc_hz "the table below".
+ *
+ * \anchor asfdoc_sam0_rtc_count_module_rtc_hz
+ * <table>
+ *   <caption>RTC Event Frequencies for Each Prescaler Bit Using a 1KHz Clock</caption>
+ *   <tr>
+ *      <th>n</th> <th>Periodic event</th>
+ *   </tr>
+ *   <tr>
+ *      <td>7</td> <td>1Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>6</td> <td>2Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>5</td> <td>4Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>4</td> <td>8Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>3</td> <td>16Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>2</td> <td>32Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>1</td> <td>64Hz</td>
+ *   </tr>
+ *   <tr>
+ *      <td>0</td> <td>128Hz</td>
+ *   </tr>
+ * </table>
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System (EVENTS) Driver"
+ *       to route output event of one module to the the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * \subsection asfdoc_sam0_rtc_count_module_overview_correction Digital Frequency Correction
+ * The RTC module contains Digital Frequency Correction logic to compensate for
+ * inaccurate source clock frequencies which would otherwise result in skewed
+ * time measurements. The correction scheme requires that at least two bits
+ * in the RTC module prescaler are reserved by the correction logic. As a
+ * result of this implementation, frequency correction is only available when
+ * the RTC is running from a 1Hz reference clock.
+ *
+ * The correction procedure is implemented by subtracting or adding a single
+ * cycle from the RTC prescaler every 1024 RTC GCLK cycles. The adjustment is
+ * applied the specified number of time (maximum 127) over 976 of these periods. The
+ * corresponding correction in PPM will be given by:
+ *
+ * \f[ Correction(PPM) = \frac{VALUE}{999424}10^6 \f]
+ *
+ * The RTC clock will tick faster if provided with a positive correction value,
+ * and slower when given a negative correction value.
+ *
+ *
+ * \subsection asfdoc_sam0_rtc_count_module_overview_tamper_detect RTC Tamper Detect
+ * see \ref asfdoc_sam0_rtc_tamper_detect
+ *
+ * \section asfdoc_sam0_rtc_count_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_rtc_count_special_considerations_clock Clock Setup
+ * \subsubsection asfdoc_sam0_rtc_count_clock_samd_r SAM D20/D21/R21/D10/D11/DA1/HA1 Clock Setup
+ * The RTC is typically clocked by a specialized GCLK generator that has a
+ * smaller prescaler than the others. By default the RTC clock is on, selected
+ * to use the internal 32KHz RC-oscillator with a prescaler of 32, giving a
+ * resulting clock frequency of 1KHz to the RTC.  When the internal RTC
+ * prescaler is set to 1024, this yields an end-frequency of 1Hz.
+ *
+ * The implementer also has the option to set other end-frequencies.
+ * \ref asfdoc_sam0_rtc_count_rtc_out_freq "The table below" lists the
+ * available RTC frequencies for each possible GCLK and RTC input prescaler
+ * options.
+ *
+ * \anchor asfdoc_sam0_rtc_count_rtc_out_freq
+ * <table>
+ *   <caption>RTC Output Frequencies from Allowable Input Clocks</caption>
+ *   <tr>
+ *     <th>End-frequency</th>
+ *     <th>GCLK prescaler</th>
+ *     <th>RTC prescaler</th>
+ *   </tr>
+ *   <tr>
+ *     <td>32KHz</td>
+ *     <td>1</td>
+ *     <td>1</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1KHz</td>
+ *     <td>32</td>
+ *     <td>1</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1Hz</td>
+ *     <td>32</td>
+ *     <td>1024</td>
+ *   </tr>
+ * </table>
+ *
+ * The overall RTC module clocking scheme is shown in
+ * \ref asfdoc_sam0_rtc_count_rtc_clock_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_rtc_count_rtc_clock_fig
+ * \dot
+ * digraph clocking_scheme {
+ *     rankdir=LR;
+ *     GCLK [shape="record", label="<f0> GCLK | <f1> RTC_GCLK",
+ *         bgcolor="lightgray", style="filled"];
+ *     RTCPRE [shape="record" label="<f0> RTC | <f1> RTC PRESCALER"];
+ *     RTC [shape="record", label="<f0> RTC | <f1> RTC CLOCK"];
+ *
+ *     GCLK:f1 -> RTCPRE:f1;
+ *     RTCPRE:f1 -> RTC:f1;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_rtc_count_clock_saml SAM L21/C20/C21/R30 Clock Setup
+ * The RTC clock can be selected from OSC32K, XOSC32K, or OSCULP32K, and a 32KHz
+ * or 1KHz oscillator clock frequency is required. This clock must be
+ * configured and enabled in the 32KHz oscillator controller before using the RTC.
+ *
+ * The table below lists the available RTC clock \ref asfdoc_sam0_rtc_count_rtc_clk.
+ *
+ * \anchor asfdoc_sam0_rtc_count_rtc_clk
+ * <table>
+ *   <caption>RTC Clocks Source</caption>
+ *   <tr>
+ *     <th>RTC clock frequency</th>
+ *     <th>Clock source</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>1.024KHz</td>
+ *     <td>ULP1K</td>
+ *     <td>1.024KHz from 32KHz internal ULP oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>32.768KHz</td>
+ *     <td>ULP32K</td>
+ *     <td>32.768KHz from 32KHz internal ULP oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1.024KHz</td>
+ *     <td>OSC1K</td>
+ *     <td>1.024KHz from 32KHz internal oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>32.768KHz</td>
+ *     <td>OSC32K</td>
+ *     <td>32.768KHz from 32KHz internal oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1.024KHz</td>
+ *     <td>XOSC1K</td>
+ *     <td>1.024KHz from 32KHz internal oscillator</td>
+ *   </tr>
+ *   <tr>
+ *     <td>32.768KHz</td>
+ *     <td>XOSC32K</td>
+ *     <td>32.768KHz from 32KHz external crystal oscillator</td>
+ *   </tr>
+ * </table>
+ *
+ * \section asfdoc_sam0_rtc_count_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_rtc_count_extra. This includes:
+ *  - \ref asfdoc_sam0_rtc_count_extra_acronyms
+ *  - \ref asfdoc_sam0_rtc_count_extra_dependencies
+ *  - \ref asfdoc_sam0_rtc_count_extra_errata
+ *  - \ref asfdoc_sam0_rtc_count_extra_history
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_rtc_count_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <conf_clocks.h>
+
+#if RTC_COUNT_ASYNC == true
+#  include <system_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ *
+ * Define port features set according to different device family.
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+/** RTC periodic interval interrupt. */
+#  define FEATURE_RTC_PERIODIC_INT
+/** RTC prescaler is off. */
+#  define FEATURE_RTC_PRESCALER_OFF
+/** RTC clock selection. */
+#  define FEATURE_RTC_CLOCK_SELECTION
+#  if !(SAMC20) && !(SAMC21)
+/** General purpose registers. */
+#  define FEATURE_RTC_GENERAL_PURPOSE_REG
+#  endif
+#else
+/** RTC continuously updated. */
+#  define FEATURE_RTC_CONTINUOUSLY_UPDATED
+#endif
+
+#if (SAML22) || defined(__DOXYGEN__)
+/** RTC tamper detection. */
+#  define FEATURE_RTC_TAMPER_DETECTION
+#endif
+
+/*@}*/
+
+#ifdef FEATURE_RTC_CLOCK_SELECTION
+/**
+ * \brief Available clock source for RTC.
+ * RTC clock source.
+ */
+enum rtc_clock_sel {
+	/** 1.024KHz from 32KHz internal ULP oscillator */
+	RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val,
+	/** 32.768KHz from 32KHz internal ULP oscillator */
+	RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val,
+#if !(SAML22)
+	/** 1.024KHz from 32KHz internal oscillator */
+	RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val,
+	/** 32.768KHz from 32KHz internal oscillator */
+	RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val,
+#endif
+	/** 1.024KHz from 32KHz external oscillator */
+	RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val,
+	/** 32.768KHz from 32.768KHz external crystal oscillator */
+	RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val,
+};
+#endif
+
+/**
+ * \brief Available operation modes for the RTC.
+ *
+ * RTC Count operating modes, to select the counting width and associated module
+ * operation.
+ */
+enum rtc_count_mode {
+	/** RTC Count module operates in 16-bit mode */
+	RTC_COUNT_MODE_16BIT = 0,
+	/** RTC Count module operates in 32-bit mode */
+	RTC_COUNT_MODE_32BIT = 1,
+};
+
+#if !defined (RTC_NUM_OF_COMP16) && defined(RTC_COMP16_NUM)
+#define RTC_NUM_OF_COMP16 RTC_COMP16_NUM
+#endif
+
+/**
+ * \brief Available compare channels.
+ *
+ * \note Not all compare channels are available in all devices and modes.
+ */
+enum rtc_count_compare {
+	/** Compare channel 0 */
+	RTC_COUNT_COMPARE_0 = 0,
+#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+	/** Compare channel 1 */
+	RTC_COUNT_COMPARE_1 = 1,
+#endif
+#if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
+	/** Compare channel 2 */
+	RTC_COUNT_COMPARE_2 = 2,
+#endif
+#if (RTC_NUM_OF_COMP16 > 3)	|| defined(__DOXYGEN__)
+	/** Compare channel 3 */
+	RTC_COUNT_COMPARE_3 = 3,
+#endif
+#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+	/** Compare channel 4 */
+	RTC_COUNT_COMPARE_4 = 4,
+#endif
+#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+	/** Compare channel 5 */
+	RTC_COUNT_COMPARE_5 = 5,
+#endif
+};
+
+#ifdef FEATURE_RTC_PERIODIC_INT
+/**
+ * \brief Available periodic interval source.
+ */
+enum rtc_count_periodic_interval{
+	/** Periodic interval 0 */
+	RTC_COUNT_PERIODIC_INTERVAL_0 = 0,
+	/** Periodic interval 1 */
+	RTC_COUNT_PERIODIC_INTERVAL_1 = 1,
+	/** Periodic interval 2 */
+	RTC_COUNT_PERIODIC_INTERVAL_2 = 2,
+	/** Periodic interval 3 */
+	RTC_COUNT_PERIODIC_INTERVAL_3 = 3,
+	/** Periodic interval 4 */
+	RTC_COUNT_PERIODIC_INTERVAL_4 = 4,
+	/** Periodic interval 5 */
+	RTC_COUNT_PERIODIC_INTERVAL_5 = 5,
+	/** Periodic interval 6 */
+	RTC_COUNT_PERIODIC_INTERVAL_6 = 6,
+	/** Periodic interval 7 */
+	RTC_COUNT_PERIODIC_INTERVAL_7 = 7,
+};
+#endif
+
+#if RTC_COUNT_ASYNC == true
+#ifdef FEATURE_RTC_PERIODIC_INT
+/**
+ * \brief Callback types.
+ *
+ * The available callback types for the RTC count module.
+ */
+enum rtc_count_callback {
+	/** Callback for Periodic Interval 0 Interrupt */
+	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0 = 0,
+	/** Callback for Periodic Interval 1 Interrupt */
+	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_1,
+	/** Callback for Periodic Interval 2 Interrupt */
+	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_2,
+	/** Callback for Periodic Interval 3 Interrupt */
+	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_3,
+	/** Callback for Periodic Interval 4 Interrupt */
+	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_4,
+	/** Callback for Periodic Interval 5 Interrupt */
+	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_5,
+	/** Callback for Periodic Interval 6 Interrupt */
+	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_6,
+	/** Callback for Periodic Interval 7 Interrupt */
+	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7,
+	/** Callback for compare channel 0 */
+	RTC_COUNT_CALLBACK_COMPARE_0,
+#  if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+	/** Callback for compare channel 1 */
+	RTC_COUNT_CALLBACK_COMPARE_1,
+#  endif
+#  if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
+	/** Callback for compare channel 2 */
+	RTC_COUNT_CALLBACK_COMPARE_2,
+#  endif
+#  if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
+	/** Callback for compare channel 3 */
+	RTC_COUNT_CALLBACK_COMPARE_3,
+#  endif
+#  if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+	/** Callback for compare channel 4 */
+	RTC_COUNT_CALLBACK_COMPARE_4,
+#  endif
+#  if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+	/** Callback for compare channel 5 */
+	RTC_COUNT_CALLBACK_COMPARE_5,
+#  endif
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/** Callback for tamper */
+	RTC_COUNT_CALLBACK_TAMPER,
+#endif
+
+	/** Callback for overflow */
+	RTC_COUNT_CALLBACK_OVERFLOW,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_RTC_COUNT_CALLBACK_N
+#  endif
+};
+#else
+/**
+ * \brief Callback types.
+ *
+ * The available callback types for the RTC count module.
+ */
+enum rtc_count_callback {
+	/** Callback for compare channel 0 */
+	RTC_COUNT_CALLBACK_COMPARE_0 = 0,
+#  if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+	/** Callback for compare channel 1 */
+	RTC_COUNT_CALLBACK_COMPARE_1,
+#  endif
+#  if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
+	/** Callback for compare channel 2 */
+	RTC_COUNT_CALLBACK_COMPARE_2,
+#  endif
+#  if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
+	/** Callback for compare channel 3 */
+	RTC_COUNT_CALLBACK_COMPARE_3,
+#  endif
+#  if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+	/** Callback for compare channel 4 */
+	RTC_COUNT_CALLBACK_COMPARE_4,
+#  endif
+#  if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+	/** Callback for compare channel 5 */
+	RTC_COUNT_CALLBACK_COMPARE_5,
+#  endif
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/** Callback for tamper */
+	RTC_COUNT_CALLBACK_TAMPER,
+#endif
+
+	/** Callback for overflow */
+	RTC_COUNT_CALLBACK_OVERFLOW,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_RTC_COUNT_CALLBACK_N
+#  endif
+};
+#endif
+
+#  if !defined(__DOXYGEN__)
+typedef void (*rtc_count_callback_t)(void);
+#  endif
+#endif
+
+#ifdef FEATURE_RTC_PRESCALER_OFF
+/**
+ * \brief RTC input clock prescaler settings.
+ *
+ * The available input clock prescaler values for the RTC count module.
+ */
+enum rtc_count_prescaler {
+	/** RTC prescaler is off, and the input clock frequency is
+	prescaled by a factor of 1 */
+	RTC_COUNT_PRESCALER_OFF      = RTC_MODE0_CTRLA_PRESCALER_OFF,
+	/** RTC input clock frequency is prescaled by a factor of 1 */
+	RTC_COUNT_PRESCALER_DIV_1    = RTC_MODE0_CTRLA_PRESCALER_DIV1,
+	/** RTC input clock frequency is prescaled by a factor of 2 */
+	RTC_COUNT_PRESCALER_DIV_2    = RTC_MODE0_CTRLA_PRESCALER_DIV2,
+	/** RTC input clock frequency is prescaled by a factor of 4 */
+	RTC_COUNT_PRESCALER_DIV_4    = RTC_MODE0_CTRLA_PRESCALER_DIV4,
+	/** RTC input clock frequency is prescaled by a factor of 8 */
+	RTC_COUNT_PRESCALER_DIV_8    = RTC_MODE0_CTRLA_PRESCALER_DIV8,
+	/** RTC input clock frequency is prescaled by a factor of 16 */
+	RTC_COUNT_PRESCALER_DIV_16   = RTC_MODE0_CTRLA_PRESCALER_DIV16,
+	/** RTC input clock frequency is prescaled by a factor of 32 */
+	RTC_COUNT_PRESCALER_DIV_32   = RTC_MODE0_CTRLA_PRESCALER_DIV32,
+	/** RTC input clock frequency is prescaled by a factor of 64 */
+	RTC_COUNT_PRESCALER_DIV_64   = RTC_MODE0_CTRLA_PRESCALER_DIV64,
+	/** RTC input clock frequency is prescaled by a factor of 128 */
+	RTC_COUNT_PRESCALER_DIV_128  = RTC_MODE0_CTRLA_PRESCALER_DIV128,
+	/** RTC input clock frequency is prescaled by a factor of 256 */
+	RTC_COUNT_PRESCALER_DIV_256  = RTC_MODE0_CTRLA_PRESCALER_DIV256,
+	/** RTC input clock frequency is prescaled by a factor of 512 */
+	RTC_COUNT_PRESCALER_DIV_512  = RTC_MODE0_CTRLA_PRESCALER_DIV512,
+	/** RTC input clock frequency is prescaled by a factor of 1024 */
+	RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRLA_PRESCALER_DIV1024,
+};
+#else
+/**
+ * \brief RTC input clock prescaler settings.
+ *
+ * The available input clock prescaler values for the RTC count module.
+ */
+enum rtc_count_prescaler {
+	/** RTC input clock frequency is prescaled by a factor of 1 */
+	RTC_COUNT_PRESCALER_DIV_1    = RTC_MODE0_CTRL_PRESCALER_DIV1,
+	/** RTC input clock frequency is prescaled by a factor of 2 */
+	RTC_COUNT_PRESCALER_DIV_2    = RTC_MODE0_CTRL_PRESCALER_DIV2,
+	/** RTC input clock frequency is prescaled by a factor of 4 */
+	RTC_COUNT_PRESCALER_DIV_4    = RTC_MODE0_CTRL_PRESCALER_DIV4,
+	/** RTC input clock frequency is prescaled by a factor of 8 */
+	RTC_COUNT_PRESCALER_DIV_8    = RTC_MODE0_CTRL_PRESCALER_DIV8,
+	/** RTC input clock frequency is prescaled by a factor of 16 */
+	RTC_COUNT_PRESCALER_DIV_16   = RTC_MODE0_CTRL_PRESCALER_DIV16,
+	/** RTC input clock frequency is prescaled by a factor of 32 */
+	RTC_COUNT_PRESCALER_DIV_32   = RTC_MODE0_CTRL_PRESCALER_DIV32,
+	/** RTC input clock frequency is prescaled by a factor of 64 */
+	RTC_COUNT_PRESCALER_DIV_64   = RTC_MODE0_CTRL_PRESCALER_DIV64,
+	/** RTC input clock frequency is prescaled by a factor of 128 */
+	RTC_COUNT_PRESCALER_DIV_128  = RTC_MODE0_CTRL_PRESCALER_DIV128,
+	/** RTC input clock frequency is prescaled by a factor of 256 */
+	RTC_COUNT_PRESCALER_DIV_256  = RTC_MODE0_CTRL_PRESCALER_DIV256,
+	/** RTC input clock frequency is prescaled by a factor of 512 */
+	RTC_COUNT_PRESCALER_DIV_512  = RTC_MODE0_CTRL_PRESCALER_DIV512,
+	/** RTC input clock frequency is prescaled by a factor of 1024 */
+	RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRL_PRESCALER_DIV1024,
+};
+#endif
+
+/**
+ * \brief RTC Count event enable/disable structure.
+ *
+ * Event flags for the \ref rtc_count_enable_events() and
+ * \ref rtc_count_disable_events().
+ */
+struct rtc_count_events {
+	/** Generate an output event on each overflow of the RTC count */
+	bool generate_event_on_overflow;
+	/** Generate an output event on a compare channel match against the RTC
+	 *  count */
+	bool generate_event_on_compare[RTC_NUM_OF_COMP16];
+	/** Generate an output event periodically at a binary division of the RTC
+	 *  counter frequency */
+	bool generate_event_on_periodic[8];
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/** Generate an output event on every tamper input */
+	bool generate_event_on_tamper;
+	/** Tamper input event and capture the COUNT value */
+	bool on_event_to_tamper;
+#endif
+};
+
+#if !defined(__DOXYGEN__)
+/**
+ * \brief Device structure.
+ */
+struct rtc_module {
+	/** RTC hardware module */
+	Rtc *hw;
+	/** Operation mode of count */
+	enum rtc_count_mode mode;
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+	/** Set if counter value should be continuously updated */
+	bool continuously_update;
+#endif
+#  if RTC_COUNT_ASYNC == true
+	/** Pointers to callback functions */
+	volatile rtc_count_callback_t callbacks[_RTC_COUNT_CALLBACK_N];
+	/** Mask for registered callbacks */
+	volatile uint16_t registered_callback;
+	/** Mask for enabled callbacks */
+	volatile uint16_t enabled_callback;
+#  endif
+};
+#endif
+
+/**
+ * \brief RTC Count configuration structure.
+ *
+ * Configuration structure for the RTC instance. This structure should
+ * be initialized using the \ref rtc_count_get_config_defaults() before any
+ * user configurations are set.
+ */
+struct rtc_count_config {
+	/** Input clock prescaler for the RTC module */
+	enum rtc_count_prescaler prescaler;
+	/** Select the operation mode of the RTC */
+	enum rtc_count_mode mode;
+	/** If true, clears the counter value on compare match. Only available
+	 *  whilst running in 32-bit mode */
+	bool clear_on_match;
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+	/** Continuously update the counter value so no synchronization is
+	 *  needed for reading */
+	bool continuously_update;
+#endif
+#if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/** Enable count read synchronization. The COUNT value requires
+	 * synchronization when reading. Disabling the synchronization
+	 * will prevent the COUNT value from displaying the current value. */
+	bool enable_read_sync;
+#endif
+
+	/** Array of Compare values. Not all Compare values are available in 32-bit
+	 *  mode */
+	uint32_t compare_values[RTC_NUM_OF_COMP16];
+};
+
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ *  \brief Gets the RTC default configurations.
+ *
+ *  Initializes the configuration structure to default values. This
+ *  function should be called at the start of any RTC initialization.
+ *
+ *  The default configuration is:
+ *  - Input clock divided by a factor of 1024
+ *  - RTC in 32-bit mode
+ *  - Clear on compare match off
+ *  - Continuously sync count register off
+ *  - No event source on
+ *  - All compare values equal 0
+ *  - Count read synchronization is enabled for SAM L22
+ *
+ *  \param[out] config  Configuration structure to be initialized to default
+ *                      values
+ */
+static inline void rtc_count_get_config_defaults(
+		struct rtc_count_config *const config)
+{
+	/* Sanity check argument */
+	Assert(config);
+
+	/* Set default into configuration structure */
+	config->prescaler           = RTC_COUNT_PRESCALER_DIV_1024;
+	config->mode                = RTC_COUNT_MODE_32BIT;
+	config->clear_on_match      = false;
+
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+	config->continuously_update = false;
+#endif
+#if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	config->enable_read_sync    = true;
+#endif
+
+	for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+		config->compare_values[i] = 0;
+	}
+}
+
+void rtc_count_reset(struct rtc_module *const module);
+void rtc_count_enable(struct rtc_module *const module);
+void rtc_count_disable(struct rtc_module *const module);
+
+#if (RTC_INST_NUM > 1) && !defined(__DOXYGEN__)
+/**
+ * \internal Find the index of given RTC module instance.
+ *
+ * \param[in] RTC module instance pointer
+ *
+ * \return Index of the given AC module instance.
+ */
+uint8_t _rtc_get_inst_index(
+		Rtc *const hw)
+{
+	/* List of available RTC modules */
+	static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
+
+	/* Find index for RTC instance */
+	for (uint32_t i = 0; i < RTC_INST_NUM; i++) {
+		if (hw == rtc_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given */
+	Assert(false);
+	return 0;
+}
+#endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */
+
+enum status_code rtc_count_init(
+		struct rtc_module *const module,
+		Rtc *const hw,
+		const struct rtc_count_config *const config);
+
+enum status_code rtc_count_frequency_correction(
+		struct rtc_module *const module,
+		const int8_t value);
+
+/** @} */
+
+/** \name Count and Compare Value Management
+ * @{
+ */
+enum status_code rtc_count_set_count(
+		struct rtc_module *const module,
+		const uint32_t count_value);
+
+uint32_t rtc_count_get_count(struct rtc_module *const module);
+
+enum status_code rtc_count_set_compare(
+		struct rtc_module *const module,
+		const uint32_t comp_value,
+		const enum rtc_count_compare comp_index);
+
+enum status_code rtc_count_get_compare(
+		struct rtc_module *const module,
+		uint32_t *const comp_value,
+		const enum rtc_count_compare comp_index);
+
+enum status_code rtc_count_set_period(
+		struct rtc_module *const module,
+		uint16_t period_value);
+
+enum status_code rtc_count_get_period(
+		struct rtc_module *const module,
+		uint16_t *const period_value);
+
+/** @} */
+
+
+/** \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Check if an RTC overflow has occurred.
+ *
+ * Checks the overflow flag in the RTC. The flag is set when there
+ * is an overflow in the clock.
+ *
+ * \param[in,out]  module  RTC hardware module
+ *
+ * \return Overflow state of the RTC module.
+ *
+ * \retval true   If the RTC count value has overflowed
+ * \retval false  If the RTC count value has not overflowed
+ */
+
+static inline bool rtc_count_is_overflow(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Return status of flag */
+	return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF);
+}
+
+/**
+ * \brief Clears the RTC overflow flag.
+ *
+ * Clears the RTC module counter overflow flag, so that new overflow conditions
+ * can be detected.
+ *
+ * \param[in,out]  module  RTC hardware module
+ */
+static inline void rtc_count_clear_overflow(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Clear OVF flag */
+	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+#ifdef FEATURE_RTC_PERIODIC_INT
+/**
+ * \brief Check if an RTC periodic interval interrupt has occurred.
+ *
+ * Checks the periodic interval flag in the RTC.
+ *
+ * \param[in,out]  module  RTC hardware module
+ * \param[in]  n  RTC periodic interval interrupt
+ *
+ * \return Periodic interval interrupt state of the RTC module.
+ *
+ * \retval true   RTC periodic interval interrupt occurs
+ * \retval false  RTC periodic interval interrupt doesn't occur
+ */
+static inline bool rtc_count_is_periodic_interval(struct rtc_module *const module,
+										enum rtc_count_periodic_interval n)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Return status of flag */
+	return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER(1 << n));
+}
+
+/**
+ * \brief Clears the RTC periodic interval flag.
+ *
+ * Clears the RTC module counter periodic interval flag, so that new periodic
+ *  interval conditions can be detected.
+ *
+ * \param[in,out]  module  RTC hardware module
+ * \param[in]  n  RTC periodic interval interrupt
+ */
+static inline void rtc_count_clear_periodic_interval(struct rtc_module *const module,
+												enum rtc_count_periodic_interval n)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Clear periodic interval flag */
+	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER(1 << n);
+}
+#endif
+bool rtc_count_is_compare_match(
+		struct rtc_module *const module,
+		const enum rtc_count_compare comp_index);
+
+enum status_code rtc_count_clear_compare_match(
+		struct rtc_module *const module,
+		const enum rtc_count_compare comp_index);
+
+/** @} */
+
+
+/**
+ * \name Event Management
+ * @{
+ */
+
+/**
+ * \brief Enables an RTC event output.
+ *
+ *  Enables one or more output events from the RTC module. See
+ *  \ref rtc_count_events for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in,out]  module  RTC hardware module
+ *  \param[in] events    Struct containing flags of events to enable
+ */
+static inline void rtc_count_enable_events(
+		struct rtc_module *const module,
+		struct rtc_count_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Check if the user has requested an overflow event */
+	if (events->generate_event_on_overflow) {
+		event_mask |= RTC_MODE0_EVCTRL_OVFEO;
+	}
+
+	/* Check if the user has requested any compare events */
+	for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+		if (events->generate_event_on_compare[i]) {
+			event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
+		}
+	}
+
+	/* Check if the user has requested any periodic events */
+	for (uint8_t i = 0; i < 8; i++) {
+		if (events->generate_event_on_periodic[i]) {
+			event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
+		}
+	}
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/* Check if the user has requested a tamper event output. */
+	if (events->generate_event_on_tamper) {
+		event_mask |= RTC_MODE0_EVCTRL_TAMPEREO;
+	}
+
+	/* Check if the user has requested a tamper event input. */
+	if (events->on_event_to_tamper) {
+		event_mask |= RTC_MODE0_EVCTRL_TAMPEVEI;
+	}
+#endif
+
+	/* Enable given event(s). */
+	rtc_module->MODE0.EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables an RTC event output.
+ *
+ *  Disabled one or more output events from the RTC module. See
+ *  \ref rtc_count_events for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in,out]  module  RTC hardware module
+ *  \param[in] events    Struct containing flags of events to disable
+ */
+static inline void rtc_count_disable_events(
+		struct rtc_module *const module,
+		struct rtc_count_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Check if the user has requested an overflow event */
+	if (events->generate_event_on_overflow) {
+		event_mask |= RTC_MODE0_EVCTRL_OVFEO;
+	}
+
+	/* Check if the user has requested any compare events */
+	for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+		if (events->generate_event_on_compare[i]) {
+			event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
+		}
+	}
+
+	/* Check if the user has requested any periodic events */
+	for (uint8_t i = 0; i < 8; i++) {
+		if (events->generate_event_on_periodic[i]) {
+			event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
+		}
+	}
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	/* Check if the user has requested a tamper event output. */
+	if (events->generate_event_on_tamper) {
+		event_mask |= RTC_MODE0_EVCTRL_TAMPEREO;
+	}
+
+	/* Check if the user has requested a tamper event input. */
+	if (events->on_event_to_tamper) {
+		event_mask |= RTC_MODE0_EVCTRL_TAMPEVEI;
+	}
+#endif
+
+	/* Disable given event(s). */
+	rtc_module->MODE0.EVCTRL.reg &= ~event_mask;
+}
+
+/** @} */
+
+#ifdef FEATURE_RTC_GENERAL_PURPOSE_REG
+/**
+ * \name RTC General Purpose Registers
+ * @{
+ */
+
+/**
+ * \brief Write a value into general purpose register.
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] n  General purpose type
+ * \param[in] index General purpose register index (0..3)
+ *
+ */
+static inline void rtc_write_general_purpose_reg(
+	struct rtc_module *const module,
+	const  uint8_t index,
+	uint32_t value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(index <= 3);
+
+	Rtc *const rtc_module = module->hw;
+
+	rtc_module->MODE0.GP[index].reg = value;
+}
+
+/**
+ * \brief Read the value from general purpose register.
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] index General purpose register index (0..3)
+ *
+ * \return Value of general purpose register.
+ */
+static inline uint32_t rtc_read_general_purpose_reg(
+	struct rtc_module *const module,
+	const  uint8_t index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(index <= 3);
+
+	Rtc *const rtc_module = module->hw;
+
+	return rtc_module->MODE0.GP[index].reg;
+}
+
+/** @} */
+#endif
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+#include "rtc_tamper.h"
+/**
+ * \brief Get the tamper stamp value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ *
+ * \return The current tamper stamp value as a 32-bit unsigned integer.
+ */
+uint32_t rtc_tamper_get_stamp (struct rtc_module *const module);
+#endif
+
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_sam0_rtc_count_extra Extra Information for RTC COUNT Driver
+ *
+ * \section asfdoc_sam0_rtc_count_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</td>
+ *		<th>Description</td>
+ *	</tr>
+ *	<tr>
+ *		<td>RTC</td>
+ *		<td>Real Time Counter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PPM</td>
+ *		<td>Part Per Million</td>
+ *	</tr>
+ *	<tr>
+ *		<td>RC</td>
+ *		<td>Resistor/Capacitor</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for SAM C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for SAM L21/L22</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for SAM R30</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for RTC tamper feature</td>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *          Added driver instance parameter to all API function calls, except
+ *          get_config_defaults
+ *      </td>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *			Updated initialization function to also enable the digital interface
+ *          clock to the module if it is disabled
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_rtc_count_exqsg Examples for RTC (COUNT) Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_rtc_count_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that a QSG can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_rtc_count_basic_use_case
+ * \if RTC_COUNT_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_rtc_count_callback_use_case
+ * \endif
+ *  - \subpage asfdoc_sam0_rtc_tamper_dma_use_case
+ *
+ * \page asfdoc_sam0_rtc_count_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42111E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42111D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42111C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42111B</td>
+ *		<td>06/2013</td>
+ *		<td>Added additional documentation on the event system. Corrected
+ *          documentation typos.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42111A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* RTC_COUNT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count_interrupt.h
new file mode 100644
index 0000000000..02fdd5d7df
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count_interrupt.h
@@ -0,0 +1,90 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Interrupt Mode)
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef RTC_COUNT_INTERRUPT_H_INCLUDED
+#define RTC_COUNT_INTERRUPT_H_INCLUDED
+
+#include "rtc_count.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_rtc_count_group
+ * @{
+ */
+
+ /**
+ * \name Callbacks
+ * @{
+ */
+enum status_code rtc_count_register_callback(
+		struct rtc_module *const module,
+		rtc_count_callback_t callback,
+		enum rtc_count_callback callback_type);
+
+enum status_code rtc_count_unregister_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type);
+
+void rtc_count_enable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type);
+
+void rtc_count_disable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTC_COUNT_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar.c
new file mode 100644
index 0000000000..a53bb3a3a2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar.c
@@ -0,0 +1,676 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Calendar Mode)
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "rtc_calendar.h"
+#include <gclk.h>
+
+#if !defined(__DOXYGEN__)
+struct rtc_module *_rtc_instance[RTC_INST_NUM];
+#endif
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in]  module  RTC hardware module
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false If the module has completed synchronization
+ * \retval true If the module synchronization is ongoing
+ */
+static inline bool rtc_calendar_is_syncing(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+        if (rtc_module->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) {
+                return true;
+        }
+
+        return false;
+}
+
+/**
+ * \brief Enables the RTC module.
+ *
+ * Enables the RTC module once it has been configured, ready for use. Most
+ * module configuration parameters cannot be altered while the module is enabled.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void rtc_calendar_enable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_CALENDAR_ASYNC == true
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Enable RTC module. */
+	rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE;
+}
+
+/**
+ * \brief Disables the RTC module.
+ *
+ * Disables the RTC module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void rtc_calendar_disable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_CALENDAR_ASYNC == true
+	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Disbale interrupt */
+	rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_MASK;
+
+	/* Disable RTC module. */
+	rtc_module->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE;
+}
+
+/**
+ * \brief Resets the RTC module
+ *
+ * Resets the RTC module to hardware defaults.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void rtc_calendar_reset(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable module before reset. */
+	rtc_calendar_disable(module);
+
+#if RTC_CALENDAR_ASYNC == true
+	module->registered_callback = 0;
+	module->enabled_callback    = 0;
+#endif
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Initiate software reset. */
+	rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST;
+}
+
+/**
+ * \brief Convert time structure to register_value.
+ * Retrieves register_value convert by the time structure.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] time  Pointer to the time structure
+ *
+ * \return 32-bit value.
+ */
+uint32_t rtc_calendar_time_to_register_value(
+		struct rtc_module *const module,
+		const struct rtc_calendar_time *const time)
+{
+	/* Initialize return value. */
+	uint32_t register_value;
+
+	/* Set year value into register_value minus initial year. */
+	register_value = (time->year - module->year_init_value) <<
+			RTC_MODE2_CLOCK_YEAR_Pos;
+
+	/* Set month value into register_value. */
+	register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos);
+
+	/* Set day value into register_value. */
+	register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos);
+
+	/* Set 24 hour value into register_value. */
+	register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos);
+
+	/* Check if 24 h clock and set pm flag. */
+	if (!(module->clock_24h) && (time->pm)) {
+		/* Set pm flag. */
+		register_value |= RTC_MODE2_CLOCK_HOUR_PM;
+	}
+
+	/* Set minute value into register_value. */
+	register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos);
+
+	/* Set second value into register_value. */
+	register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos);
+
+	return register_value;
+}
+
+/**
+ * \brief Convert register_value to time structure.
+ * Retrieves the time structure convert by register_value.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] register_value  The value stored in register
+ * \param[out] time  Pointer to the time structure
+ */
+void rtc_calendar_register_value_to_time(
+		struct rtc_module *const module,
+		const uint32_t register_value,
+		struct rtc_calendar_time *const time)
+{
+	/* Set year plus value of initial year. */
+	time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >>
+			RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value;
+
+	/* Set month value into time struct. */
+	time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >>
+			RTC_MODE2_CLOCK_MONTH_Pos);
+
+	/* Set day value into time struct. */
+	time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >>
+			RTC_MODE2_CLOCK_DAY_Pos);
+
+	if (module->clock_24h) {
+		/* Set hour in 24h mode. */
+		time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >>
+				RTC_MODE2_CLOCK_HOUR_Pos);
+	} else {
+		/* Set hour in 12h mode. */
+		time->hour = ((register_value &
+				(RTC_MODE2_CLOCK_HOUR_Msk & ~RTC_MODE2_CLOCK_HOUR_PM)) >>
+				RTC_MODE2_CLOCK_HOUR_Pos);
+
+		/* Set pm flag */
+		time->pm = ((register_value & RTC_MODE2_CLOCK_HOUR_PM) != 0);
+	}
+
+	/* Set minute value into time struct. */
+	time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >>
+			RTC_MODE2_CLOCK_MINUTE_Pos);
+
+	/* Set second value into time struct. */
+	time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >>
+			RTC_MODE2_CLOCK_SECOND_Pos);
+}
+
+/**
+ * \internal Applies the given configuration.
+ *
+ * Set the configurations given from the configuration structure to the
+ * hardware module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] config  Pointer to the configuration structure.
+ */
+static void _rtc_calendar_set_config(
+		struct rtc_module *const module,
+		const struct rtc_calendar_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Set up temporary register value. */
+	uint16_t tmp_reg;
+
+	/* Set to calendar mode and set the prescaler. */
+	tmp_reg = RTC_MODE2_CTRL_MODE(2) | config->prescaler;
+
+	/* Check clock mode. */
+	if (!(config->clock_24h)) {
+		/* Set clock mode 12h. */
+		tmp_reg |= RTC_MODE2_CTRL_CLKREP;
+	}
+
+	/* Check for clear on compare match. */
+	if (config->clear_on_match) {
+		/* Set clear on compare match. */
+		tmp_reg |= RTC_MODE2_CTRL_MATCHCLR;
+	}
+
+	/* Set temporary value to register. */
+	rtc_module->MODE2.CTRL.reg = tmp_reg;
+
+	/* Check to set continuously clock read update mode. */
+	if (config->continuously_update) {
+		/* Set continuously mode. */
+		rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT;
+	}
+
+	/* Set alarm time registers. */
+	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+		rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i);
+	}
+}
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ *
+ * Initializes the module, setting up all given configurations to provide
+ * the desired functionality of the RTC.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in]   hw      Pointer to hardware instance
+ * \param[in]   config  Pointer to the configuration structure
+ */
+void rtc_calendar_init(
+		struct rtc_module *const module,
+		Rtc *const hw,
+		const struct rtc_calendar_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
+
+	/* Set up GCLK */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
+	system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(RTC_GCLK_ID);
+
+	/* Reset module to hardware defaults. */
+	rtc_calendar_reset(module);
+
+	/* Save conf_struct internally for continued use. */
+	module->clock_24h           = config->clock_24h;
+	module->continuously_update = config->continuously_update;
+	module->year_init_value     = config->year_init_value;
+
+#if (RTC_INST_NUM == 1)
+	_rtc_instance[0] = module;
+#else
+	/* Register this instance for callbacks*/
+	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+#endif
+
+	/* Set config. */
+	_rtc_calendar_set_config(module, config);
+}
+
+/**
+ * \brief Swaps between 12h and 24h clock mode.
+ *
+ * Swaps the current RTC time mode:
+ * - If currently in 12h mode, it will swap to 24h
+ * - If currently in 24h mode, it will swap to 12h
+ *
+ * \note This will not change setting in user's configuration structure.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ */
+void rtc_calendar_swap_time_mode(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Initialize time structure. */
+	struct rtc_calendar_time time;
+	struct rtc_calendar_alarm_time alarm;
+
+	/* Get current time. */
+	rtc_calendar_get_time(module, &time);
+
+	/* Check current mode. */
+	if (module->clock_24h) {
+		/* Set pm flag. */
+		time.pm = (uint8_t)(time.hour / 12);
+
+		/* Set 12h clock hour value. */
+		time.hour = time.hour % 12;
+		if (time.hour == 0) {
+			time.hour = 12;
+		}
+
+		/* Update alarms */
+		for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+			rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+			alarm.time.pm = (uint8_t)(alarm.time.hour / 12);
+			alarm.time.hour = alarm.time.hour % 12;
+			if (alarm.time.hour == 0) {
+				alarm.time.hour = 12;
+			}
+			module->clock_24h = false;
+			rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+			module->clock_24h = true;
+		}
+
+		/* Change value in configuration structure. */
+		module->clock_24h = false;
+	} else {
+		/* Set hour value based on pm flag. */
+		if (time.pm == 1) {
+			time.hour = time.hour + 12;
+
+			time.pm = 0;
+		} else if (time.hour == 12) {
+			time.hour = 0;
+		}
+
+		/* Update alarms */
+		for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+			rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+			if (alarm.time.pm == 1) {
+				alarm.time.hour = alarm.time.hour + 12;
+				alarm.time.pm = 0;
+				module->clock_24h = true;
+				rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+				module->clock_24h = false;
+			} else if (alarm.time.hour == 12) {
+				alarm.time.hour = 0;
+			}
+		}
+
+		/* Change value in configuration structure. */
+		module->clock_24h = true;
+	}
+
+	/* Disable RTC so new configuration can be set. */
+	rtc_calendar_disable(module);
+
+	/* Toggle mode. */
+	rtc_module->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP;
+
+	/* Enable RTC. */
+	rtc_calendar_enable(module);
+
+	/* Set new time format in CLOCK register. */
+	rtc_calendar_set_time(module, &time);
+}
+
+/**
+ * \brief Set the current calendar time to desired time.
+ *
+ * Sets the time provided to the calendar.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] time  The time to set in the calendar
+ */
+void rtc_calendar_set_time(
+		struct rtc_module *const module,
+		const struct rtc_calendar_time *const time)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	uint32_t register_value = rtc_calendar_time_to_register_value(module, time);
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Write value to register. */
+	rtc_module->MODE2.CLOCK.reg = register_value;
+}
+
+/**
+ * \brief Get the current calendar value.
+ *
+ * Retrieves the current time of the calendar.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[out] time  Pointer to value that will be filled with current time
+ */
+void rtc_calendar_get_time(
+		struct rtc_module *const module,
+		struct rtc_calendar_time *const time)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Change of read method based on value of continuously_update value in
+	 * the configuration structure. */
+	if (!(module->continuously_update)) {
+		/* Request read on CLOCK register. */
+		rtc_module->MODE2.READREQ.reg = RTC_READREQ_RREQ;
+
+		while (rtc_calendar_is_syncing(module)) {
+			/* Wait for synchronization */
+		}
+	} else if (!(rtc_module->MODE2.READREQ.reg & RTC_READREQ_RCONT)){
+		rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT | RTC_READREQ_RREQ;
+		 /* wait that the first Read request finishes */
+		while (rtc_calendar_is_syncing(module)) {
+			/* Wait for synchronization */
+		}
+	}
+
+	/* Read value. */
+	uint32_t register_value = rtc_module->MODE2.CLOCK.reg;
+
+	/* Convert value to time structure. */
+	rtc_calendar_register_value_to_time(module, register_value, time);
+}
+
+/**
+ * \brief Set the alarm time for the specified alarm.
+ *
+ * Sets the time and mask specified to the requested alarm.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] alarm        The alarm struct to set the alarm with
+ * \param[in] alarm_index  The index of the alarm to set
+ *
+ * \return Status of setting alarm.
+ * \retval STATUS_OK               If alarm was set correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_calendar_set_alarm(
+		struct rtc_module *const module,
+		const struct rtc_calendar_alarm_time *const alarm,
+		const enum rtc_calendar_alarm alarm_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Sanity check. */
+	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Get register_value from time. */
+	uint32_t register_value = rtc_calendar_time_to_register_value(module, &(alarm->time));
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set alarm value. */
+	rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value;
+
+	/* Set alarm mask */
+	rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current alarm time of specified alarm.
+ *
+ * Retrieves the current alarm time for the alarm specified alarm.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[out] alarm  Pointer to the struct that will be filled with alarm
+ *                    time and mask of the specified alarm
+ * \param[in] alarm_index  Index of alarm to get alarm time from
+ *
+ * \return Status of getting alarm.
+ * \retval STATUS_OK               If alarm was read correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_calendar_get_alarm(
+		struct rtc_module *const module,
+		struct rtc_calendar_alarm_time *const alarm,
+		const enum rtc_calendar_alarm alarm_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Sanity check. */
+	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Read alarm value. */
+	uint32_t register_value =
+			rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg;
+
+	/* Convert to time structure. */
+	rtc_calendar_register_value_to_time(module, register_value, &(alarm->time));
+
+	/* Read alarm mask */
+	alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Calibrate for too-slow or too-fast oscillator.
+ *
+ * When used, the RTC will compensate for an inaccurate oscillator. The
+ * RTC module will add or subtract cycles from the RTC prescaler to adjust the
+ * frequency in approximately 1 PPM steps. The provided correction value should
+ * be between -127 and 127, allowing for a maximum 127 PPM correction in either
+ * direction.
+ *
+ * If no correction is needed, set value to zero.
+ *
+ * \note Can only be used when the RTC is operated at 1Hz.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] value Between -127 and 127 used for the correction
+ *
+ * \return Status of the calibration procedure.
+ * \retval STATUS_OK               If calibration was done correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_calendar_frequency_correction(
+		struct rtc_module *const module,
+		const int8_t value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check if valid argument. */
+	if (abs(value) > 0x7F) {
+		/* Value bigger than allowed, return invalid argument. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	uint32_t new_correction_value;
+
+	/* Load the new correction value as a positive value, sign added later */
+	new_correction_value = abs(value);
+
+	/* Convert to positive value and adjust register sign bit. */
+	if (value < 0) {
+		new_correction_value |= RTC_FREQCORR_SIGN;
+	}
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set value. */
+	rtc_module->MODE2.FREQCORR.reg = new_correction_value;
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar_interrupt.c
new file mode 100644
index 0000000000..9664f59773
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar_interrupt.c
@@ -0,0 +1,270 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Calendar Interrupt Mode)
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "rtc_calendar_interrupt.h"
+
+extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ * To enable the callback, the \ref rtc_calendar_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]  callback      Pointer to the function desired for the specified
+ *                           callback
+ * \param[in]  callback_type Callback type to register
+ *
+ * \return                        Status of registering callback.
+ * \retval STATUS_OK              Registering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to register, a callback is not available
+ */
+enum status_code rtc_calendar_register_callback(
+		struct rtc_module *const module,
+		rtc_calendar_callback_t callback,
+		enum rtc_calendar_callback callback_type)
+{
+
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
+		status = STATUS_OK;
+	} else if (callback_type > RTC_NUM_OF_ALARMS) {
+		/* Make sure alarm callback can be registered */
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	if (status == STATUS_OK) {
+		/* Register callback */
+		module->callbacks[callback_type] = callback;
+		/* Set corresponding bit to set callback as registered */
+		module->registered_callback |= (1 << callback_type);
+	}
+
+	return status;
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ *
+ * \return                        Status of unregistering callback.
+ * \retval STATUS_OK              Unregistering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to unregister, a callback is not available
+ */
+enum status_code rtc_calendar_unregister_callback(
+		struct rtc_module *const module,
+		enum rtc_calendar_callback callback_type)
+{
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
+		status = STATUS_OK;
+	} else if (callback_type > RTC_NUM_OF_ALARMS) {
+		/* Make sure alarm callback can be unregistered */
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	if (status == STATUS_OK) {
+		/* Unregister callback */
+		module->callbacks[callback_type] = NULL;
+
+		/* Clear corresponding bit to set callback as unregistered */
+		module->registered_callback &= ~(1 << callback_type);
+	}
+	return status;
+}
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to enable
+ */
+void rtc_calendar_enable_callback(
+		struct rtc_module *const module,
+		enum rtc_calendar_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
+		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_OVF;
+	} else {
+		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_ALARM(1 << callback_type);
+	}
+	/* Mark callback as enabled. */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to disable
+ */
+void rtc_calendar_disable_callback(
+		struct rtc_module *const module,
+		enum rtc_calendar_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable interrupt */
+	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
+		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_OVF;
+	} else {
+		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_ALARM(1 << callback_type);
+	}
+
+	/* Mark callback as disabled. */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal Interrupt handler for RTC
+ *
+ * \param [in] instance_index  Default value 0
+ */
+static void _rtc_interrupt_handler(const uint32_t instance_index)
+{
+	struct rtc_module *module = _rtc_instance[instance_index];
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Combine callback registered and enabled masks */
+	uint16_t callback_mask = module->enabled_callback;
+	callback_mask &= module->registered_callback;
+
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status = rtc_module->MODE2.INTFLAG.reg;
+	interrupt_status &= rtc_module->MODE2.INTENSET.reg;
+
+	if (interrupt_status & RTC_MODE2_INTFLAG_OVF) {
+		/* Overflow interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_OVERFLOW)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_OVERFLOW]();
+		}
+
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 0)) {
+		/* Alarm 0 interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_0)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_0]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 0);
+
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 1)) {
+		#if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+		/* Alarm 1 interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_1)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_1]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 1);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 2)) {
+		#if (RTC_NUM_OF_ALARMS > 2)	|| defined(__DOXYGEN__)
+		/* Alarm 2 interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_2)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_2]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 2);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 3)) {
+		#if (RTC_NUM_OF_ALARMS > 3)	|| defined(__DOXYGEN__)
+		/* Alarm 3 interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_3)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_3]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 3);
+		#endif
+	}
+}
+
+/**
+ * \internal ISR handler for RTC
+ */
+#if (RTC_INST_NUM == 1)
+void RTC_Handler(void)
+{
+	_rtc_interrupt_handler(0);
+}
+#elif (RTC_INST_NUM > 1)
+#  define _RTC_INTERRUPT_HANDLER(n, unused) \
+		void RTC##n##_Handler(void) \
+		{ \
+			_rtc_interrupt_handler(n); \
+		}
+
+MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
+#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count.c
new file mode 100644
index 0000000000..044fcabe7e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count.c
@@ -0,0 +1,784 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Mode)
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "rtc_count.h"
+#include <gclk.h>
+
+#if !defined(__DOXYGEN__)
+struct rtc_module *_rtc_instance[RTC_INST_NUM];
+#endif
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in]  module  RTC hardware module
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static bool rtc_count_is_syncing(struct rtc_module *const module)
+{
+ 	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+        if (rtc_module->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) {
+                return true;
+        }
+
+        return false;
+}
+
+/**
+ * \brief Enables the RTC module.
+ *
+ * Enables the RTC module once it has been configured, ready for use. Most
+ * module configuration parameters cannot be altered while the module is enabled.
+ *
+ * \param[in,out]  module  RTC hardware module
+ */
+void rtc_count_enable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_COUNT_ASYNC == true
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Enable RTC module. */
+	rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
+}
+
+/**
+ * \brief Disables the RTC module.
+ *
+ * Disables the RTC module.
+ *
+ * \param[in,out]  module  RTC hardware module
+ */
+void rtc_count_disable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_COUNT_ASYNC == true
+	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Disbale interrupt */
+	rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
+
+	/* Disable RTC module. */
+	rtc_module->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
+}
+
+/**
+ * \brief Resets the RTC module.
+ * Resets the RTC to hardware defaults.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ */
+void rtc_count_reset(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable module before reset. */
+	rtc_count_disable(module);
+
+#if RTC_COUNT_ASYNC == true
+	module->registered_callback = 0;
+	module->enabled_callback    = 0;
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Initiate software reset. */
+	rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST;
+}
+
+/**
+ * \internal Applies the given configuration.
+ *
+ * Sets the configurations given from the configuration structure to the
+ * hardware module.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in] config  Pointer to the configuration structure.
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               RTC configurations was set successfully.
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given.
+ */
+static enum status_code _rtc_count_set_config(
+		struct rtc_module *const module,
+		const struct rtc_count_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	rtc_module->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | config->prescaler;
+
+	/* Set mode and clear on match if applicable. */
+	switch (config->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Set 32bit mode and clear on match if applicable. */
+			rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(0);
+
+			/* Check if clear on compare match should be set. */
+			if (config->clear_on_match) {
+				/* Set clear on match. */
+				rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR;
+			}
+			/* Set compare values. */
+			for (uint8_t i = 0; i < RTC_NUM_OF_COMP32; i++) {
+				while (rtc_count_is_syncing(module)) {
+					/* Wait for synchronization */
+				}
+
+				rtc_count_set_compare(module, config->compare_values[i],
+						(enum rtc_count_compare)i);
+			}
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Set 16bit mode. */
+			rtc_module->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(1);
+
+			/* Check if match on clear is set, and return invalid
+			 * argument if set. */
+			if (config->clear_on_match) {
+				Assert(false);
+				return STATUS_ERR_INVALID_ARG;
+			}
+			/* Set compare values. */
+			for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+				while (rtc_count_is_syncing(module)) {
+					/* Wait for synchronization */
+				}
+
+				rtc_count_set_compare(module, config->compare_values[i],
+						(enum rtc_count_compare)i);
+			}
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check to set continuously clock read update mode. */
+	if (config->continuously_update) {
+		/* Set continuously mode. */
+		rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT;
+	}
+
+	/* Return status OK if everything was configured. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ *
+ * Initializes the module, setting up all given configurations to provide
+ * the desired functionality of the RTC.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in]   hw      Pointer to hardware instance
+ * \param[in] config  Pointer to the configuration structure
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK               If the initialization was run stressfully
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given
+ */
+enum status_code rtc_count_init(
+		struct rtc_module *const module,
+		Rtc *const hw,
+		const struct rtc_count_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
+
+	/* Set up GCLK */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
+	system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(RTC_GCLK_ID);
+
+	/* Reset module to hardware defaults. */
+	rtc_count_reset(module);
+
+	/* Save conf_struct internally for continued use. */
+	module->mode                = config->mode;
+	module->continuously_update = config->continuously_update;
+
+#  if (RTC_INST_NUM == 1)
+	_rtc_instance[0] = module;
+#  else
+	/* Register this instance for callbacks*/
+	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+#  endif
+
+	/* Set config and return status. */
+	return _rtc_count_set_config(module, config);
+}
+
+/**
+ * \brief Set the current count value to desired value.
+ *
+ * Sets the value of the counter to the specified value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] count_value  The value to be set in count register
+ *
+ * \return Status of setting the register.
+ * \retval STATUS_OK               If everything was executed correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_count_set_count(
+		struct rtc_module *const module,
+		const uint32_t count_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set count according to mode */
+	switch(module->mode){
+		case RTC_COUNT_MODE_32BIT:
+			/* Write value to register. */
+			rtc_module->MODE0.COUNT.reg = count_value;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check if 16-bit value is provided. */
+			if(count_value > 0xffff){
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Write value to register. */
+			rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current count value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ *
+ * Returns the current count value.
+ *
+ * \return The current counter value as a 32-bit unsigned integer.
+ */
+uint32_t rtc_count_get_count(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Initialize return value. */
+	uint32_t ret_val;
+
+	/* Change of read method based on value of continuously_update value in
+	 * the configuration structure. */
+	if(!(module->continuously_update)) {
+		/* Request read on count register. */
+		rtc_module->MODE0.READREQ.reg = RTC_READREQ_RREQ;
+
+		while (rtc_count_is_syncing(module)) {
+			/* Wait for synchronization */
+		}
+	} else if (!(rtc_module->MODE0.READREQ.reg & RTC_READREQ_RCONT)){
+		rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT | RTC_READREQ_RREQ;
+		 /* wait that the first Read request finishes */
+		while (rtc_count_is_syncing(module)) {
+			/* Wait for synchronization */
+		}
+	}
+
+	/* Read value based on mode. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Return count value in 32-bit mode. */
+			ret_val = rtc_module->MODE0.COUNT.reg;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Return count value in 16-bit mode. */
+			ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
+
+			break;
+
+		default:
+			Assert(false);
+			/* Counter not initialized. Assume counter value 0.*/
+			ret_val = 0;
+			break;
+	}
+
+	return ret_val;
+}
+
+/**
+ * \brief Set the compare value for the specified compare.
+ *
+ * Sets the value specified by the implementer to the requested compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_value  The value to be written to the compare
+ * \param[in] comp_index  Index of the compare to set
+ *
+ * \return Status indicating if compare was successfully set.
+ * \retval STATUS_OK               If compare was successfully set
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_set_compare(
+		struct rtc_module *const module,
+		const uint32_t comp_value,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set compare values based on operation mode. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Set compare value for COMP. */
+			rtc_module->MODE0.COMP[comp_index].reg = comp_value;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Check that 16-bit value is provided. */
+			if (comp_value > 0xffff) {
+				Assert(false);
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Set compare value for COMP. */
+			rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+
+	/* Return status if everything is OK. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current compare value of specified compare.
+ *
+ * Retrieves the current value of the specified compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[out] comp_value  Pointer to 32-bit integer that will be populated with
+ *                         the current compare value
+ * \param[in]  comp_index  Index of compare to check
+ *
+ * \return Status of the reading procedure.
+ * \retval STATUS_OK               If the value was read correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_get_compare(
+		struct rtc_module *const module,
+		uint32_t *const comp_value,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Get compare value for COMP. */
+			*comp_value = rtc_module->MODE0.COMP[comp_index].reg;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Get compare value for COMP. */
+			*comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+	/* Return status showing everything is OK. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the value of period.
+ *
+ * Retrieves the value of the period for the 16-bit mode counter.
+ *
+ * \note Only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[out] period_value  Pointer to value for return argument
+ *
+ * \return Status of getting the period value.
+ * \retval STATUS_OK                   If the period value was read correctly
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If incorrect mode was set
+ */
+enum status_code rtc_count_get_period(
+		struct rtc_module *const module,
+		uint16_t *const period_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check that correct mode is set. */
+	if (module->mode != RTC_COUNT_MODE_16BIT) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Returns the value. */
+	*period_value = rtc_module->MODE1.PER.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Set the given value to the period.
+ *
+ * Sets the given value to the period.
+ *
+ * \note Only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] period_value  The value to set to the period
+ *
+ * \return Status of setting the period value.
+ * \retval STATUS_OK                   If the period was set correctly
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If module is not operated in 16-bit mode
+ */
+enum status_code rtc_count_set_period(
+		struct rtc_module *const module,
+		const uint16_t period_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check that correct mode is set. */
+	if (module->mode != RTC_COUNT_MODE_16BIT) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Write value to register. */
+	rtc_module->MODE1.PER.reg = period_value;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Check if RTC compare match has occurred.
+ *
+ * Checks the compare flag to see if a match has occurred. The compare flag is
+ * set when there is a compare match between counter and the compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_index  Index of compare to check current flag
+ */
+bool rtc_count_is_compare_match(
+		struct rtc_module *const module,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check sanity. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (comp_index > RTC_NUM_OF_COMP32) {
+				return false;
+			}
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (comp_index > RTC_NUM_OF_COMP16) {
+				return false;
+			}
+
+			break;
+
+		default:
+			Assert(false);
+			return false;
+	}
+
+	/* Set status of INTFLAG as return argument. */
+	return (rtc_module->MODE0.INTFLAG.reg & (1 << comp_index)) ? true : false;
+}
+
+/**
+ * \brief Clears RTC compare match flag.
+ *
+ * Clears the compare flag. The compare flag is set when there is a compare
+ * match between the counter and the compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_index  Index of compare to check current flag
+ *
+ * \return Status indicating if flag was successfully cleared.
+ * \retval STATUS_OK               If flag was successfully cleared
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_clear_compare_match(
+		struct rtc_module *const module,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check sanity. */
+	switch (module->mode){
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (comp_index > RTC_NUM_OF_COMP32) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+
+	/* Clear INTFLAG. */
+	rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Calibrate for too-slow or too-fast oscillator.
+ *
+ * When used, the RTC will compensate for an inaccurate oscillator. The
+ * RTC module will add or subtract cycles from the RTC prescaler to adjust the
+ * frequency in approximately 1 PPM steps. The provided correction value should
+ * be between 0 and 127, allowing for a maximum 127 PPM correction.
+ *
+ * If no correction is needed, set value to zero.
+ *
+ * \note Can only be used when the RTC is operated in 1Hz.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] value  Ranging from -127 to 127 used for the correction
+ *
+ * \return Status of the calibration procedure.
+ * \retval STATUS_OK               If calibration was executed correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_count_frequency_correction(
+		struct rtc_module *const module,
+		const int8_t value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check if valid argument. */
+	if (abs(value) > 0x7F) {
+		/* Value bigger than allowed, return invalid argument. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	uint32_t new_correction_value;
+
+	/* Load the new correction value as a positive value, sign added later */
+	new_correction_value = abs(value);
+
+	/* Convert to positive value and adjust register sign bit. */
+	if (value < 0) {
+		new_correction_value |= RTC_FREQCORR_SIGN;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set value. */
+	rtc_module->MODE0.FREQCORR.reg = new_correction_value;
+
+	return STATUS_OK;
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count_interrupt.c
new file mode 100644
index 0000000000..444008e144
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count_interrupt.c
@@ -0,0 +1,320 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Interrupt Mode)
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "rtc_count_interrupt.h"
+
+extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ * To enable the callback, the \ref rtc_count_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]  callback      Pointer to the function desired for the specified
+ *                           callback
+ * \param[in]  callback_type Callback type to register
+ *
+ * \return                        Status of registering callback.
+ * \retval STATUS_OK              Registering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to register a callback not available
+ */
+enum status_code rtc_count_register_callback(
+		struct rtc_module *const module,
+		rtc_count_callback_t callback,
+		enum rtc_count_callback callback_type)
+{
+
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+		status = STATUS_OK;
+	} else {
+		/* Make sure callback type can be registered */
+		switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (callback_type > RTC_NUM_OF_COMP32) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (callback_type > RTC_NUM_OF_COMP16) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		default:
+			status = STATUS_ERR_INVALID_ARG;
+		}
+	}
+
+	if (status == STATUS_OK) {
+		/* Register callback */
+		module->callbacks[callback_type] = callback;
+		/* Set corresponding bit to set callback as registered */
+		module->registered_callback |= (1 << callback_type);
+	}
+
+	return status;
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ *
+ * \return                        Status of unregistering callback.
+ * \retval STATUS_OK              Unregistering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to unregister a callback not available
+ */
+enum status_code rtc_count_unregister_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+		status = STATUS_OK;
+	} else {
+		/* Make sure callback type can be unregistered */
+		switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (callback_type > RTC_NUM_OF_COMP32) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (callback_type > RTC_NUM_OF_COMP16) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		default:
+			status = STATUS_ERR_INVALID_ARG;
+		}
+	}
+	if (status == STATUS_OK) {
+		/* Unregister callback */
+		module->callbacks[callback_type] = NULL;
+
+		/* Clear corresponding bit to set callback as unregistered */
+		module->registered_callback &= ~(1 << callback_type);
+	}
+	return status;
+}
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to enable
+ */
+void rtc_count_enable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
+	} else {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
+	}
+	/* Mark callback as enabled. */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to disable
+ */
+void rtc_count_disable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable interrupt */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
+	} else {
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
+	}
+
+	/* Mark callback as disabled. */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal Interrupt handler for RTC
+ *
+ * \param [in] instance_index  Default value 0
+ */
+static void _rtc_interrupt_handler(const uint32_t instance_index)
+{
+	struct rtc_module *module = _rtc_instance[instance_index];
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Combine callback registered and enabled masks */
+	uint16_t callback_mask = module->enabled_callback;
+	callback_mask &= module->registered_callback;
+
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
+	interrupt_status &= rtc_module->MODE0.INTENSET.reg;
+
+	if (interrupt_status & RTC_MODE0_INTFLAG_OVF) {
+		/* Overflow interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW)) {
+			module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
+		}
+
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0)) {
+		/* Compare 0 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1)) {
+		#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+		/* Compare 1 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2)) {
+		#if (RTC_NUM_OF_COMP16 > 2)	|| defined(__DOXYGEN__)
+		/* Compare 2 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3)) {
+		#if (RTC_NUM_OF_COMP16 > 3)	|| defined(__DOXYGEN__)
+		/* Compare 3 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4)) {
+		#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+		/* Compare 4 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5)) {
+		#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+		/* Compare 5 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
+		#endif
+	}
+}
+
+/**
+ * \internal ISR handler for RTC
+ */
+#if (RTC_INST_NUM == 1)
+void RTC_Handler(void)
+{
+	_rtc_interrupt_handler(0);
+}
+#elif (RTC_INST_NUM > 1)
+#  define _RTC_INTERRUPT_HANDLER(n, unused) \
+		void RTC##n##_Handler(void) \
+		{ \
+			_rtc_interrupt_handler(n); \
+		}
+
+MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
+#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/module_config/conf_rtc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/module_config/conf_rtc.h
new file mode 100644
index 0000000000..f337c7ec4b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/module_config/conf_rtc.h
@@ -0,0 +1,55 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver Configuration Header
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_RTC_H_INCLUDED
+#define CONF_RTC_H_INCLUDED
+
+/** Select RTC clock. Use 1.024kHz from 32kHz internal ULP oscillator(OSCULP32K)
+ *  for RTC clock.
+ */
+#  define RTC_CLOCK_SOURCE    RTC_CLOCK_SELECTION_ULP1K
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar.c
new file mode 100644
index 0000000000..884b24a0b7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar.c
@@ -0,0 +1,824 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Calendar Mode)
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "rtc_calendar.h"
+#include <gclk.h>
+#include "conf_rtc.h"
+
+#if !defined(__DOXYGEN__)
+struct rtc_module *_rtc_instance[RTC_INST_NUM];
+#endif
+
+#if !defined(RTC_CLOCK_SOURCE)
+#  warning  RTC_CLOCK_SOURCE is not defined, assuming RTC_CLOCK_SELECTION_ULP1K.
+#  define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K
+#endif
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in]  module  RTC hardware module
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static inline bool rtc_calendar_is_syncing(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	if (rtc_module->MODE2.SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Enables the RTC module.
+ *
+ * Enables the RTC module once it has been configured, ready for use. Most
+ * module configuration parameters cannot be altered while the module is enabled.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void rtc_calendar_enable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_CALENDAR_ASYNC == true
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Enable RTC module. */
+	rtc_module->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Disables the RTC module.
+ *
+ * Disables the RTC module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void rtc_calendar_disable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_CALENDAR_ASYNC == true
+	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Disbale interrupt */
+	rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_MASK;
+
+	/* Disable RTC module. */
+	rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Resets the RTC module.
+ *
+ * Resets the RTC module to hardware defaults.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void rtc_calendar_reset(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable module before reset. */
+	rtc_calendar_disable(module);
+
+#if RTC_CALENDAR_ASYNC == true
+	module->registered_callback = 0;
+	module->enabled_callback    = 0;
+#endif
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Initiate software reset. */
+	rtc_module->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Convert time structure to register_value.
+ * Retrieves register_value convert by the time structure.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] time  Pointer to the time structure
+ *
+ * \return 32-bit value.
+ */
+uint32_t rtc_calendar_time_to_register_value(
+		struct rtc_module *const module,
+		const struct rtc_calendar_time *const time)
+{
+	/* Initialize return value. */
+	uint32_t register_value;
+
+	/* Set year value into register_value minus initial year. */
+	register_value = (time->year - module->year_init_value) <<
+			RTC_MODE2_CLOCK_YEAR_Pos;
+
+	/* Set month value into register_value. */
+	register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos);
+
+	/* Set day value into register_value. */
+	register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos);
+
+	/* Set 24 hour value into register_value. */
+	register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos);
+
+	/* Check if 24h clock and set pm flag. */
+	if (!(module->clock_24h) && (time->pm)) {
+		/* Set pm flag. */
+		register_value |= (0x10u << RTC_MODE2_CLOCK_HOUR_Pos);
+	}
+
+	/* Set minute value into register_value. */
+	register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos);
+
+	/* Set second value into register_value. */
+	register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos);
+
+	return register_value;
+}
+
+/**
+ * \brief Convert register_value to time structure.
+ * Retrieves the time structure convert by register_value.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] register_value  The value stored in register
+ * \param[out] time  Pointer to the time structure
+ */
+void rtc_calendar_register_value_to_time(
+		struct rtc_module *const module,
+		const uint32_t register_value,
+		struct rtc_calendar_time *const time)
+{
+	/* Set year plus value of initial year. */
+	time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >>
+			RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value;
+
+	/* Set month value into time struct. */
+	time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >>
+			RTC_MODE2_CLOCK_MONTH_Pos);
+
+	/* Set day value into time struct. */
+	time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >>
+			RTC_MODE2_CLOCK_DAY_Pos);
+
+	if (module->clock_24h) {
+		/* Set hour in 24h mode. */
+		time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >>
+				RTC_MODE2_CLOCK_HOUR_Pos);
+	} else {
+		/* Set hour in 12h mode. */
+		time->hour = ((register_value &
+				(RTC_MODE2_CLOCK_HOUR_Msk & ~(0x10u << RTC_MODE2_CLOCK_HOUR_Pos))) >>
+				RTC_MODE2_CLOCK_HOUR_Pos);
+
+		/* Set pm flag */
+		time->pm = ((register_value & (0x10u << RTC_MODE2_CLOCK_HOUR_Pos)) != 0);
+	}
+
+	/* Set minute value into time struct. */
+	time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >>
+			RTC_MODE2_CLOCK_MINUTE_Pos);
+
+	/* Set second value into time struct. */
+	time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >>
+			RTC_MODE2_CLOCK_SECOND_Pos);
+}
+
+/**
+ * \internal Applies the given configuration.
+ *
+ * Set the configurations given from the configuration structure to the
+ * hardware module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] config  Pointer to the configuration structure
+ */
+static void _rtc_calendar_set_config(
+		struct rtc_module *const module,
+		const struct rtc_calendar_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Set up temporary register value. */
+	uint16_t tmp_reg;
+
+	/* Set to calendar mode and set the prescaler. */
+	tmp_reg = RTC_MODE2_CTRLA_MODE(2) | config->prescaler;
+
+#if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	if(config->enable_read_sync) {
+		tmp_reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
+	}
+#endif
+
+	/* Check clock mode. */
+	if (!(config->clock_24h)) {
+		/* Set clock mode 12h. */
+		tmp_reg |= RTC_MODE2_CTRLA_CLKREP;
+	}
+
+	/* Check for clear on compare match. */
+	if (config->clear_on_match) {
+		/* Set clear on compare match. */
+		tmp_reg |= RTC_MODE2_CTRLA_MATCHCLR;
+	}
+
+	/* Set temporary value to register. */
+	rtc_module->MODE2.CTRLA.reg = tmp_reg;
+
+	/* Set alarm time registers. */
+	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+		rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i);
+	}
+}
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ *
+ * Initializes the module, setting up all given configurations to provide
+ * the desired functionality of the RTC.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in]   hw      Pointer to hardware instance
+ * \param[in]   config  Pointer to the configuration structure
+ */
+void rtc_calendar_init(
+		struct rtc_module *const module,
+		Rtc *const hw,
+		const struct rtc_calendar_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC);
+
+	/* Select RTC clock */
+	OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE;
+
+	/* Reset module to hardware defaults. */
+	rtc_calendar_reset(module);
+
+	/* Save conf_struct internally for continued use. */
+	module->clock_24h           = config->clock_24h;
+	module->year_init_value     = config->year_init_value;
+
+#if (RTC_INST_NUM == 1)
+	_rtc_instance[0] = module;
+#else
+	/* Register this instance for callbacks*/
+	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+#endif
+
+	/* Set config. */
+	_rtc_calendar_set_config(module, config);
+}
+
+/**
+ * \brief Swaps between 12h and 24h clock mode.
+ *
+ * Swaps the current RTC time mode.
+ * - If currently in 12h mode, it will swap to 24h.
+ * - If currently in 24h mode, it will swap to 12h.
+ *
+ * \note This will not change setting in user's configuration structure.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ */
+void rtc_calendar_swap_time_mode(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Initialize time structure. */
+	struct rtc_calendar_time time;
+	struct rtc_calendar_alarm_time alarm;
+
+	/* Get current time. */
+	rtc_calendar_get_time(module, &time);
+
+	/* Check current mode. */
+	if (module->clock_24h) {
+		/* Set pm flag. */
+		time.pm = (uint8_t)(time.hour / 12);
+
+		/* Set 12h clock hour value. */
+		time.hour = time.hour % 12;
+		if (time.hour == 0) {
+			time.hour = 12;
+		}
+
+		/* Update alarms */
+		for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+			rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+			alarm.time.pm = (uint8_t)(alarm.time.hour / 12);
+			alarm.time.hour = alarm.time.hour % 12;
+			if (alarm.time.hour == 0) {
+				alarm.time.hour = 12;
+			}
+			module->clock_24h = false;
+			rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+			module->clock_24h = true;
+		}
+
+		/* Change value in configuration structure. */
+		module->clock_24h = false;
+	} else {
+		/* Set hour value based on pm flag. */
+		if (time.pm == 1) {
+			time.hour = time.hour + 12;
+
+			time.pm = 0;
+		} else if (time.hour == 12) {
+			time.hour = 0;
+		}
+
+		/* Update alarms */
+		for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+			rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+			if (alarm.time.pm == 1) {
+				alarm.time.hour = alarm.time.hour + 12;
+				alarm.time.pm = 0;
+				module->clock_24h = true;
+				rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+				module->clock_24h = false;
+			} else if (alarm.time.hour == 12) {
+				alarm.time.hour = 0;
+			}
+		}
+
+		/* Change value in configuration structure. */
+		module->clock_24h = true;
+	}
+
+	/* Disable RTC so new configuration can be set. */
+	rtc_calendar_disable(module);
+
+	/* Toggle mode. */
+	rtc_module->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
+
+	/* Enable RTC. */
+	rtc_calendar_enable(module);
+
+	/* Set new time format in CLOCK register. */
+	rtc_calendar_set_time(module, &time);
+}
+
+/**
+ * \brief Set the current calendar time to desired time.
+ *
+ * Sets the time provided to the calendar.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] time  The time to set in the calendar
+ */
+void rtc_calendar_set_time(
+		struct rtc_module *const module,
+		const struct rtc_calendar_time *const time)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	uint32_t register_value = rtc_calendar_time_to_register_value(module, time);
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Write value to register. */
+	rtc_module->MODE2.CLOCK.reg = register_value;
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Get the current calendar value.
+ *
+ * Retrieves the current time of the calendar.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[out] time  Pointer to value that will be filled with current time
+ */
+void rtc_calendar_get_time(
+		struct rtc_module *const module,
+		struct rtc_calendar_time *const time)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Read value. */
+	uint32_t register_value = rtc_module->MODE2.CLOCK.reg;
+
+	/* Convert value to time structure. */
+	rtc_calendar_register_value_to_time(module, register_value, time);
+}
+
+/**
+ * \brief Set the alarm time for the specified alarm.
+ *
+ * Sets the time and mask specified to the requested alarm.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] alarm        The alarm struct to set the alarm with
+ * \param[in] alarm_index  The index of the alarm to set
+ *
+ * \return Status of setting alarm.
+ * \retval STATUS_OK               If alarm was set correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_calendar_set_alarm(
+		struct rtc_module *const module,
+		const struct rtc_calendar_alarm_time *const alarm,
+		const enum rtc_calendar_alarm alarm_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Sanity check. */
+	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Get register_value from time. */
+	uint32_t register_value = rtc_calendar_time_to_register_value(module, &(alarm->time));
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set alarm value. */
+	rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value;
+
+	while (rtc_calendar_is_syncing(module)) {
+			/* Wait for synchronization */
+	}
+
+	/* Set alarm mask */
+	rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask;
+
+	while (rtc_calendar_is_syncing(module)) {
+			/* Wait for synchronization */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current alarm time of specified alarm.
+ *
+ * Retrieves the current alarm time for the specified alarm.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[out] alarm  Pointer to the struct that will be filled with alarm
+ *                    time and mask of the specified alarm.
+ * \param[in] alarm_index  Index of alarm to get alarm time from
+ *
+ * \return Status of getting alarm.
+ * \retval STATUS_OK               If alarm was read correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_calendar_get_alarm(
+		struct rtc_module *const module,
+		struct rtc_calendar_alarm_time *const alarm,
+		const enum rtc_calendar_alarm alarm_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Sanity check. */
+	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Read alarm value. */
+	uint32_t register_value =
+			rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg;
+
+	/* Convert to time structure. */
+	rtc_calendar_register_value_to_time(module, register_value, &(alarm->time));
+
+	/* Read alarm mask */
+	alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Calibrate for too-slow or too-fast oscillator.
+ *
+ * When used, the RTC will compensate for an inaccurate oscillator. The
+ * RTC module will add or subtract cycles from the RTC prescaler to adjust the
+ * frequency in approximately 1 PPM steps. The provided correction value should
+ * be between 0 and 127, allowing for a maximum 127 PPM correction in either
+ * direction.
+ *
+ * If no correction is needed, set value to zero.
+ *
+ * \note Can only be used when the RTC is operated at 1Hz.
+ *
+ * \param[in, out] module  Pointer to the software instance struct
+ * \param[in] value Between -127 and 127 used for the correction
+ *
+ * \return Status of the calibration procedure.
+ * \retval STATUS_OK               If calibration was done correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_calendar_frequency_correction(
+		struct rtc_module *const module,
+		const int8_t value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check if valid argument. */
+	if (abs(value) > 0x7F) {
+		/* Value bigger than allowed, return invalid argument. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	uint32_t new_correction_value;
+
+	/* Load the new correction value as a positive value, sign added later */
+	new_correction_value = abs(value);
+
+	/* Convert to positive value and adjust register sign bit. */
+	if (value < 0) {
+		new_correction_value |= RTC_FREQCORR_SIGN;
+	}
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set value. */
+	rtc_module->MODE2.FREQCORR.reg = new_correction_value;
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	return STATUS_OK;
+}
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+/**
+ * \brief Applies the given configuration.
+ *
+ * Sets the configurations given from the configuration structure to the
+ * RTC tamper and it should be called before RTC module enable.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in] config  Pointer to the configuration structure
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               RTC configurations was set successfully
+ *
+ * \note If tamper input configured as active layer protection, RTC prescaler
+ *       output automatically enabled in the function.
+ */
+enum status_code rtc_tamper_set_config ( 
+		struct rtc_module *const module,
+		struct rtc_tamper_config *const tamper_cfg)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(tamper_cfg);
+
+	Rtc *const rtc_module = module->hw;
+	uint16_t ctrl_b = 0;
+
+	/* Configure enable backup and GP register reset on tamper or not. */
+	if(tamper_cfg->bkup_reset_on_tamper) {
+		rtc_module->MODE2.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+	} else {
+		rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+	}
+	
+	if (tamper_cfg->gp_reset_on_tamper) {
+		rtc_module->MODE2.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+	} else {
+		rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+	}
+
+	/* Configure tamper detection of frequency and debounce setting. */
+	ctrl_b = tamper_cfg->actl_freq_div | tamper_cfg->deb_freq_div;
+	if(tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_ASYNC) {
+		ctrl_b |= RTC_MODE0_CTRLB_DEBASYNC;
+	} else if (tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_MAJORITY) {
+		ctrl_b |= RTC_MODE0_CTRLB_DEBMAJ;
+	}
+	if(tamper_cfg->dma_tamper_enable) {
+		ctrl_b |= RTC_MODE0_CTRLB_DMAEN;
+	}
+	if (tamper_cfg->gp0_enable) {
+		ctrl_b |= RTC_MODE0_CTRLB_GP0EN;
+	}
+
+	/* Configure tamper input. */
+	volatile RTC_TAMPCTRL_Type *tamper_ctrl = &(rtc_module->MODE2.TAMPCTRL);
+
+	struct rtc_tamper_input_config in_cfg;
+	for (uint8_t tamper_id = 0; tamper_id < RTC_TAMPER_NUM; tamper_id++) {
+		in_cfg = tamper_cfg->in_cfg[tamper_id];
+
+		if(in_cfg.action == RTC_TAMPER_INPUT_ACTION_ACTL) {
+			ctrl_b |= RTC_MODE0_CTRLB_RTCOUT;
+		}
+	
+		switch(tamper_id) {
+			case 0:
+				tamper_ctrl->bit.IN0ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL0 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC0 = in_cfg.debounce_enable;
+				break;
+			case 1:
+				tamper_ctrl->bit.IN1ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL1 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC1 = in_cfg.debounce_enable;
+				break;
+			case 2:
+				tamper_ctrl->bit.IN2ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL2 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC2 = in_cfg.debounce_enable;
+				break;
+			case 3:
+				tamper_ctrl->bit.IN3ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL3 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC3 = in_cfg.debounce_enable;
+				break;
+			case 4:
+				tamper_ctrl->bit.IN4ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL4 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC4 = in_cfg.debounce_enable;
+				break;
+			default:
+				Assert(false);
+				break;
+		}
+	}
+
+	rtc_module->MODE2.CTRLB.reg = ctrl_b;
+
+	/* Return status OK if everything was configured. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the tamper stamp value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[out] time  Pointer to value that filled with tamper stamp time
+ */
+void rtc_tamper_get_stamp (struct rtc_module *const module,
+		struct rtc_calendar_time *const time)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_calendar_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Initialize return value. */
+	uint32_t tamper_stamp = rtc_module->MODE2.TIMESTAMP.reg;
+
+	/* Convert value to time structure. */
+	rtc_calendar_register_value_to_time(module, tamper_stamp, time);
+}
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar_interrupt.c
new file mode 100644
index 0000000000..a00604ffa6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar_interrupt.c
@@ -0,0 +1,315 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Calendar Interrupt Mode)
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "rtc_calendar_interrupt.h"
+
+extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
+
+/**
+ * \brief Registers callback for the specified callback type.
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ * To enable the callback, the \ref rtc_calendar_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]  callback      Pointer to the function desired for the specified
+ *                           callback
+ * \param[in]  callback_type Callback type to register
+ *
+ * \return                        Status of registering callback.
+ * \retval STATUS_OK              Registering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to register, a callback is not available
+ */
+enum status_code rtc_calendar_register_callback(
+		struct rtc_module *const module,
+		rtc_calendar_callback_t callback,
+		enum rtc_calendar_callback callback_type)
+{
+
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+		|| callback_type == RTC_CALENDAR_CALLBACK_TAMPER
+#endif
+		|| (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7)) {
+		status = STATUS_OK;
+	} else if (callback_type > (RTC_NUM_OF_ALARMS + RTC_PER_NUM)) {
+		/* Make sure alarm callback can be registered */
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	if (status == STATUS_OK) {
+		/* Register callback */
+		module->callbacks[callback_type] = callback;
+		/* Set corresponding bit to set callback as registered */
+		module->registered_callback |= (1 << callback_type);
+	}
+
+	return status;
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type.
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ *
+ * \return                        Status of unregistering callback.
+ * \retval STATUS_OK              Unregistering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to unregister, a callback is not available
+ */
+enum status_code rtc_calendar_unregister_callback(
+		struct rtc_module *const module,
+		enum rtc_calendar_callback callback_type)
+{
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+		|| callback_type == RTC_CALENDAR_CALLBACK_TAMPER
+#endif
+		|| (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7)) {
+		status = STATUS_OK;
+	} else if (callback_type > (RTC_NUM_OF_ALARMS + RTC_PER_NUM)) {
+		/* Make sure alarm callback can be unregistered */
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	if (status == STATUS_OK) {
+		/* Unregister callback */
+		module->callbacks[callback_type] = NULL;
+
+		/* Clear corresponding bit to set callback as unregistered */
+		module->registered_callback &= ~(1 << callback_type);
+	}
+	return status;
+}
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to enable
+ */
+void rtc_calendar_enable_callback(
+		struct rtc_module *const module,
+		enum rtc_calendar_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
+		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_OVF;
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (callback_type == RTC_CALENDAR_CALLBACK_TAMPER) {
+		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_TAMPER;
+#endif
+	} else if (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7) {
+		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_PER((1 << callback_type));
+	}else {
+		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_ALARM(1 << (callback_type - RTC_PER_NUM));
+	}
+	/* Mark callback as enabled. */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to disable
+ */
+void rtc_calendar_disable_callback(
+		struct rtc_module *const module,
+		enum rtc_calendar_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable interrupt */
+	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
+		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_OVF;
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (callback_type == RTC_CALENDAR_CALLBACK_TAMPER) {
+		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_TAMPER;
+#endif
+	} else if (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7) {
+		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_PER((1 << callback_type));
+	}else {
+		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_ALARM(1 << (callback_type - RTC_PER_NUM));
+	}
+
+	/* Mark callback as disabled. */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal Interrupt handler for RTC
+ *
+ * \param [in] instance_index  Default value 0
+ */
+static void _rtc_interrupt_handler(const uint32_t instance_index)
+{
+	struct rtc_module *module = _rtc_instance[instance_index];
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Combine callback registered and enabled masks */
+	uint16_t callback_mask = module->enabled_callback;
+	callback_mask &= module->registered_callback;
+
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status = rtc_module->MODE2.INTFLAG.reg;
+	interrupt_status &= rtc_module->MODE2.INTENSET.reg;
+
+	if (interrupt_status & RTC_MODE2_INTFLAG_OVF) {
+		/* Overflow interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_OVERFLOW)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_OVERFLOW]();
+		}
+
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_TAMPER) {
+		/* Tamper interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_TAMPER)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_TAMPER]();
+		}
+
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+#endif
+	}else if (interrupt_status & RTC_MODE2_INTFLAG_PER(0xff)) {
+		uint8_t i  = 0;
+		for (i = 0;i < RTC_PER_NUM;i++) {
+			if ((interrupt_status & RTC_MODE2_INTFLAG_PER(1 << i))
+			  && (callback_mask & (1 << i))) {
+				module->callbacks[i]();
+			}
+
+			/* Clear interrupt flag */
+			rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER(1<<i);
+		}
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 0)) {
+		/* Alarm 0 interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_0)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_0]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 0);
+
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 1)) {
+		#if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+		/* Alarm 1 interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_1)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_1]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 1);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 2)) {
+		#if (RTC_NUM_OF_ALARMS > 2)	|| defined(__DOXYGEN__)
+		/* Alarm 2 interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_2)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_2]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 2);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 3)) {
+		#if (RTC_NUM_OF_ALARMS > 3)	|| defined(__DOXYGEN__)
+		/* Alarm 3 interrupt */
+		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_3)) {
+			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_3]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 3);
+		#endif
+	}
+}
+
+/**
+ * \internal ISR handler for RTC
+ */
+#if (RTC_INST_NUM == 1)
+void RTC_Handler(void)
+{
+	_rtc_interrupt_handler(0);
+}
+#elif (RTC_INST_NUM > 1)
+#  define _RTC_INTERRUPT_HANDLER(n, unused) \
+		void RTC##n##_Handler(void) \
+		{ \
+			_rtc_interrupt_handler(n); \
+		}
+
+MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
+#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count.c
new file mode 100644
index 0000000000..ae73d9399a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count.c
@@ -0,0 +1,951 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Mode)
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "rtc_count.h"
+#include <clock.h>
+#include <gclk.h>
+#include "conf_rtc.h"
+
+#if !defined(__DOXYGEN__)
+struct rtc_module *_rtc_instance[RTC_INST_NUM];
+#endif
+
+#if !defined(RTC_CLOCK_SOURCE)
+#  warning  RTC_CLOCK_SOURCE is not defined, assuming RTC_CLOCK_SELECTION_ULP1K.
+#  define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K
+#endif
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in]  module  RTC hardware module
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static bool rtc_count_is_syncing(struct rtc_module *const module)
+{
+ 	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	if (rtc_module->MODE0.SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Enables the RTC module.
+ *
+ * Enables the RTC module once it has been configured, ready for use. Most
+ * module configuration parameters cannot be altered while the module is enabled.
+ *
+ * \param[in,out]  module  RTC hardware module
+ */
+void rtc_count_enable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_COUNT_ASYNC == true
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Enable RTC module. */
+	rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Disables the RTC module.
+ *
+ * Disables the RTC module.
+ *
+ * \param[in,out]  module  RTC hardware module
+ */
+void rtc_count_disable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_COUNT_ASYNC == true
+	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Disbale interrupt */
+	rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
+
+	/* Disable RTC module. */
+	rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Resets the RTC module.
+ * Resets the RTC to hardware defaults.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ */
+void rtc_count_reset(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable module before reset. */
+	rtc_count_disable(module);
+
+#if RTC_COUNT_ASYNC == true
+	module->registered_callback = 0;
+	module->enabled_callback    = 0;
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Initiate software reset. */
+	rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \internal Applies the given configuration.
+ *
+ * Sets the configurations given from the configuration structure to the
+ * hardware module
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in] config  Pointer to the configuration structure
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               RTC configurations was set successfully
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given
+ */
+static enum status_code _rtc_count_set_config(
+		struct rtc_module *const module,
+		const struct rtc_count_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if SAML21 || SAMR30
+	rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0)
+#if (SAML21XXXB) || (SAMR30)
+				    | (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
+#endif
+				    | config->prescaler;
+#endif
+#if (SAMC20) || (SAMC21) || (SAML22)
+	rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | config->prescaler
+			| (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos);
+#endif
+
+	/* Set mode and clear on match if applicable. */
+	switch (config->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Set 32-bit mode and clear on match if applicable. */
+			rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(0);
+
+			/* Check if clear on compare match should be set. */
+			if (config->clear_on_match) {
+				/* Set clear on match. */
+				rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
+			}
+			/* Set compare values. */
+			for (uint8_t i = 0; i < RTC_COMP32_NUM; i++) {
+				rtc_count_set_compare(module, config->compare_values[i],
+						(enum rtc_count_compare)i);
+			}
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Set 16bit mode. */
+			rtc_module->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(1);
+
+			/* Check if match on clear is set, and return invalid
+			 * argument if set. */
+			if (config->clear_on_match) {
+				Assert(false);
+				return STATUS_ERR_INVALID_ARG;
+			}
+			/* Set compare values. */
+			for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+				rtc_count_set_compare(module, config->compare_values[i],
+						(enum rtc_count_compare)i);
+			}
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Return status OK if everything was configured. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ *
+ * Initializes the module, setting up all given configurations to provide
+ * the desired functionality of the RTC.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in]   hw      Pointer to hardware instance
+ * \param[in] config  Pointer to the configuration structure
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK               If the initialization was run stressfully
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given
+ */
+enum status_code rtc_count_init(
+		struct rtc_module *const module,
+		Rtc *const hw,
+		const struct rtc_count_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC);
+
+	/* Select RTC clock */
+	OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE;
+
+	/* Reset module to hardware defaults. */
+	rtc_count_reset(module);
+
+	/* Save conf_struct internally for continued use. */
+	module->mode                = config->mode;
+
+#  if (RTC_INST_NUM == 1)
+	_rtc_instance[0] = module;
+#  else
+	/* Register this instance for callbacks*/
+	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+#  endif
+
+	/* Set config and return status. */
+	return _rtc_count_set_config(module, config);
+}
+
+/**
+ * \brief Set the current count value to desired value.
+ *
+ * Sets the value of the counter to the specified value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] count_value  The value to be set in count register
+ *
+ * \return Status of setting the register.
+ * \retval STATUS_OK               If everything was executed correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_count_set_count(
+		struct rtc_module *const module,
+		const uint32_t count_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set count according to mode */
+	switch(module->mode){
+		case RTC_COUNT_MODE_32BIT:
+			/* Write value to register. */
+			rtc_module->MODE0.COUNT.reg = count_value;
+			break;
+		case RTC_COUNT_MODE_16BIT:
+			/* Check if 16-bit value is provided. */
+			if(count_value > 0xffff){
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Write value to register. */
+			rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current count value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ *
+ * Returns the current count value.
+ *
+ * \return The current counter value as a 32-bit unsigned integer.
+ */
+uint32_t rtc_count_get_count(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Initialize return value. */
+	uint32_t ret_val;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Read value based on mode. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Return count value in 32-bit mode. */
+			ret_val = rtc_module->MODE0.COUNT.reg;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Return count value in 16-bit mode. */
+			ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
+
+			break;
+
+		default:
+			Assert(false);
+			/* Counter not initialized. Assume counter value 0.*/
+			ret_val = 0;
+			break;
+	}
+
+	return ret_val;
+}
+
+/**
+ * \brief Set the compare value for the specified compare.
+ *
+ * Sets the value specified by the implementer to the requested compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_value  The value to be written to the compare
+ * \param[in] comp_index  Index of the compare to set
+ *
+ * \return Status indicating if compare was successfully set.
+ * \retval STATUS_OK               If compare was successfully set
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_set_compare(
+		struct rtc_module *const module,
+		const uint32_t comp_value,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set compare values based on operation mode. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_COMP32_NUM) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Set compare value for COMP. */
+			rtc_module->MODE0.COMP[comp_index].reg = comp_value;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Check that 16-bit value is provided. */
+			if (comp_value > 0xffff) {
+				Assert(false);
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Set compare value for COMP. */
+			rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Return status if everything is OK. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current compare value of specified compare.
+ *
+ * Retrieves the current value of the specified compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[out] comp_value  Pointer to 32-bit integer that will be populated with
+ *                         the current compare value
+ * \param[in]  comp_index  Index of compare to check
+ *
+ * \return Status of the reading procedure.
+ * \retval STATUS_OK               If the value was read correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_get_compare(
+		struct rtc_module *const module,
+		uint32_t *const comp_value,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_COMP32_NUM) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Get compare value for COMP. */
+			*comp_value = rtc_module->MODE0.COMP[comp_index].reg;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Get compare value for COMP. */
+			*comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+	/* Return status showing everything is OK. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the value of period.
+ *
+ * Retrieves the value of the period for the 16-bit mode counter.
+ *
+ * \note Only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[out] period_value  Pointer to value for return argument
+ *
+ * \return Status of getting the period value.
+ * \retval STATUS_OK                   If the period value was read correctly
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If incorrect mode was set
+ */
+enum status_code rtc_count_get_period(
+		struct rtc_module *const module,
+		uint16_t *const period_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Check that correct mode is set. */
+	if (module->mode != RTC_COUNT_MODE_16BIT) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Returns the value. */
+	*period_value = rtc_module->MODE1.PER.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Set the given value to the period.
+ *
+ * Sets the given value to the period.
+ *
+ * \note Only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] period_value  The value to set to the period
+ *
+ * \return Status of setting the period value.
+ * \retval STATUS_OK                   If the period was set correctly
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If module is not operated in 16-bit mode
+ */
+enum status_code rtc_count_set_period(
+		struct rtc_module *const module,
+		const uint16_t period_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check that correct mode is set. */
+	if (module->mode != RTC_COUNT_MODE_16BIT) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Write value to register. */
+	rtc_module->MODE1.PER.reg = period_value;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Check if RTC compare match has occurred.
+ *
+ * Checks the compare flag to see if a match has occurred. The compare flag is
+ * set when there is a compare match between counter and the compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_index  Index of compare to check current flag
+ */
+bool rtc_count_is_compare_match(
+		struct rtc_module *const module,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check sanity. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (comp_index > RTC_COMP32_NUM) {
+				return false;
+			}
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (comp_index > RTC_NUM_OF_COMP16) {
+				return false;
+			}
+
+			break;
+
+		default:
+			Assert(false);
+			return false;
+	}
+
+	/* Set status of INTFLAG as return argument. */
+	return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP(1 << comp_index)) ? true : false;
+}
+
+/**
+ * \brief Clears RTC compare match flag.
+ *
+ * Clears the compare flag. The compare flag is set when there is a compare
+ * match between the counter and the compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_index  Index of compare to check current flag
+ *
+ * \return Status indicating if flag was successfully cleared.
+ * \retval STATUS_OK               If flag was successfully cleared
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_clear_compare_match(
+		struct rtc_module *const module,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check sanity. */
+	switch (module->mode){
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (comp_index > RTC_COMP32_NUM) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+
+	/* Clear INTFLAG. */
+	rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Calibrate for too-slow or too-fast oscillator.
+ *
+ * When used, the RTC will compensate for an inaccurate oscillator. The
+ * RTC module will add or subtract cycles from the RTC prescaler to adjust the
+ * frequency in approximately 1 PPM steps. The provided correction value should
+ * be between 0 and 127, allowing for a maximum 127 PPM correction.
+ *
+ * If no correction is needed, set value to zero.
+ *
+ * \note Can only be used when the RTC is operated in 1Hz.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] value  Ranging from -127 to 127 used for the correction
+ *
+ * \return Status of the calibration procedure.
+ * \retval STATUS_OK               If calibration was executed correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_count_frequency_correction(
+		struct rtc_module *const module,
+		const int8_t value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check if valid argument. */
+	if (abs(value) > 0x7F) {
+		/* Value bigger than allowed, return invalid argument. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	uint32_t new_correction_value;
+
+	/* Load the new correction value as a positive value, sign added later */
+	new_correction_value = abs(value);
+
+	/* Convert to positive value and adjust register sign bit. */
+	if (value < 0) {
+		new_correction_value |= RTC_FREQCORR_SIGN;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set value. */
+	rtc_module->MODE0.FREQCORR.reg = new_correction_value;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	return STATUS_OK;
+}
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+/**
+ * \brief Applies the given configuration.
+ *
+ * Sets the configurations given from the configuration structure to the
+ * RTC tamper and it should be called before RTC module enable. 
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in] config  Pointer to the configuration structure
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               RTC configurations was set successfully
+ * \note If tamper input configured as active layer protection, RTC prescaler
+ *       output automatically enabled in the function.
+ */
+enum status_code rtc_tamper_set_config ( 
+		struct rtc_module *const module,
+		struct rtc_tamper_config *const tamper_cfg)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(tamper_cfg);
+
+	Rtc *const rtc_module = module->hw;
+	uint16_t ctrl_b = 0;
+
+	/* Configure enable backup and GP register reset on tamper or not. */
+	if(tamper_cfg->bkup_reset_on_tamper) {
+		rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+	} else {
+		rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+	}
+	
+	if (tamper_cfg->gp_reset_on_tamper) {
+		rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+	} else {
+		rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+	}
+
+	/* Configure tamper detection of frequency and debounce setting. */
+	ctrl_b = tamper_cfg->actl_freq_div | tamper_cfg->deb_freq_div;
+	if(tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_ASYNC) {
+		ctrl_b |= RTC_MODE0_CTRLB_DEBASYNC;
+	} else if (tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_MAJORITY) {
+		ctrl_b |= RTC_MODE0_CTRLB_DEBMAJ;
+	}
+	if(tamper_cfg->dma_tamper_enable) {
+		ctrl_b |= RTC_MODE0_CTRLB_DMAEN;
+	}
+	if (tamper_cfg->gp0_enable) {
+		ctrl_b |= RTC_MODE0_CTRLB_GP0EN;
+	}
+
+	/* Configure tamper input. */
+	volatile RTC_TAMPCTRL_Type *tamper_ctrl = &(rtc_module->MODE0.TAMPCTRL);
+
+	struct rtc_tamper_input_config in_cfg;
+	for (uint8_t tamper_id = 0; tamper_id < RTC_TAMPER_NUM; tamper_id++) {
+		in_cfg = tamper_cfg->in_cfg[tamper_id];
+
+		if(in_cfg.action == RTC_TAMPER_INPUT_ACTION_ACTL) {
+			ctrl_b |= RTC_MODE0_CTRLB_RTCOUT;
+		}
+	
+		switch(tamper_id) {
+			case 0:
+				tamper_ctrl->bit.IN0ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL0 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC0 = in_cfg.debounce_enable;
+				break;
+			case 1:
+				tamper_ctrl->bit.IN1ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL1 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC1 = in_cfg.debounce_enable;
+				break;
+			case 2:
+				tamper_ctrl->bit.IN2ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL2 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC2 = in_cfg.debounce_enable;
+				break;
+			case 3:
+				tamper_ctrl->bit.IN3ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL3 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC3 = in_cfg.debounce_enable;
+				break;
+			case 4:
+				tamper_ctrl->bit.IN4ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL4 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC4 = in_cfg.debounce_enable;
+				break;
+			default:
+				Assert(false);
+				break;
+		}
+	}
+
+	rtc_module->MODE0.CTRLB.reg = ctrl_b;
+
+	/* Return status OK if everything was configured. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the tamper stamp value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ *
+ * \return The current tamper stamp value as a 32-bit unsigned integer.
+ */
+uint32_t rtc_tamper_get_stamp (struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Initialize return value. */
+	uint32_t tamper_stamp = 0;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Read value based on mode. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Return stamp value in 32-bit mode. */
+			tamper_stamp = rtc_module->MODE0.TIMESTAMP.reg;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Return stamp value in 16-bit mode. */
+			tamper_stamp = (uint32_t)rtc_module->MODE1.TIMESTAMP.reg;
+
+			break;
+
+		default:
+			Assert(false);
+			break;
+	}
+
+	return tamper_stamp;
+}
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count_interrupt.c
new file mode 100644
index 0000000000..2c8c95c042
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count_interrupt.c
@@ -0,0 +1,365 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Interrupt Mode)
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "rtc_count_interrupt.h"
+
+extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
+
+/**
+ * \brief Registers callback for the specified callback type.
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ * To enable the callback, the \ref rtc_count_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]  callback      Pointer to the function desired for the specified
+ *                           callback
+ * \param[in]  callback_type Callback type to register
+ *
+ * \return                        Status of registering callback.
+ * \retval STATUS_OK              Registering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to register a callback not available
+ */
+enum status_code rtc_count_register_callback(
+		struct rtc_module *const module,
+		rtc_count_callback_t callback,
+		enum rtc_count_callback callback_type)
+{
+
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+		|| callback_type == RTC_COUNT_CALLBACK_TAMPER
+#endif
+		|| (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7)) {
+		status = STATUS_OK;
+	} else {
+		/* Make sure callback type can be registered */
+		switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (callback_type > (RTC_COMP32_NUM + RTC_PER_NUM)) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (callback_type > (RTC_NUM_OF_COMP16 + RTC_PER_NUM)) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		default:
+			status = STATUS_ERR_INVALID_ARG;
+		}
+	}
+
+	if (status == STATUS_OK) {
+		/* Register callback */
+		module->callbacks[callback_type] = callback;
+		/* Set corresponding bit to set callback as registered */
+		module->registered_callback |= (1 << callback_type);
+	}
+
+	return status;
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type.
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ *
+ * \return                        Status of unregistering callback.
+ * \retval STATUS_OK              Unregistering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to unregister a callback not available
+ */
+enum status_code rtc_count_unregister_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+		|| callback_type == RTC_COUNT_CALLBACK_TAMPER
+#endif
+		|| (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7)) {
+		status = STATUS_OK;
+	} else {
+		/* Make sure callback type can be unregistered */
+		switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (callback_type > (RTC_COMP32_NUM + RTC_PER_NUM)) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (callback_type > (RTC_NUM_OF_COMP16 + RTC_PER_NUM)) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		default:
+			status = STATUS_ERR_INVALID_ARG;
+		}
+	}
+	if (status == STATUS_OK) {
+		/* Unregister callback */
+		module->callbacks[callback_type] = NULL;
+
+		/* Clear corresponding bit to set callback as unregistered */
+		module->registered_callback &= ~(1 << callback_type);
+	}
+	return status;
+}
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to enable
+ */
+void rtc_count_enable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (callback_type == RTC_COUNT_CALLBACK_TAMPER) {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_TAMPER;
+#endif
+	} else if (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7) {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_PER(1 << callback_type);
+	}else {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << (callback_type - RTC_PER_NUM));
+	}
+	/* Mark callback as enabled. */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to disable
+ */
+void rtc_count_disable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable interrupt */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (callback_type == RTC_COUNT_CALLBACK_TAMPER) {
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_TAMPER;
+#endif
+	} else if(callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7){
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_PER(1 << callback_type);;
+	}else {
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << (callback_type - RTC_PER_NUM));
+	}
+
+	/* Mark callback as disabled. */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal Interrupt handler for RTC
+ *
+ * \param [in] instance_index  Default value 0
+ */
+static void _rtc_interrupt_handler(const uint32_t instance_index)
+{
+	struct rtc_module *module = _rtc_instance[instance_index];
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Combine callback registered and enabled masks */
+	uint16_t callback_mask = module->enabled_callback;
+	callback_mask &= module->registered_callback;
+
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
+	interrupt_status &= rtc_module->MODE0.INTENSET.reg;
+
+	if (interrupt_status & RTC_MODE0_INTFLAG_OVF) {
+		/* Overflow interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW)) {
+			module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
+		}
+
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (interrupt_status & RTC_MODE0_INTFLAG_TAMPER) {
+		/* Tamper interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_TAMPER)) {
+			module->callbacks[RTC_COUNT_CALLBACK_TAMPER]();
+		}
+
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_PER(0xff)) {
+		uint8_t i  = 0;
+		for ( i = 0;i < RTC_PER_NUM;i++) {
+			if ((interrupt_status & RTC_MODE1_INTFLAG_PER(1 << i))
+			  && (callback_mask & (1 << i))) {
+				module->callbacks[i]();
+			}
+
+			/* Clear interrupt flag */
+			rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_PER(1<<i);
+		}
+	}else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0)) {
+		/* Compare 0 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1)) {
+		#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+		/* Compare 1 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2)) {
+		#if (RTC_NUM_OF_COMP16 > 2)	|| defined(__DOXYGEN__)
+		/* Compare 2 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3)) {
+		#if (RTC_NUM_OF_COMP16 > 3)	|| defined(__DOXYGEN__)
+		/* Compare 3 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4)) {
+		#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+		/* Compare 4 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5)) {
+		#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+		/* Compare 5 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
+		#endif
+	}
+}
+
+/**
+ * \internal ISR handler for RTC
+ */
+#if (RTC_INST_NUM == 1)
+void RTC_Handler(void)
+{
+	_rtc_interrupt_handler(0);
+}
+#elif (RTC_INST_NUM > 1)
+#  define _RTC_INTERRUPT_HANDLER(n, unused) \
+		void RTC##n##_Handler(void) \
+		{ \
+			_rtc_interrupt_handler(n); \
+		}
+
+MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
+#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_tamper.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_tamper.h
new file mode 100644
index 0000000000..57b1dd2bc4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_tamper.h
@@ -0,0 +1,378 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Tamper)
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef RTC_TAMPER_H_INCLUDED
+#define RTC_TAMPER_H_INCLUDED
+
+/**
+ *
+ * \section asfdoc_sam0_rtc_tamper_detect RTC Tamper Detect
+ * The RTC provides several selectable polarity external inputs (INn) that can be
+ * used for tamper detection. When detect, tamper inputs support the four actions:
+ *   - Off
+ *   - Wake
+ *   - Capture
+ *   - Active layer protection
+ *
+ * \note The Active Layer Protection is a means of detecting broken traces on the
+ * PCB provided by RTC. In this mode an RTC output signal is routed over critical
+ * components on the board and fed back to one of the RTC inputs. The input and
+ * output signals are compared and a tamper condition is detected when they do not match.
+ *
+ *
+ * Separate debouncers are embedded for each external input. The detection time 
+ * depends on whether the debouncer operates synchronously or asynchronously, 
+ * and whether majority detection is enabled or not. For details, refer to the section
+ * "Tamper Detection" of datasheet.
+ * \if RTC_COUNT_CALLBACK_MODE
+ *  \addtogroup asfdoc_sam0_rtc_count_group
+ * \else
+ * \if RTC_CALENDAR_CALLBACK_MODE
+ *  \addtogroup asfdoc_sam0_rtc_calendar_group
+ * \endif
+ * \endif
+ * @{
+ */
+
+#if defined(FEATURE_RTC_TAMPER_DETECTION) || defined(__DOXYGEN__)
+
+/** RTC tamper ID0 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID0    (1UL << 0)
+/** RTC tamper ID1 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID1    (1UL << 1)
+/** RTC tamper ID2 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID2    (1UL << 2)
+/** RTC tamper ID3 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID3    (1UL << 3)
+/** RTC tamper ID4 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID4    (1UL << 4)
+/** RTC tamper input event detection bitmask. */
+#define RTC_TAMPER_DETECT_EVT    (1UL << 5)
+
+
+
+/**
+ * \brief RTC tamper active layer frequency divider.
+ *
+ * The available prescaler factor for the RTC clock output used during active
+ * layer protection.
+ */
+enum rtc_tamper_active_layer_freq_divider {
+	/** RTC active layer frequency is prescaled by a factor of 2 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_2    = RTC_MODE0_CTRLB_ACTF_DIV2,
+	/** RTC active layer frequency is prescaled by a factor of 4 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_4    = RTC_MODE0_CTRLB_ACTF_DIV4,
+	/** RTC active layer frequency is prescaled by a factor of 8 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_8    = RTC_MODE0_CTRLB_ACTF_DIV8,
+	/** RTC active layer frequency is prescaled by a factor of 16 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_16   = RTC_MODE0_CTRLB_ACTF_DIV16,
+	/** RTC active layer frequency is prescaled by a factor of 32 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_32   = RTC_MODE0_CTRLB_ACTF_DIV32,
+	/** RTC active layer frequency is prescaled by a factor of 64 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_64   = RTC_MODE0_CTRLB_ACTF_DIV64,
+	/** RTC active layer frequency is prescaled by a factor of 128 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_128  = RTC_MODE0_CTRLB_ACTF_DIV128,
+	/** RTC active layer frequency is prescaled by a factor of 256 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_256  = RTC_MODE0_CTRLB_ACTF_DIV256,
+};
+
+/**
+ * \brief RTC tamper debounce frequency divider.
+ *
+ * The available prescaler factor for the input debouncers.
+ */
+enum rtc_tamper_debounce_freq_divider {
+	/** RTC debounce frequency is prescaled by a factor of 2 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_2    = RTC_MODE0_CTRLB_DEBF_DIV2,
+	/** RTC debounce frequency is prescaled by a factor of 4 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_4    = RTC_MODE0_CTRLB_DEBF_DIV4,
+	/** RTC debounce frequency is prescaled by a factor of 8 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_8    = RTC_MODE0_CTRLB_DEBF_DIV8,
+	/** RTC debounce frequency is prescaled by a factor of 16 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_16   = RTC_MODE0_CTRLB_DEBF_DIV16,
+	/** RTC debounce frequency is prescaled by a factor of 32 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_32   = RTC_MODE0_CTRLB_DEBF_DIV32,
+	/** RTC debounce frequency is prescaled by a factor of 64 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_64   = RTC_MODE0_CTRLB_DEBF_DIV64,
+	/** RTC debounce frequency is prescaled by a factor of 128 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_128  = RTC_MODE0_CTRLB_DEBF_DIV128,
+	/** RTC debounce frequency is prescaled by a factor of 256 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_256  = RTC_MODE0_CTRLB_DEBF_DIV256,
+};
+
+/**
+ * \brief RTC tamper input action.
+ *
+ * The available action taken by the tamper input.
+ */
+enum rtc_tamper_input_action {
+	/** RTC tamper input action is disabled */
+	RTC_TAMPER_INPUT_ACTION_OFF     = RTC_TAMPCTRL_IN0ACT_OFF,
+	/** RTC tamper input action is wake and set tamper flag */
+	RTC_TAMPER_INPUT_ACTION_WAKE    = RTC_TAMPCTRL_IN0ACT_WAKE,
+	/** RTC tamper input action is capture timestamp and set tamper flag */
+	RTC_TAMPER_INPUT_ACTION_CAPTURE = RTC_TAMPCTRL_IN0ACT_CAPTURE,
+	/** RTC tamper input action is compare IN to OUT, when a mismatch occurs,
+	 *  capture timestamp and set tamper flag */
+	RTC_TAMPER_INPUT_ACTION_ACTL    = RTC_TAMPCTRL_IN0ACT_ACTL,
+};
+
+/**
+ * \brief RTC tamper input level select.
+ *
+ * The available edge condition for tamper INn level select.
+ */
+enum rtc_tamper_level_sel {
+	/** A falling edge condition will be detected on Tamper input */
+	RTC_TAMPER_LEVEL_FALLING = (0),
+	/** A rising edge condition will be detected on Tamper input */
+	RTC_TAMPER_LEVEL_RISING  = (1),
+};
+
+/**
+ * \brief RTC tamper debounce sequential.
+ *
+ * The available sequential for tamper debounce.
+ */
+enum rtc_tamper_debounce_seq {
+	/** Tamper input detect edge with synchronous stability debounce */
+	RTC_TAMPER_DEBOUNCE_SYNC,
+	/** Tamper input detect edge with asynchronous stability debounce */
+	RTC_TAMPER_DEBOUNCE_ASYNC,
+	/** Tamper input detect edge with majority debounce */
+	RTC_TAMPER_DEBOUNCE_MAJORITY,
+};
+
+/**
+ * \brief RTC tamper input configuration structure.
+ *
+ * The configuration structure for tamper INn.
+ */
+struct rtc_tamper_input_config {
+	/** Debounce enable */
+	bool debounce_enable;
+	/** Tamper level select */
+	enum rtc_tamper_level_sel level;
+	/** Tamper input action */
+	enum rtc_tamper_input_action action;
+};
+
+/**
+ * \brief RTC Tamper configuration structure.
+ *
+ * The configuration structure for the RTC tamper. This structure should
+ * be initialized using the \ref rtc_tamper_get_config_defaults() before any
+ * user configurations are set.
+ */
+struct rtc_tamper_config {
+	/** Backup register reset on tamper enable */
+	bool bkup_reset_on_tamper;
+	/** GP register reset on tamper enable */
+	bool gp_reset_on_tamper;
+	/** Active layer frequency */
+	enum rtc_tamper_active_layer_freq_divider actl_freq_div;
+	/** Debounce frequency */
+	enum rtc_tamper_debounce_freq_divider deb_freq_div;
+	/** Debounce sequential */
+	enum rtc_tamper_debounce_seq deb_seq;
+	/** DMA on tamper enable */
+	bool dma_tamper_enable;
+	/** General Purpose 0/1 Enable */
+	bool gp0_enable;
+	/** Tamper IN configuration */
+	struct rtc_tamper_input_config in_cfg[RTC_TAMPER_NUM];
+};
+
+/**
+ * \name RTC Tamper Detection
+ * @{
+ */
+
+/**
+ *  \brief Gets the RTC tamper default configurations.
+ *
+ *  Initializes the configuration structure to default values. 
+ *
+ *  The default configuration is as follows:
+ *  - Disable backup register reset on tamper
+ *  - Disable GP register reset on tamper
+ *  - Active layer clock divided by a factor of 8
+ *  - Debounce clock divided by a factor of 8
+ *  - Detect edge on INn with synchronous stability debouncing
+ *  - Disable DMA on  tamper
+ *  - Enable GP register
+ *  - Disable debouce, detect on falling edge and no action on INn
+ *
+ *  \param[out] config Configuration structure to be initialized to default values.
+ */
+static inline void rtc_tamper_get_config_defaults(
+		struct rtc_tamper_config *const config)
+{
+	/* Sanity check argument */
+	Assert(config);
+
+	config->bkup_reset_on_tamper= false;
+	config->gp_reset_on_tamper  = false;
+	config->actl_freq_div       = RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_8;
+	config->deb_freq_div        = RTC_TAMPER_DEBOUNCE_FREQ_DIV_8;
+	config->deb_seq             = RTC_TAMPER_DEBOUNCE_SYNC;
+	config->dma_tamper_enable   = false;
+	config->gp0_enable          = true;
+
+	for (uint8_t id = 0; id < RTC_TAMPER_NUM; id++) {
+		config->in_cfg[id].debounce_enable = false;
+		config->in_cfg[id].level = RTC_TAMPER_LEVEL_FALLING;
+		config->in_cfg[id].action = RTC_TAMPER_INPUT_ACTION_OFF;
+	}
+}
+enum status_code rtc_tamper_set_config (struct rtc_module *const module,
+		struct rtc_tamper_config *const tamper_cfg);
+
+/**
+ * \brief Retrieves the RTC tamper detection status.
+ *
+ * Retrieves the detection status of each input pin and the input event.
+ *
+ * \param[in] module  Pointer to the RTC software instance struct
+ *
+ * \return Bitmask of detection flags.
+ *
+ * \retval RTC_TAMPER_DETECT_ID0   Tamper condition on IN0 has been detected
+ * \retval RTC_TAMPER_DETECT_ID1   Tamper condition on IN1 has been detected
+ * \retval RTC_TAMPER_DETECT_ID2   Tamper condition on IN2 has been detected
+ * \retval RTC_TAMPER_DETECT_ID3   Tamper condition on IN3 has been detected
+ * \retval RTC_TAMPER_DETECT_ID4   Tamper condition on IN4 has been detected
+ * \retval RTC_TAMPER_DETECT_EVT   Tamper input event has been detected
+ */
+static inline uint32_t rtc_tamper_get_detect_flag (struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	uint32_t tamper_id = module->hw->MODE0.TAMPID.reg;
+	uint32_t detect_flags = 0;
+
+	if (tamper_id & RTC_TAMPID_TAMPID0) {
+		detect_flags |= RTC_TAMPER_DETECT_ID0;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPID1) {
+		detect_flags |= RTC_TAMPER_DETECT_ID1;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPID2) {
+		detect_flags |= RTC_TAMPER_DETECT_ID2;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPID3) {
+		detect_flags |= RTC_TAMPER_DETECT_ID3;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPID4) {
+		detect_flags |= RTC_TAMPER_DETECT_ID4;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPEVT) {
+		detect_flags |= RTC_TAMPER_DETECT_EVT;
+	}
+
+	return detect_flags;
+}
+
+/**
+ * \brief Clears RTC tamper detection flag.
+ *
+ * Clears the given detection flag of the module.
+ *
+ * \param[in] module   Pointer to the TC software instance struct
+ * \param[in] detect_flags  Bitmask of detection flags
+ */
+static inline void rtc_tamper_clear_detect_flag(
+		struct rtc_module *const module,
+		const uint32_t detect_flags)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	uint32_t tamper_id = 0;
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID0) {
+		tamper_id |= RTC_TAMPID_TAMPID0;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID1) {
+		tamper_id |= RTC_TAMPID_TAMPID1;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID2) {
+		tamper_id |= RTC_TAMPID_TAMPID2;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID3) {
+		tamper_id |= RTC_TAMPID_TAMPID3;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID4) {
+		tamper_id |= RTC_TAMPID_TAMPID4;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_EVT) {
+		tamper_id |= RTC_TAMPID_TAMPEVT;
+	}
+
+	module->hw->MODE0.TAMPID.reg = tamper_id;
+
+}
+
+/** @} */
+
+#endif
+/** @} */
+
+
+#endif /* RTC_TAMPER_H_INCLUDED */
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.c
new file mode 100644
index 0000000000..ef868a51a6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.c
@@ -0,0 +1,311 @@
+/**
+ * \file
+ *
+ * \brief SAM Sigma-Delta Analog-to-Digital Converter (SDADC) Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "sdadc.h"
+
+/**
+* \internal Configure MUX settings for the analog pins
+*
+* This function will set the given SDADC input pins
+* to the analog function in the pinmux, giving
+* the SDADC access to the analog signal
+*
+* \param [in] pin AINxx pin to configure
+*/
+static inline void _sdadc_configure_ain_pin(uint32_t pin)
+{
+	/* Pinmapping table for AINxx -> GPIO pin number */
+	const uint32_t pinmapping[] = {
+#if (SAMC21E)
+			PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
+#elif (SAMC21G)
+			PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
+			PIN_PB08B_SDADC_INN1, PIN_PB09B_SDADC_INP1,
+#elif (SAMC21J)
+			PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
+			PIN_PB08B_SDADC_INN1, PIN_PB09B_SDADC_INP1,
+			PIN_PB06B_SDADC_INN2, PIN_PB07B_SDADC_INP2,
+#else
+#  error SDADC pin mappings are not defined for this device.
+#endif
+	};
+
+	uint32_t pin_map_result;
+
+	struct system_pinmux_config config;
+	system_pinmux_get_config_defaults(&config);
+
+	config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+	config.mux_position = 1;
+
+	pin_map_result = pinmapping[pin * 2];
+	system_pinmux_pin_set_config(pin_map_result, &config);
+
+	pin_map_result = pinmapping[pin * 2 + 1];
+	system_pinmux_pin_set_config(pin_map_result, &config);
+}
+
+/**
+ * \internal Writes an SDADC configuration to the hardware module
+ *
+ * Writes out a given SDADC module configuration to the hardware module.
+ *
+ * \param[out] module_inst  Pointer to the SDADC software instance struct
+ * \param[in]  config       Pointer to configuration struct
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               The configuration was successful
+ * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
+ */
+static enum status_code _sdadc_set_config(
+		struct sdadc_module *const module_inst,
+		struct sdadc_config *const config)
+{
+	/* Get the hardware module pointer */
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(SDADC_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(SDADC_GCLK_ID);
+
+	/* Setup pinmuxing for analog inputs */
+	_sdadc_configure_ain_pin(config->mux_input);
+
+	/* Configure run in standby */
+	sdadc_module->CTRLA.reg = (config->run_in_standby << SDADC_CTRLA_RUNSTDBY_Pos)
+			| (config->on_command << SDADC_CTRLA_ONDEMAND_Pos);
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure reference */
+	sdadc_module->REFCTRL.reg = (config->reference.ref_sel) | (config->reference.ref_range) |
+						(config->reference.on_ref_buffer << SDADC_REFCTRL_ONREFBUF_Pos);
+
+	/* Configure CTRLB */
+	sdadc_module->CTRLB.reg =
+			(config->skip_count << SDADC_CTRLB_SKPCNT_Pos) |
+			(config->clock_prescaler / 2 - 1) | config->osr;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure CTRLC */
+	sdadc_module->CTRLC.reg =
+			(config->freerunning << SDADC_CTRLC_FREERUN_Pos);
+
+	/* Configure SEQCTRL */
+	sdadc_module->SEQCTRL.reg =
+			(config->seq_enable[0]) | (config->seq_enable[1] << 1) | (config->seq_enable[2] << 2);
+
+	/* Check validity of window thresholds */
+	if (config->window.window_mode != SDADC_WINDOW_MODE_DISABLE) {
+		if (config->window.window_lower_value > (int32_t)(SDADC_RESULT_RESULT_Msk / 2) ||
+			config->window.window_lower_value < -(int32_t)(SDADC_RESULT_RESULT_Msk / 2 + 1) ||
+			config->window.window_upper_value > (int32_t)(SDADC_RESULT_RESULT_Msk / 2) ||
+			config->window.window_upper_value < -(int32_t)(SDADC_RESULT_RESULT_Msk / 2 + 1)) {
+			/* Invalid value */
+			return STATUS_ERR_INVALID_ARG;
+		} else if (config->window.window_lower_value > (int32_t)SDADC_RESULT_RESULT_Msk ||
+				config->window.window_upper_value > (int32_t)SDADC_RESULT_RESULT_Msk){
+			/* Invalid value */
+			return STATUS_ERR_INVALID_ARG;
+		}
+	}
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure window mode */
+	sdadc_module->WINCTRL.reg = config->window.window_mode;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	sdadc_module->WINLT.reg =
+			config->window.window_lower_value << SDADC_WINLT_WINLT_Pos;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	sdadc_module->WINUT.reg = config->window.window_upper_value <<
+			SDADC_WINUT_WINUT_Pos;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure pin scan mode and positive and negative input pins */
+	sdadc_module->INPUTCTRL.reg = config->mux_input;
+
+	/* Configure events */
+	sdadc_module->EVCTRL.reg = config->event_action;
+
+	/* Disable all interrupts */
+	sdadc_module->INTENCLR.reg = (1 << SDADC_INTENCLR_WINMON_Pos) |
+			(1 << SDADC_INTENCLR_OVERRUN_Pos) | (1 << SDADC_INTENCLR_RESRDY_Pos);
+
+	/* Make sure offset correction value is valid */
+	if (config->correction.offset_correction > (int32_t)(SDADC_OFFSETCORR_MASK / 2) ||
+		config->correction.offset_correction < - (int32_t)(SDADC_OFFSETCORR_MASK / 2 + 1)) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		while (sdadc_is_syncing(module_inst)) {
+			/* Wait for synchronization */
+		}
+
+		/* Set offset correction value */
+		sdadc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+				SDADC_OFFSETCORR_OFFSETCORR_Pos;
+	}
+
+	/* Make sure gain_correction value is valid */
+	if (config->correction.gain_correction > SDADC_GAINCORR_MASK) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		while (sdadc_is_syncing(module_inst)) {
+			/* Wait for synchronization */
+		}
+
+		/* Set gain correction value */
+		sdadc_module->GAINCORR.reg = config->correction.gain_correction <<
+				SDADC_GAINCORR_GAINCORR_Pos;
+	}
+
+	/* Make sure shift_correction value is valid */
+	if (config->correction.shift_correction > SDADC_SHIFTCORR_MASK) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		while (sdadc_is_syncing(module_inst)) {
+			/* Wait for synchronization */
+		}
+
+		/* Set shift correction value */
+		sdadc_module->SHIFTCORR.reg = config->correction.shift_correction <<
+				SDADC_SHIFTCORR_SHIFTCORR_Pos;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the SDADC.
+ *
+ * Initializes the SDADC device struct and the hardware module based on the
+ * given configuration struct values.
+ *
+ * \param[out] module_inst Pointer to the SDADC software instance struct
+ * \param[in]  hw          Pointer to the SDADC module instance
+ * \param[in]  config      Pointer to the configuration struct
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK                The initialization was successful
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) were provided
+ * \retval STATUS_BUSY          The module is busy with a reset operation
+ * \retval STATUS_ERR_DENIED        The module is enabled
+ */
+enum status_code sdadc_init(
+		struct sdadc_module *const module_inst,
+		Sdadc *hw,
+		struct sdadc_config *config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_SDADC);
+
+	if (hw->CTRLA.reg & SDADC_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	if (hw->CTRLA.reg & SDADC_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Store the selected reference for later use */
+	module_inst->reference = config->reference;
+
+#if SDADC_CALLBACK_MODE == true
+	for (uint8_t i = 0; i < SDADC_CALLBACK_N; i++) {
+		module_inst->callback[i] = NULL;
+	};
+
+	module_inst->registered_callback_mask = 0;
+	module_inst->enabled_callback_mask = 0;
+	module_inst->remaining_conversions = 0;
+	module_inst->job_status = STATUS_OK;
+
+	_sdadc_instances[0] = module_inst;
+
+	if (config->event_action == SDADC_EVENT_ACTION_DISABLED &&
+			!config->freerunning) {
+		module_inst->software_trigger = true;
+	} else {
+		module_inst->software_trigger = false;
+	}
+#endif
+
+	/* Write configuration to module */
+	return _sdadc_set_config(module_inst, config);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.h
new file mode 100644
index 0000000000..ad42c9a22e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.h
@@ -0,0 +1,1157 @@
+/**
+ * \file
+ *
+ * \brief SAM Sigma-Delta Analog-to-Digital Converter (SDADC) Driver
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SDADC_H_INCLUDED
+#define SDADC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_sdadc_group SAM Sigma-Delta Analog-to-Digital Converter (SDADC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's SDADC functionality.
+ *
+ * The following peripheral is used by this module:
+ *  - SDADC (Sigma-Delta Analog-to-Digital Converter)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_sdadc_prerequisites
+ *  - \ref asfdoc_sam0_sdadc_module_overview
+ *  - \ref asfdoc_sam0_sdadc_special_considerations
+ *  - \ref asfdoc_sam0_sdadc_extra_info
+ *  - \ref asfdoc_sam0_sdadc_examples
+ *  - \ref asfdoc_sam0_sdadc_api_overview
+ *
+ *
+ * \section asfdoc_sam0_sdadc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_sdadc_module_overview Module Overview
+ *
+ * The Sigma-Delta Analog-to-Digital Converter (SDADC) converts analog signals to
+ * digital values. The sigma-delta architecture of the SDADC implies a filtering
+ * and a decimation of the bitstream at the output of the SDADC. The input selection
+ * is up to three input analog channels.
+ *
+ * The SDADC provides up to 16-bit resolution at about 1000 samples per second (1KSPS)
+ * and sized 24 bits signed result to handle filtering and gain correction without overflow.
+ * The SDADC measurements can be started by either application software or an incoming
+ * event from another peripheral in the device.
+ *
+ * The conversion is performed on a full range between 0V and the reference voltage.
+ * Both internal and external reference voltages can be selected. The reference range
+ * must be set to match the voltage of the reference used. Analog inputs between
+ * these voltages convert to values based on a linear conversion.
+ *
+ *
+ * \subsection asfdoc_sam0_sdadc_module_overview_clock Sample Clock
+ * A generic clock (GCLK_SDADC) is required to generate the CLK_SDADC to the SDADC
+ * module. The SDADC features a prescaler, which enables conversion at lower clock
+ * rates than the input Generic Clock to the SDADC module.
+ *
+ * The SDADC data sampling frequency (CLK_SDADC_FS) in the SDADC module is the
+ * CLK_SDADC/4, the reduction comes from the phase generator between the prescaler
+ * and the SDADC.
+ *
+ * OSR is the Over Sampling Ratio, which can be modified to change the output data
+ * rate. The conversion time depends on the selected OSR and the sampling frequency
+ * of the SDADC.
+ * The conversion time can be described with:
+ * \f[
+ * t_{SAMPLE} = \frac {22 + 3 \times OSR} {CLK \_ SDADC \_ FS}
+ * \f]
+ * -# Initialization of the SDADC (22 sigma-delta samples).
+ * -# Filling of the decimation filter (3*OSR sigma-delta samples).
+ *
+ * \subsection asfdoc_sam0_sdadc_module_overview_offset_corr Gain and Offset Correction
+ * A specific offset, gain, and shift can be applied to each source of the SDADC
+ * by performing the following operation:
+ * \f[
+ * Data = (Data_{0} + OFFSET) \times \frac {GAIN}{2^{SHIFT}}
+ * \f]
+ *
+ *
+ * \subsection asfdoc_sam0_sdadc_module_overview_window_monitor Window Monitor
+ * The SDADC module window monitor function can be used to automatically compare
+ * the conversion result against a predefined pair of upper and lower
+ * threshold values.
+ *
+ *
+ * \subsection asfdoc_sam0_sdadc_module_overview_events Events
+ * Event generation and event actions are configurable in the SDADC.
+ *
+ * The SDADC has two actions that can be triggered upon event reception:
+ * \li Start conversion
+ * \li Conversion flush
+ *
+ * The SDADC can generate two kinds of events:
+ * \li Window monitor
+ * \li Result ready
+ *
+ * If the event actions are enabled in the configuration, any incoming event
+ * will trigger the action.
+ *
+ * If the window monitor event is enabled, an event will be generated
+ * when the configured window condition is detected.
+ *
+ * If the result ready event is enabled, an event will be generated when a
+ * conversion is completed.
+ *
+ *
+ * \section asfdoc_sam0_sdadc_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_sdadc_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_sdadc_extra. This includes:
+ *  - \ref asfdoc_sam0_sdadc_extra_acronyms
+ *  - \ref asfdoc_sam0_sdadc_extra_dependencies
+ *  - \ref asfdoc_sam0_sdadc_extra_errata
+ *  - \ref asfdoc_sam0_sdadc_extra_history
+ *
+ *
+ * \section asfdoc_sam0_sdadc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sdadc_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_sdadc_api_overview API Overview
+ * @{
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system.h>
+
+#if SDADC_CALLBACK_MODE == true
+#  include <system_interrupt.h>
+
+#if !defined(__DOXYGEN__)
+extern struct sdadc_module *_sdadc_instances[SDADC_INST_NUM];
+#endif
+
+/** Forward definition of the device instance. */
+struct sdadc_module;
+
+/** Type of the callback functions. */
+typedef void (*sdadc_callback_t)(const struct sdadc_module *const module);
+
+/**
+ * \brief SDADC Callback enum.
+ *
+ * Callback types for SDADC callback driver.
+ *
+ */
+enum sdadc_callback {
+	/** Callback for buffer received */
+	SDADC_CALLBACK_READ_BUFFER,
+	/** Callback when window is hit */
+	SDADC_CALLBACK_WINDOW,
+	/** Callback for error */
+	SDADC_CALLBACK_ERROR,
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	SDADC_CALLBACK_N,
+#  endif
+};
+
+#endif
+
+/**
+ * \name Module Status Flags
+ *
+ * SDADC status flags, returned by \ref sdadc_get_status() and cleared by
+ * \ref sdadc_clear_status().
+ *
+ * @{
+ */
+
+/** SDADC result ready. */
+#define SDADC_STATUS_RESULT_READY  (1UL << 0)
+/** SDADC result overwritten before read. */
+#define SDADC_STATUS_OVERRUN       (1UL << 1)
+/** Window monitor match. */
+#define SDADC_STATUS_WINDOW        (1UL << 2)
+
+/** @} */
+
+/**
+ * \brief SDADC reference voltage enum.
+ *
+ * Enum for the possible reference voltages for the SDADC.
+ *
+ */
+enum sdadc_reference_select {
+	/** Internal Bandgap Reference */
+	SDADC_REFERENCE_INTREF = SDADC_REFCTRL_REFSEL(0),
+	/** External reference B */
+	SDADC_REFERENCE_AREFB  = SDADC_REFCTRL_REFSEL(1),
+	/** DACOUT */
+	SDADC_REFERENCE_DACOUT = SDADC_REFCTRL_REFSEL(2),
+	/** VDDANA */
+	SDADC_REFERENCE_INTVCC = SDADC_REFCTRL_REFSEL(3),
+};
+
+/**
+ * \brief SDADC reference range enum.
+ *
+ * Enum for the matched voltage range of the SDADC reference used.
+ *
+ */
+enum sdadc_reference_range {
+	/** Vref < 1.4V */
+	SDADC_REFRANGE_0 = SDADC_REFCTRL_REFRANGE(0),
+	/** 1.4V < Vref < 2.4V */
+	SDADC_REFRANGE_1 = SDADC_REFCTRL_REFRANGE(1),
+	/** 2.4V < Vref < 3.6V */
+	SDADC_REFRANGE_2 = SDADC_REFCTRL_REFRANGE(2),
+	/** Vref > 3.6V */
+	SDADC_REFRANGE_3 = SDADC_REFCTRL_REFRANGE(3),
+};
+
+/**
+ * \brief SDADC over sampling ratio enum.
+ *
+ * Enum for the over sampling ratio, which change the output data rate.
+ *
+ */
+enum sdadc_over_sampling_ratio {
+	/** SDADC over Sampling Ratio is 64 */
+	SDADC_OVER_SAMPLING_RATIO64    = SDADC_CTRLB_OSR(0),
+	/** SDADC over Sampling Ratio is 128 */
+	SDADC_OVER_SAMPLING_RATIO128   = SDADC_CTRLB_OSR(1),
+	/** SDADC over Sampling Ratio is 256 */
+	SDADC_OVER_SAMPLING_RATIO256   = SDADC_CTRLB_OSR(2),
+	/** SDADC over Sampling Ratio is 512 */
+	SDADC_OVER_SAMPLING_RATIO512   = SDADC_CTRLB_OSR(3),
+	/** SDADC over Sampling Ratio is 1024 */
+	SDADC_OVER_SAMPLING_RATIO1024  = SDADC_CTRLB_OSR(4),
+};
+
+/**
+ * \brief SDADC window monitor mode enum.
+ *
+ * Enum for the possible window monitor modes for the SDADC.
+ *
+ */
+enum sdadc_window_mode {
+	/** No window mode */
+	SDADC_WINDOW_MODE_DISABLE          = SDADC_WINCTRL_WINMODE(0),
+	/** RESULT > WINLT */
+	SDADC_WINDOW_MODE_ABOVE            = SDADC_WINCTRL_WINMODE(1),
+	/** RESULT < WINUT */
+	SDADC_WINDOW_MODE_BELOW            = SDADC_WINCTRL_WINMODE(2),
+	/** WINLT < RESULT < WINUT */
+	SDADC_WINDOW_MODE_INSIDE           = SDADC_WINCTRL_WINMODE(3),
+	/** !(WINLT < RESULT < WINUT) */
+	SDADC_WINDOW_MODE_OUTSIDE          = SDADC_WINCTRL_WINMODE(4),
+};
+
+/**
+ * \brief SDADC event action enum.
+ *
+ * Enum for the possible actions to take on an incoming event.
+ *
+ */
+enum sdadc_event_action {
+	/** Event action disabled */
+	SDADC_EVENT_ACTION_DISABLED         = 0,
+	/** Flush SDADC and start conversion */
+	SDADC_EVENT_ACTION_FLUSH_START_CONV = SDADC_EVCTRL_FLUSHEI,
+	/** Start conversion */
+	SDADC_EVENT_ACTION_START_CONV       = SDADC_EVCTRL_STARTEI,
+};
+
+/**
+ * \brief SDADC MUX input selection enum.
+ *
+ * Enum for the possible MUX input selections for the SDADC.
+ *
+ */
+enum sdadc_mux_input {
+	/** Select SDADC AINN0 and AINP0 pins */
+	SDADC_MUX_INPUT_AIN0    = SDADC_INPUTCTRL_MUXSEL_AIN0,
+	/** Select SDADC AINN1 and AINP1 pins */
+	SDADC_MUX_INPUT_AIN1    = SDADC_INPUTCTRL_MUXSEL_AIN1,
+	/** Select SDADC AINN2 and AINP2 pins */
+	SDADC_MUX_INPUT_AIN2    = SDADC_INPUTCTRL_MUXSEL_AIN2,
+};
+
+#if SDADC_CALLBACK_MODE == true
+/**
+ * Enum for the possible SDADC interrupt flags.
+ */
+enum sdadc_interrupt_flag {
+	/** SDADC result ready */
+	SDADC_INTERRUPT_RESULT_READY = SDADC_INTFLAG_RESRDY,
+	/** SDADC result overwritten before read */
+	SDADC_INTERRUPT_OVERRUN      = SDADC_INTFLAG_OVERRUN,
+	/** Window monitor match */
+	SDADC_INTERRUPT_WINDOW       = SDADC_INTFLAG_WINMON,
+};
+#endif
+
+/**
+ * \brief Reference configuration structure.
+ *
+ * Reference configuration structure.
+ */
+struct sdadc_reference {
+	/** Reference voltage selection */
+	enum sdadc_reference_select ref_sel;
+	/** Reference voltage range */
+	enum sdadc_reference_select ref_range;
+	/** Reference buffer turning switch */
+	bool on_ref_buffer;
+};
+
+/**
+ * \brief Window monitor configuration structure.
+ *
+ * Window monitor configuration structure.
+ */
+struct sdadc_window_config {
+	/** Selected window mode */
+	enum sdadc_window_mode window_mode;
+	/** Lower window value */
+	int32_t window_lower_value;
+	/** Upper window value */
+	int32_t window_upper_value;
+};
+
+/**
+ * \brief SDADC event enable/disable structure.
+ *
+ * Event flags for the SDADC module. This is used to enable and
+ * disable events via \ref sdadc_enable_events() and \ref sdadc_disable_events().
+ */
+struct sdadc_events {
+	/** Enable event generation on conversion done */
+	bool generate_event_on_conversion_done;
+	/** Enable event generation on window monitor */
+	bool generate_event_on_window_monitor;
+};
+
+/**
+ * \brief SDADC correction configuration structure.
+ *
+ * Offset, gain, and shift correction configuration structure.
+ * Part of the \ref sdadc_config struct will be initialized by
+ * \ref sdadc_get_config_defaults.
+ */
+struct sdadc_correction_config {
+	/** Offset correction */
+	int32_t offset_correction;
+	/** Gain correction */
+	uint16_t gain_correction;
+	/** Shift correction */
+	uint8_t shift_correction;
+};
+
+/**
+ * \brief SDADC configuration structure.
+ *
+ * Configuration structure for an SDADC instance. This structure should be
+ * initialized by the \ref sdadc_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct sdadc_config {
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+	/** Voltage reference */
+	struct sdadc_reference reference;
+	/** Over sampling ratio */
+	enum sdadc_over_sampling_ratio osr;
+	/** Clock prescaler */
+	uint8_t clock_prescaler;
+	/** Skip Count */
+	uint8_t skip_count;
+	/** MUX input */
+	enum sdadc_mux_input mux_input;
+	/** Enables free running mode if true */
+	bool freerunning;
+	/** Enables SDADC in standby sleep mode if true */
+	bool run_in_standby;
+	/** Enables SDADC depend on other peripheral if true */
+	bool on_command;
+	/** Enables positive input in the sequence if true */
+	bool seq_enable[3];
+	/** Window monitor configuration structure */
+	struct sdadc_window_config window;
+	/** Gain and offset correction configuration structure */
+	struct sdadc_correction_config correction;
+	/** Event action to take on incoming event */
+	enum sdadc_event_action event_action;
+};
+
+/**
+ * \brief SDADC software device instance structure.
+ *
+ * SDADC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct sdadc_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to SDADC hardware module */
+	Sdadc *hw;
+	/** Keep reference configuration so we know when enable is called */
+	struct sdadc_reference reference;
+#  if SDADC_CALLBACK_MODE == true
+	/** Array to store callback functions */
+	sdadc_callback_t callback[SDADC_CALLBACK_N];
+	/** Pointer to buffer used for SDADC results */
+	volatile int32_t *job_buffer;
+	/** Remaining number of conversions in current job */
+	volatile uint16_t remaining_conversions;
+	/** Bit mask for callbacks registered */
+	uint8_t registered_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t enabled_callback_mask;
+	/** Holds the status of the ongoing or last conversion job */
+	volatile enum status_code job_status;
+	/** If software triggering is needed */
+	bool software_trigger;
+#  endif
+#endif
+};
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+enum status_code sdadc_init(
+		struct sdadc_module *const module_inst,
+		Sdadc *hw,
+		struct sdadc_config *config);
+
+/**
+ * \brief Initializes an SDADC configuration structure to defaults.
+ *
+ * Initializes a given SDADC configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li GCLK generator 0 (GCLK main) clock source
+ *  \li Positive reference 1
+ *  \li Div 2 clock prescaler
+ *  \li Over Sampling Ratio is 64
+ *  \li Skip 0 samples
+ *  \li MUX input on SDADC AIN1
+ *  \li All events (input and generation) disabled
+ *  \li Free running disabled
+ *  \li Run in standby disabled
+ *  \li On command disabled
+ *  \li Disable all positive input in sequence
+ *  \li Window monitor disabled
+ *  \li No gain/offset/shift correction
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+static inline void sdadc_get_config_defaults(struct sdadc_config *const config)
+{
+	Assert(config);
+	config->clock_source                  = GCLK_GENERATOR_0;
+	config->reference.ref_sel             = SDADC_REFERENCE_INTREF;
+	config->reference.ref_range           = SDADC_REFRANGE_0;
+	config->reference.on_ref_buffer       = false;
+	config->clock_prescaler               = 2;
+	config->osr                           = SDADC_OVER_SAMPLING_RATIO64;
+	config->skip_count                    = 2;
+	config->mux_input                     = SDADC_MUX_INPUT_AIN1;
+	config->event_action                  = SDADC_EVENT_ACTION_DISABLED;
+	config->freerunning                   = false;
+	config->run_in_standby                = false;
+	config->on_command                    = false;
+	config->seq_enable[0]                 = false;
+	config->seq_enable[1]                 = false;
+	config->seq_enable[2]                 = false;
+	config->window.window_mode            = SDADC_WINDOW_MODE_DISABLE;
+	config->window.window_upper_value     = 0;
+	config->window.window_lower_value     = 0;
+	config->correction.gain_correction    = 1;
+	config->correction.offset_correction  = SDADC_OFFSETCORR_RESETVALUE;
+	config->correction.shift_correction   = SDADC_SHIFTCORR_RESETVALUE;
+}
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module_inst  Pointer to the SDADC software instance struct
+ *
+ * \return Bitmask of \c SDADC_STATUS_* flags.
+ *
+ * \retval SDADC_STATUS_RESULT_READY  SDADC result is ready to be read
+ * \retval SDADC_STATUS_WINDOW        SDADC has detected a value inside the set
+ *                                  window range
+ * \retval SDADC_STATUS_OVERRUN       SDADC result has overrun
+ */
+static inline uint32_t sdadc_get_status(
+		struct sdadc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	uint32_t int_flags = sdadc_module->INTFLAG.reg;
+
+	uint32_t status_flags = 0;
+
+	/* Check for SDADC Result Ready */
+	if (int_flags & SDADC_INTFLAG_RESRDY) {
+		status_flags |= SDADC_STATUS_RESULT_READY;
+	}
+
+	/* Check for SDADC Window Match */
+	if (int_flags & SDADC_INTFLAG_WINMON) {
+		status_flags |= SDADC_STATUS_WINDOW;
+	}
+
+	/* Check for SDADC Overrun */
+	if (int_flags & SDADC_INTFLAG_OVERRUN) {
+		status_flags |= SDADC_STATUS_OVERRUN;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst   Pointer to the SDADC software instance struct
+ * \param[in] status_flags  Bitmask of \c SDADC_STATUS_* flags to clear
+ */
+static inline void sdadc_clear_status(
+		struct sdadc_module *const module_inst,
+		const uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	uint32_t int_flags = 0;
+
+	/* Check for SDADC Result Ready */
+	if (status_flags & SDADC_STATUS_RESULT_READY) {
+		int_flags |= SDADC_INTFLAG_RESRDY;
+	}
+
+	/* Check for SDADC Window Match */
+	if (status_flags & SDADC_STATUS_WINDOW) {
+		int_flags |= SDADC_INTFLAG_WINMON;
+	}
+
+	/* Check for SDADC Overrun */
+	if (status_flags & SDADC_STATUS_OVERRUN) {
+		int_flags |= SDADC_INTFLAG_OVERRUN;
+	}
+
+	/* Clear interrupt flag */
+	sdadc_module->INTFLAG.reg = int_flags;
+}
+
+/**
+ * \brief Get a module sequence flag.
+ *
+ * Get the given status flag of the module.
+ *
+ * \param[in]   module_inst   Pointer to the SDADC software instance struct
+ * \param[out]  seq_state     Identifies the last conversion done in the sequence
+ *
+ * \return Status of the SDADC sequence conversion.
+ *
+ * \retval true  When the sequence start
+ * \retval false When the last conversion in a sequence is done
+ */
+static inline bool sdadc_get_sequence_status(
+		struct sdadc_module *const module_inst,
+		uint8_t* seq_state)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	/* Get SDADC result */
+	*seq_state = sdadc_module->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQSTATE_Msk;
+
+	return ((sdadc_module->SEQSTATUS.bit.SEQBUSY == 1) ? true : false);
+}
+/** @} */
+
+/**
+ * \name Enable, Disable, and Reset SDADC Module, Start Conversion and Read Result
+ * @{
+ */
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module_inst  Pointer to the SDADC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+static inline bool sdadc_is_syncing(
+	struct sdadc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	if (sdadc_module->SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Enables the SDADC module.
+ *
+ * Enables an SDADC module that has previously been configured. If any internal reference
+ * is selected it will be enabled.
+ *
+ * \param[in] module_inst  Pointer to the SDADC software instance struct
+ */
+static inline enum status_code sdadc_enable(
+		struct sdadc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+#if SDADC_CALLBACK_MODE == true
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_SDADC);
+#endif
+
+	sdadc_module->CTRLA.reg |= SDADC_CTRLA_ENABLE;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables the SDADC module.
+ *
+ * Disables an SDADC module that was previously enabled.
+ *
+ * \param[in] module_inst Pointer to the SDADC software instance struct
+ */
+static inline enum status_code sdadc_disable(
+		struct sdadc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+#if SDADC_CALLBACK_MODE == true
+	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_SDADC);
+#endif
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Disbale interrupt */
+	sdadc_module->INTENCLR.reg = SDADC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	sdadc_module->INTFLAG.reg = SDADC_INTFLAG_MASK;
+
+	sdadc_module->CTRLA.reg &= ~SDADC_CTRLA_ENABLE;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Resets the SDADC module.
+ *
+ * Resets an SDADC module, clearing all module state, and registers to their
+ * default values.
+ *
+ * \param[in] module_inst  Pointer to the SDADC software instance struct
+ */
+static inline enum status_code sdadc_reset(
+		struct sdadc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	/* Disable to make sure the pipeline is flushed before reset */
+	sdadc_disable(module_inst);
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Software reset the module */
+	sdadc_module->CTRLA.reg |= SDADC_CTRLA_SWRST;
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Enables an SDADC event input or output.
+ *
+ *  Enables one or more input or output events to or from the SDADC module. See
+ *  \ref sdadc_events for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the SDADC peripheral
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+static inline void sdadc_enable_events(
+		struct sdadc_module *const module_inst,
+		struct sdadc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Window Monitor event */
+	if (events->generate_event_on_window_monitor) {
+		event_mask |= SDADC_EVCTRL_WINMONEO;
+	}
+
+	/* Configure Result Ready event */
+	if (events->generate_event_on_conversion_done) {
+		event_mask |= SDADC_EVCTRL_RESRDYEO;
+	}
+
+	sdadc_module->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables an SDADC event input or output.
+ *
+ *  Disables one or more input or output events to or from the SDADC module. See
+ *  \ref sdadc_events for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the SDADC peripheral
+ *  \param[in] events       Struct containing flags of events to disable
+ */
+static inline void sdadc_disable_events(
+		struct sdadc_module *const module_inst,
+		struct sdadc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Window Monitor event */
+	if (events->generate_event_on_window_monitor) {
+		event_mask |= SDADC_EVCTRL_WINMONEO;
+	}
+
+	/* Configure Result Ready event */
+	if (events->generate_event_on_conversion_done) {
+		event_mask |= SDADC_EVCTRL_RESRDYEO;
+	}
+
+	sdadc_module->EVCTRL.reg &= ~event_mask;
+}
+
+/**
+ * \brief Starts an SDADC conversion.
+ *
+ * Starts a new SDADC conversion.
+ *
+ * \param[in] module_inst  Pointer to the SDADC software instance struct
+ */
+static inline void sdadc_start_conversion(
+		struct sdadc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	sdadc_module->SWTRIG.reg |= SDADC_SWTRIG_START;
+}
+
+/**
+ * \brief Reads the SDADC result.
+ *
+ * Reads the result from an SDADC conversion that was previously started.
+ *
+ * \param[in]  module_inst  Pointer to the SDADC software instance struct
+ * \param[out] result       Pointer to store the result value in
+ *
+ * \return Status of the SDADC read request.
+ * \retval STATUS_OK           The result was retrieved successfully
+ * \retval STATUS_BUSY         A conversion result was not ready
+ * \retval STATUS_ERR_OVERFLOW The result register has been overwritten by the
+ *                             SDADC module before the result was read by the software
+ */
+static inline enum status_code sdadc_read(
+		struct sdadc_module *const module_inst,
+		int32_t *result)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(result);
+
+	if (!(sdadc_get_status(module_inst) & SDADC_STATUS_RESULT_READY)) {
+		/* Result not ready */
+		return STATUS_BUSY;
+	}
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	/* Get SDADC result */
+	*result = ((int32_t)(sdadc_module->RESULT.reg << 8)) >> 8;
+
+	/* Reset ready flag */
+	sdadc_clear_status(module_inst, SDADC_STATUS_RESULT_READY);
+
+	if (sdadc_get_status(module_inst) & SDADC_STATUS_OVERRUN) {
+		sdadc_clear_status(module_inst, SDADC_STATUS_OVERRUN);
+		return STATUS_ERR_OVERFLOW;
+	}
+
+	return STATUS_OK;
+}
+
+/** @} */
+
+/**
+ * \name Runtime Changes of SDADC Module
+ * @{
+ */
+
+/**
+ * \brief Flushes the SDADC pipeline.
+ *
+ * Flushes the pipeline and restart the SDADC clock on the next peripheral clock
+ * edge. All conversions in progress will be lost. When flush is complete, the
+ * module will resume where it left off.
+ *
+ * \param[in] module_inst  Pointer to the SDADC software instance struct
+ */
+static inline void sdadc_flush(
+		struct sdadc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	sdadc_module->SWTRIG.reg |= SDADC_SWTRIG_FLUSH;
+}
+
+/**
+ * \brief Sets the SDADC window mode.
+ *
+ * Sets the SDADC window mode to a given mode and value range.
+ *
+ * \param[in] module_inst         Pointer to the SDADC software instance struct
+ * \param[in] window_mode         Window monitor mode to set
+ * \param[in] window_lower_value  Lower window monitor threshold value
+ * \param[in] window_upper_value  Upper window monitor threshold value
+  */
+static inline void sdadc_set_window_mode(
+		struct sdadc_module *const module_inst,
+		const enum sdadc_window_mode window_mode,
+		const int16_t window_lower_value,
+		const int16_t window_upper_value)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set window mode */
+	sdadc_module->WINCTRL.reg = window_mode << SDADC_WINCTRL_WINMODE_Pos;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set lower window monitor threshold value */
+	sdadc_module->WINLT.reg = window_lower_value << SDADC_WINLT_WINLT_Pos;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set upper window monitor threshold value */
+	sdadc_module->WINUT.reg = window_upper_value << SDADC_WINUT_WINUT_Pos;
+}
+
+/**
+ * \brief Sets MUX SDADC input pin.
+ *
+ * Sets the MUX SDADC input pin selection.
+ *
+ * \param[in] module_inst     Pointer to the SDADC software instance struct
+ * \param[in] mux_input       MUX input pin
+ */
+static inline void sdadc_set_mux_input(
+		struct sdadc_module *const module_inst,
+		const enum sdadc_mux_input mux_input)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+
+	while (sdadc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set mux input pin */
+	sdadc_module->INPUTCTRL.reg =
+			(sdadc_module->INPUTCTRL.reg & ~SDADC_INPUTCTRL_MUXSEL_Msk) | mux_input;
+}
+
+
+/** @} */
+
+#if SDADC_CALLBACK_MODE == true
+/**
+ * \name Enable and Disable Interrupts
+ * @{
+ */
+
+/**
+ * \brief Enable interrupt.
+ *
+ * Enable the given interrupt request from the SDADC module.
+ *
+ * \param[in] module_inst Pointer to the SDADC software instance struct
+ * \param[in] interrupt Interrupt to enable
+ */
+static inline void sdadc_enable_interrupt(struct sdadc_module *const module_inst,
+		enum sdadc_interrupt_flag interrupt)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+	/* Enable interrupt */
+	sdadc_module->INTENSET.reg = interrupt;
+}
+
+/**
+ * \brief Disable interrupt.
+ *
+ * Disable the given interrupt request from the SDADC module.
+ *
+ * \param[in] module_inst Pointer to the SDADC software instance struct
+ * \param[in] interrupt Interrupt to disable
+ */
+static inline void sdadc_disable_interrupt(struct sdadc_module *const module_inst,
+		enum sdadc_interrupt_flag interrupt)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Sdadc *const sdadc_module = module_inst->hw;
+	/* Enable interrupt */
+	sdadc_module->INTENCLR.reg = interrupt;
+}
+
+/** @} */
+#endif /* SDADC_CALLBACK_MODE == true */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_sdadc_extra Extra Information for SDADC Driver
+ *
+ * \section asfdoc_sam0_sdadc_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>SDADC</td>
+ *		<td>Sigma-Delta Analog-to-Digital Converter</td>
+ *	</tr>
+ *  <tr>
+ *		<td>OSR</td>
+ *		<td>Over Sampling Ratio</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_sdadc_extra_dependencies Dependencies
+ * This driver has no dependencies.
+ *
+ *
+ * \section asfdoc_sam0_sdadc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_sdadc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+  *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_sdadc_exqsg Examples for SDADC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sdadc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_sdadc_basic_use_case
+ * \if SDADC_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_sdadc_basic_use_case_callback
+ * \endif
+ *
+ * \page asfdoc_sam0_sdadc_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42496A</td>
+ *		<td>09/2015</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* SDADC_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.c
new file mode 100644
index 0000000000..11543fa620
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.c
@@ -0,0 +1,252 @@
+/**
+ * \file
+ *
+ * \brief SAM Sigma-Delta Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "sdadc_callback.h"
+
+struct sdadc_module *_sdadc_instances[SDADC_INST_NUM];
+
+static void _sdadc_interrupt_handler(const uint8_t instance)
+{
+	struct sdadc_module *module = _sdadc_instances[instance];
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->INTFLAG.reg;
+
+	if (flags & SDADC_INTFLAG_RESRDY) {
+		if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_READ_BUFFER)) &&
+				(module->registered_callback_mask & (1 << SDADC_CALLBACK_READ_BUFFER))) {
+			/* clear interrupt flag */
+			module->hw->INTFLAG.reg = SDADC_INTFLAG_RESRDY;
+
+			/* store SDADC result in job buffer */
+			*(module->job_buffer++) = ((int32_t)(module->hw->RESULT.reg << 8)) >> 8;
+
+			if (--module->remaining_conversions > 0) {
+				if (module->software_trigger == true) {
+					sdadc_start_conversion(module);
+				}
+			} else {
+				if (module->job_status == STATUS_BUSY) {
+					/* job is complete. update status,disable interrupt
+					 *and call callback */
+					module->job_status = STATUS_OK;
+					sdadc_disable_interrupt(module, SDADC_INTERRUPT_RESULT_READY);
+
+					(module->callback[SDADC_CALLBACK_READ_BUFFER])(module);
+				}
+			}
+		}
+	}
+
+	if (flags & SDADC_INTFLAG_WINMON) {
+		module->hw->INTFLAG.reg = SDADC_INTFLAG_WINMON;
+		if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_WINDOW)) &&
+				(module->registered_callback_mask & (1 << SDADC_CALLBACK_WINDOW))) {
+			(module->callback[SDADC_CALLBACK_WINDOW])(module);
+		}
+
+	}
+
+	if (flags & SDADC_INTFLAG_OVERRUN) {
+		module->hw->INTFLAG.reg = SDADC_INTFLAG_OVERRUN;
+		if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_ERROR)) &&
+				(module->registered_callback_mask & (1 << SDADC_CALLBACK_ERROR))) {
+			(module->callback[SDADC_CALLBACK_ERROR])(module);
+		}
+	}
+}
+
+/** Interrupt handler for the SDADC module. */
+void SDADC_Handler(void)
+{
+	_sdadc_interrupt_handler(0);
+}
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by for the interrupt handler to call it
+ * when the condition for the callback is met.
+ *
+ * \param[in] module         Pointer to SDADC software instance struct
+ * \param[in] callback_func  Pointer to callback function
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void sdadc_register_callback(
+		struct sdadc_module *const module,
+		sdadc_callback_t callback_func,
+		enum sdadc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->registered_callback_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in] module         Pointer to SDADC software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void sdadc_unregister_callback(
+		struct sdadc_module *const module,
+		enum sdadc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->registered_callback_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Read multiple samples from SDADC.
+ *
+ * Read \c samples from the SDADC into the \c buffer.
+ * If there is no hardware trigger defined (event action) the
+ * driver will retrigger the SDADC conversion whenever a conversion
+ * is complete until \c samples has been acquired. To avoid
+ * jitter in the sampling frequency using an event trigger is advised.
+ *
+ * \param[in]  module_inst  Pointer to the SDADC software instance struct
+ * \param[in]  samples      Number of samples to acquire
+ * \param[out] buffer       Buffer to store the SDADC samples
+ *
+ * \return Status of the job start.
+ * \retval STATUS_OK        The conversion job was started successfully and is
+ *                          in progress
+ * \retval STATUS_BUSY      The SDADC is already busy with another job
+ */
+enum status_code sdadc_read_buffer_job(
+		struct sdadc_module *const module_inst,
+		int32_t *buffer,
+		uint16_t samples)
+{
+	Assert(module_inst);
+	Assert(samples);
+	Assert(buffer);
+
+	if(module_inst->remaining_conversions != 0 ||
+			module_inst->job_status == STATUS_BUSY){
+		return STATUS_BUSY;
+	}
+
+	module_inst->job_status = STATUS_BUSY;
+	module_inst->remaining_conversions = samples;
+	module_inst->job_buffer = buffer;
+
+	sdadc_enable_interrupt(module_inst, SDADC_INTERRUPT_RESULT_READY);
+
+	if(module_inst->software_trigger == true) {
+		sdadc_start_conversion(module_inst);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Gets the status of a job.
+ *
+ * Gets the status of an ongoing or the last job.
+ *
+ * \param [in]  module_inst Pointer to the SDADC software instance struct
+ * \param [in]  type        Type of job to abort
+ *
+ * \return Status of the job.
+ */
+enum status_code sdadc_get_job_status(
+		struct sdadc_module *module_inst,
+		enum sdadc_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == SDADC_JOB_READ_BUFFER ) {
+		return module_inst->job_status;
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Aborts an ongoing job.
+ *
+ * Aborts an ongoing job with given type.
+ *
+ * \param [in]  module_inst Pointer to the SDADC software instance struct
+ * \param [in]  type        Type of job to abort
+ */
+void sdadc_abort_job(
+		struct sdadc_module *module_inst,
+		enum sdadc_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == SDADC_JOB_READ_BUFFER) {
+		/* Disable interrupt */
+		sdadc_disable_interrupt(module_inst, SDADC_INTERRUPT_RESULT_READY);
+		/* Mark job as aborted */
+		module_inst->job_status = STATUS_ABORTED;
+		module_inst->remaining_conversions = 0;
+	}
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.h
new file mode 100644
index 0000000000..d078758ef3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.h
@@ -0,0 +1,182 @@
+/**
+ * \file
+ *
+ * \brief SAM Sigma-Delta Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SDADC_CALLBACK_H_INCLUDED
+#define SDADC_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sdadc_group
+ *
+ * @{
+ */
+
+#include <sdadc.h>
+
+/**
+ * Enum for the possible types of SDADC asynchronous jobs that may be issued to
+ * the driver.
+ */
+enum sdadc_job_type {
+	/** Asynchronous SDADC read into a user provided buffer */
+	SDADC_JOB_READ_BUFFER,
+};
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void sdadc_register_callback(
+		struct sdadc_module *const module,
+		sdadc_callback_t callback_func,
+		enum sdadc_callback callback_type);
+
+void sdadc_unregister_callback(
+		struct sdadc_module *module,
+		enum sdadc_callback callback_type);
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback function registered by \ref
+ * sdadc_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are met.
+ *
+ * \param[in]     module Pointer to SDADC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \returns    Status of the operation.
+ * \retval     STATUS_OK              If operation was completed
+ * \retval     STATUS_ERR_INVALID     If operation was not completed,
+ *                                    due to invalid callback_type
+ *
+ */
+static inline void sdadc_enable_callback(
+		struct sdadc_module *const module,
+		enum sdadc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->enabled_callback_mask |= (1 << callback_type);
+
+	/* Enable window interrupt if this is a window callback */
+	if (callback_type == SDADC_CALLBACK_WINDOW) {
+		sdadc_enable_interrupt(module, SDADC_INTERRUPT_WINDOW);
+	}
+	/* Enable overrun interrupt if error callback is registered */
+	if (callback_type == SDADC_CALLBACK_ERROR) {
+		sdadc_enable_interrupt(module, SDADC_INTERRUPT_OVERRUN);
+	}
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback function registered by the \ref
+ * sdadc_register_callback.
+ *
+ * \param[in]     module Pointer to SDADC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \returns    Status of the operation.
+ * \retval     STATUS_OK              If operation was completed
+ * \retval     STATUS_ERR_INVALID     If operation was not completed,
+ *                                    due to invalid callback_type
+ *
+ */
+static inline void sdadc_disable_callback(
+		struct sdadc_module *const module,
+		enum sdadc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->enabled_callback_mask &= ~(1 << callback_type);
+
+	/* Disable window interrupt if this is a window callback */
+	if (callback_type == SDADC_CALLBACK_WINDOW) {
+		sdadc_disable_interrupt(module, SDADC_INTERRUPT_WINDOW);
+	}
+	/* Disable overrun interrupt if this is the error callback */
+	if (callback_type == SDADC_CALLBACK_ERROR) {
+		sdadc_disable_interrupt(module, SDADC_INTERRUPT_OVERRUN);
+	}
+}
+
+/** @} */
+
+
+/**
+ * \name Job Management
+ * @{
+ */
+enum status_code sdadc_read_buffer_job(
+		struct sdadc_module *const module_inst,
+		int32_t *buffer,
+		uint16_t samples);
+
+enum status_code sdadc_get_job_status(
+		struct sdadc_module *module_inst,
+		enum sdadc_job_type type);
+
+void sdadc_abort_job(
+		struct sdadc_module *module_inst,
+		enum sdadc_job_type type);
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SDADC_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_common.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_common.h
new file mode 100644
index 0000000000..405b5575a3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_common.h
@@ -0,0 +1,614 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Common Driver
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef I2C_COMMON_H_INCLUDED
+#define I2C_COMMON_H_INCLUDED
+
+#include <compiler.h>
+#include <sercom.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \if (I2C_MASTER_MODE && I2C_SLAVE_MODE)
+ *   \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C (SERCOM I2C) Driver
+ * \elseif I2C_MASTER_MODE
+ *   \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Master Mode (SERCOM I2C) Driver
+ * \elseif I2C_SLAVE_MODE
+ *   \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Slave Mode (SERCOM I2C) Driver
+ * \endif
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's SERCOM
+ * I<SUP>2</SUP>C module, for the transfer of data via an I<SUP>2</SUP>C bus.
+ * The following driver API modes are covered by this manual:
+ *
+ * \if I2C_MASTER_MODE
+ * - Master Mode Polled APIs
+ * \endif
+ * \if I2C_MASTER_CALLBACK_MODE
+ * - Master Mode Callback APIs
+ * \endif
+ * \if I2C_SLAVE_MODE
+ * - Slave Mode Polled APIs
+ * \endif
+ * \if I2C_SLAVE_CALLBACK_MODE
+ * - Slave Mode Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_i2c_prerequisites
+ * - \ref asfdoc_sam0_sercom_i2c_overview
+ * - \ref asfdoc_sam0_sercom_i2c_special_considerations
+ * - \ref asfdoc_sam0_sercom_i2c_extra
+ * - \ref asfdoc_sam0_sercom_i2c_examples
+ * - \ref asfdoc_sam0_sercom_i2c_api_overview
+ *
+ * \section asfdoc_sam0_sercom_i2c_prerequisites Prerequisites
+ * There are no prerequisites.
+ *
+ * \section asfdoc_sam0_sercom_i2c_overview Module Overview
+ * The outline of this section is as follows:
+ * - \ref asfdoc_sam0_sercom_i2c_module_features
+ * - \ref asfdoc_sam0_sercom_i2c_functional_desc
+ * - \ref asfdoc_sam0_sercom_i2c_bus_topology
+ * - \ref asfdoc_sam0_sercom_i2c_transactions
+ * - \ref asfdoc_sam0_sercom_i2c_multi_master
+ * - \ref asfdoc_sam0_sercom_i2c_bus_states
+ * - \ref asfdoc_sam0_sercom_i2c_timeout
+ * - \ref asfdoc_sam0_sercom_i2c_sleep_modes
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_module_features Driver Feature Macro Definition
+ * <table>
+ *	<tr>
+ *		<th>Driver Feature Macro</th>
+ *		<th>Supported devices</th>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED</td>
+ *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_I2C_10_BIT_ADDRESS</td>
+ *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_I2C_SCL_STRETCH_MODE</td>
+ *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_I2C_SCL_EXTEND_TIMEOUT</td>
+ *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
+ *	</tr>
+ * </table>
+ * \note The specific features are only available in the driver when the selected
+ * device supports those features. 
+ * \note When using the I2C high-speed mode for off-board communication,
+ * there are various high frequency interference, which can lead to distortion of the signals 
+ * and communication failure. When using Xplained Pro boards in order to test I2C high-speed 
+ * communication, the following recommendation should be followed:
+ * - Use the SDA-line on PA08 and SCL-line on PA09 for both boards. This will provide stronger
+ * pull-ups on both SDA and SCL.
+ * - The SCL should not be higher than 1.5MHz.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_functional_desc Functional Description
+ * The I<SUP>2</SUP>C provides a simple two-wire bidirectional bus consisting of a
+ * wired-AND type serial clock line (SCL) and a wired-AND type serial data line
+ * (SDA).
+ *
+ * The I<SUP>2</SUP>C bus provides a simple, but efficient method of interconnecting
+ * multiple master and slave devices. An arbitration mechanism is provided for
+ * resolving bus ownership between masters, as only one master device may own
+ * the bus at any given time. The arbitration mechanism relies on the wired-AND
+ * connections to avoid bus drivers short-circuiting.
+ *
+ * A unique address is assigned to all slave devices connected to the bus. A
+ * device can contain both master and slave logic, and can emulate multiple
+ * slave devices by responding to more than one address.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_bus_topology Bus Topology
+ * The I<SUP>2</SUP>C bus topology is illustrated in
+ * \ref asfdoc_sam0_sercom_i2c_bus_topology_figure "the figure below". The pull-up
+ * resistors (Rs) will provide a high level on the bus lines when none of the
+ * I<SUP>2</SUP>C devices are driving the bus. These are optional, and can be
+ * replaced with a constant current source.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_bus_topology_figure
+ * \image html bus_topology.svg "I2C Bus Topology" Width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_transactions Transactions
+ * The I<SUP>2</SUP>C standard defines three fundamental transaction formats:
+ * - Master Write
+ *   - The master transmits data packets to the slave after addressing it
+ * - Master Read
+ *   - The slave transmits data packets to the master after being addressed
+ * - Combined Read/Write
+ *   - A combined transaction consists of several write and read transactions
+ *
+ * A data transfer starts with the master issuing a \b Start condition on the
+ * bus, followed by the address of the slave together with a bit to indicate
+ * whether the master wants to read from or write to the slave.
+ * The addressed slave must respond to this by sending an \b ACK back to the
+ * master.
+ *
+ * After this, data packets are sent from the master or slave, according to the
+ * read/write bit. Each packet must be acknowledged (ACK) or not
+ * acknowledged (NACK) by the receiver.
+ *
+ * If a slave responds with a NACK, the master must assume that the slave
+ * cannot receive any more data and cancel the write operation.
+ *
+ * The master completes a transaction by issuing a \b Stop condition.
+ *
+ * A master can issue multiple \b Start conditions during a transaction; this
+ * is then called a \b Repeated \b Start condition.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_address_packets Address Packets
+ * The slave address consists of seven bits. The 8<SUP>th</SUP> bit in the transfer
+ * determines the data direction (read or write). An address packet always
+ * succeeds a \b Start or \b Repeated \b Start condition. The 8<SUP>th</SUP> bit is handled
+ * in the driver, and the user will only have to provide the 7-bit address.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_data_packets Data Packets
+ * Data packets are nine bits long, consisting of one 8-bit data byte, and an
+ * acknowledgement bit. Data packets follow either an address packet or another
+ * data packet on the bus.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_trans_examples Transaction Examples
+ * The gray bits in the following examples are sent from master to slave, and
+ * the white bits are sent from slave to master.
+ * Example of a read transaction is shown in
+ * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_read "the figure below". Here, the
+ * master first issues a \b Start condition and gets ownership of the bus. An
+ * address packet with the direction flag set to read is then sent and
+ * acknowledged by the slave. Then the slave sends one data packet which is
+ * acknowledged by the master. The slave sends another packet, which is not
+ * acknowledged by the master and indicates that the master will terminate the
+ * transaction. In the end, the transaction is terminated by the master issuing
+ * a \b Stop condition.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_read
+ * \image html i2c_read.svg "I2C Packet Read" Width=100%
+ *
+ * Example of a write transaction is shown in
+ * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_write "the figure below". Here, the
+ * master first issues a \b Start condition and gets ownership of the bus. An
+ * address packet with the dir flag set to write is then sent and acknowledged
+ * by the slave. Then the master sends two data packets, each acknowledged by
+ * the slave. In the end, the transaction is terminated by the master issuing
+ * a \b Stop condition.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_write
+ * \image html i2c_write.svg "I2C Packet Write" Width=100%
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_packet_timeout Packet Timeout
+ * When a master sends an I<SUP>2</SUP>C packet, there is no way of
+ * being sure that a slave will acknowledge the packet. To avoid stalling the
+ * device forever while waiting for an acknowledge, a user selectable timeout
+ * is provided in the \ref i2c_master_config struct which
+ * lets the driver exit a read or write operation after the specified time.
+ * The function will then return the STATUS_ERR_TIMEOUT flag.
+ *
+ * This is also the case for the slave when using the functions postfixed
+ * \c _wait.
+ *
+ * The time before the timeout occurs, will be the same as
+ * for \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "unknown bus state" timeout.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_repeated_start Repeated Start
+ * To issue a \b Repeated \b Start, the functions postfixed \c _no_stop must be
+ * used.
+ * These functions will not send a \b Stop condition when the transfer is done,
+ * thus the next transfer will start with a \b Repeated \b Start. To end the
+ * transaction, the functions without the \c _no_stop postfix must be used
+ * for the last read/write.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_multi_master Multi Master
+ * In a multi master environment, arbitration of the bus is important, as only
+ * one master can own the bus at any point.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_arbitration Arbitration
+ *
+ * \par Clock stretching
+ * The serial clock line is always driven by a master device. However, all
+ * devices connected to the bus are allowed stretch the low period of the clock
+ * to slow down the overall clock frequency or to insert wait states while
+ * processing data.
+ * Both master and slave can randomly stretch the clock, which will force the
+ * other device into a wait-state until the clock line goes high again.
+ *
+ * \par Arbitration on the data line
+ * If two masters start transmitting at the same time, they will both transmit
+ * until one master detects that the other master is pulling the data line low.
+ * When this is detected, the master not pulling the line low, will stop the
+ * transmission and wait until the bus is idle.
+ * As it is the master trying to contact the slave with the lowest address that
+ * will get the bus ownership, this will create an arbitration scheme always
+ * prioritizing the slaves with the lowest address in case of a bus collision.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_clock_sync Clock Synchronization
+ * In situations where more than one master is trying to control the bus clock
+ * line at the same time, a clock synchronization algorithm based on the same
+ * principles used for clock stretching is necessary.
+ *
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_bus_states Bus States
+ * As the I<SUP>2</SUP>C bus is limited to one transaction at the time,
+ * a master that wants to perform a bus transaction must wait until the bus is
+ * free.
+ * Because of this, it is necessary for all masters in a multi-master system to
+ * know the current status of the bus to be able to avoid conflicts and to
+ * ensure data integrity.
+ * \li \b IDLE No activity on the bus (between a \b Stop and a new \b Start
+ * condition)
+ * \li \b OWNER If the master initiates a transaction successfully
+ * \li \b BUSY If another master is driving the bus
+ * \li \b UNKNOWN If the master has recently been enabled or connected to
+ * the bus. Is forced to \b IDLE after given
+ * \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" when
+ * the master module is enabled
+ *
+ * The bus state diagram can be seen in
+ * \ref asfdoc_sam0_sercom_i2c_bus_states_figure "the figure below".
+ * \li S: Start condition
+ * \li P: Stop condition
+ * \li Sr: Repeated start condition
+ * \anchor asfdoc_sam0_sercom_i2c_bus_states_figure
+ * \image html bus_state_diagram.svg "I2C Bus State Diagram" Width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_timeout Bus Timing
+ * Inactive bus timeout for the master and SDA hold time is configurable in the
+ * drivers.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_unknown_bus_timeout Unknown Bus State Timeout
+ * When a master is enabled or connected to the bus, the bus state will be
+ * unknown until either a given timeout or a stop command has occurred. The
+ * timeout is configurable in the \ref i2c_master_config struct.
+ * The timeout time will depend on toolchain and optimization level used, as
+ * the timeout is a loop incrementing a value until it reaches the specified
+ * timeout value.
+ *
+ * \subsubsection sda_hold SDA Hold Timeout
+ * When using the I<SUP>2</SUP>C in slave mode, it will be important to
+ * set a SDA hold time which assures that the master will be able to pick up
+ * the bit sent from the slave. The SDA hold time makes sure that this is the
+ * case by holding the data line low for a given period after the negative edge
+ * on the clock.
+ *
+ * The SDA hold time is also available for the master driver, but is not a
+ * necessity.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_sleep_modes Operation in Sleep Modes
+ * The I<SUP>2</SUP>C module can operate in all sleep modes by setting
+ * the run_in_standby Boolean in the \ref i2c_master_config or
+ * \ref i2c_slave_config struct.
+ * The operation in slave and master mode is shown in
+ * \ref asfdoc_sam0_sercom_i2c_sleep_modes_table "the table below".
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_sleep_modes_table
+ * <table>
+ *   <caption>I2C Standby Operations</caption>
+ *   <tr>
+ *      <th>Run in standby</th>
+ *      <th>Slave</th>
+ *      <th>Master</th>
+ *   </tr>
+ *   <tr>
+ *      <td>false</td>
+ *      <td>Disabled, all reception is dropped</td>
+ *      <td>Generic Clock (GCLK) disabled when master is idle</td>
+ *   </tr>
+ *   <tr>
+ *      <td>true</td>
+ *      <td>Wake on address match when enabled</td>
+ *      <td>GCLK enabled while in sleep modes</td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_sercom_i2c_special_considerations Special Considerations
+ *
+ * \if (I2C_MASTER_CALLBACK_MODE || I2C_SLAVE_CALLBACK_MODE)
+ *   \subsection asfdoc_sam0_sercom_i2c_common_interrupt Interrupt-driven Operation
+ *   While an interrupt-driven operation is in progress, subsequent calls to a
+ *   write or read operation will return the STATUS_BUSY flag, indicating that
+ *   only one operation is allowed at any given time.
+ *
+ *   To check if another transmission can be initiated, the user can either call
+ *   another transfer operation, or use the
+ *   \ref i2c_master_get_job_status/\ref i2c_slave_get_job_status functions
+ *   depending on mode.
+ *
+ *   If the user would like to get callback from operations while using the
+ *   interrupt-driven driver, the callback must be registered and then enabled
+ *   using the "register_callback" and "enable_callback" functions.
+ * \else
+ *   There are no special considerations for this driver for the APIs listed in
+ *   this document.
+ * \endif
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra Extra Information
+ * For extra information, see \ref asfdoc_sam0_sercom_i2c_extra_info_page.
+ * This includes:
+ *  - \ref asfdoc_sam0_sercom_i2c_acronyms
+ *  - \ref asfdoc_sam0_sercom_i2c_extra_dependencies
+ *  - \ref asfdoc_sam0_sercom_i2c_extra_errata
+ *  - \ref asfdoc_sam0_sercom_i2c_extra_history
+ *
+ * \section asfdoc_sam0_sercom_i2c_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_i2c_exqsg.
+ *
+ * \section asfdoc_sam0_sercom_i2c_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \name Driver Feature Definition
+ * Define SERCOM I<SUP>2</SUP>C driver features set according to different device family.
+ *
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || (SAMDA1) || \
+	(SAMHA1) || (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__)
+/** Fast mode plus and high speed support. */
+#  define FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+/** 10-bit address support */
+#  define FEATURE_I2C_10_BIT_ADDRESS
+/** SCL stretch mode support */
+#  define FEATURE_I2C_SCL_STRETCH_MODE
+/** SCL extend timeout support */
+#  define FEATURE_I2C_SCL_EXTEND_TIMEOUT
+#  define FEATURE_I2C_DMA_SUPPORT
+#endif
+/*@}*/
+
+/** \brief Transfer direction
+ *
+ * For master: transfer direction or setting direction bit in address.
+ * For slave: direction of request from master.
+ */
+enum i2c_transfer_direction {
+	/** Master write operation is in progress */
+	I2C_TRANSFER_WRITE = 0,
+	/** Master read operation is in progress */
+	I2C_TRANSFER_READ  = 1,
+};
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_extra_info_page  Extra Information for SERCOM I2C Driver
+ *
+ * \section asfdoc_sam0_sercom_i2c_acronyms Acronyms
+ * \ref asfdoc_sam0_sercom_i2c_acronyms_table "Below" is a table listing the acronyms
+ * used in this module, along with their intended meanings.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_acronyms_table
+ * <table>
+ *  <caption>Acronyms</caption>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>SDA</td>
+ *		<td>Serial Data Line</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SCL</td>
+ *		<td>Serial Clock Line</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>Serial Communication Interface</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DMA</td>
+ *		<td>Direct Memory Access</td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_dependencies Dependencies
+ * The I<SUP>2</SUP>C driver has the following dependencies:
+ * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_history Module History
+ * \ref asfdoc_sam0_sercom_i2c_extra_history_table "Below" is an overview of the
+ * module history, detailing enhancements and fixes made to the module since
+ * its first release. The current version of this corresponds to the newest
+ * version listed in
+ * \ref asfdoc_sam0_sercom_i2c_extra_history_table "the table below".
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_extra_history_table
+ * <table>
+ *  <caption>Module History</caption>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *		\li Added 10-bit addressing and high speed support in SAM D21
+ *		\li Separate structure i2c_packet into i2c_master_packet and i2c_slave packet
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *		\li Added support for SCL stretch and extended timeout hardware features in SAM D21
+ *		\li Added fast mode plus support in SAM D21
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Fixed incorrect logical mask for determining if a bus error has
+ *          occurred in I<SUP>2</SUP>C Slave mode
+ *      </td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_exqsg Examples for SERCOM I2C Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_i2c_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.  
+ *
+ * \if I2C_MASTER_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case"
+ * \endif
+ * \if I2C_MASTER_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_master_callback_use_case "Quick Start Guide for the I2C Master module - Callback Use Case"
+ * - \subpage asfdoc_sam0_sercom_i2c_master_dma_use_case "Quick Start Guide for the I2C Master module - DMA Use Case"
+ * \endif
+ * \if I2C_SLAVE_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_basic_use_case "Quick Start Guide for the I2C Slave module - Basic Use Case"
+ * \endif
+ * \if I2C_SLAVE_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_callback_use_case "Quick Start Guide for the I2C Slave module - Callback Use Case"
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_dma_use_case "Quick Start Guide for the I2C Slave module - DMA Use Case"
+ * \endif
+ *
+ * \page asfdoc_sam0_sercom_i2c_document_revision_history Document Revision History
+ *
+ * \if (I2C_MASTER_MODE || I2C_MASTER_CALLBACK_MODE)
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42117E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42117D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for 10-bit addressing and high speed in SAM D21.
+ *		    Added support for SAM R21 and SAM D10/D11.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42117C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42117B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42117A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ * \else
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42116E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42116D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for 10-bit addressing and high speed in SAM D21.
+ *		    Added support for SAM R21 and SAM D10/D11.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42116C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42116B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42116A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ *\endif
+ */
+
+#endif /* I2C_COMMON_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master.h
new file mode 100644
index 0000000000..79c2effe8e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master.h
@@ -0,0 +1,629 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Master Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2C_MASTER_H_INCLUDED
+#define I2C_MASTER_H_INCLUDED
+
+#include "i2c_common.h"
+#include <sercom.h>
+#include <pinmux.h>
+
+#if I2C_MASTER_CALLBACK_MODE == true
+#  include <sercom_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PINMUX_DEFAULT
+#  define PINMUX_DEFAULT 0
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_i2c_group
+ *
+ * @{
+ */
+
+/**
+ * \brief I<SUP>2</SUP>C master packet for read/write
+ *
+ * Structure to be used when transferring I<SUP>2</SUP>C master packets.
+ */
+struct i2c_master_packet {
+	/** Address to slave device  */
+	uint16_t address;
+	/** Length of data array */
+	uint16_t data_length;
+	/** Data array containing all data to be transferred */
+	uint8_t *data;
+	/** Use 10-bit addressing. Set to false if the feature is not supported by the device  */
+	bool ten_bit_address;
+	/** Use high speed transfer. Set to false if the feature is not supported by the device */
+	bool high_speed;
+	/** High speed mode master code (0000 1XXX), valid when high_speed is true */
+	uint8_t hs_master_code;
+};
+
+/** \brief Interrupt flags
+ *
+ * Flags used when reading or setting interrupt flags.
+ */
+enum i2c_master_interrupt_flag {
+	/** Interrupt flag used for write */
+	I2C_MASTER_INTERRUPT_WRITE = 0,
+	/** Interrupt flag used for read */
+	I2C_MASTER_INTERRUPT_READ  = 1,
+};
+
+/**
+ * \brief Values for hold time after start bit.
+ *
+ * Values for the possible I<SUP>2</SUP>C master mode SDA internal hold times after start
+ * bit has been sent.
+ */
+enum i2c_master_start_hold_time {
+	/** Internal SDA hold time disabled */
+	I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0),
+	/** Internal SDA hold time 50ns - 100ns */
+	I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1),
+	/** Internal SDA hold time 300ns - 600ns */
+	I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2),
+	/** Internal SDA hold time 400ns - 800ns */
+	I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3),
+};
+
+/**
+ * \brief Values for inactive bus time-out.
+ *
+ * If the inactive bus time-out is enabled and the bus is inactive for
+ * longer than the time-out setting, the bus state logic will be set to idle.
+ */
+enum i2c_master_inactive_timeout {
+	/** Inactive bus time-out disabled */
+	I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0),
+	/** Inactive bus time-out 5-6 SCL cycle time-out */
+	I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1),
+	/** Inactive bus time-out 10-11 SCL cycle time-out */
+	I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2),
+	/** Inactive bus time-out 20-21 SCL cycle time-out */
+	I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3),
+};
+
+/**
+ * \brief I<SUP>2</SUP>C frequencies
+ *
+ * Values for I<SUP>2</SUP>C speeds supported by the module. The driver
+ * will also support setting any other value, in which case set
+ * the value in the \ref i2c_master_config at desired value divided by 1000.
+ *
+ * Example: If 10KHz operation is required, give baud_rate in the configuration
+ * structure the value 10.
+ */
+enum i2c_master_baud_rate {
+	/** Baud rate at 100KHz (Standard-mode) */
+	I2C_MASTER_BAUD_RATE_100KHZ = 100,
+	/** Baud rate at 400KHz (Fast-mode) */
+	I2C_MASTER_BAUD_RATE_400KHZ = 400,
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+	/** Baud rate at 1MHz (Fast-mode Plus) */
+	I2C_MASTER_BAUD_RATE_1000KHZ = 1000,
+	/** Baud rate at 3.4MHz (High-speed mode) */
+	I2C_MASTER_BAUD_RATE_3400KHZ = 3400,
+#endif
+};
+
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+/**
+ * \brief Enum for the transfer speed
+ *
+ * Enum for the transfer speed.
+ */
+enum i2c_master_transfer_speed {
+	/** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */
+	I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0),
+	/** Fast-mode Plus (Fm+) up to 1MHz */
+	I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1),
+	/** High-speed mode (Hs-mode) up to 3.4MHz */
+	I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2),
+};
+#endif
+
+#if I2C_MASTER_CALLBACK_MODE == true
+/**
+ * \brief Callback types
+ *
+ * The available callback types for the I<SUP>2</SUP>C master module.
+ */
+enum i2c_master_callback {
+	/** Callback for packet write complete */
+	I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
+	/** Callback for packet read complete */
+	I2C_MASTER_CALLBACK_READ_COMPLETE  = 1,
+	/** Callback for error */
+	I2C_MASTER_CALLBACK_ERROR          = 2,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_I2C_MASTER_CALLBACK_N             = 3,
+#  endif
+};
+
+#  if !defined(__DOXYGEN__)
+/* Prototype for software module */
+struct i2c_master_module;
+
+typedef void (*i2c_master_callback_t)(
+		struct i2c_master_module *const module);
+#  endif
+#endif
+
+/**
+ * \brief SERCOM I<SUP>2</SUP>C Master driver software device instance structure.
+ *
+ * SERCOM I<SUP>2</SUP>C Master driver software instance structure, used to
+ * retain software state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct i2c_master_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware instance initialized for the struct */
+	Sercom *hw;
+	/** Module lock */
+	volatile bool locked;
+	/** Unknown bus state timeout */
+	uint16_t unknown_bus_state_timeout;
+	/** Buffer write timeout value */
+	uint16_t buffer_timeout;
+	/** If true, stop condition will be sent after a read/write */
+	bool send_stop;
+	/** If true, nack signal will be sent after a read/write */
+	bool send_nack;
+#  if I2C_MASTER_CALLBACK_MODE == true
+	/** Pointers to callback functions */
+	volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
+	/** Mask for registered callbacks */
+	volatile uint8_t registered_callback;
+	/** Mask for enabled callbacks */
+	volatile uint8_t enabled_callback;
+	/** The total number of bytes to transfer */
+	volatile uint16_t buffer_length;
+	/**
+	 * Counter used for bytes left to send in write and to count number of
+	 * obtained bytes in read
+	 */
+	volatile uint16_t buffer_remaining;
+	/** Data buffer for packet write and read */
+	volatile uint8_t *buffer;
+	/** Save direction of async request. 1 = read, 0 = write */
+	volatile enum i2c_transfer_direction transfer_direction;
+	/** Status for status read back in error callback */
+	volatile enum status_code status;
+#  endif
+#endif
+};
+
+/**
+ * \brief Configuration structure for the I<SUP>2</SUP>C Master device
+ *
+ * This is the configuration structure for the I<SUP>2</SUP>C Master device. It
+ * is used as an argument for \ref i2c_master_init to provide the desired
+ * configurations for the module. The structure should be initialized using the
+ * \ref i2c_master_get_config_defaults.
+ */
+struct i2c_master_config {
+	/** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
+	 * standard-mode, Fast-mode, and Fast-mode Plus Transfers,
+	 * \ref i2c_master_baud_rate */
+	uint32_t baud_rate;
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+	/** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
+	 * High-speed mode, \ref i2c_master_baud_rate */
+	uint32_t baud_rate_high_speed;
+	/** Transfer speed mode */
+	enum i2c_master_transfer_speed transfer_speed;
+#endif
+	/** GCLK generator to use as clock source */
+	enum gclk_generator generator_source;
+	/** Bus hold time after start signal on data line */
+	enum i2c_master_start_hold_time start_hold_time;
+	/** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" */
+	uint16_t unknown_bus_state_timeout;
+	/** Timeout for packet write to wait for slave */
+	uint16_t buffer_timeout;
+	/** Set to keep module active in sleep modes */
+	bool run_in_standby;
+	/** PAD0 (SDA) pinmux */
+	uint32_t pinmux_pad0;
+	/** PAD1 (SCL) pinmux */
+	uint32_t pinmux_pad1;
+	/** Set to enable SCL low time-out */
+	bool scl_low_timeout;
+	/** Inactive bus time out */
+	enum i2c_master_inactive_timeout inactive_timeout;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+	/** Set to enable SCL stretch only after ACK bit (required for high speed) */
+	bool scl_stretch_only_after_ack_bit;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+	/** Set to enable slave SCL low extend time-out */
+	bool slave_scl_low_extend_timeout;
+	/** Set to enable maser SCL low extend time-out */
+	bool master_scl_low_extend_timeout;
+#endif
+	/** Get more accurate BAUD, considering rise time(required for standard-mode and Fast-mode) */
+	uint16_t sda_scl_rise_time_ns;
+};
+
+/**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code i2c_master_lock(
+		struct i2c_master_module *const module)
+{
+	enum status_code status;
+
+	system_interrupt_enter_critical_section();
+
+	if (module->locked) {
+		status = STATUS_BUSY;
+	} else {
+		module->locked = true;
+		status = STATUS_OK;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline void i2c_master_unlock(struct i2c_master_module *const module)
+{
+	module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Returns the synchronization status of the module
+ *
+ * Returns the synchronization status of the module.
+ *
+ * \param[in]  module  Pointer to software module structure
+ *
+ * \return Status of the synchronization.
+ * \retval true   Module is busy synchronizing
+ * \retval false  Module is not synchronizing
+ */
+static inline bool i2c_master_is_syncing (
+		const struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_hw = &(module->hw->I2CM);
+
+#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
+	return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY);
+#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
+	return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
+#else
+#  error Unknown SERCOM SYNCBUSY scheme!
+#endif
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal
+ * Wait for hardware module to sync
+ *
+ * \param[in]  module  Pointer to software module structure
+ */
+static void _i2c_master_wait_for_sync(
+		const struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+
+	while (i2c_master_is_syncing(module)) {
+		/* Wait for I2C module to sync. */
+	}
+}
+#endif
+
+/**
+ * \brief Gets the I<SUP>2</SUP>C master default configurations
+ *
+ * Use to initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Baudrate 100KHz
+ * - GCLK generator 0
+ * - Do not run in standby
+ * - Start bit hold time 300ns - 600ns
+ * - Buffer timeout = 65535
+ * - Unknown bus status timeout = 65535
+ * - Do not run in standby
+ * - PINMUX_DEFAULT for SERCOM pads
+ *
+ * Those default configuration only available if the device supports it:
+ * - High speed baudrate 3.4MHz
+ * - Standard-mode and Fast-mode transfer speed
+ * - SCL stretch disabled
+ * - Slave SCL low extend time-out disabled
+ * - Master SCL low extend time-out disabled
+ *
+ * \param[out] config  Pointer to configuration structure to be initiated
+ */
+static inline void i2c_master_get_config_defaults(
+		struct i2c_master_config *const config)
+{
+	/*Sanity check argument */
+	Assert(config);
+	config->baud_rate        = I2C_MASTER_BAUD_RATE_100KHZ;
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+	config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
+	config->transfer_speed       = I2C_MASTER_SPEED_STANDARD_AND_FAST;
+#endif
+	config->generator_source = GCLK_GENERATOR_0;
+	config->run_in_standby   = false;
+	config->start_hold_time  = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
+	config->buffer_timeout   = 65535;
+	config->unknown_bus_state_timeout = 65535;
+	config->pinmux_pad0      = PINMUX_DEFAULT;
+	config->pinmux_pad1      = PINMUX_DEFAULT;
+	config->scl_low_timeout  = false;
+	config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+	config->scl_stretch_only_after_ack_bit = false;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+	config->slave_scl_low_extend_timeout   = false;
+	config->master_scl_low_extend_timeout  = false;
+#endif
+	/* The typical value is 215ns */
+	config->sda_scl_rise_time_ns = 215;
+}
+
+enum status_code i2c_master_init(
+		struct i2c_master_module *const module,
+		Sercom *const hw,
+		const struct i2c_master_config *const config);
+
+/**
+ * \brief Enables the I<SUP>2</SUP>C module
+ *
+ * Enables the requested I<SUP>2</SUP>C module and set the bus state to IDLE
+ * after the specified \ref asfdoc_sam0_sercom_i2c_timeout "timeout" period if no
+ * stop bit is detected.
+ *
+ * \param[in]  module  Pointer to the software module struct
+ */
+static inline void i2c_master_enable(
+		const struct i2c_master_module *const module)
+{
+	/* Sanity check of arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Timeout counter used to force bus state */
+	uint32_t timeout_counter = 0;
+
+	/* Wait for module to sync */
+	_i2c_master_wait_for_sync(module);
+
+	/* Enable module */
+	i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Enable module interrupts */
+	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+	/* Start timeout if bus state is unknown */
+	while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
+		timeout_counter++;
+		if(timeout_counter >= (module->unknown_bus_state_timeout)) {
+			/* Timeout, force bus state to idle */
+			i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1);
+			/* Workaround #1 */
+			return;
+		}
+	}
+}
+
+/**
+ * \brief Disable the I<SUP>2</SUP>C module
+ *
+ * Disables the requested I<SUP>2</SUP>C module.
+ *
+ * \param[in]  module  Pointer to the software module struct
+ */
+static inline void i2c_master_disable(
+		const struct i2c_master_module *const module)
+{
+	/* Sanity check of arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+		/* Disable module interrupts */
+		system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+	/* Wait for module to sync */
+	_i2c_master_wait_for_sync(module);
+
+	/* Disbale interrupt */
+	i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MASK;
+
+	/* Disable module */
+	i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+
+}
+
+void i2c_master_reset(struct i2c_master_module *const module);
+
+/** @} */
+
+/**
+* \name Read and Write
+* @{
+*/
+
+enum status_code i2c_master_read_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+void i2c_master_send_stop(struct i2c_master_module *const module);
+
+void i2c_master_send_nack(struct i2c_master_module *const module);
+
+enum status_code i2c_master_read_byte(
+		struct i2c_master_module *const module,
+		uint8_t *byte);
+
+enum status_code i2c_master_write_byte(
+		struct i2c_master_module *const module,
+		uint8_t byte);
+
+enum status_code i2c_master_read_packet_wait_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+/** @} */
+
+#ifdef FEATURE_I2C_DMA_SUPPORT
+/**
+* \name SERCOM I2C Master with DMA Interfaces
+* @{
+*/
+
+/**
+ * \brief Set I<SUP>2</SUP>C for DMA transfer with slave address and transfer size.
+ *
+ * This function will set the slave address, transfer size and enable the auto transfer
+ * mode for DMA.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ * \param[in] addr I<SUP>2</SUP>C slave address
+ * \param[in] length I<SUP>2</SUP>C transfer length with DMA
+ * \param[in] direction I<SUP>2</SUP>C transfer direction
+ *
+ */
+static inline void i2c_master_dma_set_transfer(struct i2c_master_module *const module,
+		uint16_t addr, uint8_t length, enum i2c_transfer_direction direction)
+{
+	module->hw->I2CM.ADDR.reg =
+		SERCOM_I2CM_ADDR_ADDR(addr<<1) |
+		SERCOM_I2CM_ADDR_LENEN |
+		SERCOM_I2CM_ADDR_LEN(length) |
+		direction;
+}
+
+/** @} */
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_MASTER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master_interrupt.h
new file mode 100644
index 0000000000..249525d3c1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master_interrupt.h
@@ -0,0 +1,214 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Master Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2C_MASTER_INTERRUPT_H_INCLUDED
+#define I2C_MASTER_INTERRUPT_H_INCLUDED
+
+#include "i2c_master.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_i2c_group
+ * @{
+ *
+ */
+
+/**
+ * \name Callbacks
+ * @{
+ */
+#if !defined(__DOXYGEN__)
+void _i2c_master_interrupt_handler(
+		uint8_t instance);
+#endif
+
+void i2c_master_register_callback(
+		struct i2c_master_module *const module,
+		i2c_master_callback_t callback,
+		enum i2c_master_callback callback_type);
+
+void i2c_master_unregister_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Callback type to enable
+ */
+static inline void i2c_master_enable_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as enabled */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Callback type to disable
+ */
+static inline void i2c_master_disable_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as disabled */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/** @} */
+
+/**
+ * \name Read and Write, Interrupt-driven
+ * @{
+ */
+
+enum status_code i2c_master_read_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+ 
+enum status_code i2c_master_read_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_job_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+/**
+ * \brief Cancel any currently ongoing operation
+ *
+ * Terminates the running transfer operation.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static inline void i2c_master_cancel_job(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Set buffer to 0 */
+	module->buffer_remaining = 0;
+	/* Update status */
+	module->status = STATUS_ABORTED;
+}
+
+/**
+ * \brief Get status from ongoing job
+ *
+ * Will return the status of a transfer operation.
+ *
+ * \param[in] module  Pointer to software module structure
+ *
+ * \return Last status code from transfer operation.
+ * \retval STATUS_OK                    No error has occurred
+ * \retval STATUS_BUSY                  If transfer is in progress
+ * \retval STATUS_BUSY                  If master module is busy
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ * \retval STATUS_ERR_TIMEOUT           If timeout occurred
+ * \retval STATUS_ERR_OVERFLOW          If slave did not acknowledge last sent
+ *                                      data, indicating that slave does not
+ *                                      want more data and was not able to read
+ */
+static inline enum status_code i2c_master_get_job_status(
+		struct i2c_master_module *const module)
+{
+	/* Check sanity */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Return current status code */
+	return module->status;
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_MASTER_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c
new file mode 100644
index 0000000000..2122e8d1f3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c
@@ -0,0 +1,1050 @@
+/**
+ * \file
+ *
+ * \brief SAM I2C Master Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_master.h"
+
+#if I2C_MASTER_CALLBACK_MODE == true
+# include "i2c_master_interrupt.h"
+#endif
+
+/* Forward declaration */
+enum status_code _i2c_master_wait_for_bus(
+		struct i2c_master_module *const module);
+
+enum status_code _i2c_master_address_response(
+		struct i2c_master_module *const module);
+
+enum status_code _i2c_master_send_hs_master_code(
+		struct i2c_master_module *const module,
+		uint8_t hs_master_code);
+
+#if !defined(__DOXYGEN__)
+
+/**
+ * \internal Sets configurations to module
+ *
+ * \param[out] module  Pointer to software module structure
+ * \param[in]  config  Configuration structure with configurations to set
+ *
+ * \return Status of setting configuration.
+ * \retval STATUS_OK                        If module was configured correctly
+ * \retval STATUS_ERR_ALREADY_INITIALIZED   If setting other GCLK generator than
+ *                                          previously set
+ * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE  If given baudrate is not compatible
+ *                                          with set GCLK frequency
+ */
+static enum status_code _i2c_master_set_config(
+		struct i2c_master_module *const module,
+		const struct i2c_master_config *const config)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+
+	/* Temporary variables. */
+	uint32_t tmp_ctrla;
+	int32_t tmp_baud = 0;
+	int32_t tmp_baud_hs = 0;
+	int32_t tmp_baudlow_hs = 0;
+	enum status_code tmp_status_code = STATUS_OK;
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	Sercom *const sercom_hw = module->hw;
+
+	uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
+
+	/* Pin configuration */
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+
+	uint32_t pad0 = config->pinmux_pad0;
+	uint32_t pad1 = config->pinmux_pad1;
+
+	/* SERCOM PAD0 - SDA */
+	if (pad0 == PINMUX_DEFAULT) {
+		pad0 = _sercom_get_default_pad(sercom_hw, 0);
+	}
+	pin_conf.mux_position = pad0 & 0xFFFF;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+	system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+	/* SERCOM PAD1 - SCL */
+	if (pad1 == PINMUX_DEFAULT) {
+		pad1 = _sercom_get_default_pad(sercom_hw, 1);
+	}
+	pin_conf.mux_position = pad1 & 0xFFFF;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+	system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+	/* Save timeout on unknown bus state in software module. */
+	module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
+
+	/* Save timeout on buffer write. */
+	module->buffer_timeout = config->buffer_timeout;
+
+	/* Set whether module should run in standby. */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
+	} else {
+		tmp_ctrla = 0;
+	}
+
+	/* Check and set start data hold timeout. */
+	if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
+		tmp_ctrla |= config->start_hold_time;
+	}
+
+	/* Check and set transfer speed */
+	tmp_ctrla |= config->transfer_speed;
+
+	/* Check and set SCL low timeout. */
+	if (config->scl_low_timeout) {
+		tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	}
+
+	/* Check and set inactive bus timeout. */
+	if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
+		tmp_ctrla |= config->inactive_timeout;
+	}
+
+	/* Check and set SCL clock stretch mode. */
+	if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED)) {
+		tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
+	}
+
+	/* Check and set slave SCL low extend timeout. */
+	if (config->slave_scl_low_extend_timeout) {
+		tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	}
+
+	/* Check and set master SCL low extend timeout. */
+	if (config->master_scl_low_extend_timeout) {
+		tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	}
+
+	/* Write config to register CTRLA. */
+	i2c_module->CTRLA.reg |= tmp_ctrla;
+
+	/* Set configurations in CTRLB. */
+	i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
+
+	/* Find and set baudrate, considering sda/scl rise time */
+	uint32_t fgclk       = system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index);
+	uint32_t fscl        = 1000 * config->baud_rate;
+	uint32_t fscl_hs     = 1000 * config->baud_rate_high_speed;
+	uint32_t trise       = config->sda_scl_rise_time_ns;
+	
+	tmp_baud = (int32_t)(div_ceil(
+			fgclk - fscl * (10 + (fgclk * 0.000000001)* trise), 2 * fscl));
+	
+	/* For High speed mode, set the SCL ratio of high:low to 1:2. */
+	if (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED) {
+		tmp_baudlow_hs = (int32_t)((fgclk * 2.0) / (3.0 * fscl_hs) - 1);
+		if (tmp_baudlow_hs) {
+			tmp_baud_hs = (int32_t)(fgclk / fscl_hs) - 2 - tmp_baudlow_hs;
+		} else {
+			tmp_baud_hs = (int32_t)(div_ceil(fgclk, 2 * fscl_hs)) - 1;
+		}
+	}
+
+	/* Check that baudrate is supported at current speed. */
+	if (tmp_baud > 255 || tmp_baud < 0 || tmp_baud_hs > 255 || tmp_baud_hs < 0) {
+		/* Baud rate not supported. */
+		tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+	if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) {
+		/* Baud rate acceptable. */
+		i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
+			SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs) | SERCOM_I2CM_BAUD_HSBAUDLOW(tmp_baudlow_hs);
+	}
+
+	return tmp_status_code;
+}
+#endif /* __DOXYGEN__ */
+
+/**
+ * \brief Initializes the requested I<SUP>2</SUP>C hardware module
+ *
+ * Initializes the SERCOM I<SUP>2</SUP>C master device requested and sets the provided
+ * software module struct. Run this function before any further use of
+ * the driver.
+ *
+ * \param[out] module  Pointer to software module struct
+ * \param[in]  hw      Pointer to the hardware instance
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK                        Module initiated correctly
+ * \retval STATUS_ERR_DENIED                If module is enabled
+ * \retval STATUS_BUSY                      If module is busy resetting
+ * \retval STATUS_ERR_ALREADY_INITIALIZED   If setting other GCLK generator than
+ *                                          previously set
+ * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE  If given baudrate is not compatible
+ *                                          with set GCLK frequency
+ *
+ */
+enum status_code i2c_master_init(
+		struct i2c_master_module *const module,
+		Sercom *const hw,
+		const struct i2c_master_config *const config)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize software module */
+	module->hw = hw;
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index, gclk_index;
+
+#if (SAML22) || (SAMC20)
+	pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#elif (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#elif (SAMC21)
+	pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	if (sercom_index == 5) {
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#else
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	/* Turn on module in PM */
+#if (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+	} else {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+	}
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+#endif
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+	/* Check if module is enabled. */
+	if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if reset is in progress. */
+	if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
+		return STATUS_BUSY;
+	}
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Get sercom instance index and register callback. */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+	_sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
+	_sercom_instances[instance_index] = module;
+
+	/* Initialize values in module. */
+	module->registered_callback = 0;
+	module->enabled_callback = 0;
+	module->buffer_length = 0;
+	module->buffer_remaining = 0;
+
+	module->status = STATUS_OK;
+	module->buffer = NULL;
+#endif
+
+	/* Set sercom module to operate in I2C master mode. */
+	i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5);
+
+	/* Set config and return status. */
+	return _i2c_master_set_config(module, config);
+}
+
+/**
+ * \brief Resets the hardware module
+ *
+ * Reset the module to hardware defaults.
+ *
+ * \param[in,out] module Pointer to software module structure
+ */
+void i2c_master_reset(struct i2c_master_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Wait for sync */
+	_i2c_master_wait_for_sync(module);
+
+	/* Disable module */
+	i2c_master_disable(module);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Clear all pending interrupts */
+	system_interrupt_enter_critical_section();
+	system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+	system_interrupt_leave_critical_section();
+#endif
+
+	/* Wait for sync */
+	_i2c_master_wait_for_sync(module);
+
+	/* Reset module */
+	i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal
+ * Address response. Called when address is answered or timed out.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ *
+ * \return Status of address response.
+ * \retval STATUS_OK                    No error has occurred
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code _i2c_master_address_response(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Check for error and ignore bus-error; workaround for BUSSTATE stuck in
+	 * BUSY */
+	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
+
+		/* Clear write interrupt flag */
+		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+
+		/* Check arbitration. */
+		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
+			/* Return packet collision. */
+			return STATUS_ERR_PACKET_COLLISION;
+		}
+	/* Check that slave responded with ack. */
+	} else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+		/* Slave busy. Issue ack and stop command. */
+		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+
+		/* Return bad address value. */
+		return STATUS_ERR_BAD_ADDRESS;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Waits for answer on bus.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ *
+ * \return Status of bus.
+ * \retval STATUS_OK           If given response from slave device
+ * \retval STATUS_ERR_TIMEOUT  If no response was given within specified timeout
+ *                             period
+ */
+enum status_code _i2c_master_wait_for_bus(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Wait for reply. */
+	uint16_t timeout_counter = 0;
+	while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
+			!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) {
+
+		/* Check timeout condition. */
+		if (++timeout_counter >= module->buffer_timeout) {
+			return STATUS_ERR_TIMEOUT;
+		}
+	}
+	return STATUS_OK;
+}
+#endif /* __DOXYGEN__ */
+
+/**
+ * \internal
+ * Send master code for high speed transfer.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ * \param[in]     hs_master_code 8-bit master code (0000 1XXX)
+ *
+ * \return Status of bus.
+ * \retval STATUS_OK           No error happen
+ */
+enum status_code _i2c_master_send_hs_master_code(
+		struct i2c_master_module *const module,
+		uint8_t hs_master_code)
+{
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	/* Return value. */
+	enum status_code tmp_status;
+
+	/* Set NACK for high speed code */
+	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	/* Send high speed code */
+	i2c_module->ADDR.reg = hs_master_code;
+	/* Wait for response on bus. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+	/* Clear write interrupt flag */
+	i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
+
+	return tmp_status;
+}
+
+
+/**
+ * \internal
+ * Starts blocking read operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ *
+ */
+static enum status_code _i2c_master_read_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Return value. */
+	enum status_code tmp_status;
+	uint16_t tmp_data_length = packet->data_length;
+
+	/* Written buffer counter. */
+	uint16_t counter = 0;
+
+	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+	/* Switch to high speed mode */
+	if (packet->high_speed) {
+		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
+	}
+
+	/* Set action to ACK. */
+	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+	/* Set address and direction bit. Will send start command on bus. */
+	if (packet->ten_bit_address) {
+		/*
+		 * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
+		 * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
+		 */
+		i2c_module->ADDR.reg = (packet->address << 1) |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+			SERCOM_I2CM_ADDR_TENBITEN;
+
+		/* Wait for response on bus. */
+		tmp_status = _i2c_master_wait_for_bus(module);
+
+		/* Set action to ack. */
+		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+		/* Check for address response error unless previous error is
+		 * detected. */
+		if (tmp_status == STATUS_OK) {
+			tmp_status = _i2c_master_address_response(module);
+		}
+
+		if (tmp_status == STATUS_OK) {
+			/*
+			 * Write ADDR[7:0] register to "11110 address[9:8] 1"
+			 * ADDR.TENBITEN must be cleared
+			 */
+			i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
+				(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+				I2C_TRANSFER_READ;
+		} else {
+			return tmp_status;
+		}
+	} else {
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+	}
+
+	/* Wait for response on bus. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+
+	/* Set action to ack or nack. */
+	if ((sclsm_flag) && (packet->data_length == 1)) {
+		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	} else {
+		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;	
+	}
+
+	/* Check for address response error unless previous error is
+	 * detected. */
+	if (tmp_status == STATUS_OK) {
+		tmp_status = _i2c_master_address_response(module);
+	}
+
+	/* Check that no error has occurred. */
+	if (tmp_status == STATUS_OK) {
+		/* Read data buffer. */
+		while (tmp_data_length--) {
+			/* Check that bus ownership is not lost. */
+			if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
+				return STATUS_ERR_PACKET_COLLISION;
+			}
+
+			if (module->send_nack && (((!sclsm_flag) && (tmp_data_length == 0)) ||
+					((sclsm_flag) && (tmp_data_length == 1)))) {
+				/* Set action to NACK */
+				i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+			} else {
+				/* Save data to buffer. */
+				_i2c_master_wait_for_sync(module);
+				packet->data[counter++] = i2c_module->DATA.reg;
+				/* Wait for response. */
+				tmp_status = _i2c_master_wait_for_bus(module);
+			}
+
+			/* Check for error. */
+			if (tmp_status != STATUS_OK) {
+				break;
+			}
+		}
+
+		if (module->send_stop) {
+			/* Send stop command unless arbitration is lost. */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		}
+
+		/* Save last data to buffer. */
+		_i2c_master_wait_for_sync(module);
+		packet->data[counter] = i2c_module->DATA.reg;
+	}
+
+	return tmp_status;
+}
+
+/**
+ * \brief Reads data packet from slave
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus and sends a stop condition when finished.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_read_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = true;
+	module->send_nack = true;
+
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Reads data packet from slave without sending a stop condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus without sending a stop condition when done, thus retaining ownership of
+ * the bus when done. To end the transaction, a
+ * \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_read_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = false;
+	module->send_nack = true;
+
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts blocking read operation.
+ * \brief Reads data packet from slave without sending a nack signal and a stop
+ * condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus without sending a nack signal and a stop condition when done,
+ * thus retaining ownership of the bus when done. To end the transaction, a
+ * \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_read_packet_wait_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = false;
+	module->send_nack = false;
+
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts blocking write operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    The packet was write successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+static enum status_code _i2c_master_write_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Return value. */
+	enum status_code tmp_status;
+	uint16_t tmp_data_length = packet->data_length;
+
+	_i2c_master_wait_for_sync(module);
+
+	/* Switch to high speed mode */
+	if (packet->high_speed) {
+		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
+	}
+
+	/* Set action to ACK. */
+	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+	/* Set address and direction bit. Will send start command on bus. */
+	if (packet->ten_bit_address) {
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+			SERCOM_I2CM_ADDR_TENBITEN;
+	} else {
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+	}
+	/* Wait for response on bus. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+
+	/* Check for address response error unless previous error is
+	 * detected. */
+	if (tmp_status == STATUS_OK) {
+		tmp_status = _i2c_master_address_response(module);
+	}
+
+	/* Check that no error has occurred. */
+	if (tmp_status == STATUS_OK) {
+		/* Buffer counter. */
+		uint16_t buffer_counter = 0;
+
+		/* Write data buffer. */
+		while (tmp_data_length--) {
+			/* Check that bus ownership is not lost. */
+			if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
+				return STATUS_ERR_PACKET_COLLISION;
+			}
+
+			/* Write byte to slave. */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->DATA.reg = packet->data[buffer_counter++];
+
+			/* Wait for response. */
+			tmp_status = _i2c_master_wait_for_bus(module);
+
+			/* Check for error. */
+			if (tmp_status != STATUS_OK) {
+				break;
+			}
+
+			/* Check for NACK from slave. */
+			if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+				/* Return bad data value. */
+				tmp_status = STATUS_ERR_OVERFLOW;
+				break;
+			}
+		}
+
+		if (module->send_stop) {
+			/* Stop command */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		}
+	}
+
+	return tmp_status;
+}
+
+/**
+ * \brief Writes data packet to slave
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * and sends a stop condition when finished.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    If packet was write successfully
+ * \retval STATUS_BUSY                  If master module is busy with a job
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ * \retval STATUS_ERR_TIMEOUT           If timeout occurred
+ * \retval STATUS_ERR_OVERFLOW          If slave did not acknowledge last sent
+ *                                      data, indicating that slave does not
+ *                                      want more data and was not able to read
+ *                                      last data sent
+ */
+enum status_code i2c_master_write_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = true;
+	module->send_nack = true;
+
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Writes data packet to slave without sending a stop condition when done
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * without sending a stop condition, thus retaining ownership of the bus when
+ * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition or sending a
+ * stop with the \ref i2c_master_send_stop function must be performed.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    If packet was write successfully
+ * \retval STATUS_BUSY                  If master module is busy
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ * \retval STATUS_ERR_TIMEOUT           If timeout occurred
+ * \retval STATUS_ERR_OVERFLOW          If slave did not acknowledge last sent
+ *                                      data, indicating that slave do not want
+ *                                      more data
+ */
+enum status_code i2c_master_write_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = false;
+	module->send_nack = true;
+
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Sends stop condition on bus
+ *
+ * Sends a stop condition on bus.
+ *
+ * \note This function can only be used after the
+ *       \ref i2c_master_write_packet_wait_no_stop function. If a stop condition
+ *       is to be sent after a read, the \ref i2c_master_read_packet_wait
+ *       function must be used.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void i2c_master_send_stop(struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Send stop command */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+}
+
+/**
+ * \brief Sends nack signal on bus
+ *
+ * Sends a nack signal on bus.
+ *
+ * \note This function can only be used after the
+ *       \ref i2c_master_write_packet_wait_no_nack function,
+ *        or \ref i2c_master_read_byte function.
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void i2c_master_send_nack(struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Send nack signal */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+}
+
+/**
+ * \brief Reads one byte data from slave
+ *
+ * \param[in,out]  module  Pointer to software module struct
+ * \param[out]     byte    Read one byte data to slave
+ *
+ * \return Status of reading byte.
+ * \retval STATUS_OK                    One byte was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_read_byte(
+		struct i2c_master_module *const module,
+		uint8_t *byte)
+{
+  	enum status_code tmp_status;
+  	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	/* Write byte to slave. */
+	_i2c_master_wait_for_sync(module);
+	*byte = i2c_module->DATA.reg;
+	/* Wait for response. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+
+	return tmp_status;
+}
+
+/**
+ * \brief Write one byte data to slave
+ *
+ * \param[in,out]  module  Pointer to software module struct
+ * \param[in]      byte    Send one byte data to slave
+ *
+ * \return Status of writing byte.
+ * \retval STATUS_OK                    One byte was write successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_write_byte(
+		struct i2c_master_module *const module,
+		uint8_t byte)
+{
+  	enum status_code tmp_status;
+  	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Write byte to slave. */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->DATA.reg = byte;
+	/* Wait for response. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+	return tmp_status;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c
new file mode 100644
index 0000000000..7551b29125
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c
@@ -0,0 +1,762 @@
+/**
+ * \file
+ *
+ * \brief SAM I2C Master Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_master_interrupt.h"
+
+extern enum status_code _i2c_master_wait_for_bus(
+		struct i2c_master_module *const module);
+
+extern enum status_code _i2c_master_address_response(
+		struct i2c_master_module *const module);
+
+extern enum status_code _i2c_master_send_hs_master_code(
+		struct i2c_master_module *const module,
+		uint8_t hs_master_code);;
+
+/**
+ * \internal
+ * Read next data. Used by interrupt handler to get next data byte from slave.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_read(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+	/* Find index to save next value in buffer */
+	uint16_t buffer_index = module->buffer_length;
+	buffer_index -= module->buffer_remaining;
+
+	module->buffer_remaining--;
+
+	if (sclsm_flag) {
+		if (module->send_nack && module->buffer_remaining == 1) {
+			/* Set action to NACK. */
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+		}
+	} else {
+		if (module->send_nack && module->buffer_remaining == 0) {
+			/* Set action to NACK. */
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+		}
+	}
+
+	if (module->buffer_remaining == 0) {
+		if (module->send_stop) {
+			/* Send stop condition */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		}
+	}
+	
+	/* Read byte from slave and put in buffer */
+	_i2c_master_wait_for_sync(module);
+	module->buffer[buffer_index] = i2c_module->DATA.reg;
+}
+
+/**
+ * \internal
+ *
+ * Write next data. Used by interrupt handler to send next data byte to slave.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_write(struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Check for ack from slave */
+	if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+	{
+		/* Set status */
+		module->status = STATUS_ERR_OVERFLOW;
+		/* Do not write more data */
+		return;
+	}
+
+	/* Find index to get next byte in buffer */
+	uint16_t buffer_index = module->buffer_length;
+	buffer_index -= module->buffer_remaining;
+
+	module->buffer_remaining--;
+
+	/* Write byte from buffer to slave */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->DATA.reg = module->buffer[buffer_index];
+}
+
+/**
+ * \internal
+ * Acts on slave address response. Checks for errors concerning master->slave
+ * handshake.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_async_address_response(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Check for error. Ignore bus-error; workaround for bus state stuck in
+	 * BUSY.
+	 */
+	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
+	{
+		/* Clear write interrupt flag */
+		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
+
+		/* Check arbitration */
+		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
+			/* Return busy */
+			module->status = STATUS_ERR_PACKET_COLLISION;
+		}
+		/* No slave responds */
+		else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+			module->status           = STATUS_ERR_BAD_ADDRESS;
+			module->buffer_remaining = 0;
+
+			if (module->send_stop) {
+				/* Send stop condition */
+				_i2c_master_wait_for_sync(module);
+				i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+			}
+		}
+	}
+
+	module->buffer_length = module->buffer_remaining;
+
+	/* Check for status OK. */
+	if (module->status == STATUS_BUSY) {
+		/* Call function based on transfer direction. */
+		if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+			_i2c_master_write(module);
+		} else {
+			_i2c_master_read(module);
+		}
+	}
+}
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ *
+ * To enable the callback, the \ref i2c_master_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback       Pointer to the function desired for the
+ *                                specified callback
+ * \param[in]      callback_type  Callback type to register
+ */
+void i2c_master_register_callback(
+		struct i2c_master_module *const module,
+		const i2c_master_callback_t callback,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(callback);
+
+	/* Register callback */
+	module->callbacks[callback_type] = callback;
+
+	/* Set corresponding bit to set callback as registered */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ */
+void i2c_master_unregister_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Register callback */
+	module->callbacks[callback_type] = NULL;
+
+	/* Clear corresponding bit to set callback as unregistered */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal
+ * Starts a read bytes operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_read_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_READ;
+	module->status             = STATUS_BUSY;
+	module->send_stop = false;
+	module->send_nack = false;
+	
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Starts a read packet operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+static enum status_code _i2c_master_read_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	enum status_code tmp_status;
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_READ;
+	module->status             = STATUS_BUSY;
+
+	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+	/* Switch to high speed mode */
+	if (packet->high_speed) {
+		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
+	}
+
+	/* Set action to ACK or NACK. */
+	if ((sclsm_flag) && (packet->data_length == 1)) {
+		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	} else {
+		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	}
+
+	if (packet->ten_bit_address) {
+		/*
+		 * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
+		 * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
+		 */
+		i2c_module->ADDR.reg = (packet->address << 1) |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+			SERCOM_I2CM_ADDR_TENBITEN;
+
+		/* Wait for response on bus. */
+		tmp_status = _i2c_master_wait_for_bus(module);
+
+		/* Set action to ack. */
+		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+		/* Check for address response error unless previous error is
+		 * detected. */
+		if (tmp_status == STATUS_OK) {
+			tmp_status = _i2c_master_address_response(module);
+		}
+
+		if (tmp_status == STATUS_OK) {
+			/* Enable interrupts */
+			i2c_module->INTENSET.reg =
+				SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+			/*
+			 * Write ADDR[7:0] register to "11110 address[9:8] 1"
+			 * ADDR.TENBITEN must be cleared
+			 */
+			i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
+				(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+				I2C_TRANSFER_READ;
+		} else {
+			return tmp_status;
+		}
+	} else {
+		/* Enable interrupts */
+		i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+		/* Set address and direction bit. Will send start command on bus */
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a read packet operation
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus. This is the non-blocking equivalent of \ref i2c_master_read_packet_wait.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_read_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we send STOP */
+	module->send_stop = true;
+	module->send_nack = true;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a read packet operation without sending a STOP condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
+ * sending a stop condition, thus retaining ownership of the bus when done.
+ * To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If reading was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another operation
+ */
+enum status_code i2c_master_read_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we don't send STOP */
+	module->send_stop = false;
+	module->send_nack = true;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a read packet operation without sending a NACK signal and a 
+ * STOP condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
+ * sending a nack and a stop condition, thus retaining ownership of the bus when done.
+ * To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If reading was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another operation
+ */
+enum status_code i2c_master_read_packet_job_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we don't send STOP */
+	module->send_stop = false;
+	module->send_nack = false;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts a write bytes operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting write I<SUP>2</SUP>C bytes.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_write_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_WRITE;
+	module->status             = STATUS_BUSY;
+	module->send_stop = false;
+	module->send_nack = false;
+	
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal Initiates a write packet operation
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK   If writing was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another transfer
+ */
+static enum status_code _i2c_master_write_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Switch to high speed mode */
+	if (packet->high_speed) {
+		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
+	}
+
+	/* Set action to ACK. */
+	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_WRITE;
+	module->status             = STATUS_BUSY;
+
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	/* Set address and direction bit, will send start command on bus */
+	if (packet->ten_bit_address) {
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+			SERCOM_I2CM_ADDR_TENBITEN;
+	} else {
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a write packet operation
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C
+ * bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_write_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with another job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we send STOP at end*/
+	module->send_stop = true;
+	module->send_nack = true;
+	/* Start write operation */
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a write packet operation without sending a STOP condition when done
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * without sending a stop condition, thus retaining ownership of the bus when
+ * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition or sending
+ * a stop with the \ref i2c_master_send_stop function must be performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another
+ */
+enum status_code i2c_master_write_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with another job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Do not send stop condition when done */
+	module->send_stop = false;
+	module->send_nack = true;
+	/* Start write operation */
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Interrupt handler for I<SUP>2</SUP>C master.
+ *
+ * \param[in] instance  SERCOM instance that triggered the interrupt
+ */
+void _i2c_master_interrupt_handler(
+		uint8_t instance)
+{
+	/* Get software module for callback handling */
+	struct i2c_master_module *module =
+			(struct i2c_master_module*)_sercom_instances[instance];
+
+	Assert(module);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+	/* Combine callback registered and enabled masks */
+	uint8_t callback_mask = module->enabled_callback;
+	callback_mask &= module->registered_callback;
+
+	/* Check if the module should respond to address ack */
+	if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
+		/* Call function for address response */
+		_i2c_master_async_address_response(module);
+
+	/* Check if buffer write is done */
+	} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+			(module->status == STATUS_BUSY) &&
+			(module->transfer_direction == I2C_TRANSFER_WRITE)) {
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg =
+				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+
+		module->buffer_length = 0;
+		module->status        = STATUS_OK;
+
+		if (module->send_stop) {
+			/* Send stop condition */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		} else {
+			/* Clear write interrupt flag */
+			i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+		}
+		
+		if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
+			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+		}
+
+	/* Continue buffer write/read */
+	} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
+		/* Check that bus ownership is not lost */
+		if ((!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) &&
+				(!(sclsm_flag && (module->buffer_remaining == 1))))	{
+			module->status = STATUS_ERR_PACKET_COLLISION;
+		} else if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+			_i2c_master_write(module);
+		} else {
+			_i2c_master_read(module);
+		}
+	}
+
+	/* Check if read buffer transfer is complete */
+	if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+			(module->status == STATUS_BUSY) &&
+			(module->transfer_direction == I2C_TRANSFER_READ)) {
+		
+		/* Clear read interrupt flag */
+		if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
+			i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+		}
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg =
+				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+		module->buffer_length = 0;
+		module->status        = STATUS_OK;
+
+		/* Call appropriate callback if enabled and registered */
+		if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
+				&& (module->transfer_direction == I2C_TRANSFER_READ)) {
+			module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
+		} else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
+				&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
+			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+		}
+	}
+
+	/* Check for error */
+	if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) {
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
+				SERCOM_I2CM_INTENCLR_SB;
+
+		module->buffer_length = 0;
+		module->buffer_remaining = 0;
+
+		/* Send nack and stop command unless arbitration is lost */
+		if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
+				module->send_stop) {
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
+					SERCOM_I2CM_CTRLB_CMD(3);
+		}
+
+		/* Call error callback if enabled and registered */
+		if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) {
+			module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c
new file mode 100644
index 0000000000..1130877947
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c
@@ -0,0 +1,745 @@
+/**
+ * \file
+ *
+ * \brief SAM I2C Slave Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_slave.h"
+#if I2C_SLAVE_CALLBACK_MODE == true
+#  include "i2c_slave_interrupt.h"
+#endif
+
+/**
+ * \internal Sets configuration to module
+ *
+ * \param[out] module  Pointer to software module structure
+ * \param[in]  config  Configuration structure with configurations to set
+ *
+ * \return Status of setting configuration.
+ * \retval STATUS_OK                       Module was configured correctly
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  If setting other GCLK generator than
+ *                                         previously set
+ */
+static enum status_code _i2c_slave_set_config(
+		struct i2c_slave_module *const module,
+		const struct i2c_slave_config *const config)
+{
+	uint32_t tmp_ctrla;
+
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+	Sercom *const sercom_hw = module->hw;
+
+	module->buffer_timeout = config->buffer_timeout;
+	module->ten_bit_address = config->ten_bit_address;
+
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+
+	uint32_t pad0 = config->pinmux_pad0;
+	uint32_t pad1 = config->pinmux_pad1;
+
+	/* SERCOM PAD0 - SDA */
+	if (pad0 == PINMUX_DEFAULT) {
+		pad0 = _sercom_get_default_pad(sercom_hw, 0);
+	}
+	pin_conf.mux_position = pad0 & 0xFFFF;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+	system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+	/* SERCOM PAD1 - SCL */
+	if (pad1 == PINMUX_DEFAULT) {
+		pad1 = _sercom_get_default_pad(sercom_hw, 1);
+	}
+	pin_conf.mux_position = pad1 & 0xFFFF;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+	system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+	/* Prepare config to write to register CTRLA */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY;
+	} else {
+		tmp_ctrla = 0;
+	}
+
+	/* Check and set SCL clock stretch mode. */
+	if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_SLAVE_SPEED_HIGH_SPEED)) {
+		tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
+	}
+	
+	tmp_ctrla |= ((uint32_t)config->sda_hold_time |
+			config->transfer_speed |
+			(config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) |
+			(config->slave_scl_low_extend_timeout << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos));
+
+	i2c_hw->CTRLA.reg |= tmp_ctrla;
+
+	/* Set CTRLB configuration */
+	i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode;
+
+	i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos |
+			config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos |
+			config->ten_bit_address << SERCOM_I2CS_ADDR_TENBITEN_Pos |
+			config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the requested I<SUP>2</SUP>C hardware module
+ *
+ * Initializes the SERCOM I<SUP>2</SUP>C slave device requested and sets the provided
+ * software module struct.  Run this function before any further use of
+ * the driver.
+ *
+ * \param[out] module  Pointer to software module struct
+ * \param[in]  hw      Pointer to the hardware instance
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK                       Module initiated correctly
+ * \retval STATUS_ERR_DENIED               If module is enabled
+ * \retval STATUS_BUSY                     If module is busy resetting
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  If setting other GCLK generator than
+ *                                         previously set
+ */
+enum status_code i2c_slave_init(
+		struct i2c_slave_module *const module,
+		Sercom *const hw,
+		const struct i2c_slave_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize software module */
+	module->hw = hw;
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Check if module is enabled */
+	if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if reset is in progress */
+	if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) {
+		return STATUS_BUSY;
+	}
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index, gclk_index; 
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+#if (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#else
+	pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+#else
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+	
+	/* Turn on module in PM */
+#if (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+	} else {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);	
+	}
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+#endif
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Get sercom instance index */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+
+	/* Save software module in interrupt handler */
+	_sercom_set_handler(instance_index, _i2c_slave_interrupt_handler);
+
+	/* Save software module */
+	_sercom_instances[instance_index] = module;
+
+	/* Initialize values in module */
+	module->registered_callback = 0;
+	module->enabled_callback = 0;
+	module->buffer_length = 0;
+	module->nack_on_address = config->enable_nack_on_address;
+#endif
+
+	/* Set SERCOM module to operate in I2C slave mode */
+	i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x4);
+
+	/* Set config and return status */
+	return _i2c_slave_set_config(module, config);
+}
+
+/**
+ * \brief Resets the hardware module
+ *
+ * This will reset the module to hardware defaults.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+void i2c_slave_reset(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Reset module instance */
+	module->registered_callback = 0;
+	module->enabled_callback = 0;
+	module->buffer_length = 0;
+	module->buffer_remaining = 0;
+	module->buffer = NULL;
+#endif
+
+	/* Disable module */
+	i2c_slave_disable(module);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Clear all pending interrupts */
+	system_interrupt_enter_critical_section();
+	system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+	system_interrupt_leave_critical_section();
+#endif
+
+	/* Wait for sync */
+	_i2c_slave_wait_for_sync(module);
+
+	/* Reset module */
+	i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST;
+}
+
+/**
+ * \internal Waits for answer on bus
+ *
+ * \param[in]  module  Pointer to software module structure
+ *
+ * \return Status of bus.
+ * \retval STATUS_OK           If given response from slave device
+ * \retval STATUS_ERR_TIMEOUT  If no response was given within specified timeout
+ *                             period
+ */
+static enum status_code _i2c_slave_wait_for_bus(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Wait for reply */
+	uint16_t timeout_counter = 0;
+	while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) &&
+			(!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) &&
+			(!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) {
+
+		/* Check timeout condition */
+		if (++timeout_counter >= module->buffer_timeout) {
+			return STATUS_ERR_TIMEOUT;
+		}
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Writes a packet to the master
+ *
+ * Writes a packet to the master. This will wait for the master to issue
+ * a request.
+ *
+ * \param[in]  module  Pointer to software module structure
+ * \param[in]  packet  Packet to write to master
+ *
+ * \return Status of packet write.
+ * \retval STATUS_OK                Packet was written successfully
+ * \retval STATUS_ERR_DENIED        Start condition not received, another
+ *                                  interrupt flag is set
+ * \retval STATUS_ERR_IO            There was an error in the previous transfer
+ * \retval STATUS_ERR_BAD_FORMAT    Master wants to write data
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) was provided
+ * \retval STATUS_ERR_BUSY          The I<SUP>2</SUP>C module is busy with a job
+ * \retval STATUS_ERR_ERR_OVERFLOW  Master NACKed before entire packet was
+ *                                  transferred
+ * \retval STATUS_ERR_TIMEOUT       No response was given within the timeout
+ *                                  period
+ */
+enum status_code i2c_slave_write_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	uint16_t length = packet->data_length;
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Check if the module is busy with a job or AMATCH is enabled */
+	if (module->buffer_remaining > 0 ||
+			(i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	enum status_code status;
+	/* Wait for master to send address packet */
+	status = _i2c_slave_wait_for_bus(module);
+
+	if (status != STATUS_OK) {
+			/* Timeout, return */
+			return status;
+	}
+	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		/* Not address interrupt, something is wrong */
+		return STATUS_ERR_DENIED;
+	}
+
+	if (module->ten_bit_address) {
+		/* ACK the first address */
+		i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+		/* Wait for address interrupt */
+		status = _i2c_slave_wait_for_bus(module);
+
+		if (status != STATUS_OK) {
+			/* Timeout, return */
+			return STATUS_ERR_TIMEOUT;
+		}
+
+		if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+			/* Not address interrupt, something is wrong */
+			return STATUS_ERR_DENIED;
+		}
+	}
+
+	/* Check if there was an error in last transfer */
+	if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+			SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
+		return STATUS_ERR_IO;
+	}
+
+	/* Check direction */
+	if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+		/* Write request from master, send NACK and return */
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+		return STATUS_ERR_BAD_FORMAT;
+	}
+
+	/* Read request from master, ACK address */
+	i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+	uint16_t i = 0;
+
+	/* Wait for data interrupt */
+	status = _i2c_slave_wait_for_bus(module);
+	if (status != STATUS_OK) {
+			/* Timeout, return */
+			return status;
+	}
+
+	while (length--) {
+		/* Write data */
+		_i2c_slave_wait_for_sync(module);
+		i2c_hw->DATA.reg = packet->data[i++];
+
+		/* Wait for response from master */
+		status = _i2c_slave_wait_for_bus(module);
+
+		if (status != STATUS_OK) {
+			/* Timeout, return */
+			return status;
+		}
+
+		if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK &&
+				length !=0) {
+			/* NACK from master, abort */
+			/* Release line */
+			i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+			return STATUS_ERR_OVERFLOW;
+		}
+		/* ACK from master, continue writing */
+	}
+
+	/* Release line */
+	i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Reads a packet from the master
+ *
+ * Reads a packet from the master. This will wait for the master to issue a
+ * request.
+ *
+ * \param[in]  module  Pointer to software module structure
+ * \param[out] packet  Packet to read from master
+ *
+ * \return Status of packet read.
+ * \retval STATUS_OK                Packet was read successfully
+ * \retval STATUS_ABORTED           Master sent stop condition or repeated
+ *                                  start before specified length of bytes
+ *                                  was received
+ * \retval STATUS_ERR_IO            There was an error in the previous transfer
+ * \retval STATUS_ERR_DENIED        Start condition not received, another
+ *                                  interrupt flag is set
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) was provided
+ * \retval STATUS_ERR_BUSY          The I<SUP>2</SUP>C module is busy with a job
+ * \retval STATUS_ERR_BAD_FORMAT    Master wants to read data
+ * \retval STATUS_ERR_ERR_OVERFLOW  Last byte received overflows buffer
+ */
+enum status_code i2c_slave_read_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	uint16_t length = packet->data_length;
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Check if the module is busy with a job or AMATCH is enabled */
+	if (module->buffer_remaining > 0 ||
+			(i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	enum status_code status;
+
+	/* Wait for master to send address packet */
+	status = _i2c_slave_wait_for_bus(module);
+	if (status != STATUS_OK) {
+		/* Timeout, return */
+		return status;
+	}
+
+	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		/* Not address interrupt, something is wrong */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if there was an error in the last transfer */
+	if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+			SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
+		return STATUS_ERR_IO;
+	}
+	/* Check direction */
+	if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+		/* Read request from master, send NACK and return */
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+		return STATUS_ERR_BAD_FORMAT;
+	}
+
+	/* Write request from master, ACK address */
+	i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+	uint16_t i = 0;
+	while (length--) {
+
+		/* Wait for next byte or stop condition */
+		status = _i2c_slave_wait_for_bus(module);
+		if (status != STATUS_OK) {
+			/* Timeout, return */
+			return status;
+		}
+
+		if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) ||
+				i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
+			/* Master sent stop condition, or repeated start, read done */
+			/* Clear stop flag */
+			i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+			return STATUS_ABORTED;
+		}
+
+		/* Read data */
+		_i2c_slave_wait_for_sync(module);
+		packet->data[i++] = i2c_hw->DATA.reg;
+
+	}
+
+	/* Packet read done, wait for packet to NACK, Stop or repeated start */
+	status = _i2c_slave_wait_for_bus(module);
+
+	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
+		/* Buffer is full, send NACK */
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+	}
+	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
+		/* Clear stop flag */
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Waits for a start condition on the bus
+ *
+ * \note This function is only available for 7-bit slave addressing.
+ *
+ * Waits for the master to issue a start condition on the bus.
+ * 
+ * \note This function does not check for errors in the last transfer,
+ * this will be discovered when reading or writing.
+ *
+ * \param[in]  module  Pointer to software module structure
+ *
+ * \return Direction of the current transfer, when in slave mode.
+ * \retval I2C_SLAVE_DIRECTION_NONE   No request from master within timeout
+ *                                    period
+ * \retval I2C_SLAVE_DIRECTION_READ   Write request from master
+ * \retval I2C_SLAVE_DIRECTION_WRITE  Read request from master
+ */
+enum i2c_slave_direction i2c_slave_get_direction_wait(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	enum status_code status;
+
+	/* Wait for address interrupt */
+	status = _i2c_slave_wait_for_bus(module);
+
+	if (status != STATUS_OK) {
+		/* Timeout, return */
+		return I2C_SLAVE_DIRECTION_NONE;
+	}
+
+	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		/* Not address interrupt, something is wrong */
+		return I2C_SLAVE_DIRECTION_NONE;
+	}
+
+	/* Check direction */
+	if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+		/* Read request from master */
+		return I2C_SLAVE_DIRECTION_WRITE;
+	} else {
+		/* Write request from master */
+		return I2C_SLAVE_DIRECTION_READ;
+	}
+}
+
+/**
+ * \brief Retrieves the current module status
+ *
+ * Checks the status of the module and returns it as a bitmask of status
+ * flags.
+ *
+ * \param[in] module      Pointer to the I<SUP>2</SUP>C slave software device struct
+ *
+ * \return Bitmask of status flags.
+ *
+ * \retval I2C_SLAVE_STATUS_ADDRESS_MATCH   A valid address has been received
+ * \retval I2C_SLAVE_STATUS_DATA_READY      A I<SUP>2</SUP>C slave byte transmission is
+ *                                          successfully completed
+ * \retval I2C_SLAVE_STATUS_STOP_RECEIVED   A stop condition is detected for a
+ *                                          transaction being processed
+ * \retval I2C_SLAVE_STATUS_CLOCK_HOLD      The slave is holding the SCL line
+ *                                          low
+ * \retval I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT An SCL low time-out has occurred
+ * \retval I2C_SLAVE_STATUS_REPEATED_START  Indicates a repeated start, only
+ *                                          valid if \ref
+ *                                          I2C_SLAVE_STATUS_ADDRESS_MATCH is
+ *                                          set
+ * \retval I2C_SLAVE_STATUS_RECEIVED_NACK   The last data packet sent was not
+ *                                          acknowledged
+ * \retval I2C_SLAVE_STATUS_COLLISION       The I<SUP>2</SUP>C slave was not able to
+ *                                          transmit a high data or NACK bit
+ * \retval I2C_SLAVE_STATUS_BUS_ERROR       An illegal bus condition has
+ *                                          occurred on the bus
+ */
+uint32_t i2c_slave_get_status(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	uint8_t intflags = i2c_hw->INTFLAG.reg;
+	uint8_t status = i2c_hw->STATUS.reg;
+	uint32_t status_flags = 0;
+
+	/* Check Address Match flag */
+	if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) {
+		status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH;
+	}
+	/* Check Data Ready flag */
+	if (intflags & SERCOM_I2CS_INTFLAG_DRDY) {
+		status_flags |= I2C_SLAVE_STATUS_DATA_READY;
+	}
+	/* Check Stop flag */
+	if (intflags & SERCOM_I2CS_INTFLAG_PREC) {
+		status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED;
+	}
+	/* Check Clock Hold */
+	if (status & SERCOM_I2CS_STATUS_CLKHOLD) {
+		status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD;
+	}
+	/* Check SCL Low Timeout */
+	if (status & SERCOM_I2CS_STATUS_LOWTOUT) {
+		status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT;
+	}
+	/* Check Repeated Start */
+	if (status & SERCOM_I2CS_STATUS_SR) {
+		status_flags |= I2C_SLAVE_STATUS_REPEATED_START;
+	}
+	/* Check Received Not Acknowledge */
+	if (status & SERCOM_I2CS_STATUS_RXNACK) {
+		status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK;
+	}
+	/* Check Transmit Collision */
+	if (status & SERCOM_I2CS_STATUS_COLL) {
+		status_flags |= I2C_SLAVE_STATUS_COLLISION;
+	}
+	/* Check Bus Error */
+	if (status & SERCOM_I2CS_STATUS_BUSERR) {
+		status_flags |= I2C_SLAVE_STATUS_BUS_ERROR;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag
+ *
+ * Clears the given status flag of the module.
+ *
+ * \note Not all status flags can be cleared.
+ *
+ * \param[in] module         Pointer to the I<SUP>2</SUP>C software device struct
+ * \param[in] status_flags   Bit mask of status flags to clear
+ *
+ */
+void i2c_slave_clear_status(
+		struct i2c_slave_module *const module,
+		uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Clear Address Match flag */
+	if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) {
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+	}
+	/* Clear Data Ready flag */
+	if (status_flags & I2C_SLAVE_STATUS_DATA_READY) {
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+	}
+	/* Clear Stop flag */
+	if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) {
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+	}
+	/* Clear SCL Low Timeout */
+	if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) {
+		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+	}
+	/* Clear Transmit Collision */
+	if (status_flags & I2C_SLAVE_STATUS_COLLISION) {
+		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+	}
+	/* Clear Bus Error */
+	if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) {
+		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c
new file mode 100644
index 0000000000..0a6f234f8b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c
@@ -0,0 +1,434 @@
+/**
+ * \file
+ *
+ * \brief SAM I2C Slave Interrupt Driver
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_slave_interrupt.h"
+
+/**
+ * \brief Enables sending of NACK on address match
+ *
+ * Enables sending of NACK on address match, thus discarding
+ * any incoming transaction.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+void i2c_slave_enable_nack_on_address(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+
+	module->nack_on_address = true;
+}
+
+/**
+ * \brief Disables sending NACK on address match
+ *
+ * Disables sending of NACK on address match, thus
+ * acknowledging incoming transactions.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+void i2c_slave_disable_nack_on_address(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+
+	module->nack_on_address = false;
+}
+
+/**
+ * \internal
+ * Reads next data. Used by interrupt handler to get next data byte from master.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_slave_read(
+		struct i2c_slave_module *const module)
+{
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Read byte from master and put in buffer. */
+	*(module->buffer++) = i2c_hw->DATA.reg;
+
+	/*Decrement remaining buffer length */
+	module->buffer_remaining--;
+}
+
+/**
+ * \internal
+ * Writes next data. Used by interrupt handler to send next data byte to master.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_slave_write(
+		struct i2c_slave_module *const module)
+{
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Write byte from buffer to master */
+	i2c_hw->DATA.reg = *(module->buffer++);
+
+	/*Decrement remaining buffer length */
+	module->buffer_remaining--;
+}
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type. To enable the callback, the
+ * \ref i2c_slave_enable_callback function must be used.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback       Pointer to the function desired for the
+ *                               specified callback
+ * \param[in]     callback_type  Callback type to register
+ */
+void i2c_slave_register_callback(
+		struct i2c_slave_module *const module,
+		i2c_slave_callback_t callback,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(callback);
+
+	/* Register callback. */
+	module->callbacks[callback_type] = callback;
+
+	/* Set corresponding bit to set callback as initiated. */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * Removes the currently registered callback for the given callback
+ * type.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback_type  Callback type to unregister
+ */
+void i2c_slave_unregister_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Register callback. */
+	module->callbacks[callback_type] = NULL;
+
+	/* Set corresponding bit to set callback as initiated. */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Initiates a reads packet operation
+ *
+ * Reads a data packet from the master. A write request must be initiated by
+ * the master before the packet can be read.
+ *
+ * The \ref I2C_SLAVE_CALLBACK_WRITE_REQUEST callback can be used to call this
+ * function.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting asynchronously reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_slave_read_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy doing async operation. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Save packet to software module. */
+	module->buffer           = packet->data;
+	module->buffer_remaining = packet->data_length;
+	module->buffer_length    = packet->data_length;
+	module->status           = STATUS_BUSY;
+
+	/* Enable interrupts */
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+	i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
+			SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
+
+	/* Read will begin when master initiates the transfer */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a write packet operation
+ *
+ * Writes a data packet to the master. A read request must be initiated by
+ * the master before the packet can be written.
+ *
+ * The \ref I2C_SLAVE_CALLBACK_READ_REQUEST callback can be used to call this
+ * function.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If writing was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another transfer
+ */
+enum status_code i2c_slave_write_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy doing async operation. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Save packet to software module. */
+	module->buffer           = packet->data;
+	module->buffer_remaining = packet->data_length;
+	module->buffer_length    = packet->data_length;
+	module->status           = STATUS_BUSY;
+
+	/* Enable interrupts */
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+	i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
+			SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal Interrupt handler for I<SUP>2</SUP>C slave
+ *
+ * \param[in] instance Sercom instance that triggered the interrupt
+ */
+void _i2c_slave_interrupt_handler(
+		uint8_t instance)
+{
+	/* Get software module for callback handling. */
+	struct i2c_slave_module *module =
+			(struct i2c_slave_module*)_sercom_instances[instance];
+
+	Assert(module);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Combine callback registered and enabled masks. */
+	uint8_t callback_mask = module->enabled_callback;
+	callback_mask &= module->registered_callback;
+
+
+	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
+	/* Address match */
+		/* Check if last transfer is done - repeated start */
+		if (module->buffer_length != module->buffer_remaining &&
+				module->transfer_direction == I2C_TRANSFER_WRITE) {
+
+			module->status = STATUS_OK;
+			module->buffer_length = 0;
+			module->buffer_remaining = 0;
+
+			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))) {
+				module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+			}
+		} else if (module->buffer_length != module->buffer_remaining &&
+				module->transfer_direction == I2C_TRANSFER_READ) {
+			module->status = STATUS_OK;
+			module->buffer_length = 0;
+			module->buffer_remaining = 0;
+
+			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))) {
+				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+			}
+		}
+
+		if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+				SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
+			/* An error occurred in last packet transfer */
+			module->status = STATUS_ERR_IO;
+
+			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER))) {
+				module->callbacks[I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER](module);
+			}
+		}
+		if (module->nack_on_address) {
+			/* NACK address, workaround 13574 */
+			_i2c_slave_set_ctrlb_ackact(module, false);
+		} else if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR) {
+			/* Set transfer direction in module instance */
+			module->transfer_direction = I2C_TRANSFER_READ;
+
+			/* Read request from master */
+			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) {
+				module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
+			}
+
+			if (module->buffer_length == 0) {
+				/* Data buffer not set up, NACK address, workaround 13574*/
+				_i2c_slave_set_ctrlb_ackact(module, false);
+			} else {
+				/* ACK address, workaround 13574 */
+				_i2c_slave_set_ctrlb_ackact(module, true);
+			}
+		} else {
+			/* Set transfer direction in dev inst */
+			module->transfer_direction = I2C_TRANSFER_WRITE;
+
+			/* Write request from master */
+			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)) {
+				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
+			}
+
+			if (module->buffer_length == 0) {
+				/* Data buffer not set up, NACK address, workaround 13574 */
+				_i2c_slave_set_ctrlb_ackact(module, false);
+			} else {
+				/* ACK address, workaround 13574 */
+				_i2c_slave_set_ctrlb_ackact(module, true);
+			}
+		}
+
+		/* ACK or NACK address, Workaround 13574 */
+		_i2c_slave_set_ctrlb_cmd3(module);
+
+		/* ACK next incoming packet, workaround 13574 */
+		_i2c_slave_set_ctrlb_ackact(module, true);
+
+	} else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
+		/* Stop condition on bus - current transfer done */
+
+		/* Clear Stop interrupt */
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+
+		/* Disable interrupts */
+		i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_DRDY;
+
+		if (!((module->enabled_callback & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
+				|| (module->enabled_callback == (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)))) {
+			/* Disable address match if read/write request is not enabled */
+			i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+		}
+
+		if (!(module->status == STATUS_ERR_OVERFLOW || module->status == STATUS_ERR_IO)) {
+			module->status = STATUS_OK;
+			module->buffer_length = 0;
+			module->buffer_remaining = 0;
+
+			/* Call appropriate callback if enabled and registered */
+			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))
+					&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
+				/* Read from master complete */
+				module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+			} else if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))
+					&& (module->transfer_direction == I2C_TRANSFER_READ)) {
+				/* Write to master complete */
+				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+			}
+					}
+	} else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
+		/* Check if buffer is full, or NACK from master */
+		if (module->buffer_remaining <= 0 ||
+				(module->transfer_direction == I2C_TRANSFER_READ &&
+				(module->buffer_length > module->buffer_remaining) &&
+				(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK))) {
+
+			module->buffer_remaining = 0;
+			module->buffer_length = 0;
+
+			if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+				/* Buffer is full, send NACK, workaround 13574 */
+				_i2c_slave_set_ctrlb_ackact(module, false);
+				i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+
+				/* Set status, new character in DATA register will overflow
+				 * buffer */
+				module->status = STATUS_ERR_OVERFLOW;
+
+				if (callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR)) {
+					/* Read complete */
+					module->callbacks[I2C_SLAVE_CALLBACK_ERROR](module);
+				}
+			} else {
+				/* Release SCL and wait for new start condition */
+				_i2c_slave_set_ctrlb_ackact(module, false);
+				i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+
+				/* Transfer successful */
+				module->status = STATUS_OK;
+
+				/* Disable interrupts */
+				i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_DRDY;
+			}
+
+		/* Continue buffer write/read */
+		} else if (module->buffer_length > 0 && module->buffer_remaining > 0) {
+			/* Call function based on transfer direction */
+			if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+				_i2c_slave_read(module);
+			} else {
+				_i2c_slave_write(module);
+			}
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c
new file mode 100644
index 0000000000..ce4f58c230
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c
@@ -0,0 +1,881 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 I2C Master Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_master.h"
+
+#if I2C_MASTER_CALLBACK_MODE == true
+# include "i2c_master_interrupt.h"
+#endif
+
+#if !defined(__DOXYGEN__)
+
+/**
+ * \internal Sets configurations to module
+ *
+ * \param[out] module  Pointer to software module structure
+ * \param[in]  config  Configuration structure with configurations to set
+ *
+ * \return Status of setting configuration.
+ * \retval STATUS_OK                        If module was configured correctly
+ * \retval STATUS_ERR_ALREADY_INITIALIZED   If setting other GCLK generator than
+ *                                          previously set
+ * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE  If given baud rate is not compatible
+ *                                          with set GCLK frequency
+ */
+static enum status_code _i2c_master_set_config(
+		struct i2c_master_module *const module,
+		const struct i2c_master_config *const config)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+
+	/* Temporary variables. */
+	uint32_t tmp_ctrla;
+	int32_t tmp_baud;
+	enum status_code tmp_status_code = STATUS_OK;
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	Sercom *const sercom_hw = module->hw;
+
+	uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
+
+	/* Pin configuration */
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+
+	uint32_t pad0 = config->pinmux_pad0;
+	uint32_t pad1 = config->pinmux_pad1;
+
+	/* SERCOM PAD0 - SDA */
+	if (pad0 == PINMUX_DEFAULT) {
+		pad0 = _sercom_get_default_pad(sercom_hw, 0);
+	}
+	pin_conf.mux_position = pad0 & 0xFFFF;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+	system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+	/* SERCOM PAD1 - SCL */
+	if (pad1 == PINMUX_DEFAULT) {
+		pad1 = _sercom_get_default_pad(sercom_hw, 1);
+	}
+	pin_conf.mux_position = pad1 & 0xFFFF;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+	system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+	/* Save timeout on unknown bus state in software module. */
+	module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
+
+	/* Save timeout on buffer write. */
+	module->buffer_timeout = config->buffer_timeout;
+
+	/* Set whether module should run in standby. */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
+	} else {
+		tmp_ctrla = 0;
+	}
+
+	/* Check and set start data hold timeout. */
+	if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
+		tmp_ctrla |= config->start_hold_time;
+	}
+
+	/* Check and set SCL low timeout. */
+	if (config->scl_low_timeout) {
+		tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUT;
+	}
+
+	/* Check and set inactive bus timeout. */
+	if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
+		tmp_ctrla |= config->inactive_timeout;
+	}
+
+	/* Write config to register CTRLA. */
+	i2c_module->CTRLA.reg |= tmp_ctrla;
+
+	/* Set configurations in CTRLB. */
+	i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
+
+	/* Find and set baudrate. */
+	tmp_baud = (int32_t)(div_ceil(
+				system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index),
+				(2000*(config->baud_rate))) - 5);
+
+	/* Check that baud rate is supported at current speed. */
+	if (tmp_baud > 255 || tmp_baud < 0) {
+		/* Baud rate not supported. */
+		tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	} else {
+		/* Baud rate acceptable. */
+		i2c_module->BAUD.reg = (uint8_t)tmp_baud;
+	}
+
+	return tmp_status_code;
+}
+#endif /* __DOXYGEN__ */
+
+/**
+ * \brief Initializes the requested I<SUP>2</SUP>C hardware module
+ *
+ * Initializes the SERCOM I<SUP>2</SUP>C master device requested and sets the provided
+ * software module struct. Run this function before any further use of
+ * the driver.
+ *
+ * \param[out] module  Pointer to software module struct
+ * \param[in]  hw      Pointer to the hardware instance
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK                        Module initiated correctly
+ * \retval STATUS_ERR_DENIED                If module is enabled
+ * \retval STATUS_BUSY                      If module is busy resetting
+ * \retval STATUS_ERR_ALREADY_INITIALIZED   If setting other GCLK generator than
+ *                                          previously set
+ * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE  If given baudrate is not compatible
+ *                                          with set GCLK frequency
+ *
+ */
+enum status_code i2c_master_init(
+		struct i2c_master_module *const module,
+		Sercom *const hw,
+		const struct i2c_master_config *const config)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize software module */
+	module->hw = hw;
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+	/* Turn on module in PM */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+	/* Check if module is enabled. */
+	if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if reset is in progress. */
+	if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
+		return STATUS_BUSY;
+	}
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Get sercom instance index and register callback. */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+	_sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
+	_sercom_instances[instance_index] = module;
+
+	/* Initialize values in module. */
+	module->registered_callback = 0;
+	module->enabled_callback = 0;
+	module->buffer_length = 0;
+	module->buffer_remaining = 0;
+
+	module->status = STATUS_OK;
+	module->buffer = NULL;
+#endif
+
+	/* Set sercom module to operate in I2C master mode. */
+	i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER;
+
+	/* Set config and return status. */
+	return _i2c_master_set_config(module, config);
+}
+
+/**
+ * \brief Resets the hardware module
+ *
+ * Reset the module to hardware defaults.
+ *
+ * \param[in,out] module Pointer to software module structure
+ */
+void i2c_master_reset(struct i2c_master_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Wait for sync */
+	_i2c_master_wait_for_sync(module);
+
+	/* Disable module */
+	i2c_master_disable(module);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Clear all pending interrupts */
+	system_interrupt_enter_critical_section();
+	system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+	system_interrupt_leave_critical_section();
+#endif
+
+	/* Wait for sync */
+	_i2c_master_wait_for_sync(module);
+
+	/* Reset module */
+	i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal
+ * Address response. Called when address is answered or timed out.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ *
+ * \return Status of address response.
+ * \retval STATUS_OK                    No error has occurred
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+static enum status_code _i2c_master_address_response(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Check for error and ignore bus-error; workaround for BUSSTATE stuck in
+	 * BUSY */
+	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
+
+		/* Clear write interrupt flag */
+		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+
+		/* Check arbitration. */
+		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
+			/* Return packet collision. */
+			return STATUS_ERR_PACKET_COLLISION;
+		}
+	/* Check that slave responded with ack. */
+	} else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+		/* Slave busy. Issue ack and stop command. */
+		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+
+		/* Return bad address value. */
+		return STATUS_ERR_BAD_ADDRESS;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Waits for answer on bus.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ *
+ * \return Status of bus.
+ * \retval STATUS_OK           If given response from slave device
+ * \retval STATUS_ERR_TIMEOUT  If no response was given within specified timeout
+ *                             period
+ */
+static enum status_code _i2c_master_wait_for_bus(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Wait for reply. */
+	uint16_t timeout_counter = 0;
+	while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
+			!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) {
+
+		/* Check timeout condition. */
+		if (++timeout_counter >= module->buffer_timeout) {
+			return STATUS_ERR_TIMEOUT;
+		}
+	}
+	return STATUS_OK;
+}
+#endif /* __DOXYGEN__ */
+
+/**
+ * \internal
+ * Starts blocking read operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ *
+ */
+static enum status_code _i2c_master_read_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Return value. */
+	enum status_code tmp_status;
+	uint16_t tmp_data_length = packet->data_length;
+
+	/* Written buffer counter. */
+	uint16_t counter = 0;
+
+	/* Set address and direction bit. Will send start command on bus. */
+	i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ;
+
+	/* Wait for response on bus. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+
+	/* Set action to ack. */
+	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+	/* Check for address response error unless previous error is
+	 * detected. */
+	if (tmp_status == STATUS_OK) {
+		tmp_status = _i2c_master_address_response(module);
+	}
+
+	/* Check that no error has occurred. */
+	if (tmp_status == STATUS_OK) {
+		/* Read data buffer. */
+		while (tmp_data_length--) {
+			/* Check that bus ownership is not lost. */
+			if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
+				return STATUS_ERR_PACKET_COLLISION;
+			}
+
+			if (module->send_nack && tmp_data_length == 0) {
+				/* Set action to NACK */
+				i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+			} else {
+				/* Save data to buffer. */
+				_i2c_master_wait_for_sync(module);
+				packet->data[counter++] = i2c_module->DATA.reg;
+				/* Wait for response. */
+				tmp_status = _i2c_master_wait_for_bus(module);
+			}
+
+			/* Check for error. */
+			if (tmp_status != STATUS_OK) {
+				break;
+			}
+		}
+
+		if (module->send_stop) {
+			/* Send stop command unless arbitration is lost. */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		} else {
+		  	_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(1);
+		}
+
+		/* Save last data to buffer. */
+		_i2c_master_wait_for_sync(module);
+		packet->data[counter] = i2c_module->DATA.reg;
+	}
+
+	return tmp_status;
+}
+
+/**
+ * \brief Reads data packet from slave
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus and sends a stop condition when finished.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_read_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = true;
+	module->send_nack = true;
+	
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Reads data packet from slave without sending a stop condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus without sending a stop condition when done, thus retaining ownership of
+ * the bus when done. To end the transaction, a
+ * \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_read_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = false;
+	module->send_nack = true;
+	
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts blocking read operation.
+ * \brief Reads data packet from slave without sending a nack signal and a stop 
+ * condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus without sending a nack signal and a stop condition when done, 
+ * thus retaining ownership of the bus when done. To end the transaction, a
+ * \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK                    The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_read_packet_wait_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = false;
+	module->send_nack = false;
+
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts blocking write operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    The packet was write successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+static enum status_code _i2c_master_write_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Return value. */
+	enum status_code tmp_status;
+	uint16_t tmp_data_length = packet->data_length;
+
+	_i2c_master_wait_for_sync(module);
+
+	/* Set address and direction bit. Will send start command on bus. */
+	i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE;
+
+	/* Wait for response on bus. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+
+	/* Check for address response error unless previous error is
+	 * detected. */
+	if (tmp_status == STATUS_OK) {
+		tmp_status = _i2c_master_address_response(module);
+	}
+
+	/* Check that no error has occurred. */
+	if (tmp_status == STATUS_OK) {
+		/* Buffer counter. */
+		uint16_t buffer_counter = 0;
+
+		/* Write data buffer. */
+		while (tmp_data_length--) {
+			/* Check that bus ownership is not lost. */
+			if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
+				return STATUS_ERR_PACKET_COLLISION;
+			}
+
+			/* Write byte to slave. */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->DATA.reg = packet->data[buffer_counter++];
+
+			/* Wait for response. */
+			tmp_status = _i2c_master_wait_for_bus(module);
+
+			/* Check for error. */
+			if (tmp_status != STATUS_OK) {
+				break;
+			}
+
+			/* Check for NACK from slave. */
+			if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+				/* Return bad data value. */
+				tmp_status = STATUS_ERR_OVERFLOW;
+				break;
+			}
+		}
+
+		if (module->send_stop) {
+			/* Stop command */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		}
+	}
+
+	return tmp_status;
+}
+
+/**
+ * \brief Writes data packet to slave
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * and sends a stop condition when finished.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    If packet was write successfully
+ * \retval STATUS_BUSY                  If master module is busy with a job
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ * \retval STATUS_ERR_TIMEOUT           If timeout occurred
+ * \retval STATUS_ERR_OVERFLOW          If slave did not acknowledge last sent
+ *                                      data, indicating that slave does not
+ *                                      want more data and was not able to read
+ *                                      last data sent
+ */
+enum status_code i2c_master_write_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = true;
+	module->send_nack = true;
+	
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Writes data packet to slave without sending a stop condition when done
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * without sending a stop condition, thus retaining ownership of the bus when
+ * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition or sending a
+ * stop with the \ref i2c_master_send_stop function must be performed.
+ *
+ * \note This will stall the device from any other operation. For
+ *       interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of write packet.
+ * \retval STATUS_OK                    If packet was write successfully
+ * \retval STATUS_BUSY                  If master module is busy
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ * \retval STATUS_ERR_TIMEOUT           If timeout occurred
+ * \retval STATUS_ERR_OVERFLOW          If slave did not acknowledge last sent
+ *                                      data, indicating that slave do not want
+ *                                      more data
+ */
+enum status_code i2c_master_write_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	module->send_stop = false;
+	module->send_nack = true;
+	
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Sends stop condition on bus
+ *
+ * Sends a stop condition on bus.
+ *
+ * \note This function can only be used after the
+ *       \ref i2c_master_write_packet_wait_no_stop function. If a stop condition
+ *       is to be sent after a read, the \ref i2c_master_read_packet_wait
+ *       function must be used.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void i2c_master_send_stop(struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Send stop command */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+}
+
+/**
+ * \brief Sends nack signal on bus
+ *
+ * Sends a nack signal on bus.
+ *
+ * \note This function can only be used after the
+ *       \ref i2c_master_write_packet_wait_no_nack function,
+ *        or \ref i2c_master_read_byte function.
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void i2c_master_send_nack(struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Send nack signal */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+}
+
+/**
+ * \brief Reads one byte data from slave
+ *
+ * \param[in,out]  module  Pointer to software module struct
+ * \param[out]     byte    Read one byte data to slave
+ *
+ * \return Status of reading byte.
+ * \retval STATUS_OK                    One byte was read successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_read_byte(
+		struct i2c_master_module *const module,
+		uint8_t *byte)
+{
+  	enum status_code tmp_status;
+  	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	/* Write byte to slave. */
+	_i2c_master_wait_for_sync(module);
+	*byte = i2c_module->DATA.reg;
+	/* Wait for response. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+	
+	return tmp_status;
+}
+
+/**
+ * \brief Write one byte data to slave
+ *
+ * \param[in,out]  module  Pointer to software module struct
+ * \param[in]      byte    Send one byte data to slave
+ *
+ * \return Status of writing byte.
+ * \retval STATUS_OK                    One byte was write successfully
+ * \retval STATUS_ERR_TIMEOUT           If no response was given within
+ *                                      specified timeout period
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ */
+enum status_code i2c_master_write_byte(
+		struct i2c_master_module *const module,
+		uint8_t byte)
+{
+  	enum status_code tmp_status;
+  	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	
+	/* Write byte to slave. */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->DATA.reg = byte;
+	/* Wait for response. */
+	tmp_status = _i2c_master_wait_for_bus(module);
+	return tmp_status;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c
new file mode 100644
index 0000000000..07c892a036
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c
@@ -0,0 +1,670 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 I2C Master Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_master_interrupt.h"
+
+/**
+ * \internal
+ * Read next data. Used by interrupt handler to get next data byte from slave.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_read(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Find index to save next value in buffer */
+	uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
+
+	module->buffer_remaining--;
+
+	if (!module->buffer_remaining) {
+		/* Send nack */
+	  	if (module->send_nack)
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+		if (module->send_stop) {
+			/* Send stop condition */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		} else {
+		  	_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(1);
+		}
+	} else {
+		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	}
+
+	/* Read byte from slave and put in buffer */
+	_i2c_master_wait_for_sync(module);
+	module->buffer[buffer_index] = i2c_module->DATA.reg;
+}
+
+/**
+ * \internal
+ *
+ * Write next data. Used by interrupt handler to send next data byte to slave.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_write(struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Check for ack from slave */
+	if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+	{
+		/* Set status */
+		module->status = STATUS_ERR_OVERFLOW;
+		/* Do not write more data */
+		return;
+	}
+
+	/* Find index to get next byte in buffer */
+	uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
+
+	module->buffer_remaining--;
+
+	/* Write byte from buffer to slave */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->DATA.reg = module->buffer[buffer_index];
+}
+
+/**
+ * \internal
+ * Acts on slave address response. Checks for errors concerning master->slave
+ * handshake.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_async_address_response(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Check for error. Ignore bus-error; workaround for bus state stuck in
+	 * BUSY.
+	 */
+	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
+	{
+		/* Clear write interrupt flag */
+		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
+
+		/* Check arbitration */
+		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
+			/* Return busy */
+			module->status = STATUS_ERR_PACKET_COLLISION;
+		}
+	}
+
+	if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+		/* Return bad address value */
+		module->status           = STATUS_ERR_BAD_ADDRESS;
+		module->buffer_remaining = 0;
+
+		if (module->send_stop) {
+			/* Send stop condition */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		}
+	}
+
+	module->buffer_length = module->buffer_remaining;
+
+	/* Check for status OK. */
+	if (module->status == STATUS_BUSY) {
+		/* Call function based on transfer direction. */
+		if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+			_i2c_master_write(module);
+		} else {
+			_i2c_master_read(module);
+		}
+	}
+}
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ *
+ * To enable the callback, the \ref i2c_master_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback       Pointer to the function desired for the
+ *                                specified callback
+ * \param[in]      callback_type  Callback type to register
+ */
+void i2c_master_register_callback(
+		struct i2c_master_module *const module,
+		const i2c_master_callback_t callback,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(callback);
+
+	/* Register callback */
+	module->callbacks[callback_type] = callback;
+
+	/* Set corresponding bit to set callback as registered */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ */
+void i2c_master_unregister_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Register callback */
+	module->callbacks[callback_type] = NULL;
+
+	/* Clear corresponding bit to set callback as unregistered */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal
+ * Starts a read bytes operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_read_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_READ;
+	module->status             = STATUS_BUSY;
+	module->send_stop = false;
+	module->send_nack = false;
+	
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Starts a read packet operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+static enum status_code _i2c_master_read_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_READ;
+	module->status             = STATUS_BUSY;
+
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	/* Set address and direction bit. Will send start command on bus */
+	i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a read packet operation
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus. This is the non-blocking equivalent of \ref i2c_master_read_packet_wait.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_read_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we send STOP */
+	module->send_stop = true;
+	module->send_nack = true;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a read packet operation without sending a STOP condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
+ * sending a stop condition, thus retaining ownership of the bus when done.
+ * To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If reading was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another operation
+ */
+enum status_code i2c_master_read_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we don't send STOP */
+	module->send_stop = false;
+	module->send_nack = true;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a read packet operation without sending a NACK signal and a 
+ * STOP condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
+ * sending a nack and a stop condition, thus retaining ownership of the bus when done.
+ * To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If reading was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another operation
+ */
+enum status_code i2c_master_read_packet_job_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we don't send STOP */
+	module->send_stop = false;
+	module->send_nack = false;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts a write bytes operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting write I<SUP>2</SUP>C bytes.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_write_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_WRITE;
+	module->status             = STATUS_BUSY;
+	module->send_stop = false;
+	module->send_nack = false;
+	
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal Initiates a write packet operation
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK   If writing was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another transfer
+ */
+static enum status_code _i2c_master_write_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_WRITE;
+	module->status             = STATUS_BUSY;
+
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	/* Set address and direction bit, will send start command on bus */
+	i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a write packet operation
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C
+ * bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_write_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with another job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we send STOP at end*/
+	module->send_stop = true;
+	module->send_nack = true;
+	/* Start write operation */
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a write packet operation without sending a STOP condition when done
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * without sending a stop condition, thus retaining ownership of the bus when
+ * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition or sending
+ * a stop with the \ref i2c_master_send_stop function must be performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another
+ */
+enum status_code i2c_master_write_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with another job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Do not send stop condition when done */
+	module->send_stop = false;
+	module->send_nack = true;
+	/* Start write operation */
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Interrupt handler for I<SUP>2</SUP>C master.
+ *
+ * \param[in] instance  SERCOM instance that triggered the interrupt
+ */
+void _i2c_master_interrupt_handler(
+		uint8_t instance)
+{
+	/* Get software module for callback handling */
+	struct i2c_master_module *module =
+			(struct i2c_master_module*)_sercom_instances[instance];
+
+	Assert(module);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Combine callback registered and enabled masks */
+	uint8_t callback_mask = module->enabled_callback &
+			module->registered_callback;
+
+	/* Check if the module should respond to address ack */
+	if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
+		/* Call function for address response */
+		_i2c_master_async_address_response(module);
+
+	/* Check if buffer write is done */
+	} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+			(module->status == STATUS_BUSY) &&
+			(module->transfer_direction == I2C_TRANSFER_WRITE)) {
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg =
+				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+
+		module->buffer_length = 0;
+		module->status        = STATUS_OK;
+
+		if (module->send_stop) {
+			/* Send stop condition */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		} else {
+			/* Clear write interrupt flag */
+			i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+		}
+		if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
+			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+		}
+
+	/* Continue buffer write/read */
+	} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
+		/* Check that bus ownership is not lost */
+		if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
+			module->status = STATUS_ERR_PACKET_COLLISION;
+		} else if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+			_i2c_master_write(module);
+		} else {
+			_i2c_master_read(module);
+		}
+	}
+
+	/* Check if read buffer transfer is complete */
+	if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+			(module->status == STATUS_BUSY) &&
+			(module->transfer_direction == I2C_TRANSFER_READ)) {
+
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg =
+				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+		module->buffer_length = 0;
+		module->status        = STATUS_OK;
+
+		/* Call appropriate callback if enabled and registered */
+		if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
+				&& (module->transfer_direction == I2C_TRANSFER_READ)) {
+			module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
+		} else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
+				&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
+			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+		}
+	}
+
+	/* Check for error */
+	if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) {
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
+				SERCOM_I2CM_INTENCLR_SB;
+
+		module->buffer_length = 0;
+		module->buffer_remaining = 0;
+
+		/* Send nack and stop command unless arbitration is lost */
+		if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
+				module->send_stop) {
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
+					SERCOM_I2CM_CTRLB_CMD(3);
+		}
+
+		/* Call error callback if enabled and registered */
+		if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) {
+			module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c
new file mode 100644
index 0000000000..c403479a38
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c
@@ -0,0 +1,693 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 I2C Slave Driver
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_slave.h"
+#if I2C_SLAVE_CALLBACK_MODE == true
+#  include "i2c_slave_interrupt.h"
+#endif
+
+/**
+ * \internal Sets configuration to module
+ *
+ * \param[out] module  Pointer to software module structure
+ * \param[in]  config  Configuration structure with configurations to set
+ *
+ * \return Status of setting configuration.
+ * \retval STATUS_OK                       Module was configured correctly
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  If setting other GCLK generator than
+ *                                         previously set
+ */
+static enum status_code _i2c_slave_set_config(
+		struct i2c_slave_module *const module,
+		const struct i2c_slave_config *const config)
+{
+	uint32_t tmp_ctrla;
+
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(config);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+	Sercom *const sercom_hw = module->hw;
+
+	module->buffer_timeout = config->buffer_timeout;
+
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+
+	uint32_t pad0 = config->pinmux_pad0;
+	uint32_t pad1 = config->pinmux_pad1;
+
+	/* SERCOM PAD0 - SDA */
+	if (pad0 == PINMUX_DEFAULT) {
+		pad0 = _sercom_get_default_pad(sercom_hw, 0);
+	}
+	pin_conf.mux_position = pad0 & 0xFFFF;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+	system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+	/* SERCOM PAD1 - SCL */
+	if (pad1 == PINMUX_DEFAULT) {
+		pad1 = _sercom_get_default_pad(sercom_hw, 1);
+	}
+	pin_conf.mux_position = pad1 & 0xFFFF;
+	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+	system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+	/* Prepare config to write to register CTRLA */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY;
+	} else {
+		tmp_ctrla = 0;
+	}
+
+	tmp_ctrla |= config->sda_hold_time |
+			(config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUT_Pos);
+
+	i2c_hw->CTRLA.reg |= tmp_ctrla;
+
+	/* Set CTRLB configuration */
+	i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode;
+
+	i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos |
+			config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos |
+			config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the requested I<SUP>2</SUP>C hardware module
+ *
+ * Initializes the SERCOM I<SUP>2</SUP>C slave device requested and sets the provided
+ * software module struct.  Run this function before any further use of
+ * the driver.
+ *
+ * \param[out] module  Pointer to software module struct
+ * \param[in]  hw      Pointer to the hardware instance
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK                       Module initiated correctly
+ * \retval STATUS_ERR_DENIED               If module is enabled
+ * \retval STATUS_BUSY                     If module is busy resetting
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  If setting other GCLK generator than
+ *                                         previously set
+ */
+enum status_code i2c_slave_init(
+		struct i2c_slave_module *const module,
+		Sercom *const hw,
+		const struct i2c_slave_config *const config)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize software module */
+	module->hw = hw;
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Check if module is enabled. */
+	if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if reset is in progress. */
+	if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) {
+		return STATUS_BUSY;
+	}
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+	/* Turn on module in PM */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Get sercom instance index. */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+
+	/* Save software module in interrupt handler. */
+	_sercom_set_handler(instance_index, _i2c_slave_interrupt_handler);
+
+	/* Save software module. */
+	_sercom_instances[instance_index] = module;
+
+	/* Initialize values in module. */
+	module->registered_callback = 0;
+	module->enabled_callback = 0;
+	module->buffer_length = 0;
+	module->nack_on_address = config->enable_nack_on_address;
+#endif
+
+	/* Set SERCOM module to operate in I2C slave mode. */
+	i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE;
+
+	/* Set config and return status. */
+	return _i2c_slave_set_config(module, config);
+}
+
+/**
+ * \brief Resets the hardware module
+ *
+ * This will reset the module to hardware defaults.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+void i2c_slave_reset(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Reset module instance. */
+	module->registered_callback = 0;
+	module->enabled_callback = 0;
+	module->buffer_length = 0;
+	module->buffer_remaining = 0;
+	module->buffer = NULL;
+#endif
+
+	/* Disable module */
+	i2c_slave_disable(module);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Clear all pending interrupts. */
+	system_interrupt_enter_critical_section();
+	system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+	system_interrupt_leave_critical_section();
+#endif
+
+	/* Wait for sync. */
+	_i2c_slave_wait_for_sync(module);
+
+	/* Reset module. */
+	i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST;
+}
+
+/**
+ * \internal Waits for answer on bus
+ *
+ * \param[in]  module  Pointer to software module structure
+ *
+ * \return Status of bus.
+ * \retval STATUS_OK           If given response from slave device
+ * \retval STATUS_ERR_TIMEOUT  If no response was given within specified timeout
+ *                             period
+ */
+static enum status_code _i2c_slave_wait_for_bus(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Wait for reply. */
+	uint16_t timeout_counter = 0;
+	while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) &&
+			(!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) &&
+			(!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) {
+
+		/* Check timeout condition. */
+		if (++timeout_counter >= module->buffer_timeout) {
+			return STATUS_ERR_TIMEOUT;
+		}
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Writes a packet to the master
+ *
+ * Writes a packet to the master. This will wait for the master to issue
+ * a request.
+ *
+ * \param[in]  module  Pointer to software module structure
+ * \param[in]  packet  Packet to write to master
+ *
+ * \return Status of packet write.
+ * \retval STATUS_OK                Packet was written successfully
+ * \retval STATUS_ERR_DENIED        Start condition not received, another
+ *                                  interrupt flag is set
+ * \retval STATUS_ERR_IO            There was an error in the previous transfer
+ * \retval STATUS_ERR_BAD_FORMAT    Master wants to write data
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) was provided
+ * \retval STATUS_ERR_BUSY          The I<SUP>2</SUP>C module is busy with a job
+ * \retval STATUS_ERR_ERR_OVERFLOW  Master NACKed before entire packet was
+ *                                  transferred
+ * \retval STATUS_ERR_TIMEOUT       No response was given within the timeout
+ *                                  period
+ */
+enum status_code i2c_slave_write_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	uint16_t length = packet->data_length;
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Check if the module is busy with a job or AMATCH is enabled */
+	if (module->buffer_remaining > 0 ||
+			(i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	enum status_code status;
+	/* Wait for master to send address packet */
+	status = _i2c_slave_wait_for_bus(module);
+
+	if (status != STATUS_OK) {
+			/* Timeout, return */
+			return status;
+	}
+	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		/* Not address interrupt, something is wrong */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if there was an error in last transfer */
+	if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+			SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
+		return STATUS_ERR_IO;
+	}
+
+	/* Check direction */
+	if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+		/* Write request from master, send NACK and return, workaround 13574*/
+		_i2c_slave_set_ctrlb_ackact(module, false);
+		_i2c_slave_set_ctrlb_cmd3(module);
+		return STATUS_ERR_BAD_FORMAT;
+	}
+
+	/* Read request from master, ACK address, workaround 13574 */
+	_i2c_slave_set_ctrlb_ackact(module, true);
+	_i2c_slave_set_ctrlb_cmd3(module);
+
+	uint16_t i = 0;
+
+	/* Wait for data interrupt */
+	status = _i2c_slave_wait_for_bus(module);
+	if (status != STATUS_OK) {
+			/* Timeout, return */
+			return status;
+	}
+
+	while (length--) {
+		/* Write data */
+		_i2c_slave_wait_for_sync(module);
+		i2c_hw->DATA.reg = packet->data[i++];
+
+		/* Wait for response from master */
+		status = _i2c_slave_wait_for_bus(module);
+
+		if (status != STATUS_OK) {
+			/* Timeout, return */
+			return status;
+		}
+
+		if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK &&
+				length !=0) {
+			/* NACK from master, abort */
+			/* Release line */
+			i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+			return STATUS_ERR_OVERFLOW;
+			/* Workaround: PIF will probably not be set, ignore */
+		}
+		/* ACK from master, continue writing */
+	}
+
+	/* Release line */
+	i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Reads a packet from the master
+ *
+ * Reads a packet from the master. This will wait for the master to issue a
+ * request.
+ *
+ * \param[in]  module  Pointer to software module structure
+ * \param[out] packet  Packet to read from master
+ *
+ * \return Status of packet read.
+ * \retval STATUS_OK                Packet was read successfully
+ * \retval STATUS_ABORTED           Master sent stop condition or repeated
+ *                                  start before specified length of bytes
+ *                                  was received
+ * \retval STATUS_ERR_IO            There was an error in the previous transfer
+ * \retval STATUS_ERR_DENIED        Start condition not received, another
+ *                                  interrupt flag is set
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) was provided
+ * \retval STATUS_ERR_BUSY          The I<SUP>2</SUP>C module is busy with a job
+ * \retval STATUS_ERR_BAD_FORMAT    Master wants to read data
+ * \retval STATUS_ERR_ERR_OVERFLOW  Last byte received overflows buffer
+ */
+enum status_code i2c_slave_read_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	uint16_t length = packet->data_length;
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Check if the module is busy with a job or AMATCH is enabled */
+	if (module->buffer_remaining > 0 ||
+			(i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	enum status_code status;
+
+	/* Wait for master to send address packet */
+	status = _i2c_slave_wait_for_bus(module);
+	if (status != STATUS_OK) {
+		/* Timeout, return */
+		return status;
+	}
+
+	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		/* Not address interrupt, something is wrong */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if there was an error in the last transfer */
+	if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+			SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
+		return STATUS_ERR_IO;
+	}
+	/* Check direction */
+	if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+		/* Read request from master, send NACK and return, workaround 13574 */
+		_i2c_slave_set_ctrlb_ackact(module, false);
+		_i2c_slave_set_ctrlb_cmd3(module);
+		return STATUS_ERR_BAD_FORMAT;
+	}
+
+	/* Write request from master, ACK address, workaround 13574 */
+	_i2c_slave_set_ctrlb_ackact(module, true);
+	_i2c_slave_set_ctrlb_cmd3(module);
+
+	uint16_t i = 0;
+	while (length--) {
+
+		/* Wait for next byte or stop condition */
+		status = _i2c_slave_wait_for_bus(module);
+		if (status != STATUS_OK) {
+			/* Timeout, return */
+			return status;
+		}
+
+		if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) ||
+				i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
+			/* Master sent stop condition, or repeated start, read done */
+			/* Clear stop flag */
+			i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+			return STATUS_ABORTED;
+		}
+
+		/* Read data */
+		_i2c_slave_wait_for_sync(module);
+		packet->data[i++] = i2c_hw->DATA.reg;
+
+	}
+
+	/* Packet read done, wait for packet to NACK, Stop or repeated start */
+	status = _i2c_slave_wait_for_bus(module);
+
+	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
+		/* Buffer is full, send NACK */
+		_i2c_slave_set_ctrlb_ackact(module, false);
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+	}
+	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
+		/* Clear stop flag */
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Waits for a start condition on the bus
+ *
+ * \note This function is only available for 7-bit slave addressing.
+ *
+ * Waits for the master to issue a start condition on the bus.
+ * \note This function does not check for errors in the last transfer,
+ * this will be discovered when reading or writing.
+ *
+ * \param[in]  module  Pointer to software module structure
+ *
+ * \return Direction of the current transfer, when in slave mode.
+ * \retval I2C_SLAVE_DIRECTION_NONE   No request from master within timeout
+ *                                    period
+ * \retval I2C_SLAVE_DIRECTION_READ   Write request from master
+ * \retval I2C_SLAVE_DIRECTION_WRITE  Read request from master
+ */
+enum i2c_slave_direction i2c_slave_get_direction_wait(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	enum status_code status;
+
+	/* Wait for address interrupt */
+	status = _i2c_slave_wait_for_bus(module);
+
+	if (status != STATUS_OK) {
+		/* Timeout, return */
+		return I2C_SLAVE_DIRECTION_NONE;
+	}
+
+	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+		/* Not address interrupt, something is wrong */
+		return I2C_SLAVE_DIRECTION_NONE;
+	}
+
+	/* Check direction */
+	if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+		/* Read request from master */
+		return I2C_SLAVE_DIRECTION_WRITE;
+	} else {
+		/* Write request from master */
+		return I2C_SLAVE_DIRECTION_READ;
+	}
+}
+
+/**
+ * \brief Retrieves the current module status
+ *
+ * Checks the status of the module and returns it as a bitmask of status
+ * flags.
+ *
+ * \param[in] module      Pointer to the I<SUP>2</SUP>C slave software device struct
+ *
+ * \return Bitmask of status flags.
+ *
+ * \retval I2C_SLAVE_STATUS_ADDRESS_MATCH   A valid address has been received
+ * \retval I2C_SLAVE_STATUS_DATA_READY      A I<SUP>2</SUP>C slave byte transmission is
+ *                                          successfully completed
+ * \retval I2C_SLAVE_STATUS_STOP_RECEIVED   A stop condition is detected for a
+ *                                          transaction being processed
+ * \retval I2C_SLAVE_STATUS_CLOCK_HOLD      The slave is holding the SCL line
+ *                                          low
+ * \retval I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT An SCL low time-out has occurred
+ * \retval I2C_SLAVE_STATUS_REPEATED_START  Indicates a repeated start, only
+ *                                          valid if \ref
+ *                                          I2C_SLAVE_STATUS_ADDRESS_MATCH is
+ *                                          set
+ * \retval I2C_SLAVE_STATUS_RECEIVED_NACK   The last data packet sent was not
+ *                                          acknowledged
+ * \retval I2C_SLAVE_STATUS_COLLISION       The I<SUP>2</SUP>C slave was not able to
+ *                                          transmit a high data or NACK bit
+ * \retval I2C_SLAVE_STATUS_BUS_ERROR       An illegal bus condition has
+ *                                          occurred on the bus
+ */
+uint32_t i2c_slave_get_status(
+		struct i2c_slave_module *const module)
+{
+	 /* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	uint8_t intflags = i2c_hw->INTFLAG.reg;
+	uint8_t status = i2c_hw->STATUS.reg;
+	uint32_t status_flags = 0;
+
+	/* Check Address Match flag */
+	if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) {
+		status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH;
+	}
+	/* Check Data Ready flag */
+	if (intflags & SERCOM_I2CS_INTFLAG_DRDY) {
+		status_flags |= I2C_SLAVE_STATUS_DATA_READY;
+	}
+	/* Check Stop flag */
+	if (intflags & SERCOM_I2CS_INTFLAG_PREC) {
+		status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED;
+	}
+	/* Check Clock Hold */
+	if (status & SERCOM_I2CS_STATUS_CLKHOLD) {
+		status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD;
+	}
+	/* Check SCL Low Timeout */
+	if (status & SERCOM_I2CS_STATUS_LOWTOUT) {
+		status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT;
+	}
+	/* Check Repeated Start */
+	if (status & SERCOM_I2CS_STATUS_SR) {
+		status_flags |= I2C_SLAVE_STATUS_REPEATED_START;
+	}
+	/* Check Received Not Acknowledge */
+	if (status & SERCOM_I2CS_STATUS_RXNACK) {
+		status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK;
+	}
+	/* Check Transmit Collision */
+	if (status & SERCOM_I2CS_STATUS_COLL) {
+		status_flags |= I2C_SLAVE_STATUS_COLLISION;
+	}
+	/* Check Bus Error */
+	if (status & SERCOM_I2CS_STATUS_BUSERR) {
+		status_flags |= I2C_SLAVE_STATUS_BUS_ERROR;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag
+ *
+ * Clears the given status flag of the module.
+ *
+ * \note Not all status flags can be cleared.
+ *
+ * \param[in] module         Pointer to the I<SUP>2</SUP>C software device struct
+ * \param[in] status_flags   Bit mask of status flags to clear
+ *
+ */
+void i2c_slave_clear_status(
+		struct i2c_slave_module *const module,
+		uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Clear Address Match flag */
+	if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) {
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+	}
+	/* Clear Data Ready flag */
+	if (status_flags & I2C_SLAVE_STATUS_DATA_READY) {
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+	}
+	/* Clear Stop flag */
+	if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) {
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+	}
+	/* Clear SCL Low Timeout */
+	if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) {
+		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+	}
+	/* Clear Transmit Collision */
+	if (status_flags & I2C_SLAVE_STATUS_COLLISION) {
+		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+	}
+	/* Clear Bus Error */
+	if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) {
+		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c
new file mode 100644
index 0000000000..29d222bd2c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c
@@ -0,0 +1,434 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 I2C Slave Interrupt Driver
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "i2c_slave_interrupt.h"
+
+/**
+ * \brief Enables sending of NACK on address match
+ *
+ * Enables sending of NACK on address match, thus discarding
+ * any incoming transaction.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+void i2c_slave_enable_nack_on_address(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+
+	module->nack_on_address = true;
+}
+
+/**
+ * \brief Disables sending NACK on address match
+ *
+ * Disables sending of NACK on address match, thus
+ * acknowledging incoming transactions.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+void i2c_slave_disable_nack_on_address(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+
+	module->nack_on_address = false;
+}
+
+/**
+ * \internal
+ * Reads next data. Used by interrupt handler to get next data byte from master.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_slave_read(
+		struct i2c_slave_module *const module)
+{
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Read byte from master and put in buffer. */
+	*(module->buffer++) = i2c_hw->DATA.reg;
+
+	/*Decrement remaining buffer length */
+	module->buffer_remaining--;
+}
+
+/**
+ * \internal
+ * Writes next data. Used by interrupt handler to send next data byte to master.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_slave_write(
+		struct i2c_slave_module *const module)
+{
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Write byte from buffer to master */
+	i2c_hw->DATA.reg = *(module->buffer++);
+
+	/*Decrement remaining buffer length */
+	module->buffer_remaining--;
+}
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type. To enable the callback, the
+ * \ref i2c_slave_enable_callback function must be used.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback       Pointer to the function desired for the
+ *                               specified callback
+ * \param[in]     callback_type  Callback type to register
+ */
+void i2c_slave_register_callback(
+		struct i2c_slave_module *const module,
+		i2c_slave_callback_t callback,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(callback);
+
+	/* Register callback. */
+	module->callbacks[callback_type] = callback;
+
+	/* Set corresponding bit to set callback as initiated. */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * Removes the currently registered callback for the given callback
+ * type.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback_type  Callback type to unregister
+ */
+void i2c_slave_unregister_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Register callback. */
+	module->callbacks[callback_type] = NULL;
+
+	/* Set corresponding bit to set callback as initiated. */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Initiates a reads packet operation
+ *
+ * Reads a data packet from the master. A write request must be initiated by
+ * the master before the packet can be read.
+ *
+ * The \ref I2C_SLAVE_CALLBACK_WRITE_REQUEST callback can be used to call this
+ * function.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting asynchronously reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_slave_read_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy doing async operation. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Save packet to software module. */
+	module->buffer           = packet->data;
+	module->buffer_remaining = packet->data_length;
+	module->buffer_length    = packet->data_length;
+	module->status           = STATUS_BUSY;
+
+	/* Enable interrupts */
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+	i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
+			SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
+
+	/* Read will begin when master initiates the transfer */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a write packet operation
+ *
+ * Writes a data packet to the master. A read request must be initiated by
+ * the master before the packet can be written.
+ *
+ * The \ref I2C_SLAVE_CALLBACK_READ_REQUEST callback can be used to call this
+ * function.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If writing was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another transfer
+ */
+enum status_code i2c_slave_write_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy doing async operation. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Save packet to software module. */
+	module->buffer           = packet->data;
+	module->buffer_remaining = packet->data_length;
+	module->buffer_length    = packet->data_length;
+	module->status           = STATUS_BUSY;
+
+	/* Enable interrupts */
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+	i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
+			SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal Interrupt handler for I<SUP>2</SUP>C slave
+ *
+ * \param[in] instance Sercom instance that triggered the interrupt
+ */
+void _i2c_slave_interrupt_handler(
+		uint8_t instance)
+{
+	/* Get software module for callback handling. */
+	struct i2c_slave_module *module =
+			(struct i2c_slave_module*)_sercom_instances[instance];
+
+	Assert(module);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Combine callback registered and enabled masks. */
+	uint8_t callback_mask =
+			module->enabled_callback & module->registered_callback;
+
+
+	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
+	/* Address match */
+		/* Check if last transfer is done - repeated start */
+		if (module->buffer_length != module->buffer_remaining &&
+				module->transfer_direction == I2C_TRANSFER_WRITE) {
+
+			module->status = STATUS_OK;
+			module->buffer_length = 0;
+			module->buffer_remaining = 0;
+
+			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))) {
+				module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+			}
+		} else if (module->buffer_length != module->buffer_remaining &&
+				module->transfer_direction == I2C_TRANSFER_READ) {
+			module->status = STATUS_OK;
+			module->buffer_length = 0;
+			module->buffer_remaining = 0;
+
+			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))) {
+				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+			}
+		}
+
+		if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+				SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
+			/* An error occurred in last packet transfer */
+			module->status = STATUS_ERR_IO;
+
+			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER))) {
+				module->callbacks[I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER](module);
+			}
+		}
+		if (module->nack_on_address) {
+			/* NACK address, workaround 13574 */
+			_i2c_slave_set_ctrlb_ackact(module, false);
+		} else if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR) {
+			/* Set transfer direction in module instance */
+			module->transfer_direction = I2C_TRANSFER_READ;
+
+			/* Read request from master */
+			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) {
+				module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
+			}
+
+			if (module->buffer_length == 0) {
+				/* Data buffer not set up, NACK address, workaround 13574*/
+				_i2c_slave_set_ctrlb_ackact(module, false);
+			} else {
+				/* ACK address, workaround 13574 */
+				_i2c_slave_set_ctrlb_ackact(module, true);
+			}
+		} else {
+			/* Set transfer direction in dev inst */
+			module->transfer_direction = I2C_TRANSFER_WRITE;
+
+			/* Write request from master */
+			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)) {
+				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
+			}
+
+			if (module->buffer_length == 0) {
+				/* Data buffer not set up, NACK address, workaround 13574 */
+				_i2c_slave_set_ctrlb_ackact(module, false);
+			} else {
+				/* ACK address, workaround 13574 */
+				_i2c_slave_set_ctrlb_ackact(module, true);
+			}
+		}
+
+		/* ACK or NACK address, Workaround 13574 */
+		_i2c_slave_set_ctrlb_cmd3(module);
+
+		/* ACK next incoming packet, workaround 13574 */
+		_i2c_slave_set_ctrlb_ackact(module, true);
+
+	} else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
+		/* Stop condition on bus - current transfer done */
+
+		/* Clear Stop interrupt */
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+
+		/* Disable interrupts */
+		i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_DRDY;
+
+		if (!((module->enabled_callback & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
+				|| (module->enabled_callback == (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)))) {
+			/* Disable address match if read/write request is not enabled */
+			i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+		}
+
+		if (!(module->status == STATUS_ERR_OVERFLOW || module->status == STATUS_ERR_IO)) {
+			module->status = STATUS_OK;
+			module->buffer_length = 0;
+			module->buffer_remaining = 0;
+
+			/* Call appropriate callback if enabled and registered */
+			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))
+					&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
+				/* Read from master complete */
+				module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+			} else if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))
+					&& (module->transfer_direction == I2C_TRANSFER_READ)) {
+				/* Write to master complete */
+				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+			}
+					}
+	} else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
+		/* Check if buffer is full, or NACK from master */
+		if (module->buffer_remaining <= 0 ||
+				(module->transfer_direction == I2C_TRANSFER_READ &&
+				(module->buffer_length > module->buffer_remaining) &&
+				(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK))) {
+
+			module->buffer_remaining = 0;
+			module->buffer_length = 0;
+
+			if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+				/* Buffer is full, send NACK, workaround 13574 */
+				_i2c_slave_set_ctrlb_ackact(module, false);
+				i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+
+				/* Set status, new character in DATA register will overflow
+				 * buffer */
+				module->status = STATUS_ERR_OVERFLOW;
+
+				if (callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR)) {
+					/* Read complete */
+					module->callbacks[I2C_SLAVE_CALLBACK_ERROR](module);
+				}
+			} else {
+				/* Release SCL and wait for new start condition */
+				_i2c_slave_set_ctrlb_ackact(module, false);
+				i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+
+				/* Transfer successful */
+				module->status = STATUS_OK;
+
+				/* Disable interrupts */
+				i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_DRDY;
+			}
+
+		/* Continue buffer write/read */
+		} else if (module->buffer_length > 0 && module->buffer_remaining > 0) {
+			/* Call function based on transfer direction */
+			if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+				_i2c_slave_read(module);
+			} else {
+				_i2c_slave_write(module);
+			}
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave.h
new file mode 100644
index 0000000000..011104f04d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave.h
@@ -0,0 +1,753 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Slave Driver
+ *
+ * Copyright (c) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2C_SLAVE_H_INCLUDED
+#define I2C_SLAVE_H_INCLUDED
+
+#include "i2c_common.h"
+#include <sercom.h>
+#include <pinmux.h>
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+#  include <sercom_interrupt.h>
+#endif
+
+#ifndef PINMUX_DEFAULT
+#  define PINMUX_DEFAULT 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_i2c_group
+ *
+ * @{
+ *
+ */
+
+/**
+ * \name I2C Slave Status Flags
+ *
+ * I<SUP>2</SUP>C slave status flags, returned by \ref i2c_slave_get_status() and cleared
+ * by \ref i2c_slave_clear_status().
+ * @{
+ */
+
+/** Address Match.
+ * \note Should only be cleared internally by driver.
+ */
+#define I2C_SLAVE_STATUS_ADDRESS_MATCH     (1UL << 0)
+/** Data Ready. */
+#define I2C_SLAVE_STATUS_DATA_READY        (1UL << 1)
+/** Stop Received. */
+#define I2C_SLAVE_STATUS_STOP_RECEIVED     (1UL << 2)
+/** Clock Hold.
+ * \note Cannot be cleared, only valid when I2C_SLAVE_STATUS_ADDRESS_MATCH is
+ * set.
+ */
+#define I2C_SLAVE_STATUS_CLOCK_HOLD        (1UL << 3)
+/** SCL Low Timeout. */
+#define I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT   (1UL << 4)
+/** Repeated Start.
+ * \note Cannot be cleared, only valid when I2C_SLAVE_STATUS_ADDRESS_MATCH is
+ * set.
+ */
+#define I2C_SLAVE_STATUS_REPEATED_START    (1UL << 5)
+/** Received not acknowledge.
+ * \note Cannot be cleared.
+ */
+#define I2C_SLAVE_STATUS_RECEIVED_NACK     (1UL << 6)
+/** Transmit Collision. */
+#define I2C_SLAVE_STATUS_COLLISION         (1UL << 7)
+/** Bus error. */
+#define I2C_SLAVE_STATUS_BUS_ERROR         (1UL << 8)
+
+/** @} */
+
+/**
+ * \brief I<SUP>2</SUP>C slave packet for read/write
+ *
+ * Structure to be used when transferring I<SUP>2</SUP>C slave packets.
+ */
+struct i2c_slave_packet {
+	/** Length of data array */
+	uint16_t data_length;
+	/** Data array containing all data to be transferred */
+	uint8_t *data;
+};
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /**
+ * \brief Callback types
+ *
+ * The available callback types for the I<SUP>2</SUP>C slave.
+ */
+enum i2c_slave_callback {
+	/** Callback for packet write complete */
+	I2C_SLAVE_CALLBACK_WRITE_COMPLETE,
+	/** Callback for packet read complete */
+	I2C_SLAVE_CALLBACK_READ_COMPLETE,
+	/**
+	 * Callback for read request from master - can be used to
+	 * issue a write
+	 */
+	I2C_SLAVE_CALLBACK_READ_REQUEST,
+	/**
+	 * Callback for write request from master - can be used to issue a read
+	 */
+	I2C_SLAVE_CALLBACK_WRITE_REQUEST,
+	/** Callback for error */
+	I2C_SLAVE_CALLBACK_ERROR,
+	/**
+	 * Callback for error in last transfer. Discovered on a new address
+	 * interrupt.
+	 */
+	I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_I2C_SLAVE_CALLBACK_N,
+#  endif
+};
+
+#  if !defined(__DOXYGEN__)
+/** Software module prototype */
+struct i2c_slave_module;
+
+/** Callback type */
+typedef void (*i2c_slave_callback_t)(
+		struct i2c_slave_module *const module);
+#  endif
+#endif
+
+/**
+ * \brief Enum for the possible SDA hold times with respect to the negative
+ * edge of SCL
+ *
+ * Enum for the possible SDA hold times with respect to the negative edge
+ * of SCL.
+ */
+enum i2c_slave_sda_hold_time {
+	/** SDA hold time disabled */
+	I2C_SLAVE_SDA_HOLD_TIME_DISABLED =
+			((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((0) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+	/** SDA hold time 50ns - 100ns */
+	I2C_SLAVE_SDA_HOLD_TIME_50NS_100NS =
+			((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((1) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+	/** SDA hold time 300ns - 600ns */
+	I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS =
+			((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((2) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+	/** SDA hold time 400ns - 800ns */
+	I2C_SLAVE_SDA_HOLD_TIME_400NS_800NS =
+			((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+};
+
+/**
+ * \brief Enum for the possible address modes
+ *
+ * Enum for the possible address modes.
+ */
+enum i2c_slave_address_mode {
+	/** Address match on address_mask used as a mask to address */
+	I2C_SLAVE_ADDRESS_MODE_MASK = SERCOM_I2CS_CTRLB_AMODE(0),
+	/** Address math on both address and address_mask */
+	I2C_SLAVE_ADDRESS_MODE_TWO_ADDRESSES = SERCOM_I2CS_CTRLB_AMODE(1),
+	/**
+	 * Address match on range of addresses between and including address and
+	 * address_mask
+	 */
+	I2C_SLAVE_ADDRESS_MODE_RANGE = SERCOM_I2CS_CTRLB_AMODE(2),
+};
+
+/**
+ * \brief Enum for the direction of a request
+ *
+ * Enum for the direction of a request.
+ */
+enum i2c_slave_direction {
+	/** Read */
+	I2C_SLAVE_DIRECTION_READ,
+	/** Write */
+	I2C_SLAVE_DIRECTION_WRITE,
+	/** No direction */
+	I2C_SLAVE_DIRECTION_NONE,
+};
+
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+/**
+ * \brief Enum for the transfer speed
+ *
+ * Enum for the transfer speed.
+ */
+enum i2c_slave_transfer_speed {
+	/** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */
+	I2C_SLAVE_SPEED_STANDARD_AND_FAST = SERCOM_I2CS_CTRLA_SPEED(0),
+	/** Fast-mode Plus (Fm+) up to 1MHz */
+	I2C_SLAVE_SPEED_FAST_MODE_PLUS = SERCOM_I2CS_CTRLA_SPEED(1),
+	/** High-speed mode (Hs-mode) up to 3.4MHz */
+	I2C_SLAVE_SPEED_HIGH_SPEED = SERCOM_I2CS_CTRLA_SPEED(2),
+};
+#endif
+
+/**
+ * \brief SERCOM I<SUP>2</SUP>C slave driver software device instance structure.
+ *
+ * SERCOM I<SUP>2</SUP>C slave driver software instance structure, used to
+ * retain software state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct i2c_slave_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware instance initialized for the struct */
+	Sercom *hw;
+	/** Module lock */
+	volatile bool locked;
+	/** Timeout value for polled functions */
+	uint16_t buffer_timeout;
+#  ifdef FEATURE_I2C_10_BIT_ADDRESS
+	/** Using 10-bit addressing for the slave */
+	bool ten_bit_address;
+#  endif
+#  if I2C_SLAVE_CALLBACK_MODE == true
+	/** Nack on address match */
+	bool nack_on_address;
+	/** Pointers to callback functions */
+	volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N];
+	/** Mask for registered callbacks */
+	volatile uint8_t registered_callback;
+	/** Mask for enabled callbacks */
+	volatile uint8_t enabled_callback;
+	/** The total number of bytes to transfer */
+	volatile uint16_t buffer_length;
+	/**
+	 * Counter used for bytes left to send in write and to count number of
+	 * obtained bytes in read
+	 */
+	uint16_t buffer_remaining;
+	/** Data buffer for packet write and read */
+	volatile uint8_t *buffer;
+	/** Save direction of request from master. 1 = read, 0 = write. */
+	volatile enum i2c_transfer_direction transfer_direction;
+	/** Status for status read back in error callback */
+	volatile enum status_code status;
+#  endif
+#endif
+};
+
+/**
+ * \brief Configuration structure for the I<SUP>2</SUP>C slave device
+ *
+ * This is the configuration structure for the I<SUP>2</SUP>C slave device. It is used
+ * as an argument for \ref i2c_slave_init to provide the desired
+ * configurations for the module. The structure should be initialized using the
+ * \ref i2c_slave_get_config_defaults.
+ */
+struct i2c_slave_config {
+	/** Set to enable the SCL low timeout */
+	bool enable_scl_low_timeout;
+	/** SDA hold time with respect to the negative edge of SCL */
+	enum i2c_slave_sda_hold_time sda_hold_time;
+	/** Timeout to wait for master in polled functions */
+	uint16_t buffer_timeout;
+	/** Addressing mode */
+	enum i2c_slave_address_mode address_mode;
+	/** Address or upper limit of address range */
+	uint16_t address;
+	/** Address mask, second address, or lower limit of address range */
+	uint16_t address_mask;
+#ifdef FEATURE_I2C_10_BIT_ADDRESS
+	/** Enable 10-bit addressing */
+	bool ten_bit_address;
+#endif
+	/**
+	 * Enable general call address recognition (general call address
+	 * is defined as 0000000 with direction bit 0).
+	 */
+	bool enable_general_call_address;
+
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+	/** Transfer speed mode */
+	enum i2c_slave_transfer_speed transfer_speed;
+#endif
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/**
+	 * Enable NACK on address match (this can be changed after initialization
+	 * via the \ref i2c_slave_enable_nack_on_address and
+	 * \ref i2c_slave_disable_nack_on_address functions).
+	 */
+	bool enable_nack_on_address;
+#endif
+	/** GCLK generator to use as clock source */
+	enum gclk_generator generator_source;
+	/** Set to keep module active in sleep modes */
+	bool run_in_standby;
+	/** PAD0 (SDA) pinmux */
+	uint32_t pinmux_pad0;
+	/** PAD1 (SCL) pinmux */
+	uint32_t pinmux_pad1;
+	/** Set to enable SCL low time-out */
+	bool scl_low_timeout;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+	/** Set to enable SCL stretch only after ACK bit (required for high speed) */
+	bool scl_stretch_only_after_ack_bit;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+	/** Set to enable slave SCL low extend time-out */
+	bool slave_scl_low_extend_timeout;
+#endif
+};
+
+
+/**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code i2c_slave_lock(
+		struct i2c_slave_module *const module)
+{
+	enum status_code status;
+
+	system_interrupt_enter_critical_section();
+
+	if (module->locked) {
+		status = STATUS_BUSY;
+	} else {
+		module->locked = true;
+		status = STATUS_OK;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline void i2c_slave_unlock(struct i2c_slave_module *const module)
+{
+	module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Returns the synchronization status of the module
+ *
+ * Returns the synchronization status of the module.
+ *
+ * \param[out] module  Pointer to software module structure
+ *
+ * \return Status of the synchronization.
+ * \retval true   Module is busy synchronizing
+ * \retval false  Module is not synchronizing
+ */
+static inline bool i2c_slave_is_syncing(
+		const struct i2c_slave_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+	/* Return sync status */
+#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
+	return (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_SYNCBUSY);
+#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
+	return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_MASK);
+#else
+#  error Unknown SERCOM SYNCBUSY scheme!
+#endif
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Wait for hardware module to sync
+ *
+ * \param[in]  module  Pointer to software module structure
+ */
+static void _i2c_slave_wait_for_sync(
+		const struct i2c_slave_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+
+	while (i2c_slave_is_syncing(module)) {
+		/* Wait for I<SUP>2</SUP>C module to sync */
+	}
+}
+#endif
+
+///@cond INTERNAL
+/**
+ * \internal Workaround for errata 13574
+ * Instead set ACK/NACK of CTRLB
+ *
+ * This errata exist in part revisions of SAM D20/D21/D09
+ * D10/D11/L21/L22/DA1/C20/C21/R30/HA1, but workaround can be works in all
+ * revision of those device. As this function operation
+ * should be use less cpu time as possible, so caller
+ * function can ignore to check revision number, and use
+ * this workaround in all revision of those device.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ * \param[in] send_ack true send ACK, false send NACK
+ */
+static inline void _i2c_slave_set_ctrlb_ackact(
+		struct i2c_slave_module *const module,
+		bool send_ack)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAML21 || SAMDA1 ||  \
+		SAML22 || SAMC20 || SAMC21 || SAMHA1 || SAMR30)
+	/* Workaround, Following two write are atomic */
+	system_interrupt_enter_critical_section();
+	i2c_hw->STATUS.reg = 0;
+
+	if (send_ack == true) {
+		i2c_hw->CTRLB.reg = 0;
+	}
+	else {
+		i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
+	}
+	system_interrupt_leave_critical_section();
+#else
+	/* Normal operation */
+	if (send_ack == true) {
+		i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	}
+	else {
+		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+	}
+#endif
+	return;
+}
+
+/**
+ * \internal Workaround for SAM0 errata 13574,
+ * instead Set CMD3 of CTRLB
+ *
+ * This errata exist in part revisions of SAM D20/D21/D09
+ * D10/D11/L21/DA1/C20/C21/R30/HA1, but workaround can be works in all
+ * revision of those device. As this function operation
+ * should be use less cpu time as possible, so caller
+ * function can ignore to check revision number, and use
+ * this workaround in all revision of those device.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static inline void _i2c_slave_set_ctrlb_cmd3(
+		struct i2c_slave_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAML21 || SAML22 || \
+		SAMDA1 || SAMC20 || SAMC21 || SAMR30 || SAMHA1)
+	/* Workaround */
+	/*
+	 * Below code instead i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3);
+	 * CMD=0x3 clears all interrupts, so to keep the result similar
+	 * PREC is cleared if it was set
+	 */
+	if (i2c_hw->INTFLAG.bit.PREC) {
+		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+	}
+	i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+#else
+	/* Normal operation */
+	i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3);
+#endif
+	return;
+}
+///@endcond
+
+/**
+ * \brief Gets the I<SUP>2</SUP>C slave default configurations
+ *
+ * This will initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Disable SCL low timeout
+ * - 300ns - 600ns SDA hold time
+ * - Buffer timeout = 65535
+ * - Address with mask
+ * - Address = 0
+ * - Address mask = 0 (one single address)
+ * - General call address disabled
+ * - Address nack disabled if the interrupt driver is used
+ * - GCLK generator 0
+ * - Do not run in standby
+ * - PINMUX_DEFAULT for SERCOM pads
+ *
+ * Those default configuration only available if the device supports it:
+ * - Not using 10-bit addressing
+ * - Standard-mode and Fast-mode transfer speed
+ * - SCL stretch disabled
+ * - Slave SCL low extend time-out disabled
+ *
+ * \param[out] config  Pointer to configuration structure to be initialized
+ */
+static inline void i2c_slave_get_config_defaults(
+		struct i2c_slave_config *const config)
+{
+	/*Sanity check argument */
+	Assert(config);
+	config->enable_scl_low_timeout = false;
+	config->sda_hold_time = I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS;
+	config->buffer_timeout = 65535;
+	config->address_mode = I2C_SLAVE_ADDRESS_MODE_MASK;
+	config->address = 0;
+	config->address_mask = 0;
+#ifdef FEATURE_I2C_10_BIT_ADDRESS
+	config->ten_bit_address = false;
+#endif
+	config->enable_general_call_address = false;
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+	config->transfer_speed = I2C_SLAVE_SPEED_STANDARD_AND_FAST;
+#endif
+#if I2C_SLAVE_CALLBACK_MODE == true
+	config->enable_nack_on_address = false;
+#endif
+	config->generator_source = GCLK_GENERATOR_0;
+	config->run_in_standby = false;
+	config->pinmux_pad0 = PINMUX_DEFAULT;
+	config->pinmux_pad1 = PINMUX_DEFAULT;
+	config->scl_low_timeout  = false;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+	config->scl_stretch_only_after_ack_bit = false;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+	config->slave_scl_low_extend_timeout   = false;
+#endif
+}
+
+enum status_code i2c_slave_init(struct i2c_slave_module *const module,
+		Sercom *const hw,
+		const struct i2c_slave_config *const config);
+
+/**
+ * \brief Enables the I<SUP>2</SUP>C module
+ *
+ * This will enable the requested I<SUP>2</SUP>C module.
+ *
+ * \param[in]  module Pointer to the software module struct
+ */
+static inline void i2c_slave_enable(
+		const struct i2c_slave_module *const module)
+{
+	/* Sanity check of arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Enable global interrupt for module */
+	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+	/* Wait for module to sync */
+	_i2c_slave_wait_for_sync(module);
+
+	/* Enable module */
+	i2c_hw->CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+}
+
+
+/**
+ * \brief Disables the I<SUP>2</SUP>C module
+ *
+ * This will disable the I<SUP>2</SUP>C module specified in the provided software module
+ * structure.
+ *
+ * \param[in]  module  Pointer to the software module struct
+ */
+static inline void i2c_slave_disable(
+		const struct i2c_slave_module *const module)
+{
+	/* Sanity check of arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+	/* Disable interrupts */
+	i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC |
+			SERCOM_I2CS_INTENSET_AMATCH | SERCOM_I2CS_INTENSET_DRDY;
+
+	/* Clear interrupt flags */
+	i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_AMATCH |
+			SERCOM_I2CS_INTFLAG_DRDY;
+
+	/* Disable global interrupt for module */
+	system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+	/* Wait for module to sync */
+	_i2c_slave_wait_for_sync(module);
+
+	/* Disable module */
+	i2c_hw->CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+}
+
+void i2c_slave_reset(
+		struct i2c_slave_module *const module);
+
+/** @} */
+
+/**
+ * \name Read and Write
+ * @{
+ */
+
+enum status_code i2c_slave_write_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet);
+enum status_code i2c_slave_read_packet_wait(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet);
+enum i2c_slave_direction i2c_slave_get_direction_wait(
+		struct i2c_slave_module *const module);
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+uint32_t i2c_slave_get_status(
+		struct i2c_slave_module *const module);
+void i2c_slave_clear_status(
+		struct i2c_slave_module *const module,
+		uint32_t status_flags);
+/** @} */
+
+#ifdef FEATURE_I2C_DMA_SUPPORT
+/**
+ * \name SERCOM I2C slave with DMA Interfaces
+ * @{
+ */
+
+/**
+ * \brief Read SERCOM I<SUP>2</SUP>C interrupt status.
+ *
+ * Read I<SUP>2</SUP>C interrupt status for DMA transfer.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ */
+static inline uint8_t i2c_slave_dma_read_interrupt_status(struct i2c_slave_module *const module)
+{
+	return (uint8_t)module->hw->I2CS.INTFLAG.reg;
+}
+
+/**
+ * \brief Write SERCOM I<SUP>2</SUP>C interrupt status.
+ *
+ * Write I<SUP>2</SUP>C interrupt status for DMA transfer.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ * \param[in] flag Interrupt flag status
+ *
+ */
+static inline void i2c_slave_dma_write_interrupt_status(struct i2c_slave_module *const module,
+		uint8_t flag)
+{
+	module->hw->I2CS.INTFLAG.reg = flag;
+}
+
+/** @} */
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_SLAVE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h
new file mode 100644
index 0000000000..cf1c4362c7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h
@@ -0,0 +1,215 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Slave Interrupt Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef I2C_SLAVE_INTERRUPT_H_INCLUDED
+#define I2C_SLAVE_INTERRUPT_H_INCLUDED
+
+#include "i2c_slave.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_i2c_group
+ * @{
+ *
+ */
+
+/**
+ * \name Address Match Functionality
+ * @{
+ */
+
+void i2c_slave_enable_nack_on_address(
+		struct i2c_slave_module *const module);
+void i2c_slave_disable_nack_on_address(
+		struct i2c_slave_module *const module);
+
+/** @} */
+
+/**
+ * \name Callbacks
+ * @{
+ */
+#if !defined(__DOXYGEN__)
+void _i2c_slave_interrupt_handler(uint8_t instance);
+#endif
+
+void i2c_slave_register_callback(
+		struct i2c_slave_module *const module,
+		i2c_slave_callback_t callback,
+		enum i2c_slave_callback callback_type);
+
+void i2c_slave_unregister_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback_type  Callback type to enable
+ */
+static inline void i2c_slave_enable_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as enabled */
+	module->enabled_callback |= (1 << callback_type);
+
+	/* Enable address callback */
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+	if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST ||
+			callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST) {
+		i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+	}
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback_type  Callback type to disable
+ */
+static inline void i2c_slave_disable_callback(
+		struct i2c_slave_module *const module,
+		enum i2c_slave_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as disabled */
+	module->enabled_callback &= ~(1 << callback_type);
+	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+	if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST ||
+			callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST ||
+			module->status != STATUS_BUSY) {
+		i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+	}
+}
+
+/** @} */
+
+/**
+ * \name Read and Write, Interrupt-Driven
+ * @{
+ */
+
+
+enum status_code i2c_slave_read_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet);
+
+enum status_code i2c_slave_write_packet_job(
+		struct i2c_slave_module *const module,
+		struct i2c_slave_packet *const packet);
+
+/**
+ * \brief Cancels any currently ongoing operation
+ *
+ * Terminates the running transfer operation.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static inline void i2c_slave_cancel_job(
+		struct i2c_slave_module *const module)
+{
+	/* Sanity check. */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Set buffer to 0. */
+	module->buffer_remaining = 0;
+	module->buffer_length = 0;
+}
+
+/**
+ * \brief Gets status of ongoing job
+ *
+ * Will return the status of the ongoing job, or the error that occurred
+ * in the last transfer operation.
+ * The status will be cleared when starting a new job.
+ *
+ * \param[in,out] module Pointer to software module structure
+ *
+ * \return                      Status of job.
+ * \retval STATUS_OK            No error has occurred
+ * \retval STATUS_BUSY          Transfer is in progress
+ * \retval STATUS_ERR_IO        A collision, timeout or bus error happened in
+ *                              the last transfer
+ * \retval STATUS_ERR_TIMEOUT   A timeout occurred
+ * \retval STATUS_ERR_OVERFLOW  Data from master overflows receive buffer
+ */
+static inline enum status_code i2c_slave_get_job_status(
+		struct i2c_slave_module *const module)
+{
+	/* Check sanity. */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Return current status code. */
+	return module->status;
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_SLAVE_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.c
new file mode 100644
index 0000000000..270973a7db
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.c
@@ -0,0 +1,290 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "sercom.h"
+
+#define SHIFT 32
+#define BAUD_INT_MAX   8192
+#define BAUD_FP_MAX     8
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Configuration structure to save current gclk status.
+ */
+struct _sercom_conf {
+	/* Status of gclk generator initialization */
+	bool generator_is_set;
+	/* Sercom gclk generator used */
+	enum gclk_generator generator_source;
+};
+
+static struct _sercom_conf _sercom_config;
+
+
+/**
+ * \internal Calculate 64 bit division, ref can be found in
+ * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
+ */
+static uint64_t long_division(uint64_t n, uint64_t d)
+{
+	int32_t i;
+	uint64_t q = 0, r = 0, bit_shift;
+	for (i = 63; i >= 0; i--) {
+		bit_shift = (uint64_t)1 << i;
+
+		r = r << 1;
+
+		if (n & bit_shift) {
+			r |= 0x01;
+		}
+
+		if (r >= d) {
+			r = r - d;
+			q |= bit_shift;
+		}
+	}
+
+	return q;
+}
+
+/**
+ * \internal Calculate synchronous baudrate value (SPI/UART)
+ */
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudvalue)
+{
+	/* Baud value variable */
+	uint16_t baud_calculated = 0;
+	uint32_t clock_value = external_clock;
+
+
+	/* Check if baudrate is outside of valid range */
+	if (baudrate > (external_clock / 2)) {
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+
+	/* Calculate BAUD value from clock frequency and baudrate */
+	clock_value = external_clock / 2;
+	while (clock_value >= baudrate) {
+		clock_value = clock_value - baudrate;
+		baud_calculated++;
+	}
+	baud_calculated = baud_calculated - 1;
+
+	/* Check if BAUD value is more than 255, which is maximum
+	 * for synchronous mode */
+	if (baud_calculated > 0xFF) {
+		/* Return with an error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	} else {
+		*baudvalue = baud_calculated;
+		return STATUS_OK;
+	}
+}
+
+/**
+ * \internal Calculate asynchronous baudrate value (UART)
+*/
+enum status_code _sercom_get_async_baud_val(
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num)
+{
+	/* Temporary variables  */
+	uint64_t ratio = 0;
+	uint64_t scale = 0;
+	uint64_t baud_calculated = 0;
+	uint8_t baud_fp;
+	uint32_t baud_int = 0;
+	uint64_t temp1;
+
+	/* Check if the baudrate is outside of valid range */
+	if ((baudrate * sample_num) > peripheral_clock) {
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+
+	if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
+		/* Calculate the BAUD value */
+		temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
+		ratio = long_division(temp1, peripheral_clock);
+		scale = ((uint64_t)1 << SHIFT) - ratio;
+		baud_calculated = (65536 * scale) >> SHIFT;
+	} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
+		temp1 = ((uint64_t)baudrate * sample_num);
+		baud_int = long_division( peripheral_clock, temp1);
+		if(baud_int > BAUD_INT_MAX) {
+				return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+		}
+		temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
+		baud_fp = temp1 - 8 * baud_int;
+		baud_calculated = baud_int | (baud_fp << 13);
+	}
+
+	*baudval = baud_calculated;
+	return STATUS_OK;
+}
+#endif
+
+/**
+ * \brief Set GCLK channel to generator.
+ *
+ * This will set the appropriate GCLK channel to the requested GCLK generator.
+ * This will set the generator for all SERCOM instances, and the user will thus
+ * only be able to set the same generator that has previously been set, if any.
+ *
+ * After the generator has been set the first time, the generator can be changed
+ * using the \c force_change flag.
+ *
+ * \param[in]  generator_source The generator to use for SERCOM.
+ * \param[in]  force_change     Force change the generator.
+ *
+ * \return Status code indicating the GCLK generator change operation.
+ * \retval STATUS_OK                       If the generator update request was
+ *                                         successful.
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  If a generator was already configured
+ *                                         and the new configuration was not
+ *                                         forced.
+ */
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change)
+{
+	/* Check if valid option */
+	if (!_sercom_config.generator_is_set || force_change) {
+		/* Create and fill a GCLK configuration structure for the new config */
+		struct system_gclk_chan_config gclk_chan_conf;
+		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+		gclk_chan_conf.source_generator = generator_source;
+		system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
+		system_gclk_chan_enable(SERCOM_GCLK_ID);
+
+		/* Save config */
+		_sercom_config.generator_source = generator_source;
+		_sercom_config.generator_is_set = true;
+
+		return STATUS_OK;
+	} else if (generator_source == _sercom_config.generator_source) {
+		/* Return status OK if same config */
+		return STATUS_OK;
+	}
+
+	/* Return invalid config to already initialized GCLK */
+	return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/** \internal
+ * Creates a switch statement case entry to convert a SERCOM instance and pad
+ * index to the default SERCOM pad MUX setting.
+ */
+#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
+		case (uintptr_t)SERCOM##n: \
+			switch (pad) { \
+				case 0: \
+					return SERCOM##n##_PAD0_DEFAULT; \
+				case 1: \
+					return SERCOM##n##_PAD1_DEFAULT; \
+				case 2: \
+					return SERCOM##n##_PAD2_DEFAULT; \
+				case 3: \
+					return SERCOM##n##_PAD3_DEFAULT; \
+			} \
+			break;
+
+/**
+ * \internal Gets the default PAD pinout for a given SERCOM.
+ *
+ * Returns the pinmux settings for the given SERCOM and pad. This is used
+ * for default configuration of pins.
+ *
+ * \param[in]  sercom_module   Pointer to the SERCOM module
+ * \param[in]  pad             PAD to get default pinout for
+ *
+ * \returns The default pinmux for the given SERCOM instance and PAD
+ *
+ */
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad)
+{
+	switch ((uintptr_t)sercom_module) {
+		/* Auto-generate a lookup table for the default SERCOM pad defaults */
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \internal
+ * Find index of given instance.
+ *
+ * \param[in] sercom_instance  Instance pointer.
+ *
+ * \return Index of given instance.
+ */
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance)
+{
+	/* Save all available SERCOM instances for compare */
+	Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+
+	/* Find index for sercom instance */
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+		if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given */
+	Assert(false);
+	return 0;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.h
new file mode 100644
index 0000000000..60ce6f8ad1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.h
@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SERCOM_H_INCLUDED
+#define SERCOM_H_INCLUDED
+
+#include <compiler.h>
+#include <system.h>
+#include <clock.h>
+#include <system_interrupt.h>
+#include "sercom_pinout.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* SERCOM modules should share  same slow GCLK channel ID */
+#define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
+
+#if (0x1ff >= REV_SERCOM)
+#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
+#elif (0x400 >= REV_SERCOM)
+#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
+#else
+#  error "Unknown SYNCBUSY scheme for this SERCOM revision"
+#endif
+
+/**
+ * \brief sercom asynchronous operation mode
+ *
+ * Select sercom asynchronous operation mode
+ */
+enum sercom_asynchronous_operation_mode {
+	SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
+	SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
+};
+
+/**
+ * \brief sercom asynchronous samples per bit
+ *
+ * Select number of samples per bit
+ */
+enum sercom_asynchronous_sample_num {
+	SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
+	SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
+	SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
+};
+
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change);
+
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudval);
+
+enum status_code _sercom_get_async_baud_val(
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num);
+
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad);
+
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance);
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SERCOM_H_INCLUDED
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.c
new file mode 100644
index 0000000000..b26d05b6e7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.c
@@ -0,0 +1,141 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "sercom_interrupt.h"
+
+void *_sercom_instances[SERCOM_INST_NUM];
+
+/** Save status of initialized handlers */
+static bool _handler_table_initialized = false;
+
+/** Void pointers for saving device instance structures */
+static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
+
+/**
+ * \internal
+ * Default interrupt handler.
+ *
+ * \param[in] instance SERCOM instance used.
+ */
+static void _sercom_default_handler(
+		const uint8_t instance)
+{
+	Assert(false);
+}
+
+/**
+ * \internal
+ * Saves the given callback handler.
+ *
+ * \param[in]  instance           Instance index.
+ * \param[in]  interrupt_handler  Pointer to instance callback handler.
+ */
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler)
+{
+	/* Initialize handlers with default handler and device instances with 0 */
+	if (_handler_table_initialized == false) {
+		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
+			_sercom_instances[i] = NULL;
+		}
+
+		_handler_table_initialized = true;
+	}
+
+	/* Save interrupt handler */
+	_sercom_interrupt_handlers[instance] = interrupt_handler;
+}
+
+
+/** \internal
+ * Converts a given SERCOM index to its interrupt vector index.
+ */
+#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
+		SYSTEM_INTERRUPT_MODULE_SERCOM##n,
+
+/** \internal
+ * Generates a SERCOM interrupt handler function for a given SERCOM index.
+ */
+#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
+		void SERCOM##n##_Handler(void) \
+		{ \
+			_sercom_interrupt_handlers[n](n); \
+		}
+
+/**
+ * \internal
+ * Returns the system interrupt vector.
+ *
+ * \param[in]  sercom_instance  Instance pointer
+ *
+ * \return Enum of system interrupt vector
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
+ */
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance)
+{
+	const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
+		{
+			MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
+		};
+
+	/* Retrieve the index of the SERCOM being requested */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
+
+	/* Get the vector number from the lookup table for the requested SERCOM */
+	return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
+}
+
+/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
+MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.h
new file mode 100644
index 0000000000..18945f5186
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SERCOM_INTERRUPT_H_INCLUDED
+#define SERCOM_INTERRUPT_H_INCLUDED
+
+#include "sercom.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Look-up table for device instances */
+extern void *_sercom_instances[SERCOM_INST_NUM];
+
+typedef void (*sercom_handler_t)(uint8_t instance);
+
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance);
+
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SERCOM_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_pinout.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_pinout.h
new file mode 100644
index 0000000000..fdbc5405e2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_pinout.h
@@ -0,0 +1,547 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM Module Pinout Definitions
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SERCOM_PINOUT_H_INCLUDED
+#define SERCOM_PINOUT_H_INCLUDED
+
+#include <compiler.h>
+
+#if SAMR21E
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+# if SAM_PART_IS_DEFINED(SAMR21E19A)
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+# else
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA27F_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA28F_SERCOM3_PAD1
+#endif
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+	/* SERCOM4 */
+# if SAM_PART_IS_DEFINED(SAMR21E19A)
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+# else
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+# endif
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif SAMR21G
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif (SAMD09)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU) 
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA22C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA23C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA16D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA25D_SERCOM2_PAD3
+
+#elif (SAMD10C) || (SAMD11C)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L)
+
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+#elif (SAML22N)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PB02C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PB21C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PB00C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PB01C_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12C_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13C_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14C_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15C_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+#elif (SAML22J) || (SAML22G)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA12D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA13D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA14D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA15D_SERCOM3_PAD3
+#elif (SAMC20E) || (SAMC21E)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+#elif (SAMC20G) || (SAMC21G)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+  #ifdef ID_SERCOM4
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+  #endif
+
+  #ifdef ID_SERCOM5
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+  #endif
+
+#elif (SAMC20J) || (SAMC21J)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+  #ifdef ID_SERCOM4
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+  #endif
+
+  #ifdef ID_SERCOM5
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB00D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB01D_SERCOM5_PAD3
+  #endif
+
+#elif (SAMDA1)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if (SAMDA1E)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+  #else
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+  #endif
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif   SAM_PART_IS_DEFINED(SAMHA1G14A) || SAM_PART_IS_DEFINED(SAMHA1G15A) || \
+	SAM_PART_IS_DEFINED(SAMHA1G16A)
+	
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB16C_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB17C_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA21C_SERCOM5_PAD3
+
+#elif (SAML21E) || (SAMR30E)
+
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if !SAM_PART_IS_DEFINED(SAML21E18A) && !SAM_PART_IS_DEFINED(SAMR30E18A)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+  #endif
+
+#else
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+#if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L)
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+#else
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+#endif
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if !(SAMD20E || SAMD21E)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+  #endif
+
+#endif
+
+#endif /* SERCOM_PINOUT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/module_config/conf_spi.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/module_config/conf_spi.h
new file mode 100644
index 0000000000..18b4f76ef1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/module_config/conf_spi.h
@@ -0,0 +1,55 @@
+/**
+ * \file
+ *
+ * \brief SAM SPI configuration
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef CONF_SPI_H_INCLUDED
+#  define CONF_SPI_H_INCLUDED
+
+#  define CONF_SPI_MASTER_ENABLE     true
+#  define CONF_SPI_SLAVE_ENABLE      true
+
+#endif /* CONF_SPI_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.c
new file mode 100644
index 0000000000..c0b4acb4a0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.c
@@ -0,0 +1,1265 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "spi.h"
+
+/**
+ * \brief Resets the SPI module
+ *
+ * This function will reset the SPI module to its power on default values and
+ * disable it.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ */
+void spi_reset(
+		struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Disable the module */
+	spi_disable(module);
+
+	while (spi_is_syncing(module)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Software reset the module */
+	spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+}
+
+/**
+ * \brief Set the baudrate of the SPI module
+ *
+ * This function will set the baudrate of the SPI module.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ * \param[in]  baudrate  The baudrate wanted
+ *
+ * \return The status of the configuration.
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_OK               If the configuration was written
+ */
+enum status_code spi_set_baudrate(
+		struct spi_module *const module,
+		uint32_t baudrate)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(baudrate);
+	Assert(module->hw);
+
+	/* Value to write to BAUD register */
+	uint16_t baud = 0;
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Disable the module */
+	spi_disable(module);
+
+	while (spi_is_syncing(module)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Find frequency of the internal SERCOMi_GCLK_ID_CORE */
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index);
+
+	/* Get baud value, based on baudrate and the internal clock frequency */
+	enum status_code error_code = _sercom_get_sync_baud_val(
+			baudrate, internal_clock, &baud);
+
+	if (error_code != STATUS_OK) {
+		/* Baud rate calculation error, return status code */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	spi_module->BAUD.reg = (uint8_t)baud;
+
+	while (spi_is_syncing(module)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Enable the module */
+	spi_enable(module);
+
+	while (spi_is_syncing(module)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	return STATUS_OK;
+}
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+/**
+ * \internal Clears the Transmit Complete interrupt flag.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ */
+static void _spi_clear_tx_complete_flag(
+		struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Clear interrupt flag */
+	spi_module->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+}
+#  endif
+
+/**
+ * \internal Writes an SPI SERCOM configuration to the hardware module.
+ *
+ * This function will write out a given configuration to the hardware module.
+ * Can only be done when the module is disabled.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return The status of the configuration.
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_OK               If the configuration was written
+ */
+static enum status_code _spi_set_config(
+		struct spi_module *const module,
+		const struct spi_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(config);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+	Sercom *const hw = module->hw;
+
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+	pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	if(config->mode == SPI_MODE_SLAVE) {
+		pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+	}
+
+	uint32_t pad_pinmuxes[] = {
+			config->pinmux_pad0, config->pinmux_pad1,
+			config->pinmux_pad2, config->pinmux_pad3
+		};
+
+	/* Configure the SERCOM pins according to the user configuration */
+	for (uint8_t pad = 0; pad < 4; pad++) {
+		uint32_t current_pinmux = pad_pinmuxes[pad];
+
+		if (current_pinmux == PINMUX_DEFAULT) {
+			current_pinmux = _sercom_get_default_pad(hw, pad);
+		}
+
+		if (current_pinmux != PINMUX_UNUSED) {
+			pin_conf.mux_position = current_pinmux & 0xFFFF;
+			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+		}
+	}
+
+	module->mode             = config->mode;
+	module->character_size   = config->character_size;
+	module->receiver_enabled = config->receiver_enable;
+#  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
+	module->master_slave_select_enable = config->master_slave_select_enable;
+#  endif
+
+#  if CONF_SPI_MASTER_ENABLE == true
+	/* Value to write to BAUD register */
+	uint16_t baud = 0;
+#  endif
+	/* Value to write to CTRLA register */
+	uint32_t ctrla = 0;
+	/* Value to write to CTRLB register */
+	uint32_t ctrlb = 0;
+
+# if CONF_SPI_MASTER_ENABLE == true
+	/* Find baud value and write it */
+	if (config->mode == SPI_MODE_MASTER) {
+		/* Find frequency of the internal SERCOMi_GCLK_ID_CORE */
+		uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+		uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+		uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index);
+
+		/* Get baud value, based on baudrate and the internal clock frequency */
+		enum status_code error_code = _sercom_get_sync_baud_val(
+				config->mode_specific.master.baudrate,
+				internal_clock, &baud);
+
+		if (error_code != STATUS_OK) {
+			/* Baud rate calculation error, return status code */
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		spi_module->BAUD.reg = (uint8_t)baud;
+	}
+# endif
+# if CONF_SPI_SLAVE_ENABLE == true
+	if (config->mode == SPI_MODE_SLAVE) {
+		/* Set frame format */
+		ctrla = config->mode_specific.slave.frame_format;
+
+		/* Set address mode */
+		ctrlb = config->mode_specific.slave.address_mode;
+
+		/* Set address and address mask*/
+		spi_module->ADDR.reg |=
+				(config->mode_specific.slave.address      << SERCOM_SPI_ADDR_ADDR_Pos) |
+				(config->mode_specific.slave.address_mask << SERCOM_SPI_ADDR_ADDRMASK_Pos);
+
+		if (config->mode_specific.slave.preload_enable) {
+			/* Enable pre-loading of shift register */
+			ctrlb |= SERCOM_SPI_CTRLB_PLOADEN;
+		}
+	}
+# endif
+	/* Set data order */
+	ctrla |= config->data_order;
+
+	/* Set clock polarity and clock phase */
+	ctrla |= config->transfer_mode;
+
+	/* Set MUX setting */
+	ctrla |= config->mux_setting;
+
+	/* Set SPI character size */
+	ctrlb |= config->character_size;
+
+	/* Set whether module should run in standby. */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY;
+	}
+
+	if (config->receiver_enable) {
+		/* Enable receiver */
+		ctrlb |= SERCOM_SPI_CTRLB_RXEN;
+	}
+#  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+	if (config->select_slave_low_detect_enable) {
+		/* Enable Slave Select Low Detect */
+		ctrlb |= SERCOM_SPI_CTRLB_SSDE;
+	}
+#  endif
+#  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
+	if (config->master_slave_select_enable) {
+		/* Enable Master Slave Select */
+		ctrlb |= SERCOM_SPI_CTRLB_MSSEN;
+	}
+#  endif
+	/* Write CTRLA register */
+	spi_module->CTRLA.reg |= ctrla;
+
+	/* Write CTRLB register */
+	spi_module->CTRLB.reg |= ctrlb;
+
+	return STATUS_OK;
+}
+
+#if SPI_CALLBACK_MODE == false
+/**
+ * \internal Checks an SPI config against current set config
+ *
+ * This function will check that the config does not alter the
+ * configuration of the module. If the new config changes any
+ * setting, the initialization will be discarded.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return The status of the configuration.
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_DENIED       If configuration was different from previous
+ * \retval STATUS_OK               If the configuration was written
+ */
+static enum status_code _spi_check_config(
+		struct spi_module *const module,
+		const struct spi_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(config);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+	Sercom *const hw = module->hw;
+
+	uint32_t pad_pinmuxes[] = {
+		config->pinmux_pad0, config->pinmux_pad1,
+		config->pinmux_pad2, config->pinmux_pad3
+	};
+
+	/* Compare the current SERCOM pins against the user configuration */
+	for (uint8_t pad = 0; pad < 4; pad++) {
+		uint32_t current_pinmux = pad_pinmuxes[pad];
+
+		if (current_pinmux == PINMUX_DEFAULT) {
+			current_pinmux = _sercom_get_default_pad(hw, pad);
+		}
+
+		if (current_pinmux == PINMUX_UNUSED) {
+			continue;
+		}
+
+		if ((current_pinmux & 0xFFFF) !=
+				system_pinmux_pin_get_mux_position(current_pinmux >> 16)) {
+			module->hw = NULL;
+			return STATUS_ERR_DENIED;
+		}
+	}
+
+#  if CONF_SPI_MASTER_ENABLE == true
+	/* Value to read BAUD register */
+	uint16_t baud;
+	uint32_t external_clock = system_gclk_chan_get_hz(SERCOM_GCLK_ID);
+#  endif
+	/* Value to read CTRLA, CTRLB and ADDR register */
+	uint32_t ctrla = 0;
+	uint32_t ctrlb = 0;
+#  if CONF_SPI_SLAVE_ENABLE == true
+	uint32_t addr = 0;
+#  endif
+
+#  if CONF_SPI_MASTER_ENABLE == true
+	/* Find baud value and compare it */
+	if (config->mode == SPI_MODE_MASTER) {
+		enum status_code error_code = _sercom_get_sync_baud_val(
+				config->mode_specific.master.baudrate,
+				external_clock, &baud);
+
+		if (error_code != STATUS_OK) {
+			/* Baud rate calculation error, return status code */
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		if (spi_module->BAUD.reg !=  (uint8_t)baud) {
+			return STATUS_ERR_DENIED;
+		}
+
+		ctrla |= SERCOM_SPI_CTRLA_MODE(0x3);
+	}
+#  endif
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if (config->mode == SPI_MODE_SLAVE) {
+
+		/* Set frame format */
+		ctrla |= config->mode_specific.slave.frame_format;
+
+		/* Set address mode */
+		ctrlb |= config->mode_specific.slave.address_mode;
+
+		/* Set address and address mask*/
+		addr |= (config->mode_specific.slave.address      << SERCOM_SPI_ADDR_ADDR_Pos) |
+				(config->mode_specific.slave.address_mask << SERCOM_SPI_ADDR_ADDRMASK_Pos);
+		if (spi_module->CTRLA.reg != addr) {
+			return STATUS_ERR_DENIED;
+		}
+
+		if (config->mode_specific.slave.preload_enable) {
+			/* Enable pre-loading of shift register */
+			ctrlb |= SERCOM_SPI_CTRLB_PLOADEN;
+		}
+		ctrla |= SERCOM_SPI_CTRLA_MODE(0x2);
+	}
+#  endif
+	/* Set data order */
+	ctrla |= config->data_order;
+
+	/* Set clock polarity and clock phase */
+	ctrla |= config->transfer_mode;
+
+	/* Set MUX setting */
+	ctrla |= config->mux_setting;
+
+	/* Set SPI character size */
+	ctrlb |= config->character_size;
+
+	if (config->run_in_standby) {
+		/* Enable in sleep mode */
+		ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY;
+	}
+
+	if (config->receiver_enable) {
+		/* Enable receiver */
+		ctrlb |= SERCOM_SPI_CTRLB_RXEN;
+	}
+
+#  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+	if (config->select_slave_low_detect_enable) {
+		/* Enable Slave Select Low Detect */
+		ctrlb |= SERCOM_SPI_CTRLB_SSDE;
+	}
+#  endif
+#  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
+	if (config->master_slave_select_enable) {
+		/* Enable Master Slave Select */
+		ctrlb |= SERCOM_SPI_CTRLB_MSSEN;
+	}
+#  endif
+
+	ctrla |= SERCOM_SPI_CTRLA_ENABLE;
+
+	/* Check that same config is set */
+	if (spi_module->CTRLA.reg == ctrla &&
+			spi_module->CTRLB.reg == ctrlb) {
+		module->mode           = config->mode;
+		module->character_size = config->character_size;
+		return STATUS_OK;
+	}
+
+	/* Not same config, wipe module pointer and return */
+	module->hw = NULL;
+
+	return STATUS_ERR_DENIED;
+}
+#endif
+
+/**
+ * \brief Initializes the SERCOM SPI module
+ *
+ * This function will initialize the SERCOM SPI module, based on the values
+ * of the config struct.
+ *
+ * \param[out]  module  Pointer to the software instance struct
+ * \param[in]   hw      Pointer to hardware instance
+ * \param[in]   config  Pointer to the config struct
+ *
+ * \return Status of the initialization.
+ * \retval STATUS_OK               Module initiated correctly
+ * \retval STATUS_ERR_DENIED       If module is enabled
+ * \retval STATUS_BUSY             If module is busy resetting
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code spi_init(
+		struct spi_module *const module,
+		Sercom *const hw,
+		const struct spi_config *const config)
+{
+
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module->hw = hw;
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Check if module is enabled. */
+	if (spi_module->CTRLA.reg & SERCOM_SPI_CTRLA_ENABLE) {
+#  if SPI_CALLBACK_MODE == false
+		/* Check if config is valid */
+		return _spi_check_config(module, config);
+#  else
+		return STATUS_ERR_DENIED;
+#  endif
+	}
+
+	/* Check if reset is in progress. */
+	if (spi_module->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST){
+		return STATUS_BUSY;
+	}
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index, gclk_index;
+#if (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+#  ifdef ID_SERCOM5
+		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+		gclk_index   =  SERCOM5_GCLK_ID_CORE;
+#  else
+		return STATUS_ERR_INVALID_ARG;
+#  endif
+	} else {
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#elif (SAMC21) 
+	if (sercom_index == 5) {
+#  ifdef ID_SERCOM5
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   =  SERCOM5_GCLK_ID_CORE;
+#  else
+		return STATUS_ERR_INVALID_ARG;
+#  endif
+	} else {
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#elif (SAMC20) || (SAML22)
+	pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#else
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	/* Turn on module in PM */
+#if (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+#  ifdef ID_SERCOM5
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+#  else
+		return STATUS_ERR_INVALID_ARG;
+#  endif
+	} else {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+	}
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+#endif
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+#  if CONF_SPI_MASTER_ENABLE == true
+	if (config->mode == SPI_MODE_MASTER) {
+		/* Set the SERCOM in SPI master mode */
+		spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3);
+	}
+#  endif
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if (config->mode == SPI_MODE_SLAVE) {
+		/* Set the SERCOM in SPI slave mode */
+		spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x2);
+	}
+#  endif
+
+#if SPI_CALLBACK_MODE == true
+	/* Temporary variables */
+	uint8_t i;
+	uint8_t instance_index;
+
+	/* Initialize parameters */
+	for (i = 0; i < SPI_CALLBACK_N; i++) {
+		module->callback[i]        = NULL;
+	}
+	module->tx_buffer_ptr              = NULL;
+	module->rx_buffer_ptr              = NULL;
+	module->remaining_tx_buffer_length = 0x0000;
+	module->remaining_rx_buffer_length = 0x0000;
+	module->registered_callback        = 0x00;
+	module->enabled_callback           = 0x00;
+	module->status                     = STATUS_OK;
+	module->dir                        = SPI_DIRECTION_IDLE;
+	module->locked                     = false;
+	/*
+	 * Set interrupt handler and register SPI software module struct in
+	 * look-up table
+	 */
+	instance_index = _sercom_get_sercom_inst_index(module->hw);
+	_sercom_set_handler(instance_index, _spi_interrupt_handler);
+	_sercom_instances[instance_index] = module;
+#endif
+
+	/* Write configuration to module and return status code */
+	return _spi_set_config(module, config);
+}
+
+/**
+ * \brief Reads buffer of \c length SPI characters
+ *
+ * This function will read a buffer of data from an SPI peripheral by sending
+ * dummy SPI character if in master mode, or by waiting for data in slave mode.
+ *
+ * \note If address matching is enabled for the slave, the first character
+ *       received and placed in the buffer will be the address.
+ *
+ * \param[in]  module   Pointer to the software instance struct
+ * \param[out] rx_data  Data buffer for received data
+ * \param[in]  length   Length of data to receive
+ * \param[in]  dummy    8- or 9-bit dummy byte to shift out in master mode
+ *
+ * \return Status of the read operation.
+ * \retval STATUS_OK              If the read was completed
+ * \retval STATUS_ABORTED          If transaction was ended by master before
+ *                                 the entire buffer was transferred
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided
+ * \retval STATUS_ERR_TIMEOUT     If the operation was not completed within the
+ *                                timeout in slave mode
+ * \retval STATUS_ERR_DENIED      If the receiver is not enabled
+ * \retval STATUS_ERR_OVERFLOW    If the data is overflown
+ */
+enum status_code spi_read_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length,
+		uint16_t dummy)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+#  if SPI_CALLBACK_MODE == true
+	if (module->status == STATUS_BUSY) {
+		/* Check if the SPI module is busy with a job */
+		return STATUS_BUSY;
+	}
+#  endif
+
+	/* Sanity check arguments */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) {
+		/* Clear TX complete flag */
+		_spi_clear_tx_complete_flag(module);
+	}
+#  endif
+	uint16_t rx_pos = 0;
+
+	while (length--) {
+#  if CONF_SPI_MASTER_ENABLE == true
+		if (module->mode == SPI_MODE_MASTER) {
+			/* Wait until the module is ready to write a character */
+			while (!spi_is_ready_to_write(module)) {
+			}
+
+			/* Send dummy SPI character to read in master mode */
+			spi_write(module, dummy);
+		}
+#  endif
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+		/* Start timeout period for slave */
+		if (module->mode == SPI_MODE_SLAVE) {
+			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
+				if (spi_is_ready_to_read(module)) {
+					break;
+				}
+			}
+			/* Check if master has ended the transaction */
+			if (spi_is_write_complete(module)) {
+				_spi_clear_tx_complete_flag(module);
+				return STATUS_ABORTED;
+			}
+
+			if (!spi_is_ready_to_read(module)) {
+				/* Not ready to read data within timeout period */
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+#  endif
+
+		/* Wait until the module is ready to read a character */
+		while (!spi_is_ready_to_read(module)) {
+		}
+
+		uint16_t received_data = 0;
+		enum status_code retval = spi_read(module, &received_data);
+
+		if (retval != STATUS_OK) {
+			/* Overflow, abort */
+			return retval;
+		}
+
+		/* Read value will be at least 8-bits long */
+		rx_data[rx_pos++] = received_data;
+
+		/* If 9-bit data, write next received byte to the buffer */
+		if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+			rx_data[rx_pos++] = (received_data >> 8);
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Sends and reads a single SPI character
+ *
+ * This function will transfer a single SPI character via SPI and return the
+ * SPI character that is shifted into the shift register.
+ *
+ * In master mode the SPI character will be sent immediately and the received
+ * SPI character will be read as soon as the shifting of the data is
+ * complete.
+ *
+ * In slave mode this function will place the data to be sent into the transmit
+ * buffer. It will then block until an SPI master has shifted a complete
+ * SPI character, and the received data is available.
+ *
+ * \note The data to be sent might not be sent before the next transfer, as
+ *       loading of the shift register is dependent on SCK.
+ * \note If address matching is enabled for the slave, the first character
+ *       received and placed in the buffer will be the address.
+ *
+ * \param[in]  module   Pointer to the software instance struct
+ * \param[in]  tx_data  SPI character to transmit
+ * \param[out] rx_data  Pointer to store the received SPI character
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK            If the operation was completed
+ * \retval STATUS_ERR_TIMEOUT   If the operation was not completed within the
+ *                              timeout in slave mode
+ * \retval STATUS_ERR_DENIED    If the receiver is not enabled
+ * \retval STATUS_ERR_OVERFLOW  If the incoming data is overflown
+ */
+enum status_code spi_transceive_wait(
+		struct spi_module *const module,
+		uint16_t tx_data,
+		uint16_t *rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#  if SPI_CALLBACK_MODE == true
+	if (module->status == STATUS_BUSY) {
+		/* Check if the SPI module is busy with a job */
+		return STATUS_BUSY;
+	}
+#  endif
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	uint16_t j;
+#  endif
+	enum status_code retval = STATUS_OK;
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	/* Start timeout period for slave */
+	if (module->mode == SPI_MODE_SLAVE) {
+		for (j = 0; j <= SPI_TIMEOUT; j++) {
+			if (spi_is_ready_to_write(module)) {
+				break;
+			} else if (j == SPI_TIMEOUT) {
+				/* Not ready to write data within timeout period */
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+	}
+#  endif
+	/* Wait until the module is ready to write the character */
+	while (!spi_is_ready_to_write(module)) {
+	}
+
+	/* Write data */
+	spi_write(module, tx_data);
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	/* Start timeout period for slave */
+	if (module->mode == SPI_MODE_SLAVE) {
+		for (j = 0; j <= SPI_TIMEOUT; j++) {
+			if (spi_is_ready_to_read(module)) {
+				break;
+			} else if (j == SPI_TIMEOUT) {
+				/* Not ready to read data within timeout period */
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+	}
+#  endif
+
+	/* Wait until the module is ready to read the character */
+	while (!spi_is_ready_to_read(module)) {
+	}
+
+	/* Read data */
+	retval = spi_read(module, rx_data);
+
+	return retval;
+}
+
+ /**
+ * \brief Selects slave device
+ *
+ * This function will drive the slave select pin of the selected device low or
+ * high depending on the select Boolean.
+ * If slave address recognition is enabled, the address will be sent to the
+ * slave when selecting it.
+ *
+ * \param[in] module  Pointer to the software module struct
+ * \param[in] slave   Pointer to the attached slave
+ * \param[in] select  Boolean stating if the slave should be selected or
+ *                    deselected
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                   If the slave device was selected
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If the SPI module is operating in slave
+ *                                     mode
+ * \retval STATUS_BUSY                 If the SPI module is not ready to write
+ *                                     the slave address
+ */
+enum status_code spi_select_slave(
+		struct spi_module *const module,
+		struct spi_slave_inst *const slave,
+		const bool select)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(slave);
+
+	/* Check that the SPI module is operating in master mode */
+	if (module->mode != SPI_MODE_MASTER) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+#  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
+	if(!(module->master_slave_select_enable))
+#  endif
+	{
+		if (select) {
+			/* Check if address recognition is enabled */
+			if (slave->address_enabled) {
+				/* Check if the module is ready to write the address */
+				if (!spi_is_ready_to_write(module)) {
+					/* Not ready, do not select slave and return */
+					port_pin_set_output_level(slave->ss_pin, true);
+					return STATUS_BUSY;
+				}
+
+				/* Drive Slave Select low */
+				port_pin_set_output_level(slave->ss_pin, false);
+
+				/* Write address to slave */
+				spi_write(module, slave->address);
+
+				if (!(module->receiver_enabled)) {
+					/* Flush contents of shift register shifted back from slave */
+					while (!spi_is_ready_to_read(module)) {
+					}
+					uint16_t flush = 0;
+					spi_read(module, &flush);
+				}
+			} else {
+				/* Drive Slave Select low */
+				port_pin_set_output_level(slave->ss_pin, false);
+			}
+		} else {
+			/* Drive Slave Select high */
+			port_pin_set_output_level(slave->ss_pin, true);
+		}
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Sends a buffer of \c length SPI characters
+ *
+ * This function will send a buffer of SPI characters via the SPI
+ * and discard any data that is received. To both send and receive a buffer of
+ * data, use the \ref spi_transceive_buffer_wait function.
+ *
+ * Note that this function does not handle the _SS (slave select) pin(s) in
+ * master mode; this must be handled by the user application.
+ *
+ * \param[in] module   Pointer to the software instance struct
+ * \param[in] tx_data  Pointer to the buffer to transmit
+ * \param[in] length   Number of SPI characters to transfer
+ *
+ * \return Status of the write operation.
+ * \retval STATUS_OK               If the write was completed
+ * \retval STATUS_ABORTED          If transaction was ended by master before
+ *                                 entire buffer was transferred
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_TIMEOUT      If the operation was not completed within the
+ *                                 timeout in slave mode
+ */
+enum status_code spi_write_buffer_wait(
+		struct spi_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+#  if SPI_CALLBACK_MODE == true
+	if (module->status == STATUS_BUSY) {
+		/* Check if the SPI module is busy with a job */
+		return STATUS_BUSY;
+	}
+#  endif
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) {
+		/* Clear TX complete flag */
+		_spi_clear_tx_complete_flag(module);
+	}
+#  endif
+
+	uint16_t tx_pos = 0;
+	uint16_t flush_length = length;
+
+	/* Write block */
+	while (length--) {
+#  if CONF_SPI_SLAVE_ENABLE == true
+		/* Start timeout period for slave */
+		if (module->mode == SPI_MODE_SLAVE) {
+			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
+				if (spi_is_ready_to_write(module)) {
+					break;
+				}
+			}
+			/* Check if master has ended the transaction */
+			if (spi_is_write_complete(module)) {
+				_spi_clear_tx_complete_flag(module);
+				return STATUS_ABORTED;
+			}
+
+			if (!spi_is_ready_to_write(module)) {
+				/* Not ready to write data within timeout period */
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+#  endif
+
+		/* Wait until the module is ready to write a character */
+		while (!spi_is_ready_to_write(module)) {
+		}
+
+		/* Write value will be at least 8-bits long */
+		uint16_t data_to_send = tx_data[tx_pos++];
+
+		/* If 9-bit data, get next byte to send from the buffer */
+		if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+			data_to_send |= (tx_data[tx_pos++] << 8);
+		}
+
+		/* Write the data to send */
+		spi_write(module, data_to_send);
+
+		if (module->receiver_enabled) {
+#  if CONF_SPI_SLAVE_ENABLE == true
+			/* Start timeout period for slave */
+			if (module->mode == SPI_MODE_SLAVE) {
+				for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
+					if (length && spi_is_ready_to_write(module)) {
+						data_to_send = tx_data[tx_pos++];
+						/* If 9-bit data, get next byte to send from the buffer */
+						if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+							data_to_send |= (tx_data[tx_pos++] << 8);
+						}
+
+						/* Write the data to send */
+						spi_write(module, data_to_send);
+						length--;
+					}
+					if (spi_is_ready_to_read(module)) {
+						break;
+					}
+				}
+
+				/* Check if master has ended the transaction */
+				if (spi_is_write_complete(module)) {
+					_spi_clear_tx_complete_flag(module);
+					return STATUS_ABORTED;
+				}
+
+				if (!spi_is_ready_to_read(module)) {
+					/* Not ready to read data within timeout period */
+					return STATUS_ERR_TIMEOUT;
+				}
+			}
+#  endif
+
+			while (!spi_is_ready_to_read(module)) {
+			}
+
+			/* Flush read buffer */
+			uint16_t flush;
+			spi_read(module, &flush);
+			flush_length--;
+		}
+	}
+
+#  if CONF_SPI_MASTER_ENABLE == true
+	if (module->mode == SPI_MODE_MASTER) {
+		/* Wait for last byte to be transferred */
+		while (!spi_is_write_complete(module)) {
+		}
+	}
+#  endif
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if (module->mode == SPI_MODE_SLAVE) {
+		if (module->receiver_enabled) {
+			while (flush_length) {
+				/* Start timeout period for slave */
+				for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
+					if (spi_is_ready_to_read(module)) {
+						break;
+					}
+				}
+				if (!spi_is_ready_to_read(module)) {
+					/* Not ready to read data within timeout period */
+					return STATUS_ERR_TIMEOUT;
+				}
+				/* Flush read buffer */
+				uint16_t flush;
+				spi_read(module, &flush);
+				flush_length--;
+			}
+		}
+	}
+#  endif
+	return STATUS_OK;
+}
+
+/**
+ * \brief Sends and receives a buffer of \c length SPI characters
+ *
+ * This function will send and receive a buffer of data via the SPI.
+ *
+ * In master mode the SPI characters will be sent immediately and the
+ * received SPI character will  be read as soon as the shifting of the SPI
+ * character is complete.
+ *
+ * In slave mode this function will place the data to be sent into the transmit
+ * buffer. It will then block until an SPI master has shifted the complete
+ * buffer and the received data is available.
+ *
+ * \param[in]  module   Pointer to the software instance struct
+ * \param[in]  tx_data  Pointer to the buffer to transmit
+ * \param[out] rx_data  Pointer to the buffer where received data will be stored
+ * \param[in]  length   Number of SPI characters to transfer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK               If the operation was completed
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_TIMEOUT      If the operation was not completed within the
+ *                                 timeout in slave mode
+ * \retval STATUS_ERR_DENIED       If the receiver is not enabled
+ * \retval STATUS_ERR_OVERFLOW     If the data is overflown
+ */
+enum status_code spi_transceive_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+#  if SPI_CALLBACK_MODE == true
+	if (module->status == STATUS_BUSY) {
+		/* Check if the SPI module is busy with a job */
+		return STATUS_BUSY;
+	}
+#  endif
+
+	/* Sanity check arguments */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) {
+		/* Clear TX complete flag */
+		_spi_clear_tx_complete_flag(module);
+	}
+#  endif
+
+	uint16_t tx_pos = 0;
+	uint16_t rx_pos = 0;
+	uint16_t rx_length = length;
+
+	/* Send and receive buffer */
+	while (length--) {
+#  if CONF_SPI_SLAVE_ENABLE == true
+		/* Start timeout period for slave */
+		if (module->mode == SPI_MODE_SLAVE) {
+			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
+				if (spi_is_ready_to_write(module)) {
+					break;
+				}
+			}
+			/* Check if master has ended the transaction */
+			if (spi_is_write_complete(module)) {
+				_spi_clear_tx_complete_flag(module);
+				return STATUS_ABORTED;
+			}
+
+			if (!spi_is_ready_to_write(module)) {
+				/* Not ready to write data within timeout period */
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+#  endif
+
+		/* Wait until the module is ready to write a character */
+		while (!spi_is_ready_to_write(module)) {
+		}
+
+		/* Write value will be at least 8-bits long */
+		uint16_t data_to_send = tx_data[tx_pos++];
+
+		/* If 9-bit data, get next byte to send from the buffer */
+		if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+			data_to_send |= (tx_data[tx_pos++] << 8);
+		}
+
+		/* Write the data to send */
+		spi_write(module, data_to_send);
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+		/* Start timeout period for slave */
+		if (module->mode == SPI_MODE_SLAVE) {
+			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
+				if (spi_is_ready_to_write(module)) {
+					data_to_send = tx_data[tx_pos++];
+					/* If 9-bit data, get next byte to send from the buffer */
+					if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+						data_to_send |= (tx_data[tx_pos++] << 8);
+					}
+
+					/* Write the data to send */
+					spi_write(module, data_to_send);
+					length--;
+				}
+				if (spi_is_ready_to_read(module)) {
+					break;
+				}
+			}
+			/* Check if master has ended the transaction */
+			if (spi_is_write_complete(module)) {
+				_spi_clear_tx_complete_flag(module);
+				return STATUS_ABORTED;
+			}
+
+			if (!spi_is_ready_to_read(module)) {
+				/* Not ready to read data within timeout period */
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+#  endif
+
+		/* Wait until the module is ready to read a character */
+		while (!spi_is_ready_to_read(module)) {
+		}
+
+		enum status_code retval;
+		uint16_t received_data = 0;
+		rx_length--;
+
+		retval = spi_read(module, &received_data);
+
+		if (retval != STATUS_OK) {
+			/* Overflow, abort */
+			return retval;
+		}
+
+		/* Read value will be at least 8-bits long */
+		rx_data[rx_pos++] = received_data;
+
+		/* If 9-bit data, write next received byte to the buffer */
+		if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+			rx_data[rx_pos++] = (received_data >> 8);
+		}
+	}
+
+#  if CONF_SPI_MASTER_ENABLE == true
+	if (module->mode == SPI_MODE_MASTER) {
+		/* Wait for last byte to be transferred */
+		while (!spi_is_write_complete(module)) {
+		}
+	}
+#  endif
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if (module->mode == SPI_MODE_SLAVE) {
+		while (rx_length) {
+			/* Start timeout period for slave */
+			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
+				if (spi_is_ready_to_read(module)) {
+					break;
+				}
+			}
+			if (!spi_is_ready_to_read(module)) {
+				/* Not ready to read data within timeout period */
+				return STATUS_ERR_TIMEOUT;
+			}
+			enum status_code retval;
+			uint16_t received_data = 0;
+			rx_length--;
+
+			retval = spi_read(module, &received_data);
+
+			if (retval != STATUS_OK) {
+				/* Overflow, abort */
+				return retval;
+			}
+			/* Read value will be at least 8-bits long */
+			rx_data[rx_pos++] = received_data;
+
+			/* If 9-bit data, write next received byte to the buffer */
+			if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+				rx_data[rx_pos++] = (received_data >> 8);
+			}
+		}
+	}
+#  endif
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.h
new file mode 100644
index 0000000000..81a55ec9e2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.h
@@ -0,0 +1,1808 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SPI_H_INCLUDED
+#define SPI_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_sercom_spi_group SAM Serial Peripheral Interface (SERCOM SPI) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the SERCOM module in
+ * its SPI mode to transfer SPI  data frames. The following driver API modes
+ * are covered by this manual:
+ *
+ * - Polled APIs
+ * \if SPI_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_spi_prerequisites
+ * - \ref asfdoc_sam0_sercom_spi_module_overview
+ * - \ref asfdoc_sam0_sercom_spi_special_considerations
+ * - \ref asfdoc_sam0_sercom_spi_extra_info
+ * - \ref asfdoc_sam0_sercom_spi_examples
+ * - \ref asfdoc_sam0_sercom_spi_api_overview
+ *
+ * \section asfdoc_sam0_sercom_spi_prerequisites Prerequisites
+ * There are no prerequisites.
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_module_overview Module Overview
+ * The Serial Peripheral Interface (SPI) is a high-speed synchronous data
+ * transfer interface using three or four pins. It allows fast communication
+ * between a master device and one or more peripheral devices.
+ *
+ * A device connected to the bus must act as a master or a slave. The master
+ * initiates and controls all data transactions.
+ * The SPI master initiates a communication cycle by pulling low the Slave
+ * Select (SS) pin of the desired slave. The Slave Select pin is active low.
+ * Master and slave prepare data to be sent in their respective shift
+ * registers, and the master generates the required clock pulses on the SCK
+ * line to interchange data. Data is always shifted from master to slave on
+ * the Master Out - Slave In (MOSI) line, and from slave to master on the
+ * Master In - Slave Out (MISO) line. After each data transfer, the master can
+ * synchronize to the slave by pulling the SS line high.
+ *
+ * \subsection asfdoc_sam0_sercom_spi_module_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver feature macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_SPI_SLAVE_SELECT_LOW_DETECT</td>
+ *    <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_SPI_HARDWARE_SLAVE_SELECT</td>
+ *    <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_SPI_ERROR_INTERRUPT</td>
+ *    <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_SPI_SYNC_SCHEME_VERSION_2</td>
+ *    <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_sercom_spi_bus SPI Bus Connection
+ * In \ref asfdoc_sam0_spi_connection_example "the figure below", the
+ * connection between one master and one slave is shown.
+ *
+ * \anchor asfdoc_sam0_spi_connection_example
+ * \dot
+ * digraph spi_slaves_par {
+ *   subgraph cluster_spi_master {
+ *    shift_reg [label="Shift register", shape=box];
+ *    mosi_m [label="MOSI", shape=none];
+ *    miso_m [label="MISO", shape=none];
+ *    sck_m [label="SCK", shape=none];
+ *    ss_m [label="GPIO pin", shape=none];
+ *    {rank=same; mosi_m miso_m sck_m ss_m}
+ *    label="SPI Master";
+ *   }
+ *   subgraph cluster_spi_slave {
+ *    mosi_s [label="MOSI", shape=none];
+ *    miso_s [label="MISO", shape=none];
+ *    sck_s [label="SCK", shape=none];
+ *    ss_s [label="SS", shape=none];
+ *    shift_reg_s [label="Shift register", shape=box];
+ *    {rank=same; mosi_s miso_s sck_s ss_s}
+ *    label="SPI Slave";
+ *    rankdir=LR;
+ *   }
+ *   shift_reg:e -> mosi_m:w [label=""];
+ *   mosi_m:e -> mosi_s:w [label=""];
+ *   mosi_s:e -> shift_reg_s:w [label=""];
+ *   miso_s:w -> miso_m:e [label=""];
+ *   sck_m -> sck_s;
+ *   ss_m -> ss_s;
+ *   shift_reg_s:se -> miso_s:e [label=""];
+ *   miso_m:w -> shift_reg:sw [label=""];
+ *   rankdir=LR;
+ * }
+ * \enddot
+ *
+ * The different lines are as follows:
+ * - \b MISO Master Input Slave Output. The line where the data is shifted
+ *   out from the slave and into the master.
+ * - \b MOSI Master Output Slave Input. The line where the data is shifted
+ *   out from the master and into the slave.
+ * - \b SCK Serial Clock. Generated by the master device.
+ * - \b SS Slave Select. To initiate a transaction, the master must pull this
+ *      line low.
+ *
+ * If the bus consists of several SPI slaves, they can be connected in parallel
+ * and the SPI master can use general I/O pins to control separate SS lines to
+ * each slave on the bus.
+ *
+ * It is also possible to connect all slaves in series. In this configuration,
+ * a common SS is provided to \c N slaves, enabling them simultaneously. The
+ * MISO from the \c N-1 slaves is connected to the MOSI on the next slave. The
+ * \c N<SUP>th</SUP> slave connects its MISO back to the master. For a
+ * complete transaction, the master must shift \c N+1 characters.
+ *
+ * \subsection asfdoc_sam0_sercom_spi_chsize SPI Character Size
+ * The SPI character size is configurable to eight or nine bits.
+ *
+ * \subsection asfdoc_sam0_sercom_spi_master_mode Master Mode
+ * When configured as a master, the SS pin will be configured as an output.
+ *
+ * \subsubsection asfdoc_sam0_sercom_spi_master_mode_data_transfer Data Transfer
+ * Writing a character will start the SPI clock generator, and
+ * the character is transferred to the shift register when the shift
+ * register is empty.
+ * Once this is done, a new character can be written.
+ * As each character is shifted out from the master, a character is shifted in
+ * from the slave. If the receiver is enabled, the data is moved to the receive
+ * buffer at the completion of the frame and can be read.
+ *
+ * \subsection asfdoc_sam0_sercom_spi_slave_mode Slave Mode
+ * When configured as a slave, the SPI interface will remain inactive with MISO
+ * tri-stated as long as the SS pin is driven high.
+ *
+ * \subsubsection asfdoc_sam0_sercom_spi_slave_mode_data_transfer_slave Data Transfer
+ * The data register can be updated at any time.
+ * As the SPI slave shift register is clocked by SCK, a minimum of three SCK
+ * cycles are needed from the time new data is written, until the character is
+ * ready to be shifted out. If the shift register has not been loaded with
+ * data, the current contents will be transmitted.
+ *
+ * If constant transmission of data is needed in SPI slave mode, the system
+ * clock should be faster than SCK.
+ * If the receiver is enabled, the received character can be read from the
+ * receive buffer. When SS line is driven high, the slave will not receive any
+ * additional data.
+ *
+ * \subsubsection asfdoc_sam0_sercom_spi_slave_mode_addr_recognition Address Recognition
+ * When the SPI slave is configured with address recognition, the first
+ * character in a transaction is checked for an address match. If there is a
+ * match, the MISO output is enabled and the transaction is processed.
+ * If the address does not match, the complete transaction is ignored.
+ *
+ * If the device is asleep, it can be woken up by an address match in order
+ * to process the transaction.
+ *
+ * \note In master mode, an address packet is written by the
+ *       \ref spi_select_slave function if the address_enabled configuration is
+ *       set in the \ref spi_slave_inst_config struct.
+ *
+ * \subsection asfdoc_sam0_sercom_spi_data_modes Data Modes
+ * There are four combinations of SCK phase and polarity with respect to
+ * serial data. \ref asfdoc_sam0_spi_mode_table "The table below" shows the
+ * clock polarity (CPOL) and clock phase (CPHA) in the different modes.
+ * <i>Leading edge</i> is the first clock edge in a clock cycle and
+ * <i>trailing edge</i> is the last clock edge in a clock cycle.
+ *
+ * \anchor asfdoc_sam0_spi_mode_table
+ * <table>
+ *   <caption>SPI Data Modes</caption>
+ *   <tr>
+ *      <th>Mode</th>
+ *      <th>CPOL</th>
+ *      <th>CPHA</th>
+ *      <th>Leading Edge</th>
+ *      <th>Trailing Edge</th>
+ *   </tr>
+ *   <tr>
+ *      <td> 0 </td>
+ *      <td> 0 </td>
+ *      <td> 0 </td>
+ *      <td> Rising, Sample </td>
+ *      <td> Falling, Setup </td>
+ *   </tr>
+ *   <tr>
+ *      <td> 1 </td>
+ *      <td> 0 </td>
+ *      <td> 1 </td>
+ *      <td> Rising, Setup </td>
+ *      <td> Falling, Sample </td>
+ *   </tr>
+ *   <tr>
+ *      <td> 2 </td>
+ *      <td> 1 </td>
+ *      <td> 0 </td>
+ *      <td> Falling, Sample </td>
+ *      <td> Rising, Setup </td>
+ *   </tr>
+ *   <tr>
+ *      <td> 3 </td>
+ *      <td> 1 </td>
+ *      <td> 1 </td>
+ *      <td> Falling, Setup </td>
+ *      <td> Rising, Sample </td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \subsection asfdoc_sam0_sercom_spi_pads SERCOM Pads
+ * The SERCOM pads are automatically configured as seen in
+ * \ref asfdoc_sam0_spi_sercom_pad_table "the table below". If the receiver
+ * is disabled, the data input (MISO for master, MOSI for slave) can be used
+ * for other purposes.
+ *
+ * In master mode, the SS pin(s) must be configured using the \ref spi_slave_inst
+ * struct.
+ *
+ * \anchor asfdoc_sam0_spi_sercom_pad_table
+ * <table>
+ *   <caption>SERCOM SPI Pad Usages</caption>
+ *   <tr>
+ *      <th> Pin </th>
+ *      <th> Master SPI </th>
+ *      <th> Slave SPI </th>
+ *   </tr>
+ *   <tr>
+ *      <td> MOSI </td>
+ *      <td> Output </td>
+ *      <td> Input </td>
+ *   </tr>
+ *   <tr>
+ *      <td> MISO </td>
+ *      <td> Input </td>
+ *      <td> Output </td>
+ *   </tr>
+ *   <tr>
+ *      <td> SCK </td>
+ *      <td> Output </td>
+ *      <td> Input </td>
+ *   </tr>
+ *   <tr>
+ *      <td> SS </td>
+ *      <td> User defined output enable </td>
+ *      <td> Input </td>
+ *   </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_sercom_spi_sleep_modes Operation in Sleep Modes
+ * The SPI module can operate in all sleep modes by setting the run_in_standby
+ * option in the \ref spi_config struct. The operation in slave and master mode
+ * is shown in the table below.
+ * <table>
+ *   <tr>
+ *      <th> run_in_standby </th>
+ *      <th> Slave </th>
+ *      <th> Master </th>
+ *   </tr>
+ *   <tr>
+ *      <td> false </td>
+ *      <td> Disabled, all reception is dropped </td>
+ *      <td> GCLK is disabled when master is idle, wake on transmit complete </td>
+ *   </tr>
+ *   <tr>
+ *      <td> true </td>
+ *      <td> Wake on reception </td>
+ *      <td> GCLK is enabled while in sleep modes, wake on all interrupts </td>
+ *   </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_sercom_spi_clock_generation Clock Generation
+ * In SPI master mode, the clock (SCK) is generated internally using the
+ * SERCOM baudrate generator. In SPI slave mode, the clock is provided by
+ * an external master on the SCK pin. This clock is used to directly clock
+ * the SPI shift register.
+ *
+ * \section asfdoc_sam0_sercom_spi_special_considerations Special Considerations
+ * \subsection pin_mux pinmux Settings
+ * The pin MUX settings must be configured properly, as not all settings
+ * can be used in different modes of operation.
+ *
+ * \section asfdoc_sam0_sercom_spi_extra_info Extra Information
+ * For extra information, see \ref asfdoc_sam0_sercom_spi_extra. This includes:
+ * - \ref asfdoc_sam0_sercom_spi_extra_acronyms
+ * - \ref asfdoc_sam0_sercom_spi_extra_dependencies
+ * - \ref asfdoc_sam0_sercom_spi_extra_workarounds
+ * - \ref asfdoc_sam0_sercom_spi_extra_history
+ *
+ * \section asfdoc_sam0_sercom_spi_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_spi_exqsg.
+ *
+ * \section asfdoc_sam0_sercom_spi_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <port.h>
+#include <sercom.h>
+#include <pinmux.h>
+#include <string.h>
+#include <conf_spi.h>
+
+#  if SPI_CALLBACK_MODE == true
+#  include <sercom_interrupt.h>
+#  endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (CONF_SPI_MASTER_ENABLE == false) && (CONF_SPI_SLAVE_ENABLE == false)
+#error "Not possible compile SPI driver, invalid driver configuration. Make sure that either/both CONF_SPI_MASTER_ENABLE/CONF_SPI_SLAVE_ENABLE is set to true."
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define SERCOM SPI features set according to different device family.
+ * @{
+ */
+#  if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAML21) || (SAMDA1) || (SAMHA1) ||\
+	  (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__)
+/** SPI slave select low detection. */
+#  define FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+/** Slave select can be controlled by hardware. */
+#  define FEATURE_SPI_HARDWARE_SLAVE_SELECT
+/** SPI with error detect feature. */
+#  define FEATURE_SPI_ERROR_INTERRUPT
+/** SPI sync scheme version 2. */
+#  define FEATURE_SPI_SYNC_SCHEME_VERSION_2
+#  endif
+/*@}*/
+
+#  ifndef PINMUX_DEFAULT
+/** Default pinmux. */
+#  define PINMUX_DEFAULT 0
+#  endif
+
+#  ifndef PINMUX_UNUSED
+/** Unused pinmux. */
+#  define PINMUX_UNUSED 0xFFFFFFFF
+#  endif
+
+#  ifndef SPI_TIMEOUT
+/** SPI timeout value. */
+#  define SPI_TIMEOUT 10000
+#  endif
+
+#  if SPI_CALLBACK_MODE == true
+/**
+ * \brief SPI Callback enum
+ *
+ * Callbacks for SPI callback driver.
+ *
+ * \note For slave mode, these callbacks will be called when a transaction
+ * is ended by the master pulling Slave Select high.
+ *
+ */
+enum spi_callback {
+	/** Callback for buffer transmitted */
+	SPI_CALLBACK_BUFFER_TRANSMITTED,
+	/** Callback for buffer received */
+	SPI_CALLBACK_BUFFER_RECEIVED,
+	/** Callback for buffers transceived */
+	SPI_CALLBACK_BUFFER_TRANSCEIVED,
+	/** Callback for error */
+	SPI_CALLBACK_ERROR,
+	/**
+	* Callback for transmission ended by master before the entire buffer was
+	* read or written from slave
+	*/
+	SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE,
+#  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+	/** Callback for  slave select low */
+	SPI_CALLBACK_SLAVE_SELECT_LOW,
+#  endif
+#  ifdef FEATURE_SPI_ERROR_INTERRUPT
+	/** Callback for combined error happen */
+	SPI_CALLBACK_COMBINED_ERROR,
+#  endif
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	SPI_CALLBACK_N,
+#  endif
+};
+#  endif
+
+#if SPI_CALLBACK_MODE == true
+#  if !defined(__DOXYGEN__)
+/**
+ * \internal SPI transfer directions
+ */
+enum _spi_direction {
+	/** Transfer direction is read */
+	SPI_DIRECTION_READ,
+	/** Transfer direction is write */
+	SPI_DIRECTION_WRITE,
+	/** Transfer direction is read and write */
+	SPI_DIRECTION_BOTH,
+	/** No transfer */
+	SPI_DIRECTION_IDLE,
+};
+#  endif
+#endif
+
+/**
+ * \brief SPI Interrupt Flags
+ *
+ * Interrupt flags for the SPI module.
+ *
+ */
+enum spi_interrupt_flag {
+	/**
+	 * This flag is set when the contents of the data register has been moved
+	 * to the shift register and the data register is ready for new data
+	 */
+	SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY = SERCOM_SPI_INTFLAG_DRE,
+	/**
+	 * This flag is set when the contents of the shift register has been
+	 * shifted out
+	 */
+	SPI_INTERRUPT_FLAG_TX_COMPLETE         = SERCOM_SPI_INTFLAG_TXC,
+	/** This flag is set when data has been shifted into the data register */
+	SPI_INTERRUPT_FLAG_RX_COMPLETE         = SERCOM_SPI_INTFLAG_RXC,
+#  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+	/** This flag is set when slave select low  */
+	SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW         = SERCOM_SPI_INTFLAG_SSL,
+#  endif
+#  ifdef FEATURE_SPI_ERROR_INTERRUPT
+	/** This flag is set when combined error happen */
+	SPI_INTERRUPT_FLAG_COMBINED_ERROR         = SERCOM_SPI_INTFLAG_ERROR,
+#  endif
+};
+
+/**
+ * \brief SPI transfer modes enum
+ *
+ * SPI transfer mode.
+ */
+enum spi_transfer_mode {
+	/** Mode 0. Leading edge: rising, sample. Trailing edge: falling, setup */
+	SPI_TRANSFER_MODE_0 = 0,
+	/** Mode 1. Leading edge: rising, setup. Trailing edge: falling, sample */
+	SPI_TRANSFER_MODE_1 = SERCOM_SPI_CTRLA_CPHA,
+	/** Mode 2. Leading edge: falling, sample. Trailing edge: rising, setup */
+	SPI_TRANSFER_MODE_2 = SERCOM_SPI_CTRLA_CPOL,
+	/** Mode 3. Leading edge: falling, setup. Trailing edge: rising, sample */
+	SPI_TRANSFER_MODE_3 = SERCOM_SPI_CTRLA_CPHA | SERCOM_SPI_CTRLA_CPOL,
+};
+
+/**
+ * \brief SPI frame format enum
+ *
+ * Frame format for slave mode.
+ */
+enum spi_frame_format {
+	/** SPI frame */
+	SPI_FRAME_FORMAT_SPI_FRAME      = SERCOM_SPI_CTRLA_FORM(0),
+	/** SPI frame with address */
+	SPI_FRAME_FORMAT_SPI_FRAME_ADDR = SERCOM_SPI_CTRLA_FORM(2),
+};
+
+/**
+ * \brief SPI signal MUX settings
+ *
+ * Set the functionality of the SERCOM pins. As not all combinations can be used
+ * in different modes of operation, proper combinations must be chosen according
+ * to the rest of the configuration.
+ *
+ * \note In master operation: DI is MISO, DO is MOSI.
+ *       In slave operation: DI is MOSI, DO is MISO.
+ *
+ * See \ref asfdoc_sam0_sercom_spi_mux_settings for a description of the
+ * various MUX setting options.
+ */
+enum spi_signal_mux_setting {
+	/** SPI MUX combination A. DOPO: 0x0, DIPO: 0x0 */
+	SPI_SIGNAL_MUX_SETTING_A =
+			(0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination B. DOPO: 0x0, DIPO: 0x1 */
+	SPI_SIGNAL_MUX_SETTING_B =
+			(0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination C. DOPO: 0x0, DIPO: 0x2 */
+	SPI_SIGNAL_MUX_SETTING_C =
+			(0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination D. DOPO: 0x0, DIPO: 0x3 */
+	SPI_SIGNAL_MUX_SETTING_D =
+			(0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination E. DOPO: 0x1, DIPO: 0x0 */
+	SPI_SIGNAL_MUX_SETTING_E =
+			(0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination F. DOPO: 0x1, DIPO: 0x1 */
+	SPI_SIGNAL_MUX_SETTING_F =
+			(0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination G. DOPO: 0x1, DIPO: 0x2 */
+	SPI_SIGNAL_MUX_SETTING_G =
+			(0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination H. DOPO: 0x1, DIPO: 0x3 */
+	SPI_SIGNAL_MUX_SETTING_H =
+			(0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination I. DOPO: 0x2, DIPO: 0x0 */
+	SPI_SIGNAL_MUX_SETTING_I =
+			(0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination J. DOPO: 0x2, DIPO: 0x1 */
+	SPI_SIGNAL_MUX_SETTING_J =
+			(0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination K. DOPO: 0x2, DIPO: 0x2 */
+	SPI_SIGNAL_MUX_SETTING_K =
+			(0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination L. DOPO: 0x2, DIPO: 0x3 */
+	SPI_SIGNAL_MUX_SETTING_L =
+			(0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination M. DOPO: 0x3, DIPO: 0x0 */
+	SPI_SIGNAL_MUX_SETTING_M =
+			(0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination N. DOPO: 0x3, DIPO: 0x1 */
+	SPI_SIGNAL_MUX_SETTING_N =
+			(0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination O. DOPO: 0x3, DIPO: 0x2 */
+	SPI_SIGNAL_MUX_SETTING_O =
+			(0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
+	/** SPI MUX combination P. DOPO: 0x3, DIPO: 0x3 */
+	SPI_SIGNAL_MUX_SETTING_P =
+			(0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+			(0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
+};
+
+/**
+ * \brief SPI address modes enum
+ *
+ * For slave mode when using the SPI frame with address format.
+ *
+ */
+enum spi_addr_mode {
+	/**
+	 * \c address_mask in the \ref spi_config struct is used as a mask to the register
+	 */
+	SPI_ADDR_MODE_MASK      = SERCOM_SPI_CTRLB_AMODE(0),
+	/**
+	 * The slave responds to the two unique addresses in \c address and
+	 * \c address_mask in the \ref spi_config struct
+	 */
+	SPI_ADDR_MODE_UNIQUE    = SERCOM_SPI_CTRLB_AMODE(1),
+	/**
+	 * The slave responds to the range of addresses between and including \c address
+	 * and \c address_mask in the \ref spi_config struct
+	 */
+	SPI_ADDR_MODE_RANGE     = SERCOM_SPI_CTRLB_AMODE(2),
+};
+
+/**
+ * \brief SPI modes enum
+ *
+ * SPI mode selection.
+ */
+enum spi_mode {
+	/** Master mode */
+	SPI_MODE_MASTER         = 1,
+	/** Slave mode */
+	SPI_MODE_SLAVE          = 0,
+};
+
+/**
+ * \brief SPI data order enum
+ *
+ * SPI data order.
+ *
+ */
+enum spi_data_order {
+	/** The LSB of the data is transmitted first */
+	SPI_DATA_ORDER_LSB      = SERCOM_SPI_CTRLA_DORD,
+	/** The MSB of the data is transmitted first */
+	SPI_DATA_ORDER_MSB      = 0,
+};
+
+/**
+ * \brief SPI character size enum
+ *
+ * SPI character size.
+ *
+ */
+enum spi_character_size {
+	/** 8-bit character */
+	SPI_CHARACTER_SIZE_8BIT = SERCOM_SPI_CTRLB_CHSIZE(0),
+	/** 9-bit character */
+	SPI_CHARACTER_SIZE_9BIT = SERCOM_SPI_CTRLB_CHSIZE(1),
+};
+
+#  if SPI_CALLBACK_MODE == true
+/** Prototype for the device instance */
+struct spi_module;
+
+/** Type of the callback functions */
+typedef void (*spi_callback_t)(struct spi_module *const module);
+
+#  if !defined(__DOXYGEN__)
+/** Prototype for the interrupt handler */
+extern void _spi_interrupt_handler(uint8_t instance);
+#  endif
+#  endif
+
+/**
+ * \brief SERCOM SPI driver software device instance structure.
+ *
+ * SERCOM SPI driver software instance structure, used to retain software state
+ * information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct spi_module {
+#  if !defined(__DOXYGEN__)
+	/** SERCOM hardware module */
+	Sercom *hw;
+	/** Module lock */
+	volatile bool locked;
+	/** SPI mode */
+	enum spi_mode mode;
+	/** SPI character size */
+	enum spi_character_size character_size;
+	/** Receiver enabled */
+	bool receiver_enabled;
+#  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
+	/** Enable Hardware Slave Select */
+	bool master_slave_select_enable;
+#  endif
+#  if SPI_CALLBACK_MODE == true
+	/** Direction of transaction */
+	volatile enum _spi_direction dir;
+	/** Array to store callback function pointers in */
+	spi_callback_t callback[SPI_CALLBACK_N];
+	/** Buffer pointer to where the next received character will be put */
+	volatile uint8_t *rx_buffer_ptr;
+	/** Buffer pointer to where the next character will be transmitted from
+	**/
+	volatile uint8_t *tx_buffer_ptr;
+	/** Remaining characters to receive */
+	volatile uint16_t remaining_rx_buffer_length;
+	/** Remaining dummy characters to send when reading */
+	volatile uint16_t remaining_dummy_buffer_length;
+	/** Remaining characters to transmit */
+	volatile uint16_t remaining_tx_buffer_length;
+	/** Bit mask for callbacks registered */
+	uint8_t registered_callback;
+	/** Bit mask for callbacks enabled */
+	uint8_t enabled_callback;
+	/** Holds the status of the ongoing or last operation */
+	volatile enum status_code status;
+#  endif
+#  endif
+};
+
+/**
+ * \brief SPI peripheral slave instance structure
+ *
+ * SPI peripheral slave software instance structure, used to configure the
+ * correct SPI transfer mode settings for an attached slave. See
+ * \ref spi_select_slave.
+ */
+struct spi_slave_inst {
+	/** Pin to use as slave select */
+	uint8_t ss_pin;
+	/** Address recognition enabled in slave device */
+	bool address_enabled;
+	/** Address of slave device */
+	uint8_t address;
+};
+
+/**
+ * \brief SPI peripheral slave configuration structure
+ *
+ * SPI Peripheral slave configuration structure.
+ */
+struct spi_slave_inst_config {
+	/** Pin to use as slave select */
+	uint8_t ss_pin;
+	/** Enable address */
+	bool address_enabled;
+	/** Address of slave */
+	uint8_t address;
+};
+
+/**
+ * \brief SPI Master configuration structure
+ *
+ * SPI Master configuration structure.
+ */
+struct spi_master_config {
+	/** Baud rate */
+	uint32_t baudrate;
+};
+
+/**
+ * \brief SPI slave configuration structure
+ *
+ * SPI slave configuration structure.
+ */
+struct spi_slave_config {
+	/** Frame format */
+	enum spi_frame_format frame_format;
+	/** Address mode */
+	enum spi_addr_mode address_mode;
+	/** Address */
+	uint8_t address;
+	/** Address mask */
+	uint8_t address_mask;
+	/** Preload data to the shift register while SS is high */
+	bool preload_enable;
+};
+
+/**
+ * \brief SPI configuration structure
+ *
+ * Configuration structure for an SPI instance. This structure should be
+ * initialized by the \ref spi_get_config_defaults function before being
+ * modified by the user application.
+ */
+struct spi_config {
+	/** SPI mode */
+	enum spi_mode mode;
+	/** Data order */
+	enum spi_data_order data_order;
+	/** Transfer mode */
+	enum spi_transfer_mode transfer_mode;
+	/** MUX setting */
+	enum spi_signal_mux_setting mux_setting;
+	/** SPI character size */
+	enum spi_character_size character_size;
+	/** Enabled in sleep modes */
+	bool run_in_standby;
+	/** Enable receiver */
+	bool receiver_enable;
+#  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+	/** Enable Slave Select Low Detect */
+	bool select_slave_low_detect_enable;
+#  endif
+#  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
+	/** Enable Master Slave Select */
+	bool master_slave_select_enable;
+#  endif
+	/** Union for slave or master specific configuration */
+	union {
+		/** Slave specific configuration */
+		struct spi_slave_config slave;
+		/** Master specific configuration */
+		struct spi_master_config master;
+	} mode_specific;
+	/** GCLK generator to use as clock source */
+	enum gclk_generator generator_source;
+	/** PAD0 pinmux */
+	uint32_t pinmux_pad0;
+	/** PAD1 pinmux */
+	uint32_t pinmux_pad1;
+	/** PAD2 pinmux */
+	uint32_t pinmux_pad2;
+	/** PAD3 pinmux */
+	uint32_t pinmux_pad3;
+};
+
+/**
+ * \brief Determines if the SPI module is currently synchronizing to the bus.
+ *
+ * This function will check if the underlying hardware peripheral module is
+ * currently synchronizing across multiple clock domains to the hardware bus.
+ * This function can be used to delay further operations on the module until it
+ * is ready.
+ *
+ * \param[in]  module  SPI hardware module
+ *
+ * \return Synchronization status of the underlying hardware module.
+ * \retval true   Module synchronization is ongoing
+ * \retval false  Module synchronization is not ongoing
+ *
+ */
+static inline bool spi_is_syncing(
+		struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+#  ifdef FEATURE_SPI_SYNC_SCHEME_VERSION_2
+	/* Return synchronization status */
+	return (spi_module->SYNCBUSY.reg);
+#  else
+	/* Return synchronization status */
+	return (spi_module->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY);
+#  endif
+}
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+
+/**
+ * \brief Initializes an SPI configuration structure to default values
+ *
+ * This function will initialize a given SPI configuration structure to a set
+ * of known default values. This function should be called on any new
+ * instance of the configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Master mode enabled
+ *  \li MSB of the data is transmitted first
+ *  \li Transfer mode 0
+ *  \li MUX Setting D
+ *  \li Character size eight bits
+ *  \li Not enabled in sleep mode
+ *  \li Receiver enabled
+ *  \li Baudrate 100000
+ *  \li Default pinmux settings for all pads
+ *  \li GCLK generator 0
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void spi_get_config_defaults(
+		struct spi_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->mode             = SPI_MODE_MASTER;
+	config->data_order       = SPI_DATA_ORDER_MSB;
+	config->transfer_mode    = SPI_TRANSFER_MODE_0;
+	config->mux_setting      = SPI_SIGNAL_MUX_SETTING_D;
+	config->character_size   = SPI_CHARACTER_SIZE_8BIT;
+	config->run_in_standby   = false;
+	config->receiver_enable  = true;
+#  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+	config->select_slave_low_detect_enable= true;
+#  endif
+#  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
+	config->master_slave_select_enable= false;
+#  endif
+	config->generator_source = GCLK_GENERATOR_0;
+
+	/* Clear mode specific config */
+	memset(&(config->mode_specific), 0, sizeof(config->mode_specific));
+
+	/* Master config defaults */
+	config->mode_specific.master.baudrate = 100000;
+
+	/* pinmux config defaults */
+	config->pinmux_pad0 = PINMUX_DEFAULT;
+	config->pinmux_pad1 = PINMUX_DEFAULT;
+	config->pinmux_pad2 = PINMUX_DEFAULT;
+	config->pinmux_pad3 = PINMUX_DEFAULT;
+
+};
+
+/**
+ * \brief Initializes an SPI peripheral slave device configuration structure to default values
+ *
+ * This function will initialize a given SPI slave device configuration
+ * structure to a set of known default values. This function should be called
+ * on any new instance of the configuration structures before being modified by
+ * the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Slave Select on GPIO pin 10
+ *  \li Addressing not enabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void spi_slave_inst_get_config_defaults(
+		struct spi_slave_inst_config *const config)
+{
+	Assert(config);
+
+	config->ss_pin          = 10;
+	config->address_enabled = false;
+	config->address         = 0;
+}
+
+/**
+ * \brief Attaches an SPI peripheral slave
+ *
+ * This function will initialize the software SPI peripheral slave, based on
+ * the values of the config struct. The slave can then be selected and
+ * optionally addressed by the \ref spi_select_slave function.
+ *
+ * \param[out] slave   Pointer to the software slave instance struct
+ * \param[in]  config  Pointer to the config struct
+ *
+ */
+static inline void spi_attach_slave(
+		struct spi_slave_inst *const slave,
+		const struct spi_slave_inst_config *const config)
+{
+	Assert(slave);
+	Assert(config);
+
+	slave->ss_pin          = config->ss_pin;
+	slave->address_enabled = config->address_enabled;
+	slave->address         = config->address;
+
+	/* Get default config for pin */
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Edit config to set the pin as output */
+	pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+
+	/* Set config on Slave Select pin */
+	port_pin_set_config(slave->ss_pin, &pin_conf);
+	port_pin_set_output_level(slave->ss_pin, true);
+}
+
+enum status_code spi_init(
+		struct spi_module *const module,
+		Sercom *const hw,
+		const struct spi_config *const config);
+
+/** @} */
+
+/**
+ * \name Enable/Disable
+ * @{
+ */
+
+/**
+ * \brief Enables the SERCOM SPI module
+ *
+ * This function will enable the SERCOM SPI module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+static inline void spi_enable(
+		struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+#  if SPI_CALLBACK_MODE == true
+	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#  endif
+
+	while (spi_is_syncing(module)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Enable SPI */
+	spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disables the SERCOM SPI module
+ *
+ * This function will disable the SERCOM SPI module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+static inline void spi_disable(
+		struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+#  if SPI_CALLBACK_MODE == true
+	system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#  endif
+
+	while (spi_is_syncing(module)) {
+		/* Wait until the synchronization is complete */
+	}
+
+	/* Disbale interrupt */
+	spi_module->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	spi_module->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK;
+
+	/* Disable SPI */
+	spi_module->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+}
+
+void spi_reset(
+		struct spi_module *const module);
+
+/** @} */
+
+enum status_code spi_set_baudrate(
+		struct spi_module *const module,
+		uint32_t baudrate);
+
+/**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code spi_lock(struct spi_module *const module)
+{
+	enum status_code status;
+
+	system_interrupt_enter_critical_section();
+
+	if (module->locked) {
+		status = STATUS_BUSY;
+	} else {
+		module->locked = true;
+		status = STATUS_OK;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline void spi_unlock(struct spi_module *const module)
+{
+	module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \name Ready to Write/Read
+ * @{
+ */
+
+ /**
+ * \brief Checks if the SPI in master mode has shifted out last data, or if the master has ended the transfer in slave mode.
+ *
+ * This function will check if the SPI master module has shifted out last data,
+ * or if the slave select pin has been drawn high by the master for the SPI
+ * slave module.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ *
+ * \return Indication of whether any writes are ongoing.
+ * \retval true   If the SPI master module has shifted out data, or slave select
+ *                has been drawn high for SPI slave
+ * \retval false  If the SPI master module has not shifted out data
+ */
+static inline bool spi_is_write_complete(
+		struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Check interrupt flag */
+	return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC);
+}
+
+ /**
+ * \brief Checks if the SPI module is ready to write data
+ *
+ * This function will check if the SPI module is ready to write data.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ *
+ * \return Indication of whether the module is ready to read data or not.
+ * \retval true   If the SPI module is ready to write data
+ * \retval false  If the SPI module is not ready to write data
+ */
+static inline bool spi_is_ready_to_write(
+		struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Check interrupt flag */
+	return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE);
+}
+
+/**
+ * \brief Checks if the SPI module is ready to read data
+ *
+ * This function will check if the SPI module is ready to read data.
+ *
+ * \param[in]  module Pointer to the software instance struct
+ *
+ * \return Indication of whether the module is ready to read data or not.
+ * \retval true   If the SPI module is ready to read data
+ * \retval false  If the SPI module is not ready to read data
+ */
+static inline bool spi_is_ready_to_read(
+		struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Check interrupt flag */
+	return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC);
+}
+/** @} */
+
+/**
+ * \name Read/Write
+ * @{
+ */
+
+ /**
+ * \brief Transfers a single SPI character
+ *
+ * This function will send a single SPI character via SPI and ignore any data
+ * shifted in by the connected device. To both send and receive data, use the
+ * \ref spi_transceive_wait function or use the \ref spi_read function after
+ * writing a character. The \ref spi_is_ready_to_write function
+ * should be called before calling this function.
+ *
+ * Note that this function does not handle the SS (Slave Select)
+ * pin(s) in master mode; this must be handled from the user application.
+ *
+ * \note In slave mode, the data will not be transferred before a master
+ *       initiates a transaction.
+ *
+ * \param[in] module   Pointer to the software instance struct
+ * \param[in] tx_data  Data to transmit
+ *
+ * \return Status of the procedure.
+ * \retval STATUS_OK    If the data was written
+ * \retval STATUS_BUSY  If the last write was not completed
+ */
+static inline enum status_code spi_write(
+		struct spi_module *module,
+		uint16_t tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Check if the data register has been copied to the shift register */
+	if (!spi_is_ready_to_write(module)) {
+		/* Data register has not been copied to the shift register, return */
+		return STATUS_BUSY;
+	}
+
+	/* Write the character to the DATA register */
+	spi_module->DATA.reg = tx_data & SERCOM_SPI_DATA_MASK;
+
+	return STATUS_OK;
+}
+
+enum status_code spi_write_buffer_wait(
+		struct spi_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length);
+
+/**
+ * \brief Reads last received SPI character
+ *
+ * This function will return the last SPI character shifted into the receive
+ * register by the \ref spi_write function.
+ *
+ * \note The \ref spi_is_ready_to_read function should be called before calling
+ *       this function.
+ *
+ * \note Receiver must be enabled in the configuration.
+ *
+ * \param[in] module    Pointer to the software instance struct
+ * \param[out] rx_data  Pointer to store the received data
+ *
+ * \returns Status of the read operation.
+ * \retval STATUS_OK            If data was read
+ * \retval STATUS_ERR_IO        If no data is available
+ * \retval STATUS_ERR_OVERFLOW  If the data is overflown
+ */
+static inline enum status_code spi_read(
+		struct spi_module *const module,
+		uint16_t *rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomSpi *const spi_module = &(module->hw->SPI);
+
+	/* Check if data is ready to be read */
+	if (!spi_is_ready_to_read(module)) {
+		/* No data has been received, return */
+		return STATUS_ERR_IO;
+	}
+
+	/* Return value */
+	enum status_code retval = STATUS_OK;
+
+	/* Check if data is overflown */
+	if (spi_module->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) {
+		retval = STATUS_ERR_OVERFLOW;
+		/* Clear overflow flag */
+		spi_module->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+	}
+
+	/* Read the character from the DATA register */
+	if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+		*rx_data = (spi_module->DATA.reg & SERCOM_SPI_DATA_MASK);
+	} else {
+		*rx_data = (uint8_t)spi_module->DATA.reg;
+	}
+
+	return retval;
+}
+
+enum status_code spi_read_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length,
+		uint16_t dummy);
+
+enum status_code spi_transceive_wait(
+		struct spi_module *const module,
+		uint16_t tx_data,
+		uint16_t *rx_data);
+
+enum status_code spi_transceive_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length);
+
+enum status_code spi_select_slave(
+		struct spi_module *const module,
+		struct spi_slave_inst *const slave,
+		bool select);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+
+/**
+ * \page asfdoc_sam0_sercom_spi_extra Extra Information for SERCOM SPI Driver
+ *
+ * \section asfdoc_sam0_sercom_spi_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>Serial Communication Interface</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SPI</td>
+ *		<td>Serial Peripheral Interface</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SCK</td>
+ *		<td>Serial Clock</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MOSI</td>
+ *		<td>Master Output Slave Input</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MISO</td>
+ *		<td>Master Input Slave Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SS</td>
+ *		<td>Slave Select</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DIO</td>
+ *		<td>Data Input Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DO</td>
+ *		<td>Data Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DI</td>
+ *		<td>Data Input</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DMA</td>
+ *		<td>Direct Memory Access</td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_sam0_sercom_spi_extra_dependencies Dependencies
+ * The SPI driver has the following dependencies:
+ * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_extra_workarounds Workarounds Implemented by Driver
+ * No workarounds in driver.
+ *
+ * \section asfdoc_sam0_sercom_spi_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added new features as below:
+ *             \li Slave select low detect
+ *             \li Hardware slave select
+ *             \li DMA support </td>
+ *	</tr>
+ *	<tr>
+ *		<td>Edited slave part of write and transceive buffer functions to ensure
+ *		that second character is sent at the right time</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Renamed the anonymous union in \c struct spi_config to
+ *          \c mode_specific</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_spi_exqsg Examples for SERCOM SPI Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_spi_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_sercom_spi_master_basic_use
+ * - \subpage asfdoc_sam0_sercom_spi_slave_basic_use
+ * \if SPI_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_spi_master_callback_use
+ * - \subpage asfdoc_sam0_sercom_spi_slave_callback_use
+ * \endif
+ * - \subpage asfdoc_sam0_sercom_spi_dma_use_case
+ */
+
+ /**
+  * \page asfdoc_sam0_sercom_spi_mux_settings MUX Settings
+  *
+  * The following lists the possible internal SERCOM module pad function
+  * assignments for the four SERCOM pads in both SPI Master and SPI Slave
+  * modes. They are combinations of DOPO and DIPO in CTRLA.
+  * Note that this is in addition to the physical GPIO pin MUX of the device,
+  * and can be used in conjunction to optimize the serial data pin-out.
+  *
+  * \section asfdoc_sam0_sercom_spi_mux_settings_master Master Mode Settings
+  * The following table describes the SERCOM pin functionalities for the various
+  * MUX settings, whilst in SPI Master mode.
+  *
+  * \note If MISO is unlisted, the SPI receiver must not be enabled for the
+  *       given MUX setting.
+  *
+  * <table>
+  *		<tr>
+  *			<th>Combination</th>
+  *			<th>DOPO / DIPO</th>
+  *			<th>SERCOM PAD[0]</th>
+  *			<th>SERCOM PAD[1]</th>
+  *			<th>SERCOM PAD[2]</th>
+  *			<th>SERCOM PAD[3]</th>
+  *		</tr>
+  *		<tr>
+  *			<td>A</td>
+  *			<td>0x0 / 0x0</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *			<td>-</td>
+  *			<td>-</td>
+  *		</tr>
+  *		<tr>
+  *			<td>B</td>
+  *			<td>0x0 / 0x1</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *			<td>-</td>
+  *			<td>-</td>
+  *		</tr>
+  *		<tr>
+  *			<td>C</td>
+  *			<td>0x0 / 0x2</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *			<td>MISO</td>
+  *			<td>-</td>
+  *		</tr>
+  *		<tr>
+  *			<td>D</td>
+  *			<td>0x0 / 0x3</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *			<td>-</td>
+  *			<td>MISO</td>
+  *		</tr>
+  *		<tr>
+  *			<td>E</td>
+  *			<td>0x1 / 0x0</td>
+  *			<td>MISO</td>
+  *			<td>-</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>F</td>
+  *			<td>0x1 / 0x1</td>
+  *			<td>-</td>
+  *			<td>MISO</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>G</td>
+  *			<td>0x1 / 0x2</td>
+  *			<td>-</td>
+  *			<td>-</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>H</td>
+  *			<td>0x1 / 0x3</td>
+  *			<td>-</td>
+  *			<td>-</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>I</td>
+  *			<td>0x2 / 0x0</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *			<td>-</td>
+  *			<td>MOSI</td>
+  *		</tr>
+  *		<tr>
+  *			<td>J</td>
+  *			<td>0x2 / 0x1</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *			<td>-</td>
+  *			<td>MOSI</td>
+  *		</tr>
+  *		<tr>
+  *			<td>K</td>
+  *			<td>0x2 / 0x2</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *			<td>MISO</td>
+  *			<td>MOSI</td>
+  *		</tr>
+  *		<tr>
+  *			<td>L</td>
+  *			<td>0x2 / 0x3</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *			<td>-</td>
+  *			<td>MOSI</td>
+  *		</tr>
+  *		<tr>
+  *			<td>M</td>
+  *			<td>0x3 / 0x0</td>
+  *			<td>MOSI</td>
+  *			<td>-</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>N</td>
+  *			<td>0x3 / 0x1</td>
+  *			<td>MOSI</td>
+  *			<td>MISO</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>O</td>
+  *			<td>0x3 / 0x2</td>
+  *			<td>MOSI</td>
+  *			<td>-</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>P</td>
+  *			<td>0x3 / 0x3</td>
+  *			<td>MOSI</td>
+  *			<td>-</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *		</tr>
+  * </table>
+  *
+  *
+  * \section asfdoc_sam0_sercom_spi_mux_settings_slave Slave Mode Settings
+  * The following table describes the SERCOM pin functionalities for the various
+  * MUX settings, whilst in SPI Slave mode.
+  *
+  * \note If MISO is unlisted, the SPI receiver must not be enabled for the
+  *       given MUX setting.
+  *
+  * <table>
+  *		<tr>
+  *			<th>Combination</th>
+  *			<th>DOPO / DIPO</th>
+  *			<th>SERCOM PAD[0]</th>
+  *			<th>SERCOM PAD[1]</th>
+  *			<th>SERCOM PAD[2]</th>
+  *			<th>SERCOM PAD[3]</th>
+  *		</tr>
+  *		<tr>
+  *			<td>A</td>
+  *			<td>0x0 / 0x0</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *			<td>/SS</td>
+  *			<td>-</td>
+  *		</tr>
+  *		<tr>
+  *			<td>B</td>
+  *			<td>0x0 / 0x1</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *			<td>/SS</td>
+  *			<td>-</td>
+  *		</tr>
+  *		<tr>
+  *			<td>C</td>
+  *			<td>0x0 / 0x2</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *			<td>/SS</td>
+  *			<td>-</td>
+  *		</tr>
+  *		<tr>
+  *			<td>D</td>
+  *			<td>0x0 / 0x3</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *			<td>/SS</td>
+  *			<td>MOSI</td>
+  *		</tr>
+  *		<tr>
+  *			<td>E</td>
+  *			<td>0x1 / 0x0</td>
+  *			<td>MOSI</td>
+  *			<td>/SS</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>F</td>
+  *			<td>0x1 / 0x1</td>
+  *			<td>-</td>
+  *			<td>/SS</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>G</td>
+  *			<td>0x1 / 0x2</td>
+  *			<td>-</td>
+  *			<td>/SS</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>H</td>
+  *			<td>0x1 / 0x3</td>
+  *			<td>-</td>
+  *			<td>/SS</td>
+  *			<td>MISO</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>I</td>
+  *			<td>0x2 / 0x0</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *			<td>/SS</td>
+  *			<td>MISO</td>
+  *		</tr>
+  *		<tr>
+  *			<td>J</td>
+  *			<td>0x2 / 0x1</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *			<td>/SS</td>
+  *			<td>MISO</td>
+  *		</tr>
+  *		<tr>
+  *			<td>K</td>
+  *			<td>0x2 / 0x2</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *			<td>/SS</td>
+  *			<td>MISO</td>
+  *		</tr>
+  *		<tr>
+  *			<td>L</td>
+  *			<td>0x2 / 0x3</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *			<td>/SS</td>
+  *			<td>MISO</td>
+  *		</tr>
+  *		<tr>
+  *			<td>M</td>
+  *			<td>0x3 / 0x0</td>
+  *			<td>MISO</td>
+  *			<td>/SS</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>N</td>
+  *			<td>0x3 / 0x1</td>
+  *			<td>MISO</td>
+  *			<td>/SS</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>O</td>
+  *			<td>0x3 / 0x2</td>
+  *			<td>MISO</td>
+  *			<td>/SS</td>
+  *			<td>MOSI</td>
+  *			<td>SCK</td>
+  *		</tr>
+  *		<tr>
+  *			<td>P</td>
+  *			<td>0x3 / 0x3</td>
+  *			<td>MISO</td>
+  *			<td>/SS</td>
+  *			<td>-</td>
+  *			<td>SCK</td>
+  *		</tr>
+  * </table>
+  *
+  *
+  *
+  * \page asfdoc_sam0_sercom_spi_document_revision_history Document Revision History
+  *
+  * <table>
+  *	<tr>
+  *		<th>Doc. Rev.</th>
+  *		<th>Date</th>
+  *		<th>Comments</th>
+  *	</tr>
+  *	<tr>
+  *		<td>42115E</td>
+  *		<td>12/2015</td>
+  *		<td>Add SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C21 support</td>
+  *	</tr>
+  *	<tr>
+  *		<td>42115D</td>
+  *		<td>12/2014</td>
+  *		<td>Add SAM R21/D10/D11 support</td>
+  *	</tr>
+  *	<tr>
+  *		<td>42115C</td>
+  *		<td>01/2014</td>
+  *		<td>Add SAM D21 support</td>
+  *	</tr>
+  *	<tr>
+  *		<td>42115B</td>
+  *		<td>11/2013</td>
+  *		<td>Replaced the pad multiplexing documentation with a condensed table</td>
+  *	</tr>
+  *	<tr>
+  *		<td>42115A</td>
+  *		<td>06/2013</td>
+  *		<td>Initial release</td>
+  *	</tr>
+  * </table>
+  */
+
+#endif /* SPI_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.c
new file mode 100644
index 0000000000..5909843b2d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.c
@@ -0,0 +1,741 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "spi_interrupt.h"
+
+/**
+ * \internal
+ *
+ * Dummy byte to send when reading in master mode.
+ */
+uint16_t dummy_write;
+
+/**
+ * \internal
+ * Starts transceive of buffers with a given length
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+static void _spi_transceive_buffer(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(tx_data);
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+	module->remaining_rx_buffer_length = length;
+	module->rx_buffer_ptr = rx_data;
+	module->tx_buffer_ptr = tx_data;
+	module->status = STATUS_BUSY;
+
+	module->dir = SPI_DIRECTION_BOTH;
+
+	/* Get a pointer to the hardware module instance */
+	SercomSpi *const hw = &(module->hw->SPI);
+
+	/* Enable the Data Register Empty and RX Complete Interrupt */
+	hw->INTENSET.reg = (SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
+			SPI_INTERRUPT_FLAG_RX_COMPLETE);
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if (module->mode == SPI_MODE_SLAVE) {
+		/* Clear TXC flag if set */
+		hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+		/* Enable transmit complete interrupt for slave */
+		hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+	}
+#  endif
+}
+
+/**
+ * \internal
+ * Starts write of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+static void _spi_write_buffer(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(tx_data);
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+	module->remaining_dummy_buffer_length = length;
+	module->tx_buffer_ptr = tx_data;
+	module->status = STATUS_BUSY;
+
+	module->dir = SPI_DIRECTION_WRITE;
+
+	/* Get a pointer to the hardware module instance */
+	SercomSpi *const hw = &(module->hw->SPI);
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if (module->mode == SPI_MODE_SLAVE) {
+		/* Clear TXC flag if set */
+		hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+		/* Enable transmit complete interrupt for slave */
+		hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+	}
+#  endif
+
+	if (module->receiver_enabled) {
+		/* Enable the Data Register Empty and RX Complete interrupt */
+		hw->INTENSET.reg = (SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
+				SPI_INTERRUPT_FLAG_RX_COMPLETE);
+	} else {
+		/* Enable the Data Register Empty interrupt */
+		hw->INTENSET.reg = SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+	}
+}
+
+/**
+ * \internal
+ * Setup SPI to read a buffer with a given length
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  length   Length of data buffer
+ *
+ */
+static void _spi_read_buffer(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(rx_data);
+
+	uint8_t tmp_intenset = 0;
+
+	/* Set length for the buffer and the pointer, and let
+	 * the interrupt handler do the rest */
+	module->remaining_rx_buffer_length = length;
+	module->remaining_dummy_buffer_length = length;
+	module->rx_buffer_ptr = rx_data;
+	module->status = STATUS_BUSY;
+
+	module->dir = SPI_DIRECTION_READ;
+
+	/* Get a pointer to the hardware module instance */
+	SercomSpi *const hw = &(module->hw->SPI);
+
+	/* Enable the RX Complete Interrupt */
+	tmp_intenset = SPI_INTERRUPT_FLAG_RX_COMPLETE;
+
+#  if CONF_SPI_MASTER_ENABLE == true
+	if (module->mode == SPI_MODE_MASTER && module->dir == SPI_DIRECTION_READ) {
+		/* Enable Data Register Empty interrupt for master */
+		tmp_intenset |= SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+	}
+#  endif
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if (module->mode == SPI_MODE_SLAVE) {
+		/* Clear TXC flag if set */
+		hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+		/* Enable transmit complete interrupt for slave */
+		tmp_intenset |= SPI_INTERRUPT_FLAG_TX_COMPLETE;
+
+		/* Workaround for SSL flag enable */
+#ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+		/* Clear SSL flag if set */
+		hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
+		/* Enable Slave Select Low Interrupt for slave */
+		tmp_intenset |= SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
+#endif
+	}
+#  endif
+
+	/* Enable all interrupts simultaneously */
+	hw->INTENSET.reg = tmp_intenset;
+}
+
+/**
+ * \brief Registers a SPI callback function
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref spi_enable_callback, in order
+ *       for the interrupt handler to call it when the conditions for the
+ *       callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void spi_register_callback(
+		struct spi_module *const module,
+		spi_callback_t callback_func,
+		enum spi_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a SPI callback function
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in] module         Pointer to SPI software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void spi_unregister_callback(
+		struct spi_module *const module,
+		enum spi_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Asynchronous buffer write
+ *
+ * Sets up the driver to write to the SPI from a given buffer. If registered
+ * and enabled, a callback function will be called when the write is finished.
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[out] tx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \returns Status of the write request operation.
+ * \retval STATUS_OK               If the operation completed successfully
+ * \retval STATUS_ERR_BUSY         If the SPI was already busy with a write
+ *                                 operation
+ * \retval STATUS_ERR_INVALID_ARG  If requested write length was zero
+ */
+enum status_code spi_write_buffer_job(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(tx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
+	if (module->status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Issue internal write */
+	_spi_write_buffer(module, tx_data, length);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Asynchronous buffer read
+ *
+ * Sets up the driver to read from the SPI to a given buffer. If registered
+ * and enabled, a callback function will be called when the read is finished.
+ *
+ * \note If address matching is enabled for the slave, the first character
+ *       received and placed in the RX buffer will be the address.
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ * \param[in]  dummy    Dummy character to send when reading in master mode
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK               If the operation completed successfully
+ * \retval  STATUS_ERR_BUSY         If the SPI was already busy with a read
+ *                                  operation
+ * \retval  STATUS_ERR_DENIED       If the receiver is not enabled
+ * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
+ */
+enum status_code spi_read_buffer_job(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length,
+		uint16_t dummy)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
+	if (module->status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	dummy_write = dummy;
+	/* Issue internal read */
+	_spi_read_buffer(module, rx_data, length);
+	return STATUS_OK;
+}
+
+/**
+ * \brief Asynchronous buffer write and read
+ *
+ * Sets up the driver to write and read to and from given buffers. If registered
+ * and enabled, a callback function will be called when the transfer is finished.
+ *
+ * \note If address matching is enabled for the slave, the first character
+ *       received and placed in the RX buffer will be the address.
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[in] tx_data   Pointer to data buffer to send
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK               If the operation completed successfully
+ * \retval  STATUS_ERR_BUSY         If the SPI was already busy with a read
+ *                                  operation
+ * \retval  STATUS_ERR_DENIED       If the receiver is not enabled
+ * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
+ */
+enum status_code spi_transceive_buffer_job(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
+	if (module->status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Issue internal transceive */
+	_spi_transceive_buffer(module, tx_data, rx_data, length);
+
+	return STATUS_OK;
+}
+/**
+ * \brief Aborts an ongoing job
+ *
+ * This function will abort the specified job type.
+ *
+ * \param[in]  module    Pointer to SPI software instance struct
+ */
+void spi_abort_job(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	SercomSpi *const spi_hw
+		= &(module->hw->SPI);
+
+	/* Abort ongoing job */
+
+	/* Disable interrupts */
+	spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE |
+			SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
+			SPI_INTERRUPT_FLAG_TX_COMPLETE;
+
+	module->status = STATUS_ABORTED;
+	module->remaining_rx_buffer_length = 0;
+	module->remaining_dummy_buffer_length = 0;
+	module->remaining_tx_buffer_length = 0;
+
+	module->dir = SPI_DIRECTION_IDLE;
+}
+
+#  if CONF_SPI_SLAVE_ENABLE == true || CONF_SPI_MASTER_ENABLE == true
+/**
+ * \internal
+ * Writes a character from the TX buffer to the Data register.
+ *
+ * \param[in,out]  module  Pointer to SPI software instance struct
+ */
+static void _spi_write(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	SercomSpi *const spi_hw = &(module->hw->SPI);
+
+	/* Write value will be at least 8-bits long */
+	uint16_t data_to_send = *(module->tx_buffer_ptr);
+	/* Increment 8-bit pointer */
+	(module->tx_buffer_ptr)++;
+
+	if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+		data_to_send |= ((*(module->tx_buffer_ptr)) << 8);
+		/* Increment 8-bit pointer */
+		(module->tx_buffer_ptr)++;
+	}
+
+	/* Write the data to send*/
+	spi_hw->DATA.reg = data_to_send & SERCOM_SPI_DATA_MASK;
+
+	/* Decrement remaining buffer length */
+	(module->remaining_tx_buffer_length)--;
+}
+#  endif
+
+#  if CONF_SPI_MASTER_ENABLE == true
+/**
+ * \internal
+ * Writes a dummy character to the Data register.
+ *
+ * \param[in,out]  module  Pointer to SPI software instance struct
+ */
+static void _spi_write_dummy(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	SercomSpi *const spi_hw = &(module->hw->SPI);
+
+	/* Write dummy byte */
+	spi_hw->DATA.reg = dummy_write;
+
+	/* Decrement remaining dummy buffer length */
+	module->remaining_dummy_buffer_length--;
+}
+#  endif
+
+/**
+ * \internal
+ * Writes a dummy character from the to the Data register.
+ *
+ * \param[in,out]  module  Pointer to SPI software instance struct
+ */
+static void _spi_read_dummy(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	SercomSpi *const spi_hw = &(module->hw->SPI);
+	uint16_t flush = 0;
+
+	/* Read dummy byte */
+	flush = spi_hw->DATA.reg;
+	UNUSED(flush);
+
+	/* Decrement remaining dummy buffer length */
+	module->remaining_dummy_buffer_length--;
+}
+
+/**
+ * \internal
+ * Reads a character from the Data register to the RX buffer.
+ *
+ * \param[in,out]  module  Pointer to SPI software instance struct
+ */
+static void _spi_read(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	SercomSpi *const spi_hw = &(module->hw->SPI);
+
+	uint16_t received_data = (spi_hw->DATA.reg & SERCOM_SPI_DATA_MASK);
+
+	/* Read value will be at least 8-bits long */
+	*(module->rx_buffer_ptr) = received_data;
+	/* Increment 8-bit pointer */
+	module->rx_buffer_ptr += 1;
+
+	if(module->character_size == SPI_CHARACTER_SIZE_9BIT) {
+		/* 9-bit data, write next received byte to the buffer */
+		*(module->rx_buffer_ptr) = (received_data >> 8);
+		/* Increment 8-bit pointer */
+		module->rx_buffer_ptr += 1;
+	}
+
+	/* Decrement length of the remaining buffer */
+	module->remaining_rx_buffer_length--;
+}
+
+/**
+ * \internal
+ *
+ * Handles interrupts as they occur, and it will run callback functions
+ * which are registered and enabled.
+ *
+ * \note This function will be called by the Sercom_Handler, and should
+ *       not be called directly from any application code.
+ *
+ * \param[in]  instance  ID of the SERCOM instance calling the interrupt
+ *                       handler.
+ */
+void _spi_interrupt_handler(
+		uint8_t instance)
+{
+	/* Get device instance from the look-up table */
+	struct spi_module *module
+		= (struct spi_module *)_sercom_instances[instance];
+
+	/* Pointer to the hardware module instance */
+	SercomSpi *const spi_hw = &(module->hw->SPI);
+
+	/* Combine callback registered and enabled masks. */
+	uint8_t callback_mask =
+			module->enabled_callback & module->registered_callback;
+
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status = spi_hw->INTFLAG.reg;
+	interrupt_status &= spi_hw->INTENSET.reg;
+
+	/* Data register empty interrupt */
+	if (interrupt_status & SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY) {
+#  if CONF_SPI_MASTER_ENABLE == true
+		if ((module->mode == SPI_MODE_MASTER) &&
+			(module->dir == SPI_DIRECTION_READ)) {
+			/* Send dummy byte when reading in master mode */
+			_spi_write_dummy(module);
+			if (module->remaining_dummy_buffer_length == 0) {
+				/* Disable the Data Register Empty Interrupt */
+				spi_hw->INTENCLR.reg
+						= SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+			}
+		}
+#  endif
+
+		if (0
+#  if CONF_SPI_MASTER_ENABLE == true
+		|| ((module->mode == SPI_MODE_MASTER) &&
+			(module->dir != SPI_DIRECTION_READ))
+#  endif
+#  if CONF_SPI_SLAVE_ENABLE == true
+		|| ((module->mode == SPI_MODE_SLAVE) &&
+			(module->dir != SPI_DIRECTION_READ))
+#  endif
+		) {
+			/* Write next byte from buffer */
+			_spi_write(module);
+			if (module->remaining_tx_buffer_length == 0) {
+				/* Disable the Data Register Empty Interrupt */
+				spi_hw->INTENCLR.reg
+						= SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+
+				if (module->dir == SPI_DIRECTION_WRITE &&
+						!(module->receiver_enabled)) {
+					/* Enable the Data Register transmit complete Interrupt */
+					spi_hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+				}
+			}
+		}
+	}
+
+	/* Receive complete interrupt*/
+	if (interrupt_status & SPI_INTERRUPT_FLAG_RX_COMPLETE) {
+		/* Check for overflow */
+		if (spi_hw->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) {
+			if (module->dir != SPI_DIRECTION_WRITE) {
+				/* Store the error code */
+				module->status = STATUS_ERR_OVERFLOW;
+
+				/* End transaction */
+				module->dir = SPI_DIRECTION_IDLE;
+
+				spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE |
+						SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+				/* Run callback if registered and enabled */
+				if (callback_mask & (1 << SPI_CALLBACK_ERROR)) {
+					(module->callback[SPI_CALLBACK_ERROR])(module);
+				}
+			}
+			/* Flush */
+			uint16_t flush = spi_hw->DATA.reg;
+			UNUSED(flush);
+			/* Clear overflow flag */
+			spi_hw->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+		} else {
+			if (module->dir == SPI_DIRECTION_WRITE) {
+				/* Flush receive buffer when writing */
+				_spi_read_dummy(module);
+				if (module->remaining_dummy_buffer_length == 0) {
+					spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE;
+					module->status = STATUS_OK;
+					module->dir = SPI_DIRECTION_IDLE;
+					/* Run callback if registered and enabled */
+					if (callback_mask &
+							(1 << SPI_CALLBACK_BUFFER_TRANSMITTED)){
+						(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
+					}
+				}
+			} else {
+				/* Read data register */
+				_spi_read(module);
+
+				/* Check if the last character have been received */
+				if (module->remaining_rx_buffer_length == 0) {
+					module->status = STATUS_OK;
+					/* Disable RX Complete Interrupt and set status */
+					spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE;
+					if(module->dir == SPI_DIRECTION_BOTH) {
+						if (callback_mask & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) {
+							(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+						}
+					} else if (module->dir == SPI_DIRECTION_READ) {
+						if (callback_mask & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) {
+							(module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
+						}
+					}
+				}
+			}
+		}
+	}
+
+	/* Transmit complete */
+	if (interrupt_status & SPI_INTERRUPT_FLAG_TX_COMPLETE) {
+#  if CONF_SPI_SLAVE_ENABLE == true
+		if (module->mode == SPI_MODE_SLAVE) {
+			/* Transaction ended by master */
+
+			/* Disable interrupts */
+			spi_hw->INTENCLR.reg =
+					SPI_INTERRUPT_FLAG_TX_COMPLETE |
+					SPI_INTERRUPT_FLAG_RX_COMPLETE |
+					SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+			/* Clear interrupt flag */
+			spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+
+
+			/* Reset all status information */
+			module->dir = SPI_DIRECTION_IDLE;
+			module->remaining_tx_buffer_length = 0;
+			module->remaining_rx_buffer_length = 0;
+			module->status = STATUS_OK;
+
+			if (callback_mask &
+					(1 << SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE)) {
+			(module->callback[SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE])
+					(module);
+			}
+
+		}
+#  endif
+#  if CONF_SPI_MASTER_ENABLE == true
+		if ((module->mode == SPI_MODE_MASTER) &&
+			(module->dir == SPI_DIRECTION_WRITE) && !(module->receiver_enabled)) {
+		  	/* Clear interrupt flag */
+		 	spi_hw->INTENCLR.reg
+					= SPI_INTERRUPT_FLAG_TX_COMPLETE;
+			/* Buffer sent with receiver disabled */
+			module->dir = SPI_DIRECTION_IDLE;
+			module->status = STATUS_OK;
+			/* Run callback if registered and enabled */
+			if (callback_mask & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)){
+				(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])
+						(module);
+			}
+		}
+#endif
+	}
+
+#  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
+#  if CONF_SPI_SLAVE_ENABLE == true
+		/* When a high to low transition is detected on the _SS pin in slave mode */
+		if (interrupt_status & SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW) {
+			if (module->mode == SPI_MODE_SLAVE) {
+				/* Disable interrupts */
+				spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
+				/* Clear interrupt flag */
+				spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
+
+				if (callback_mask & (1 << SPI_CALLBACK_SLAVE_SELECT_LOW)) {
+					(module->callback[SPI_CALLBACK_SLAVE_SELECT_LOW])(module);
+				}
+			}
+		}
+#  endif
+#  endif
+
+#  ifdef FEATURE_SPI_ERROR_INTERRUPT
+	/* When combined error happen */
+	if (interrupt_status & SPI_INTERRUPT_FLAG_COMBINED_ERROR) {
+		/* Disable interrupts */
+		spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_COMBINED_ERROR;
+		/* Clear interrupt flag */
+		spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_COMBINED_ERROR;
+
+		if (callback_mask & (1 << SPI_CALLBACK_COMBINED_ERROR)) {
+			(module->callback[SPI_CALLBACK_COMBINED_ERROR])(module);
+		}
+	}
+#  endif
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.h
new file mode 100644
index 0000000000..bb71682501
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.h
@@ -0,0 +1,190 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver (Callback Mode)
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SPI_INTERRUPT_H_INCLUDED
+#define SPI_INTERRUPT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_spi_group
+ *
+ * @{
+ */
+
+#include "spi.h"
+
+/**
+ * \name Callback Management
+ * @{
+ */
+
+void spi_register_callback(
+		struct spi_module *const module,
+		spi_callback_t callback_func,
+		enum spi_callback callback_type);
+
+void spi_unregister_callback(
+		struct spi_module *module,
+		enum spi_callback callback_type);
+
+/**
+ * \brief Enables an SPI callback of a given type
+ *
+ * Enables the callback function registered by the \ref spi_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in] module         Pointer to SPI software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ */
+static inline void spi_enable_callback(
+		struct spi_module *const module,
+		enum spi_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback function registered by the \ref spi_register_callback,
+ * and the callback will not be called from the interrupt routine.
+ *
+ * \param[in] module         Pointer to SPI software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ */
+static inline void spi_disable_callback(
+		struct spi_module *const module,
+		enum spi_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/** @} */
+
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code spi_write_buffer_job(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code spi_read_buffer_job(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length,
+		uint16_t dummy);
+
+enum status_code spi_transceive_buffer_job(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void spi_abort_job(
+		struct spi_module *const module);
+
+/**
+ * \brief Retrieves the current status of a job.
+ *
+ * Retrieves the current status of a job that was previously issued.
+ *
+ * \param[in]  module    Pointer to SPI software instance struct
+ *
+ * \return Current job status.
+ */
+static inline enum status_code spi_get_job_status(
+		const struct spi_module *const module)
+{
+	return module->status;
+}
+
+/**
+ * \brief Retrieves the status of job once it ends.
+ *
+ * Waits for current job status to become non-busy, then returns its value.
+ *
+ * \param[in]  module    Pointer to SPI software instance struct
+ *
+ * \return Current non-busy job status.
+ */
+static inline enum status_code spi_get_job_status_wait(
+		const struct spi_module *const module)
+{
+	enum status_code status;
+
+	do {
+		status = spi_get_job_status(module);
+	} while (status == STATUS_BUSY);
+
+	return status;
+}
+
+/** @} */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SPI_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi.h
new file mode 100644
index 0000000000..3bb66ff5bb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi.h
@@ -0,0 +1,55 @@
+/**
+ * \file
+ *
+ * \brief common SPI configuration
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef CONF_SPI_H_INCLUDED
+#  define CONF_SPI_H_INCLUDED
+
+#  define CONF_SPI_MASTER_ENABLE     true
+#  define CONF_SPI_SLAVE_ENABLE      false
+
+#endif /* CONF_SPI_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h
new file mode 100644
index 0000000000..394b1fa617
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h
@@ -0,0 +1,68 @@
+/**
+ * \file
+ *
+ * \brief SERCOM SPI master with vectored I/O driver configuration
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_SPI_MASTER_VEC_H
+#define CONF_SPI_MASTER_VEC_H
+
+#if defined(__FREERTOS__) || defined(__DOXYGEN__)
+#  include <FreeRTOS.h>
+#  include <semphr.h>
+
+#  define CONF_SPI_MASTER_VEC_OS_SUPPORT
+#  define CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE                   xSemaphoreHandle
+#  define CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE(semaphore)  \
+		vSemaphoreCreateBinary(semaphore)
+#  define CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE(semaphore)  \
+		vSemaphoreDelete(semaphore)
+#  define CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(semaphore)  \
+		xSemaphoreTake((semaphore), portMAX_DELAY)
+#  define CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE(semaphore)  \
+		xSemaphoreGive((semaphore))
+#  define CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(semaphore)  \
+		xSemaphoreGiveFromISR((semaphore), NULL)
+#endif
+
+#endif // CONF_SPI_MASTER_VEC_H
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c
new file mode 100644
index 0000000000..89de7dd0d7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c
@@ -0,0 +1,588 @@
+/**
+ * \file
+ *
+ * \brief SERCOM SPI master with vectored I/O driver implementation
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "spi_master_vec.h"
+#include <sercom_interrupt.h>
+#include <system.h>
+#include <system_interrupt.h>
+
+/**
+ * \ingroup asfdoc_sam0_sercom_spi_master_vec_group
+ *
+ * @{
+ */
+
+/**
+ * \name Internal functions
+ * @{
+ */
+
+/** \cond INTERNAL */
+
+static void _spi_master_vec_int_handler(uint8_t sercom_index);
+
+/**
+ * \brief Wait for SERCOM SPI to synchronize
+ *
+ * \param[in] sercom_spi SERCOM SPI to check for synchronization.
+ *
+ * \note The implementation of this function depends on the SERCOM revision.
+ */
+static inline void _spi_master_vec_wait_for_sync(SercomSpi *const sercom_spi)
+{
+#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
+	while (sercom_spi->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY) {
+		/* Intentionally left empty */
+	}
+#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
+	while (sercom_spi->SYNCBUSY.reg) {
+		/* Intentionally left empty */
+	}
+#else
+#  error Unknown SERCOM SYNCBUSY scheme!
+#endif
+}
+
+/**
+ * \brief Pin MUX configuration helper
+ *
+ * \param[in] pinmux Pin MUX setting to apply. Special values:
+ * \arg \c PINMUX_UNUSED to do nothing.
+ * \arg \c PINMUX_DEFAULT to use default pin MUX for the SERCOM pad.
+ * \param[in] sercom,padnum SERCOM pad specification, for \ref PINMUX_DEFAULT.
+ */
+static inline void _spi_master_vec_pinmux_helper(uint32_t pinmux,
+		Sercom *const sercom, uint8_t padnum)
+{
+	struct system_pinmux_config pin_conf;
+
+	if (pinmux == PINMUX_DEFAULT) {
+		pinmux = _sercom_get_default_pad(sercom, padnum);
+	}
+
+	if (pinmux == PINMUX_UNUSED) {
+		return;
+	}
+
+	system_pinmux_get_config_defaults(&pin_conf);
+	pin_conf.mux_position = pinmux & 0xFFFF;
+	system_pinmux_pin_set_config(pinmux >> 16, &pin_conf);
+};
+
+/** \endcond */
+
+/** @} */
+
+/**
+ * \brief Initialize hardware and driver instance
+ *
+ * This function configures the clock system for the specified SERCOM module,
+ * sets up the related pins and their MUX, initializes the SERCOM in SPI master
+ * mode, and prepares the driver instance for operation.
+ *
+ * \pre \ref system_init() must have been called prior to this function.
+ *
+ * The SERCOM SPI module is left disabled after initialization, and must be
+ * enabled with \ref spi_master_vec_enable() before a transfer can be done.
+ *
+ * \param[out] module Driver instance to initialize.
+ * \param[in,out] sercom SERCOM module to initialize and associate driver
+ * instance with.
+ * \param[in] config Driver configuration to use.
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK if initialization succeeded.
+ * \retval STATUS_ERR_INVALID_ARG if driver has been misconfigured.
+ */
+enum status_code spi_master_vec_init(struct spi_master_vec_module *const module,
+		Sercom *const sercom, const struct spi_master_vec_config *const config)
+{
+	Assert(module);
+	Assert(sercom);
+	Assert(config);
+
+	enum status_code status;
+	SercomSpi *const spi_hw = &(sercom->SPI);
+	struct system_gclk_chan_config gclk_chan_conf;
+	uint16_t tmp_baud;
+	uint32_t sercom_index = _sercom_get_sercom_inst_index((Sercom *)spi_hw);
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+#else
+	uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+#endif
+	uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+	uint32_t gclk_hz;
+
+	module->sercom = sercom;
+
+	/* Enable clock for the module interface */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+	/* Set up the GCLK for the module */
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->gclk_generator;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->gclk_generator, false);
+
+	_spi_master_vec_wait_for_sync(spi_hw);
+
+	/* Set up the SERCOM SPI module as master */
+	spi_hw->CTRLA.reg = SERCOM_SPI_CTRLA_MODE(0x3);
+	spi_hw->CTRLA.reg |= (uint32_t)config->mux_setting
+			| config->transfer_mode
+			| config->data_order
+			| ((config->run_in_standby || system_is_debugger_present()) ?
+					SERCOM_SPI_CTRLA_RUNSTDBY : 0);
+
+	/* Get baud value from configured baudrate and internal clock rate */
+	gclk_hz = system_gclk_chan_get_hz(gclk_index);
+	status = _sercom_get_sync_baud_val(config->baudrate, gclk_hz, &tmp_baud);
+
+	if (status != STATUS_OK) {
+		/* Baud rate calculation error! */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	spi_hw->BAUD.reg = (uint8_t)tmp_baud;
+
+	/* Configure the pin multiplexers */
+	_spi_master_vec_pinmux_helper(config->pinmux_pad0, sercom, 0);
+	_spi_master_vec_pinmux_helper(config->pinmux_pad3, sercom, 3);
+
+	/* SERCOM PAD1 and PAD2 are used for slave SS.
+	 * This is a SPI master driver, so control of slave SS must be left to
+	 * the PORT module, i.e., peripheral MUX should not be set for that pin.
+	 * DOPO controls which PAD is used for slave SS:
+	 * If DOPO is odd, SERCOM_PAD1 is SS: SERCOM_PAD2 can be MUXed.
+	 * If DOPO is even, SERCOM_PAD2 is SS: SERCOM_PAD1 can be MUXed.
+	 */
+	if (config->mux_setting & (1 << SERCOM_SPI_CTRLA_DOPO_Pos)) {
+		_spi_master_vec_pinmux_helper(config->pinmux_pad2, sercom, 2);
+	} else {
+		_spi_master_vec_pinmux_helper(config->pinmux_pad1, sercom, 1);
+	}
+
+	/* Initialize our instance and register interrupt handler + data */
+	module->rx_bufdesc_ptr = NULL;
+	module->tx_bufdesc_ptr = NULL;
+	module->direction = SPI_MASTER_VEC_DIRECTION_IDLE;
+	module->status = STATUS_OK;
+#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
+	CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE(module->busy_semaphore);
+#endif
+
+	_sercom_set_handler(sercom_index, _spi_master_vec_int_handler);
+	_sercom_instances[sercom_index] = module;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enable the SERCOM SPI module
+ *
+ * This function must be called after \ref spi_master_vec_init() before a
+ * transfer can be started.
+ *
+ * \param[in,out] module Driver instance to operate on.
+ */
+void spi_master_vec_enable(const struct spi_master_vec_module *const module)
+{
+	Assert(module);
+	Assert(module->sercom);
+
+	SercomSpi *const spi_hw = &(module->sercom->SPI);
+
+	spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC
+			| SERCOM_SPI_INTFLAG_TXC;
+
+	_spi_master_vec_wait_for_sync(spi_hw);
+
+	spi_hw->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+
+	system_interrupt_enable(_sercom_get_interrupt_vector(module->sercom));
+}
+
+/**
+ * \brief Disable the SERCOM SPI module
+ *
+ * \param[in,out] module Driver instance to operate on.
+ */
+void spi_master_vec_disable(struct spi_master_vec_module *const module)
+{
+	Assert(module);
+	Assert(module->sercom);
+
+	SercomSpi *const spi_hw = &(module->sercom->SPI);
+
+	system_interrupt_disable(_sercom_get_interrupt_vector(module->sercom));
+
+	_spi_master_vec_wait_for_sync(spi_hw);
+
+	spi_hw->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK;
+	spi_hw->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK;
+	spi_hw->CTRLB.reg = 0;
+	spi_hw->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+	module->rx_bufdesc_ptr = NULL;
+	module->tx_bufdesc_ptr = NULL;
+	module->direction = SPI_MASTER_VEC_DIRECTION_IDLE;
+	module->status = STATUS_OK;
+}
+
+/**
+ * \brief Reset the SERCOM SPI module
+ *
+ * This function will disable and reset the SPI module to its power on default
+ * values.
+ *
+ * \param[in,out] module Pointer to a driver instance.
+ */
+void spi_master_vec_reset(struct spi_master_vec_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->sercom);
+
+	SercomSpi *const spi_hw = &(module->sercom->SPI);
+
+	/* Disable the module */
+	spi_master_vec_disable(module);
+
+	_spi_master_vec_wait_for_sync(spi_hw);
+
+	/* Software reset the module */
+	spi_hw->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+
+#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
+	CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE(module->busy_semaphore);
+#endif
+}
+
+/**
+ * \brief Start vectored I/O transfer
+ *
+ * This function initiates a uni- or bidirectional SPI transfer from/to any
+ * number of data buffers. The transfer is interrupt-driven and will run in the
+ * background, after this function has returned.
+ *
+ * The buffers to transmit from or receive into must be described in arrays of
+ * buffer descriptors. These arrays \e must end with descriptors that specify
+ * zero buffer length. The first descriptor in an array can \e not specify zero
+ * length. The number of bytes to transmit and to receive do not have to be
+ * equal.
+ *
+ * If the address for a receive buffer is set to \c NULL, the received bytes
+ * corresponding to that buffer descriptor will be discarded. This is useful if
+ * slave is already set up to transfer a number of bytes, but the master has no
+ * available buffer to receive them into. As an example, to receive the two
+ * first bytes and discard the 128 following, the buffer descriptors could be:
+\code
+	struct spi_master_vec_bufdesc rx_buffers[3] = {
+		// Read two status bytes
+		{.data = status_buffer, .length = 2},
+		// Discard 128 data bytes
+		{.data = NULL, .length = 128},
+		// End of reception
+		{.length = 0},
+	};
+\endcode
+ *
+ * To initiate a unidirectional transfer, pass \c NULL as the address of either
+ * buffer descriptor array, like this:
+\code
+	// Transmit some buffers
+	spi_master_vec_transceive_buffer_job(&module, tx_buffers, NULL);
+
+	// Receive some buffers
+	spi_master_vec_transceive_buffer_job(&module, NULL, rx_buffers);
+\endcode
+ *
+ * \pre \ref spi_master_vec_init() and \ref spi_master_vec_enable() must have
+ * been called before this function.
+ *
+ * \param[in,out] module Driver instance to operate on.
+ * \param[in] tx_bufdescs address of buffer descriptor array for bytes to
+ * transmit.
+ * \arg \c NULL if the transfer is a simplex read.
+ * \param[in,out] rx_bufdescs address of buffer descriptor array for storing
+ * received bytes.
+ * \arg \c NULL if the transfer is a simplex write.
+ *
+ * \return Status of transfer start.
+ * \retval STATUS_OK if transfer was started.
+ * \retval STATUS_BUSY if a transfer is already on-going.
+ */
+enum status_code spi_master_vec_transceive_buffer_job(
+		struct spi_master_vec_module *const module,
+		struct spi_master_vec_bufdesc tx_bufdescs[],
+		struct spi_master_vec_bufdesc rx_bufdescs[])
+{
+	Assert(module);
+	Assert(module->sercom);
+	Assert(tx_bufdescs || rx_bufdescs);
+
+	SercomSpi *const spi_hw = &(module->sercom->SPI);
+	uint32_t tmp_ctrlb;
+	uint8_t tmp_intenset;
+
+	system_interrupt_enter_critical_section();
+	if (module->status == STATUS_BUSY) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	} else {
+		module->status = STATUS_BUSY;
+		system_interrupt_leave_critical_section();
+	}
+
+#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
+	CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(module->busy_semaphore);
+#endif
+
+	module->tx_bufdesc_ptr = tx_bufdescs;
+	module->rx_bufdesc_ptr = rx_bufdescs;
+
+	if (tx_bufdescs && rx_bufdescs) {
+		Assert(tx_bufdescs[0].length);
+		Assert(rx_bufdescs[0].length);
+
+		module->direction = SPI_MASTER_VEC_DIRECTION_BOTH;
+		module->tx_length = tx_bufdescs[0].length;
+		module->tx_head_ptr = tx_bufdescs[0].data;
+		module->rx_length = rx_bufdescs[0].length;
+		module->rx_head_ptr = rx_bufdescs[0].data;
+		module->tx_lead_on_rx = 0;
+		tmp_ctrlb = SERCOM_SPI_CTRLB_RXEN;
+		tmp_intenset = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC;
+	} else {
+		if (tx_bufdescs) {
+			Assert(tx_bufdescs[0].length);
+
+			module->direction = SPI_MASTER_VEC_DIRECTION_WRITE;
+			module->tx_length = tx_bufdescs[0].length;
+			module->tx_head_ptr = tx_bufdescs[0].data;
+			tmp_ctrlb = 0;
+			tmp_intenset = SERCOM_SPI_INTFLAG_DRE;
+		} else {
+			Assert(rx_bufdescs[0].length);
+
+			module->direction = SPI_MASTER_VEC_DIRECTION_READ;
+			module->rx_length = rx_bufdescs[0].length;
+			module->rx_head_ptr = rx_bufdescs[0].data;
+			module->tx_lead_on_rx = 0;
+			tmp_ctrlb = SERCOM_SPI_CTRLB_RXEN;
+			tmp_intenset = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC;
+		}
+	}
+
+	/* Ensure the SERCOM is sync'ed before writing these registers */
+	_spi_master_vec_wait_for_sync(spi_hw);
+
+	spi_hw->CTRLB.reg = tmp_ctrlb;
+	spi_hw->INTENSET.reg = tmp_intenset;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Interrupt handler
+ *
+ * \param[in] sercom_index SERCOM instance number passed from the master SERCOM
+ * driver.
+ */
+static void _spi_master_vec_int_handler(uint8_t sercom_index)
+{
+	struct spi_master_vec_module *const module =
+			_sercom_instances[sercom_index];
+	enum _spi_master_vec_direction dir = module->direction;
+	SercomSpi *const spi_hw = &(module->sercom->SPI);
+	uint8_t int_status;
+
+	int_status = spi_hw->INTFLAG.reg ;
+    int_status &= spi_hw->INTENSET.reg;
+
+	if (int_status & SERCOM_SPI_INTFLAG_DRE) {
+		uint_fast8_t tx_lead_on_rx = module->tx_lead_on_rx;
+
+		/* If TX is ahead of RX by 2+ bytes, allow RX to catch up.
+		 * Note: will only happen _once_ per READ or BOTH.
+		 */
+		if ((tx_lead_on_rx >= 2) && (dir != SPI_MASTER_VEC_DIRECTION_WRITE)) {
+			Assert((dir == SPI_MASTER_VEC_DIRECTION_READ)
+					|| (dir == SPI_MASTER_VEC_DIRECTION_BOTH));
+			Assert(int_status & SERCOM_SPI_INTFLAG_RXC);
+		/* Otherwise, we can send more bytes */
+		} else {
+			module->tx_lead_on_rx = ++tx_lead_on_rx;
+
+			/* If doing a READ, just send 0 to trigger the transfer */
+			if (dir == SPI_MASTER_VEC_DIRECTION_READ) {
+				uint32_t tx_lead_limit;
+
+				spi_hw->DATA.reg = 0;
+
+check_for_read_end:
+				/* With current TX'ed bytes, will we get the last RX byte?
+				 * If so, we can disable the DRE interrupt to stop transmitting.
+				 *
+				 * Since a buffer can have minimum 1 byte length, this check is
+				 * simplified by first checking if the RX end is so close that
+				 * the max. 2 byte lead of TX may actually fill the buffers.
+				 */
+				tx_lead_limit = (module->rx_bufdesc_ptr + 1)->length;
+
+				if (!tx_lead_limit || !(module->rx_bufdesc_ptr + 2)->length) {
+					tx_lead_limit += module->rx_length;
+
+					if (tx_lead_on_rx >= tx_lead_limit) {
+						spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE;
+					}
+				}
+			/* For WRITE and BOTH, output current byte */
+			} else {
+				spi_master_vec_buflen_t tx_length;
+				uint8_t *tx_head_ptr;
+
+				tx_head_ptr = module->tx_head_ptr;
+				spi_hw->DATA.reg = *(tx_head_ptr++);
+
+				/* Check if this was the last byte to send */
+				tx_length = module->tx_length - 1;
+
+				if (tx_length) {
+					module->tx_head_ptr = tx_head_ptr;
+					module->tx_length = tx_length;
+				} else {
+				/* Any more buffers left to send, perhaps? */
+					tx_length = (++module->tx_bufdesc_ptr)->length;
+
+					if (tx_length) {
+						module->tx_head_ptr = module->tx_bufdesc_ptr->data;
+						module->tx_length = tx_length;
+					} else {
+						if (dir == SPI_MASTER_VEC_DIRECTION_WRITE) {
+						/* Disable DRE and enable TXC to end WRITE */
+							spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE;
+							spi_hw->INTENSET.reg = SERCOM_SPI_INTFLAG_TXC;
+						} else {
+						/* For BOTH, check if we still have bytes to read */
+							dir = SPI_MASTER_VEC_DIRECTION_READ;
+							module->direction = dir;
+							goto check_for_read_end;
+						}
+					}
+				}
+			}
+		}
+	}
+
+	/* For READ and BOTH, store the received byte */
+	if (int_status & SERCOM_SPI_INTFLAG_RXC) {
+		spi_master_vec_buflen_t rx_length;
+		uint8_t *rx_head_ptr;
+
+		rx_head_ptr = module->rx_head_ptr;
+		if (rx_head_ptr != NULL) {
+			*(rx_head_ptr++) = spi_hw->DATA.reg;
+		} else {
+			uint8_t dummy;
+			dummy = spi_hw->DATA.reg;
+			UNUSED(dummy);
+		}
+		module->tx_lead_on_rx--;
+
+		/* Check if this was the last byte to receive */
+		rx_length = module->rx_length - 1;
+
+		if (rx_length) {
+			module->rx_head_ptr = rx_head_ptr;
+			module->rx_length = rx_length;
+		} else {
+			/* Any more buffers left to receive into? */
+			rx_length = (++module->rx_bufdesc_ptr)->length;
+
+			if (rx_length) {
+				module->rx_head_ptr = module->rx_bufdesc_ptr->data;
+				module->rx_length = rx_length;
+			} else {
+				/* Disable the SPI receiver (instant effect) and RX interrupt */
+				spi_hw->CTRLB.reg = 0;
+				spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_RXC;
+
+				if (dir == SPI_MASTER_VEC_DIRECTION_READ) {
+					/* If doing READ, end the transaction here */
+					dir = SPI_MASTER_VEC_DIRECTION_IDLE;
+					module->direction = dir;
+					module->status = STATUS_OK;
+#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
+					CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(module->busy_semaphore);
+#endif
+				} else {
+					/* If doing BOTH, change direction to WRITE */
+					dir = SPI_MASTER_VEC_DIRECTION_WRITE;
+					module->direction = dir;
+				}
+			}
+		}
+	}
+
+	/* For WRITE */
+	if (int_status & SERCOM_SPI_INTFLAG_TXC) {
+		/* End transaction here, since last byte has been sent */
+		spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC;
+
+		dir = SPI_MASTER_VEC_DIRECTION_IDLE;
+		module->direction = dir;
+		module->status = STATUS_OK;
+#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
+		CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(module->busy_semaphore);
+#endif
+	}
+}
+
+/**
+ * @}
+ */
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h
new file mode 100644
index 0000000000..a10ae22f14
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h
@@ -0,0 +1,692 @@
+/**
+ * \file
+ *
+ * \brief SERCOM SPI master with vectored I/O driver include
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SPI_MASTER_VEC_H
+#define SPI_MASTER_VEC_H
+
+#include <compiler.h>
+#include <gclk.h>
+#include <port.h>
+#include <spi.h>
+#include <status_codes.h>
+#include <conf_spi_master_vec.h>
+
+/**
+ * \defgroup asfdoc_sam0_sercom_spi_master_vec_group SAM Serial Peripheral Interface Master Driver w/ Vectored I/O (SERCOM SPI)
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the configuration
+ * and operation of the SERCOM module in SPI master mode and uses vectored I/O
+ * for data transfers.
+ *
+ * The following peripherals are used by this driver:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this driver:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *
+ * The reader is assumed to be familiar with the regular SERCOM SPI driver, and
+ * how it is configured and operated. Configuration of this driver is done a
+ * similar way and actually re-uses several enumerations (configuration values)
+ * from the regular SERCOM SPI driver.
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_prerequisites
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_module_overview
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_special_considerations
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_info
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_examples
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_api_overview
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_prerequisites Prerequisites
+ *
+ * This driver uses the \ref asfdoc_sam0_system_clock_group "SYSTEM clock driver"
+ * to select the SERCOM's clock source and to configure the SERCOM for the
+ * desired baud rate. Ensure that the selected clock source is configured and
+ * that the clock system is initialized. This is typically done indirectly with
+ * \ref system_init(), or directly with \ref system_clock_init().
+ *
+ * According to the datasheet, the minimum and maximum limits for the baud rate
+ * is given by: \f$ \frac{1}{2^{17}} \times f_{clk} \le f_{baud}
+ * \le \frac{1}{2} \times f_{clk} \f$.
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_module_overview Module Overview
+ *
+ * This SERCOM SPI master driver supports uni- and bidirectional transfers of
+ * 8-bit data with vectored I/O, also know as scatter/gather.
+ * It does not implement control of SS or slave addressing since the intended
+ * usage is in stacks which usually have their own protocols and handshaking
+ * schemes.
+ *
+ *
+ * \subsection asfdoc_sam0_sercom_spi_master_vectored_io Vectored I/O
+ *
+ * Vectored I/O enables the transfer of data from/to any number of buffers with
+ * arbitrary memory locations without having to do several transfers, i.e., one
+ * buffer at a time. This feature is useful in stacks because it allows each
+ * layer of the stack to have a dedicated data buffer, thus avoiding the need
+ * for a centralized data buffer that the different layers must use in
+ * cooperation.
+ *
+ * The vectored I/O relies on arrays of buffer descriptors which must be passed
+ * to the driver to start a transfer. These buffer descriptors specify where in
+ * memory each buffer is, and how large they are.
+ * \ref asfdoc_sam0_vectored_io_example "The figure below" illustrates this
+ * for an example with three buffers of varying sizes that are transmitted.
+ *
+ * \anchor asfdoc_sam0_vectored_io_example
+ * \dot
+digraph bufptr_to_spiord {
+	rankdir=LR;
+	subgraph cluster_bufptr {
+		style=invis;
+		bufptr_label [shape=none, label="Buffer descriptors"];
+		bufptrs [shape=record, label="<bf1> [0]|<bf2> [1]|<bf3> [2]|<bf4> [3]"];
+	}
+	subgraph cluster_buf {
+		style=invis;
+		buf_label [shape=none, label="Memory layout"];
+		bufs [shape=record, label="...|<b1>&quot;yy&quot;|...|<b3>&quot;z&quot;|<b2>&quot;xxx&quot;|..."];
+	}
+	subgraph cluster_spiord {
+		style=invis;
+		spiord_label [shape=none, label="SPI transmission"];
+		spiord [shape=record, label="<s1>&quot;yy&quot;|<s2>&quot;xxx&quot;|<s3>&quot;z&quot;"];
+	}
+	bufptrs:bf1 -> bufs:b1 -> spiord:s1;
+	bufptrs:bf2 -> bufs:b2 -> spiord:s2;
+	bufptrs:bf3 -> bufs:b3 -> spiord:s3;
+	bufptrs:bf4 -> "none";
+}
+ * \enddot
+ *
+ * Note that the last descriptor \e must indicate no next buffer in order for
+ * the driver to detect that the end of the buffer list has been reached. This
+ * means that for \c N buffers, \c N+1 buffer descriptors are needed.
+ *
+ * Bidirectional transfers are supported without any restrictions on the buffer
+ * descriptors, so the number of bytes and buffers to receive and transmit do
+ * \e not have to be the same.
+ *
+ * \sa spi_master_vec_transceive_buffer_job() for details on starting transfers.
+ *
+ *
+ * \subsection asfdoc_sam0_sercom_spi_master_os_support OS support
+ *
+ * Since this driver is interrupt-driven, it is possible for the MCU to run
+ * other code while a transfer is on-going.
+ *
+ * In a single-threaded application, this can be achieved by starting a transfer
+ * and then avoid any waiting for completion until absolutely required, e.g.,
+ * when a new transfer is needed.
+ *
+ * But in a multi-threaded application, for example based on FreeRTOS, one can
+ * utilize \e semaphores to let the OS know when a function is waiting and thus
+ * blocking the thread, and that other threads can be run instead. Put another
+ * way, the waiting can be made efficient.
+ *
+ * This driver has an internal semaphore which is used to signal to the OS
+ * whenever a function is waiting for a transfer to complete. And since the
+ * semaphore datatypes and functions are OS-specific, the support has been made
+ * configurable by the use of macros. Note that support for FreeRTOS is already
+ * implemented, but must be enabled.
+ *
+ * \sa CONF_SPI_MASTER_VEC_OS_SUPPORT for more on the configurable OS support.
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_sercom_spi_master_vec_special_isr Interrupt safety
+ *
+ * This driver should not be used within interrupt contexts. The reason for this
+ * is that the driver itself is interrupt driven. Further, the configurable OS
+ * support is implemented with the assumption that transfers are only started
+ * in threads, not in interrupt service routines, because it gives the simplest
+ * API.
+ *
+ *
+ * \subsection asfdoc_sam0_sercom_spi_master_vec_special_mux Signal MUX
+ *
+ * The SERCOM module has two layers of signal multiplexing in SPI mode:
+ * -# SERCOM pad MUX: This routes the SPI signals to internal lines.
+ * -# PORT pin MUX: This routes the internal line to a device pin.
+ *
+ * Both of these layers are configured in the \ref spi_master_vec_config
+ * "configuration structure", using the members named \c mux_setting and
+ * \c pinmux_padN. These must be set in combination.
+ *
+ * The driver supplies values for the
+ * \ref spi_master_vec_config::mux_setting "SERCOM pad MUX" from the standard
+ * ASF SERCOM SPI driver. For the PORT pin MUX configuration, refer to the
+ * peripheral include file for the device (\c pio_samd20XNN.h ) and use the
+ * macros that are prefixed with \c PINMUX_, such as
+ * \c PINMUX_PA04D_SERCOM0_PAD0. It is also possible to use the default pin MUX
+ * setting for a SERCOM pad by using the \ref PINMUX_DEFAULT macro. The defaults
+ * are defined in the file \ref sercom_pinout.h.
+ *
+ * Note that for \ref spi_master_vec_init() to function properly with the macro
+ * \ref PINMUX_DEFAULT, the order of the values in \c pinmux_padN \e must be
+ * correct, i.e., \c pinmux_pad0 must contain the pin MUX setting for
+ * multiplexing SERCOM pad 0, and so on.
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_extra_info Extra Information
+ *
+ * For extra information, see
+ * \subpage asfdoc_sam0_sercom_spi_master_vec_extra. This includes:
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_acronyms
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_dependencies
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_errata
+ * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_history
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_spi_master_vec_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_api_overview API Overview
+ *
+ * @{
+ */
+
+/**
+ * Driver configuration structure
+ *
+ * \sa asfdoc_sam0_sercom_spi_master_vec_special_considerations for more
+ * information regarding SERCOM pad and pin MUX.
+ */
+struct spi_master_vec_config {
+	/** Baud rate in Hertz. */
+	uint32_t baudrate;
+	/** GCLK generator to use for the SERCOM. */
+	enum gclk_generator gclk_generator;
+	/** Enabled in sleep modes. */
+	bool run_in_standby;
+	/** SERCOM pad MUX setting. */
+	enum spi_signal_mux_setting mux_setting;
+	/** Transfer mode. */
+	enum spi_transfer_mode transfer_mode;
+	/** Data order. */
+	enum spi_data_order data_order;
+	/** Pin MUX setting for SERCOM pad 0. */
+	uint32_t pinmux_pad0;
+	/** Pin MUX setting for SERCOM pad 1. */
+	uint32_t pinmux_pad1;
+	/** Pin MUX setting for SERCOM pad 2. */
+	uint32_t pinmux_pad2;
+	/** Pin MUX setting for SERCOM pad 4. */
+	uint32_t pinmux_pad3;
+};
+
+/** Buffer length container. */
+typedef uint16_t spi_master_vec_buflen_t;
+
+/** Buffer descriptor structure. */
+struct spi_master_vec_bufdesc {
+	/** Pointer to buffer start. */
+	void *data;
+	/** Length of buffer. */
+	spi_master_vec_buflen_t length;
+};
+
+/** Transfer direction */
+enum _spi_master_vec_direction {
+	SPI_MASTER_VEC_DIRECTION_READ,
+	SPI_MASTER_VEC_DIRECTION_WRITE,
+	SPI_MASTER_VEC_DIRECTION_BOTH,
+	SPI_MASTER_VEC_DIRECTION_IDLE,
+};
+
+/** Driver instance. */
+struct spi_master_vec_module {
+#if !defined(__DOXYGEN__)
+	Sercom *volatile sercom;
+	volatile bool locked;
+	volatile enum _spi_master_vec_direction direction;
+	volatile enum status_code status;
+	volatile spi_master_vec_buflen_t rx_length;
+	volatile spi_master_vec_buflen_t tx_length;
+	uint8_t *volatile rx_head_ptr;
+	uint8_t *volatile tx_head_ptr;
+	volatile uint_fast8_t tx_lead_on_rx;
+	struct spi_master_vec_bufdesc *volatile rx_bufdesc_ptr;
+	struct spi_master_vec_bufdesc *volatile tx_bufdesc_ptr;
+#  ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
+	CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE busy_semaphore;
+#  endif
+#endif
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initialize configuration with default values.
+ *
+ * \param[out] config Configuration struct to initialize.
+ */
+static inline void spi_master_vec_get_config_defaults(
+		struct spi_master_vec_config *const config)
+{
+	config->baudrate = 100000;
+	config->gclk_generator = GCLK_GENERATOR_0;
+	config->run_in_standby = false;
+	config->mux_setting = SPI_SIGNAL_MUX_SETTING_D;
+	config->transfer_mode = SPI_TRANSFER_MODE_0;
+	config->data_order = SPI_DATA_ORDER_MSB;
+	config->pinmux_pad0 = PINMUX_DEFAULT;
+	config->pinmux_pad1 = PINMUX_DEFAULT;
+	config->pinmux_pad2 = PINMUX_DEFAULT;
+	config->pinmux_pad3 = PINMUX_DEFAULT;
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum status_code spi_master_vec_init(struct spi_master_vec_module *const module,
+		Sercom *const sercom, const struct spi_master_vec_config *const config);
+
+/** @} */
+
+/**
+ * \name Enable/Disable and Reset
+ * @{
+ */
+
+void spi_master_vec_enable(const struct spi_master_vec_module *const module);
+void spi_master_vec_disable(struct spi_master_vec_module *const module);
+void spi_master_vec_reset(struct spi_master_vec_module *const module);
+
+/** @} */
+
+/**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock.
+ *
+ * \retval STATUS_OK if the module was locked.
+ * \retval STATUS_BUSY if the module was already locked.
+ */
+static inline enum status_code spi_master_vec_lock(
+		struct spi_master_vec_module *const module)
+{
+	enum status_code status;
+
+	system_interrupt_enter_critical_section();
+
+	if (module->locked) {
+		status = STATUS_BUSY;
+	} else {
+		module->locked = true;
+		status = STATUS_OK;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock.
+ */
+static inline void spi_master_vec_unlock(
+		struct spi_master_vec_module *const module)
+{
+	module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \name Read/Write and Status
+ * @{
+ */
+
+enum status_code spi_master_vec_transceive_buffer_job(
+		struct spi_master_vec_module *const module,
+		struct spi_master_vec_bufdesc tx_bufdescs[],
+		struct spi_master_vec_bufdesc rx_bufdescs[]);
+
+/**
+ * \brief Get current status of transfer.
+ *
+ * \param[in] module Driver instance to operate on.
+ *
+ * \return Current status of driver instance.
+ * \retval STATUS_OK if idle and previous transfer succeeded.
+ * \retval STATUS_BUSY if a transfer is ongoing.
+ * \retval <other> if previous transfer failed.
+ */
+static inline enum status_code spi_master_vec_get_job_status(
+		const struct spi_master_vec_module *const module)
+{
+	return module->status;
+}
+
+/**
+ * \brief Get status of transfer upon job end.
+ *
+ * \param[in]  module Driver instance to operate on.
+ *
+ * \return Current status of driver instance.
+ * \retval STATUS_OK if idle and previous transfer succeeded.
+ * \retval <other> if previous transfer failed.
+ */
+static inline enum status_code spi_master_vec_get_job_status_wait(
+		const struct spi_master_vec_module *const module)
+{
+	enum status_code status;
+
+#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
+	CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(module->busy_semaphore);
+	status = spi_master_vec_get_job_status(module);
+	CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE(module->busy_semaphore);
+#else
+	do {
+		status = spi_master_vec_get_job_status(module);
+	} while (status == STATUS_BUSY);
+#endif
+
+	return status;
+}
+
+
+/**
+ * \brief Start vectored I/O transfer, wait for it to end.
+ *
+ * \param[in,out] module Driver instance to operate on.
+ * \param[in] tx_bufdescs address of buffer descriptor array for bytes to
+ * transmit.
+ * \arg \c NULL if the transfer is a simplex read.
+ * \param[in,out] rx_bufdescs address of buffer descriptor array for storing
+ * received bytes.
+ * \arg \c NULL if the transfer is a simplex write.
+ *
+ * \return Status of transfer start.
+ * \retval STATUS_OK if transfer succeeded.
+ * \retval STATUS_BUSY if a transfer was already on-going.
+ * \retval <other> if transfer failed.
+ */
+static inline enum status_code spi_master_vec_transceive_buffer_wait(
+		struct spi_master_vec_module *const module,
+		struct spi_master_vec_bufdesc tx_bufdescs[],
+		struct spi_master_vec_bufdesc rx_bufdescs[])
+{
+	enum status_code status;
+
+	status = spi_master_vec_transceive_buffer_job(module, tx_bufdescs,
+			rx_bufdescs);
+
+	if (status == STATUS_BUSY) {
+		return status;
+	}
+
+	return spi_master_vec_get_job_status_wait(module);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \name OS Support Configuration
+ * @{
+ */
+
+/**
+ * \def CONF_SPI_MASTER_VEC_OS_SUPPORT
+ * \brief Enable support for OS
+ *
+ * Defining this symbol will enable support for an OS, e.g., FreeRTOS, by using
+ * the macros in this group:
+ * - \ref CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE
+ * - \ref CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE
+ * - \ref CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE
+ * - \ref CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE
+ * - \ref CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE
+ * - \ref CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR
+ *
+ * The user must ensure that these macros map to the implementation for the OS
+ * that is used. Further, required includes must be added alongside these macros
+ * in \ref conf_spi_master_vec.h.
+ *
+ * The purpose of this configuration is to enable usage of the OS' semaphore
+ * system to wait for transfers to end rather than continuously polling the
+ * transfer status, which is an inefficient approach.
+ */
+
+/**
+ * \def CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE
+ * \brief Semaphore datatype
+ */
+
+/**
+ * \def CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE
+ * \brief Create/initialize semaphore
+ *
+ * \param semaphore Semaphore member in driver instance.
+ */
+
+/**
+ * \def CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE
+ * \brief Delete semaphore
+ *
+ * \param semaphore Semaphore member in driver instance.
+ */
+
+/**
+ * \def CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE
+ * \brief Wait for and take semaphore
+ *
+ * \param semaphore Semaphore member in driver instance.
+ */
+
+/**
+ * \def CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE
+ * \brief Give semaphore back
+ *
+ * \param semaphore Semaphore member in driver instance.
+ */
+
+/**
+ * \def CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR
+ * \brief Give semaphore back from an ISR
+ *
+ * \param semaphore Semaphore member in driver instance.
+ */
+
+/** @} */
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_spi_master_vec_extra Extra Information for SERCOM SPI Master Driver w/ Vectored I/O
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_extra_acronyms Acronyms
+ *
+ * The table below presents the acronyms used in this module.
+ *
+ * <table>
+ *     <tr>
+ *         <th>Acronym</td>
+ *         <th>Description</td>
+ *     </tr>
+ *     <tr>
+ *         <td>GCLK</td>
+ *         <td>Generic Clock</td>
+ *     </tr>
+ *     <tr>
+ *         <td>MISO</td>
+ *         <td>Master Input, Slave Output</td>
+ *     </tr>
+ *     <tr>
+ *         <td>MOSI</td>
+ *         <td>Master Output, Slave Input</td>
+ *     </tr>
+ *     <tr>
+ *         <td>SCK</td>
+ *         <td>Serial Clock</td>
+ *     </tr>
+ *     <tr>
+ *         <td>SPI</td>
+ *         <td>Serial Peripheral Interface</td>
+ *     </tr>
+ *     <tr>
+ *         <td>SS</td>
+ *         <td>Slave Select</td>
+ *     </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_extra_dependencies Dependencies
+ *
+ * This driver has the following dependencies:
+ * - \ref asfdoc_sam0_system_group "System driver"
+ * - \ref group_sam0_utils "Compiler driver"
+ * - \ref asfdoc_sam0_port_group "Port driver"
+ * - \ref Common SERCOM driver base
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_extra_errata Errata
+ *
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_vec_extra_history Module History
+ *
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in the
+ * table.
+ *
+ * <table>
+ *     <tr>
+ *         <th>Changelog</th>
+ *     </tr>
+ *     <tr>
+ *         <td>Initial Release</td>
+ *     </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_spi_master_vec_exqsg Examples for SERCOM SPI Master Driver w/ Vectored I/O
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_spi_master_vec_group. QSGs are
+ * simple examples with step-by-step instructions to configure and use this
+ * driver in a selection of use cases. Note that QSGs can be compiled as a
+ * standalone application or be added to the user application.
+ *
+ * - \subpage asfdoc_sam0_sercom_spi_master_vec_basic
+ */
+
+ /**
+  * \page asfdoc_sam0_sercom_spi_master_vec_document_revision_history Document Revision History
+  *
+  * <table>
+  *      <tr>
+  *         <th>Doc. Rev.</td>
+  *         <th>Date</td>
+  *         <th>Comments</td>
+  *      </tr>
+  *      <tr>
+  *           <td>D</td>
+  *           <td>12/2014</td>
+  *           <td>Add SAM L21/C21 support.</td>
+  *     </tr>
+  *      <tr>
+  *           <td>C</td>
+  *           <td>04/2014</td>
+  *           <td>Add SAM D10/D11 support.</td>
+  *     </tr>
+  *     <tr>
+  *           <td>B</td>
+  *           <td>03/2014</td>
+  *           <td>Add SAMR21 support.</td>
+  *     </tr>
+  *     <tr>
+  *         <td>A</td>
+  *         <td>01/2014</td>
+  *         <td>Initial release</td>
+  *     </tr>
+  * </table>
+  */
+
+#endif /* SPI_MASTER_VEC_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.c
new file mode 100644
index 0000000000..e916cf5bd4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.c
@@ -0,0 +1,818 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "usart.h"
+#include <pinmux.h>
+#if USART_CALLBACK_MODE == true
+#  include "usart_interrupt.h"
+#endif
+
+/**
+ * \internal
+ * Set Configuration of the USART module
+ */
+static enum status_code _usart_set_config(
+		struct usart_module *const module,
+		const struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Index for generic clock */
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+	/* Cache new register values to minimize the number of register writes */
+	uint32_t ctrla = 0;
+	uint32_t ctrlb = 0;
+#ifdef FEATURE_USART_ISO7816
+	uint32_t ctrlc = 0;
+#endif
+	uint16_t baud  = 0;
+	uint32_t transfer_mode;
+
+	enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+	enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+	switch (config->sample_rate) {
+		case USART_SAMPLE_RATE_16X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+			break;
+		case USART_SAMPLE_RATE_8X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+			break;
+		case USART_SAMPLE_RATE_3X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
+			break;
+		case USART_SAMPLE_RATE_16X_FRACTIONAL:
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+			break;
+		case USART_SAMPLE_RATE_8X_FRACTIONAL:
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+			break;
+	}
+#endif
+
+	/* Set data order, internal muxing, and clock polarity */
+	ctrla = (uint32_t)config->data_order |
+		(uint32_t)config->mux_setting |
+	#ifdef FEATURE_USART_OVER_SAMPLE
+		config->sample_adjustment |
+		config->sample_rate |
+	#endif
+	#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+	#endif
+		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+
+	enum status_code status_code = STATUS_OK;
+
+	transfer_mode = (uint32_t)config->transfer_mode;
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		transfer_mode = config->iso7816_config.protocol_t;
+	}
+#endif
+	/* Get baud value from mode and clock */
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		baud = config->baudrate;
+	} else {
+#endif
+	switch (transfer_mode)
+	{
+		case USART_TRANSFER_SYNCHRONOUSLY:
+			if (!config->use_external_clock) {
+				status_code = _sercom_get_sync_baud_val(config->baudrate,
+						system_gclk_chan_get_hz(gclk_index), &baud);
+			}
+
+			break;
+
+		case USART_TRANSFER_ASYNCHRONOUSLY:
+			if (config->use_external_clock) {
+				status_code =
+						_sercom_get_async_baud_val(config->baudrate,
+							config->ext_clock_freq, &baud, mode, sample_num);
+			} else {
+				status_code =
+						_sercom_get_async_baud_val(config->baudrate,
+							system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
+			}
+
+			break;
+	}
+
+	/* Check if calculating the baudrate failed */
+	if (status_code != STATUS_OK) {
+		/* Abort */
+		return status_code;
+	}
+#ifdef FEATURE_USART_ISO7816
+	}
+#endif
+
+#ifdef FEATURE_USART_IRDA
+	if(config->encoding_format_enable) {
+		usart_hw->RXPL.reg = config->receive_pulse_length;
+	}
+#endif
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/*Set baud val */
+	usart_hw->BAUD.reg = baud;
+
+	/* Set sample mode */
+	ctrla |= transfer_mode;
+
+	if (config->use_external_clock == false) {
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
+	}
+	else {
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
+	}
+
+	/* Set stopbits and enable transceivers */
+	ctrlb =  
+		#ifdef FEATURE_USART_IRDA
+			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+		#endif
+		#ifdef FEATURE_USART_START_FRAME_DECTION
+			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+		#endif
+		#ifdef FEATURE_USART_COLLISION_DECTION
+			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+		#endif
+			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+			(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
+
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
+		if (config->iso7816_config.enable_inverse) {
+			ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
+		}
+		ctrlb |=  USART_CHARACTER_SIZE_8BIT;
+		
+		switch(config->iso7816_config.protocol_t) {
+			case ISO7816_PROTOCOL_T_0:
+				ctrlb |= (uint32_t)config->stopbits;	
+				ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
+						(config->iso7816_config.inhibit_nack) | \
+						(config->iso7816_config.successive_recv_nack) | \
+						SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
+				break;	
+			case ISO7816_PROTOCOL_T_1:
+				ctrlb |= USART_STOPBITS_1;
+				break;		
+		}
+	} else {
+#endif
+	ctrlb |= (uint32_t)config->stopbits;
+	ctrlb |= (uint32_t)config->character_size;
+	/* Check parity mode bits */
+	if (config->parity != USART_PARITY_NONE) {
+		ctrla |= SERCOM_USART_CTRLA_FORM(1);
+		ctrlb |= config->parity;
+	} else {
+#ifdef FEATURE_USART_LIN_SLAVE
+		if(config->lin_slave_enable) {
+			ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
+		} else {
+			ctrla |= SERCOM_USART_CTRLA_FORM(0);
+		}
+#else
+		ctrla |= SERCOM_USART_CTRLA_FORM(0);
+#endif
+	}
+#ifdef FEATURE_USART_ISO7816
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_MASTER
+	usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
+						| config->lin_header_delay
+						| config->lin_break_length;
+
+	if (config->lin_node != LIN_INVALID_MODE) {
+		ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
+		ctrla |= config->lin_node;
+	}
+#endif
+
+	/* Set whether module should run in standby. */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
+	}
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write configuration to CTRLB */
+	usart_hw->CTRLB.reg = ctrlb;
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write configuration to CTRLA */
+	usart_hw->CTRLA.reg = ctrla;
+
+#ifdef FEATURE_USART_RS485
+	if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
+		SERCOM_USART_CTRLA_FORM(0x07)) {
+		usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
+		usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
+	}
+#endif
+
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		_usart_wait_for_sync(module);
+		usart_hw->CTRLC.reg = ctrlc;
+	}
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the device
+ *
+ * Initializes the USART device based on the setting specified in the
+ * configuration struct.
+ *
+ * \param[out] module  Pointer to USART device
+ * \param[in]  hw      Pointer to USART hardware instance
+ * \param[in]  config  Pointer to configuration struct
+ *
+ * \return Status of the initialization.
+ *
+ * \retval STATUS_OK                       The initialization was successful
+ * \retval STATUS_BUSY                     The USART module is busy
+ *                                         resetting
+ * \retval STATUS_ERR_DENIED               The USART has not been disabled in
+ *                                         advance of initialization
+ * \retval STATUS_ERR_INVALID_ARG          The configuration struct contains
+ *                                         invalid configuration
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  The SERCOM instance has already been
+ *                                         initialized with different clock
+ *                                         configuration
+ * \retval STATUS_ERR_BAUD_UNAVAILABLE     The BAUD rate given by the
+ *                                         configuration
+ *                                         struct cannot be reached with
+ *                                         the current clock configuration
+ */
+enum status_code usart_init(
+		struct usart_module *const module,
+		Sercom *const hw,
+		const struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	enum status_code status_code = STATUS_OK;
+
+	/* Assign module pointer to software instance struct */
+	module->hw = hw;
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index, gclk_index; 
+#if (SAML22) || (SAMC20) 
+	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+#elif (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#elif (SAMC21)
+	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	
+	if (sercom_index == 5){
+		gclk_index	= SERCOM5_GCLK_ID_CORE;
+    } else {
+    	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
+#else
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+		/* The module is busy resetting itself */
+		return STATUS_BUSY;
+	}
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+		/* Check the module is enabled */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Turn on module in PM */
+#if (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+	} else {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);	
+	}
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+#endif
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+	/* Set character size */
+	module->character_size = config->character_size;
+
+	/* Set transmitter and receiver status */
+	module->receiver_enabled = config->receiver_enable;
+	module->transmitter_enabled = config->transmitter_enable;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	module->lin_slave_enabled = config->lin_slave_enable;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	module->start_frame_detection_enabled = config->start_frame_detection_enable;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	module->iso7816_mode_enabled = config->iso7816_config.enabled;
+#endif
+	/* Set configuration according to the config struct */
+	status_code = _usart_set_config(module, config);
+	if(status_code != STATUS_OK) {
+		return status_code;
+	}
+
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+	pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+	uint32_t pad_pinmuxes[] = {
+			config->pinmux_pad0, config->pinmux_pad1,
+			config->pinmux_pad2, config->pinmux_pad3
+		};
+
+	/* Configure the SERCOM pins according to the user configuration */
+	for (uint8_t pad = 0; pad < 4; pad++) {
+		uint32_t current_pinmux = pad_pinmuxes[pad];
+
+		if (current_pinmux == PINMUX_DEFAULT) {
+			current_pinmux = _sercom_get_default_pad(hw, pad);
+		}
+
+		if (current_pinmux != PINMUX_UNUSED) {
+			pin_conf.mux_position = current_pinmux & 0xFFFF;
+			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+		}
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Initialize parameters */
+	for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
+		module->callback[i]            = NULL;
+	}
+
+	module->tx_buffer_ptr              = NULL;
+	module->rx_buffer_ptr              = NULL;
+	module->remaining_tx_buffer_length = 0x0000;
+	module->remaining_rx_buffer_length = 0x0000;
+	module->callback_reg_mask          = 0x00;
+	module->callback_enable_mask       = 0x00;
+	module->rx_status                  = STATUS_OK;
+	module->tx_status                  = STATUS_OK;
+
+	/* Set interrupt handler and register USART software module struct in
+	 * look-up table */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+	_sercom_set_handler(instance_index, _usart_interrupt_handler);
+	_sercom_instances[instance_index] = module;
+#endif
+
+	return status_code;
+}
+
+/**
+ * \brief Transmit a character via the USART
+ *
+ * This blocking function will transmit a single character via the
+ * USART.
+ *
+ * \param[in]  module   Pointer to the software instance struct
+ * \param[in]  tx_data  Data to transfer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK         If the operation was completed
+ * \retval STATUS_BUSY       If the operation was not completed, due to the USART
+ *                           module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_wait(
+		struct usart_module *const module,
+		const uint16_t tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Check if the USART is busy doing asynchronous operation. */
+	if (module->remaining_tx_buffer_length > 0) {
+		return STATUS_BUSY;
+	}
+
+#else
+	/* Check if USART is ready for new data */
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+		/* Return error code */
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write data to USART module */
+	usart_hw->DATA.reg = tx_data;
+
+	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+		/* Wait until data is sent */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a character via the USART
+ *
+ * This blocking function will receive a character via the USART.
+ *
+ * \param[in]   module   Pointer to the software instance struct
+ * \param[out]  rx_data  Pointer to received data
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If the operation was completed
+ * \retval STATUS_BUSY              If the operation was not completed,
+ *                                  due to the USART module being busy
+ * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
+ *                                  due to configuration mismatch between USART
+ *                                  and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
+ *                                  due to the baudrate being too low or the
+ *                                  system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due to
+ *                                  data being corrupted
+ * \retval STATUS_ERR_DENIED        If the receiver is not enabled
+ */
+enum status_code usart_read_wait(
+		struct usart_module *const module,
+		uint16_t *const rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Error variable */
+	uint8_t error_code;
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Check if the USART is busy doing asynchronous operation. */
+	if (module->remaining_rx_buffer_length > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Check if USART has new data */
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+		/* Return error code */
+		return STATUS_BUSY;
+	}
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Read out the status code and mask away all but the 3 LSBs*/
+	error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+
+	/* Check if an error has occurred during the receiving */
+	if (error_code) {
+		/* Check which error occurred */
+		if (error_code & SERCOM_USART_STATUS_FERR) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+
+			return STATUS_ERR_BAD_FORMAT;
+		} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+
+			return STATUS_ERR_OVERFLOW;
+		} else if (error_code & SERCOM_USART_STATUS_PERR) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+
+			return STATUS_ERR_BAD_DATA;
+		}
+#ifdef FEATURE_USART_LIN_SLAVE
+		else if (error_code & SERCOM_USART_STATUS_ISF) {
+			/* Clear flag by writing 1 to it  and
+			 *  return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+
+			return STATUS_ERR_PROTOCOL;
+		}
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+		else if (error_code & SERCOM_USART_STATUS_COLL) {
+			/* Clear flag by writing 1 to it
+			 *  return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+
+			return STATUS_ERR_PACKET_COLLISION;
+		}
+#endif
+	}
+
+	/* Read data from USART module */
+	*rx_data = usart_hw->DATA.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Transmit a buffer of characters via the USART
+ *
+ * This blocking function will transmit a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c _job) functions is
+ *       not recommended as it has no functionality to check if there is an
+ *       ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer to data to transmit
+ * \param[in]  length   Number of characters to transmit
+ *
+ * \note If using 9-bit data, the array that *tx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define TX_LEN 3
+          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+          usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN);
+    \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK              If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_TIMEOUT     If operation was not completed, due to USART
+ *                                module timing out
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_wait(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Check if the buffer length is valid */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	uint16_t tx_pos = 0;
+
+	/* Blocks while buffer is being transferred */
+	while (length--) {
+		/* Wait for the USART to be ready for new data and abort
+		* operation if it doesn't get ready within the timeout*/
+		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
+				break;
+			} else if (i == USART_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+
+		/* Data to send is at least 8 bits long */
+		uint16_t data_to_send = tx_data[tx_pos++];
+
+		/* Check if the character size exceeds 8 bit */
+		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+			data_to_send |= (tx_data[tx_pos++] << 8);
+		}
+
+		/* Send the data through the USART module */
+		usart_write_wait(module, data_to_send);
+	}
+
+	/* Wait until Transmit is complete or timeout */
+	for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+		if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
+			break;
+		} else if (i == USART_TIMEOUT) {
+			return STATUS_ERR_TIMEOUT;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a buffer of \c length characters via the USART
+ *
+ * This blocking function will receive a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c *_job)
+ *       functions is not recommended as it has no functionality to check if
+ *       there is an ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[out] rx_data  Pointer to receive buffer
+ * \param[in]  length   Number of characters to receive
+ *
+ * \note If using 9-bit data, the array that *rx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define RX_LEN 3
+          uint16_t rx_buf[RX_LEN] = {0x0,};
+          usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN);
+    \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG   If operation was not completed, due to an
+ *                                  invalid argument being supplied
+ * \retval STATUS_ERR_TIMEOUT       If operation was not completed, due
+ *                                  to USART module timing out
+ * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
+ *                                  due to a configuration mismatch
+ *                                  between USART and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
+ *                                  due to the baudrate being too low or the
+ *                                  system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due
+ *                                  to data being corrupted
+ * \retval STATUS_ERR_DENIED        If the receiver is not enabled
+ */
+enum status_code usart_read_buffer_wait(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Check if the buffer length is valid */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint16_t rx_pos = 0;
+
+	/* Blocks while buffer is being received */
+	while (length--) {
+		/* Wait for the USART to have new data and abort operation if it
+		 * doesn't get ready within the timeout*/
+		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
+				break;
+			} else if (i == USART_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+
+		enum status_code retval;
+		uint16_t received_data = 0;
+
+		retval = usart_read_wait(module, &received_data);
+
+		if (retval != STATUS_OK) {
+			/* Overflow, abort */
+			return retval;
+		}
+
+		/* Read value will be at least 8-bits long */
+		rx_data[rx_pos++] = received_data;
+
+		/* If 9-bit data, write next received byte to the buffer */
+		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+			rx_data[rx_pos++] = (received_data >> 8);
+		}
+	}
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.h
new file mode 100644
index 0000000000..f1bb0d4fcd
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.h
@@ -0,0 +1,1596 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef USART_H_INCLUDED
+#define USART_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_sercom_usart_group SAM Serial USART (SERCOM USART) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the SERCOM module in
+ * its USART mode to transfer or receive USART data frames. The following driver
+ * API modes are covered by this manual:
+ *
+ *  - Polled APIs
+ * \if USART_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_usart_prerequisites
+ * - \ref asfdoc_sam0_sercom_usart_overview
+ * - \ref asfdoc_sam0_sercom_usart_special_considerations
+ * - \ref asfdoc_sam0_sercom_usart_extra_info
+ * - \ref asfdoc_sam0_sercom_usart_examples
+ * - \ref asfdoc_sam0_sercom_usart_api_overview
+ *
+ * \section asfdoc_sam0_sercom_usart_prerequisites Prerequisites
+ *
+ * To use the USART you need to have a GCLK generator enabled and running
+ * that can be used as the SERCOM clock source. This can either be configured
+ * in conf_clocks.h or by using the system clock driver.
+ *
+ * \section asfdoc_sam0_sercom_usart_overview Module Overview
+ *
+ * This driver will use one (or more) SERCOM interface(s) in the system
+ * and configure it to run as a USART interface in either synchronous
+ * or asynchronous mode.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_SYNC_SCHEME_V2</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_OVER_SAMPLE</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_HARDWARE_FLOW_CONTROL</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_IRDA</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_LIN_SLAVE</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_COLLISION_DECTION</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_START_FRAME_DECTION</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_RS485</td>
+ *    <td>SAM C20/C21</td>
+ *  </tr>
+ * <tr>
+ *    <td>FEATURE_USART_LIN_MASTER</td>
+ *    <td>SAM L22/C20/C21</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_frame_format Frame Format
+ *
+ * Communication is based on frames, where the frame format can be customized
+ * to accommodate a wide range of standards. A frame consists of a start bit,
+ * a number of data bits, an optional parity bit for error detection as well
+ * as a configurable length stop bit(s) - see
+ * \ref asfdoc_sam0_sercom_usart_frame_diagram "the figure below".
+ * \ref asfdoc_sam0_sercom_usart_frame_params "The table below" shows the
+ * available parameters you can change in a frame.
+ *
+ * \anchor asfdoc_sam0_sercom_usart_frame_params
+ * <table>
+ *  <caption>USART Frame Parameters</caption>
+ *  <tr>
+ *      <th>Parameter</th>
+ *      <th>Options</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Start bit</td>
+ *      <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Data bits</td>
+ *      <td>5, 6, 7, 8, 9</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Parity bit</td>
+ *      <td>None, Even, Odd</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Stop bits</td>
+ *      <td>1, 2</td>
+ *  </tr>
+ * </table>
+ *
+ * \anchor asfdoc_sam0_sercom_usart_frame_diagram
+ * \image html usart_frame.svg "USART Frame Overview" width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_sync Synchronous Mode
+ *
+ * In synchronous mode a dedicated clock line is provided; either by the USART
+ * itself if in master mode, or by an external master if in slave mode.
+ * Maximum transmission speed is the same as the GCLK clocking the USART
+ * peripheral when in slave mode, and the GCLK divided by two if in
+ * master mode. In synchronous mode the interface needs three lines to
+ * communicate:
+ * - TX (Transmit pin)
+ * - RX (Receive pin)
+ * - XCK (Clock pin)
+ *
+ * \subsubsection asfdoc_sam0_sercom_usart_overview_sync_sampling Data Sampling
+ * In synchronous mode the data is sampled on either the rising or falling edge
+ * of the clock signal. This is configured by setting the clock polarity in the
+ * configuration struct.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_async Asynchronous Mode
+ *
+ * In asynchronous mode no dedicated clock line is used, and the communication
+ * is based on matching the clock speed on the transmitter and receiver. The
+ * clock is generated from the internal SERCOM baudrate generator, and the
+ * frames are synchronized by using the frame start bits. Maximum transmission
+ * speed is limited to the SERCOM GCLK divided by 16.
+ * In asynchronous mode the interface only needs two lines to communicate:
+ * - TX (Transmit pin)
+ * - RX (Receive pin)
+ *
+ * \subsubsection asfdoc_sam0_sercom_usart_overview_async_clock_matching Transmitter/receiver Clock Matching
+ *
+ * For successful transmit and receive using the asynchronous mode the receiver
+ * and transmitter clocks needs to be closely matched. When receiving a frame
+ * that does not match the selected baudrate closely enough the receiver will
+ * be unable to synchronize the frame(s), and garbage transmissions will
+ * result.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_parity Parity
+ * Parity can be enabled to detect if a transmission was in error. This is done
+ * by counting the number of "1" bits in the frame. When using even parity the
+ * parity bit will be set if the total number of "1"s in the frame are an even
+ * number. If using odd parity the parity bit will be set if the total number
+ * of "1"s are odd.
+ *
+ * When receiving a character the receiver will count the number of "1"s in the
+ * frame and give an error if the received frame and parity bit disagree.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_pin_configuration GPIO Configuration
+ *
+ * The SERCOM module has four internal pads; the RX pin can be placed freely on
+ * any one of the four pads, and the TX and XCK pins have two predefined
+ * positions that can be selected as a pair. The pads can then be routed to an
+ * external GPIO pin using the normal pin multiplexing scheme on the SAM.
+ *
+ * \section asfdoc_sam0_sercom_usart_special_considerations Special Considerations
+ *
+ * \if USART_CALLBACK_MODE
+ * Never execute large portions of code in the callbacks. These
+ * are run from the interrupt routine, and thus having long callbacks will
+ * keep the processor in the interrupt handler for an equally long time.
+ * A common way to handle this is to use global flags signaling the
+ * main application that an interrupt event has happened, and only do the
+ * minimal needed processing in the callback.
+ * \else
+ * No special considerations.
+ * \endif
+ *
+ * \section asfdoc_sam0_sercom_usart_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_sercom_usart_extra. This includes:
+ * - \ref asfdoc_sam0_sercom_usart_extra_acronyms
+ * - \ref asfdoc_sam0_sercom_usart_extra_dependencies
+ * - \ref asfdoc_sam0_sercom_usart_extra_errata
+ * - \ref asfdoc_sam0_sercom_usart_extra_history
+ *
+ * \section asfdoc_sam0_sercom_usart_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_usart_exqsg.
+ *
+ * \section asfdoc_sam0_sercom_usart_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <sercom.h>
+#include <pinmux.h>
+
+#if USART_CALLBACK_MODE == true
+#  include <sercom_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define SERCOM USART features set according to different device family.
+ * @{
+ */
+
+#if (SAMD21) || (SAMR21) || (SAMD09) || (SAMD10) || (SAMD11) || \
+	(SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || \
+	(SAMR30) || (SAMHA1) || defined(__DOXYGEN__)
+/** USART sync scheme version 2. */
+#  define FEATURE_USART_SYNC_SCHEME_V2
+/** USART oversampling. */
+#  define FEATURE_USART_OVER_SAMPLE
+/** USART hardware control flow. */
+#  define FEATURE_USART_HARDWARE_FLOW_CONTROL
+/** IrDA mode. */
+#  define FEATURE_USART_IRDA
+/** LIN slave mode. */
+#  define FEATURE_USART_LIN_SLAVE
+/** USART collision detection. */
+#  define FEATURE_USART_COLLISION_DECTION
+/** USART start frame detection. */
+#  define FEATURE_USART_START_FRAME_DECTION
+/** USART start buffer overflow notification. */
+#  define FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+#endif
+
+#if (SAML22) || defined(__DOXYGEN__)
+/** ISO7816 for smart card interfacing. */
+#define FEATURE_USART_ISO7816
+#endif
+#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
+/** LIN master mode. */
+#define FEATURE_USART_LIN_MASTER
+#endif
+#if (SAML22) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
+/** RS485 mode. */
+#  define FEATURE_USART_RS485
+#endif
+/*@}*/
+
+#ifdef FEATURE_USART_LIN_MASTER
+/**
+ * \brief LIN node type
+ *
+ * LIN node type.
+ */
+enum lin_node_type {
+	/** LIN master mode */
+	LIN_MASTER_NODE = SERCOM_USART_CTRLA_FORM(0x02),
+	/** LIN slave mode */
+	LIN_SLAVE_NODE = SERCOM_USART_CTRLA_FORM(0x04),
+	/** Neither LIN master nor LIN slave mode */
+	LIN_INVALID_MODE = SERCOM_USART_CTRLA_FORM(0x00),
+};
+
+/**
+ * \brief LIN master command enum
+ *
+ * LIN master command enum.
+ */
+enum lin_master_cmd {
+	/** LIN master software control transmission command */
+	LIN_MASTER_SOFTWARE_CONTROL_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x01),
+	/** LIN master automatically transmission command */
+	LIN_MASTER_AUTO_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x02),
+};
+
+/**
+ * \brief LIN master header delay
+ *
+ * LIN master header delay between break and sync transmission,
+ * and between the sync and identifier (ID) fields.
+ * This field is only valid when using automatically transmission command
+ */
+enum lin_master_header_delay {
+	/** Delay between break and sync transmission is 1 bit time.
+		Delay between sync and ID transmission is 1 bit time. */
+	LIN_MASTER_HEADER_DELAY_0 = SERCOM_USART_CTRLC_HDRDLY(0x0),
+	/** Delay between break and sync transmission is 4 bit time.
+		Delay between sync and ID transmission is 4 bit time. */
+	LIN_MASTER_HEADER_DELAY_1 = SERCOM_USART_CTRLC_HDRDLY(0x01),
+	/** Delay between break and sync transmission is 8 bit time.
+		Delay between sync and ID transmission is 4 bit time. */
+	LIN_MASTER_HEADER_DELAY_2 = SERCOM_USART_CTRLC_HDRDLY(0x02),
+	/** Delay between break and sync transmission is 14 bit time.
+		Delay between sync and ID transmission is 4 bit time. */
+	LIN_MASTER_HEADER_DELAY_3 = SERCOM_USART_CTRLC_HDRDLY(0x03),
+};
+
+/**
+ * \brief LIN master break length
+ *
+ * Length of the break field transmitted when in LIN master mode
+ */
+enum lin_master_break_length {
+	/** Break field transmission is 13 bit times */
+	LIN_MASTER_BREAK_LENGTH_13_BIT = SERCOM_USART_CTRLC_BRKLEN(0x0),
+	/** Break field transmission is 17 bit times */
+	LIN_MASTER_BREAK_LENGTH_17_BIT = SERCOM_USART_CTRLC_BRKLEN(0x1),
+	/** Break field transmission is 21 bit times */
+	LIN_MASTER_BREAK_LENGTH_21_BIT = SERCOM_USART_CTRLC_BRKLEN(0x2),
+	/** Break field transmission is 26 bit times */
+	LIN_MASTER_BREAK_LENGTH_26_BIT = SERCOM_USART_CTRLC_BRKLEN(0x3),
+};
+#endif
+#ifdef FEATURE_USART_ISO7816
+/**
+ * \brief ISO7816 protocol type
+ *
+ * ISO7816 protocol type.
+ */
+enum iso7816_protocol_type {
+	/** ISO7816 protocol type 0 */
+	ISO7816_PROTOCOL_T_0 = SERCOM_USART_CTRLA_CMODE,
+	/** ISO7816 protocol type 1 */
+	ISO7816_PROTOCOL_T_1 = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
+};
+
+/**
+ * \brief ISO7816 guard time
+ *
+ * The value of ISO7816 guard time.
+ */
+enum iso7816_guard_time {
+	/** The guard time is 2-bit times */
+	ISO7816_GUARD_TIME_2_BIT = 2,
+	/** The guard time is 3-bit times */
+	ISO7816_GUARD_TIME_3_BIT,
+	/** The guard time is 4-bit times */
+	ISO7816_GUARD_TIME_4_BIT,
+	/** The guard time is 5-bit times */
+	ISO7816_GUARD_TIME_5_BIT,
+	/** The guard time is 6-bit times */
+	ISO7816_GUARD_TIME_6_BIT,
+	/** The guard time is 7-bit times */
+	ISO7816_GUARD_TIME_7_BIT,
+};
+
+/**
+ * \brief ISO7816 receive NACK inhibit
+ *
+ * The value of ISO7816 receive NACK inhibit.
+ */
+enum iso7816_inhibit_nack {
+	/** The NACK is generated */
+	ISO7816_INHIBIT_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
+	/** The NACK is not generated */
+	ISO7816_INHIBIT_NACK_ENABLE = SERCOM_USART_CTRLC_INACK,
+};
+
+/**
+ * \brief ISO7816 disable successive receive NACK
+ *
+ * The value of ISO7816 disable successive receive NACK.
+ */
+enum iso7816_successive_recv_nack {
+	/** The successive receive NACK is enable. */
+	ISO7816_SUCCESSIVE_RECV_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
+	/** The successive receive NACK is disable. */
+	ISO7816_SUCCESSIVE_RECV_NACK_ENABLE = SERCOM_USART_CTRLC_DSNACK,
+};
+
+/**
+ * \brief ISO7816 configuration struct
+ *
+ * ISO7816 configuration structure.
+ */
+struct iso7816_config_t {
+	/* ISO7816 mode enable */
+	bool enabled;
+	/** ISO7816 protocol type */
+	enum iso7816_protocol_type protocol_t;
+	/** Enable inverse transmission and reception */
+	bool enable_inverse;
+	/** Guard time, which lasts two bit times */
+	enum iso7816_guard_time guard_time;
+	/**
+	 * Inhibit Non Acknowledge:
+	 *   - 0: the NACK is generated;
+	 *   - 1: the NACK is not generated.
+	 */
+	enum iso7816_inhibit_nack inhibit_nack;
+	/**
+	 * Disable successive NACKs.
+	 *  - 0: NACK is sent on the ISO line as soon as a parity error occurs
+	 * in the received character. Successive parity errors are counted up to
+	 * the value in the max_iterations field. These parity errors generate
+	 * a NACK on the ISO line. As soon as this value is reached, no additional
+	 * NACK is sent on the ISO line. The ITERATION flag is asserted.
+	 */
+	enum iso7816_successive_recv_nack successive_recv_nack;
+	/* Max number of repetitions */
+	uint32_t max_iterations;
+};
+#endif
+
+#ifndef PINMUX_DEFAULT
+/** Default pinmux */
+#  define PINMUX_DEFAULT 0
+#endif
+
+#ifndef PINMUX_UNUSED
+/** Unused pinmux */
+#  define PINMUX_UNUSED 0xFFFFFFFF
+#endif
+
+#ifndef USART_TIMEOUT
+/** USART timeout value */
+#  define USART_TIMEOUT 0xFFFF
+#endif
+
+#if USART_CALLBACK_MODE == true
+/**
+ * \brief USART callback enum
+ *
+ * Callbacks for the Asynchronous USART driver.
+ */
+enum usart_callback {
+	/** Callback for buffer transmitted */
+	USART_CALLBACK_BUFFER_TRANSMITTED,
+	/** Callback for buffer received */
+	USART_CALLBACK_BUFFER_RECEIVED,
+	/** Callback for error */
+	USART_CALLBACK_ERROR,
+#ifdef FEATURE_USART_LIN_SLAVE
+	/** Callback for break character is received */
+	USART_CALLBACK_BREAK_RECEIVED,
+#endif
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	/** Callback for a change is detected on the CTS pin */
+	USART_CALLBACK_CTS_INPUT_CHANGE,
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/** Callback for a start condition is detected on the RxD line */
+	USART_CALLBACK_START_RECEIVED,
+#endif
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	USART_CALLBACK_N,
+#  endif
+};
+#endif
+
+/**
+ * \brief USART Data Order enum
+ *
+ * The data order decides which MSB or LSB is shifted out first when data is
+ * transferred.
+ */
+enum usart_dataorder {
+	/** The MSB will be shifted out first during transmission,
+	 *  and shifted in first during reception */
+	USART_DATAORDER_MSB = 0,
+	/** The LSB will be shifted out first during transmission,
+	 *  and shifted in first during reception */
+	USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD,
+};
+
+/**
+ * \brief USART Transfer mode enum
+ *
+ * Select USART transfer mode.
+ */
+enum usart_transfer_mode {
+	/** Transfer of data is done synchronously */
+	USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE),
+	/** Transfer of data is done asynchronously */
+	USART_TRANSFER_ASYNCHRONOUSLY = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
+};
+
+/**
+ * \brief USART Parity enum
+ *
+ * Select parity USART parity mode.
+ */
+enum usart_parity {
+	/** For odd parity checking, the parity bit will be set if number of
+	 *  ones being transferred is even */
+	USART_PARITY_ODD  = SERCOM_USART_CTRLB_PMODE,
+
+	/** For even parity checking, the parity bit will be set if number of
+	 *  ones being received is odd */
+	USART_PARITY_EVEN = 0,
+
+	/** No parity checking will be executed, and there will be no parity bit
+	 *  in the received frame */
+	USART_PARITY_NONE = 0xFF,
+};
+
+/**
+ * \brief USART signal MUX settings
+ *
+ * Set the functionality of the SERCOM pins.
+ *
+ * See \ref asfdoc_sam0_sercom_usart_mux_settings for a description of the
+ * various MUX setting options.
+ */
+enum usart_signal_mux_settings {
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	/** MUX setting RX_0_TX_0_XCK_1 */
+	USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)),
+	/** MUX setting RX_0_TX_2_XCK_3 */
+	USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)),
+	/** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3 */
+	USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)),
+	/** MUX setting RX_1_TX_0_XCK_1 */
+	USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)),
+	/** MUX setting RX_1_TX_2_XCK_3 */
+	USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)),
+	/** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3 */
+	USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)),
+	/** MUX setting RX_2_TX_0_XCK_1 */
+	USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)),
+	/** MUX setting RX_2_TX_2_XCK_3 */
+	USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)),
+	/** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3 */
+	USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)),
+	/** MUX setting RX_3_TX_0_XCK_1 */
+	USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)),
+	/** MUX setting RX_3_TX_2_XCK_3 */
+	USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)),
+	/** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3 */
+	USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)),
+#ifdef FEATURE_USART_RS485
+	/** MUX setting USART_RX_0_TX_0_XCK_1_TE_2 */
+	USART_RX_0_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(3)),
+	/** MUX setting USART_RX_1_TX_0_XCK_1_TE_2 */
+	USART_RX_1_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(3)),
+	/** MUX setting USART_RX_2_TX_0_XCK_1_TE_2 */
+	USART_RX_2_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(3)),
+	/** MUX setting USART_RX_3_TX_0_XCK_1_TE_2 */
+	USART_RX_3_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(3)),
+#endif
+#else
+	/** MUX setting RX_0_TX_0_XCK_1 */
+	USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)),
+	/** MUX setting RX_0_TX_2_XCK_3 */
+	USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO),
+	/** MUX setting RX_1_TX_0_XCK_1 */
+	USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)),
+	/** MUX setting RX_1_TX_2_XCK_3 */
+	USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO),
+	/** MUX setting RX_2_TX_0_XCK_1 */
+	USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)),
+	/** MUX setting RX_2_TX_2_XCK_3 */
+	USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO),
+	/** MUX setting RX_3_TX_0_XCK_1 */
+	USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)),
+	/** MUX setting RX_3_TX_2_XCK_3 */
+	USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO),
+#endif
+};
+
+/**
+ * \brief USART Stop Bits enum
+ *
+ * Number of stop bits for a frame.
+ */
+enum usart_stopbits {
+	/** Each transferred frame contains one stop bit */
+	USART_STOPBITS_1 = 0,
+	/** Each transferred frame contains two stop bits */
+	USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE,
+};
+
+/**
+ * \brief USART Character Size
+ *
+ * Number of bits for the character sent in a frame.
+ */
+enum usart_character_size {
+	/** The char being sent in a frame is five bits long */
+	USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5),
+	/** The char being sent in a frame is six bits long */
+	USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6),
+	/** The char being sent in a frame is seven bits long */
+	USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7),
+	/** The char being sent in a frame is eight bits long */
+	USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0),
+	/** The char being sent in a frame is nine bits long */
+	USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1),
+};
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+/**
+ * \brief USART Sample Rate
+ *
+ * The value of sample rate and baudrate generation mode.
+ */
+enum usart_sample_rate {
+	/** 16x over-sampling using arithmetic baudrate generation */
+	USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0),
+	/** 16x over-sampling using fractional baudrate generation */
+	USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1),
+	/** 8x over-sampling using arithmetic baudrate generation */
+	USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2),
+	/** 8x over-sampling using fractional baudrate generation */
+	USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3),
+	/** 3x over-sampling using arithmetic baudrate generation */
+	USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4),
+};
+
+/**
+ * \brief USART Sample Adjustment
+ *
+ * The value of sample number used for majority voting.
+ */
+enum usart_sample_adjustment {
+	/** The first, middle and last sample number used for majority voting is 7-8-9 */
+	USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0),
+	/** The first, middle and last sample number used for majority voting is 9-10-11 */
+	USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1),
+	/** The first, middle and last sample number used for majority voting is 11-12-13 */
+	USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2),
+	/** The first, middle and last sample number used for majority voting is 13-14-15 */
+	USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3),
+};
+#endif
+
+#ifdef FEATURE_USART_RS485
+/**
+ * \brief RS485 Guard Time
+ *
+ * The value of RS485 guard time.
+ */
+enum rs485_guard_time {
+	/** The guard time is 0-bit time */
+	RS485_GUARD_TIME_0_BIT = 0,
+	/** The guard time is 1-bit time */
+	RS485_GUARD_TIME_1_BIT,
+	/** The guard time is 2-bit times */
+	RS485_GUARD_TIME_2_BIT,
+	/** The guard time is 3-bit times */
+	RS485_GUARD_TIME_3_BIT,
+	/** The guard time is 4-bit times */
+	RS485_GUARD_TIME_4_BIT,
+	/** The guard time is 5-bit times */
+	RS485_GUARD_TIME_5_BIT,
+	/** The guard time is 6-bit times */
+	RS485_GUARD_TIME_6_BIT,
+	/** The guard time is 7-bit times */
+	RS485_GUARD_TIME_7_BIT,
+};
+#endif
+
+/**
+ * \brief USART Transceiver
+ *
+ * Select Receiver or Transmitter.
+ */
+enum usart_transceiver_type {
+	/** The parameter is for the Receiver */
+	USART_TRANSCEIVER_RX,
+	/** The parameter is for the Transmitter */
+	USART_TRANSCEIVER_TX,
+};
+
+/**
+ * \brief USART configuration struct
+ *
+ * Configuration options for USART.
+ */
+struct usart_config {
+	/** USART bit order (MSB or LSB first) */
+	enum usart_dataorder data_order;
+	/** USART in asynchronous or synchronous mode */
+	enum usart_transfer_mode transfer_mode;
+	/** USART parity */
+	enum usart_parity parity;
+	/** Number of stop bits */
+	enum usart_stopbits stopbits;
+	/** USART character size */
+	enum usart_character_size character_size;
+	/** USART pin out */
+	enum usart_signal_mux_settings mux_setting;
+#ifdef FEATURE_USART_OVER_SAMPLE
+	/** USART sample rate */
+	enum usart_sample_rate sample_rate;
+	/** USART sample adjustment */
+	enum usart_sample_adjustment sample_adjustment;
+#endif
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+	/** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs */
+	bool immediate_buffer_overflow_notification;
+#endif
+#ifdef FEATURE_USART_IRDA
+	/** Enable IrDA encoding format */
+	bool encoding_format_enable;
+	/** The minimum pulse length required for a pulse to be accepted by the IrDA receiver */
+	uint8_t receive_pulse_length;
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+	/** Enable LIN Slave Support */
+	bool lin_slave_enable;
+#endif
+
+#ifdef FEATURE_USART_LIN_MASTER
+	/** LIN node type */
+	enum lin_node_type lin_node;
+	/** LIN master header delay */
+	enum lin_master_header_delay lin_header_delay;
+	/** LIN Master Break Length */
+	enum lin_master_break_length lin_break_length;
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/** Enable start of frame dection */
+	bool start_frame_detection_enable;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	/** Enable ISO7816 for smart card interfacing */
+	struct iso7816_config_t iso7816_config;
+#endif
+#ifdef FEATURE_USART_RS485
+	/** RS485 guard time */
+	enum rs485_guard_time rs485_guard_time;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+	/** Enable collision dection */
+	bool collision_detection_enable;
+#endif
+	/** USART baudrate */
+	uint32_t baudrate;
+	/** Enable receiver */
+	bool receiver_enable;
+	/** Enable transmitter */
+	bool transmitter_enable;
+
+	/** USART Clock Polarity.
+	 * If true, data changes on falling XCK edge and
+	 * is sampled at rising edge.
+	 * If false, data changes on rising XCK edge and
+	 * is sampled at falling edge.
+	 * */
+	bool clock_polarity_inverted;
+
+	/** States whether to use the external clock applied to the XCK pin.
+	 * In synchronous mode the shift register will act directly on the XCK clock.
+	 * In asynchronous mode the XCK will be the input to the USART hardware module.
+	 */
+	bool use_external_clock;
+	/** External clock frequency in synchronous mode.
+	 * This must be set if \c use_external_clock is true. */
+	uint32_t ext_clock_freq;
+	/** If true the USART will be kept running in Standby sleep mode */
+	bool run_in_standby;
+	/** GCLK generator source */
+	enum gclk_generator generator_source;
+	/** PAD0 pinmux.
+	 *
+	 * If current USARTx has several alternative multiplexing I/O pins for PAD0, then
+	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD0
+	 * function. Make sure that no other alternative multiplexing I/O is associated
+	 * with the same USARTx PAD0.
+	 */
+	uint32_t pinmux_pad0;
+	/** PAD1 pinmux.
+	 *
+	 * If current USARTx has several alternative multiplexing I/O pins for PAD1, then
+	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD1
+	 * function. Make sure that no other alternative multiplexing I/O is associated
+	 * with the same USARTx PAD1.
+	 */
+	uint32_t pinmux_pad1;
+	/** PAD2 pinmux.
+	 *
+	 * If current USARTx has several alternative multiplexing I/O pins for PAD2, then
+	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD2
+	 * function. Make sure that no other alternative multiplexing I/O is associated
+	 * with the same USARTx PAD2.
+	 */
+	uint32_t pinmux_pad2;
+	/** PAD3 pinmux.
+	 *
+	 * If current USARTx has several alternative multiplexing I/O pins for PAD3, then
+	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD3
+	 * function. Make sure that no other alternative multiplexing I/O is associated
+	 * with the same USARTx PAD3.
+	 */
+	uint32_t pinmux_pad3;
+};
+
+#if USART_CALLBACK_MODE == true
+/**
+ * \brief USART module instance
+ *
+ * Forward Declaration for the device instance.
+ */
+struct usart_module;
+
+/**
+ * \brief USART callback type
+ *
+ * Type of the callback functions.
+ */
+typedef void (*usart_callback_t)(struct usart_module *const module);
+#endif
+
+/**
+ * \brief SERCOM USART driver software device instance structure.
+ *
+ * SERCOM USART driver software instance structure, used to retain software
+ * state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct usart_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to the hardware instance */
+	Sercom *hw;
+	/** Module lock */
+	volatile bool locked;
+	/** Character size of the data being transferred */
+	enum usart_character_size character_size;
+	/** Receiver enabled */
+	bool receiver_enabled;
+	/** Transmitter enabled */
+	bool transmitter_enabled;
+#ifdef FEATURE_USART_LIN_SLAVE
+	/** LIN Slave Support enabled */
+	bool lin_slave_enabled;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/** Start of frame dection enabled */
+	bool start_frame_detection_enabled;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	/** ISO7816 mode enable */
+	bool iso7816_mode_enabled;
+#endif
+#  if USART_CALLBACK_MODE == true
+	/** Array to store callback function pointers in */
+	usart_callback_t callback[USART_CALLBACK_N];
+	/** Buffer pointer to where the next received character will be put */
+	volatile uint8_t *rx_buffer_ptr;
+
+	/** Buffer pointer to where the next character will be transmitted from
+	**/
+	volatile uint8_t *tx_buffer_ptr;
+	/** Remaining characters to receive */
+	volatile uint16_t remaining_rx_buffer_length;
+	/** Remaining characters to transmit */
+	volatile uint16_t remaining_tx_buffer_length;
+	/** Bit mask for callbacks registered */
+	uint8_t callback_reg_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t callback_enable_mask;
+	/** Holds the status of the ongoing or last read operation */
+	volatile enum status_code rx_status;
+	/** Holds the status of the ongoing or last write operation */
+	volatile enum status_code tx_status;
+#  endif
+#endif
+};
+
+ /**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code usart_lock(
+		struct usart_module *const module)
+{
+	enum status_code status;
+
+	system_interrupt_enter_critical_section();
+
+	if (module->locked) {
+		status = STATUS_BUSY;
+	} else {
+		module->locked = true;
+		status = STATUS_OK;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ */
+static inline void usart_unlock(struct usart_module *const module)
+{
+	module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \brief Check if peripheral is busy syncing registers across clock domains
+ *
+ * Return peripheral synchronization status. If doing a non-blocking
+ * implementation this function can be used to check the sync state and hold of
+ * any new actions until sync is complete. If this function is not run; the
+ * functions will block until the sync has completed.
+ *
+ * \param[in]  module  Pointer to peripheral module
+ *
+ * \return Peripheral sync status.
+ *
+ * \retval true   Peripheral is busy syncing
+ * \retval false  Peripheral is not busy syncing and can be read/written without
+ *                stalling the bus
+ */
+static inline bool usart_is_syncing(
+		const struct usart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+#ifdef FEATURE_USART_SYNC_SCHEME_V2
+	return (usart_hw->SYNCBUSY.reg);
+#else
+	return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY);
+#endif
+}
+
+#if !defined (__DOXYGEN__)
+/**
+ * \internal
+ * Waits until synchronization is complete
+ */
+static inline void _usart_wait_for_sync(
+		const struct usart_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+
+	while (usart_is_syncing(module)) {
+		/* Wait until the synchronization is complete */
+	}
+}
+#endif
+
+/**
+ * \brief Initializes the device to predefined defaults
+ *
+ * Initialize the USART device to predefined defaults:
+ * - 8-bit asynchronous USART
+ * - No parity
+ * - One stop bit
+ * - 9600 baud
+ * - Transmitter enabled
+ * - Receiver enabled
+ * - GCLK generator 0 as clock source
+ * - Default pin configuration
+ *
+ * The configuration struct will be updated with the default
+ * configuration.
+ *
+ * \param[in,out] config  Pointer to configuration struct
+ */
+static inline void usart_get_config_defaults(
+		struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Set default config in the config struct */
+	config->data_order       = USART_DATAORDER_LSB;
+	config->transfer_mode    = USART_TRANSFER_ASYNCHRONOUSLY;
+	config->parity           = USART_PARITY_NONE;
+	config->stopbits         = USART_STOPBITS_1;
+	config->character_size   = USART_CHARACTER_SIZE_8BIT;
+	config->baudrate         = 9600;
+	config->receiver_enable  = true;
+	config->transmitter_enable = true;
+	config->clock_polarity_inverted = false;
+	config->use_external_clock = false;
+	config->ext_clock_freq   = 0;
+	config->mux_setting      = USART_RX_1_TX_2_XCK_3;
+	config->run_in_standby   = false;
+	config->generator_source = GCLK_GENERATOR_0;
+	config->pinmux_pad0      = PINMUX_DEFAULT;
+	config->pinmux_pad1      = PINMUX_DEFAULT;
+	config->pinmux_pad2      = PINMUX_DEFAULT;
+	config->pinmux_pad3      = PINMUX_DEFAULT;
+#ifdef FEATURE_USART_OVER_SAMPLE
+	config->sample_adjustment     = USART_SAMPLE_ADJUSTMENT_7_8_9;
+	config->sample_rate           = USART_SAMPLE_RATE_16X_ARITHMETIC;
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+	config->lin_slave_enable      = false;
+#endif
+
+#ifdef FEATURE_USART_LIN_MASTER
+	config->lin_node = LIN_INVALID_MODE;
+	config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
+	config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
+#endif
+
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+	config->immediate_buffer_overflow_notification  = false;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	config->start_frame_detection_enable            = false;
+#endif
+#ifdef FEATURE_USART_IRDA
+	config->encoding_format_enable                  = false;
+	config->receive_pulse_length                    = 19;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	config->iso7816_config.enabled                  = false;
+	config->iso7816_config.guard_time               = ISO7816_GUARD_TIME_2_BIT;
+	config->iso7816_config.protocol_t               = ISO7816_PROTOCOL_T_0;
+	config->iso7816_config.enable_inverse           = false;
+	config->iso7816_config.inhibit_nack             = ISO7816_INHIBIT_NACK_DISABLE;
+	config->iso7816_config.successive_recv_nack     = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
+	config->iso7816_config.max_iterations           = 7;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+	config->collision_detection_enable              = false;
+#endif
+#ifdef FEATURE_USART_RS485
+	config->rs485_guard_time = RS485_GUARD_TIME_0_BIT;
+#endif
+}
+
+enum status_code usart_init(
+		struct usart_module *const module,
+		Sercom *const hw,
+		const struct usart_config *const config);
+
+/**
+ * \brief Enable the module
+ *
+ * Enables the USART module.
+ *
+ * \param[in]  module  Pointer to USART software instance struct
+ */
+static inline void usart_enable(
+		const struct usart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+#if USART_CALLBACK_MODE == true
+	/* Enable Global interrupt for module */
+	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Enable USART module */
+	usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disable module
+ *
+ * Disables the USART module.
+ *
+ * \param[in]  module  Pointer to USART software instance struct
+ */
+static inline void usart_disable(
+		const struct usart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+#if USART_CALLBACK_MODE == true
+	/* Disable Global interrupt for module */
+	system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Disable USART module */
+	usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Resets the USART module
+ *
+ * Disables and resets the USART module.
+ *
+ * \param[in]  module  Pointer to the USART software instance struct
+ */
+static inline void usart_reset(
+		const struct usart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	usart_disable(module);
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Reset module */
+	usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
+}
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code usart_write_wait(
+		struct usart_module *const module,
+		const uint16_t tx_data);
+
+enum status_code usart_read_wait(
+		struct usart_module *const module,
+		uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_wait(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code usart_read_buffer_wait(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+/** @} */
+
+/**
+ * \name Enabling/Disabling Receiver and Transmitter
+ * @{
+ */
+
+/**
+ * \brief Enable Transceiver
+ *
+ * Enable the given transceiver. Either RX or TX.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transceiver type
+ */
+static inline void usart_enable_transceiver(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	switch (transceiver_type) {
+		case USART_TRANSCEIVER_RX:
+			/* Enable RX */
+			usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+			module->receiver_enabled = true;
+			break;
+
+		case USART_TRANSCEIVER_TX:
+			/* Enable TX */
+			usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+			module->transmitter_enabled = true;
+			break;
+	}
+	_usart_wait_for_sync(module);
+}
+
+/**
+ * \brief Disable Transceiver
+ *
+ * Disable the given transceiver (RX or TX).
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transceiver type
+ */
+static inline void usart_disable_transceiver(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	switch (transceiver_type) {
+		case USART_TRANSCEIVER_RX:
+			/* Disable RX */
+			usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+			module->receiver_enabled = false;
+			break;
+
+		case USART_TRANSCEIVER_TX:
+			/* Disable TX */
+			usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+			module->transmitter_enabled = false;
+			break;
+	}
+}
+
+/** @} */
+
+#ifdef FEATURE_USART_LIN_MASTER
+/**
+ * \name LIN Master Command and Status
+ * @{
+ */
+
+/**
+ * \brief Sending LIN command.
+ *
+ * Sending LIN command.
+ *
+ * \param[in]  module Pointer to USART software instance struct
+ * \param[in]  cmd  Cammand type
+ */
+static inline void lin_master_send_cmd(
+		struct usart_module *const module,
+		enum lin_master_cmd cmd)
+{
+	SercomUsart *const usart_hw = &(module->hw->USART);
+	_usart_wait_for_sync(module);
+	usart_hw->CTRLB.reg |= cmd;
+}
+
+/**
+ * \brief Get LIN transmission status
+ *
+ * Get LIN transmission status.
+ *
+ * \param[in]  module Pointer to USART software instance struct
+ *
+ * \return Status of LIN master transmission.
+ * \retval true   Data transmission completed
+ * \retval false  Transmission is ongoing
+ */
+static inline bool lin_master_transmission_status(struct usart_module *const module)
+{
+	SercomUsart *const usart_hw = &(module->hw->USART);
+	return ((usart_hw->STATUS.reg & SERCOM_USART_STATUS_TXE)? true:false);
+}
+
+/** @} */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+* \page asfdoc_sam0_sercom_usart_extra Extra Information for SERCOM USART Driver
+*
+* \section asfdoc_sam0_sercom_usart_extra_acronyms Acronyms
+*
+* Below is a table listing the acronyms used in this module, along with their
+* intended meanings.
+*
+* <table>
+* <tr>
+* <th>Acronym</th>
+* <th>Description</th>
+* </tr>
+* <tr>
+* <td>SERCOM</td>
+* <td>Serial Communication Interface</td>
+* </tr>
+* <tr>
+* <td>USART</td>
+* <td>Universal Synchronous and Asynchronous Serial Receiver and Transmitter</td>
+* </tr>
+* <tr>
+* <td>LSB</td>
+* <td>Least Significant Bit</td>
+* </tr>
+* <tr>
+* <td>MSB</td>
+* <td>Most Significant Bit</td>
+* </tr>
+* <tr>
+* <td>DMA</td>
+* <td>Direct Memory Access</td>
+* </tr>
+* </table>
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_dependencies Dependencies
+* This driver has the following dependencies:
+*
+* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+* - \ref asfdoc_sam0_system_clock_group "System clock configuration"
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_errata Errata
+* There are no errata related to this driver.
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_history Module History
+* An overview of the module history is presented in the table below, with
+* details on the enhancements and fixes made to the module since its first
+* release. The current version of this corresponds to the newest version in
+* the table.
+*
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added new feature as below:
+ *          \li ISO7816
+ *	</tr>
+ *	<tr>
+ *		<td>Added new features as below:
+ *          \li LIN master
+ *          \li RS485
+ *	</tr>
+ *	<tr>
+ *		<td>Added new features as below:
+ *          \li Oversample
+ *          \li Buffer overflow notification
+ *          \li Irda
+ *          \li Lin slave
+ *          \li Start frame detection
+ *          \li Hardware flow control
+ *          \li Collision detection
+ *          \li DMA support </td>
+ *	</tr>
+ *	<tr>
+ *		<td>\li Added new \c transmitter_enable and \c receiver_enable Boolean
+ *              values to \c struct usart_config
+ *          \li Altered \c usart_write_* and usart_read_* functions to abort with
+ *              an error code if the relevant transceiver is not enabled
+ *          \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait()
+ *              not aborting correctly when a timeout condition occurs</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+*/
+
+/**
+ * \page asfdoc_sam0_sercom_usart_exqsg Examples for SERCOM USART Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_usart_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_sercom_usart_basic_use_case
+ * \if USART_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_usart_callback_use_case
+ * \endif
+ * - \subpage asfdoc_sam0_sercom_usart_dma_use_case
+ * - \subpage asfdoc_sam0_sercom_usart_lin_use_case
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_mux_settings SERCOM USART MUX Settings
+ *
+ * The following lists the possible internal SERCOM module pad function
+ * assignments, for the four SERCOM pads when in USART mode. Note that this is
+ * in addition to the physical GPIO pin MUX of the device, and can be used in
+ * conjunction to optimize the serial data pin-out.
+ *
+ * When TX and RX are connected to the same pin, the USART will operate in
+ * half-duplex mode if both one transmitter and several receivers are enabled.
+ *
+ * \note When RX and XCK are connected to the same pin, the receiver must not
+ *       be enabled if the USART is configured to use an external clock.
+ *
+ *
+ * <table>
+ *		<tr>
+ *			<th>MUX/Pad</th>
+ *			<th>PAD 0</th>
+ *			<th>PAD 1</th>
+ *			<th>PAD 2</th>
+ *			<th>PAD 3</th>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_0_TX_0_XCK_1</td>
+ *			<td>TX / RX</td>
+ *			<td>XCK</td>
+ *			<td>-</td>
+ *			<td>-</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_0_TX_2_XCK_3</td>
+ *			<td>RX</td>
+ *			<td>-</td>
+ *			<td>TX</td>
+ *			<td>XCK</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_1_TX_0_XCK_1</td>
+ *			<td>TX</td>
+ *			<td>RX / XCK</td>
+ *			<td>-</td>
+ *			<td>-</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_1_TX_2_XCK_3</td>
+ *			<td>-</td>
+ *			<td>RX</td>
+ *			<td>TX</td>
+ *			<td>XCK</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_2_TX_0_XCK_1</td>
+ *			<td>TX</td>
+ *			<td>XCK</td>
+ *			<td>RX</td>
+ *			<td>-</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_2_TX_2_XCK_3</td>
+ *			<td>-</td>
+ *			<td>-</td>
+ *			<td>TX / RX</td>
+ *			<td>XCK</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_3_TX_0_XCK_1</td>
+ *			<td>TX</td>
+ *			<td>XCK</td>
+ *			<td>-</td>
+ *			<td>RX</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_3_TX_2_XCK_3</td>
+ *			<td>-</td>
+ *			<td>-</td>
+ *			<td>TX</td>
+ *			<td>RX / XCK</td>
+ *		</tr>
+ * </table>
+ *
+ * \page asfdoc_sam0_sercom_usart_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118F</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118E</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118D</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118C</td>
+ *		<td>10/2013</td>
+ *		<td>Replaced the pad multiplexing documentation with a condensed table</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+#endif /* USART_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.c
new file mode 100644
index 0000000000..cc042894c8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.c
@@ -0,0 +1,666 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "usart_interrupt.h"
+
+/**
+ * \internal
+ * Asynchronous write of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+enum status_code _usart_write_buffer(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(tx_data);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if the USART transmitter is busy */
+	if (module->remaining_tx_buffer_length > 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+
+	system_interrupt_leave_critical_section();
+
+	module->tx_buffer_ptr              = tx_data;
+	module->tx_status                  = STATUS_BUSY;
+
+	/* Enable the Data Register Empty Interrupt */
+	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Asynchronous read of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  length   Length of data buffer
+ *
+ */
+enum status_code _usart_read_buffer(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(rx_data);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if the USART receiver is busy */
+	if (module->remaining_rx_buffer_length > 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Set length for the buffer and the pointer, and let
+	 * the interrupt handler do the rest */
+	module->remaining_rx_buffer_length = length;
+
+	system_interrupt_leave_critical_section();
+
+	module->rx_buffer_ptr              = rx_data;
+	module->rx_status                  = STATUS_BUSY;
+
+	/* Enable the RX Complete Interrupt */
+	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	/* Enable the break character is received Interrupt */
+	if(module->lin_slave_enabled) {
+		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/* Enable a start condition is detected Interrupt */
+	if(module->start_frame_detection_enabled) {
+		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
+	}
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function, which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usart_enable_callback
+ *       in order for the interrupt handler to call it when the conditions for
+ *       the callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void usart_register_callback(
+		struct usart_module *const module,
+		usart_callback_t callback_func,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->callback_reg_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function, which is implemented by the user.
+ *
+ * \param[in,out]  module         Pointer to USART software instance struct
+ * \param[in]      callback_type  Callback type given by an enum
+ *
+ */
+void usart_unregister_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->callback_reg_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Asynchronous write a single char
+ *
+ * Sets up the driver to write the data given. If registered and enabled,
+ * a callback function will be called when the transmit is completed.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Data to transfer
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK         If operation was completed
+ * \retval STATUS_BUSY       If operation was not completed, due to the
+ *                           USART module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_job(
+		struct usart_module *const module,
+		const uint16_t *tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(tx_data);
+
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Call internal write buffer function with length 1 */
+	return _usart_write_buffer(module, (uint8_t *)tx_data, 1);
+}
+
+/**
+ * \brief Asynchronous read a single char
+ *
+ * Sets up the driver to read data from the USART module to the data
+ * pointer given. If registered and enabled, a callback will be called
+ * when the receiving is completed.
+ *
+ * \param[in]   module   Pointer to USART software instance struct
+ * \param[out]  rx_data  Pointer to where received data should be put
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK    If operation was completed
+ * \retval  STATUS_BUSY  If operation was not completed
+ */
+enum status_code usart_read_job(
+		struct usart_module *const module,
+		uint16_t *const rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	/* Call internal read buffer function with length 1 */
+	return _usart_read_buffer(module, (uint8_t *)rx_data, 1);
+}
+
+/**
+ * \brief Asynchronous buffer write
+ *
+ * Sets up the driver to write a given buffer over the USART. If registered and
+ * enabled, a callback function will be called.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer do data buffer to transmit
+ * \param[in]  length   Length of the data to transmit
+ *
+ * \note If using 9-bit data, the array that *tx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define TX_LEN 3
+          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+          usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN);
+    \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK              If operation was completed successfully.
+ * \retval STATUS_BUSY            If operation was not completed, due to the
+ *                                USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_job(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(tx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Issue internal asynchronous write */
+	return _usart_write_buffer(module, tx_data, length);
+}
+
+/**
+ * \brief Asynchronous buffer read
+ *
+ * Sets up the driver to read from the USART to a given buffer. If registered
+ * and enabled, a callback function will be called.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \note If using 9-bit data, the array that *rx_data point to should be defined
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+           #define RX_LEN 3
+           uint16_t rx_buf[RX_LEN] = {0x0,};
+           usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN);
+    \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK              If operation was completed
+ * \retval STATUS_BUSY            If operation was not completed, due to the
+ *                                USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_read_buffer_job(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Issue internal asynchronous read */
+	return _usart_read_buffer(module, rx_data, length);
+}
+
+/**
+ * \brief Cancels ongoing read/write operation
+ *
+ * Cancels the ongoing read/write operation modifying parameters in the
+ * USART software struct.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transfer type to cancel
+ */
+void usart_abort_job(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	switch(transceiver_type) {
+		case USART_TRANSCEIVER_RX:
+			/* Clear the interrupt flag in order to prevent the receive
+			 * complete callback to fire */
+			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+
+			/* Clear the software reception buffer */
+			module->remaining_rx_buffer_length = 0;
+
+			break;
+
+		case USART_TRANSCEIVER_TX:
+			/* Clear the interrupt flag in order to prevent the receive
+			 * complete callback to fire */
+			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+
+			/* Clear the software reception buffer */
+			module->remaining_tx_buffer_length = 0;
+
+			break;
+	}
+}
+
+/**
+ * \brief Get status from the ongoing or last asynchronous transfer operation
+ *
+ * Returns the error from a given ongoing or last asynchronous transfer operation.
+ * Either from a read or write transfer.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transfer type to check
+  *
+ * \return Status of the given job.
+ * \retval STATUS_OK               No error occurred during the last transfer
+ * \retval STATUS_BUSY             A transfer is ongoing
+ * \retval STATUS_ERR_BAD_DATA     The last operation was aborted due to a
+ *                                 parity error. The transfer could be affected
+ *                                 by external noise
+ * \retval STATUS_ERR_BAD_FORMAT   The last operation was aborted due to a
+ *                                 frame error
+ * \retval STATUS_ERR_OVERFLOW     The last operation was aborted due to a
+ *                                 buffer overflow
+ * \retval STATUS_ERR_INVALID_ARG  An invalid transceiver enum given
+ */
+enum status_code usart_get_job_status(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Variable for status code */
+	enum status_code status_code;
+
+	switch(transceiver_type) {
+	case USART_TRANSCEIVER_RX:
+			status_code = module->rx_status;
+			break;
+
+	case USART_TRANSCEIVER_TX:
+			status_code = module->tx_status;
+			break;
+
+	default:
+			status_code = STATUS_ERR_INVALID_ARG;
+			break;
+	}
+
+	return status_code;
+}
+
+/**
+ * \internal
+ * Handles interrupts as they occur, and it will run callback functions
+ * which are registered and enabled.
+ *
+ * \param[in]  instance  ID of the SERCOM instance calling the interrupt
+ *                       handler.
+ */
+void _usart_interrupt_handler(
+		uint8_t instance)
+{
+	/* Temporary variables */
+	uint16_t interrupt_status;
+	uint16_t callback_status;
+	uint8_t error_code;
+
+
+	/* Get device instance from the look-up table */
+	struct usart_module *module
+		= (struct usart_module *)_sercom_instances[instance];
+
+	/* Pointer to the hardware module instance */
+	SercomUsart *const usart_hw
+		= &(module->hw->USART);
+
+	/* Wait for the synchronization to complete */
+	_usart_wait_for_sync(module);
+
+	/* Read and mask interrupt flag register */
+	interrupt_status = usart_hw->INTFLAG.reg;
+	interrupt_status &= usart_hw->INTENSET.reg;
+	callback_status = module->callback_reg_mask &
+			module->callback_enable_mask;
+
+	/* Check if a DATA READY interrupt has occurred,
+	 * and if there is more to transfer */
+	if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
+		if (module->remaining_tx_buffer_length) {
+			/* Write value will be at least 8-bits long */
+			uint16_t data_to_send = *(module->tx_buffer_ptr);
+			/* Increment 8-bit pointer */
+			(module->tx_buffer_ptr)++;
+
+			if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+				data_to_send |= (*(module->tx_buffer_ptr) << 8);
+				/* Increment 8-bit pointer */
+				(module->tx_buffer_ptr)++;
+			}
+			/* Write the data to send */
+			usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
+
+			if (--(module->remaining_tx_buffer_length) == 0) {
+				/* Disable the Data Register Empty Interrupt */
+				usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+				/* Enable Transmission Complete interrupt */
+				usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+
+			}
+		} else {
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+		}
+	}
+
+	/* Check if the Transmission Complete interrupt has occurred and
+	 * that the transmit buffer is empty */
+	if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
+
+		/* Disable TX Complete Interrupt, and set STATUS_OK */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+		module->tx_status = STATUS_OK;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
+			(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
+		}
+	}
+
+	/* Check if the Receive Complete interrupt has occurred, and that
+	 * there's more data to receive */
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+
+		if (module->remaining_rx_buffer_length) {
+			/* Read out the status code and mask away all but the 4 LSBs*/
+			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+#if !SAMD20
+			/* CTS status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_CTS) {
+				error_code &= ~SERCOM_USART_STATUS_CTS;
+			}
+#endif
+#ifdef FEATURE_USART_LIN_MASTER
+			/* TXE status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_TXE) {
+				error_code &= ~SERCOM_USART_STATUS_TXE;
+			}
+#endif
+			/* Check if an error has occurred during the receiving */
+			if (error_code) {
+				/* Check which error occurred */
+				if (error_code & SERCOM_USART_STATUS_FERR) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_FORMAT;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+				} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_OVERFLOW;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+				} else if (error_code & SERCOM_USART_STATUS_PERR) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_DATA;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+				}
+#ifdef FEATURE_USART_LIN_SLAVE
+				else if (error_code & SERCOM_USART_STATUS_ISF) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_PROTOCOL;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+				}
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+				else if (error_code & SERCOM_USART_STATUS_COLL) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_PACKET_COLLISION;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+				}
+#endif
+
+				/* Run callback if registered and enabled */
+				if (callback_status
+						& (1 << USART_CALLBACK_ERROR)) {
+					(*(module->callback[USART_CALLBACK_ERROR]))(module);
+				}
+
+			} else {
+
+				/* Read current packet from DATA register,
+				 * increment buffer pointer and decrement buffer length */
+				uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
+
+				/* Read value will be at least 8-bits long */
+				*(module->rx_buffer_ptr) = received_data;
+				/* Increment 8-bit pointer */
+				module->rx_buffer_ptr += 1;
+
+				if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+					/* 9-bit data, write next received byte to the buffer */
+					*(module->rx_buffer_ptr) = (received_data >> 8);
+					/* Increment 8-bit pointer */
+					module->rx_buffer_ptr += 1;
+				}
+
+				/* Check if the last character have been received */
+				if(--(module->remaining_rx_buffer_length) == 0) {
+					/* Disable RX Complete Interrupt,
+					 * and set STATUS_OK */
+					usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+					module->rx_status = STATUS_OK;
+
+					/* Run callback if registered and enabled */
+					if (callback_status
+							& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
+						(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
+					}
+				}
+			}
+		} else {
+			/* This should not happen. Disable Receive Complete interrupt. */
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+		}
+	}
+
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
+			(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
+			(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
+			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
+		}
+	}
+#endif
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.h
new file mode 100644
index 0000000000..26595d0a09
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.h
@@ -0,0 +1,177 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef USART_INTERRUPT_H_INCLUDED
+#define USART_INTERRUPT_H_INCLUDED
+
+#include "usart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+enum status_code _usart_write_buffer(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code _usart_read_buffer(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void _usart_interrupt_handler(
+		uint8_t instance);
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_usart_group
+ *
+ * @{
+ */
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void usart_register_callback(
+		struct usart_module *const module,
+		usart_callback_t callback_func,
+		enum usart_callback callback_type);
+
+void usart_unregister_callback(
+		struct usart_module *module,
+		enum usart_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref usart_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+static inline void usart_enable_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->callback_enable_mask |= (1 << callback_type);
+
+}
+
+/**
+ * \brief Disable callback
+ *
+ * Disables the callback function registered by the \ref usart_register_callback,
+ * and the callback will not be called from the interrupt routine.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+static inline void usart_disable_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->callback_enable_mask &= ~(1 << callback_type);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code usart_write_job(
+		struct usart_module *const module,
+		const uint16_t *tx_data);
+
+enum status_code usart_read_job(
+		struct usart_module *const module,
+		uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_job(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code usart_read_buffer_job(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void usart_abort_job(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type);
+
+enum status_code usart_get_job_status(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USART_INTERRUPT_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/module_config/conf_slcd.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/module_config/conf_slcd.h
new file mode 100644
index 0000000000..fde8309f8e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/module_config/conf_slcd.h
@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief SAM SLCD Driver Configuration Header
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_SLCD_H_INCLUDED
+#define CONF_SLCD_H_INCLUDED
+
+/** Select SLCD clock. Use 32.768KHz OSCULP32K or XOSC32K for SLCD clock.
+ *  0 : From OSCULP32K
+ *  1 : From XOSC32K
+ */
+#define CONF_SLCD_CLOCK_SOURCE    0
+
+/** SLCD Duty Setting
+ *  0:Static duty
+ *  1:1/2 duty
+ *  2:1/3 duty
+ *  3:1/4 duty
+ *  4:1/6 duty
+ *  5:1/8 duty
+*/
+#define CONF_SLCD_DUTY         5
+
+/**
+ * SLCD Bias Setting.
+ *  0:Static bias
+ *  1:1/2 bias
+ *  2:1/3 bias
+ *  3:1/4 bias
+ */
+#define CONF_SLCD_BIAS         3
+
+/**
+ * SLCD Frame Frequency.
+ * The optimal frame frequency should be in range from 30Hz up to 100Hz
+ * to avoid flickering and ghosting effect.
+ * To get the frame frequency, CLK_SLCD_OSC is first divided by a prescaler
+ * from 16 to 128 then divided by 1 up to 8 as following.
+ *
+ * FrameRate = CLK_SLCD_OSC / (PVAL*(CKDIV+1)*(DUTY+1))
+ *
+ * SLCD Prescaler Value (PVAL).
+ * 0 : 16 prescaler
+ * 1 : 32 prescaler
+ * 2 : 64 prescaler
+ * 3 : 128 prescaler
+ *
+ * SLCD Clock divider (CKDIV)
+ * 0 : CKDIV is 0,divided by 1
+ * 1 : CKDIV is 1,divided by 2
+ * 2 : CKDIV is 2,divided by 3
+ * 3 : CKDIV is 3,divided by 4
+ * 4 : CKDIV is 4,divided by 5
+ * 5 : CKDIV is 5,divided by 6
+ * 6 : CKDIV is 6,divided by 7
+ * 7 : CKDIV is 7,divided by 8
+ */
+/**
+* With 1/8 DUTY and the following configuration(16 prescaler and CKDIV value is 7),
+* FrameRate = 32768/(16*(7+1)*8) = 32Hz
+*/
+#define CONF_SLCD_PVAL         0
+#define CONF_SLCD_CKDIV        7
+
+/** Internal/External VLCD selection.
+* 0 : Internal VLCD generation
+* 1 : External VLCD generation
+*/
+#define CONF_SLCD_VLCD_SEL        0
+
+/** Reference fefresh frequency.
+*  0: Bias Reference refresh frequency is 2KHz
+*  1: Bias Reference refresh frequency is 1KHz
+*  2: Bias Reference refresh frequency is 500Hz
+*  3: Bias Reference refresh frequency is 250Hz
+*  4: Bias Reference refresh frequency is 125Hz
+*  5: Bias Reference refresh frequency is 62.5Hz
+*/
+#define CONF_SLCD_REF_REFRESH_FREQ        0
+
+/** Power fefresh frequency.
+*  0: Charge pump refresh frequency is 2KHz
+*  1: Charge pump refresh frequency is 1KHz
+*  2: Charge pump refresh frequency is 500Hz
+*  3: Charge pump refresh frequency is 250Hz
+ */
+#define CONF_SLCD_POWER_REFRESH_FREQ       0
+
+/** LCD Working Power Mode.
+ * 0:LCD power automatically select regualation mode or pump mode.
+ * 1:LCD power use step-up pump loop only.
+ * 2:LCD power use step-down drop-out regulation loop only.
+ */
+#define CONF_SLCD_POWER_MODE       0
+
+/** COM/SEG PIN Selection.
+ * There are 52 LCD pins, but SLCD can drive up to 48 LCD pins which can be
+ * individually enabled or disabled according to the LCD glass. The number of LCD pins
+ * enabled should not be higher than the maximum of COM and SEG lines supported.
+ * COM and SEG lines are always assigned in ascending order.
+ * CONF_SLCD_PIN_L_MASK is pin mask [31,0]
+ * CONF_SLCD_PIN_H_MASK is pin mask [51,32]
+ */
+#define CONF_SLCD_PIN_L_MASK       0xffffffff
+#define CONF_SLCD_PIN_H_MASK       0xfffff
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.c
new file mode 100644
index 0000000000..01b0a4bb2b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.c
@@ -0,0 +1,698 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Segment Liquid Crystal Display(SLCD) Controller.
+ *
+ * This file defines a useful set of functions for the SLCD on SAM devices.
+ *
+ * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <slcd.h>
+#include <conf_slcd.h>
+
+#include <system.h>
+
+#if !defined(CONF_SLCD_CLOCK_SOURCE)
+#  warning  SLCD_CLOCK_SOURCE is not defined, assuming 0.
+#  define CONF_SLCD_CLOCK_SOURCE 0
+#endif
+
+#if !defined(CONF_SLCD_DUTY)
+#  warning  CONF_SLCD_DUTY is not defined, assuming 0.
+#  define CONF_SLCD_DUTY 0
+#endif
+
+#if !defined(CONF_SLCD_BIAS)
+#  warning  CONF_SLCD_BIAS is not defined, assuming 0.
+#  define CONF_SLCD_BIAS 0
+#endif
+
+#if !defined(CONF_SLCD_PVAL)
+#  warning  CONF_SLCD_PVAL is not defined, assuming 0.
+#  define CONF_SLCD_PVAL 0
+#endif
+
+#if !defined(CONF_SLCD_CKDIV)
+#  warning  CONF_SLCD_CKDIV is not defined, assuming 0.
+#  define CONF_SLCD_CKDIV 0
+#endif
+
+#if !defined(CONF_SLCD_VLCD_SEL)
+#  warning  CONF_SLCD_VLCD_SEL is not defined, assuming 0.
+#  define CONF_SLCD_VLCD_SEL 0
+#endif
+
+#if !defined(CONF_SLCD_REF_REFRESH_FREQ)
+#  warning  CONF_SLCD_REF_REFRESH_FREQ is not defined, assuming 0.
+#  define CONF_SLCD_REF_REFRESH_FREQ 0
+#endif
+
+#if !defined(CONF_SLCD_POWER_REFRESH_FREQ)
+#  warning  CONF_SLCD_POWER_REFRESH_FREQ is not defined, assuming 0.
+#  define CONF_SLCD_POWER_REFRESH_FREQ 0
+#endif
+
+#if !defined(CONF_SLCD_POWER_MODE)
+#  warning  CONF_SLCD_POWER_MODE is not defined, assuming 0.
+#  define CONF_SLCD_POWER_MODE 0
+#endif
+
+#if !defined(CONF_SLCD_PIN_L_MASK)
+#  warning  CONF_SLCD_PIN_L_MASK is not defined, assuming 0.
+#  define CONF_SLCD_PIN_L_MASK 0
+#endif
+
+#if !defined(CONF_SLCD_PIN_H_MASK)
+#  warning  CONF_SLCD_PIN_H_MASK is not defined, assuming 0.
+#  define CONF_SLCD_PIN_H_MASK 0
+#endif
+
+/**
+ * \brief Initializes SLCD configurations struct to defaults
+ *
+ * Initailizes SLCD configuration struct to predefined safe default settings.
+ *
+ * \param[in] config Pointer to an instance of \ref struct slcd_config
+ *
+ */
+void slcd_get_config_defaults(struct slcd_config *config)
+{
+	Assert(config);
+
+	config->run_in_standby = false;
+	config->waveform_mode = SLCD_LOW_POWER_WAVEFORM_MODE;
+	config->low_resistance_duration = 0;
+	config->enable_low_resistance = false;
+	config->bias_buffer_duration = 0;
+	config->enable_bias_buffer = false;
+}
+
+/**
+ * \brief Initialize SLCD module
+ *
+ * \param[in] config  Pointer to an SLCD configuration structure
+ *
+ *  \note SLCD cannot be Initialized while it is enabled.
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK SLCD configuration went successful
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid configuration was supplied
+ */
+enum status_code slcd_init(struct slcd_config *const config)
+{
+	if (!config) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_SLCD);
+
+	/* Select SLCD clock */
+	OSC32KCTRL->SLCDCTRL.reg = CONF_SLCD_CLOCK_SOURCE & OSC32KCTRL_SLCDCTRL_MASK;
+
+	slcd_disable();
+	slcd_reset();
+
+	SLCD->CTRLA.reg = SLCD_CTRLA_DUTY(CONF_SLCD_DUTY) | SLCD_CTRLA_BIAS(CONF_SLCD_BIAS)
+					 | SLCD_CTRLA_PRESC(CONF_SLCD_PVAL) | SLCD_CTRLA_CKDIV(CONF_SLCD_CKDIV)
+					 | (CONF_SLCD_VLCD_SEL << SLCD_CTRLA_XVLCD_Pos)
+					 | (config->run_in_standby << SLCD_CTRLA_RUNSTDBY_Pos)
+					 | SLCD_CTRLA_RRF(CONF_SLCD_REF_REFRESH_FREQ)
+					 | SLCD_CTRLA_PRF(CONF_SLCD_POWER_REFRESH_FREQ)
+					 | (config->waveform_mode << SLCD_CTRLA_WMOD_Pos);
+	SLCD->CTRLB.reg = SLCD_CTRLB_BBD(config->bias_buffer_duration)
+  					| (config->enable_bias_buffer << SLCD_CTRLB_BBEN_Pos)
+  					| SLCD_CTRLB_LRD(config->low_resistance_duration)
+  					| (config->enable_low_resistance << SLCD_CTRLB_LREN_Pos);
+
+
+    SLCD->CTRLC.reg |= SLCD_CTRLC_LPPM(CONF_SLCD_POWER_MODE) | SLCD_CTRLC_CTST(0x0F);
+
+	SLCD->LPENL.reg = CONF_SLCD_PIN_L_MASK & SLCD_LPENL_MASK;
+	SLCD->LPENH.reg = CONF_SLCD_PIN_H_MASK & SLCD_LPENH_MASK;
+
+   return STATUS_OK;
+}
+
+/**
+ * \brief Enables the SLCD module
+ *
+ * Enables the SLCD module once it has been configured, ready for use. Most
+ * module configuration parameters cannot be altered while the module is enabled.
+ */
+
+void slcd_enable(void)
+{
+	SLCD->CTRLA.reg |= SLCD_CTRLA_ENABLE;
+
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+
+	while (!slcd_get_vlcd_ready_status()) {
+   	}
+}
+
+/**
+ * \brief Disables the SLCD module
+ *
+ * Disables the SLCD module.
+ */
+void slcd_disable(void)
+{
+	SLCD->INTENCLR.reg = SLCD_INTENCLR_MASK;
+	SLCD->INTFLAG.reg = SLCD_INTFLAG_MASK;
+	SLCD->CTRLA.reg &= ~(SLCD_CTRLA_ENABLE);
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Check if SLCD module is enabled or not
+ *
+ * Check if SLCD module is enabled or not.
+ *
+ * \return Enable status.
+ * \retval true SLCD module is enabled
+ * \retval false SLCD module is disabled
+ */
+
+bool slcd_is_enabled(void)
+{
+	return ((SLCD->CTRLA.reg & SLCD_CTRLA_ENABLE) == SLCD_CTRLA_ENABLE);
+}
+
+/**
+ * \brief Reset the SLCD module
+ *
+ * Reset the SLCD module.
+ */
+void slcd_reset(void)
+{
+	slcd_disable();
+	SLCD->CTRLA.reg |= SLCD_CTRLA_SWRST;
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Set the SLCD fine contrast
+ *
+ * The LCD contrast is defined by the value of VLCD voltage. The higher is the
+ * VLCD voltage, the higher is the contrast. The software contrast adjustment
+ * is only possible in internal supply mode.
+ * In internal supply mode, VLCD is in the range 2.5V to 3.5V. VLCD can be
+ * adjusted with 16 steps, each step is 60 mV.The contrast value can be written
+ * at any time.
+ *
+ * \param[in] contrast Contrast value
+ *
+ * \return Status of set contrast.
+ * \retval STATUS_OK               SLCD contrast set successful
+ * \retval STATUS_ERR_INVALID_ARG  SLCD is not working in internal supply mode
+ */
+enum status_code slcd_set_contrast(uint8_t contrast)
+{
+
+	if (SLCD->CTRLA.bit.XVLCD) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+	uint16_t temp = SLCD->CTRLC.reg;
+
+	temp &= ~ SLCD_CTRLC_CTST(0xf);
+	temp |= SLCD_CTRLC_CTST(contrast);
+
+	SLCD->CTRLC.reg = temp;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes SLCD blink configurations struct to defaults
+ *
+ * Initailizes SLCD blink configuration struct to predefined safe default settings.
+ *
+ * \param[in] config Pointer to an instance of \ref struct slcd_blink_config
+ *
+ */
+void slcd_blink_get_config_defaults(struct slcd_blink_config *blink_config)
+{
+	Assert(blink_config);
+
+	blink_config->fc = SLCD_FRAME_COUNTER_0;
+	blink_config->blink_all_seg = true;
+}
+
+/**
+ * \brief Set SLCD blink mode
+ *
+ * Set SLCD blink mode.
+ *
+ *  \note SLCD blink cannot be set while module or blink is enabled.
+ *
+ * \param[in] config  Pointer to an SLCD blink configuration structure
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               SLCD blink configuration went successful
+ * \retval STATUS_ERR_INVALID_ARG  If blink configuration failed
+ */
+
+enum status_code  slcd_blink_set_config(struct slcd_blink_config *const blink_config)
+{
+	if (!blink_config) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	SLCD->BCFG.bit.MODE = (!(blink_config->blink_all_seg) << SLCD_BCFG_MODE_Pos);
+	SLCD->BCFG.bit.FCS	= SLCD_BCFG_FCS(blink_config->fc);
+	return STATUS_OK;
+}
+
+/**
+ * \brief Start an SLCD pixel/segment blinking
+ *
+ * \param[in] pix_com Pixel/segment COM coordinate
+ * \param[in] pix_seg Pixel/segment SEG coordinate (range 0 to 1 inclusive)
+ */
+void slcd_set_blink_pixel(
+		uint8_t pix_com,
+		uint8_t pix_seg)
+{
+	/* Validate parameters. */
+	Assert(pix_seg<=1);
+	
+	if (pix_seg == 0) {
+		SLCD->BCFG.reg |= SLCD_BCFG_BSS0(1 << pix_com);
+	}
+
+	if (pix_seg == 1) {
+		SLCD->BCFG.reg |= SLCD_BCFG_BSS1(1 << pix_com);
+	}
+}
+
+/**
+ * \brief Stop a specified SLCD pixel/segment from blinking
+ *
+ * \param[in] pix_com Pixel/segment COM coordinate
+ * \param[in] pix_seg Pixel/segment SEG coordinate (range 0 to 1 inclusive)
+ */
+void slcd_clear_blink_pixel(
+		uint8_t pix_com,
+		uint8_t pix_seg)
+{
+	/* Validate parameters. */
+	Assert(pix_seg<=1);
+	
+	if (pix_seg == 0) {
+		SLCD->BCFG.reg &= ~ SLCD_BCFG_BSS0(1 << pix_com);
+	}
+
+	if (pix_seg == 1) {
+		SLCD->BCFG.reg &= ~ SLCD_BCFG_BSS1(1 << pix_com);
+	}
+}
+
+/**
+ * \brief Stop all SLCD pixels/segments from blinking
+ */
+void slcd_clear_blink_all_pixel(void)
+{
+	SLCD->BCFG.bit.BSS0 = 0;
+	SLCD->BCFG.bit.BSS1 = 0;
+}
+
+
+/**
+ * \brief Set all bits in the SLCD display memory high
+ */
+void slcd_set_display_memory(void)
+{
+	SLCD->SDATAH0.reg = SLCD_SDATAH0_MASK;
+	SLCD->SDATAL0.reg = SLCD_SDATAL0_MASK;
+	SLCD->SDATAH1.reg = SLCD_SDATAH1_MASK;
+	SLCD->SDATAL1.reg = SLCD_SDATAL1_MASK;
+	SLCD->SDATAH2.reg = SLCD_SDATAH2_MASK;
+	SLCD->SDATAL2.reg = SLCD_SDATAL2_MASK;
+	SLCD->SDATAH3.reg = SLCD_SDATAH3_MASK;
+	SLCD->SDATAL3.reg = SLCD_SDATAL3_MASK;
+	SLCD->SDATAH4.reg = SLCD_SDATAH4_MASK;
+	SLCD->SDATAL4.reg = SLCD_SDATAL4_MASK;
+	SLCD->SDATAH5.reg = SLCD_SDATAH5_MASK;
+	SLCD->SDATAL5.reg = SLCD_SDATAL5_MASK;
+	SLCD->SDATAH6.reg = SLCD_SDATAH6_MASK;
+	SLCD->SDATAL6.reg = SLCD_SDATAL6_MASK;
+	SLCD->SDATAH7.reg = SLCD_SDATAH7_MASK;
+	SLCD->SDATAL7.reg = SLCD_SDATAL7_MASK;
+}
+
+
+/**
+ * \brief Enable the specified pixel/segment in the SLCD display memory
+ *
+ * \param[in] pix_com Pixel/segment COM coordinate,within [0-7]
+ * \param[in] pix_seg Pixel/segment SEG coordinate within [0-43]
+ */
+ void slcd_set_pixel(
+		uint8_t pix_com,
+		uint8_t pix_seg)
+{
+	if ((pix_com < SLCD_MAX_COM) &&
+			(pix_seg < SLCD_MAX_SEG)) {
+		switch(pix_com){
+			case 0:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH0.reg |= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL0.reg |= 1 <<pix_seg;
+				}
+				break;
+			case 1:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH1.reg |= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL1.reg |= 1 <<pix_seg;
+				}
+				break;
+			case 2:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH2.reg |= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL2.reg |= 1 <<pix_seg;
+				}
+				break;
+			case 3:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH3.reg |= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL3.reg |= 1 <<pix_seg;
+				}
+				break;
+			case 4:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH4.reg |= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL4.reg |= 1 <<pix_seg;
+				}
+				break;
+			case 5:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH5.reg |= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL5.reg |= 1 <<pix_seg;
+				}
+				break;
+			case 6:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH6.reg |= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL6.reg |= 1 <<pix_seg;
+				}
+				break;
+			case 7:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH7.reg |= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL7.reg |= 1 <<pix_seg;
+				}
+				break;
+		}
+		while (slcd_get_char_writing_status()) {
+		}
+	}
+}
+
+/**
+ * \brief Disable the specified pixel/segment in the SLCD display memory
+ *
+ * \param[in] pix_com Pixel/segment COM coordinate
+ * \param[in] pix_seg Pixel/segment SEG coordinate
+ */
+ void slcd_clear_pixel(uint8_t pix_com, uint8_t pix_seg)
+{
+	if ((pix_com < SLCD_MAX_COM) &&
+			(pix_seg < SLCD_MAX_SEG)) {
+		switch(pix_com){
+			case 0:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH0.reg &= ~(1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL0.reg &= ~(1 <<pix_seg);
+				}
+				break;
+			case 1:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH1.reg &= ~(1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL1.reg &= ~(1 <<pix_seg);
+				}
+				break;
+			case 2:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH2.reg &= (1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL2.reg &= ~(1 <<pix_seg);
+				}
+				break;
+			case 3:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH3.reg &= ~(1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL3.reg &= ~(1 <<pix_seg);
+				}
+				break;
+			case 4:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH4.reg &= ~(1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL4.reg &= ~(1 <<pix_seg);
+				}
+				break;
+			case 5:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH5.reg &= ~(1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL5.reg &= ~(1 <<pix_seg);
+				}
+				break;
+			case 6:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH6.reg &= ~(1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL6.reg &= ~(1 <<pix_seg);
+				}
+				break;
+			case 7:
+				if (pix_seg >= 32) {
+					SLCD->SDATAH7.reg &= ~(1 <<(pix_seg-32));
+				} else {
+					SLCD->SDATAL7.reg &= ~(1 <<pix_seg);
+				}
+				break;
+		}
+		while (slcd_get_char_writing_status()) {
+		}
+	}
+}
+
+/**
+ * \brief Set the specified segment in the SLCD display memory
+ *
+ * \param[in] pix_seg     Pixel/segment SEG coordinate
+ * \param[in] byte_offset Byte offset in display memory
+ * \param[in] seg_mask    Byte offset in display memory
+ */
+void slcd_set_seg_data(uint8_t seg_data,uint8_t byte_offset,uint8_t seg_mask)
+{
+	SLCD->ISDATA.reg = SLCD_ISDATA_SDATA(seg_data)
+					 | SLCD_ISDATA_OFF(byte_offset)
+					 | SLCD_ISDATA_SDMASK(seg_mask);
+
+	while (slcd_get_char_writing_status()) {
+	}
+}
+
+/**
+ * \brief Initializes SLCD Automated Character configurations struct to defaults
+ *
+ * Initailizes SLCD Automated Character configuration struct to predefined safe default settings.
+ *
+ * \param[in] config Pointer to an instance of \ref struct slcd_automated_char_config
+ *
+ */
+void slcd_automated_char_get_config_default(
+		struct slcd_automated_char_config *config)
+{
+	Assert(config);
+
+	config->order = SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_RIGHT;
+	config->fc = SLCD_FRAME_COUNTER_0;
+	config->mode = SLCD_AUTOMATED_CHAR_SEQ;
+	config->seg_line_num = 0;
+	config->start_seg_line = 0;
+	config->row_digit_num = 1;
+	config->digit_num = 0;
+	config->scrolling_step = 1;
+	config->com_line_num = 1;
+	config->data_mask = 0;
+
+}
+
+/**
+ * \brief Set SLCD automated character
+ *
+ * Set automated character mode.
+ *
+ *  \note SLCD automated character mode cannot be set while module or
+ * automated character is enabled.
+ *
+ * \param[in] config  Pointer to an SLCD automated character configuration structure
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               SLCD automated character configuration went successful
+ * \retval STATUS_ERR_INVALID_ARG  If automated character  configuration failed
+ */
+enum status_code slcd_automated_char_set_config(
+		struct slcd_automated_char_config *const config)
+{
+	if (!config) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+	SLCD->CMCFG.reg = SLCD_CMCFG_NSEG(config->seg_line_num)
+					 | (config->order  << SLCD_CMCFG_DEC_Pos);
+	SLCD->ACMCFG.reg = SLCD_ACMCFG_FCS(config->fc)
+					 | (config->mode << SLCD_ACMCFG_MODE_Pos)
+					 | SLCD_ACMCFG_STSEG(config->start_seg_line)
+					 | SLCD_ACMCFG_NDROW(config->row_digit_num)
+					 | SLCD_ACMCFG_NDIG(config->digit_num)
+					 | SLCD_ACMCFG_STEPS(config->scrolling_step)
+					 | SLCD_ACMCFG_NCOM(config->com_line_num);
+
+	SLCD->CMDMASK.reg = SLCD_CMDMASK_SDMASK(config->data_mask);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Set SLCD character mapping
+ *
+ * Set Character mode amd SEG line per digit.
+ *
+ * \param[in] order         Mapping order in char mode
+ * \param[in] seg_line_num  Define the number of SEG line per digit,
+ *                          it equal to number of SEG line - 1
+ */
+void slcd_character_map_set(
+		enum slcd_automated_char_order order,
+		uint8_t seg_line_num)
+{
+	SLCD->CMCFG.reg = SLCD_CMCFG_NSEG(seg_line_num)
+					 | (order  << SLCD_CMCFG_DEC_Pos);
+}
+
+/**
+ * \brief Write segments data to display memory in character mode
+ *
+ * \param[in] seg_data       Pixel/segment data
+ * \param[in] data_mask      Segments data mask
+ * \param[in] com_line_index COM line index
+ * \param[in] seg_line_index Segments line index
+ */
+void slcd_character_write_data(uint8_t com_line_index,
+									uint8_t seg_line_index,
+									uint32_t seg_data,uint32_t data_mask)
+{
+
+	SLCD->CMINDEX.reg = SLCD_CMINDEX_SINDEX(seg_line_index)
+						| SLCD_CMINDEX_CINDEX(com_line_index);
+	SLCD->CMDMASK.reg = SLCD_CMDMASK_SDMASK(data_mask);
+	SLCD->CMDATA.reg = SLCD_CMDATA_SDATA(seg_data);
+	while (slcd_get_char_writing_status()) {
+	}
+}
+
+/**
+ * \brief Initializes circular shift configurations struct to defaults
+ *
+ * Initailizes circular shift configuration struct to predefined safe default settings.
+ *
+ * \param[in] config Pointer to an instance of \ref struct slcd_circular_shift_config
+ *
+ */
+void slcd_circular_shift_get_config_defaults(
+		struct slcd_circular_shift_config *const config)
+{
+	Assert(config);
+
+	config->fc = SLCD_FRAME_COUNTER_0;
+	config->dir = SLCD_CIRCULAR_SHIFT_LEFT;
+	config->size = 0;
+	config->data = 0;
+}
+
+/**
+ * \brief Set SLCD circular shift
+ *
+ * Set circular shift mode.
+ *
+ * \note SLCD circular shift mode cannot be set while module or circular shift is enabled.
+ *
+ * \param[in] config  Pointer to an SLCD circular shift configuration structure
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               SLCD circular shift configuration went successful
+ * \retval STATUS_ERR_INVALID_ARG  If circular shift configuration failed
+ */
+
+enum status_code slcd_circular_shift_set_config(
+		struct slcd_circular_shift_config *const config)
+{
+	if (!config) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+	SLCD->CSRCFG.reg = SLCD_CSRCFG_FCS(config->fc)
+					 | (config->dir << SLCD_CSRCFG_DIR_Pos)
+					 | SLCD_CSRCFG_SIZE(config->size)
+					 | SLCD_CSRCFG_DATA(config->data);
+
+	return STATUS_OK;
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.h
new file mode 100644
index 0000000000..3b909a9cc0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.h
@@ -0,0 +1,949 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Segment Liquid Crystal Display(SLCD) Controller.
+ *
+ * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SLCD_H_INCLUDED
+#define SLCD_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_drivers_slcd_group SAM Segment Liquid Crystal Display(SLCD) Controller
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's SLCD functionality. The following
+ * driver API modes are covered by this manual:
+ *
+ *  - Polled APIs
+ *  - Callback APIs
+ *
+ *
+ * The following peripheral is used by this module:
+ *  - Segment Liquid Crystal Display(SLCD)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L22
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_drivers_slcd_prerequisites
+ *  - \ref asfdoc_sam0_drivers_slcd_module_overview
+ *  - \ref asfdoc_sam0_drivers_slcd_special_considerations
+ *  - \ref asfdoc_sam0_drivers_slcd_extra_info
+ *  - \ref asfdoc_sam0_drivers_slcd_examples
+ *  - \ref asfdoc_sam0_drivers_slcd_api_overview
+ *
+ *
+ * \section asfdoc_sam0_drivers_slcd_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_drivers_slcd_module_overview Module Overview
+ *
+ * \subsection asfdoc_sam0_drivers_slcd_module_overview_internal Display Overview
+ *
+ * A LCD display is made of several segments (pixels or complete symbols)
+ * which can be visible or invisible. A segment has two electrodes with liquid
+ * crystal between them. These electrodes are the common terminal (COM pin) and
+ * the segment terminal (SEG pin). When a voltage above a threshold voltage is applied
+ * across the liquid crystal, the segment becomes visible. The voltage must alternate,
+ * to avoid an electrophoresis effect in the liquid crystal, which degrades the
+ * display.
+ *
+ * The LCD controller is intended for monochrome passive liquid crystal display (LCD)
+ * with up to 8 common terminals and up to 44 segment terminals. A charge pump provides
+ * LCD display supply which can be higher than supply voltage of the device.
+ * Each LCD pin, segment or common terminals, can be configured as general purpose I/O pins
+ * if not driven by LCD controller.
+ *
+ * \section asfdoc_sam0_drivers_slcd_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_drivers_slcd_special_considerations_io I/O Lines
+ *
+ * The SLCD pins (SEG and COM) are multiplexed with other peripherals. The
+ * user application must first configure the I/O controller, to give control of
+ * the requisite pins to the SLCD.
+ *
+ * \subsection asfdoc_sam0_drivers_slcd_special_considerations_power Power Management
+ *
+ * The SLCD will continue to operate in any sleep mode where the selected source clock
+ * is running. The SLCD interrupts can be used to wake up the device from sleep modes.
+ * Events connected to the event system can trigger other operations in the system
+ * without exiting sleep modes.
+ *
+ * The power consumption of SLCD itself can be minimized by:
+ * - Using the lowest acceptable frame rate (refer to the LCD glass technical
+ * characteristics)
+ * - Using the low-power waveform (default mode)
+ * - Using automated modes of operation
+ * - Configuring the lowest possible contrast value
+ *
+ * \section asfdoc_sam0_drivers_slcd_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_drivers_slcd_extra. This includes:
+ *  - \ref asfdoc_sam0_drivers_slcd_extra_acronyms
+ *  - \ref asfdoc_sam0_drivers_slcd_extra_dependencies
+ *  - \ref asfdoc_sam0_drivers_slcd_extra_errata
+ *  - \ref asfdoc_sam0_drivers_slcd_extra_history
+ *
+ * \section asfdoc_sam0_drivers_slcd_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_drivers_slcd_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_drivers_slcd_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief SLCD frame counter definition
+ *
+ * Enum SLCD frame counter definition.
+ */
+enum slcd_frame_counter {
+	/** SLCD frame counter 0 */
+	SLCD_FRAME_COUNTER_0,
+	/** SLCD frame counter 1 */
+	SLCD_FRAME_COUNTER_1,
+	/** SLCD frame counter 2 */
+	SLCD_FRAME_COUNTER_2,
+};
+
+/**
+ * \brief Waveform mode
+ *
+ * Enum waveform mode.
+ */
+enum slcd_waveform_mode {
+	/** Low power waveform mode */
+	SLCD_LOW_POWER_WAVEFORM_MODE = 0,
+	/** Standard waveform mode */
+	SLCD_STANDARD_WAVEFORM_MODE,
+};
+
+/**
+ * \brief SLCD configuration structure
+ *
+ * Basic configuration for SLCDC.
+ */
+struct slcd_config {
+	/** Keep SLCD enabled in standby sleep mode if true */
+	bool run_in_standby;
+	/** waveform mode selection */
+	enum slcd_waveform_mode waveform_mode;
+
+	/** Low resistance network duration */
+	uint8_t low_resistance_duration;
+	/** Enable Low resistance if true */
+	bool enable_low_resistance;
+	/** Bias buffer duration */
+	uint8_t bias_buffer_duration;
+	/** Enable bias buffer if true */
+	bool enable_bias_buffer;
+};
+/**
+ * \brief SLCD event enable/disable structure
+ *
+ * Event flags for the SLCD module. This is used to enable and
+ * disable events via \ref slcd_enable_events() and \ref slcd_disable_events().
+ */
+struct slcd_events {
+	/** Enable event generation on frame counter 0 overflow */
+	bool generate_event_on_fc0_overflow;
+	/** Enable event generation on frame counter 1 overflow */
+	bool generate_event_on_fc1_overflow;
+	/** Enable event generation on frame counter 2 overflow */
+	bool generate_event_on_fc2_overflow;
+};
+
+/**
+ * \brief SLCD blink configuration
+ *
+ * SLCD blink configuration.
+ */
+struct slcd_blink_config {
+	/** Frame counter selection for blinking */
+	enum slcd_frame_counter fc;
+	/** All segments are allowed to blink if true, else only
+	  Selected segments are allowed to blink */
+	bool blink_all_seg;
+};
+
+/**
+ * \brief SLCD circular shift direction
+ *
+ * Enum SLCD circular shift direction.
+ */
+enum slcd_circular_shift_dir {
+	/** Circular shift direction is left */
+	SLCD_CIRCULAR_SHIFT_LEFT = 0,
+	/** Circular shift direction is right */
+	SLCD_CIRCULAR_SHIFT_RIGHT,
+};
+
+/**
+ * \brief SLCD circular shift configuration
+ *
+ * SLCD circular shift configuration.
+ */
+struct slcd_circular_shift_config {
+	/** Frame counter selection for circular shift */
+	enum slcd_frame_counter fc;
+	/** Shift direction */
+	enum slcd_circular_shift_dir dir;
+	/** Size of the circular shift register, MAX. size is 16 */
+	uint8_t size;
+	/** Circular shift register value */
+	uint16_t data;
+};
+
+/**
+ * \brief Automated char  order
+ *
+ * Enum automated char order.
+ */
+enum slcd_automated_char_order {
+	/** Segment is starting from bottom right */
+	SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_RIGHT = 0,
+	/** Segment is starting from bottom left */
+	SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_LEFT,
+};
+
+/**
+ * \brief Automated char display mode
+ *
+ * Enum automated char display mode.
+ */
+enum slcd_automated_char_mode {
+	/** Sequential Display Mode */
+	SLCD_AUTOMATED_CHAR_SEQ = 0,
+	/** Scrolling Display Mode */
+	SLCD_AUTOMATED_CHAR_SCROLL,
+};
+
+/**
+ * \brief Automated char configuration
+ *
+ * SLCD automated char configuration.
+ */
+struct slcd_automated_char_config {
+	/** Mapping order in automated char mode */
+	enum slcd_automated_char_order order;
+	/** Frame counter selection for automated character mapping */
+	enum slcd_frame_counter fc;
+	/** Display mode */
+	enum slcd_automated_char_mode mode;
+	/** Define the number of SEG line per digit,
+		it equal to number of SEG line - 1 */
+	uint8_t seg_line_num;
+	/** Define the index of the first segment terminal of the digit to display */
+	uint8_t start_seg_line;
+	/** Define the number of digit per row */
+	uint8_t row_digit_num;
+	/** Define the number of digit, it must be greater than 1 */
+	uint8_t digit_num;
+	/** Define the number of steps in scrolling mode.
+		scrolling_step = character string length - digit_num + 1 */
+	uint8_t scrolling_step;
+	/** Define the number of COM line per row,
+		it equal to number of COM line - 1 */
+	uint8_t com_line_num;
+	/** Segments data mask */
+	uint32_t data_mask;
+
+};
+
+/**
+ * \name SLCD Basic Operation Functions
+ * @{
+ */
+
+void slcd_get_config_defaults(struct slcd_config *config);
+enum status_code slcd_init(struct slcd_config *const config);
+void slcd_enable(void);
+void slcd_disable(void);
+bool slcd_is_enabled(void);
+void slcd_reset(void);
+enum status_code slcd_set_contrast(uint8_t contrast);
+
+/**
+ * \brief Determines if SLCD module is currently synchronizing to the bus
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module.
+ *
+ * \retval true  If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+static inline bool slcd_is_syncing(void)
+{
+
+	if (SLCD->SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Lock shadow memory
+ *
+ * It allows update of shadow display memory. If the display memory
+ * is modified, the display remains unchanged when locked.
+ */
+static inline void slcd_lock_shadow_memory(void)
+{
+	SLCD->CTRLC.reg |= SLCD_CTRLC_LOCK;
+}
+
+/**
+ * \brief Unlock shadow memory
+ *
+ * Unlock the shadow display memory.
+ */
+static inline void slcd_unlock_shadow_memory(void)
+{
+	SLCD->CTRLC.reg &= (SLCD_CTRLC_MASK & ( ~SLCD_CTRLC_LOCK));
+}
+
+/**
+ * \brief Clear display memory
+ *
+ * Clears immediately the display memory.
+ */
+static inline void slcd_clear_display_memory(void)
+{
+	SLCD->CTRLC.reg |= SLCD_CTRLC_CLEAR;
+}
+
+/**
+ * \brief Display enable
+ *
+ * Enable COM/SEG signal output.
+ */
+static inline void slcd_enable_display(void)
+{
+	SLCD->CTRLD.reg |= SLCD_CTRLD_DISPEN;
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Display disable
+ *
+ * Disable COM/SEG signal output.
+ */
+static inline void slcd_disable_display(void)
+{
+	SLCD->CTRLD.reg &= (SLCD_CTRLD_MASK & ( ~SLCD_CTRLD_DISPEN));
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+/**
+ * \brief  DMA display memory update frame counter selection
+ *
+ * It's used to select the frame counter for DMA to update the display memory.
+ *
+ *  \note It can be called only before the module is enabled.
+ *
+ *  \param[in] fc Frame coungter index
+ */
+static inline void slcd_dma_display_memory_update_fc_sel(enum slcd_frame_counter fc)
+{
+	SLCD->CTRLA.bit.DMFCS = fc;
+}
+
+/** @} */
+
+/**
+ * \name SLCD Blink Functions
+ * @{
+ */
+
+/**
+ * \brief Blink mode enable
+ *
+ * Enable blink mode.
+ */
+static inline void slcd_enable_blink(void)
+{
+	SLCD->CTRLD.reg |= SLCD_CTRLD_BLINK;
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Blink mode disable
+ *
+ * Disable blink mode.
+ */
+static inline void slcd_disable_blink(void)
+{
+	SLCD->CTRLD.reg &= ~SLCD_CTRLD_BLINK;
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+void slcd_blink_get_config_defaults(struct slcd_blink_config *blink_config);
+enum status_code slcd_blink_set_config(struct slcd_blink_config *const blink_config);
+
+void slcd_clear_blink_all_pixel(void);
+void slcd_clear_blink_pixel(uint8_t pix_com,uint8_t pix_seg);
+void slcd_set_blink_pixel(uint8_t pix_com,uint8_t pix_seg);
+
+/** @} */
+
+/**
+ * \name SLCD Blank Functions
+ * @{
+ */
+
+/**
+ * \brief Blank mode enable
+ *
+ * Enable blank mode.
+ */
+static inline void slcd_enable_blank(void)
+{
+	SLCD->CTRLD.reg |= SLCD_CTRLD_BLANK;
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+/**
+ * \brief Blank mode disable
+ *
+ * Disable blank mode.
+ */
+static inline void slcd_disable_blank(void)
+{
+	SLCD->CTRLD.reg &= ~SLCD_CTRLD_BLANK;
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+/** @} */
+
+/**
+ * \name SLCD Event Functions
+ * @{
+ */
+
+/**
+ * \brief Enables a SLCD event output
+ *
+ *  Enables one or more output events.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+static inline void slcd_enable_events(struct slcd_events *const events)
+{
+
+	Assert(hw);
+	Assert(events);
+
+	uint8_t event_mask = 0;
+
+	if (events->generate_event_on_fc0_overflow) {
+		event_mask |= SLCD_EVCTRL_FC0OEO;
+	}
+
+	if (events->generate_event_on_fc1_overflow) {
+		event_mask |= SLCD_EVCTRL_FC1OEO;
+	}
+
+	if (events->generate_event_on_fc2_overflow) {
+		event_mask |= SLCD_EVCTRL_FC2OEO;
+	}
+
+	SLCD->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables a SLCD event output
+ *
+ *  Disables one or more SLCD events output.
+ *
+ *  \param[in] events Struct containing flags of events to disable
+ */
+static inline void slcd_disable_events(struct slcd_events *const events)
+{
+
+	Assert(events);
+
+	uint8_t event_mask = 0;
+
+	if (events->generate_event_on_fc0_overflow) {
+		event_mask |= SLCD_EVCTRL_FC0OEO;
+	}
+
+	if (events->generate_event_on_fc1_overflow) {
+		event_mask |= SLCD_EVCTRL_FC1OEO;
+	}
+
+	if (events->generate_event_on_fc2_overflow) {
+		event_mask |= SLCD_EVCTRL_FC2OEO;
+	}
+
+	SLCD->EVCTRL.reg &= ~event_mask;
+}
+
+/** @} */
+
+/**
+ * \name SLCD Frame Counter Functions
+ * @{
+ */
+
+/**
+ * \brief Frame counter configuration
+ *
+ *  Config frame counter.
+ *
+ *  \note Frame counter cannot be set while it is enabled.
+ *
+ *  \param[in] fc Frame counter index
+ *  \param[in] presc_bypass_enable Bypass of the frame counter prescaler
+ *  \param[in] overflow_value  Frame counter overflow value. The number of frame
+ *		before overflow is ((overflow_value+1)*8) when presc_bypass_enable=0
+ 		else (overflow_value+1). The MAX. overflow value is 0x1FFFF.
+ */
+static inline void slcd_set_frame_counter(enum slcd_frame_counter fc,
+										   bool  presc_bypass_enable,
+										   uint16_t overflow_value)
+{
+	*(&(SLCD->FC0.reg) + fc) =  (presc_bypass_enable << SLCD_FC0_PB_Pos)
+							 | SLCD_FC0_OVF(overflow_value);
+}
+
+/**
+ * \brief Enables a frame counter
+ *
+ *  Enables one frame counter.
+ *
+ *	\param[in] fc Frame counter index
+ */
+static inline void slcd_enable_frame_counter(enum slcd_frame_counter fc)
+{
+
+	switch(fc) {
+		case SLCD_FRAME_COUNTER_0:
+			SLCD->CTRLD.reg |= SLCD_CTRLD_FC0EN;
+			break;
+		case SLCD_FRAME_COUNTER_1:
+			SLCD->CTRLD.reg |= SLCD_CTRLD_FC1EN;
+			break;
+		case SLCD_FRAME_COUNTER_2:
+			SLCD->CTRLD.reg |= SLCD_CTRLD_FC2EN;
+			break;
+		default :
+			break;
+	}
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Disable a frame counter.
+ *
+ *  Disable one frame counter.
+ *
+ *	\param[in] fc Frame counter index
+ */
+static inline void slcd_disable_frame_counter(enum slcd_frame_counter fc)
+{
+	switch(fc) {
+		case SLCD_FRAME_COUNTER_0:
+			SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC0EN;
+			break;
+		case SLCD_FRAME_COUNTER_1:
+			SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC1EN;
+			break;
+		case SLCD_FRAME_COUNTER_2:
+			SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC2EN;
+			break;
+		default :
+			break;
+	}
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+/** @} */
+
+/**
+ * \name Display Memory Functions
+ * CPU can access display memory in direct access or in indirect access.
+ * @{
+ */
+void slcd_set_display_memory(void);
+void slcd_set_pixel(uint8_t pix_com, uint8_t pix_seg);
+void slcd_clear_pixel(uint8_t pix_com, uint8_t pix_seg);
+
+void slcd_set_seg_data(uint8_t seg_data, uint8_t byte_offset, uint8_t seg_mask);
+/** @} */
+
+/**
+ * \name Character Mapping Functions
+ * @{
+ */
+
+void slcd_character_map_set(
+		enum slcd_automated_char_order order,
+		uint8_t seg_line_num);
+void slcd_character_write_data(uint8_t com_line_index,
+							uint8_t seg_line_index,
+							uint32_t seg_data,
+							uint32_t data_mask);
+
+/**
+ * \brief Enables automated character display
+ *
+ *  Enables automated character display.
+ */
+static inline void slcd_enable_automated_character(void)
+{
+	SLCD->CTRLC.reg |= SLCD_CTRLC_ACMEN;
+}
+
+/**
+ * \brief Disables automated character display
+ *
+ *  Disables automated character display.
+ */
+static inline void slcd_disable_automated_character(void)
+{
+	SLCD->CTRLC.reg &= ~SLCD_CTRLC_ACMEN;
+}
+void slcd_automated_char_get_config_default(
+		struct slcd_automated_char_config *config);
+enum status_code slcd_automated_char_set_config(
+		struct slcd_automated_char_config *const config);
+/** @} */
+
+/**
+ * \name Automated Bit Mapping Functions
+ * @{
+ */
+
+/**
+ * \brief Enables automated bit display
+ *
+ *  Enables automated bit display.
+ */
+static inline void slcd_enable_automated_bit(void)
+{
+	SLCD->CTRLC.reg |= SLCD_CTRLC_ABMEN;
+}
+
+/**
+ * \brief Disables automated bit display
+ *
+ *  Disables automated bit display.
+ */
+static inline void slcd_disable_automated_bit(void)
+{
+	SLCD->CTRLC.reg &= ~SLCD_CTRLC_ABMEN;
+}
+
+/**
+ * \brief Sets automated bit display
+ *
+ *  Sets automated bit display.
+ *
+ *  \note Automated bit cannot be set while it is enabled or busy.
+ */
+static inline void slcd_set_automated_bit(uint8_t size,enum slcd_frame_counter fc)
+{
+	if(size > 0 && size < 0x3f) {
+		SLCD->ABMCFG.reg = SLCD_ABMCFG_SIZE(size) | SLCD_ABMCFG_FCS(fc);
+	}
+}
+
+/** @} */
+
+/**
+ * \name Autonomous Segment Animation
+ * @{
+ */
+
+/**
+ * \brief Enable SLCD circular shift mode
+ */
+static inline void slcd_enable_circular_shift(void)
+{
+	SLCD->CTRLD.reg |= SLCD_CTRLD_CSREN;
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+/**
+ * \brief Disable SLCD circular shift mode
+ */
+static inline void slcd_disable_circular_shift(void)
+{
+	SLCD->CTRLD.reg &= ~SLCD_CTRLD_CSREN;
+	while (slcd_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+void slcd_circular_shift_get_config_defaults(
+		struct slcd_circular_shift_config *const config);
+
+enum status_code slcd_circular_shift_set_config(
+		struct slcd_circular_shift_config *const config);
+
+/** @} */
+
+/**
+ * \name SLCD Status
+ * @{
+ */
+
+/**
+ * \brief Checks if auto bit mapping state machine is busy
+ *
+ * Checks if  auto bit mapping state machine is busy or not.
+ *
+ * \retval true   Auto bit mapping state machine is busy
+ * \retval false  Auto bit mapping state machine is idle
+ */
+
+static inline bool slcd_get_auto_bit_status(void)
+{
+	return ((SLCD->STATUS.reg & SLCD_STATUS_ABMBUSY) == SLCD_STATUS_ABMBUSY);
+}
+
+/**
+ * \brief Checks if auto character mapping state machine is busy
+ *
+ * Checks if  auto character state machine is busy or not.
+ *
+ * \retval true   Auto character mapping state machine is busy
+ * \retval false  Auto character mapping state machine is idle
+ */
+
+static inline bool slcd_get_auto_char_status(void)
+{
+	return ((SLCD->STATUS.reg & SLCD_STATUS_ACMBUSY) == SLCD_STATUS_ACMBUSY);
+}
+
+/**
+ * \brief Checks if character writing function is busy
+ *
+ * Checksif character writing function is busy or not.
+ *
+ * \retval true   Character writting function is busy
+ * \retval false  Character writting function is ready for use
+ */
+
+static inline bool slcd_get_char_writing_status(void)
+{
+	return ((SLCD->STATUS.reg & SLCD_STATUS_CMWRBUSY) == SLCD_STATUS_CMWRBUSY);
+}
+
+/**
+ * \brief Checks VLCD and VDD33 status
+ *
+ * Checks VLCD and VDD33 status.
+ *
+ * \retval true   VDD33 is greater than target VLCD
+ * \retval false  Target VLCD is greater than vdd33
+ */
+
+static inline bool slcd_get_vlcd_vdd33_status(void)
+{
+	return ((SLCD->STATUS.reg & SLCD_STATUS_VLCDS) == SLCD_STATUS_VLCDS);
+}
+
+/**
+ * \brief Checks LCD charge pump status
+ *
+ * Checks LCD Charge Pump Status.
+ *
+ * \retval true   LCD power charge pump is running
+ * \retval false  LCD power charge pump is stopped
+ */
+
+static inline bool slcd_get_charge_pump_status(void)
+{
+	return ((SLCD->STATUS.reg & SLCD_STATUS_PRUN) == SLCD_STATUS_PRUN);
+}
+
+/**
+ * \brief Checks if VLCD  is ready
+ *
+ * Checks if VLCD is well regulated to the target value.
+ *
+ * \retval true   VLCD is well regulated to the target value
+ * \retval false  VLCD is not well regulated to the target value
+ */
+
+static inline bool slcd_get_vlcd_ready_status(void)
+{
+	return ((SLCD->STATUS.reg & SLCD_STATUS_VLCDR) == SLCD_STATUS_VLCDR);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_drivers_slcd_extra Extra Information for SLCD
+ *
+ * \section asfdoc_sam0_drivers_slcd_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>SLCD</td>
+ *      <td>Segment Liquid Crystal Display</td>
+ * </tr>
+ *  <tr>
+ *      <td>COM</td>
+ *      <td>Common, denotes how many segments are connected to a segment terminal</td>
+ * </tr>
+ *  <tr>
+ *      <td>SEG</td>
+ *      <td>Segment, the least viewing element (pixel) which can be on or off</td>
+ * </tr>
+ *  <tr>
+ *      <td>Duty</td>
+ *      <td> 1/(Number of common terminals on an actual LCD display)</td>
+ * </tr>
+ *  <tr>
+ *      <td>Bias</td>
+ *      <td>1/(Number of voltage levels used driving a LCD display -1)</td>
+ * </tr>
+ *  <tr>
+ *      <td>Frame Rate</td>
+ *      <td>Number of times the LCD segments are energized per second</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_drivers_slcd_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_drivers_slcd_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_drivers_slcd_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_drivers_slcd_exqsg Examples for SLCD
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_drivers_slcd_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_slcd_basic_use_case
+ *
+ * \page asfdoc_sam0_drivers_slcd_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *      <td>42605A</td>
+ *		<td>12/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ *
+ */
+
+#endif  /* SLCD_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.c
new file mode 100644
index 0000000000..9b300aded1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.c
@@ -0,0 +1,125 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Segment Liquid Crystal Display(SLCD) Controller.
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "slcd.h"
+#include "slcd_callback.h"
+
+/**
+* \internal
+* \brief slcd callback function pointer
+*/
+slcd_callback_t slcd_callback_pointer[SLCD_CALLBACK_TYPE_NUM];
+
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref slcd_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     callback_func Pointer to callback function
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \retval STATUS_OK  The function exited successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+
+enum status_code slcd_register_callback(
+	const slcd_callback_t callback,
+	const enum slcd_callback_type type)
+{
+	if (type >= SLCD_CALLBACK_TYPE_NUM){
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	slcd_callback_pointer[type] = callback;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function implemented by the user.
+ *
+ * \param[in]  callback_type Callback type given by an enum
+ *
+ * \retval STATUS_OK  The function exited successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+
+enum status_code slcd_unregister_callback(
+	const slcd_callback_t callback,
+	const enum slcd_callback_type type)
+{
+	if (type >= SLCD_CALLBACK_TYPE_NUM){
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	slcd_callback_pointer[type] = NULL;
+	return STATUS_OK;
+}
+
+/**
+* \internal The SLCD interrupt handler.
+*/
+void SLCD_Handler(void)
+{
+	uint32_t status = SLCD->INTFLAG.reg;
+	for (uint8_t i = 0; i < SLCD_CALLBACK_TYPE_NUM; i++) {
+		if (status & (1 << i)) {
+			/* Clear the INTFLAG anyway */
+			SLCD->INTFLAG.reg = 1 << i;
+
+			if (slcd_callback_pointer[i]) {
+				slcd_callback_pointer[i]((enum slcd_callback_type)i);
+			}
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.h
new file mode 100644
index 0000000000..d6d9723840
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.h
@@ -0,0 +1,138 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Segment Liquid Crystal Display(SLCD) Controller.
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SLCD_CALLBACK_H_INCLUDED
+#define SLCD_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system_interrupt.h>
+/**
+ * \addtogroup asfdoc_sam0_drivers_slcd_group
+ *
+ * @{
+ */
+
+/**
+ * \brief SLCD callback type
+ *
+ * Enum SLCD callback type. 
+ */
+enum slcd_callback_type {
+	/** Frame Counter 0 Overflow callback */
+	SLCD_CALLBACK_FC0_OVERFLOW = 0,
+	/** Frame Counter 1 Overflow callback */
+	SLCD_CALLBACK_FC1_OVERFLOW,
+	/** Frame Counter 2 Overflow callback */
+	SLCD_CALLBACK_FC2_OVERFLOW,
+	/** VLCD Ready Toggle callback */
+	SLCD_CALLBACK_VLCD_READY,
+	/** VLCD Status Toggle callback */
+	SLCD_CALLBACK_VLCD_TOGGLE,
+	/** Pump Run Status Toggle callback */
+	SLCD_CALLBACK_PUMP_TOGGLE,
+};
+
+/** SLCD interrupt callback function type. */
+typedef void (*slcd_callback_t)(enum slcd_callback_type type);
+
+/** \internal Max number of callback type. */
+#define SLCD_CALLBACK_TYPE_NUM 6
+
+/** \name Callback Function
+ * @{
+ */
+
+enum status_code slcd_register_callback(
+	const slcd_callback_t callback,
+	const enum slcd_callback_type type);
+
+enum status_code slcd_unregister_callback(
+	const slcd_callback_t callback,
+	const enum slcd_callback_type type);
+
+/**
+ * \brief Enable an SLCD callback
+ *
+ * \param[in] type Callback source type
+ *
+ * \retval STATUS_OK  The function exited successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+static inline void slcd_enable_callback(const enum slcd_callback_type type)
+{
+	if (type < SLCD_CALLBACK_TYPE_NUM){
+		SLCD->INTENSET.reg = 1 << type;
+	}
+}
+
+/**
+ * \brief Disable an SLCD callback
+ *
+ * \param[in]  type Callback source type
+ *
+ * \retval STATUS_OK  The function exited successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+static inline void slcd_disable_callback(const enum slcd_callback_type type)
+{
+	if (type < SLCD_CALLBACK_TYPE_NUM){
+		SLCD->INTENCLR.reg = 1 << type;
+	}
+}
+
+/** @} */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* SLCD_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/module_config/conf_spi.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/module_config/conf_spi.h
new file mode 100644
index 0000000000..a2facfe9ad
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/module_config/conf_spi.h
@@ -0,0 +1,55 @@
+/**
+ * \file
+ *
+ * \brief SAM SPI configuration
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef CONF_SPI_H_INCLUDED
+#  define CONF_SPI_H_INCLUDED
+
+#  define CONF_SPI_MASTER_ENABLE     true
+#  define CONF_SPI_SLAVE_ENABLE      true
+
+#endif /* CONF_SPI_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.c
new file mode 100644
index 0000000000..32bd853035
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.c
@@ -0,0 +1,866 @@
+/**
+ * \file
+ *
+ * \brief Serial Peripheral Interface Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "spi.h"
+
+/**
+ * \brief Determines if the SPI module is currently synchronizing to the bus.
+ *
+ * This function will check if the underlying hardware peripheral module is
+ * currently synchronizing across multiple clock domains to the hardware bus.
+ * This function can be used to delay further operations on the module until it
+ * is ready.
+ *
+ * \param[in]  module  SPI hardware module
+ *
+ * \return Synchronization status of the underlying hardware module
+ * \retval true   Module synchronization is ongoing
+ * \retval false  Module synchronization is not ongoing
+ *
+ */
+static bool _spi_is_active(Spi *const spi_module)
+{
+	Assert(spi_module);
+
+	return spi_module->SPI_BUS_STATUS.bit.SPI_ACTIVE;
+}
+
+/**
+ * \internal Enable SPI clock.
+ *
+ * This function will enable SPI clock.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ */
+static void _spi_clock_enable(struct spi_module *const module)
+{
+	Assert(module);
+
+	Spi *const spi_module = (module->hw);
+
+	if (spi_module == (void *)SPI0) {
+		system_clock_peripheral_enable(PERIPHERAL_SPI0_SCK_CLK);
+		system_clock_peripheral_enable(PERIPHERAL_SPI0_SCK_PHASE);
+		system_clock_peripheral_enable(PERIPHERAL_SPI0_IF);
+		system_clock_peripheral_enable(PERIPHERAL_SPI0_CORE);
+	} else if (spi_module == (void *)SPI1) {
+		system_clock_peripheral_enable(PERIPHERAL_SPI1_SCK_CLK);
+		system_clock_peripheral_enable(PERIPHERAL_SPI1_SCK_PHASE);
+		system_clock_peripheral_enable(PERIPHERAL_SPI1_IF);
+		system_clock_peripheral_enable(PERIPHERAL_SPI1_CORE);
+	}
+}
+
+/**
+ * \internal Disable SPI clock.
+ *
+ * This function will disable SPI clock.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ */
+static void _spi_clock_disable(struct spi_module *const module)
+{
+	Assert(module);
+
+	Spi *const spi_module = (module->hw);
+
+	if (spi_module == (void *)SPI0) {
+		system_clock_peripheral_disable(PERIPHERAL_SPI0_SCK_CLK);
+		system_clock_peripheral_disable(PERIPHERAL_SPI0_SCK_PHASE);
+		system_clock_peripheral_disable(PERIPHERAL_SPI0_IF);
+		system_clock_peripheral_disable(PERIPHERAL_SPI0_CORE);
+	} else if (spi_module == (void *)SPI1) {
+		system_clock_peripheral_disable(PERIPHERAL_SPI1_SCK_CLK);
+		system_clock_peripheral_disable(PERIPHERAL_SPI1_SCK_PHASE);
+		system_clock_peripheral_disable(PERIPHERAL_SPI1_IF);
+		system_clock_peripheral_disable(PERIPHERAL_SPI1_CORE);
+	}
+}
+
+/**
+ * \internal Writes an SPI configuration to the hardware module.
+ *
+ * This function will write out a given configuration to the hardware module.
+ * Can only be done when the module is disabled.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return The status of the configuration
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_OK               If the configuration was written
+ */
+static enum status_code _spi_set_config(
+		struct spi_module *const module,
+		const struct spi_config *const config)
+{
+	Assert(module);
+	Assert(config);
+
+	Spi *const spi_module = (module->hw);
+
+	module->mode  = config->mode;
+
+#if CONF_SPI_MASTER_ENABLE == true
+	/* Find baud value and write it */
+	if (config->mode == SPI_MODE_MASTER) {
+		spi_module->SPI_CLK_DIVIDER.reg = config->clock_divider;
+	}
+#endif
+
+	/* Set data order */
+	if (config->data_order == SPI_DATA_ORDER_LSB) {
+		spi_module->SPI_CONFIGURATION.bit.LSB_FIRST_ENABLE = 0x1;
+	} else {
+		spi_module->SPI_CONFIGURATION.bit.LSB_FIRST_ENABLE = 0x0;
+	}
+
+	/* Set clock polarity and clock phase */
+	switch(config->transfer_mode)
+	{
+		case SPI_TRANSFER_MODE_0:
+			spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x0;
+			spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x0;
+			break;
+		case SPI_TRANSFER_MODE_1:
+			spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x1;
+			spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x0;
+			break;
+		case SPI_TRANSFER_MODE_2:
+			spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x0;
+			spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x1;
+			break;
+		case SPI_TRANSFER_MODE_3:
+			spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x1;
+			spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x1;
+			break;
+		default:
+			break;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Checks if the SPI in master mode has shifted out last data, or if the
+ * master has ended the transfer in slave mode.
+ *
+ * This function will check if the SPI master module has shifted out last data,
+ * or if the slave select pin has been drawn high by the master for the SPI
+ * slave module.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ *
+ * \return Indication of whether any writes are ongoing
+ * \retval true   If the SPI master module has shifted out data, or slave select
+ *                has been drawn high for SPI slave
+ * \retval false  If the SPI master module has not shifted out data
+ */
+static inline bool _spi_is_write_complete(
+		Spi *const spi_module)
+{
+	Assert(spi_module);
+
+	/* Check interrupt flag */
+	return (spi_module->TRANSMIT_STATUS.bit.TX_FIFO_EMPTY);
+}
+
+
+ /**
+ * \brief Checks if the SPI module is ready to write data
+ *
+ * This function will check if the SPI module is ready to write data.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ *
+ * \return Indication of whether the module is ready to read data or not
+ * \retval true   If the SPI module is ready to write data
+ * \retval false  If the SPI module is not ready to write data
+ */
+static inline bool _spi_is_ready_to_write(
+		Spi *const spi_module)
+{
+	Assert(spi_module);
+
+	/* Check interrupt flag */
+	return (spi_module->TRANSMIT_STATUS.bit.TX_FIFO_NOT_FULL);
+}
+
+/**
+ * \brief Checks if the SPI module is ready to read data
+ *
+ * This function will check if the SPI module is ready to read data.
+ *
+ * \param[in]  module Pointer to the software instance struct
+ *
+ * \return Indication of whether the module is ready to read data or not
+ * \retval true   If the SPI module is ready to read data
+ * \retval false  If the SPI module is not ready to read data
+ */
+static inline bool _spi_is_ready_to_read(
+		Spi *const spi_module)
+{
+	Assert(spi_module);
+
+	/* Check interrupt flag */
+	return (spi_module->RECEIVE_STATUS.bit.RX_FIFO_NOT_EMPTY);
+}
+
+/**
+ * \brief Initializes an SPI peripheral slave device configuration structure to default values
+ *
+ * This function will initialize a given SPI slave device configuration
+ * structure to a set of known default values. This function should be called
+ * on any new instance of the configuration structures before being modified by
+ * the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Slave Select on GPIO pin 12
+ *  \li Addressing not enabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void spi_slave_inst_get_config_defaults(
+		struct spi_slave_inst_config *const config)
+{
+	Assert(config);
+
+	config->ss_pin          = PIN_LP_GPIO_12;
+	config->address_enabled = false;
+	config->address         = 0;
+}
+
+/**
+ * \brief Initializes an SPI configuration structure to default values
+ *
+ * This function will initialize a given SPI configuration structure to a set
+ * of known default values. This function should be called on any new
+ * instance of the configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Master mode enabled
+ *  \li MSB of the data is transmitted first
+ *  \li Transfer mode 0
+ *  \li MUX Setting 0
+ *  \li Character size 8 bit
+ *  \li Not enabled in sleep mode
+ *  \li Receiver enabled
+ *  \li Baudrate 50000
+ *  \li Default pinmux settings for all pads
+ *  \li Clock source 0 (26MHz)
+ *  \li	Clock divider  (Formula: baud_rate = ((clock input freq/clock_divider+1)/2))
+ *                                  (For Example: if clock source is CLOCK_INPUT_0 then
+ *                                  ((26000000/(129+1))/2) = 100000 bps)
+ *
+ * \param[in,out] config  Configuration structure to initialize to default values
+ */
+void spi_get_config_defaults(
+		struct spi_config *const config)
+{
+	Assert(config);
+
+	config->mode             = SPI_MODE_MASTER;
+	config->data_order       = SPI_DATA_ORDER_MSB;
+	config->transfer_mode    = SPI_TRANSFER_MODE_0;
+	config->clock_source     = SPI_CLK_INPUT_0;
+	config->clock_divider    = 129;
+
+	config->pin_number_pad[0] = PIN_LP_GPIO_10;
+	config->pin_number_pad[1] = PIN_LP_GPIO_11;
+	config->pin_number_pad[2] = PIN_LP_GPIO_12;
+	config->pin_number_pad[3] = PIN_LP_GPIO_13;
+
+	config->pinmux_sel_pad[0] = MUX_LP_GPIO_10_SPI0_SCK;
+	config->pinmux_sel_pad[1] = MUX_LP_GPIO_11_SPI0_MOSI;
+	config->pinmux_sel_pad[2] = MUX_LP_GPIO_12_SPI0_SSN;
+	config->pinmux_sel_pad[3] = MUX_LP_GPIO_13_SPI0_MISO;
+};
+
+/**
+ * \brief Attaches an SPI peripheral slave
+ *
+ * This function will initialize the software SPI peripheral slave, based on
+ * the values of the config struct. The slave can then be selected and
+ * optionally addressed by the \ref spi_select_slave function.
+ *
+ * \param[out] slave   Pointer to the software slave instance struct
+ * \param[in]  config  Pointer to the config struct
+ *
+ */
+void spi_attach_slave(
+		struct spi_slave_inst *const slave,
+		struct spi_slave_inst_config *const config)
+{
+	Assert(slave);
+	Assert(config);
+
+	slave->ss_pin          = config->ss_pin;
+	slave->address_enabled = config->address_enabled;
+	slave->address         = config->address;
+
+	struct gpio_config config_gpio;
+	gpio_get_config_defaults(&config_gpio);
+	config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
+	gpio_pin_set_config(slave->ss_pin, &config_gpio);
+
+	gpio_pin_set_output_level(slave->ss_pin, true);
+}
+
+/**
+ * \brief Resets the SPI module
+ *
+ * This function will reset the SPI module to its power on default values and
+ * disable it.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ */
+void spi_reset(struct spi_module *const module)
+{
+	/* Sanity check arguments */
+	Spi *const spi_module = (module->hw);
+
+	/* Disable the module */
+	spi_disable(module);
+
+	/* Software reset the module */
+	if(spi_module == (void *)SPI0) {
+		system_peripheral_reset(PERIPHERAL_SPI0_CORE);
+		system_peripheral_reset(PERIPHERAL_SPI0_IF);
+	} else if (spi_module == (void *)SPI1) {
+		system_peripheral_reset(PERIPHERAL_SPI1_CORE);
+		system_peripheral_reset(PERIPHERAL_SPI1_IF);
+	}
+}
+
+/**
+ * \brief Initializes the SPI module
+ *
+ * This function will initialize the SPI module, based on the values
+ * of the config struct.
+ *
+ * \param[out]  module  Pointer to the software instance struct
+ * \param[in]   hw      Pointer to hardware instance
+ * \param[in]   config  Pointer to the config struct
+ *
+ * \return Status of the initialization
+ * \retval STATUS_OK               Module initiated correctly
+ * \retval STATUS_ERR_DENIED       If module is enabled
+ * \retval STATUS_BUSY             If module is busy resetting
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code spi_init(
+		struct spi_module *const module,
+		Spi *const hw,
+		const struct spi_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	uint8_t idx;
+
+	/* Initialize device instance */
+	module->hw = hw;
+
+	Spi *const spi_module = (module->hw);
+
+	/* Check if module is enabled. */
+	if (spi_module->SPI_MODULE_ENABLE.reg & SPI_MODULE_ENABLE_MASK) {
+		spi_module->SPI_MODULE_ENABLE.reg = (0x0ul << SPI_MODULE_ENABLE_ENABLE_Pos);
+	}
+
+	spi_reset(module);
+	_spi_clock_enable(module);
+
+#if SPI_CALLBACK_MODE == true
+	if (module->hw == SPI0) {
+		_spi_instances[0] = module;
+		system_register_isr(RAM_ISR_TABLE_SPIRX0_INDEX, (uint32_t)spi_rx0_isr_handler);
+		system_register_isr(RAM_ISR_TABLE_SPITX0_INDEX, (uint32_t)spi_tx0_isr_handler);
+	} else if (module->hw == SPI1) {
+		_spi_instances[1] = module;
+		system_register_isr(RAM_ISR_TABLE_SPIRX1_INDEX, (uint32_t)spi_rx1_isr_handler);
+		system_register_isr(RAM_ISR_TABLE_SPITX1_INDEX, (uint32_t)spi_tx1_isr_handler);
+	}
+#endif
+
+	//Program the pinmux.
+	struct gpio_config config_gpio;
+	gpio_get_config_defaults(&config_gpio);
+
+	/* Set the pinmux for this spi module. */
+	for(idx = 0; idx < 4; idx++) {
+		if (config->pin_number_pad[idx] != PINMUX_UNUSED) {
+			if (config->mode == SPI_MODE_MASTER) {
+				config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
+			} else if (config->mode == SPI_MODE_SLAVE) {
+				config_gpio.direction = GPIO_PIN_DIR_INPUT;
+			}
+			gpio_pin_set_config(config->pin_number_pad[idx], &config_gpio);
+			gpio_pinmux_cofiguration(config->pin_number_pad[idx], \
+						(uint16_t)(config->pinmux_sel_pad[idx]));
+		}
+	}
+
+	/* Set up the input clock for the module */
+	spi_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
+
+#  if CONF_SPI_MASTER_ENABLE == true
+	if (config->mode == SPI_MODE_MASTER) {
+		/* Set the mode in SPI master mode */
+		spi_module->SPI_MASTER_MODE.reg = SPI_MODE_MASTER;
+	}
+#  endif
+
+#  if CONF_SPI_SLAVE_ENABLE == true
+	if (config->mode == SPI_MODE_SLAVE) {
+		/* Set the mode in SPI slave mode */
+		spi_module->SPI_MASTER_MODE.reg = SPI_MODE_SLAVE;
+	}
+#  endif
+
+#if SPI_CALLBACK_MODE == true
+	/* Temporary variables */
+	uint8_t i;
+
+	/* Initialize parameters */
+	for (i = 0; i < SPI_CALLBACK_N; i++) {
+		module->callback[i]        = NULL;
+	}
+	module->tx_buffer_ptr              = NULL;
+	module->rx_buffer_ptr              = NULL;
+	module->remaining_tx_buffer_length = 0x0000;
+	module->remaining_rx_buffer_length = 0x0000;
+	module->registered_callback        = 0x00;
+	module->enabled_callback           = 0x00;
+	module->status                     = STATUS_OK;
+	module->dir                        = SPI_DIRECTION_IDLE;
+	module->locked                     = 0;
+#endif
+
+	/* Write configuration to module and return status code */
+	return _spi_set_config(module, config);
+}
+
+/**
+ * \name Enable/Disable
+ * @{
+ */
+
+/**
+ * \brief Enables the SPI module
+ *
+ * This function will enable the SPI module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void spi_enable(struct spi_module *const module)
+{
+	Spi *const spi_module = (module->hw);
+
+#if SPI_CALLBACK_MODE == true
+	if(spi_module == SPI0) {
+		NVIC_EnableIRQ(SPI0_RX_IRQn);
+		NVIC_EnableIRQ(SPI0_TX_IRQn);
+	} else if(spi_module == SPI1) {
+		NVIC_EnableIRQ(SPI1_RX_IRQn);
+		NVIC_EnableIRQ(SPI1_TX_IRQn);
+	}
+#endif
+
+	/* Enable SPI */
+	spi_module->SPI_MODULE_ENABLE.reg = SPI_MODULE_ENABLE_ENABLE;
+}
+
+/**
+ * \brief Disables the SPI module
+ *
+ * This function will disable the SPI module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void spi_disable(struct spi_module *const module)
+{
+	Spi *const spi_module = (module->hw);
+
+#  if SPI_CALLBACK_MODE == true
+	if(spi_module == SPI0) {
+		NVIC_DisableIRQ(SPI0_RX_IRQn);
+		NVIC_DisableIRQ(SPI0_TX_IRQn);
+	} else if(spi_module == SPI1) {
+		NVIC_DisableIRQ(SPI1_RX_IRQn);
+		NVIC_DisableIRQ(SPI1_TX_IRQn);
+	}
+#  endif
+
+	/* Disable SPI */
+	spi_module->SPI_MODULE_ENABLE.reg = (0x0ul << SPI_MODULE_ENABLE_ENABLE_Pos);
+	_spi_clock_disable(module);
+}
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK   If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+enum status_code spi_lock(struct spi_module *const module)
+{
+	enum status_code status;
+
+	if (module->locked) {
+		status = STATUS_BUSY;
+	} else {
+		module->locked = true;
+		status = STATUS_OK;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock.
+ *
+ * \retval STATUS_OK   If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+void spi_unlock(struct spi_module *const module)
+{
+	module->locked = false;
+}
+
+/**
+ * \brief Transfers a single SPI character
+ *
+ * This function will send a single SPI character via SPI and ignore any data
+ * shifted in by the connected device. To both send and receive data, use the
+ * \ref spi_transceive_wait function or use the \ref spi_read function after
+ * writing a character.
+ *
+ * Note that this function does not handle the SS (Slave Select)
+ * pin(s) in master mode; this must be handled from the user application.
+ *
+ * \note In slave mode, the data will not be transferred before a master
+ *       initiates a transaction.
+ *
+ * \param[in] module   Pointer to the software instance struct
+ * \param[in] tx_data  Data to transmit
+ *
+ * \return Status of the procedure
+ * \retval STATUS_OK    If the data was written
+ * \retval STATUS_BUSY  If the last write was not completed
+ */
+enum status_code spi_write(struct spi_module *module, uint8_t tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Spi *const spi_module = (module->hw);
+
+	/* Check if the data register has been copied to the shift register */
+	if (!_spi_is_ready_to_write(spi_module)) {
+		/* Data register has not been copied to the shift register, return */
+		return STATUS_BUSY;
+	}
+
+	/* Write the character to the DATA register */
+	spi_module->TRANSMIT_DATA.reg = tx_data & SPI_TRANSMIT_DATA_MASK;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Reads last received SPI character
+ *
+ * This function will return the last SPI character shifted into the receive
+ * register by the \ref spi_write function
+ *
+ * \note Receiver must be enabled in the configuration
+ *
+ * \param[in] module    Pointer to the software instance struct
+ * \param[out] rx_data  Pointer to store the received data
+ *
+ * \returns Status of the read operation.
+ * \retval STATUS_OK            If data was read
+ * \retval STATUS_ERR_IO        If no data is available
+ * \retval STATUS_ERR_OVERFLOW  If the data is overflown
+ */
+enum status_code spi_read(
+		struct spi_module *const module,
+		uint8_t *rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Spi *const spi_module = (module->hw);
+
+	/* Check if data is ready to be read */
+	if (!_spi_is_ready_to_read(spi_module)) {
+		/* No data has been received, return */
+		return STATUS_ERR_IO;
+	}
+
+	/* Return value */
+	enum status_code retval = STATUS_OK;
+
+	/* Check if data is overflown */
+	if (spi_module->RECEIVE_STATUS.bit.FIFO_OVERRUN) {
+		retval = STATUS_ERR_OVERFLOW;
+	}
+
+	/* Read the character from the DATA register */
+	*rx_data = ((uint8_t)spi_module->RECEIVE_DATA.reg & SPI_RECEIVE_DATA_MASK);
+
+	return retval;
+}
+
+/**
+ * \brief Transceive requested amount of data to and from the SPI.
+ *
+ * This function will return after sending and receiving requested amount of data
+ *
+ * \note Receiver must be enabled in the configuration
+ * \note The \ref spi_select_slave function should be called before calling
+ *       this function.
+ *
+ * \param[in] module    Pointer to the software instance struct
+ * \param[in] tx_data   Pointer containing the data to be transmitted
+ * \param[in] length    Length of data to be read
+ * \param[out] rx_data  Pointer to store the received data
+ *
+ * \returns Status of the read operation.
+ * \retval STATUS_OK            If data was read
+ * \retval STATUS_ERR_IO        If no data is available
+ * \retval STATUS_ERR_OVERFLOW  If the data is overflown
+ */
+enum status_code spi_transceive_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	Spi *spi_module = module->hw;
+	uint8_t dummy = 0;
+	uint8_t skip_mosi = 0;
+	uint8_t skip_miso = 0;
+	uint8_t status;
+	uint16_t transfer_len = 0;
+
+	if(spi_module == 0) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+	if(!tx_data) {
+		tx_data = &dummy;
+		*tx_data = module->tx_dummy_byte;
+		skip_mosi = 1;
+	} else if(!rx_data) {
+		rx_data = &dummy;
+		skip_miso = 1;
+	} else if(length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check for Idle */
+	do {
+		status = _spi_is_active(spi_module);
+	}while(status);
+
+	/* Clear all status registers */
+	spi_module->RECEIVE_STATUS.reg;
+	spi_module->TRANSMIT_STATUS.reg;
+
+	/* Start transfer */
+	while(transfer_len < length) {
+		/* Write data to MOSI */
+		while(!_spi_is_ready_to_write(spi_module));
+		spi_module->TRANSMIT_DATA.reg = *tx_data;
+		/* Read data shifted from MISO */
+		while(!_spi_is_ready_to_read(spi_module));
+		*rx_data = spi_module->RECEIVE_DATA.reg;
+		transfer_len++;
+		if (!skip_mosi) {
+			tx_data++;
+		}
+		if (!skip_miso) {
+			rx_data++;
+		}
+	}
+	/* check TXFIFO is empty */
+	do {
+		status = _spi_is_write_complete(spi_module);
+	}while(!status);
+
+	return STATUS_OK;
+
+}
+
+/**
+ * \brief Transceive single byte of data to and from the SPI.
+ *
+ * This function will return after single byte of data transceived.
+ *
+ * \note Receiver must be enabled in the configuration
+ * \note The \ref spi_select_slave function should be called before calling
+ *       this function.
+ *
+ * \param[in] module    Pointer to the software instance struct
+ * \param[in] tx_data   Pointer containing the data to be transmitted
+ * \param[out] rx_data  Pointer to store the received data
+ *
+ * \returns Status of the read operation.
+ * \retval STATUS_OK            If data was read
+ * \retval STATUS_ERR_IO        If no data is available
+ * \retval STATUS_ERR_OVERFLOW  If the data is overflown
+ */
+enum status_code spi_transceive_wait(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data)
+{
+	return spi_transceive_buffer_wait(module, tx_data, rx_data, 1);
+}
+
+/**
+ * \brief Reads requested amount of data from the SPI.
+ *
+ * This function will return after reading requested amount of data
+ *
+ * \note Receiver must be enabled in the configuration
+ * \note The \ref spi_select_slave function should be called before calling
+ *       this function.
+ *
+ * \param[in] module    Pointer to the software instance struct
+ * \param[in] length    Length of data to be read
+ * \param[in] dummy     Dummy byte to be sent on bus when reading data
+ * \param[out] rx_data  Pointer to store the received data
+ *
+ * \returns Status of the read operation.
+ * \retval STATUS_OK            If data was read
+ * \retval STATUS_ERR_IO        If no data is available
+ * \retval STATUS_ERR_OVERFLOW  If the data is overflown
+ */
+enum status_code spi_read_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length,
+		uint8_t dummy)
+{
+	module->tx_dummy_byte = dummy;
+	return spi_transceive_buffer_wait(module, NULL, rx_data, length);
+}
+
+/**
+ * \brief Writes requested amount of data to the SPI.
+ *
+ * This function will return after writing requested amount of data
+ *
+ * \note The \ref spi_select_slave function should be called before calling
+ *       this function.
+ *
+ * \param[in] module    Pointer to the software instance struct
+ * \param[in] length    length of data to be read
+ * \param[out] tx_data  Pointer to buffer to be transmitted
+ *
+ * \returns Status of the read operation.
+ * \retval STATUS_OK            If data was read
+ * \retval STATUS_ERR_IO        If no data is available
+ * \retval STATUS_ERR_OVERFLOW  If the data is overflown
+ */
+enum status_code spi_write_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	return spi_transceive_buffer_wait(module, tx_data, NULL, length);
+}
+
+/**
+ * \brief Asserting/Deasserting the slave select for the corresponding slave.
+ *
+ * This function will assert or deassert the SS of the requested slave device.
+ *
+ * \param[in] module    Pointer to the software instance struct
+ * \param[in] slave     Pointer containing slave instance
+ * \param[in] select    Bool to select the salve or deselect
+ *
+ * \returns Status of the slave select operation.
+ *
+ * \retval STATUS_OK                If SS pin is a valid one and selected/deselected
+ * \retval STATUS_ERR_INVALID_ARG   Invalid SS pin
+ */
+enum status_code spi_select_slave(
+		struct spi_module *const module,
+		struct spi_slave_inst *const slave,
+		bool select)
+{
+	uint8_t gpio_num = slave->ss_pin;
+	if(select) {
+		/* ASSERT Slave select pin */
+		gpio_pin_set_output_level(gpio_num, false);
+	} else {
+		/* DEASSERT Slave select pin */
+		gpio_pin_set_output_level(gpio_num, true);
+	}
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.h
new file mode 100644
index 0000000000..943a4a8f84
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.h
@@ -0,0 +1,625 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver for SAMB
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SPI_H_INCLUDED
+#define SPI_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_drivers_spi_group SAM Serial Peripheral Interface (SPI) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM-based microcontrollers provides 
+ * an interface for the configuration and management of the module in 
+ * its SPI mode to transfer SPI data frames. The following driver API modes 
+ * are covered by this manual:
+ *
+ * - Polled APIs
+ * \if SPI_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - SPI (Serial Peripheral Interface)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_samb_drivers_spi_prerequisites
+ * - \ref asfdoc_samb_drivers_spi_module_overview
+ * - \ref asfdoc_samb_drivers_spi_special_considerations
+ * - \ref asfdoc_samb_drivers_spi_extra_info
+ * - \ref asfdoc_samb_drivers_spi_examples
+ * - \ref asfdoc_samb_drivers_spi_api_overview
+ *
+ * \section asfdoc_samb_drivers_spi_prerequisites Prerequisites
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_drivers_spi_module_overview Module Overview
+ * \subsection asfdoc_samb_drivers_spi_bus SPI Bus Connection
+ * In \ref asfdoc_sam0_spi_connection_example "the figure below", the
+ * connection between one master and one slave is shown.
+ *
+ * \anchor asfdoc_sam0_spi_connection_example
+ * \image html spi_block_diagram.svg "SPI Block Diagram"
+ *
+ * The different lines are as follows:
+ * - \b MISO Master Input Slave Output. The line where the data is shifted
+ *   out from the slave and into the master.
+ * - \b MOSI Master Output Slave Input. The line where the data is shifted
+ *   out from the master and into the slave.
+ * - \b SCK Serial Clock. Generated by the master device.
+ * - \b SS Slave Select. To initiate a transaction, the master must pull this
+ *      line low.
+ *
+ * If the bus consists of several SPI slaves, they can be connected in parallel
+ * and the SPI master can use general I/O pins to control separate SS lines to
+ * each slave on the bus.
+ *
+ * It is also possible to connect all slaves in series. In this configuration,
+ * a common SS is provided to \c N slaves, enabling them simultaneously. The
+ * MISO from the \c N-1 slaves is connected to the MOSI on the next slave. The
+ * \c N<SUP>th</SUP> slave connects its MISO back to the master. For a
+ * complete transaction, the master must shift \c N+1 characters.
+ *
+ * \subsection asfdoc_samb_drivers_spi_chsize SPI Character Size
+ * The SPI character size is configurable to eight bits.
+ *
+ * \subsection asfdoc_samb_drivers_spi_master_mode Master Mode
+ * When configured as a master, the SS pin will be configured as an output.
+ *
+ * \subsubsection asfdoc_samb_drivers_spi_master_mode_data_transfer Data Transfer
+ * Writing a character will start the SPI clock generator, and
+ * the character is transferred to the shift register when the shift
+ * register is empty.
+ * Once this is done, a new character can be written.
+ * As each character is shifted out from the master, a character is shifted in
+ * from the slave. If the receiver is enabled, the data is moved to the receive
+ * buffer at the completion of the frame and can be read.
+ *
+ * \subsection asfdoc_samb_drivers_spi_slave_mode Slave Mode
+ * When configured as a slave, the SPI interface will remain inactive with MISO
+ * tri-stated as long as the SS pin is driven high.
+ *
+ * \subsubsection asfdoc_samb_drivers_spi_slave_mode_data_transfer_slave Data Transfer
+ * The data register can be updated at any time.
+ * As the SPI slave shift register is clocked by SCK, a minimum of three SCK
+ * cycles are needed from the time new data is written, until the character is
+ * ready to be shifted out. If the shift register has not been loaded with
+ * data, the current contents will be transmitted.
+ *
+ * If constant transmission of data is needed in SPI slave mode, the system
+ * clock should be faster than SCK.
+ *
+ * \subsection asfdoc_samb_drivers_spi_data_modes Data Modes
+ * There are four combinations of SCK phase and polarity with respect to
+ * serial data. \ref asfdoc_samb_drivers_spi_mode_table "The table below" shows the
+ * clock polarity (CPOL) and clock phase (CPHA) in the different modes.
+ * <i>Leading edge</i> is the first clock edge in a clock cycle and
+ * <i>trailing edge</i> is the last clock edge in a clock cycle.
+ *
+ * \anchor asfdoc_samb_drivers_spi_mode_table
+ * <table>
+ *   <caption>SPI Data Modes</caption>
+ *   <tr>
+ *      <th>Mode</th>
+ *      <th>CPOL</th>
+ *      <th>CPHA</th>
+ *      <th>Leading Edge</th>
+ *      <th>Trailing Edge</th>
+ *   </tr>
+ *   <tr>
+ *      <td> 0 </td>
+ *      <td> 0 </td>
+ *      <td> 0 </td>
+ *      <td> Rising, Sample </td>
+ *      <td> Falling, Setup </td>
+ *   </tr>
+ *   <tr>
+ *      <td> 1 </td>
+ *      <td> 0 </td>
+ *      <td> 1 </td>
+ *      <td> Rising, Setup </td>
+ *      <td> Falling, Sample </td>
+ *   </tr>
+ *   <tr>
+ *      <td> 2 </td>
+ *      <td> 1 </td>
+ *      <td> 0 </td>
+ *      <td> Falling, Sample </td>
+ *      <td> Rising, Setup </td>
+ *   </tr>
+ *   <tr>
+ *      <td> 3 </td>
+ *      <td> 1 </td>
+ *      <td> 1 </td>
+ *      <td> Falling, Setup </td>
+ *      <td> Rising, Sample </td>
+ *   </tr>
+ * </table>
+ *
+ * \section asfdoc_samb_drivers_spi_special_considerations Special Considerations
+ * The pin MUX settings must be configured properly, as not all settings
+ * can be used in different modes of operation.
+ *
+ * \section asfdoc_samb_drivers_spi_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_drivers_spi_extra. This includes:
+ *  - \ref asfdoc_samb_drivers_spi_extra_acronyms
+ *  - \ref asfdoc_samb_drivers_spi_extra_dependencies
+ *  - \ref asfdoc_samb_drivers_spi_extra_errata
+ *  - \ref asfdoc_samb_drivers_spi_extra_history
+ *
+ * \section asfdoc_samb_drivers_spi_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_drivers_spi_exqsg.
+ *
+ * \section asfdoc_samb_drivers_spi_api_overview API Overview
+ * @{
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <compiler.h>
+#include <conf_spi.h>
+#include <gpio.h>
+#include <system_sam_b.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (CONF_SPI_MASTER_ENABLE == false) && (CONF_SPI_SLAVE_ENABLE == false)
+#error "Not possible compile SPI driver, invalid driver configuration. Make sure that either/both CONF_SPI_MASTER_ENABLE/CONF_SPI_SLAVE_ENABLE is set to true."
+#endif
+
+#  ifndef SPI_TIMEOUT
+/** SPI timeout value */
+#  define SPI_TIMEOUT 10000
+#  endif
+
+#  ifndef PINMUX_UNUSED
+/** Unused pinmux. */
+#  define PINMUX_UNUSED 0xFFFFFFFF
+#  endif
+
+#  if SPI_CALLBACK_MODE == true
+/** Prototype for the device instance. */
+struct spi_module;
+/** Type of the callback functions */
+typedef void (*spi_callback_t)(struct spi_module *const module);
+
+/**
+ * \brief SPI Callback enum
+ *
+ * Callbacks for SPI callback driver.
+ *
+ * \note For slave mode, these callbacks will be called when a transaction
+ * is ended by the master pulling Slave Select high.
+ *
+ */
+enum spi_callback {
+	/** Callback for buffer transmitted */
+	SPI_CALLBACK_BUFFER_TRANSMITTED,
+	/** Callback for buffer received */
+	SPI_CALLBACK_BUFFER_RECEIVED,
+	/** Callback for buffers transceived */
+	SPI_CALLBACK_BUFFER_TRANSCEIVED,
+	/** Callback for error */
+	SPI_CALLBACK_ERROR,
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	SPI_CALLBACK_N,
+#  endif
+};
+
+#  if !defined(__DOXYGEN__)
+/** Prototype for the interrupt handler */
+extern struct spi_module *_spi_instances[SPI_INST_NUM];
+extern void spi_rx0_isr_handler(void);
+extern void spi_tx0_isr_handler(void);
+extern void spi_rx1_isr_handler(void);
+extern void spi_tx1_isr_handler(void);
+/**
+ * \brief SPI transfer directions
+ */
+enum _spi_direction {
+	/** Transfer direction is read. */
+	SPI_DIRECTION_READ,
+	/** Transfer direction is write. */
+	SPI_DIRECTION_WRITE,
+	/** Transfer direction is read and write. */
+	SPI_DIRECTION_BOTH,
+	/** No transfer. */
+	SPI_DIRECTION_IDLE,
+};
+#  endif
+#  endif
+
+/**
+ * \brief SPI transfer modes enum
+ *
+ * SPI transfer mode.
+ */
+enum spi_transfer_mode {
+	/** Mode 0. Leading edge: rising, sample. Trailing edge: falling, setup */
+	SPI_TRANSFER_MODE_0 = 0,
+	/** Mode 1. Leading edge: rising, setup. Trailing edge: falling, sample */
+	SPI_TRANSFER_MODE_1 = SPI_CONFIGURATION_SCK_PHASE_1,
+	/** Mode 2. Leading edge: falling, sample. Trailing edge: rising, setup */
+	SPI_TRANSFER_MODE_2 = SPI_CONFIGURATION_SCK_POLARITY_1,
+	/** Mode 3. Leading edge: falling, setup. Trailing edge: rising, sample */
+	SPI_TRANSFER_MODE_3 = SPI_CONFIGURATION_SCK_PHASE_1 | \
+						SPI_CONFIGURATION_SCK_POLARITY_1,
+};
+
+/**
+ * \brief SPI modes enum
+ *
+ * SPI mode selection.
+ */
+enum spi_mode {
+	/** Master mode */
+	SPI_MODE_MASTER         = 1,
+	/** Slave mode */
+	SPI_MODE_SLAVE          = 0,
+};
+
+/**
+ * \brief SPI data order enum
+ *
+ * SPI data order.
+ *
+ */
+enum spi_data_order {
+	/** The MSB of the data is transmitted first */
+	SPI_DATA_ORDER_MSB      = 0,
+	/** The LSB of the data is transmitted first */
+	SPI_DATA_ORDER_LSB      = SPI_CONFIGURATION_LSB_FIRST_ENABLE_1,
+};
+
+/**
+ * \brief SPI module clock input
+ *
+ * SPI module clock.
+ *
+ */
+enum spi_clock_input {
+	/** source from clock input 0 26MHz*/
+	SPI_CLK_INPUT_0 = 0,
+	/** source from clock input 1 13MHz */
+	SPI_CLK_INPUT_1,
+	/** source from clock input 2 6.5MHz*/
+	SPI_CLK_INPUT_2,
+	/** source from clock input 3 3MHz*/
+	SPI_CLK_INPUT_3,
+};
+
+/**
+ * \brief  SPI driver software device instance structure.
+ *
+ *  SPI driver software instance structure, used to retain software state
+ * information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct spi_module {
+#  if !defined(__DOXYGEN__)
+	/** Hardware module */
+	Spi *hw;
+	/** Module lock */
+	volatile uint8_t locked;
+	/** SPI mode */
+	enum spi_mode mode;
+	/** Transmit dummy data when receiving*/
+	uint8_t tx_dummy_byte;
+#if SPI_CALLBACK_MODE == true
+	/** Direction of transaction */
+	volatile enum _spi_direction dir;
+	/** Array to store callback function pointers in */
+	spi_callback_t callback[SPI_CALLBACK_N];
+	/** Buffer pointer to where the next received character will be put */
+	volatile uint8_t *rx_buffer_ptr;
+	/** Buffer pointer to where the next character will be transmitted from
+	**/
+	volatile uint8_t *tx_buffer_ptr;
+	/** Remaining characters to receive */
+	volatile uint16_t remaining_rx_buffer_length;
+	/** Remaining dummy characters to send when reading */
+	volatile uint16_t remaining_dummy_buffer_length;
+	/** Remaining characters to transmit */
+	volatile uint16_t remaining_tx_buffer_length;
+	/** Bit mask for callbacks registered */
+	uint8_t registered_callback;
+	/** Bit mask for callbacks enabled */
+	uint8_t enabled_callback;
+	/** Holds the status of the ongoing or last operation */
+	volatile enum status_code status;
+#  endif
+#  endif
+};
+
+/**
+ * \brief SPI peripheral slave instance structure
+ *
+ * SPI peripheral slave software instance structure, used to configure the
+ * correct SPI transfer mode settings for an attached slave. See
+ * \ref spi_select_slave.
+ */
+struct spi_slave_inst {
+	/** Pin to use as Slave Select */
+	uint8_t ss_pin;
+	/** Address recognition enabled in slave device */
+	uint8_t address_enabled;
+	/** Address of slave device */
+	uint8_t address;
+};
+
+/**
+ * \brief SPI peripheral slave configuration structure
+ *
+ * SPI Peripheral slave configuration structure
+ */
+struct spi_slave_inst_config {
+	/** Pin to use as Slave Select */
+	uint8_t ss_pin;
+	/** Enable address */
+	bool address_enabled;
+	/** Address of slave */
+	uint8_t address;
+};
+
+/**
+ * \brief SPI configuration structure
+ *
+ * Configuration structure for an SPI instance. This structure should be
+ * initialized by the \ref spi_get_config_defaults function before being
+ * modified by the user application.
+ */
+struct spi_config {
+	/** SPI mode */
+	enum spi_mode mode;
+	/** Data order */
+	enum spi_data_order data_order;
+	/** Transfer mode */
+	enum spi_transfer_mode transfer_mode;
+	/** clock source to use */
+	enum spi_clock_input clock_source;
+	/** clock divider value to use*/
+	uint8_t clock_divider;
+	/** SPI PAD pin number */
+	uint32_t pin_number_pad[4];
+	/** SPI PAD pinmux selection */
+	uint32_t pinmux_sel_pad[4];
+};
+
+/**
+ * \name Initialization functions
+ * @{
+ */
+
+enum status_code spi_init(
+		struct spi_module *const module,
+		Spi *const hw,
+		const struct spi_config *const config);
+
+void spi_reset(struct spi_module *const module);
+
+void spi_slave_inst_get_config_defaults(
+		struct spi_slave_inst_config *const config);
+
+void spi_get_config_defaults(struct spi_config *const config);
+
+void spi_attach_slave(
+		struct spi_slave_inst *const slave,
+		struct spi_slave_inst_config *const config);
+
+/** @} */
+
+/**
+ * \name Enable/Disable
+ * @{
+ */
+
+void spi_enable(struct spi_module *const module);
+void spi_disable(struct spi_module *const module);
+
+/** @} */
+
+/**
+ * \name Lock/Unlock
+ * @{
+ */
+
+enum status_code spi_lock(struct spi_module *const module);
+void spi_unlock(struct spi_module *const module);
+
+/** @} */
+
+
+/**
+ * \name Read/Write
+ * @{
+ */
+
+enum status_code spi_write(
+		struct spi_module *module,
+		uint8_t tx_data);
+
+enum status_code spi_write_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code spi_read(
+		struct spi_module *const module,
+		uint8_t *rx_data);
+
+enum status_code spi_read_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length,
+		uint8_t dummy);
+
+enum status_code spi_transceive_wait(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data);
+
+enum status_code spi_transceive_buffer_wait(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length);
+
+enum status_code spi_select_slave(
+		struct spi_module *const module,
+		struct spi_slave_inst *const slave,
+		bool select);
+
+/** @} */
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_samb_drivers_spi_extra Extra Information for SPI Driver
+ *
+ * \section asfdoc_samb_drivers_spi_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>SPI</td>
+ *		<td>Serial Peripheral Interface</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SCK</td>
+ *		<td>Serial Clock</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MOSI</td>
+ *		<td>Master Output Slave Input</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MISO</td>
+ *		<td>Master Input Slave Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SS</td>
+ *		<td>Slave Select</td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_samb_drivers_spi_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_drivers_spi_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ * \section asfdoc_samb_drivers_spi_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_drivers_spi_exqsg Examples for SPI Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_drivers_spi_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_samb_spi_master_basic_use
+ * - \subpage asfdoc_samb_spi_slave_basic_use
+ * \if SPI_CALLBACK_MODE
+ * - \subpage asfdoc_samb_spi_master_callback_use
+ * - \subpage asfdoc_samb_spi_slave_callback_use
+ * \endif
+ */
+ 
+ /**
+ *
+ * \page asfdoc_samb_drivers_spi_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>A</td>
+ *		<td>09/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif //SPI_H_INCLUDED
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.c
new file mode 100644
index 0000000000..238980d333
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.c
@@ -0,0 +1,764 @@
+/**
+ * \file
+ *
+ * \brief Serial Peripheral Interface Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "spi_callback.h"
+
+struct spi_module *_spi_instances[SPI_INST_NUM];
+
+/**
+ * \internal
+ *
+ * Dummy byte to send when reading in master mode.
+ */
+static uint16_t dummy_write;
+static bool flag_direction_both[SPI_INST_NUM];
+
+/**
+ * \internal
+ * Writes a character from the TX buffer to the Data register.
+ *
+ * \param[in,out]  module  Pointer to SPI software instance struct
+ */
+static void _spi_write(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	Spi *const spi_hw = module->hw;
+
+	/* Write value will be at least 8-bits long */
+	uint16_t data_to_send = *(module->tx_buffer_ptr);
+	/* Increment 8-bit pointer */
+	(module->tx_buffer_ptr)++;
+
+	/* Write the data to send*/
+	spi_hw->TRANSMIT_DATA.reg = data_to_send & SPI_TRANSMIT_DATA_MASK;
+
+	/* Decrement remaining buffer length */
+	(module->remaining_tx_buffer_length)--;
+}
+
+/**
+ * \internal
+ * Reads a character from the Data register to the RX buffer.
+ *
+ * \param[in,out]  module  Pointer to SPI software instance struct
+ */
+static void _spi_read(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	Spi *const spi_hw = module->hw;
+
+	uint16_t received_data = (spi_hw->RECEIVE_DATA.reg & SPI_RECEIVE_DATA_MASK);
+
+	/* Read value will be at least 8-bits long */
+	*(module->rx_buffer_ptr) = received_data;
+	/* Increment 8-bit pointer */
+	module->rx_buffer_ptr += 1;
+
+	/* Decrement length of the remaining buffer */
+	module->remaining_rx_buffer_length--;
+}
+
+#if CONF_SPI_MASTER_ENABLE == true
+/**
+ * \internal
+ * Writes a dummy character to the Data register.
+ *
+ * \param[in,out]  module  Pointer to SPI software instance struct
+ */
+static void _spi_write_dummy(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	Spi *const spi_hw = module->hw;
+
+	/* Write dummy byte */
+	spi_hw->TRANSMIT_DATA.reg = dummy_write;
+
+	/* Decrement remaining dummy buffer length */
+	module->remaining_dummy_buffer_length--;
+}
+#endif
+
+/**
+ * \internal
+ * Writes a dummy character from the to the Data register.
+ *
+ * \param[in,out]  module  Pointer to SPI software instance struct
+ */
+static void _spi_read_dummy(
+		struct spi_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	Spi *const spi_hw = module->hw;
+	uint16_t flush = 0;
+
+	/* Read dummy byte */
+	flush = spi_hw->RECEIVE_DATA.reg;
+	UNUSED(flush);
+
+	/* Decrement remaining dummy buffer length */
+	module->remaining_dummy_buffer_length--;
+}
+
+void spi_rx0_isr_handler(void)
+{
+	struct spi_module *module = _spi_instances[0];
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->RECEIVE_STATUS.reg;
+	flags &= module->hw->RX_INTERRUPT_MASK.reg;
+
+	if (flags & SPI_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
+		if (module->hw->RECEIVE_STATUS.reg & SPI_RECEIVE_STATUS_FIFO_OVERRUN) {
+			if (module->dir != SPI_DIRECTION_WRITE) {
+				/* Store the error code */
+				module->status = STATUS_ERR_OVERFLOW;
+
+				/* End transaction */
+				module->dir = SPI_DIRECTION_IDLE;
+
+				module->hw->RX_INTERRUPT_MASK.reg &=
+					~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
+					SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+				/* Run callback if registered and enabled */
+				if ((module->enabled_callback & (1 << SPI_CALLBACK_ERROR)) &&
+					(module->registered_callback & (1 << SPI_CALLBACK_ERROR))) {
+					module->status = STATUS_ERR_OVERFLOW;
+					module->hw->RX_INTERRUPT_MASK.reg &=
+							~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK);
+					(module->callback[SPI_CALLBACK_ERROR])(module);
+				}
+			}
+			/* Flush */
+			uint16_t flush = module->hw->RECEIVE_DATA.reg;
+			UNUSED(flush);
+		} else {
+			if (module->dir == SPI_DIRECTION_WRITE) {
+				/* Flush receive buffer when writing */
+				_spi_read_dummy(module);
+				if (module->remaining_dummy_buffer_length == 0) {
+					module->hw->RX_INTERRUPT_MASK.reg &=
+						~SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK;
+					module->status = STATUS_OK;
+					module->dir = SPI_DIRECTION_IDLE;
+					///* Run callback if registered and enabled */
+					//if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&
+						//(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED))) {
+						//(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
+					//}
+				}
+			} else {
+				_spi_read(module);
+				if (module->remaining_rx_buffer_length == 0) {
+					if(module->dir == SPI_DIRECTION_READ) {
+						if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) &&
+							(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED))) {
+							module->status = STATUS_OK;
+							module->hw->RX_INTERRUPT_MASK.reg &=
+									~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+							(module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
+						}
+					} else if (module->dir == SPI_DIRECTION_BOTH) {
+						if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
+							(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))) {
+								module->hw->RX_INTERRUPT_MASK.reg &=
+										~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+								if (flag_direction_both[0]) {
+									module->status = STATUS_OK;
+									flag_direction_both[0] = false;
+									(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+								} else {
+									flag_direction_both[0] = true;
+								}
+						}
+					}
+				}
+			}
+		}
+	}
+}
+
+void spi_tx0_isr_handler(void)
+{
+	struct spi_module *module = _spi_instances[0];
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
+	flags &= module->hw->TX_INTERRUPT_MASK.reg;
+
+	if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_1) {
+#  if CONF_SPI_MASTER_ENABLE == true
+		if ((module->mode == SPI_MODE_MASTER) &&
+			(module->dir == SPI_DIRECTION_READ)) {
+			/* Send dummy byte when reading in master mode */
+			_spi_write_dummy(module);
+			if (module->remaining_dummy_buffer_length == 0) {
+				/* Disable the Data Register Empty Interrupt */
+				module->hw->TX_INTERRUPT_MASK.reg &=
+					~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+			}
+		}
+#  endif
+		if (0
+#  if CONF_SPI_MASTER_ENABLE == true
+		|| ((module->mode == SPI_MODE_MASTER) &&
+		(module->dir != SPI_DIRECTION_READ))
+#  endif
+#  if CONF_SPI_SLAVE_ENABLE == true
+		|| ((module->mode == SPI_MODE_SLAVE) &&
+		(module->dir != SPI_DIRECTION_READ))
+#  endif
+		) {
+			_spi_write(module);
+			if (module->remaining_tx_buffer_length == 0) {
+				module->hw->TX_INTERRUPT_MASK.reg &=
+						~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+				module->hw->TX_INTERRUPT_MASK.reg |=
+						SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+			}
+		}
+	}
+	if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
+		if (module->dir == SPI_DIRECTION_WRITE) {
+			if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&
+				(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED))) {
+					module->status = STATUS_OK;
+					/* Disable interrupt */
+					module->hw->TX_INTERRUPT_MASK.reg &=
+							~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+					(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
+				}
+		} else if (module->dir == SPI_DIRECTION_BOTH) {
+			if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
+				(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))) {
+					/* Disable interrupt */
+					module->hw->TX_INTERRUPT_MASK.reg &=
+							~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+					if (flag_direction_both[0]) {
+						module->status = STATUS_OK;
+						flag_direction_both[0] = false;
+						(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+					} else {
+						flag_direction_both[0] = true;
+					}
+			}
+		}
+	}
+}
+
+void spi_rx1_isr_handler(void)
+{
+	struct spi_module *module = _spi_instances[1];
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->RECEIVE_STATUS.reg;
+	flags &= module->hw->RX_INTERRUPT_MASK.reg;
+
+	if (flags & SPI_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
+		if (module->hw->RECEIVE_STATUS.reg & SPI_RECEIVE_STATUS_FIFO_OVERRUN) {
+			if (module->dir != SPI_DIRECTION_WRITE) {
+				/* Store the error code */
+				module->status = STATUS_ERR_OVERFLOW;
+
+				/* End transaction */
+				module->dir = SPI_DIRECTION_IDLE;
+
+				module->hw->RX_INTERRUPT_MASK.reg &=
+						~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
+						SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+				/* Run callback if registered and enabled */
+				if ((module->enabled_callback & (1 << SPI_CALLBACK_ERROR)) &&
+					(module->registered_callback & (1 << SPI_CALLBACK_ERROR))) {
+					module->status = STATUS_ERR_OVERFLOW;
+					module->hw->RX_INTERRUPT_MASK.reg &=
+							~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK);
+					(module->callback[SPI_CALLBACK_ERROR])(module);
+				}
+			}
+			/* Flush */
+			uint16_t flush = module->hw->RECEIVE_DATA.reg;
+			UNUSED(flush);
+		} else {
+			if (module->dir == SPI_DIRECTION_WRITE) {
+				/* Flush receive buffer when writing */
+				_spi_read_dummy(module);
+				if (module->remaining_dummy_buffer_length == 0) {
+					module->hw->RX_INTERRUPT_MASK.reg &=
+							~SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK;
+					module->status = STATUS_OK;
+					module->dir = SPI_DIRECTION_IDLE;
+				}
+			} else {
+				_spi_read(module);
+				if (module->remaining_rx_buffer_length == 0) {
+					if(module->dir == SPI_DIRECTION_READ) {
+						if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) &&
+							(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED))) {
+							module->status = STATUS_OK;
+							module->hw->RX_INTERRUPT_MASK.reg &=
+									~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+							(module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
+						}
+					} else if (module->dir == SPI_DIRECTION_BOTH) {
+						if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
+							(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))) {
+							module->hw->RX_INTERRUPT_MASK.reg &=
+									~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+							if (flag_direction_both[1]) {
+								module->status = STATUS_OK;
+								flag_direction_both[1] = false;
+								(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+							} else {
+								flag_direction_both[1] = true;
+							}
+						}
+					}
+				}
+			}
+		}
+	}
+}
+
+void spi_tx1_isr_handler(void)
+{
+	struct spi_module *module = _spi_instances[1];
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
+	flags &= module->hw->TX_INTERRUPT_MASK.reg;
+
+	if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_1) {
+#  if CONF_SPI_MASTER_ENABLE == true
+		if ((module->mode == SPI_MODE_MASTER) &&
+		(module->dir == SPI_DIRECTION_READ)) {
+			/* Send dummy byte when reading in master mode */
+			_spi_write_dummy(module);
+			if (module->remaining_dummy_buffer_length == 0) {
+				/* Disable the Data Register Empty Interrupt */
+				module->hw->TX_INTERRUPT_MASK.reg &=
+				~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+			}
+		}
+#  endif
+		if (0
+#  if CONF_SPI_MASTER_ENABLE == true
+		|| ((module->mode == SPI_MODE_MASTER) &&
+		(module->dir != SPI_DIRECTION_READ))
+#  endif
+#  if CONF_SPI_SLAVE_ENABLE == true
+		|| ((module->mode == SPI_MODE_SLAVE) &&
+		(module->dir != SPI_DIRECTION_READ))
+#  endif
+		) {
+			_spi_write(module);
+			if (module->remaining_tx_buffer_length == 0) {
+				module->hw->TX_INTERRUPT_MASK.reg &=
+						~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+				module->hw->TX_INTERRUPT_MASK.reg |=
+				SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+			}
+		}
+	}
+	if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
+		if (module->dir == SPI_DIRECTION_WRITE) {
+			if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&
+			(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED))) {
+				module->status = STATUS_OK;
+				/* Disable interrupt */
+				module->hw->TX_INTERRUPT_MASK.reg &=
+						~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+				(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
+			}
+		} else if (module->dir == SPI_DIRECTION_BOTH) {
+			if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
+				(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))) {
+				/* Disable interrupt */
+				module->hw->TX_INTERRUPT_MASK.reg &=
+						~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+				if (flag_direction_both[1]) {
+					module->status = STATUS_OK;
+					flag_direction_both[1] = false;
+					(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+				} else {
+					flag_direction_both[1] = true;
+				}
+			}
+		}
+	}
+}
+
+/**
+ * \brief Registers a SPI callback function
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref spi_enable_callback, in order
+ *       for the interrupt handler to call it when the conditions for the
+ *       callback type are met.
+ *
+ * \param[in]  module         Pointer to SPI software instance struct
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void spi_register_callback(
+		struct spi_module *const module,
+		spi_callback_t callback_func,
+		enum spi_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a SPI callback function
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in] module         Pointer to SPI software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void spi_unregister_callback(
+		struct spi_module *const module,
+		enum spi_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref spi_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in]  module         Pointer to SPI software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+void spi_enable_callback(struct spi_module *const module,
+		enum spi_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback function registered by the \ref spi_register_callback.
+ * The callback function will not be called from the interrupt handler.
+ *
+ * \param[in]  module         Pointer to SPI software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+void spi_disable_callback(struct spi_module *const module,
+		enum spi_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal
+ * Starts write of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+static void _spi_write_buffer(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(tx_data);
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+	module->remaining_dummy_buffer_length = length;
+	module->tx_buffer_ptr = tx_data;
+	module->status = STATUS_BUSY;
+
+	module->dir = SPI_DIRECTION_WRITE;
+
+	/* Get a pointer to the hardware module instance */
+	Spi *const hw = module->hw;
+
+	hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+}
+
+/**
+ * \internal
+ * Setup SPI to read a buffer with a given length
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  length   Length of data buffer
+ *
+ */
+static void _spi_read_buffer(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(rx_data);
+
+	/* Set length for the buffer and the pointer, and let
+	 * the interrupt handler do the rest */
+	module->remaining_rx_buffer_length = length;
+	module->remaining_dummy_buffer_length = length;
+	module->rx_buffer_ptr = rx_data;
+	module->status = STATUS_BUSY;
+
+	module->dir = SPI_DIRECTION_READ;
+
+	/* Get a pointer to the hardware module instance */
+	Spi *const hw = module->hw;
+
+	hw->RX_INTERRUPT_MASK.reg = SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+
+#if CONF_SPI_MASTER_ENABLE == true
+	hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+#endif
+}
+
+/**
+ * \internal
+ * Starts transceive of buffers with a given length
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+static void _spi_transceive_buffer(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(tx_data);
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+	module->remaining_rx_buffer_length = length;
+	module->rx_buffer_ptr = rx_data;
+	module->tx_buffer_ptr = tx_data;
+	module->status = STATUS_BUSY;
+
+	module->dir = SPI_DIRECTION_BOTH;
+
+	if (module->hw == SPI0) {
+		flag_direction_both[0] = false;
+	} else if (module->hw == SPI1) {
+		flag_direction_both[1] = false;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	Spi *const hw = module->hw;
+
+	/* Enable the Data Register Empty and RX Complete Interrupt */
+	hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+	hw->RX_INTERRUPT_MASK.reg = SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+}
+
+/**
+ * \brief Asynchronous buffer write
+ *
+ * Sets up the driver to write to the SPI from a given buffer. If registered
+ * and enabled, a callback function will be called when the write is finished.
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[out] tx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \returns Status of the write request operation.
+ * \retval STATUS_OK               If the operation completed successfully
+ * \retval STATUS_ERR_BUSY         If the SPI was already busy with a write
+ *                                 operation
+ * \retval STATUS_ERR_INVALID_ARG  If requested write length was zero
+ */
+enum status_code spi_write_buffer_job(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(tx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
+	if (module->status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Issue internal write */
+	_spi_write_buffer(module, tx_data, length);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Asynchronous buffer read
+ *
+ * Sets up the driver to read from the SPI to a given buffer. If registered
+ * and enabled, a callback function will be called when the read is finished.
+ *
+ * \note If address matching is enabled for the slave, the first character
+ *       received and placed in the RX buffer will be the address.
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ * \param[in]  dummy    Dummy character to send when reading in master mode
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK               If the operation completed successfully
+ * \retval  STATUS_ERR_BUSY         If the SPI was already busy with a read
+ *                                  operation
+ * \retval  STATUS_ERR_DENIED       If the receiver is not enabled
+ * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
+ */
+enum status_code spi_read_buffer_job(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length,
+		uint16_t dummy)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
+	if (module->status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	dummy_write = dummy;
+	/* Issue internal read */
+	_spi_read_buffer(module, rx_data, length);
+	return STATUS_OK;
+}
+
+/**
+ * \brief Asynchronous buffer write and read
+ *
+ * Sets up the driver to write and read to and from given buffers. If registered
+ * and enabled, a callback function will be called when the transfer is finished.
+ *
+ * \note If address matching is enabled for the slave, the first character
+ *       received and placed in the RX buffer will be the address.
+ *
+ * \param[in]  module   Pointer to SPI software instance struct
+ * \param[in] tx_data   Pointer to data buffer to send
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK               If the operation completed successfully
+ * \retval  STATUS_ERR_BUSY         If the SPI was already busy with a read
+ *                                  operation
+ * \retval  STATUS_ERR_DENIED       If the receiver is not enabled
+ * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
+ */
+enum status_code spi_transceive_buffer_job(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
+	if (module->status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Issue internal transceive */
+	_spi_transceive_buffer(module, tx_data, rx_data, length);
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.h
new file mode 100644
index 0000000000..82dbb339fc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.h
@@ -0,0 +1,110 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SPI_CALLBACK_H_INCLUDED
+#define SPI_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_samb_drivers_spi_group
+ *
+ * @{
+ */
+
+#include "spi.h"
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void spi_register_callback(
+		struct spi_module *const module,
+		spi_callback_t callback_func,
+		enum spi_callback callback_type);
+
+void spi_unregister_callback(
+		struct spi_module *module,
+		enum spi_callback callback_type);
+
+void spi_enable_callback(
+		struct spi_module *const module,
+		enum spi_callback callback_type);
+
+void spi_disable_callback(
+		struct spi_module *const module,
+		enum spi_callback callback_type);
+/** @} */
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code spi_write_buffer_job(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+enum status_code spi_read_buffer_job(
+		struct spi_module *const module,
+		uint8_t *rx_data,
+		uint16_t length,
+		uint16_t dummy);
+enum status_code spi_transceive_buffer_job(
+		struct spi_module *const module,
+		uint8_t *tx_data,
+		uint8_t *rx_data,
+		uint16_t length);
+/** @} */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif	//SPI_H_INCLUDED
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.c
new file mode 100644
index 0000000000..0524e2e1ae
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.c
@@ -0,0 +1,477 @@
+/**
+ * \file
+ *
+ * \brief SAM SPI Flash Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "spi_flash.h"
+
+/**
+ *  \brief SPI flash write enable.
+ *
+ * Enable SPI flash write
+ */
+static void spi_flash_write_enable(void)
+{
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0);
+	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_WRITE_ENABLE;
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = SPI_FLASH_DMA_START_ADDRESS_RESETVALUE;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
+		/* Wait for current flash transaction done. */
+	}
+}
+
+/**
+ *  \brief SPI flash write disable.
+ *
+ * Disable SPI flash write
+ */
+static void spi_flash_write_disable(void)
+{
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0);
+	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_WRITE_DISABLE;
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = SPI_FLASH_DMA_START_ADDRESS_MASK;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
+		/* Wait for current flash transaction done. */
+	}
+}
+
+/**
+ *  \brief SPI flash read status register.
+ *
+ * Read SPI flash status
+ *
+ * \return Status register value.
+ */
+static uint8_t spi_flash_read_status_reg(void)
+{
+	volatile uint32_t status_value;
+
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x01);
+	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_READ_STATUS;
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = (uint32_t)&status_value;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
+		/* Wait for current flash transaction done. */
+	}
+
+	return (status_value & 0xFF);
+}
+
+/**
+ * \brief Program SPI Flash page
+ *
+ * Program SPI Flash page
+ *
+ * \param[in]  memory_addr    Start address of memory
+ * \param[in]  flash_addr     Start address of the spi flash
+ * \param[in]  size           Number of bytes to be programmed to flash
+ */
+static void spi_flash_page_program(uint32_t flash_addr, uint32_t memory_addr, uint16_t size)
+{
+	unsigned char cmd[8];
+
+	spi_flash_write_enable();
+
+	cmd[0] = SPI_FLASH_CMD_PAGE_PROGRAM;
+	cmd[1] = (unsigned char) (flash_addr >> 16);
+	cmd[2] = (unsigned char) (flash_addr >> 8);
+	cmd[3] = (unsigned char) (flash_addr);
+
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
+	SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_PRO;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = memory_addr;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x04) | \
+			SPI_FLASH_TRANSACTION_CTRL_WDATA_COUNT(size);
+
+	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
+		/* Wait for current flash transaction done. */
+	}
+
+	/* add additional read_status_reg before the while this gives the flash
+	 * memory time to update the registers.
+	 */
+	for(uint16_t i = 0; i < 0xFFFF; i++) {
+		/* Waiting... */
+	}
+	//spi_flash_read_status_reg();
+	while(spi_flash_read_status_reg() & 0x01);
+	spi_flash_write_disable();
+}
+
+/**
+ * \brief Initializes the SPI Flash module
+ *
+ * Initializes the SPI Flash module
+ */
+void spi_flash_init(void)
+{
+	/* PINMUX init */
+	LPMCU_MISC_REGS0->PINMUX_SEL_3.reg = \
+							LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_0_SEL_SPI_FLASH0_SCK | \ 
+							LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_1_SEL_SPI_FLASH0_TXD | \
+							LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_2_SEL_SPI_FLASH0_SSN | \
+							LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_3_SEL_SPI_FLASH0_RXD;
+
+	SPI_FLASH0->MODE_CTRL.reg = SPI_FLASH_MODE_CTRL_RESETVALUE;
+	spi_flash_leave_low_power_mode();
+}
+
+/**
+ * \brief Read SPI Flash Chip ID
+ *
+ * Reads SPI Flash Chip ID
+ */
+uint32_t spi_flash_rdid(void)
+{
+	volatile uint32_t register_value;
+
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x04);
+	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_READ_ID;
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = (uint32_t)&register_value;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
+		/* Wait for current flash transaction done. */
+	}
+
+	return (register_value);
+}
+
+/**
+ * \brief Read SPI Flash memory
+ *
+ * Reads SPI Flash memory with up to page size (256 bytes) length
+ * \param[in]  read_buf    Pointer to buffer to read into
+ * \param[in]  flash_addr  Flash memory address to read from
+ * \param[in]  size        Data length to be read, must be less than or equal to FLASH_PAGE_SIZE
+ */
+void spi_flash_read(uint8_t *read_buf, uint32_t flash_addr, uint32_t size)
+{
+	uint8_t   cmd[8] = {0, };
+	uint32_t  memory_addr;
+	uint32_t  i=0;
+	uint8_t   *data = read_buf;
+
+	/* Get the destination buffer Address. */
+	if((flash_addr + size) > FLASH_MEMORY_SIZE) {
+		for(i=0; i < size; i++) {
+			data[i] = 0;
+		}
+	}
+
+	memory_addr = (unsigned long)read_buf;
+
+	/* Perform read operation. */
+	cmd[0] = SPI_FLASH_CMD_READ_HIGH_SPEED;
+	cmd[1] = (unsigned char) (flash_addr >> 16);
+	cmd[2] = (unsigned char) (flash_addr >> 8);
+	cmd[3] = (unsigned char) (flash_addr);
+	cmd[4] = 0xA5;
+
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(size);
+	SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
+	SPI_FLASH0->CMD_BUFFER1.reg = cmd[4];
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_READ;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = memory_addr;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x05);
+
+	for (i = 0; i < 0xFF; i++) {
+		/* Waiting...*/
+	}
+	while ((SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) && \
+			(spi_flash_read_status_reg() & 0x01)){
+		/* Wait for current flash transaction done. */
+	}
+}
+
+/**
+ * \brief Write SPI Flash memory
+ *
+ * Writes SPI Flash memory with up to page size (256 bytes) length
+ * \param[in]  write_buf    Pointer to buffer to write from
+ * \param[in]  flash_addr   Flash memory address to write to
+ * \param[in]  size         Data length to be written, must be less than or
+ *                          equal to FLASH_PAGE_SIZE
+ */
+int8_t spi_flash_write(void *write_buf, uint32_t flash_addr, uint32_t size)
+{
+	int8_t      ret = -1;
+	uint32_t    write_size;
+	uint32_t    offset;
+	uint32_t    memory_addr;
+
+	for (uint32_t i = 0; i < 0x1FFFF; i++) {
+		/* Waiting...*/
+	}
+	if((write_buf != NULL) && (size != 0)) {
+		/* Ensure the write size does not exceed the flash limit. */
+		if((flash_addr + size) <= FLASH_MEMORY_SIZE) {
+			/* Get the destination buffer Address. */
+			memory_addr = (unsigned long)write_buf;
+			/* Perform read operation. */
+			offset = flash_addr % FLASH_PAGE_SIZE;
+
+			/* First part of data in the address page. */
+			if (offset) {
+				write_size = FLASH_PAGE_SIZE - offset;
+				spi_flash_page_program(flash_addr, memory_addr, min(size, write_size));
+				if (size < write_size) {
+					ret = 0;
+					goto EXIT;
+				}
+				memory_addr += write_size;
+				flash_addr += write_size;
+				size -= write_size;
+			}
+			do {
+				write_size = min(size, FLASH_PAGE_SIZE);
+
+				/* Write complete page or the remaining data. */
+				spi_flash_page_program(flash_addr, memory_addr, write_size);
+				memory_addr += write_size;
+				flash_addr += write_size;
+				size -= write_size;
+			} while (size > 0);
+			ret = 0;
+		}
+	}
+	EXIT:
+	return ret;
+}
+
+/**
+ * \brief Erase SPI Flash sector
+ *
+ * Erases SPI Flash Sector
+ * \param[in]  flash_addr  Flash memory address within the sector to erase
+ */
+void spi_flash_sector_erase(uint32_t flash_addr)
+{
+	uint8_t cmd[8] = {0,};
+	uint32_t  i=0;
+
+	cmd[0] = SPI_FLASH_CMD_SECTOR_ERASE;
+	cmd[1] = (char)(flash_addr >> 16);
+	cmd[2] = (char)(flash_addr >> 8);
+	cmd[3] = (char)(flash_addr);
+
+	spi_flash_write_enable();
+	spi_flash_read_status_reg();
+
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
+	SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_PRO;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x04);
+
+	for (i = 0; i < 0xFF; i++) {
+		/* Waiting...*/
+	}
+
+	while ((SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) && \
+			(spi_flash_read_status_reg() & 0x01)){
+		/* Wait for current flash transaction done. */
+	}
+}
+
+/**
+ * \brief Erase SPI Flash sector
+ *
+ * Erases SPI Flash Sector
+ * \param[in]  start_offset   Start address of the spi flash
+ * \param[in]  size           Size of the spi flash
+ *
+ * \retval 1    Address over spi flash memory size
+ * \retval 0    Operation complete
+ */
+unsigned char spi_flash_erase(uint32_t start_offset, uint32_t size)
+{
+    unsigned long end_offset = start_offset + size;
+
+
+    /* Check address overflow */
+    if (end_offset > FLASH_MEMORY_SIZE) {
+        return 1;
+    }
+
+    /* Align to previous sector boundary */
+    start_offset = start_offset & FLASH_SECT_MASK;
+
+    /* Erase next sectors */
+    spi_flash_write_enable();
+    while(start_offset < end_offset) {
+			spi_flash_sector_erase(start_offset);
+			while(spi_flash_read_status_reg() & 0x01) {
+				/* Waiting. */
+			}
+			start_offset += FLASH_SECTOR_SIZE;
+    }
+
+	spi_flash_write_disable();
+
+    return 0;
+}
+
+/**
+ * \brief Enter SPI Flash low power mode
+ *
+ * Enter SPI Flash low power mode
+ */
+void spi_flash_enter_low_power_mode(void)
+{
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
+	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_ENTER_LOW_POWER;
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
+		/* Wait for current flash transaction done. */
+	}
+}
+
+/**
+ * \brief Exit SPI Flash Low power mode
+ *
+ * Exit SPI Flash Low power mode
+ */
+void spi_flash_leave_low_power_mode(void)
+{
+	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
+	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_LEAVE_LOW_POWER;
+	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+	SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
+
+	SPI_FLASH0->TRANSACTION_CTRL.reg = \
+			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
+		/* Wait for current flash transaction done. */
+	}
+}
+
+/**
+ * \brief Initializes the SPI Flash module
+ */
+void spi_flash_clock_init(void)
+{	
+	/* Reset SPI_Flash */
+	system_peripheral_reset(PERIPHERAL_SPI_FLASH);
+	system_peripheral_reset(PERIPHERAL_SPI_FLASH_IF);
+	/* SPI_Flash core clock enable */
+	system_clock_peripheral_enable(PERIPHERAL_SPI_FLASH);
+	/* change clock speed */
+	system_clock_peripheral_freq_config(PERIPHERAL_SPI_FLASH, CLOCK_FREQ_13_MHZ);
+}
+
+/**
+ * \brief Turns off the supply to SPI_Flash Core
+ *
+ * This functions turns off the supply to SPI_Flash core.
+ * Since SPI_Flash won't be used on every wakeup it is safe to disable
+ * the power to SPI_Flash core and enable it when required.
+ *
+ */
+void spi_flash_turn_off(void)
+{
+	LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~LPMCU_MISC_REGS_PULL_ENABLE_LP_SIP__Msk;
+	
+	LPMCU_MISC_REGS0->SPIFLASH_VDDIO_CTRL.reg = 0x0;
+}
+
+/**
+ * \brief Turns on the supply to SPI_Flash Core
+ *
+ * This functions turns on the supply to SPI_Flash core.
+ *
+ */
+void spi_flash_turn_on(void)
+{
+	LPMCU_MISC_REGS0->PULL_ENABLE.reg |= LPMCU_MISC_REGS_PULL_ENABLE_LP_SIP__Msk;
+	
+	LPMCU_MISC_REGS0->SPIFLASH_VDDIO_CTRL.reg = LPMCU_MISC_REGS_SPIFLASH_VDDIO_CTRL_ENABLE;
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.h
new file mode 100644
index 0000000000..7b2258583e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.h
@@ -0,0 +1,293 @@
+/**
+ * \file
+ *
+ * \brief SAM SPI Flash Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SPI_FLASH_H_INCLUDED
+#define SPI_FLASH_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_spi_flash_group SAM SPI Flash Driver (SPI Flash)
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's SPI Flash functionality. The
+ * following driver API modes are covered by this manual:
+ *
+ * The following peripherals are used by this module:
+ *  - SPI Flash (SPI Flash Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_spi_flash_prerequisites
+ *  - \ref asfdoc_samb_spi_flash_module_overview
+ *  - \ref asfdoc_samb_spi_flash_special_considerations
+ *  - \ref asfdoc_samb_spi_flash_extra_info
+ *  - \ref asfdoc_samb_spi_flash_examples
+ *  - \ref asfdoc_samb_spi_flash_api_overview
+ *
+ *
+ * \section asfdoc_samb_spi_flash_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_spi_flash_module_overview Module Overview
+ * The AHB SPI-Flash Controller is used to access the internal stacked FLASH
+ * memory to access various instruction/data code needed for storing
+ * application code, code patches, and OTA images.
+ *
+ * The table above describes the stacked SPI Flash memory organization and layout.
+ * Boot up, the ROM boot loader starts loading different sections of from the
+ * flash by first reading the flash header to figure out the locations and sizes
+ * for different sections, then copying the sections one by one into their
+ * respective memory regions. The header and all sections have CRC calculated
+ * for integrity check. If CRC fails, section will not be loaded into RAM.
+ *
+ * <table>
+ *  <tr>
+ *    <th>SPI flash memory address</th>
+ *    <th>Function description</th>
+ *  </tr>
+ *  <tr>
+ *    <td>0x0000 ~ 0x0FFF</td>
+ *    <td>Flash Header</td>
+ *  </tr>
+ *  <tr>
+ *    <td>0x1000 ~ End of patch section (according to patch size)</td>
+ *    <td>Patch image section</td>
+ *  </tr>
+ *  <tr>
+ *    <td>User App Start Section ~ User App End Section <=254KB</td>
+ *    <td>USER APP</td>
+ *  </tr>
+ *  <tr>
+ *    <td>NVDS 4KB</td>
+ *    <td>NVDS</td>
+ *  </tr>
+ * </table>
+ *
+ * \section asfdoc_samb_spi_flash_special_considerations Special Considerations
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_samb_spi_flash_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_spi_flash_extra. This includes:
+ *  - \ref asfdoc_samb_spi_flash_extra_acronyms
+ *  - \ref asfdoc_samb_spi_flash_extra_dependencies
+ *  - \ref asfdoc_samb_spi_flash_extra_errata
+ *  - \ref asfdoc_samb_spi_flash_extra_history
+ *
+ *
+ * \section asfdoc_samb_spi_flash_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_spi_flash_exqsg.
+ *
+ *
+ * \section asfdoc_samb_spi_flash_api_overview API Overview
+ * @{
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <compiler.h>
+#include <gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Flash memory size: 256 KBytes */
+#define FLASH_MEMORY_SIZE       0x40000
+
+/** Accessible NVDS area start spi flash address */
+#define FLASH_NVDS_START_ADDRESS  0x3F000
+
+/** Accessible NVDS area spi flash size */
+#define FLASH_NVDS_SIZE         0x1000
+
+/** Flash memory sector size 4 KBytes */
+#define FLASH_SECTOR_SIZE       0x1000
+
+/** Flash memory page size: 256 Bytes */
+#define FLASH_PAGE_SIZE         0x100
+
+/** Flash sector Mask */
+#define FLASH_SECT_MASK         0xFFF000
+
+/** Flash page mask */
+#define FLASH_PAGE_MASK         0xFFFF00
+
+/** SPI flash write enable */
+#define SPI_FLASH_CMD_WRITE_ENABLE      0x06
+/** SPI flash write disable */
+#define SPI_FLASH_CMD_WRITE_DISABLE     0x04
+/** SPI flash read identification */
+#define SPI_FLASH_CMD_READ_ID           0x9F
+/** SPI flash read status register */
+#define SPI_FLASH_CMD_READ_STATUS       0x05
+/** SPI flash write status register */
+#define SPI_FLASH_CMD_WRITE_STATUS      0x01
+/** SPI flash read data bytes */
+#define SPI_FLASH_CMD_READ_DATA         0x03
+/** SPI flash read data bytes at higher speed */
+#define SPI_FLASH_CMD_READ_HIGH_SPEED   0x0B
+/** SPI flash page program */
+#define SPI_FLASH_CMD_PAGE_PROGRAM      0x02
+/** SPI flash sector erase */
+#define SPI_FLASH_CMD_SECTOR_ERASE      0x20
+/** SPI flash bulk erase */
+#define SPI_FLASH_CMD_BULK_ERASE        0xC7
+/** SPI flash deep power-down */
+#define SPI_FLASH_CMD_ENTER_LOW_POWER   0xB9
+/** SPI flash release from deep power down */
+#define SPI_FLASH_CMD_LEAVE_LOW_POWER   0xAB
+
+/** SPI flash direction: send command */
+#define SPI_FLASH_DIRECTION_CMD         0x01
+/** SPI flash direction: program or erase */
+#define SPI_FLASH_DIRECTION_PRO         0x0F
+/** SPI flash direction: read data */
+#define SPI_FLASH_DIRECTION_READ        0x1F
+
+/** \name SPI flash callback config
+ * @{
+ */
+void spi_flash_init(void) ;
+/** @}*/
+
+/** \name SPI flash read/write/erase operation
+ * @{
+ */
+uint32_t spi_flash_rdid(void);
+void spi_flash_read(uint8_t *read_buf, uint32_t flash_addr, uint32_t size);
+int8_t spi_flash_write(void *write_buf, uint32_t flash_addr, uint32_t size);
+void spi_flash_sector_erase(uint32_t flash_addr);
+uint8_t spi_flash_erase(uint32_t start_offset, uint32_t size);
+void spi_flash_enter_low_power_mode(void);
+void spi_flash_leave_low_power_mode(void);
+void spi_flash_clock_init(void);
+void spi_flash_turn_off(void);
+void spi_flash_turn_on(void);
+/** @}*/
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \page asfdoc_samb_spi_flash_extra Extra Information for SPI Flash Driver
+ *
+ * \section asfdoc_samb_spi_flash_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>SPI Flash</td>
+ *		<td>Serial Peripheral Interface Flash</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_samb_spi_flash_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_spi_flash_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_spi_flash_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_spi_flash_exqsg Examples for SPI Flash Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_spi_flash_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_spi_flash_basic_use_case
+ *
+ * \page asfdoc_samb_spi_flash_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>A</td>
+ *		<td>09/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock.h
new file mode 100644
index 0000000000..0d350428d5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock.h
@@ -0,0 +1,53 @@
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_CLOCK_H_INCLUDED
+#define SYSTEM_CLOCK_H_INCLUDED
+
+#include <compiler.h>
+#include <gclk.h>
+#include <clock_feature.h>
+
+#endif /* SYSTEM_CLOCK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock.c
new file mode 100644
index 0000000000..fdb392ef16
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock.c
@@ -0,0 +1,906 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 Clock Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+#include <conf_clocks.h>
+#include <system.h>
+
+/**
+ * \internal
+ * \brief DFLL-specific data container.
+ */
+struct _system_clock_dfll_config {
+	uint32_t control;
+	uint32_t val;
+	uint32_t mul;
+};
+
+/**
+ * \internal
+ * \brief XOSC-specific data container.
+ */
+struct _system_clock_xosc_config {
+	uint32_t frequency;
+};
+
+/**
+ * \internal
+ * \brief System clock module data container.
+ */
+struct _system_clock_module {
+	volatile struct _system_clock_dfll_config dfll;
+	volatile struct _system_clock_xosc_config xosc;
+	volatile struct _system_clock_xosc_config xosc32k;
+};
+
+/**
+ * \internal
+ * \brief Internal module instance to cache configuration values.
+ */
+static struct _system_clock_module _system_clock_inst = {
+		.dfll = {
+			.control     = 0,
+			.val     = 0,
+			.mul     = 0,
+		},
+		.xosc = {
+			.frequency   = 0,
+		},
+		.xosc32k = {
+			.frequency   = 0,
+		},
+	};
+
+/**
+ * \internal
+ * \brief Wait for sync to the DFLL control registers.
+ */
+static inline void _system_dfll_wait_for_sync(void)
+{
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
+		/* Wait for DFLL sync */
+	}
+}
+
+/**
+ * \internal
+ * \brief Wait for sync to the OSC32K control registers.
+ */
+static inline void _system_osc32k_wait_for_sync(void)
+{
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
+		/* Wait for OSC32K sync */
+	}
+}
+
+static inline void _system_clock_source_dfll_set_config_errata_9905(void)
+{
+
+	/* Disable ONDEMAND mode while writing configurations */
+	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND;
+	_system_dfll_wait_for_sync();
+
+	SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
+	SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
+
+	/* Write full configuration to DFLL control register */
+	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+}
+
+/**
+ * \brief Retrieve the frequency of a clock source.
+ *
+ * Determines the current operating frequency of a given clock source.
+ *
+ * \param[in] clock_source  Clock source to get the frequency
+ *
+ * \returns Frequency of the given clock source, in Hz.
+ */
+uint32_t system_clock_source_get_hz(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		return _system_clock_inst.xosc.frequency;
+
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		return 32768UL;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		return 32768UL;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		return _system_clock_inst.xosc32k.frequency;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+
+		/* Check if the DFLL has been configured */
+		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+			return 0;
+
+		/* Make sure that the DFLL module is ready */
+		_system_dfll_wait_for_sync();
+
+		/* Check if operating in closed loop mode */
+		if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) {
+			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+					(_system_clock_inst.dfll.mul & 0xffff);
+		}
+
+		return 48000000UL;
+
+	default:
+		return 0;
+	}
+}
+
+/**
+ * \brief Configure the internal OSC8M oscillator clock source.
+ *
+ * Configures the 8MHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config  OSC8M configuration structure containing the new config
+ */
+void system_clock_source_osc8m_set_config(
+		struct system_clock_source_osc8m_config *const config)
+{
+	SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
+
+	/* Use temporary struct to reduce register access */
+	temp.bit.PRESC    = config->prescaler;
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+
+	SYSCTRL->OSC8M = temp;
+}
+
+/**
+ * \brief Configure the internal OSC32K oscillator clock source.
+ *
+ * Configures the 32KHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config  OSC32K configuration structure containing the new config
+ */
+void system_clock_source_osc32k_set_config(
+		struct system_clock_source_osc32k_config *const config)
+{
+	SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
+
+	/* Update settings via a temporary struct to reduce register access */
+	temp.bit.EN1K     = config->enable_1khz_output;
+	temp.bit.EN32K    = config->enable_32khz_output;
+	temp.bit.STARTUP  = config->startup_time;
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+	temp.bit.WRTLOCK  = config->write_once;
+
+	SYSCTRL->OSC32K  = temp;
+}
+
+/**
+ * \brief Configure the external oscillator clock source.
+ *
+ * Configures the external oscillator clock source with the given configuration
+ * settings.
+ *
+ * \param[in] config  External oscillator configuration structure containing
+ *                    the new config
+ */
+void system_clock_source_xosc_set_config(
+		struct system_clock_source_xosc_config *const config)
+{
+	SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
+
+	temp.bit.STARTUP = config->startup_time;
+
+	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+		temp.bit.XTALEN = 1;
+	} else {
+		temp.bit.XTALEN = 0;
+	}
+
+	temp.bit.AMPGC = config->auto_gain_control;
+
+	/* Set gain if automatic gain control is not selected */
+	if (!config->auto_gain_control) {
+		if (config->frequency <= 2000000) {
+			temp.bit.GAIN = 0;
+		} else if (config->frequency <= 4000000) {
+			temp.bit.GAIN = 1;
+		} else if (config->frequency <= 8000000) {
+			temp.bit.GAIN = 2;
+		} else if (config->frequency <= 16000000) {
+			temp.bit.GAIN = 3;
+		} else if (config->frequency <= 32000000) {
+			temp.bit.GAIN = 4;
+		}
+
+	}
+
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+
+	/* Store XOSC frequency for internal use */
+	_system_clock_inst.xosc.frequency = config->frequency;
+
+	SYSCTRL->XOSC = temp;
+}
+
+/**
+ * \brief Configure the XOSC32K external 32KHz oscillator clock source.
+ *
+ * Configures the external 32KHz oscillator clock source with the given
+ * configuration settings.
+ *
+ * \param[in] config  XOSC32K configuration structure containing the new config
+ */
+void system_clock_source_xosc32k_set_config(
+		struct system_clock_source_xosc32k_config *const config)
+{
+	SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
+
+	temp.bit.STARTUP = config->startup_time;
+
+	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+		temp.bit.XTALEN = 1;
+	} else {
+		temp.bit.XTALEN = 0;
+	}
+
+	temp.bit.AAMPEN = config->auto_gain_control;
+	temp.bit.EN1K = config->enable_1khz_output;
+	temp.bit.EN32K = config->enable_32khz_output;
+
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+	temp.bit.WRTLOCK  = config->write_once;
+
+	/* Cache the new frequency in case the user needs to check the current
+	 * operating frequency later */
+	_system_clock_inst.xosc32k.frequency = config->frequency;
+
+	SYSCTRL->XOSC32K = temp;
+}
+///@cond INTERNAL
+
+/**
+ * \internal
+ * \name Header file macro copies for runtime support of different revisions
+ *
+ * These macroes are copied from the header file to be able to support both new and old register layout runtime.
+ *
+ * @{
+ */
+#define _SYSTEM_OLD_DFLLVAL_FINE_Pos    0
+#define _SYSTEM_OLD_DFLLVAL_FINE_Msk    (0xFFu << _SYSTEM_OLD_DFLLVAL_FINE_Pos)
+#define _SYSTEM_OLD_DFLLVAL_FINE(value) ((_SYSTEM_OLD_DFLLVAL_FINE_Msk & ((value) << _SYSTEM_OLD_DFLLVAL_FINE_Pos)))
+
+#define _SYSTEM_OLD_DFLLVAL_COARSE_Pos  8
+#define _SYSTEM_OLD_DFLLVAL_COARSE_Msk  (0x1Fu << _SYSTEM_OLD_DFLLVAL_COARSE_Pos)
+#define _SYSTEM_OLD_DFLLVAL_COARSE(value) ((_SYSTEM_OLD_DFLLVAL_COARSE_Msk & ((value) << _SYSTEM_OLD_DFLLVAL_COARSE_Pos)))
+
+#define _SYSTEM_NEW_DFLLVAL_FINE_Pos    0
+#define _SYSTEM_NEW_DFLLVAL_FINE_Msk    (0x3FFu << _SYSTEM_NEW_DFLLVAL_FINE_Pos)
+#define _SYSTEM_NEW_DFLLVAL_FINE(value) ((_SYSTEM_NEW_DFLLVAL_FINE_Msk & ((value) << _SYSTEM_NEW_DFLLVAL_FINE_Pos)))
+
+#define _SYSTEM_NEW_DFLLVAL_COARSE_Pos  10
+#define _SYSTEM_NEW_DFLLVAL_COARSE_Msk  (0x3Fu << _SYSTEM_NEW_DFLLVAL_COARSE_Pos)
+#define _SYSTEM_NEW_DFLLVAL_COARSE(value) ((_SYSTEM_NEW_DFLLVAL_COARSE_Msk & ((value) << _SYSTEM_NEW_DFLLVAL_COARSE_Pos)))
+
+#define _SYSTEM_OLD_DFLLMUL_FSTEP_Pos   16
+#define _SYSTEM_OLD_DFLLMUL_FSTEP_Msk   (0xFFu << _SYSTEM_OLD_DFLLMUL_FSTEP_Pos)
+#define _SYSTEM_OLD_DFLLMUL_FSTEP(value) ((_SYSTEM_OLD_DFLLMUL_FSTEP_Msk & ((value) << _SYSTEM_OLD_DFLLMUL_FSTEP_Pos)))
+
+#define _SYSTEM_OLD_DFLLMUL_CSTEP_Pos   24
+#define _SYSTEM_OLD_DFLLMUL_CSTEP_Msk   (0x1Fu << _SYSTEM_OLD_DFLLMUL_CSTEP_Pos)
+#define _SYSTEM_OLD_DFLLMUL_CSTEP(value) ((_SYSTEM_OLD_DFLLMUL_CSTEP_Msk & ((value) << _SYSTEM_OLD_DFLLMUL_CSTEP_Pos)))
+
+#define _SYSTEM_NEW_DFLLMUL_FSTEP_Pos   16
+#define _SYSTEM_NEW_DFLLMUL_FSTEP_Msk   (0x3FFu << _SYSTEM_NEW_DFLLMUL_FSTEP_Pos)
+#define _SYSTEM_NEW_DFLLMUL_FSTEP(value) ((_SYSTEM_NEW_DFLLMUL_FSTEP_Msk & ((value) << _SYSTEM_NEW_DFLLMUL_FSTEP_Pos)))
+
+#define _SYSTEM_NEW_DFLLMUL_CSTEP_Pos   26
+#define _SYSTEM_NEW_DFLLMUL_CSTEP_Msk   (0x3Fu << _SYSTEM_NEW_DFLLMUL_CSTEP_Pos)
+#define _SYSTEM_NEW_DFLLMUL_CSTEP(value) ((_SYSTEM_NEW_DFLLMUL_CSTEP_Msk & ((value) << _SYSTEM_NEW_DFLLMUL_CSTEP_Pos)))
+
+#define _SYSTEM_MCU_REVISION_D 3
+
+///@endcond
+
+
+/**
+ * \brief Configure the DFLL clock source.
+ *
+ * Configures the Digital Frequency Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DFLL will be running when this function returns, as the DFLL module
+ *       needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config  DFLL configuration structure containing the new config
+ */
+void system_clock_source_dfll_set_config(
+		struct system_clock_source_dfll_config *const config)
+{
+
+	/* Get MCU revision */
+	uint32_t rev = system_get_device_id();
+
+	rev &= DSU_DID_REVISION_Msk;
+	rev = rev >> DSU_DID_REVISION_Pos;
+
+	if (rev < _SYSTEM_MCU_REVISION_D) {
+		_system_clock_inst.dfll.val =
+				_SYSTEM_OLD_DFLLVAL_COARSE(config->coarse_value) |
+				_SYSTEM_OLD_DFLLVAL_FINE(config->fine_value);
+	} else {
+		_system_clock_inst.dfll.val =
+				_SYSTEM_NEW_DFLLVAL_COARSE(config->coarse_value) |
+				_SYSTEM_NEW_DFLLVAL_FINE(config->fine_value);
+	}
+
+	_system_clock_inst.dfll.control =
+			(uint32_t)config->wakeup_lock     |
+			(uint32_t)config->stable_tracking |
+			(uint32_t)config->quick_lock      |
+			(uint32_t)config->chill_cycle     |
+			((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
+
+	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+
+		if(rev < _SYSTEM_MCU_REVISION_D) {
+			_system_clock_inst.dfll.mul =
+					_SYSTEM_OLD_DFLLMUL_CSTEP(config->coarse_max_step) |
+					_SYSTEM_OLD_DFLLMUL_FSTEP(config->fine_max_step)   |
+					SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+		} else {
+			_system_clock_inst.dfll.mul =
+					_SYSTEM_NEW_DFLLMUL_CSTEP(config->coarse_max_step) |
+					_SYSTEM_NEW_DFLLMUL_FSTEP(config->fine_max_step)   |
+					SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+		}
+
+		/* Enable the closed loop mode */
+		_system_clock_inst.dfll.control |= config->loop_mode;
+	}
+}
+
+/**
+ * \brief Writes the calibration values for a given oscillator clock source.
+ *
+ * Writes an oscillator calibration value to the given oscillator control
+ * registers. The acceptable ranges are:
+ *
+ * For OSC32K:
+ *  - 7 bits (max value 128)
+ * For OSC8MHZ:
+ *  - 8 bits (Max value 255)
+ * For OSCULP:
+ *  - 5 bits (Max value 32)
+ *
+ * \note The frequency range parameter applies only when configuring the 8MHz
+ *       oscillator and will be ignored for the other oscillators.
+ *
+ * \param[in] clock_source       Clock source to calibrate
+ * \param[in] calibration_value  Calibration value to write
+ * \param[in] freq_range         Frequency range (8MHz oscillator only)
+ *
+ * \retval STATUS_OK               The calibration value was written
+ *                                 successfully.
+ * \retval STATUS_ERR_INVALID_ARG  The setting is not valid for selected clock
+ *                                 source.
+ */
+enum status_code system_clock_source_write_calibration(
+		const enum system_clock_source clock_source,
+		const uint16_t calibration_value,
+		const uint8_t freq_range)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+
+		if (calibration_value > 0xfff || freq_range > 4) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		SYSCTRL->OSC8M.bit.CALIB  = calibration_value;
+		SYSCTRL->OSC8M.bit.FRANGE = freq_range;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+
+		if (calibration_value > 128) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		_system_osc32k_wait_for_sync();
+		SYSCTRL->OSC32K.bit.CALIB = calibration_value;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+
+		if (calibration_value > 32) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
+		break;
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+		break;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables a clock source.
+ *
+ * Enables a clock source which has been previously configured.
+ *
+ * \param[in] clock_source       Clock source to enable
+ *
+ * \retval STATUS_OK               Clock source was enabled successfully and
+ *                                 is ready
+ * \retval STATUS_ERR_INVALID_ARG  The clock source is not available on this
+ *                                 device
+ */
+enum status_code system_clock_source_enable(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+		return STATUS_OK;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
+		_system_clock_source_dfll_set_config_errata_9905();
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Always enabled */
+		return STATUS_OK;
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables a clock source.
+ *
+ * Disables a clock source that was previously enabled.
+ *
+ * \param[in] clock_source  Clock source to disable
+ *
+ * \retval STATUS_OK               Clock source was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  An invalid or unavailable clock source was
+ *                                 given
+ */
+enum status_code system_clock_source_disable(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		_system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
+		SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Not possible to disable */
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Checks if a clock source is ready.
+ *
+ * Checks if a given clock source is ready to be used.
+ *
+ * \param[in] clock_source  Clock source to check if ready
+ *
+ * \returns Ready state of the given clock source.
+ *
+ * \retval true   Clock source is enabled and ready
+ * \retval false  Clock source is disabled or not yet ready
+ */
+bool system_clock_source_is_ready(
+		const enum system_clock_source clock_source)
+{
+	uint32_t mask = 0;
+
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		mask = SYSCTRL_PCLKSR_OSC8MRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		mask = SYSCTRL_PCLKSR_OSC32KRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		mask = SYSCTRL_PCLKSR_XOSCRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		mask = SYSCTRL_PCLKSR_XOSC32KRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+			mask = (SYSCTRL_PCLKSR_DFLLRDY |
+			        SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
+		} else {
+			mask = SYSCTRL_PCLKSR_DFLLRDY;
+		}
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Not possible to disable */
+		return true;
+
+	default:
+		return false;
+	}
+
+	return ((SYSCTRL->PCLKSR.reg & mask) == mask);
+}
+
+/* Include some checks for conf_clocks.h validation */
+#include "clock_config_check.h"
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
+ */
+#  define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
+	if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
+		struct system_gclk_gen_config gclk_conf;                          \
+		system_gclk_gen_get_config_defaults(&gclk_conf);                  \
+		gclk_conf.source_clock    = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE;   \
+		gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER;      \
+		gclk_conf.run_in_standby  = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
+		gclk_conf.output_enable   = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE;  \
+		system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf);       \
+		system_gclk_gen_enable(GCLK_GENERATOR_##n);                       \
+	}
+
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h,
+ * provided that it is not the main Generic Clock Generator channel.
+ */
+#  define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
+		if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
+#endif
+
+/** \internal
+ *
+ * Switch all peripheral clock to a not enabled general clock
+ * to save power.
+ */
+static void _switch_peripheral_gclk(void)
+{
+	uint32_t gclk_id;
+	struct system_gclk_chan_config gclk_conf;
+
+#if CONF_CLOCK_GCLK_1_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_1;
+#elif CONF_CLOCK_GCLK_2_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_2;
+#elif CONF_CLOCK_GCLK_3_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_3;
+#elif CONF_CLOCK_GCLK_4_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_4;
+#elif CONF_CLOCK_GCLK_5_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_5;
+#elif CONF_CLOCK_GCLK_6_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_6;
+#elif CONF_CLOCK_GCLK_7_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_7;
+#else
+	gclk_conf.source_generator = GCLK_GENERATOR_7;
+#endif
+
+	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
+		system_gclk_chan_set_config(gclk_id, &gclk_conf);
+	}
+}
+
+/**
+ * \brief Initialize clock system based on the configuration in conf_clocks.h.
+ *
+ * This function will apply the settings in conf_clocks.h when run from the user
+ * application. All clock sources and GCLK generators are running when this function
+ * returns.
+ *
+ * \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
+ * the OSC8M default enable can be disabled after system_clock_init. Make sure the
+ * clock switch successfully before disabling OSC8M.
+ */
+void system_clock_init(void)
+{
+	/* Various bits in the INTFLAG register can be set to one at startup.
+	   This will ensure that these bits are cleared */
+	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
+			SYSCTRL_INTFLAG_DFLLRDY;
+
+	system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
+
+	/* Switch all peripheral clock to a not enabled general clock to save power. */
+	_switch_peripheral_gclk();
+
+	/* XOSC */
+#if CONF_CLOCK_XOSC_ENABLE == true
+	struct system_clock_source_xosc_config xosc_conf;
+	system_clock_source_xosc_get_config_defaults(&xosc_conf);
+
+	xosc_conf.external_clock    = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
+	xosc_conf.startup_time      = CONF_CLOCK_XOSC_STARTUP_TIME;
+	xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
+	xosc_conf.frequency         = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
+	xosc_conf.on_demand         = CONF_CLOCK_XOSC_ON_DEMAND;
+	xosc_conf.run_in_standby    = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
+
+	system_clock_source_xosc_set_config(&xosc_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
+#endif
+
+
+	/* XOSC32K */
+#if CONF_CLOCK_XOSC32K_ENABLE == true
+	struct system_clock_source_xosc32k_config xosc32k_conf;
+	system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
+
+	xosc32k_conf.frequency           = 32768UL;
+	xosc32k_conf.external_clock      = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
+	xosc32k_conf.startup_time        = CONF_CLOCK_XOSC32K_STARTUP_TIME;
+	xosc32k_conf.auto_gain_control   = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
+	xosc32k_conf.enable_1khz_output  = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
+	xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
+	xosc32k_conf.on_demand           = false;
+	xosc32k_conf.run_in_standby      = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
+
+	system_clock_source_xosc32k_set_config(&xosc32k_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+	if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
+		SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
+	}
+#endif
+
+
+	/* OSCK32K */
+#if CONF_CLOCK_OSC32K_ENABLE == true
+	SYSCTRL->OSC32K.bit.CALIB =
+			(*(uint32_t *)FUSES_OSC32KCAL_ADDR >> FUSES_OSC32KCAL_Pos);
+
+	struct system_clock_source_osc32k_config osc32k_conf;
+	system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
+
+	osc32k_conf.startup_time        = CONF_CLOCK_OSC32K_STARTUP_TIME;
+	osc32k_conf.enable_1khz_output  = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
+	osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
+	osc32k_conf.on_demand           = CONF_CLOCK_OSC32K_ON_DEMAND;
+	osc32k_conf.run_in_standby      = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
+
+	system_clock_source_osc32k_set_config(&osc32k_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
+#endif
+
+
+	/* DFLL Config (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+	struct system_clock_source_dfll_config dfll_conf;
+	system_clock_source_dfll_get_config_defaults(&dfll_conf);
+
+	dfll_conf.loop_mode      = CONF_CLOCK_DFLL_LOOP_MODE;
+	dfll_conf.on_demand      = false;
+
+	/* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping
+     in DFLL.COARSE helps to output a frequency close to 48 MHz.
+	   Not applicable for silicon rev C and previous*/
+
+	/* Get MCU revision */
+	uint32_t rev = system_get_device_id();
+
+	rev &= DSU_DID_REVISION_Msk;
+	rev = rev >> DSU_DID_REVISION_Pos;
+
+	if (rev >= _SYSTEM_MCU_REVISION_D) {
+#define NVM_DFLL_COARSE_POS    58 /* DFLL48M Coarse calibration value bit position.*/
+#define NVM_DFLL_COARSE_SIZE   6  /* DFLL48M Coarse calibration value bit size.*/
+
+		uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+				+ (NVM_DFLL_COARSE_POS / 32))
+			>> (NVM_DFLL_COARSE_POS % 32))
+			& ((1 << NVM_DFLL_COARSE_SIZE) - 1);
+		/* In some revision chip, the coarse calibration value is not correct. */
+		if (coarse == 0x3f) {
+			coarse = 0x1f;
+		}
+		dfll_conf.coarse_value = coarse;
+	}
+
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
+		dfll_conf.fine_value   = CONF_CLOCK_DFLL_FINE_VALUE;
+	}
+
+#  if CONF_CLOCK_DFLL_QUICK_LOCK == true
+	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+#  else
+	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
+#  endif
+
+#  if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
+	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+#  else
+	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+#  endif
+
+#  if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
+	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+#  else
+	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
+#  endif
+
+#  if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
+	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+#  else
+	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+#  endif
+
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+		dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
+	}
+
+	dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
+	dfll_conf.fine_max_step   = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
+
+	system_clock_source_dfll_set_config(&dfll_conf);
+#endif
+
+
+	/* OSC8M */
+	struct system_clock_source_osc8m_config osc8m_conf;
+	system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
+
+	osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
+	osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
+	osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
+
+	system_clock_source_osc8m_set_config(&osc8m_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
+
+
+	/* GCLK */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+	system_gclk_init();
+
+	/* Configure all GCLK generators except for the main generator, which
+	 * is configured later after all other clock systems are set up */
+	MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
+
+#  if CONF_CLOCK_DFLL_ENABLE == true
+	/* Enable DFLL reference clock if in closed loop mode */
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+		struct system_gclk_chan_config dfll_gclk_chan_conf;
+
+		system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
+		dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
+		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
+		system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
+	}
+#  endif
+#endif
+
+
+	/* DFLL Enable (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+	if (CONF_CLOCK_DFLL_ON_DEMAND) {
+		SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
+	}
+#endif
+
+	/* CPU and BUS clocks */
+	system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
+
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
+
+	/* GCLK 0 */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+	/* Configure the main GCLK last as it might depend on other generators */
+	_CONF_CLOCK_GCLK_CONFIG(0, ~);
+#endif
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_config_check.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_config_check.h
new file mode 100644
index 0000000000..f43ddf0e90
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_config_check.h
@@ -0,0 +1,378 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 Clock Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CLOCK_CONFIG_CHECK_H
+#  define CLOCK_CONFIG_CHECK_H
+
+#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
+#  error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CPU_DIVIDER)
+#  error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBA_DIVIDER)
+#  error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBB_DIVIDER)
+#  error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBC_DIVIDER)
+#  error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_PRESCALER)
+#  error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)
+#  error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ENABLE)
+#  error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
+#  error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
+#  error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
+#  error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
+#  error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)
+#  error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
+#  error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE)
+#  error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
+#  error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE)
+#  error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
+#  error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
+#  error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
+#  error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
+#  error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
+#  error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
+#  error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
+#  error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
+#  error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
+#  error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
+#  error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
+#  error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
+#  error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
+#  error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
+#  error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
+#  error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
+#  error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
+#  error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
+#  error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
+#  error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
+#  error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
+#  error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
+#  error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
+#  error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
+#  error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
+#  error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#endif /* CLOCK_CONFIG_CHECK_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_feature.h
new file mode 100644
index 0000000000..2c1e343704
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_feature.h
@@ -0,0 +1,1491 @@
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
+#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK)
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's clocking related functions. This includes
+ * the various clock sources, bus clocks, and generic clocks within the device,
+ * with functions to manage the enabling, disabling, source selection, and
+ * prescaling of clocks to various internal peripherals.
+ *
+ * The following peripherals are used by this module:
+ *
+ * - GCLK (Generic Clock Management)
+ * - PM (Power Management)
+ * - SYSCTRL (Clock Source Control)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D10/D11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_clock_prerequisites
+ *  - \ref asfdoc_sam0_system_clock_module_overview
+ *  - \ref asfdoc_sam0_system_clock_special_considerations
+ *  - \ref asfdoc_sam0_system_clock_extra_info
+ *  - \ref asfdoc_sam0_system_clock_examples
+ *  - \ref asfdoc_sam0_system_clock_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_clock_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_module_overview Module Overview
+ * The SAM devices contain a sophisticated clocking system, which is designed
+ * to give the maximum flexibility to the user application. This system allows
+ * a system designer to tune the performance and power consumption of the device
+ * in a dynamic manner, to achieve the best trade-off between the two for a
+ * particular application.
+ *
+ * This driver provides a set of functions for the configuration and management
+ * of the various clock related functionality within the device.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
+ * <table>
+ *	<tr>
+ *		<th>Driver Feature Macro</th>
+ *		<th>Supported devices</th>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_SYSTEM_CLOCK_DPLL</td>
+ *		<td>SAM D21, SAM R21, SAM D10, SAM D11</td>
+ *	</tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
+ * The SAM devices have a number of master clock source modules, each of
+ * which being capable of producing a stabilized output frequency, which can then
+ * be fed into the various peripherals and modules within the device.
+ *
+ * Possible clock source modules include internal R/C oscillators, internal
+ * DFLL modules, as well as external crystal oscillators and/or clock inputs.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
+ * The CPU and AHB/APBx buses are clocked by the same physical clock source
+ * (referred in this module as the Main Clock), however the APBx buses may
+ * have additional prescaler division ratios set to give each peripheral bus a
+ * different clock speed.
+ *
+ * The general main clock tree for the CPU and associated buses is shown in
+ * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_clock_tree
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   clk_src [label="Clock Sources", shape=none, height=0];
+ *   node [label="CPU Bus" shape=ellipse] cpu_bus;
+ *   node [label="AHB Bus" shape=ellipse] ahb_bus;
+ *   node [label="APBA Bus" shape=ellipse] apb_a_bus;
+ *   node [label="APBB Bus" shape=ellipse] apb_b_bus;
+ *   node [label="APBC Bus" shape=ellipse] apb_c_bus;
+ *   node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
+ *   node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
+ *   node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
+ *   node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
+ *   node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
+ *
+ *   clk_src         -> main_clock_mux;
+ *   main_clock_mux  -> main_prescaler;
+ *   main_prescaler  -> cpu_bus;
+ *   main_prescaler  -> ahb_bus;
+ *   main_prescaler  -> apb_a_prescaler;
+ *   main_prescaler  -> apb_b_prescaler;
+ *   main_prescaler  -> apb_c_prescaler;
+ *   apb_a_prescaler -> apb_a_bus;
+ *   apb_b_prescaler -> apb_b_bus;
+ *   apb_c_prescaler -> apb_c_bus;
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
+ * To save power, the input clock to one or more peripherals on the AHB and APBx
+ * buses can be masked away - when masked, no clock is passed into the module.
+ * Disabling of clocks of unused modules will prevent all access to the masked
+ * module, but will reduce the overall device power consumption.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
+ * Within the SAM devices there are a number of Generic Clocks; these are used to
+ * provide clocks to the various peripheral clock domains in the device in a
+ * standardized manner. One or more master source clocks can be selected as the
+ * input clock to a Generic Clock Generator, which can prescale down the input
+ * frequency to a slower rate for use in a peripheral.
+ *
+ * Additionally, a number of individually selectable Generic Clock Channels are
+ * provided, which multiplex and gate the various generator outputs for one or
+ * more peripherals within the device. This setup allows for a single common
+ * generator to feed one or more channels, which can then be enabled or disabled
+ * individually as required.
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_overview
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="Clock\nSource a" shape=square] system_clock_source;
+ *   node [label="Generator 1" shape=square] clock_gen;
+ *   node [label="Channel x" shape=square] clock_chan0;
+ *   node [label="Channel y" shape=square] clock_chan1;
+ *   node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
+ *   node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
+ *
+ *   system_clock_source -> clock_gen;
+ *   clock_gen   -> clock_chan0;
+ *   clock_chan0 -> peripheral0;
+ *   clock_gen   -> clock_chan1;
+ *   clock_chan1 -> peripheral1;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
+ * An example setup of a complete clock chain within the device is shown in
+ * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_example_fig
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="External\nOscillator" shape=square] system_clock_source0;
+ *   node [label="Generator 0" shape=square] clock_gen0;
+ *   node [label="Channel x" shape=square] clock_chan0;
+ *   node [label="Core CPU" shape=ellipse  style=filled fillcolor=lightgray] peripheral0;
+ *
+ *   system_clock_source0 -> clock_gen0;
+ *   clock_gen0    -> clock_chan0;
+ *   clock_chan0   -> peripheral0;
+ *   node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
+ *   node [label="Generator 1" shape=square] clock_gen1;
+ *   node [label="Channel y" shape=square] clock_chan1;
+ *   node [label="Channel z" shape=square] clock_chan2;
+ *   node [label="SERCOM\nModule" shape=ellipse  style=filled fillcolor=lightgray] peripheral1;
+ *   node [label="Timer\nModule" shape=ellipse  style=filled fillcolor=lightgray] peripheral2;
+ *
+ *   system_clock_source1 -> clock_gen1;
+ *   clock_gen1    -> clock_chan1;
+ *   clock_gen1    -> clock_chan2;
+ *   clock_chan1   -> peripheral1;
+ *   clock_chan2   -> peripheral2;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
+ * Each Generic Clock generator within the device can source its input clock
+ * from one of the provided Source Clocks, and prescale the output for one or
+ * more Generic Clock Channels in a one-to-many relationship. The generators
+ * thus allow for several clocks to be generated of different frequencies,
+ * power usages, and accuracies, which can be turned on and off individually to
+ * disable the clocks to multiple peripherals as a group.
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
+ * To connect a Generic Clock Generator to a peripheral within the
+ * device, a Generic Clock Channel is used. Each peripheral or
+ * peripheral group has an associated Generic Clock Channel, which serves as the
+ * clock input for the peripheral(s). To supply a clock to the peripheral
+ * module(s), the associated channel must be connected to a running Generic
+ * Clock Generator and the channel enabled.
+ *
+ * \section asfdoc_sam0_system_clock_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
+ *  - \ref asfdoc_sam0_system_clock_extra_acronyms
+ *  - \ref asfdoc_sam0_system_clock_extra_dependencies
+ *  - \ref asfdoc_sam0_system_clock_extra_errata
+ *  - \ref asfdoc_sam0_system_clock_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_clock_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_clock_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <gclk.h>
+
+/**
+ * \name Driver Feature Definition
+ * Define system clock features set according to different device family.
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || defined(__DOXYGEN__)
+/** Digital Phase Locked Loop (DPLL) feature support. */
+#  define FEATURE_SYSTEM_CLOCK_DPLL
+#endif
+/*@}*/
+
+/**
+ * \brief Available start-up times for the XOSC32K.
+ *
+ * Available external 32KHz oscillator start-up times, as a number of external
+ * clock cycles.
+ */
+enum system_xosc32k_startup {
+	/** Wait zero clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC32K_STARTUP_0,
+	/** Wait 32 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC32K_STARTUP_32,
+	/** Wait 2048 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC32K_STARTUP_2048,
+	/** Wait 4096 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC32K_STARTUP_4096,
+	/** Wait 16384 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC32K_STARTUP_16384,
+	/** Wait 32768 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC32K_STARTUP_32768,
+	/** Wait 65536 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC32K_STARTUP_65536,
+	/** Wait 131072 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC32K_STARTUP_131072,
+};
+
+/**
+ * \brief Available start-up times for the XOSC.
+ *
+ * Available external oscillator start-up times, as a number of external clock
+ * cycles.
+ */
+enum system_xosc_startup {
+	/** Wait one clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_1,
+	/** Wait two clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_2,
+	/** Wait four clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_4,
+	/** Wait eight clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_8,
+	/** Wait 16 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_16,
+	/** Wait 32 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_32,
+	/** Wait 64 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_64,
+	/** Wait 128 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_128,
+	/** Wait 256 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_256,
+	/** Wait 512 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_512,
+	/** Wait 1024 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_1024,
+	/** Wait 2048 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_2048,
+	/** Wait 4096 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_4096,
+	/** Wait 8192 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_8192,
+	/** Wait 16384 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_16384,
+	/** Wait 32768 clock cycles until the clock source is considered stable. */
+	SYSTEM_XOSC_STARTUP_32768,
+};
+
+/**
+ * \brief Available start-up times for the OSC32K.
+ *
+ * Available internal 32KHz oscillator start-up times, as a number of internal
+ * OSC32K clock cycles.
+ */
+enum system_osc32k_startup {
+	/** Wait three clock cycles until the clock source is considered stable. */
+	SYSTEM_OSC32K_STARTUP_3,
+	/** Wait four clock cycles until the clock source is considered stable. */
+	SYSTEM_OSC32K_STARTUP_4,
+	/** Wait six clock cycles until the clock source is considered stable. */
+	SYSTEM_OSC32K_STARTUP_6,
+	/** Wait ten clock cycles until the clock source is considered stable. */
+	SYSTEM_OSC32K_STARTUP_10,
+	/** Wait 18 clock cycles until the clock source is considered stable. */
+	SYSTEM_OSC32K_STARTUP_18,
+	/** Wait 34 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_34,
+	/** Wait 66 clock cycles until the clock source is considered stable. */
+	SYSTEM_OSC32K_STARTUP_66,
+	/** Wait 130 clock cycles until the clock source is considered stable. */
+	SYSTEM_OSC32K_STARTUP_130,
+};
+
+/**
+ * \brief Division prescalers for the internal 8MHz system clock.
+ *
+ * Available prescalers for the internal 8MHz (nominal) system clock.
+ */
+enum system_osc8m_div {
+	/** Do not divide the 8MHz RC oscillator output. */
+	SYSTEM_OSC8M_DIV_1,
+	/** Divide the 8MHz RC oscillator output by two. */
+	SYSTEM_OSC8M_DIV_2,
+	/** Divide the 8MHz RC oscillator output by four. */
+	SYSTEM_OSC8M_DIV_4,
+	/** Divide the 8MHz RC oscillator output by eight. */
+	SYSTEM_OSC8M_DIV_8,
+};
+
+/**
+ * \brief Frequency range for the internal 8MHz RC oscillator.
+ *
+ * Internal 8MHz RC oscillator frequency range setting.
+ */
+enum system_osc8m_frequency_range {
+	/** Frequency range 4MHz to 6MHz. */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
+	/** Frequency range 6MHz to 8MHz. */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
+	/** Frequency range 8MHz to 11MHz. */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
+	/** Frequency range 11MHz to 15MHz. */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
+};
+
+/**
+ * \brief Main CPU and APB/AHB bus clock source prescaler values.
+ *
+ * Available division ratios for the CPU and APB/AHB bus clocks.
+ */
+enum system_main_clock_div {
+	/** Divide Main clock by one. */
+	SYSTEM_MAIN_CLOCK_DIV_1,
+	/** Divide Main clock by two. */
+	SYSTEM_MAIN_CLOCK_DIV_2,
+	/** Divide Main clock by four. */
+	SYSTEM_MAIN_CLOCK_DIV_4,
+	/** Divide Main clock by eight. */
+	SYSTEM_MAIN_CLOCK_DIV_8,
+	/** Divide Main clock by 16. */
+	SYSTEM_MAIN_CLOCK_DIV_16,
+	/** Divide Main clock by 32. */
+	SYSTEM_MAIN_CLOCK_DIV_32,
+	/** Divide Main clock by 64. */
+	SYSTEM_MAIN_CLOCK_DIV_64,
+	/** Divide Main clock by 128. */
+	SYSTEM_MAIN_CLOCK_DIV_128,
+};
+
+/**
+ * \brief External clock source types.
+ *
+ * Available external clock source types.
+ */
+enum system_clock_external {
+	/** The external clock source is a crystal oscillator. */
+	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
+	/** The connected clock source is an external logic level clock signal. */
+	SYSTEM_CLOCK_EXTERNAL_CLOCK,
+};
+
+/**
+ * \brief Operating modes of the DFLL clock source.
+ *
+ * Available operating modes of the DFLL clock source module.
+ */
+enum system_clock_dfll_loop_mode {
+	/** The DFLL is operating in open loop mode with no feedback. */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
+	/** The DFLL is operating in closed loop mode with frequency feedback from
+	 *  a low frequency reference clock.
+	 */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
+
+#ifdef SYSCTRL_DFLLCTRL_USBCRM
+	/** The DFLL is operating in USB recovery mode with frequency feedback
+	 *  from USB SOF.
+	 */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
+#endif
+};
+
+/**
+ * \brief Locking behavior for the DFLL during device wake-up.
+ *
+ * DFLL lock behavior modes on device wake-up from sleep.
+ */
+enum system_clock_dfll_wakeup_lock {
+	/** Keep DFLL lock when the device wakes from sleep. */
+	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
+	/** Lose DFLL lock when the devices wakes from sleep. */
+	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
+};
+
+/**
+ * \brief Fine tracking behavior for the DFLL once a lock has been acquired.
+ *
+ * DFLL fine tracking behavior modes after a lock has been acquired.
+ */
+enum system_clock_dfll_stable_tracking {
+	/** Keep tracking after the DFLL has gotten a fine lock. */
+	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
+	/** Stop tracking after the DFLL has gotten a fine lock. */
+	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
+};
+
+/**
+ * \brief Chill-cycle behavior of the DFLL module.
+ *
+ * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
+ * of time when the DFLL output frequency is not measured by the unit, to allow
+ * the output to stabilize after a change in the input clock source.
+ */
+enum system_clock_dfll_chill_cycle {
+	/** Enable a chill cycle, where the DFLL output frequency is not measured. */
+	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
+	/** Disable a chill cycle, where the DFLL output frequency is not measured. */
+	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
+};
+
+/**
+ * \brief QuickLock settings for the DFLL module.
+ *
+ * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
+ * the DFLL output frequency at the expense of accuracy.
+ */
+enum system_clock_dfll_quick_lock {
+	/** Enable the QuickLock feature for looser lock requirements on the DFLL. */
+	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
+	/** Disable the QuickLock feature for strict lock requirements on the DFLL. */
+	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
+};
+
+/**
+ * \brief Available clock sources in the system.
+ *
+ * Clock sources available to the GCLK generators.
+ */
+enum system_clock_source {
+	/** Internal 8MHz RC oscillator. */
+	SYSTEM_CLOCK_SOURCE_OSC8M    = GCLK_SOURCE_OSC8M,
+	/** Internal 32KHz RC oscillator. */
+	SYSTEM_CLOCK_SOURCE_OSC32K   = GCLK_SOURCE_OSC32K,
+	/** External oscillator. */
+	SYSTEM_CLOCK_SOURCE_XOSC     = GCLK_SOURCE_XOSC ,
+	/** External 32KHz oscillator. */
+	SYSTEM_CLOCK_SOURCE_XOSC32K  = GCLK_SOURCE_XOSC32K,
+	/** Digital Frequency Locked Loop (DFLL). */
+	SYSTEM_CLOCK_SOURCE_DFLL     = GCLK_SOURCE_DFLL48M,
+	/** Internal Ultra Low Power 32KHz oscillator. */
+	SYSTEM_CLOCK_SOURCE_ULP32K   = GCLK_SOURCE_OSCULP32K,
+	/** Generator input pad. */
+	SYSTEM_CLOCK_SOURCE_GCLKIN     = GCLK_SOURCE_GCLKIN,
+	/** Generic clock generator one output. */
+	SYSTEM_CLOCK_SOURCE_GCLKGEN1   = GCLK_SOURCE_GCLKGEN1,
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	/** Digital Phase Locked Loop (DPLL).
+	 * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
+	 */
+	SYSTEM_CLOCK_SOURCE_DPLL     = GCLK_SOURCE_FDPLL,
+#endif
+};
+
+/**
+ * \brief List of APB peripheral buses.
+ *
+ * Available bus clock domains on the APB bus.
+ */
+enum system_clock_apb_bus {
+	/** Peripheral bus A on the APB bus. */
+	SYSTEM_CLOCK_APB_APBA,
+	/** Peripheral bus B on the APB bus. */
+	SYSTEM_CLOCK_APB_APBB,
+	/** Peripheral bus C on the APB bus. */
+	SYSTEM_CLOCK_APB_APBC,
+};
+
+/**
+ * \brief Configuration structure for XOSC.
+ *
+ * External oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc_config {
+	/** External clock type. */
+	enum system_clock_external external_clock;
+	/** Crystal oscillator start-up time. */
+	enum system_xosc_startup startup_time;
+	/** Enable automatic amplitude gain control. */
+	bool auto_gain_control;
+	/** External clock/crystal frequency. */
+	uint32_t frequency;
+	/** Keep the XOSC enabled in standby sleep mode. */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the XOSC won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for XOSC32K.
+ *
+ * External 32KHz oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc32k_config {
+	/** External clock type. */
+	enum system_clock_external external_clock;
+	/** Crystal oscillator start-up time. */
+	enum system_xosc32k_startup startup_time;
+	/** Enable automatic amplitude control. */
+	bool auto_gain_control;
+	/** Enable 1KHz output. */
+	bool enable_1khz_output;
+	/** Enable 32KHz output. */
+	bool enable_32khz_output;
+	/** External clock/crystal frequency. */
+	uint32_t frequency;
+	/** Keep the XOSC32K enabled in standby sleep mode. */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the XOSC32K won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Lock configuration after it has been written,
+	 *  a device reset will release the lock. */
+	bool write_once;
+};
+
+/**
+ * \brief Configuration structure for OSC8M.
+ *
+ * Internal 8MHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc8m_config {
+	/** Internal 8MHz RC oscillator prescaler. */
+	enum system_osc8m_div prescaler;
+	/** Keep the OSC8M enabled in standby sleep mode. */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the OSC8M won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for OSC32K.
+ *
+ * Internal 32KHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc32k_config {
+	/** Startup time. */
+	enum system_osc32k_startup startup_time;
+	/** Enable 1KHz output. */
+	bool enable_1khz_output;
+	/** Enable 32KHz output. */
+	bool enable_32khz_output;
+	/** Keep the OSC32K enabled in standby sleep mode. */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the OSC32K won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Lock configuration after it has been written,
+	 *  a device reset will release the lock. */
+	bool write_once;
+};
+
+/**
+ * \brief Configuration structure for DFLL.
+ *
+ * DFLL oscillator configuration structure.
+ */
+struct system_clock_source_dfll_config {
+	/** Loop mode. */
+	enum system_clock_dfll_loop_mode loop_mode;
+	/** Run On Demand. If this is set the DFLL won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Enable Quick Lock. */
+	enum system_clock_dfll_quick_lock quick_lock;
+	/** Enable Chill Cycle. */
+	enum system_clock_dfll_chill_cycle chill_cycle;
+	/** DFLL lock state on wakeup. */
+	enum system_clock_dfll_wakeup_lock wakeup_lock;
+	/** DFLL tracking after fine lock. */
+	enum system_clock_dfll_stable_tracking stable_tracking;
+	/** Coarse calibration value (Open loop mode). */
+	uint8_t coarse_value;
+	/** Fine calibration value (Open loop mode). */
+	uint16_t fine_value;
+	/** Coarse adjustment maximum step size (Closed loop mode). */
+	uint8_t coarse_max_step;
+	/** Fine adjustment maximum step size (Closed loop mode). */
+	uint16_t fine_max_step;
+	/** DFLL multiply factor (Closed loop mode. */
+	uint16_t multiply_factor;
+};
+
+/**
+ * \name External Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external oscillator module:
+ *   - External Crystal
+ *   - Start-up time of 16384 external clock cycles
+ *   - Automatic crystal gain control mode enabled
+ *   - Frequency of 12MHz
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc_get_config_defaults(
+		struct system_clock_source_xosc_config *const config)
+{
+	Assert(config);
+
+	config->external_clock    = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+	config->startup_time      = SYSTEM_XOSC_STARTUP_16384;
+	config->auto_gain_control = true;
+	config->frequency         = 12000000UL;
+	config->run_in_standby    = false;
+	config->on_demand         = true;
+}
+
+void system_clock_source_xosc_set_config(
+		struct system_clock_source_xosc_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name External 32KHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC32K.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external 32KHz oscillator module:
+ *   - External Crystal
+ *   - Start-up time of 16384 external clock cycles
+ *   - Automatic crystal gain control mode disabled
+ *   - Frequency of 32.768KHz
+ *   - 1KHz clock output disabled
+ *   - 32KHz clock output enabled
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *   - Don't lock registers after configuration has been written
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc32k_get_config_defaults(
+		struct system_clock_source_xosc32k_config *const config)
+{
+	Assert(config);
+
+	config->external_clock      = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+	config->startup_time        = SYSTEM_XOSC32K_STARTUP_16384;
+	config->auto_gain_control   = false;
+	config->frequency           = 32768UL;
+	config->enable_1khz_output  = false;
+	config->enable_32khz_output = true;
+	config->run_in_standby      = false;
+	config->on_demand           = true;
+	config->write_once          = false;
+}
+
+void system_clock_source_xosc32k_set_config(
+		struct system_clock_source_xosc32k_config *const config);
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 32KHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC32K.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 32KHz oscillator module:
+ *   - 1KHz clock output enabled
+ *   - 32KHz clock output enabled
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *   - Set startup time to 130 cycles
+ *   - Don't lock registers after configuration has been written
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc32k_get_config_defaults(
+		struct system_clock_source_osc32k_config *const config)
+{
+	Assert(config);
+
+	config->enable_1khz_output  = true;
+	config->enable_32khz_output = true;
+	config->run_in_standby      = false;
+	config->on_demand           = true;
+	config->startup_time        = SYSTEM_OSC32K_STARTUP_130;
+	config->write_once          = false;
+}
+
+void system_clock_source_osc32k_set_config(
+		struct system_clock_source_osc32k_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 8MHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC8M.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 8MHz (nominal) oscillator module:
+ *   - Clock output frequency divided by a factor of eight
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc8m_get_config_defaults(
+		struct system_clock_source_osc8m_config *const config)
+{
+	Assert(config);
+
+	config->prescaler       = SYSTEM_OSC8M_DIV_8;
+	config->run_in_standby  = false;
+	config->on_demand       = true;
+}
+
+void system_clock_source_osc8m_set_config(
+		struct system_clock_source_osc8m_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal DFLL Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DFLL.
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DFLL oscillator module:
+ *   - Open loop mode
+ *   - QuickLock mode enabled
+ *   - Chill cycle enabled
+ *   - Output frequency lock maintained during device wake-up
+ *   - Continuous tracking of the output frequency
+ *   - Default tracking values at the mid-points for both coarse and fine
+ *     tracking parameters
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dfll_get_config_defaults(
+		struct system_clock_source_dfll_config *const config)
+{
+	Assert(config);
+
+	config->loop_mode       = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
+	config->quick_lock      = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+	config->chill_cycle     = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+	config->wakeup_lock     = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+	config->on_demand       = true;
+
+	/* Open loop mode calibration value */
+	config->coarse_value    = 0x1f / 4; /* Midpoint */
+	config->fine_value      = 0xff / 4; /* Midpoint */
+
+	/* Closed loop mode */
+	config->coarse_max_step = 1;
+	config->fine_max_step   = 1;
+	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
+}
+
+void system_clock_source_dfll_set_config(
+		struct system_clock_source_dfll_config *const config);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Clock Source Management
+ * @{
+ */
+enum status_code system_clock_source_write_calibration(
+		const enum system_clock_source system_clock_source,
+		const uint16_t calibration_value,
+		const uint8_t freq_range);
+
+enum status_code system_clock_source_enable(
+		const enum system_clock_source system_clock_source);
+
+enum status_code system_clock_source_disable(
+		const enum system_clock_source clk_source);
+
+bool system_clock_source_is_ready(
+		const enum system_clock_source clk_source);
+
+uint32_t system_clock_source_get_hz(
+		const enum system_clock_source clk_source);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Main Clock Management
+ * @{
+ */
+
+/**
+ * \brief Set main CPU clock divider.
+ *
+ * Sets the clock divider used on the main clock to provide the CPU clock.
+ *
+ * \param[in] divider  CPU clock divider to set
+ */
+static inline void system_cpu_clock_set_divider(
+		const enum system_main_clock_div divider)
+{
+	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
+	PM->CPUSEL.reg = (uint32_t)divider;
+}
+
+/**
+ * \brief Retrieves the current frequency of the CPU core.
+ *
+ * Retrieves the operating frequency of the CPU core, obtained from the main
+ * generic clock and the set CPU bus divider.
+ *
+ * \return Current CPU frequency in Hz.
+ */
+static inline uint32_t system_cpu_clock_get_hz(void)
+{
+	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
+}
+
+/**
+ * \brief Set APBx clock divider.
+ *
+ * Set the clock divider used on the main clock to provide the clock for the
+ * given APBx bus.
+ *
+ * \param[in] divider  APBx bus divider to set
+ * \param[in] bus      APBx bus to set divider
+ *
+ * \returns Status of the clock division change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus ID was given
+ * \retval STATUS_OK               The APBx clock was set successfully
+ */
+static inline enum status_code system_apb_clock_set_divider(
+		const enum system_clock_apb_bus bus,
+		const enum system_main_clock_div divider)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBASEL.reg = (uint32_t)divider;
+			break;
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBSEL.reg = (uint32_t)divider;
+			break;
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCSEL.reg = (uint32_t)divider;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the current frequency of a ABPx.
+ *
+ * Retrieves the operating frequency of an APBx bus, obtained from the main
+ * generic clock and the set APBx bus divider.
+ *
+ * \return Current APBx bus frequency in Hz.
+ */
+static inline uint32_t system_apb_clock_get_hz(
+		const enum system_clock_apb_bus bus)
+{
+	uint16_t bus_divider = 0;
+
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			bus_divider = PM->APBASEL.reg;
+			break;
+		case SYSTEM_CLOCK_APB_APBB:
+			bus_divider = PM->APBBSEL.reg;
+			break;
+		case SYSTEM_CLOCK_APB_APBC:
+			bus_divider = PM->APBCSEL.reg;
+			break;
+		default:
+			Assert(false);
+			return 0;
+	}
+
+	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * \name Bus Clock Masking
+ * @{
+ */
+
+/**
+ * \brief Set bits in the clock mask for the AHB bus.
+ *
+ * This function will set bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will enable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask  AHB clock mask to enable
+ */
+static inline void system_ahb_clock_set_mask(
+		const uint32_t ahb_mask)
+{
+	PM->AHBMASK.reg |= ahb_mask;
+}
+
+/**
+ * \brief Clear bits in the clock mask for the AHB bus.
+ *
+ * This function will clear bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will disable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask  AHB clock mask to disable
+ */
+static inline void system_ahb_clock_clear_mask(
+		const uint32_t ahb_mask)
+{
+	PM->AHBMASK.reg &= ~ahb_mask;
+}
+
+/**
+ * \brief Set bits in the clock mask for an APBx bus.
+ *
+ * This function will set bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will enable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask  APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ *                  the device header files
+ * \param[in] bus   Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
+ *                  constants from the device header files
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus given
+ * \retval STATUS_OK               The clock mask was set successfully
+ */
+static inline enum status_code system_apb_clock_set_mask(
+		const enum system_clock_apb_bus bus,
+		const uint32_t mask)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBAMASK.reg |= mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBMASK.reg |= mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCMASK.reg |= mask;
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Clear bits in the clock mask for an APBx bus.
+ *
+ * This function will clear bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will disable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask  APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ *                  the device header files
+ * \param[in] bus   Bus to clear clock mask bits
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus ID was given
+ * \retval STATUS_OK               The clock mask was changed successfully
+ */
+static inline enum status_code system_apb_clock_clear_mask(
+		const enum system_clock_apb_bus bus,
+		const uint32_t mask)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBAMASK.reg &= ~mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBMASK.reg &= ~mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCMASK.reg &= ~mask;
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * @}
+ */
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+/**
+ * \brief Reference clock source of the DPLL module.
+ */
+enum system_clock_source_dpll_reference_clock {
+	/** Select CLK_DPLL_REF0 as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
+	/** Select CLK_DPLL_REF1 as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
+	/** Select GCLK_DPLL as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
+};
+
+/**
+ * \brief Lock time-out value of the DPLL module.
+ */
+enum system_clock_source_dpll_lock_time {
+	/** Set no time-out as default. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
+	/** Set time-out if no lock within 8ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
+	/** Set time-out if no lock within 9ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
+	/** Set time-out if no lock within 10ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
+	/** Set time-out if no lock within 11ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
+};
+
+/**
+ * \brief Filter type of the DPLL module.
+ */
+enum system_clock_source_dpll_filter {
+	/** Default filter mode. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
+	/** Low bandwidth filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
+	/** High bandwidth filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
+	/** High damping filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
+};
+
+/**
+ * \brief Configuration structure for DPLL.
+ *
+ * DPLL oscillator configuration structure.
+ */
+struct system_clock_source_dpll_config {
+	/** Run On Demand. If this is set the DPLL won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Keep the DPLL enabled in standby sleep mode. */
+	bool run_in_standby;
+	/** Bypass lock signal. */
+	bool lock_bypass;
+	/** Wake up fast. If this is set DPLL output clock is enabled after
+	 * the startup time. */
+	bool wake_up_fast;
+	/** Enable low power mode.  */
+	bool low_power_enable;
+
+	/** Output frequency of the clock. */
+	uint32_t output_frequency;
+	/** Reference frequency of the clock. */
+	uint32_t reference_frequency;
+	/** Devider of reference clock. */
+	uint16_t reference_divider;
+
+	/** Filter type of the DPLL module. */
+	enum system_clock_source_dpll_filter          filter;
+	/** Lock time-out value of the DPLL module. */
+	enum system_clock_source_dpll_lock_time       lock_time;
+	/** Reference clock source of the DPLL module. */
+	enum system_clock_source_dpll_reference_clock reference_clock;
+};
+
+/**
+ * \name Internal DPLL Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DPLL.
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DPLL oscillator module:
+ *   - Run only when requested by peripheral (on demand)
+ *   - Don't run in STANDBY sleep mode
+ *   - Lock bypass disabled
+ *   - Fast wake up disabled
+ *   - Low power mode disabled
+ *   - Output frequency is 48MHz
+ *   - Reference clock frequency is 32768Hz
+ *   - Not divide reference clock
+ *   - Select REF0 as reference clock
+ *   - Set lock time to default mode
+ *   - Use default filter
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dpll_get_config_defaults(
+		struct system_clock_source_dpll_config *const config)
+{
+	config->on_demand           = true;
+	config->run_in_standby      = false;
+	config->lock_bypass         = false;
+	config->wake_up_fast        = false;
+	config->low_power_enable    = false;
+
+	config->output_frequency    = 48000000;
+	config->reference_frequency = 32768;
+	config->reference_divider   = 1;
+	config->reference_clock     = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
+
+	config->lock_time           = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
+	config->filter              = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
+};
+
+void system_clock_source_dpll_set_config(
+		struct system_clock_source_dpll_config *const config);
+
+/* @} */
+#endif
+
+/**
+ * \name System Clock Initialization
+ * @{
+ */
+
+void system_clock_init(void);
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Flash Wait States
+ * @{
+ */
+
+/**
+ * \brief Set flash controller wait states.
+ *
+ * Will set the number of wait states that are used by the onboard
+ * flash memory. The number of wait states depend on both device
+ * supply voltage and CPU speed. The required number of wait states
+ * can be found in the electrical characteristics of the device.
+ *
+ * \param[in] wait_states Number of wait states to use for internal flash
+ */
+static inline void system_flash_set_waitstates(uint8_t wait_states)
+{
+	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
+			((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
+
+	NVMCTRL->CTRLB.bit.RWS = wait_states;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
+ *
+ * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>DFLL</td>
+ *		<td>Digital Frequency Locked Loop</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC32K</td>
+ *		<td>Internal 32KHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC8M</td>
+ *		<td>Internal 8MHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PLL</td>
+ *		<td>Phase Locked Loop</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC</td>
+ *		<td>Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>XOSC</td>
+ *		<td>External Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>XOSC32K</td>
+ *		<td>External 32KHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>AHB</td>
+ *		<td>Advanced High-performance Bus</td>
+ *	</tr>
+ *	<tr>
+ *		<td>APB</td>
+ *		<td>Advanced Peripheral Bus</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DPLL</td>
+ *		<td>Digital Phase Locked Loop</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_errata Errata
+ *
+ *	- This driver implements experimental workaround for errata 9905
+ *
+ *	  "The DFLL clock must be requested before being configured otherwise a
+ *	  write access to a DFLL register can freeze the device."
+ *	  This driver will enable and configure the DFLL before the ONDEMAND bit is set.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *			\li Corrected OSC32K startup time definitions
+ *			\li Support locking of OSC32K and XOSC32K config register (default: false)
+ *			\li Added DPLL support, functions added:
+ *			    \c system_clock_source_dpll_get_config_defaults() and
+ *		        \c system_clock_source_dpll_set_config()
+ *			\li Moved gclk channel locking feature out of the config struct
+ *			    functions added:
+ *			    \c system_gclk_chan_lock(),
+ *			    \c system_gclk_chan_is_locked()
+ *			    \c system_gclk_chan_is_enabled() and
+ *			    \c system_gclk_gen_is_enabled()
+ *		</td>
+ *	</tr>
+ *  <tr>
+ *		<td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
+ *		    and configured to a failed/not running clock generator</td>
+ *  </tr>
+ *	<tr>
+ *		<td>
+ *			\li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
+ *			\li Fixed system_flash_set_waitstates() failing with an assertion
+ *			    if an odd number of wait states provided
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *			\li Updated DFLL configuration function to implement workaround for
+ *			    errata 9905 in the DFLL module
+ *			\li Updated \c system_clock_init() to reset interrupt flags before
+ *			    they are used
+ *			\li Fixed \c system_clock_source_get_hz() to return correcy DFLL
+ *			    frequency number
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>\li Fixed \c system_clock_source_is_ready not returning the correct
+ *              state for \c SYSTEM_CLOCK_SOURCE_OSC8M
+ *          \li Renamed the various \c system_clock_source_*_get_default_config()
+ *              functions to \c system_clock_source_*_get_config_defaults() to
+ *              match the remainder of ASF
+ *          \li Added OSC8M calibration constant loading from the device signature
+ *              row when the oscillator is initialized
+ *          \li Updated default configuration of the XOSC32 to disable Automatic
+ *              Gain Control due to silicon errata
+ *      </td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in
+ * a selection of use cases. Note that QSGs can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_clock_basic_use_case
+ *  - \subpage asfdoc_sam0_system_gclk_basic_use_case
+ *
+ * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>E</td>
+ *		<td>04/2015</td>
+ *		<td>Added support for SAMDA1.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAMR21 and SAMD10/D11.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAMD21.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos. Fixed missing steps in the Basic
+ *          Use Case Quick Start Guide.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/gclk.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/gclk.c
new file mode 100644
index 0000000000..36579ad9ae
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/gclk.c
@@ -0,0 +1,522 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 Generic Clock Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <gclk.h>
+#include <clock.h>
+#include <system_interrupt.h>
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false if the module has completed synchronization
+ * \retval true if the module synchronization is ongoing
+ */
+static inline bool system_gclk_is_syncing(void)
+{
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Initializes the GCLK driver.
+ *
+ * Initializes the Generic Clock module, disabling and resetting all active
+ * Generic Clock Generators and Channels to their power-on default values.
+ */
+void system_gclk_init(void)
+{
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+	/* Software reset the module to ensure it is re-initialized correctly */
+	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
+		/* Wait for reset to complete */
+	}
+}
+
+/**
+ * \brief Writes a Generic Clock Generator configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock Generator configuration
+ * to the hardware module.
+ *
+ * \note Changing the clock source on the fly (on a running
+ *       generator) can take additional time if the clock source is configured
+ *       to only run on-demand (ONDEMAND bit is set) and it is not currently
+ *       running (no peripheral is requesting the clock source). In this case
+ *       the GCLK will request the new clock while still keeping a request to
+ *       the old clock source until the new clock source is ready.
+ *
+ * \note This function will not start a generator that is not already running;
+ *       to start the generator, call \ref system_gclk_gen_enable()
+ *       after configuring a generator.
+ *
+ * \param[in] generator  Generic Clock Generator index to configure
+ * \param[in] config     Configuration settings for the generator
+ */
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache new register configurations to minimize sync requirements. */
+	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
+
+	/* Select the requested source clock for the generator */
+	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+	/* Configure the clock to be either high or low when disabled */
+	if (config->high_when_disabled) {
+		new_genctrl_config |= GCLK_GENCTRL_OOV;
+	}
+
+	/* Configure if the clock output to I/O pin should be enabled. */
+	if (config->output_enable) {
+		new_genctrl_config |= GCLK_GENCTRL_OE;
+	}
+
+	/* Set division factor */
+	if (config->division_factor > 1) {
+		/* Check if division is a power of two */
+		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
+			/* Determine the index of the highest bit set to get the
+			 * division factor that must be loaded into the division
+			 * register */
+
+			uint32_t div2_count = 0;
+
+			uint32_t mask;
+			for (mask = (1UL << 1); mask < config->division_factor;
+						mask <<= 1) {
+				div2_count++;
+			}
+
+			/* Set binary divider power of 2 division factor */
+			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
+			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+		} else {
+			/* Set integer division factor */
+
+			new_gendiv_config  |=
+					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
+
+			/* Enable non-binary division with increased duty cycle accuracy */
+			new_genctrl_config |= GCLK_GENCTRL_IDC;
+		}
+
+	}
+
+	/* Enable or disable the clock in standby mode */
+	if (config->run_in_standby) {
+		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+	}
+
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the correct generator */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+
+	/* Write the new generator configuration */
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+	GCLK->GENDIV.reg  = new_gendiv_config;
+
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Enables a Generic Clock Generator that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock Generator that was previously
+ * configured via a call to \ref system_gclk_gen_set_config().
+ *
+ * \param[in] generator  Generic Clock Generator index to enable
+ */
+void system_gclk_gen_enable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Enable generator */
+	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock Generator that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock Generator that was previously
+ * started via a call to \ref system_gclk_gen_enable().
+ *
+ * \param[in] generator  Generic Clock Generator index to disable
+ */
+void system_gclk_gen_disable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Disable generator */
+	GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+	while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock Generator is enabled.
+ *
+ * \param[in] generator  Generic Clock Generator index to check
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock Generator is enabled
+ * \retval false The Generic Clock Generator is disabled
+ */
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	/* Obtain the enabled status */
+	enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock generator.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * generator, used as a source to a Generic Clock Channel module.
+ *
+ * \param[in] generator  Generic Clock Generator index
+ *
+ * \return The frequency of the generic clock generator, in Hz.
+ */
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the appropriate generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Get the frequency of the source connected to the GCLK generator */
+	uint32_t gen_input_hz = system_clock_source_get_hz(
+			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+
+	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+
+	/* Select the appropriate generator division register */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	uint32_t divider = GCLK->GENDIV.bit.DIV;
+
+	system_interrupt_leave_critical_section();
+
+	/* Check if the generator is using fractional or binary division */
+	if (!divsel && divider > 1) {
+		gen_input_hz /= divider;
+	} else if (divsel) {
+		gen_input_hz >>= (divider+1);
+	}
+
+	return gen_input_hz;
+}
+
+/**
+ * \brief Writes a Generic Clock configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock configuration to the
+ * hardware module. If the clock is currently running, it will be stopped.
+ *
+ * \note Once called the clock will not be running; to start the clock,
+ *       call \ref system_gclk_chan_enable() after configuring a clock channel.
+ *
+ * \param[in] channel   Generic Clock channel to configure
+ * \param[in] config    Configuration settings for the clock
+ *
+ */
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache the new config to reduce sync requirements */
+	uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
+
+	/* Select the desired generic clock generator */
+	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+
+	/* Disable generic clock channel */
+	system_gclk_chan_disable(channel);
+
+	/* Write the new configuration */
+	GCLK->CLKCTRL.reg = new_clkctrl_config;
+}
+
+/**
+ * \brief Enables a Generic Clock that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock that was previously
+ * configured via a call to \ref system_gclk_chan_set_config().
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_enable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Enable the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock that was previously started
+ * via a call to \ref system_gclk_chan_enable().
+ *
+ * \param[in] channel  Generic Clock channel to disable
+ */
+void system_gclk_chan_disable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Sanity check WRTLOCK */
+	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+
+	/* Switch to known-working source so that the channel can be disabled */
+	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+	GCLK->CLKCTRL.bit.GEN = 0;
+
+	/* Disable the generic clock */
+	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	/* Restore previous configured clock generator */
+	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is enabled
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock channel is enabled
+ * \retval false The Generic Clock channel is disabled
+ */
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	enabled = GCLK->CLKCTRL.bit.CLKEN;
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Locks a Generic Clock channel from further configuration writes.
+ *
+ * Locks a generic clock channel from further configuration writes. It is only
+ * possible to unlock the channel configuration through a power on reset.
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_lock(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Lock the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is locked.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The lock status.
+ * \retval true The Generic Clock channel is locked
+ * \retval false The Generic Clock channel is not locked
+ */
+bool system_gclk_chan_is_locked(
+		const uint8_t channel)
+{
+	bool locked;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	locked = GCLK->CLKCTRL.bit.WRTLOCK;
+
+	system_interrupt_leave_critical_section();
+
+	return locked;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock channel.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * channel, used as a source to a device peripheral module.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The frequency of the generic clock channel, in Hz.
+ */
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel)
+{
+	uint8_t gen_id;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	gen_id = GCLK->CLKCTRL.bit.GEN;
+
+	system_interrupt_leave_critical_section();
+
+	/* Return the clock speed of the associated GCLK generator */
+	return system_gclk_gen_get_hz(gen_id);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/module_config/conf_clocks.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/module_config/conf_clocks.h
new file mode 100644
index 0000000000..5f51a8e926
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/module_config/conf_clocks.h
@@ -0,0 +1,170 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 Clock configuration
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+#  define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+#  define CONF_CLOCK_FLASH_WAIT_STATES            0
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+#  define CONF_CLOCK_XOSC32K_ENABLE               false
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            true
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       false
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+#  define CONF_CLOCK_DFLL_ENABLE                  false
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
+#  define CONF_CLOCK_DFLL_ON_DEMAND               false
+
+/* DFLL open loop mode configuration */
+#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)
+
+/* DFLL closed loop mode configuration */
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         1465 /* (48000000 / 32768) */
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)
+
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 */
+#  define CONF_CLOCK_GCLK_1_ENABLE                false
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                false
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             32
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 */
+#  define CONF_CLOCK_GCLK_3_ENABLE                false
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 4 */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
new file mode 100644
index 0000000000..115149730f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
@@ -0,0 +1,1038 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Clock Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+#include <conf_clocks.h>
+#include <system.h>
+
+#ifndef SYSCTRL_FUSES_OSC32K_ADDR
+#if (SAMR21) || (SAMD) || (SAMHA1)
+#  define SYSCTRL_FUSES_OSC32K_ADDR FUSES_OSC32K_CAL_ADDR
+#  define SYSCTRL_FUSES_OSC32K_Pos  FUSES_OSC32K_CAL_Pos
+#elif (SAML21)
+#  define SYSCTRL_FUSES_OSC32K_ADDR NVMCTRL_OTP4
+#  define SYSCTRL_FUSES_OSC32K_Pos  6
+
+#else
+#  define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR
+#  define SYSCTRL_FUSES_OSC32K_Pos  SYSCTRL_FUSES_OSC32K_CAL_Pos
+#endif
+#endif
+
+/**
+ * \internal
+ * \brief DFLL-specific data container.
+ */
+struct _system_clock_dfll_config {
+	uint32_t control;
+	uint32_t val;
+	uint32_t mul;
+};
+
+/**
+ * \internal
+ * \brief DPLL-specific data container.
+ */
+struct _system_clock_dpll_config {
+	uint32_t frequency;
+};
+
+
+/**
+ * \internal
+ * \brief XOSC-specific data container.
+ */
+struct _system_clock_xosc_config {
+	uint32_t frequency;
+};
+
+/**
+ * \internal
+ * \brief System clock module data container.
+ */
+struct _system_clock_module {
+	volatile struct _system_clock_dfll_config dfll;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	volatile struct _system_clock_dpll_config dpll;
+#endif
+
+	volatile struct _system_clock_xosc_config xosc;
+	volatile struct _system_clock_xosc_config xosc32k;
+};
+
+/**
+ * \internal
+ * \brief Internal module instance to cache configuration values.
+ */
+static struct _system_clock_module _system_clock_inst = {
+		.dfll = {
+			.control     = 0,
+			.val     = 0,
+			.mul     = 0,
+		},
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+		.dpll = {
+			.frequency   = 0,
+		},
+#endif
+		.xosc = {
+			.frequency   = 0,
+		},
+		.xosc32k = {
+			.frequency   = 0,
+		},
+	};
+
+/**
+ * \internal
+ * \brief Wait for sync to the DFLL control registers.
+ */
+static inline void _system_dfll_wait_for_sync(void)
+{
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
+		/* Wait for DFLL sync */
+	}
+}
+
+/**
+ * \internal
+ * \brief Wait for sync to the OSC32K control registers.
+ */
+static inline void _system_osc32k_wait_for_sync(void)
+{
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
+		/* Wait for OSC32K sync */
+	}
+}
+
+static inline void _system_clock_source_dfll_set_config_errata_9905(void)
+{
+
+	/* Disable ONDEMAND mode while writing configurations */
+	SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
+	_system_dfll_wait_for_sync();
+
+	SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
+	SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
+
+	/* Write full configuration to DFLL control register */
+	SYSCTRL->DFLLCTRL.reg = 0;
+	_system_dfll_wait_for_sync();
+	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+}
+
+/**
+ * \brief Retrieve the frequency of a clock source.
+ *
+ * Determines the current operating frequency of a given clock source.
+ *
+ * \param[in] clock_source  Clock source to get the frequency
+ *
+ * \returns Frequency of the given clock source, in Hz.
+ */
+uint32_t system_clock_source_get_hz(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		return _system_clock_inst.xosc.frequency;
+
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		return 32768UL;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		return 32768UL;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		return _system_clock_inst.xosc32k.frequency;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+
+		/* Check if the DFLL has been configured */
+		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+			return 0;
+
+		/* Make sure that the DFLL module is ready */
+		_system_dfll_wait_for_sync();
+
+		/* Check if operating in closed loop mode */
+		if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) {
+			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+					(_system_clock_inst.dfll.mul & 0xffff);
+		}
+
+		return 48000000UL;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	case SYSTEM_CLOCK_SOURCE_DPLL:
+		if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
+			return 0;
+		}
+
+		return _system_clock_inst.dpll.frequency;
+#endif
+
+	default:
+		return 0;
+	}
+}
+
+/**
+ * \brief Configure the internal OSC8M oscillator clock source.
+ *
+ * Configures the 8MHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config  OSC8M configuration structure containing the new config
+ */
+void system_clock_source_osc8m_set_config(
+		struct system_clock_source_osc8m_config *const config)
+{
+	SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
+
+	/* Use temporary struct to reduce register access */
+	temp.bit.PRESC    = config->prescaler;
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+
+	SYSCTRL->OSC8M = temp;
+}
+
+/**
+ * \brief Configure the internal OSC32K oscillator clock source.
+ *
+ * Configures the 32KHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config  OSC32K configuration structure containing the new config
+ */
+void system_clock_source_osc32k_set_config(
+		struct system_clock_source_osc32k_config *const config)
+{
+	SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
+
+	/* Update settings via a temporary struct to reduce register access */
+	temp.bit.EN1K     = config->enable_1khz_output;
+	temp.bit.EN32K    = config->enable_32khz_output;
+	temp.bit.STARTUP  = config->startup_time;
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+	temp.bit.WRTLOCK  = config->write_once;
+
+	SYSCTRL->OSC32K  = temp;
+}
+
+/**
+ * \brief Configure the external oscillator clock source.
+ *
+ * Configures the external oscillator clock source with the given configuration
+ * settings.
+ *
+ * \param[in] config  External oscillator configuration structure containing
+ *                    the new config
+ */
+void system_clock_source_xosc_set_config(
+		struct system_clock_source_xosc_config *const config)
+{
+	SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
+
+	temp.bit.STARTUP = config->startup_time;
+
+	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+		temp.bit.XTALEN = 1;
+	} else {
+		temp.bit.XTALEN = 0;
+	}
+
+	temp.bit.AMPGC = config->auto_gain_control;
+
+	/* Set gain if automatic gain control is not selected */
+	if (!config->auto_gain_control) {
+		if (config->frequency <= 2000000) {
+			temp.bit.GAIN = 0;
+		} else if (config->frequency <= 4000000) {
+			temp.bit.GAIN = 1;
+		} else if (config->frequency <= 8000000) {
+			temp.bit.GAIN = 2;
+		} else if (config->frequency <= 16000000) {
+			temp.bit.GAIN = 3;
+		} else if (config->frequency <= 32000000) {
+			temp.bit.GAIN = 4;
+		}
+
+	}
+
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+
+	/* Store XOSC frequency for internal use */
+	_system_clock_inst.xosc.frequency = config->frequency;
+
+	SYSCTRL->XOSC = temp;
+}
+
+/**
+ * \brief Configure the XOSC32K external 32KHz oscillator clock source.
+ *
+ * Configures the external 32KHz oscillator clock source with the given
+ * configuration settings.
+ *
+ * \param[in] config  XOSC32K configuration structure containing the new config
+ */
+void system_clock_source_xosc32k_set_config(
+		struct system_clock_source_xosc32k_config *const config)
+{
+	SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
+
+	temp.bit.STARTUP = config->startup_time;
+
+	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+		temp.bit.XTALEN = 1;
+	} else {
+		temp.bit.XTALEN = 0;
+	}
+
+	temp.bit.AAMPEN = config->auto_gain_control;
+	temp.bit.EN1K = config->enable_1khz_output;
+	temp.bit.EN32K = config->enable_32khz_output;
+
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+	temp.bit.WRTLOCK  = config->write_once;
+
+	/* Cache the new frequency in case the user needs to check the current
+	 * operating frequency later */
+	_system_clock_inst.xosc32k.frequency = config->frequency;
+
+	SYSCTRL->XOSC32K = temp;
+}
+
+/**
+ * \brief Configure the DFLL clock source.
+ *
+ * Configures the Digital Frequency Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DFLL will be running when this function returns, as the DFLL module
+ *       needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config  DFLL configuration structure containing the new config
+ */
+void system_clock_source_dfll_set_config(
+		struct system_clock_source_dfll_config *const config)
+{
+	_system_clock_inst.dfll.val =
+			SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |
+			SYSCTRL_DFLLVAL_FINE(config->fine_value);
+
+	_system_clock_inst.dfll.control =
+			(uint32_t)config->wakeup_lock     |
+			(uint32_t)config->stable_tracking |
+			(uint32_t)config->quick_lock      |
+			(uint32_t)config->chill_cycle     |
+			((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
+
+	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+
+		_system_clock_inst.dfll.mul =
+				SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
+				SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
+				SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+		/* Enable the closed loop mode */
+		_system_clock_inst.dfll.control |= config->loop_mode;
+	}
+	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
+
+		_system_clock_inst.dfll.mul =
+				SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
+				SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
+				SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+		/* Enable the USB recovery mode */
+		_system_clock_inst.dfll.control |= config->loop_mode |
+				SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_BPLCKC;
+	}
+}
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+/**
+ * \brief Configure the DPLL clock source.
+ *
+ * Configures the Digital Phase-Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DPLL will be running when this function returns, as the DPLL module
+ *       needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config  DPLL configuration structure containing the new config
+ */
+void system_clock_source_dpll_set_config(
+		struct system_clock_source_dpll_config *const config)
+{
+
+	uint32_t tmpldr;
+	uint8_t  tmpldrfrac;
+	uint32_t refclk;
+
+	refclk = config->reference_frequency;
+
+	/* Only reference clock REF1 can be divided */
+	if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) {
+		refclk = refclk / (2 * (config->reference_divider + 1));
+	}
+
+	/* Calculate LDRFRAC and LDR */
+	tmpldr = (config->output_frequency << 4) / refclk;
+	tmpldrfrac = tmpldr & 0x0f;
+	tmpldr = (tmpldr >> 4) - 1;
+
+	SYSCTRL->DPLLCTRLA.reg =
+			((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
+			((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);
+
+	SYSCTRL->DPLLRATIO.reg =
+			SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) |
+			SYSCTRL_DPLLRATIO_LDR(tmpldr);
+
+	SYSCTRL->DPLLCTRLB.reg =
+			SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) |
+			((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
+			SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) |
+			SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) |
+			((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) |
+			((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
+			SYSCTRL_DPLLCTRLB_FILTER(config->filter);
+
+	/*
+	 * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16)
+	 */
+	_system_clock_inst.dpll.frequency =
+			(refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4;
+}
+#endif
+
+/**
+ * \brief Writes the calibration values for a given oscillator clock source.
+ *
+ * Writes an oscillator calibration value to the given oscillator control
+ * registers. The acceptable ranges are:
+ *
+ * For OSC32K:
+ *  - 7 bits (max value 128)
+ * For OSC8MHZ:
+ *  - 8 bits (Max value 255)
+ * For OSCULP:
+ *  - 5 bits (Max value 32)
+ *
+ * \note The frequency range parameter applies only when configuring the 8MHz
+ *       oscillator and will be ignored for the other oscillators.
+ *
+ * \param[in] clock_source       Clock source to calibrate
+ * \param[in] calibration_value  Calibration value to write
+ * \param[in] freq_range         Frequency range (8MHz oscillator only)
+ *
+ * \retval STATUS_OK               The calibration value was written
+ *                                 successfully.
+ * \retval STATUS_ERR_INVALID_ARG  The setting is not valid for selected clock
+ *                                 source.
+ */
+enum status_code system_clock_source_write_calibration(
+		const enum system_clock_source clock_source,
+		const uint16_t calibration_value,
+		const uint8_t freq_range)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+
+		if (calibration_value > 0xfff || freq_range > 4) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		SYSCTRL->OSC8M.bit.CALIB  = calibration_value;
+		SYSCTRL->OSC8M.bit.FRANGE = freq_range;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+
+		if (calibration_value > 128) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		_system_osc32k_wait_for_sync();
+		SYSCTRL->OSC32K.bit.CALIB = calibration_value;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+
+		if (calibration_value > 32) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
+		break;
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+		break;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables a clock source.
+ *
+ * Enables a clock source which has been previously configured.
+ *
+ * \param[in] clock_source       Clock source to enable
+ *
+ * \retval STATUS_OK               Clock source was enabled successfully and
+ *                                 is ready
+ * \retval STATUS_ERR_INVALID_ARG  The clock source is not available on this
+ *                                 device
+ */
+enum status_code system_clock_source_enable(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+		return STATUS_OK;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
+		_system_clock_source_dfll_set_config_errata_9905();
+		break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	case SYSTEM_CLOCK_SOURCE_DPLL:
+		SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
+		break;
+#endif
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Always enabled */
+		return STATUS_OK;
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables a clock source.
+ *
+ * Disables a clock source that was previously enabled.
+ *
+ * \param[in] clock_source  Clock source to disable
+ *
+ * \retval STATUS_OK               Clock source was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  An invalid or unavailable clock source was
+ *                                 given
+ */
+enum status_code system_clock_source_disable(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		_system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
+		SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+		break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	case SYSTEM_CLOCK_SOURCE_DPLL:
+		SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
+		break;
+#endif
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Not possible to disable */
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Checks if a clock source is ready.
+ *
+ * Checks if a given clock source is ready to be used.
+ *
+ * \param[in] clock_source  Clock source to check if ready
+ *
+ * \returns Ready state of the given clock source.
+ *
+ * \retval true   Clock source is enabled and ready
+ * \retval false  Clock source is disabled or not yet ready
+ */
+bool system_clock_source_is_ready(
+		const enum system_clock_source clock_source)
+{
+	uint32_t mask = 0;
+
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		mask = SYSCTRL_PCLKSR_OSC8MRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		mask = SYSCTRL_PCLKSR_OSC32KRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		mask = SYSCTRL_PCLKSR_XOSCRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		mask = SYSCTRL_PCLKSR_XOSC32KRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+			mask = (SYSCTRL_PCLKSR_DFLLRDY |
+			        SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
+		} else {
+			mask = SYSCTRL_PCLKSR_DFLLRDY;
+		}
+		break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	case SYSTEM_CLOCK_SOURCE_DPLL:
+		return ((SYSCTRL->DPLLSTATUS.reg &
+				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
+				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
+#endif
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Not possible to disable */
+		return true;
+
+	default:
+		return false;
+	}
+
+	return ((SYSCTRL->PCLKSR.reg & mask) == mask);
+}
+
+/* Include some checks for conf_clocks.h validation */
+#include "clock_config_check.h"
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
+ */
+#  define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
+	if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
+		struct system_gclk_gen_config gclk_conf;                          \
+		system_gclk_gen_get_config_defaults(&gclk_conf);                  \
+		gclk_conf.source_clock    = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE;   \
+		gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER;      \
+		gclk_conf.run_in_standby  = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
+		gclk_conf.output_enable   = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE;  \
+		system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf);       \
+		system_gclk_gen_enable(GCLK_GENERATOR_##n);                       \
+	}
+
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h,
+ * provided that it is not the main Generic Clock Generator channel.
+ */
+#  define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
+		if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
+#endif
+
+/** \internal
+ *
+ * Switch all peripheral clock to a not enabled general clock
+ * to save power.
+ */
+static void _switch_peripheral_gclk(void)
+{
+	uint32_t gclk_id;
+	struct system_gclk_chan_config gclk_conf;
+
+#if CONF_CLOCK_GCLK_1_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_1;
+#elif CONF_CLOCK_GCLK_2_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_2;
+#elif CONF_CLOCK_GCLK_3_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_3;
+#elif CONF_CLOCK_GCLK_4_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_4;
+#elif CONF_CLOCK_GCLK_5_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_5;
+#elif CONF_CLOCK_GCLK_6_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_6;
+#elif CONF_CLOCK_GCLK_7_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_7;
+#else
+	gclk_conf.source_generator = GCLK_GENERATOR_7;
+#endif
+
+	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
+		system_gclk_chan_set_config(gclk_id, &gclk_conf);
+	}
+}
+
+/**
+ * \brief Initialize clock system based on the configuration in conf_clocks.h.
+ *
+ * This function will apply the settings in conf_clocks.h when run from the user
+ * application. All clock sources and GCLK generators are running when this function
+ * returns.
+ *
+ * \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
+ * the OSC8M default enable can be disabled after system_clock_init. Make sure the
+ * clock switch successfully before disabling OSC8M.
+ */
+void system_clock_init(void)
+{
+	/* Various bits in the INTFLAG register can be set to one at startup.
+	   This will ensure that these bits are cleared */
+	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
+			SYSCTRL_INTFLAG_DFLLRDY;
+
+	system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
+
+	/* Switch all peripheral clock to a not enabled general clock to save power. */
+	_switch_peripheral_gclk();
+
+	/* XOSC */
+#if CONF_CLOCK_XOSC_ENABLE == true
+	struct system_clock_source_xosc_config xosc_conf;
+	system_clock_source_xosc_get_config_defaults(&xosc_conf);
+
+	xosc_conf.external_clock    = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
+	xosc_conf.startup_time      = CONF_CLOCK_XOSC_STARTUP_TIME;
+	xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
+	xosc_conf.frequency         = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
+	xosc_conf.on_demand         = CONF_CLOCK_XOSC_ON_DEMAND;
+	xosc_conf.run_in_standby    = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
+
+	system_clock_source_xosc_set_config(&xosc_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
+#endif
+
+
+	/* XOSC32K */
+#if CONF_CLOCK_XOSC32K_ENABLE == true
+	struct system_clock_source_xosc32k_config xosc32k_conf;
+	system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
+
+	xosc32k_conf.frequency           = 32768UL;
+	xosc32k_conf.external_clock      = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
+	xosc32k_conf.startup_time        = CONF_CLOCK_XOSC32K_STARTUP_TIME;
+	xosc32k_conf.auto_gain_control   = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
+	xosc32k_conf.enable_1khz_output  = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
+	xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
+	xosc32k_conf.on_demand           = false;
+	xosc32k_conf.run_in_standby      = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
+
+	system_clock_source_xosc32k_set_config(&xosc32k_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+	if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
+		SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
+	}
+#endif
+
+
+	/* OSCK32K */
+#if CONF_CLOCK_OSC32K_ENABLE == true
+	SYSCTRL->OSC32K.bit.CALIB =
+			((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> 
+			SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful);
+
+	struct system_clock_source_osc32k_config osc32k_conf;
+	system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
+
+	osc32k_conf.startup_time        = CONF_CLOCK_OSC32K_STARTUP_TIME;
+	osc32k_conf.enable_1khz_output  = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
+	osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
+	osc32k_conf.on_demand           = CONF_CLOCK_OSC32K_ON_DEMAND;
+	osc32k_conf.run_in_standby      = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
+
+	system_clock_source_osc32k_set_config(&osc32k_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
+#endif
+
+
+	/* DFLL Config (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+	struct system_clock_source_dfll_config dfll_conf;
+	system_clock_source_dfll_get_config_defaults(&dfll_conf);
+
+	dfll_conf.loop_mode      = CONF_CLOCK_DFLL_LOOP_MODE;
+	dfll_conf.on_demand      = false;
+
+	/* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping 
+	   in DFLL.COARSE helps to output a frequency close to 48 MHz.*/
+#define NVM_DFLL_COARSE_POS    58 /* DFLL48M Coarse calibration value bit position.*/
+#define NVM_DFLL_COARSE_SIZE   6  /* DFLL48M Coarse calibration value bit size.*/
+
+	uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+			+ (NVM_DFLL_COARSE_POS / 32))
+		>> (NVM_DFLL_COARSE_POS % 32))
+		& ((1 << NVM_DFLL_COARSE_SIZE) - 1);
+	/* In some revision chip, the coarse calibration value is not correct. */
+	if (coarse == 0x3f) {
+		coarse = 0x1f;
+	}
+	dfll_conf.coarse_value = coarse;
+
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
+		dfll_conf.fine_value   = CONF_CLOCK_DFLL_FINE_VALUE;
+	}
+
+#  if CONF_CLOCK_DFLL_QUICK_LOCK == true
+	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+#  else
+	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
+#  endif
+
+#  if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
+	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+#  else
+	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+#  endif
+
+#  if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
+	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+#  else
+	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
+#  endif
+
+#  if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
+	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+#  else
+	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+#  endif
+
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+		dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
+	}
+
+	dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
+	dfll_conf.fine_max_step   = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
+
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
+		dfll_conf.fine_max_step   = 10; 
+		dfll_conf.fine_value   = 0x1ff;
+		dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+		dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+		dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+		dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+
+		dfll_conf.multiply_factor = 48000;
+	}
+
+	system_clock_source_dfll_set_config(&dfll_conf);
+#endif
+
+
+	/* OSC8M */
+	struct system_clock_source_osc8m_config osc8m_conf;
+	system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
+
+	osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
+	osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
+	osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
+
+	system_clock_source_osc8m_set_config(&osc8m_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
+
+
+	/* GCLK */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+	system_gclk_init();
+
+	/* Configure all GCLK generators except for the main generator, which
+	 * is configured later after all other clock systems are set up */
+	MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
+
+#  if CONF_CLOCK_DFLL_ENABLE == true
+	/* Enable DFLL reference clock if in closed loop mode */
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+		struct system_gclk_chan_config dfll_gclk_chan_conf;
+
+		system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
+		dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
+		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
+		system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
+	}
+#  endif
+
+#  if CONF_CLOCK_DPLL_ENABLE == true
+	/* Enable DPLL internal lock timer and reference clock */
+	struct system_gclk_chan_config dpll_gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf);
+	if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) {
+		dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR;
+		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf);
+		system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K);
+	}
+
+	if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) {
+		dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR;
+		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf);
+		system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL);
+	}
+#  endif
+#endif
+
+
+	/* DFLL Enable (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+	if (CONF_CLOCK_DFLL_ON_DEMAND) {
+		SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
+	}
+#endif
+
+	/* DPLL */
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+#  if (CONF_CLOCK_DPLL_ENABLE == true)
+
+	/* Enable DPLL reference clock */
+	if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) {
+		/* XOSC32K should have been enabled for DPLL_REF0 */
+		Assert(CONF_CLOCK_XOSC32K_ENABLE);
+	} else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) {
+		/* XOSC should have been enabled for DPLL_REF1 */
+		Assert(CONF_CLOCK_XOSC_ENABLE);
+	}
+	else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) {
+		/* GCLK should have been enabled */
+		Assert(CONF_CLOCK_CONFIGURE_GCLK);
+	}
+	else {
+		Assert(false);
+	}
+
+	struct system_clock_source_dpll_config dpll_config;
+	system_clock_source_dpll_get_config_defaults(&dpll_config);
+
+	dpll_config.on_demand        = false;
+	dpll_config.run_in_standby   = CONF_CLOCK_DPLL_RUN_IN_STANDBY;
+	dpll_config.lock_bypass      = CONF_CLOCK_DPLL_LOCK_BYPASS;
+	dpll_config.wake_up_fast     = CONF_CLOCK_DPLL_WAKE_UP_FAST;
+	dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE;
+
+	dpll_config.filter           = CONF_CLOCK_DPLL_FILTER;
+	dpll_config.lock_time        = CONF_CLOCK_DPLL_LOCK_TIME;
+
+	dpll_config.reference_clock     = CONF_CLOCK_DPLL_REFERENCE_CLOCK;
+	dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY;
+	dpll_config.reference_divider   = CONF_CLOCK_DPLL_REFERENCE_DIVIDER;
+	dpll_config.output_frequency    = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY;
+
+	system_clock_source_dpll_set_config(&dpll_config);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));
+	if (CONF_CLOCK_DPLL_ON_DEMAND) {
+		SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1;
+	}
+
+#  endif
+#endif
+
+	/* CPU and BUS clocks */
+	system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
+
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
+
+	/* GCLK 0 */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+	/* Configure the main GCLK last as it might depend on other generators */
+	_CONF_CLOCK_GCLK_CONFIG(0, ~);
+#endif
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
new file mode 100644
index 0000000000..56fa2c3923
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
@@ -0,0 +1,454 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Clock Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CLOCK_CONFIG_CHECK_H
+#  define CLOCK_CONFIG_CHECK_H
+
+#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
+#  error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CPU_DIVIDER)
+#  error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBA_DIVIDER)
+#  error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBB_DIVIDER)
+#  error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBC_DIVIDER)
+#  error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_PRESCALER)
+#  error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)
+#  error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ENABLE)
+#  error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
+#  error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
+#  error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
+#  error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
+#  error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)
+#  error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
+#  error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE)
+#  error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
+#  error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE)
+#  error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
+#  error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
+#  error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
+#  error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
+#  error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
+#  error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
+#  error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
+#  error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
+#  error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ENABLE)
+#  error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ON_DEMAND)
+#  error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY)
+#  error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS)
+#  error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST)
+#  error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE)
+#  error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_TIME)
+#  error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK)
+#  error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_FILTER)
+#  error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY)
+#  error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER)
+#  error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY)
+#  error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR)
+#  error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
+#  error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
+#  error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
+#  error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
+#  error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
+#  error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
+#  error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
+#  error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
+#  error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
+#  error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
+#  error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
+#  error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
+#  error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
+#  error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
+#  error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
+#  error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
+#  error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
+#  error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_ENABLE)
+#  error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_PRESCALER)
+#  error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#endif /* CLOCK_CONFIG_CHECK_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
new file mode 100644
index 0000000000..db993049a6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
@@ -0,0 +1,1493 @@
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
+#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management (SYSTEM CLOCK) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's clocking related functions. This includes
+ * the various clock sources, bus clocks, and generic clocks within the device,
+ * with functions to manage the enabling, disabling, source selection, and
+ * prescaling of clocks to various internal peripherals.
+ *
+ * The following peripherals are used by this module:
+ *
+ * - GCLK (Generic Clock Management)
+ * - PM (Power Management)
+ * - SYSCTRL (Clock Source Control)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_clock_prerequisites
+ *  - \ref asfdoc_sam0_system_clock_module_overview
+ *  - \ref asfdoc_sam0_system_clock_special_considerations
+ *  - \ref asfdoc_sam0_system_clock_extra_info
+ *  - \ref asfdoc_sam0_system_clock_examples
+ *  - \ref asfdoc_sam0_system_clock_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_clock_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_module_overview Module Overview
+ * The SAM devices contain a sophisticated clocking system, which is designed
+ * to give the maximum flexibility to the user application. This system allows
+ * a system designer to tune the performance and power consumption of the device
+ * in a dynamic manner, to achieve the best trade-off between the two for a
+ * particular application.
+ *
+ * This driver provides a set of functions for the configuration and management
+ * of the various clock related functionality within the device.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
+ * <table>
+ *	<tr>
+ *		<th>Driver Feature Macro</th>
+ *		<th>Supported devices</th>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_SYSTEM_CLOCK_DPLL</td>
+ *		<td>SAM D21, SAM R21, SAM D10, SAM D11, SAM DA1</td>
+ *	</tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
+ * The SAM devices have a number of master clock source modules, each of
+ * which being capable of producing a stabilized output frequency, which can then
+ * be fed into the various peripherals and modules within the device.
+ *
+ * Possible clock source modules include internal R/C oscillators, internal
+ * DFLL modules, as well as external crystal oscillators and/or clock inputs.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
+ * The CPU and AHB/APBx buses are clocked by the same physical clock source
+ * (referred in this module as the Main Clock), however the APBx buses may
+ * have additional prescaler division ratios set to give each peripheral bus a
+ * different clock speed.
+ *
+ * The general main clock tree for the CPU and associated buses is shown in
+ * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_clock_tree
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   clk_src [label="Clock Sources", shape=none, height=0];
+ *   node [label="CPU Bus" shape=ellipse] cpu_bus;
+ *   node [label="AHB Bus" shape=ellipse] ahb_bus;
+ *   node [label="APBA Bus" shape=ellipse] apb_a_bus;
+ *   node [label="APBB Bus" shape=ellipse] apb_b_bus;
+ *   node [label="APBC Bus" shape=ellipse] apb_c_bus;
+ *   node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
+ *   node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
+ *   node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
+ *   node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
+ *   node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
+ *
+ *   clk_src         -> main_clock_mux;
+ *   main_clock_mux  -> main_prescaler;
+ *   main_prescaler  -> cpu_bus;
+ *   main_prescaler  -> ahb_bus;
+ *   main_prescaler  -> apb_a_prescaler;
+ *   main_prescaler  -> apb_b_prescaler;
+ *   main_prescaler  -> apb_c_prescaler;
+ *   apb_a_prescaler -> apb_a_bus;
+ *   apb_b_prescaler -> apb_b_bus;
+ *   apb_c_prescaler -> apb_c_bus;
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
+ * To save power, the input clock to one or more peripherals on the AHB and APBx
+ * buses can be masked away - when masked, no clock is passed into the module.
+ * Disabling of clocks of unused modules will prevent all access to the masked
+ * module, but will reduce the overall device power consumption.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
+ * Within the SAM devices there are a number of Generic Clocks; these are used to
+ * provide clocks to the various peripheral clock domains in the device in a
+ * standardized manner. One or more master source clocks can be selected as the
+ * input clock to a Generic Clock Generator, which can prescale down the input
+ * frequency to a slower rate for use in a peripheral.
+ *
+ * Additionally, a number of individually selectable Generic Clock Channels are
+ * provided, which multiplex and gate the various generator outputs for one or
+ * more peripherals within the device. This setup allows for a single common
+ * generator to feed one or more channels, which can then be enabled or disabled
+ * individually as required.
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_overview
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="Clock\nSource a" shape=square] system_clock_source;
+ *   node [label="Generator 1" shape=square] clock_gen;
+ *   node [label="Channel x" shape=square] clock_chan0;
+ *   node [label="Channel y" shape=square] clock_chan1;
+ *   node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
+ *   node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
+ *
+ *   system_clock_source -> clock_gen;
+ *   clock_gen   -> clock_chan0;
+ *   clock_chan0 -> peripheral0;
+ *   clock_gen   -> clock_chan1;
+ *   clock_chan1 -> peripheral1;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
+ * An example setup of a complete clock chain within the device is shown in
+ * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_example_fig
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="External\nOscillator" shape=square] system_clock_source0;
+ *   node [label="Generator 0" shape=square] clock_gen0;
+ *   node [label="Channel x" shape=square] clock_chan0;
+ *   node [label="Core CPU" shape=ellipse  style=filled fillcolor=lightgray] peripheral0;
+ *
+ *   system_clock_source0 -> clock_gen0;
+ *   clock_gen0    -> clock_chan0;
+ *   clock_chan0   -> peripheral0;
+ *   node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
+ *   node [label="Generator 1" shape=square] clock_gen1;
+ *   node [label="Channel y" shape=square] clock_chan1;
+ *   node [label="Channel z" shape=square] clock_chan2;
+ *   node [label="SERCOM\nModule" shape=ellipse  style=filled fillcolor=lightgray] peripheral1;
+ *   node [label="Timer\nModule" shape=ellipse  style=filled fillcolor=lightgray] peripheral2;
+ *
+ *   system_clock_source1 -> clock_gen1;
+ *   clock_gen1    -> clock_chan1;
+ *   clock_gen1    -> clock_chan2;
+ *   clock_chan1   -> peripheral1;
+ *   clock_chan2   -> peripheral2;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
+ * Each Generic Clock generator within the device can source its input clock
+ * from one of the provided Source Clocks, and prescale the output for one or
+ * more Generic Clock Channels in a one-to-many relationship. The generators
+ * thus allow for several clocks to be generated of different frequencies,
+ * power usages, and accuracies, which can be turned on and off individually to
+ * disable the clocks to multiple peripherals as a group.
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
+ * To connect a Generic Clock Generator to a peripheral within the
+ * device, a Generic Clock Channel is used. Each peripheral or
+ * peripheral group has an associated Generic Clock Channel, which serves as the
+ * clock input for the peripheral(s). To supply a clock to the peripheral
+ * module(s), the associated channel must be connected to a running Generic
+ * Clock Generator and the channel enabled.
+ *
+ * \section asfdoc_sam0_system_clock_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
+ *  - \ref asfdoc_sam0_system_clock_extra_acronyms
+ *  - \ref asfdoc_sam0_system_clock_extra_dependencies
+ *  - \ref asfdoc_sam0_system_clock_extra_errata
+ *  - \ref asfdoc_sam0_system_clock_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_clock_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_clock_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <gclk.h>
+
+/**
+ * \name Driver Feature Definition
+ * Define system clock features set according to different device family.
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAMDA1) || (SAMHA1) || defined(__DOXYGEN__)
+/** Digital Phase Locked Loop (DPLL) feature support. */
+#  define FEATURE_SYSTEM_CLOCK_DPLL
+#endif
+/*@}*/
+
+/**
+ * \brief Available start-up times for the XOSC32K.
+ *
+ * Available external 32KHz oscillator start-up times, as a number of external
+ * clock cycles.
+ */
+enum system_xosc32k_startup {
+	/** Wait zero clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_0,
+	/** Wait 32 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_32,
+	/** Wait 2048 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_2048,
+	/** Wait 4096 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_4096,
+	/** Wait 16384 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_16384,
+	/** Wait 32768 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_32768,
+	/** Wait 65536 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_65536,
+	/** Wait 131072 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_131072,
+};
+
+/**
+ * \brief Available start-up times for the XOSC.
+ *
+ * Available external oscillator start-up times, as a number of external clock
+ * cycles.
+ */
+enum system_xosc_startup {
+	/** Wait one clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_1,
+	/** Wait two clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_2,
+	/** Wait four clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_4,
+	/** Wait eight clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_8,
+	/** Wait 16 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_16,
+	/** Wait 32 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_32,
+	/** Wait 64 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_64,
+	/** Wait 128 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_128,
+	/** Wait 256 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_256,
+	/** Wait 512 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_512,
+	/** Wait 1024 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_1024,
+	/** Wait 2048 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_2048,
+	/** Wait 4096 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_4096,
+	/** Wait 8192 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_8192,
+	/** Wait 16384 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_16384,
+	/** Wait 32768 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_32768,
+};
+
+/**
+ * \brief Available start-up times for the OSC32K.
+ *
+ * Available internal 32KHz oscillator start-up times, as a number of internal
+ * OSC32K clock cycles.
+ */
+enum system_osc32k_startup {
+	/** Wait three clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_3,
+	/** Wait four clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_4,
+	/** Wait six clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_6,
+	/** Wait ten clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_10,
+	/** Wait 18 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_18,
+	/** Wait 34 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_34,
+	/** Wait 66 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_66,
+	/** Wait 130 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_130,
+};
+
+/**
+ * \brief Division prescalers for the internal 8MHz system clock.
+ *
+ * Available prescalers for the internal 8MHz (nominal) system clock.
+ */
+enum system_osc8m_div {
+	/** Do not divide the 8MHz RC oscillator output */
+	SYSTEM_OSC8M_DIV_1,
+	/** Divide the 8MHz RC oscillator output by two */
+	SYSTEM_OSC8M_DIV_2,
+	/** Divide the 8MHz RC oscillator output by four */
+	SYSTEM_OSC8M_DIV_4,
+	/** Divide the 8MHz RC oscillator output by eight */
+	SYSTEM_OSC8M_DIV_8,
+};
+
+/**
+ * \brief Frequency range for the internal 8MHz RC oscillator.
+ *
+ * Internal 8MHz RC oscillator frequency range setting.
+ */
+enum system_osc8m_frequency_range {
+	/** Frequency range 4MHz to 6MHz */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
+	/** Frequency range 6MHz to 8MHz */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
+	/** Frequency range 8MHz to 11MHz */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
+	/** Frequency range 11MHz to 15MHz */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
+};
+
+/**
+ * \brief Main CPU and APB/AHB bus clock source prescaler values.
+ *
+ * Available division ratios for the CPU and APB/AHB bus clocks.
+ */
+enum system_main_clock_div {
+	/** Divide Main clock by one */
+	SYSTEM_MAIN_CLOCK_DIV_1,
+	/** Divide Main clock by two */
+	SYSTEM_MAIN_CLOCK_DIV_2,
+	/** Divide Main clock by four */
+	SYSTEM_MAIN_CLOCK_DIV_4,
+	/** Divide Main clock by eight */
+	SYSTEM_MAIN_CLOCK_DIV_8,
+	/** Divide Main clock by 16 */
+	SYSTEM_MAIN_CLOCK_DIV_16,
+	/** Divide Main clock by 32 */
+	SYSTEM_MAIN_CLOCK_DIV_32,
+	/** Divide Main clock by 64 */
+	SYSTEM_MAIN_CLOCK_DIV_64,
+	/** Divide Main clock by 128 */
+	SYSTEM_MAIN_CLOCK_DIV_128,
+};
+
+/**
+ * \brief External clock source types.
+ *
+ * Available external clock source types.
+ */
+enum system_clock_external {
+	/** The external clock source is a crystal oscillator */
+	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
+	/** The connected clock source is an external logic level clock signal */
+	SYSTEM_CLOCK_EXTERNAL_CLOCK,
+};
+
+/**
+ * \brief Operating modes of the DFLL clock source.
+ *
+ * Available operating modes of the DFLL clock source module.
+ */
+enum system_clock_dfll_loop_mode {
+	/** The DFLL is operating in open loop mode with no feedback */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
+	/** The DFLL is operating in closed loop mode with frequency feedback from
+	 *  a low frequency reference clock
+	 */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
+
+#ifdef SYSCTRL_DFLLCTRL_USBCRM
+	/** The DFLL is operating in USB recovery mode with frequency feedback
+	 *  from USB SOF.
+	 */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
+#endif
+};
+
+/**
+ * \brief Locking behavior for the DFLL during device wake-up.
+ *
+ * DFLL lock behavior modes on device wake-up from sleep.
+ */
+enum system_clock_dfll_wakeup_lock {
+	/** Keep DFLL lock when the device wakes from sleep */
+	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
+	/** Lose DFLL lock when the devices wakes from sleep */
+	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
+};
+
+/**
+ * \brief Fine tracking behavior for the DFLL once a lock has been acquired.
+ *
+ * DFLL fine tracking behavior modes after a lock has been acquired.
+ */
+enum system_clock_dfll_stable_tracking {
+	/** Keep tracking after the DFLL has gotten a fine lock */
+	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
+	/** Stop tracking after the DFLL has gotten a fine lock */
+	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
+};
+
+/**
+ * \brief Chill-cycle behavior of the DFLL module.
+ *
+ * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
+ * of time when the DFLL output frequency is not measured by the unit, to allow
+ * the output to stabilize after a change in the input clock source.
+ */
+enum system_clock_dfll_chill_cycle {
+	/** Enable a chill cycle, where the DFLL output frequency is not measured */
+	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
+	/** Disable a chill cycle, where the DFLL output frequency is not measured */
+	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
+};
+
+/**
+ * \brief QuickLock settings for the DFLL module.
+ *
+ * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
+ * the DFLL output frequency at the expense of accuracy.
+ */
+enum system_clock_dfll_quick_lock {
+	/** Enable the QuickLock feature for looser lock requirements on the DFLL */
+	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
+	/** Disable the QuickLock feature for strict lock requirements on the DFLL */
+	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
+};
+
+/**
+ * \brief Available clock sources in the system.
+ *
+ * Clock sources available to the GCLK generators.
+ */
+enum system_clock_source {
+	/** Internal 8MHz RC oscillator */
+	SYSTEM_CLOCK_SOURCE_OSC8M    = GCLK_SOURCE_OSC8M,
+	/** Internal 32KHz RC oscillator */
+	SYSTEM_CLOCK_SOURCE_OSC32K   = GCLK_SOURCE_OSC32K,
+	/** External oscillator */
+	SYSTEM_CLOCK_SOURCE_XOSC     = GCLK_SOURCE_XOSC ,
+	/** External 32KHz oscillator */
+	SYSTEM_CLOCK_SOURCE_XOSC32K  = GCLK_SOURCE_XOSC32K,
+	/** Digital Frequency Locked Loop (DFLL) */
+	SYSTEM_CLOCK_SOURCE_DFLL     = GCLK_SOURCE_DFLL48M,
+	/** Internal Ultra Low Power 32KHz oscillator */
+	SYSTEM_CLOCK_SOURCE_ULP32K   = GCLK_SOURCE_OSCULP32K,
+	/** Generator input pad */
+	SYSTEM_CLOCK_SOURCE_GCLKIN     = GCLK_SOURCE_GCLKIN,
+	/** Generic clock generator one output */
+	SYSTEM_CLOCK_SOURCE_GCLKGEN1   = GCLK_SOURCE_GCLKGEN1,
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	/** Digital Phase Locked Loop (DPLL).
+	 * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
+	 */
+	SYSTEM_CLOCK_SOURCE_DPLL     = GCLK_SOURCE_FDPLL,
+#endif
+};
+
+/**
+ * \brief List of APB peripheral buses.
+ *
+ * Available bus clock domains on the APB bus.
+ */
+enum system_clock_apb_bus {
+	/** Peripheral bus A on the APB bus */
+	SYSTEM_CLOCK_APB_APBA,
+	/** Peripheral bus B on the APB bus */
+	SYSTEM_CLOCK_APB_APBB,
+	/** Peripheral bus C on the APB bus */
+	SYSTEM_CLOCK_APB_APBC,
+};
+
+/**
+ * \brief Configuration structure for XOSC.
+ *
+ * External oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc_config {
+	/** External clock type */
+	enum system_clock_external external_clock;
+	/** Crystal oscillator start-up time */
+	enum system_xosc_startup startup_time;
+	/** Enable automatic amplitude gain control */
+	bool auto_gain_control;
+	/** External clock/crystal frequency */
+	uint32_t frequency;
+	/** Keep the XOSC enabled in standby sleep mode */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the XOSC won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for XOSC32K.
+ *
+ * External 32KHz oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc32k_config {
+	/** External clock type */
+	enum system_clock_external external_clock;
+	/** Crystal oscillator start-up time */
+	enum system_xosc32k_startup startup_time;
+	/** Enable automatic amplitude control */
+	bool auto_gain_control;
+	/** Enable 1KHz output */
+	bool enable_1khz_output;
+	/** Enable 32KHz output */
+	bool enable_32khz_output;
+	/** External clock/crystal frequency */
+	uint32_t frequency;
+	/** Keep the XOSC32K enabled in standby sleep mode */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the XOSC32K won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Lock configuration after it has been written,
+	 *  a device reset will release the lock */
+	bool write_once;
+};
+
+/**
+ * \brief Configuration structure for OSC8M.
+ *
+ * Internal 8MHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc8m_config {
+	/** Internal 8MHz RC oscillator prescaler */
+	enum system_osc8m_div prescaler;
+	/** Keep the OSC8M enabled in standby sleep mode */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the OSC8M won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for OSC32K.
+ *
+ * Internal 32KHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc32k_config {
+	/** Startup time */
+	enum system_osc32k_startup startup_time;
+	/** Enable 1KHz output */
+	bool enable_1khz_output;
+	/** Enable 32KHz output */
+	bool enable_32khz_output;
+	/** Keep the OSC32K enabled in standby sleep mode */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the OSC32K won't run
+	 * until requested by a peripheral */
+	bool on_demand;
+	/** Lock configuration after it has been written,
+	 *  a device reset will release the lock */
+	bool write_once;
+};
+
+/**
+ * \brief Configuration structure for DFLL.
+ *
+ * DFLL oscillator configuration structure.
+ */
+struct system_clock_source_dfll_config {
+	/** Loop mode */
+	enum system_clock_dfll_loop_mode loop_mode;
+	/** Run On Demand. If this is set the DFLL won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Enable Quick Lock */
+	enum system_clock_dfll_quick_lock quick_lock;
+	/** Enable Chill Cycle */
+	enum system_clock_dfll_chill_cycle chill_cycle;
+	/** DFLL lock state on wakeup */
+	enum system_clock_dfll_wakeup_lock wakeup_lock;
+	/** DFLL tracking after fine lock */
+	enum system_clock_dfll_stable_tracking stable_tracking;
+	/** Coarse calibration value (Open loop mode) */
+	uint8_t coarse_value;
+	/** Fine calibration value (Open loop mode) */
+	uint16_t fine_value;
+	/** Coarse adjustment maximum step size (Closed loop mode) */
+	uint8_t coarse_max_step;
+	/** Fine adjustment maximum step size (Closed loop mode) */
+	uint16_t fine_max_step;
+	/** DFLL multiply factor (Closed loop mode */
+	uint16_t multiply_factor;
+};
+
+/**
+ * \name External Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external oscillator module:
+ *   - External Crystal
+ *   - Start-up time of 16384 external clock cycles
+ *   - Automatic crystal gain control mode enabled
+ *   - Frequency of 12MHz
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc_get_config_defaults(
+		struct system_clock_source_xosc_config *const config)
+{
+	Assert(config);
+
+	config->external_clock    = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+	config->startup_time      = SYSTEM_XOSC_STARTUP_16384;
+	config->auto_gain_control = true;
+	config->frequency         = 12000000UL;
+	config->run_in_standby    = false;
+	config->on_demand         = true;
+}
+
+void system_clock_source_xosc_set_config(
+		struct system_clock_source_xosc_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name External 32KHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC32K.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external 32KHz oscillator module:
+ *   - External Crystal
+ *   - Start-up time of 16384 external clock cycles
+ *   - Automatic crystal gain control mode disabled
+ *   - Frequency of 32.768KHz
+ *   - 1KHz clock output disabled
+ *   - 32KHz clock output enabled
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *   - Don't lock registers after configuration has been written
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc32k_get_config_defaults(
+		struct system_clock_source_xosc32k_config *const config)
+{
+	Assert(config);
+
+	config->external_clock      = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+	config->startup_time        = SYSTEM_XOSC32K_STARTUP_16384;
+	config->auto_gain_control   = false;
+	config->frequency           = 32768UL;
+	config->enable_1khz_output  = false;
+	config->enable_32khz_output = true;
+	config->run_in_standby      = false;
+	config->on_demand           = true;
+	config->write_once          = false;
+}
+
+void system_clock_source_xosc32k_set_config(
+		struct system_clock_source_xosc32k_config *const config);
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 32KHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC32K.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 32KHz oscillator module:
+ *   - 1KHz clock output enabled
+ *   - 32KHz clock output enabled
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *   - Set startup time to 130 cycles
+ *   - Don't lock registers after configuration has been written
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc32k_get_config_defaults(
+		struct system_clock_source_osc32k_config *const config)
+{
+	Assert(config);
+
+	config->enable_1khz_output  = true;
+	config->enable_32khz_output = true;
+	config->run_in_standby      = false;
+	config->on_demand           = true;
+	config->startup_time        = SYSTEM_OSC32K_STARTUP_130;
+	config->write_once          = false;
+}
+
+void system_clock_source_osc32k_set_config(
+		struct system_clock_source_osc32k_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 8MHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC8M.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 8MHz (nominal) oscillator module:
+ *   - Clock output frequency divided by a factor of eight
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc8m_get_config_defaults(
+		struct system_clock_source_osc8m_config *const config)
+{
+	Assert(config);
+
+	config->prescaler       = SYSTEM_OSC8M_DIV_8;
+	config->run_in_standby  = false;
+	config->on_demand       = true;
+}
+
+void system_clock_source_osc8m_set_config(
+		struct system_clock_source_osc8m_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal DFLL Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DFLL.
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DFLL oscillator module:
+ *   - Open loop mode
+ *   - QuickLock mode enabled
+ *   - Chill cycle enabled
+ *   - Output frequency lock maintained during device wake-up
+ *   - Continuous tracking of the output frequency
+ *   - Default tracking values at the mid-points for both coarse and fine
+ *     tracking parameters
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dfll_get_config_defaults(
+		struct system_clock_source_dfll_config *const config)
+{
+	Assert(config);
+
+	config->loop_mode       = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
+	config->quick_lock      = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+	config->chill_cycle     = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+	config->wakeup_lock     = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+	config->on_demand       = true;
+
+	/* Open loop mode calibration value */
+	config->coarse_value    = 0x1f / 4; /* Midpoint */
+	config->fine_value      = 0xff / 4; /* Midpoint */
+
+	/* Closed loop mode */
+	config->coarse_max_step = 1;
+	config->fine_max_step   = 1;
+	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
+}
+
+void system_clock_source_dfll_set_config(
+		struct system_clock_source_dfll_config *const config);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Clock Source Management
+ * @{
+ */
+enum status_code system_clock_source_write_calibration(
+		const enum system_clock_source system_clock_source,
+		const uint16_t calibration_value,
+		const uint8_t freq_range);
+
+enum status_code system_clock_source_enable(
+		const enum system_clock_source system_clock_source);
+
+enum status_code system_clock_source_disable(
+		const enum system_clock_source clk_source);
+
+bool system_clock_source_is_ready(
+		const enum system_clock_source clk_source);
+
+uint32_t system_clock_source_get_hz(
+		const enum system_clock_source clk_source);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Main Clock Management
+ * @{
+ */
+
+/**
+ * \brief Set main CPU clock divider.
+ *
+ * Sets the clock divider used on the main clock to provide the CPU clock.
+ *
+ * \param[in] divider  CPU clock divider to set
+ */
+static inline void system_cpu_clock_set_divider(
+		const enum system_main_clock_div divider)
+{
+	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
+	PM->CPUSEL.reg = (uint32_t)divider;
+}
+
+/**
+ * \brief Retrieves the current frequency of the CPU core.
+ *
+ * Retrieves the operating frequency of the CPU core, obtained from the main
+ * generic clock and the set CPU bus divider.
+ *
+ * \return Current CPU frequency in Hz.
+ */
+static inline uint32_t system_cpu_clock_get_hz(void)
+{
+	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
+}
+
+/**
+ * \brief Set APBx clock divider.
+ *
+ * Set the clock divider used on the main clock to provide the clock for the
+ * given APBx bus.
+ *
+ * \param[in] divider  APBx bus divider to set
+ * \param[in] bus      APBx bus to set divider
+ *
+ * \returns Status of the clock division change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus ID was given
+ * \retval STATUS_OK               The APBx clock was set successfully
+ */
+static inline enum status_code system_apb_clock_set_divider(
+		const enum system_clock_apb_bus bus,
+		const enum system_main_clock_div divider)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBASEL.reg = (uint32_t)divider;
+			break;
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBSEL.reg = (uint32_t)divider;
+			break;
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCSEL.reg = (uint32_t)divider;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the current frequency of a ABPx.
+ *
+ * Retrieves the operating frequency of an APBx bus, obtained from the main
+ * generic clock and the set APBx bus divider.
+ *
+ * \return Current APBx bus frequency in Hz.
+ */
+static inline uint32_t system_apb_clock_get_hz(
+		const enum system_clock_apb_bus bus)
+{
+	uint16_t bus_divider = 0;
+
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			bus_divider = PM->APBASEL.reg;
+			break;
+		case SYSTEM_CLOCK_APB_APBB:
+			bus_divider = PM->APBBSEL.reg;
+			break;
+		case SYSTEM_CLOCK_APB_APBC:
+			bus_divider = PM->APBCSEL.reg;
+			break;
+		default:
+			Assert(false);
+			return 0;
+	}
+
+	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * \name Bus Clock Masking
+ * @{
+ */
+
+/**
+ * \brief Set bits in the clock mask for the AHB bus.
+ *
+ * This function will set bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will enable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask  AHB clock mask to enable
+ */
+static inline void system_ahb_clock_set_mask(
+		const uint32_t ahb_mask)
+{
+	PM->AHBMASK.reg |= ahb_mask;
+}
+
+/**
+ * \brief Clear bits in the clock mask for the AHB bus.
+ *
+ * This function will clear bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will disable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask  AHB clock mask to disable
+ */
+static inline void system_ahb_clock_clear_mask(
+		const uint32_t ahb_mask)
+{
+	PM->AHBMASK.reg &= ~ahb_mask;
+}
+
+/**
+ * \brief Set bits in the clock mask for an APBx bus.
+ *
+ * This function will set bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will enable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask  APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ *                  the device header files
+ * \param[in] bus   Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
+ *                  constants from the device header files
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus given
+ * \retval STATUS_OK               The clock mask was set successfully
+ */
+static inline enum status_code system_apb_clock_set_mask(
+		const enum system_clock_apb_bus bus,
+		const uint32_t mask)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBAMASK.reg |= mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBMASK.reg |= mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCMASK.reg |= mask;
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Clear bits in the clock mask for an APBx bus.
+ *
+ * This function will clear bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will disable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask  APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ *                  the device header files
+ * \param[in] bus   Bus to clear clock mask bits
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus ID was given
+ * \retval STATUS_OK               The clock mask was changed successfully
+ */
+static inline enum status_code system_apb_clock_clear_mask(
+		const enum system_clock_apb_bus bus,
+		const uint32_t mask)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBAMASK.reg &= ~mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBMASK.reg &= ~mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCMASK.reg &= ~mask;
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * @}
+ */
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+/**
+ * \brief Reference clock source of the DPLL module.
+ */
+enum system_clock_source_dpll_reference_clock {
+	/** Select XOSC32K as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
+	/** Select XOSC as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
+	/** Select GCLK as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
+};
+
+/**
+ * \brief Lock time-out value of the DPLL module.
+ */
+enum system_clock_source_dpll_lock_time {
+	/** Set no time-out as default. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
+	/** Set time-out if no lock within 8ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
+	/** Set time-out if no lock within 9ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
+	/** Set time-out if no lock within 10ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
+	/** Set time-out if no lock within 11ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
+};
+
+/**
+ * \brief Filter type of the DPLL module.
+ */
+enum system_clock_source_dpll_filter {
+	/** Default filter mode. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
+	/** Low bandwidth filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
+	/** High bandwidth filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
+	/** High damping filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
+};
+
+/**
+ * \brief Configuration structure for DPLL.
+ *
+ * DPLL oscillator configuration structure.
+ */
+struct system_clock_source_dpll_config {
+	/** Run On Demand. If this is set the DPLL won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Keep the DPLL enabled in standby sleep mode. */
+	bool run_in_standby;
+	/** Bypass lock signal. */
+	bool lock_bypass;
+	/** Wake up fast. If this is set DPLL output clock is enabled after
+	 * the startup time. */
+	bool wake_up_fast;
+	/** Enable low power mode.  */
+	bool low_power_enable;
+
+	/** Output frequency of the clock. */
+	uint32_t output_frequency;
+	/** Reference frequency of the clock. */
+	uint32_t reference_frequency;
+	/** Devider of reference clock. */
+	uint16_t reference_divider;
+
+	/** Filter type of the DPLL module. */
+	enum system_clock_source_dpll_filter          filter;
+	/** Lock time-out value of the DPLL module. */
+	enum system_clock_source_dpll_lock_time       lock_time;
+	/** Reference clock source of the DPLL module. */
+	enum system_clock_source_dpll_reference_clock reference_clock;
+};
+
+/**
+ * \name Internal DPLL Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DPLL.
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DPLL oscillator module:
+ *   - Run only when requested by peripheral (on demand)
+ *   - Don't run in STANDBY sleep mode
+ *   - Lock bypass disabled
+ *   - Fast wake up disabled
+ *   - Low power mode disabled
+ *   - Output frequency is 48MHz
+ *   - Reference clock frequency is 32768Hz
+ *   - Not divide reference clock
+ *   - Select REF0 as reference clock
+ *   - Set lock time to default mode
+ *   - Use default filter
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dpll_get_config_defaults(
+		struct system_clock_source_dpll_config *const config)
+{
+	config->on_demand           = true;
+	config->run_in_standby      = false;
+	config->lock_bypass         = false;
+	config->wake_up_fast        = false;
+	config->low_power_enable    = false;
+
+	config->output_frequency    = 48000000;
+	config->reference_frequency = 32768;
+	config->reference_divider   = 1;
+	config->reference_clock     = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
+
+	config->lock_time           = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
+	config->filter              = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
+};
+
+void system_clock_source_dpll_set_config(
+		struct system_clock_source_dpll_config *const config);
+
+/* @} */
+#endif
+
+/**
+ * \name System Clock Initialization
+ * @{
+ */
+
+void system_clock_init(void);
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Flash Wait States
+ * @{
+ */
+
+/**
+ * \brief Set flash controller wait states.
+ *
+ * Will set the number of wait states that are used by the onboard
+ * flash memory. The number of wait states depend on both device
+ * supply voltage and CPU speed. The required number of wait states
+ * can be found in the electrical characteristics of the device.
+ *
+ * \param[in] wait_states Number of wait states to use for internal flash
+ */
+static inline void system_flash_set_waitstates(uint8_t wait_states)
+{
+	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
+			((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
+
+	NVMCTRL->CTRLB.bit.RWS = wait_states;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
+ *
+ * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>DFLL</td>
+ *		<td>Digital Frequency Locked Loop</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC32K</td>
+ *		<td>Internal 32KHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC8M</td>
+ *		<td>Internal 8MHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PLL</td>
+ *		<td>Phase Locked Loop</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC</td>
+ *		<td>Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>XOSC</td>
+ *		<td>External Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>XOSC32K</td>
+ *		<td>External 32KHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>AHB</td>
+ *		<td>Advanced High-performance Bus</td>
+ *	</tr>
+ *	<tr>
+ *		<td>APB</td>
+ *		<td>Advanced Peripheral Bus</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DPLL</td>
+ *		<td>Digital Phase Locked Loop</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_errata Errata
+ *
+ *	- This driver implements experimental workaround for errata 9905
+ *
+ *	  "The DFLL clock must be requested before being configured otherwise a
+ *	  write access to a DFLL register can freeze the device."
+ *	  This driver will enable and configure the DFLL before the ONDEMAND bit is set.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *			\li Corrected OSC32K startup time definitions
+ *			\li Support locking of OSC32K and XOSC32K config register (default: false)
+ *			\li Added DPLL support, functions added:
+ *			    \c system_clock_source_dpll_get_config_defaults() and
+ *		        \c system_clock_source_dpll_set_config()
+ *			\li Moved gclk channel locking feature out of the config struct
+ *			    functions added:
+ *			    \c system_gclk_chan_lock(),
+ *			    \c system_gclk_chan_is_locked()
+ *			    \c system_gclk_chan_is_enabled() and
+ *			    \c system_gclk_gen_is_enabled()
+ *		</td>
+ *	</tr>
+ *  <tr>
+ *		<td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
+ *		    and configured to a failed/not running clock generator</td>
+ *  </tr>
+ *	<tr>
+ *		<td>
+ *			\li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
+ *			\li Fixed system_flash_set_waitstates() failing with an assertion
+ *			    if an odd number of wait states provided
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *			\li Updated DFLL configuration function to implement workaround for
+ *			    errata 9905 in the DFLL module
+ *			\li Updated \c system_clock_init() to reset interrupt flags before
+ *			    they are used
+ *			\li Fixed \c system_clock_source_get_hz() to return correcy DFLL
+ *			    frequency number
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>\li Fixed \c system_clock_source_is_ready not returning the correct
+ *              state for \c SYSTEM_CLOCK_SOURCE_OSC8M
+ *          \li Renamed the various \c system_clock_source_*_get_default_config()
+ *              functions to \c system_clock_source_*_get_config_defaults() to
+ *              match the remainder of ASF
+ *          \li Added OSC8M calibration constant loading from the device signature
+ *              row when the oscillator is initialized
+ *          \li Updated default configuration of the XOSC32 to disable Automatic
+ *              Gain Control due to silicon errata
+ *      </td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in
+ * a selection of use cases. Note that a QSG can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_clock_basic_use_case
+ *  - \subpage asfdoc_sam0_system_gclk_basic_use_case
+ *
+ * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42119E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM DA1 and SAM D09</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42119D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42119C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42119B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos. Fixed missing steps in the Basic
+ *          Use Case Quick Start Guide</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42119A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
new file mode 100644
index 0000000000..e1c186cf67
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
@@ -0,0 +1,522 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Generic Clock Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <gclk.h>
+#include <clock.h>
+#include <system_interrupt.h>
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false if the module has completed synchronization
+ * \retval true if the module synchronization is ongoing
+ */
+static inline bool system_gclk_is_syncing(void)
+{
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Initializes the GCLK driver.
+ *
+ * Initializes the Generic Clock module, disabling and resetting all active
+ * Generic Clock Generators and Channels to their power-on default values.
+ */
+void system_gclk_init(void)
+{
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+	/* Software reset the module to ensure it is re-initialized correctly */
+	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
+		/* Wait for reset to complete */
+	}
+}
+
+/**
+ * \brief Writes a Generic Clock Generator configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock Generator configuration
+ * to the hardware module.
+ *
+ * \note Changing the clock source on the fly (on a running
+ *       generator) can take additional time if the clock source is configured
+ *       to only run on-demand (ONDEMAND bit is set) and it is not currently
+ *       running (no peripheral is requesting the clock source). In this case
+ *       the GCLK will request the new clock while still keeping a request to
+ *       the old clock source until the new clock source is ready.
+ *
+ * \note This function will not start a generator that is not already running;
+ *       to start the generator, call \ref system_gclk_gen_enable()
+ *       after configuring a generator.
+ *
+ * \param[in] generator  Generic Clock Generator index to configure
+ * \param[in] config     Configuration settings for the generator
+ */
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache new register configurations to minimize sync requirements. */
+	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
+
+	/* Select the requested source clock for the generator */
+	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+	/* Configure the clock to be either high or low when disabled */
+	if (config->high_when_disabled) {
+		new_genctrl_config |= GCLK_GENCTRL_OOV;
+	}
+
+	/* Configure if the clock output to I/O pin should be enabled. */
+	if (config->output_enable) {
+		new_genctrl_config |= GCLK_GENCTRL_OE;
+	}
+
+	/* Set division factor */
+	if (config->division_factor > 1) {
+		/* Check if division is a power of two */
+		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
+			/* Determine the index of the highest bit set to get the
+			 * division factor that must be loaded into the division
+			 * register */
+
+			uint32_t div2_count = 0;
+
+			uint32_t mask;
+			for (mask = (1UL << 1); mask < config->division_factor;
+						mask <<= 1) {
+				div2_count++;
+			}
+
+			/* Set binary divider power of 2 division factor */
+			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
+			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+		} else {
+			/* Set integer division factor */
+
+			new_gendiv_config  |=
+					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
+
+			/* Enable non-binary division with increased duty cycle accuracy */
+			new_genctrl_config |= GCLK_GENCTRL_IDC;
+		}
+
+	}
+
+	/* Enable or disable the clock in standby mode */
+	if (config->run_in_standby) {
+		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+	}
+
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the correct generator */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+
+	/* Write the new generator configuration */
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+	GCLK->GENDIV.reg  = new_gendiv_config;
+
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Enables a Generic Clock Generator that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock Generator that was previously
+ * configured via a call to \ref system_gclk_gen_set_config().
+ *
+ * \param[in] generator  Generic Clock Generator index to enable
+ */
+void system_gclk_gen_enable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Enable generator */
+	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock Generator that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock Generator that was previously
+ * started via a call to \ref system_gclk_gen_enable().
+ *
+ * \param[in] generator  Generic Clock Generator index to disable
+ */
+void system_gclk_gen_disable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Disable generator */
+	GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+	while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock Generator is enabled.
+ *
+ * \param[in] generator  Generic Clock Generator index to check
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock Generator is enabled
+ * \retval false The Generic Clock Generator is disabled
+ */
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	/* Obtain the enabled status */
+	enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock generator.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * generator, used as a source to a Generic Clock Channel module.
+ *
+ * \param[in] generator  Generic Clock Generator index
+ *
+ * \return The frequency of the generic clock generator, in Hz.
+ */
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the appropriate generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Get the frequency of the source connected to the GCLK generator */
+	uint32_t gen_input_hz = system_clock_source_get_hz(
+			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+
+	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+
+	/* Select the appropriate generator division register */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	uint32_t divider = GCLK->GENDIV.bit.DIV;
+
+	system_interrupt_leave_critical_section();
+
+	/* Check if the generator is using fractional or binary division */
+	if (!divsel && divider > 1) {
+		gen_input_hz /= divider;
+	} else if (divsel) {
+		gen_input_hz >>= (divider+1);
+	}
+
+	return gen_input_hz;
+}
+
+/**
+ * \brief Writes a Generic Clock configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock configuration to the
+ * hardware module. If the clock is currently running, it will be stopped.
+ *
+ * \note Once called the clock will not be running; to start the clock,
+ *       call \ref system_gclk_chan_enable() after configuring a clock channel.
+ *
+ * \param[in] channel   Generic Clock channel to configure
+ * \param[in] config    Configuration settings for the clock
+ *
+ */
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache the new config to reduce sync requirements */
+	uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
+
+	/* Select the desired generic clock generator */
+	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+
+	/* Disable generic clock channel */
+	system_gclk_chan_disable(channel);
+
+	/* Write the new configuration */
+	GCLK->CLKCTRL.reg = new_clkctrl_config;
+}
+
+/**
+ * \brief Enables a Generic Clock that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock that was previously
+ * configured via a call to \ref system_gclk_chan_set_config().
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_enable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Enable the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock that was previously started
+ * via a call to \ref system_gclk_chan_enable().
+ *
+ * \param[in] channel  Generic Clock channel to disable
+ */
+void system_gclk_chan_disable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Sanity check WRTLOCK */
+	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+
+	/* Switch to known-working source so that the channel can be disabled */
+	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+	GCLK->CLKCTRL.bit.GEN = 0;
+
+	/* Disable the generic clock */
+	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	/* Restore previous configured clock generator */
+	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is enabled.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock channel is enabled
+ * \retval false The Generic Clock channel is disabled
+ */
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	enabled = GCLK->CLKCTRL.bit.CLKEN;
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Locks a Generic Clock channel from further configuration writes.
+ *
+ * Locks a generic clock channel from further configuration writes. It is only
+ * possible to unlock the channel configuration through a power on reset.
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_lock(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Lock the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is locked.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The lock status.
+ * \retval true The Generic Clock channel is locked
+ * \retval false The Generic Clock channel is not locked
+ */
+bool system_gclk_chan_is_locked(
+		const uint8_t channel)
+{
+	bool locked;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	locked = GCLK->CLKCTRL.bit.WRTLOCK;
+
+	system_interrupt_leave_critical_section();
+
+	return locked;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock channel.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * channel, used as a source to a device peripheral module.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The frequency of the generic clock channel, in Hz.
+ */
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel)
+{
+	uint8_t gen_id;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	gen_id = GCLK->CLKCTRL.bit.GEN;
+
+	system_interrupt_leave_critical_section();
+
+	/* Return the clock speed of the associated GCLK generator */
+	return system_gclk_gen_get_hz(gen_id);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/module_config/conf_clocks.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/module_config/conf_clocks.h
new file mode 100644
index 0000000000..e23359cd64
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/module_config/conf_clocks.h
@@ -0,0 +1,197 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Clock configuration
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+#  define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+#  define CONF_CLOCK_FLASH_WAIT_STATES            0
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+#  define CONF_CLOCK_XOSC32K_ENABLE               false
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            true
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       false
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+#  define CONF_CLOCK_DFLL_ENABLE                  false
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
+#  define CONF_CLOCK_DFLL_ON_DEMAND               false
+
+/* DFLL open loop mode configuration */
+#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)
+
+/* DFLL closed loop mode configuration */
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         1465 /* (48000000 / 32768) */
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)
+
+/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
+#  define CONF_CLOCK_DPLL_ENABLE                  false
+#  define CONF_CLOCK_DPLL_ON_DEMAND               true
+#  define CONF_CLOCK_DPLL_RUN_IN_STANDBY          false
+#  define CONF_CLOCK_DPLL_LOCK_BYPASS             false
+#  define CONF_CLOCK_DPLL_WAKE_UP_FAST            false
+#  define CONF_CLOCK_DPLL_LOW_POWER_ENABLE        false
+
+#  define CONF_CLOCK_DPLL_LOCK_TIME               SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
+#  define CONF_CLOCK_DPLL_REFERENCE_CLOCK         SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
+#  define CONF_CLOCK_DPLL_FILTER                  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
+
+#  define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY     32768
+#  define CONF_CLOCK_DPLL_REFERENCE_DIVIDER       1
+#  define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY        48000000
+
+/* DPLL GCLK reference configuration */
+#  define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR  GCLK_GENERATOR_1
+/* DPLL GCLK lock timer configuration */
+#  define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR     GCLK_GENERATOR_1
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 */
+#  define CONF_CLOCK_GCLK_1_ENABLE                false
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                false
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             32
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 */
+#  define CONF_CLOCK_GCLK_3_ENABLE                false
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 4 */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 8 */
+#  define CONF_CLOCK_GCLK_8_ENABLE                false
+#  define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_8_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_8_PRESCALER             1
+#  define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE         false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/gclk.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/gclk.h
new file mode 100644
index 0000000000..ff26eac9eb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/gclk.h
@@ -0,0 +1,307 @@
+/**
+ * \file
+ *
+ * \brief SAM Generic Clock Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
+#define SYSTEM_CLOCK_GCLK_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_system_clock_group
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief List of available GCLK generators.
+ *
+ * List of Available GCLK generators. This enum is used in the peripheral
+ * device drivers to select the GCLK generator to be used for its operation.
+ *
+ * The number of GCLK generators available is device dependent.
+ */
+enum gclk_generator {
+	/** GCLK generator channel 0 */
+	GCLK_GENERATOR_0,
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
+	/** GCLK generator channel 1 */
+	GCLK_GENERATOR_1,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
+	/** GCLK generator channel 2 */
+	GCLK_GENERATOR_2,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
+	/** GCLK generator channel 3 */
+	GCLK_GENERATOR_3,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
+	/** GCLK generator channel 4 */
+	GCLK_GENERATOR_4,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
+	/** GCLK generator channel 5 */
+	GCLK_GENERATOR_5,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
+	/** GCLK generator channel 6 */
+	GCLK_GENERATOR_6,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
+	/** GCLK generator channel 7 */
+	GCLK_GENERATOR_7,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
+	/** GCLK generator channel 8 */
+	GCLK_GENERATOR_8,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
+	/** GCLK generator channel 9 */
+	GCLK_GENERATOR_9,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
+	/** GCLK generator channel 10 */
+	GCLK_GENERATOR_10,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
+	/** GCLK generator channel 11 */
+	GCLK_GENERATOR_11,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
+	/** GCLK generator channel 12 */
+	GCLK_GENERATOR_12,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
+	/** GCLK generator channel 13 */
+	GCLK_GENERATOR_13,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
+	/** GCLK generator channel 14 */
+	GCLK_GENERATOR_14,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
+	/** GCLK generator channel 15 */
+	GCLK_GENERATOR_15,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
+	/** GCLK generator channel 16 */
+	GCLK_GENERATOR_16,
+#endif
+};
+
+/**
+ * \brief Generic Clock Generator configuration structure.
+ *
+ * Configuration structure for a Generic Clock Generator channel. This
+ * structure should be initialized by the
+ * \ref system_gclk_gen_get_config_defaults() function before being modified by
+ * the user application.
+ */
+struct system_gclk_gen_config {
+	/** Source clock input channel index, see the \ref system_clock_source */
+	uint8_t source_clock;
+	/** If \c true, the generator output level is high when disabled */
+	bool high_when_disabled;
+	/** Integer division factor of the clock output compared to the input */
+	uint32_t division_factor;
+	/** If \c true, the clock is kept enabled during device standby mode */
+	bool run_in_standby;
+	/** If \c true, enables GCLK generator clock output to a GPIO pin */
+	bool output_enable;
+};
+
+/**
+ * \brief Generic Clock configuration structure.
+ *
+ * Configuration structure for a Generic Clock channel. This structure
+ * should be initialized by the \ref system_gclk_chan_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct system_gclk_chan_config {
+	/** Generic Clock Generator source channel */
+	enum gclk_generator source_generator;
+};
+
+/** \name Generic Clock Management
+ * @{
+ */
+void system_gclk_init(void);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Generators)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock Generator configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock Generator configuration structure to
+ * a set of known default values. This function should be called on all
+ * new instances of these configuration structures before being modified
+ * by the user application.
+ *
+ * The default configuration is:
+ *  \li The clock is generated undivided from the source frequency
+ *  \li The clock generator output is low when the generator is disabled
+ *  \li The input clock is sourced from input clock channel 0
+ *  \li The clock will be disabled during sleep
+ *  \li The clock output will not be routed to a physical GPIO pin
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_gclk_gen_get_config_defaults(
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->division_factor    = 1;
+	config->high_when_disabled = false;
+#if SAML21 || SAML22  || SAMR30
+	config->source_clock       = GCLK_SOURCE_OSC16M;
+#elif (SAMC20) || (SAMC21)
+	config->source_clock       = GCLK_SOURCE_OSC48M;
+#else
+	config->source_clock       = GCLK_SOURCE_OSC8M;
+#endif
+	config->run_in_standby     = false;
+	config->output_enable      = false;
+}
+
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config);
+
+void system_gclk_gen_enable(
+		const uint8_t generator);
+
+void system_gclk_gen_disable(
+		const uint8_t generator);
+
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Channels)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li The clock is sourced from the Generic Clock Generator channel 0
+ *  \li The clock configuration will not be write-locked when set
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_gclk_chan_get_config_defaults(
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->source_generator = GCLK_GENERATOR_0;
+}
+
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config);
+
+void system_gclk_chan_enable(
+		const uint8_t channel);
+
+void system_gclk_chan_disable(
+		const uint8_t channel);
+
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel);
+
+void system_gclk_chan_lock(
+		const uint8_t channel);
+
+bool system_gclk_chan_is_locked(
+		const uint8_t channel);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Frequency Retrieval
+ * @{
+ */
+
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator);
+
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.c
new file mode 100644
index 0000000000..24ee27ffa2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.c
@@ -0,0 +1,217 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "system_interrupt.h"
+
+/**
+ * \brief Check if a interrupt line is pending.
+ *
+ * Checks if the requested interrupt vector is pending.
+ *
+ * \param[in] vector  Interrupt vector number to check
+ *
+ * \returns A boolean identifying if the requested interrupt vector is pending.
+ *
+ * \retval true   Specified interrupt vector is pending
+ * \retval false  Specified interrupt vector is not pending
+ *
+ */
+bool system_interrupt_is_pending(
+		const enum system_interrupt_vector vector)
+{
+	bool result;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
+	} else {
+		Assert(false);
+		result = false;
+	}
+
+	return result;
+}
+
+/**
+ * \brief Set a interrupt vector as pending.
+ *
+ * Set the requested interrupt vector as pending (i.e. issues a software
+ * interrupt request for the specified vector). The software handler will be
+ * handled (if enabled) in a priority order based on vector number and
+ * configured priority settings.
+ *
+ * \param[in] vector  Interrupt vector number which is set as pending
+ *
+ * \returns Status code identifying if the vector was successfully set as
+ *          pending.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_pending(
+		const enum system_interrupt_vector vector)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		NVIC->ISPR[0] = (1 << vector);
+	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+		/* Note: Because NMI has highest priority it will be executed
+		 * immediately after it has been set pending */
+		SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+	} else {
+		/* The user want to set something unsupported as pending */
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Clear pending interrupt vector.
+ *
+ * Clear a pending interrupt vector, so the software handler is not executed.
+ *
+ * \param[in] vector  Interrupt vector number to clear
+ *
+ * \returns A status code identifying if the interrupt pending state was
+ *          successfully cleared.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_clear_pending(
+		const enum system_interrupt_vector vector)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		NVIC->ICPR[0] = (1 << vector);
+	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+		/* Note: Clearing of NMI pending interrupts does not make sense and is
+		 * not supported by the device, as it has the highest priority and will
+		 * always be executed at the moment it is set */
+		return STATUS_ERR_INVALID_ARG;
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+	} else {
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Set interrupt vector priority level.
+ *
+ * Set the priority level of an external interrupt or exception.
+ *
+ * \param[in] vector          Interrupt vector to change
+ * \param[in] priority_level  New vector priority level to set
+ *
+ * \returns Status code indicating if the priority level of the interrupt was
+ *          successfully set.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_priority(
+		const enum system_interrupt_vector vector,
+		const enum system_interrupt_priority_level priority_level)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		uint8_t register_num = vector / 4;
+		uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+		NVIC->IP[register_num] =
+				(NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) |
+				(priority_level << priority_pos);
+
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
+	} else {
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Get interrupt vector priority level.
+ *
+ * Retrieves the priority level of the requested external interrupt or exception.
+ *
+ * \param[in] vector  Interrupt vector of which the priority level will be read
+ *
+ * \return Currently configured interrupt priority level of the given interrupt
+ *         vector.
+ */
+enum system_interrupt_priority_level system_interrupt_get_priority(
+		const enum system_interrupt_vector vector)
+{
+	uint8_t register_num = vector / 4;
+	uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+	enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
+
+	if (vector >= 0) {
+		priority = (enum system_interrupt_priority_level)
+				((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		priority = (enum system_interrupt_priority_level)
+				((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+	}
+
+	return priority;
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.h
new file mode 100644
index 0000000000..940170e7c2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.h
@@ -0,0 +1,430 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_INTERRUPT_H_INCLUDED
+#define SYSTEM_INTERRUPT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt (SYSTEM INTERRUPT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of internal software and
+ * hardware interrupts/exceptions.
+ *
+ * The following peripheral is used by this module:
+ *  - NVIC (Nested Vector Interrupt Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_interrupt_prerequisites
+ *  - \ref asfdoc_sam0_system_interrupt_module_overview
+ *  - \ref asfdoc_sam0_system_interrupt_special_considerations
+ *  - \ref asfdoc_sam0_system_interrupt_extra_info
+ *  - \ref asfdoc_sam0_system_interrupt_examples
+ *  - \ref asfdoc_sam0_system_interrupt_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_module_overview Module Overview
+ *
+ * The ARM&reg; Cortex&reg; M0+ core contains an interrupt and exception vector table, which
+ * can be used to configure the device's interrupt handlers; individual
+ * interrupts and exceptions can be enabled and disabled, as well as configured
+ * with a variable priority.
+ *
+ * This driver provides a set of wrappers around the core interrupt functions,
+ * to expose a simple API for the management of global and individual interrupts
+ * within the device.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
+ * In some applications it is important to ensure that no interrupts may be
+ * executed by the system whilst a critical portion of code is being run; for
+ * example, a buffer may be copied from one context to another - during which
+ * interrupts must be disabled to avoid corruption of the source buffer contents
+ * until the copy has completed. This driver provides a basic API to enter and
+ * exit nested critical sections, so that global interrupts can be kept disabled
+ * for as long as necessary to complete a critical application code section.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
+ * For some applications, it may be desirable to raise a module or core
+ * interrupt via software. For this reason, a set of APIs to set an interrupt or
+ * exception as pending are provided to the user application.
+ *
+ * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
+ *
+ * Interrupts from peripherals in the SAM devices are on a per-module basis;
+ * an interrupt raised from any source within a module will cause a single,
+ * module-common handler to execute. It is the user application or driver's
+ * responsibility to de-multiplex the module-common interrupt to determine the
+ * exact interrupt cause.
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes:
+ *  - \ref asfdoc_sam0_system_interrupt_extra_acronyms
+ *  - \ref asfdoc_sam0_system_interrupt_extra_dependencies
+ *  - \ref asfdoc_sam0_system_interrupt_extra_errata
+ *  - \ref asfdoc_sam0_system_interrupt_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_interrupt_exqsg.
+ *
+ * \section asfdoc_sam0_system_interrupt_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <core_cm0plus.h>
+#include "system_interrupt_features.h"
+
+/**
+ * \brief Table of possible system interrupt/exception vector priorities.
+ *
+ * Table of all possible interrupt and exception vector priorities within the
+ * device.
+ */
+enum system_interrupt_priority_level {
+	/** Priority level 0, the highest possible interrupt priority */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_0  = 0,
+	/** Priority level 1 */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_1  = 1,
+	/** Priority level 2 */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_2  = 2,
+	/** Priority level 3, the lowest possible interrupt priority */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_3  = 3,
+};
+
+/**
+ * \name Critical Section Management
+ * @{
+ */
+
+/**
+ * \brief Enters a critical section.
+ *
+ * Disables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_enter_critical_section(void)
+{
+	cpu_irq_enter_critical();
+}
+
+/**
+ * \brief Leaves a critical section.
+ *
+ * Enables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_leave_critical_section(void)
+{
+	cpu_irq_leave_critical();
+}
+
+/** @} */
+
+/**
+ * \name Interrupt Enabling/Disabling
+ * @{
+ */
+
+/**
+ * \brief Check if global interrupts are enabled.
+ *
+ * Checks if global interrupts are currently enabled.
+ *
+ * \returns A boolean that identifies if the global interrupts are enabled or not.
+ *
+ * \retval true   Global interrupts are currently enabled
+ * \retval false  Global interrupts are currently disabled
+ *
+ */
+static inline bool system_interrupt_is_global_enabled(void)
+{
+	return cpu_irq_is_enabled();
+}
+
+/**
+ * \brief Enables global interrupts.
+ *
+ * Enables global interrupts in the device to fire any enabled interrupt handlers.
+ */
+static inline void system_interrupt_enable_global(void)
+{
+	cpu_irq_enable();
+}
+
+/**
+ * \brief Disables global interrupts.
+ *
+ * Disabled global interrupts in the device, preventing any enabled interrupt
+ * handlers from executing.
+ */
+static inline void system_interrupt_disable_global(void)
+{
+	cpu_irq_disable();
+}
+
+/**
+ * \brief Checks if an interrupt vector is enabled or not.
+ *
+ * Checks if a specific interrupt vector is currently enabled.
+ *
+ * \param[in] vector  Interrupt vector number to check
+ *
+ * \returns A variable identifying if the requested interrupt vector is enabled.
+ *
+ * \retval true   Specified interrupt vector is currently enabled
+ * \retval false  Specified interrupt vector is currently disabled
+ *
+ */
+static inline bool system_interrupt_is_enabled(
+		const enum system_interrupt_vector vector)
+{
+	return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
+}
+
+/**
+ * \brief Enable interrupt vector.
+ *
+ * Enables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector Interrupt vector to enable
+ */
+static inline void system_interrupt_enable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/**
+ * \brief Disable interrupt vector.
+ *
+ * Disables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector  Interrupt vector to disable
+ */
+static inline void system_interrupt_disable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/** @} */
+
+/**
+ * \name Interrupt State Management
+ * @{
+ */
+
+/**
+ * \brief Get active interrupt (if any).
+ *
+ * Return the vector number for the current executing software handler, if any.
+ *
+ * \return Interrupt number that is currently executing.
+ */
+static inline enum system_interrupt_vector system_interrupt_get_active(void)
+{
+	uint32_t IPSR = __get_IPSR();
+	/* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */
+	return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16);
+}
+
+bool system_interrupt_is_pending(
+		const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_set_pending(
+		const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_clear_pending(
+		const enum system_interrupt_vector vector);
+
+/** @} */
+
+/**
+ * \name Interrupt Priority Management
+ * @{
+ */
+
+enum status_code system_interrupt_set_priority(
+		const enum system_interrupt_vector vector,
+		const enum system_interrupt_priority_level priority_level);
+
+enum system_interrupt_priority_level system_interrupt_get_priority(
+		const enum system_interrupt_vector vector);
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>ISR</td>
+ *		<td>Interrupt Service Routine</td>
+ *	</tr>
+ *	<tr>
+ *		<td>NMI</td>
+ *		<td>Non-maskable Interrupt</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>Serial Communication Interface</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
+ *  - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
+ *
+ * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42122E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd20/system_interrupt_features.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd20/system_interrupt_features.h
new file mode 100644
index 0000000000..3bfebfe7f5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd20/system_interrupt_features.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief SAM D20 System Interrupt Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+
+#if !defined(__DOXYGEN__)
+
+/* Generates a interrupt vector table enum list entry for a given module type
+   and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
+#  define _MODULE_IRQn(n, module) \
+		SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+
+/* Generates interrupt vector table enum list entries for all instances of a
+   given module type on the selected device. */
+#  define _SYSTEM_INTERRUPT_MODULES(name) \
+		MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+
+#  define _SYSTEM_INTERRUPT_IPSR_MASK              0x0000003f
+#  define _SYSTEM_INTERRUPT_PRIORITY_MASK          0x00000003
+
+#  define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START  0
+
+#  define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS        30
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_interrupt_group
+ * @{
+ */
+
+/**
+ * \brief Table of possible system interrupt/exception vector numbers.
+ *
+ * Table of all possible interrupt and exception vector indexes within the
+ * SAM D20 device.
+ */
+#if defined(__DOXYGEN__)
+/** \note The actual enumeration name is "system_interrupt_vector". */
+enum system_interrupt_vector_samd20 {
+#else
+enum system_interrupt_vector {
+#endif
+	/** Interrupt vector index for a NMI interrupt */
+	SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
+	/** Interrupt vector index for a Hard Fault memory access exception */
+	SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
+	/** Interrupt vector index for a Supervisor Call exception */
+	SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
+	/** Interrupt vector index for a Pending Supervisor interrupt */
+	SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
+	/** Interrupt vector index for a System Tick interrupt */
+	SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
+
+	/** Interrupt vector index for a Power Manager peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
+	/** Interrupt vector index for a System Control peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
+	/** Interrupt vector index for a Watch Dog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
+	/** Interrupt vector index for a Real Time Clock peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
+	/** Interrupt vector index for an External Interrupt peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
+	/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
+	SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
+	/** Interrupt vector index for an Event System interrupt */
+	SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
+#if defined(__DOXYGEN__)
+	/** Interrupt vector index for a SERCOM peripheral interrupt.
+	 *
+	 *  Each specific device may contain several SERCOM peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
+	/** Interrupt vector index for a Timer/Counter peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TC0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
+#else
+	_SYSTEM_INTERRUPT_MODULES(SERCOM)
+	_SYSTEM_INTERRUPT_MODULES(TC)
+#endif
+	/** Interrupt vector index for an Analog Comparator peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
+	/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
+	/** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
+};
+
+/** @} */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
new file mode 100644
index 0000000000..25dfa838db
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
@@ -0,0 +1,195 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 System Interrupt Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+
+#if !defined(__DOXYGEN__)
+
+/* Generates a interrupt vector table enum list entry for a given module type
+   and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
+#  define _MODULE_IRQn(n, module) \
+		SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+
+/* Generates interrupt vector table enum list entries for all instances of a
+   given module type on the selected device. */
+#  define _SYSTEM_INTERRUPT_MODULES(name) \
+		MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+
+#  define _SYSTEM_INTERRUPT_IPSR_MASK              0x0000003f
+#  define _SYSTEM_INTERRUPT_PRIORITY_MASK          0x00000003
+
+#  define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START  0
+
+#  define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS        30
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_interrupt_group
+ * @{
+ */
+
+/**
+ * \brief Table of possible system interrupt/exception vector numbers.
+ *
+ * Table of all possible interrupt and exception vector indexes within the
+ * SAM D21 device. Check peripherals configuration in SAM D21 datasheet for
+ * available vector index for specific device.
+ *
+ */
+#if defined(__DOXYGEN__)
+/** \note The actual enumeration name is "system_interrupt_vector". */
+enum system_interrupt_vector_samd21 {
+#else
+enum system_interrupt_vector {
+#endif
+	/** Interrupt vector index for a NMI interrupt */
+	SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
+	/** Interrupt vector index for a Hard Fault memory access exception */
+	SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
+	/** Interrupt vector index for a Supervisor Call exception */
+	SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
+	/** Interrupt vector index for a Pending Supervisor interrupt */
+	SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
+	/** Interrupt vector index for a System Tick interrupt */
+	SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
+
+	/** Interrupt vector index for a Power Manager peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
+	/** Interrupt vector index for a System Control peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
+	/** Interrupt vector index for a Watch Dog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
+	/** Interrupt vector index for a Real Time Clock peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
+	/** Interrupt vector index for an External Interrupt peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
+	/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
+	SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
+	/** Interrupt vector index for a Direct Memory Access interrupt */
+	SYSTEM_INTERRUPT_MODULE_DMA        = DMAC_IRQn,
+#if defined(__DOXYGEN__) || defined(ID_USB)
+	/** Interrupt vector index for a Universal Serial Bus interrupt */
+	SYSTEM_INTERRUPT_MODULE_USB        = USB_IRQn,
+#endif
+	/** Interrupt vector index for an Event System interrupt */
+	SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
+#if defined(__DOXYGEN__)
+	/** Interrupt vector index for a SERCOM peripheral interrupt.
+	 *
+	 *  Each specific device may contain several SERCOM peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
+
+	/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TCC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TCC0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCCn        = TCCn_IRQn,
+
+	/** Interrupt vector index for a Timer/Counter peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TC3).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
+#else
+	_SYSTEM_INTERRUPT_MODULES(SERCOM)
+
+	_SYSTEM_INTERRUPT_MODULES(TCC)
+
+	SYSTEM_INTERRUPT_MODULE_TC3        = TC3_IRQn,
+	SYSTEM_INTERRUPT_MODULE_TC4        = TC4_IRQn,
+	SYSTEM_INTERRUPT_MODULE_TC5        = TC5_IRQn,
+#  if defined(ID_TC6)
+	SYSTEM_INTERRUPT_MODULE_TC6        = TC6_IRQn,
+#  endif
+#  if defined(ID_TC7)
+	SYSTEM_INTERRUPT_MODULE_TC7        = TC7_IRQn,
+#  endif
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_ADC)
+	/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_AC)
+	/** Interrupt vector index for an Analog Comparator peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_DAC)
+	/** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_PTC)
+	/** Interrupt vector index for a Peripheral Touch Controller peripheral
+	 *  interrupt */
+	SYSTEM_INTERRUPT_MODULE_PTC        = PTC_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_I2S)
+	/** Interrupt vector index for a Inter-IC Sound Interface peripheral
+	 *  interrupt */
+	SYSTEM_INTERRUPT_MODULE_I2S        = I2S_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_AC1)
+	/** Interrupt vector index for an Analog Comparator 1 peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AC1        = AC1_IRQn,
+#endif
+};
+
+/** @} */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.c
new file mode 100644
index 0000000000..a2c9c7cdcc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.c
@@ -0,0 +1,311 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <pinmux.h>
+
+/**
+ * \internal
+ * Writes out a given configuration of a Port pin configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] port      Base of the PORT module to configure
+ * \param[in] pin_mask  Mask of the port pin to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+static void _system_pinmux_config(
+		PortGroup *const port,
+		const uint32_t pin_mask,
+		const struct system_pinmux_config *const config)
+{
+	Assert(port);
+	Assert(config);
+
+	/* Track the configuration bits into a temporary variable before writing */
+	uint32_t pin_cfg = 0;
+
+	/* Enabled powersave mode, don't create configuration */
+	if (!config->powersave) {
+		/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
+		 * be written later) and store the new MUX mask */
+		if (config->mux_position != SYSTEM_PINMUX_GPIO) {
+			pin_cfg |= PORT_WRCONFIG_PMUXEN;
+			pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
+		}
+
+		/* Check if the user has requested that the input buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Enable input buffer flag */
+			pin_cfg |= PORT_WRCONFIG_INEN;
+
+			/* Enable pull-up/pull-down control flag if requested */
+			if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
+				pin_cfg |= PORT_WRCONFIG_PULLEN;
+			}
+
+			/* Clear the port DIR bits to disable the output buffer */
+			port->DIRCLR.reg = pin_mask;
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Cannot use a pull-up if the output driver is enabled,
+			 * if requested the input buffer can only sample the current
+			 * output state */
+			pin_cfg &= ~PORT_WRCONFIG_PULLEN;
+		}
+	} else {
+		port->DIRCLR.reg = pin_mask;
+	}
+
+	/* The Write Configuration register (WRCONFIG) requires the
+	 * pins to to grouped into two 16-bit half-words - split them out here */
+	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+	uint32_t upper_pin_mask = (pin_mask >> 16);
+
+	/* Configure the lower 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+
+	/* Configure the upper 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+			PORT_WRCONFIG_HWSEL;
+
+	if(!config->powersave) {
+		/* Set the pull-up state once the port pins are configured if one was
+		 * requested and it does not violate the valid set of port
+		 * configurations */
+		if (pin_cfg & PORT_WRCONFIG_PULLEN) {
+			/* Set the OUT register bits to enable the pull-up if requested,
+			 * clear to enable pull-down */
+			if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
+				port->OUTSET.reg = pin_mask;
+			} else {
+				port->OUTCLR.reg = pin_mask;
+			}
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Set the port DIR bits to enable the output buffer */
+			port->DIRSET.reg = pin_mask;
+		}
+	}
+}
+
+/**
+ * \brief Writes a Port pin configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin configuration to the hardware
+ * module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config)
+{
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+	_system_pinmux_config(port, pin_mask, config);
+}
+
+/**
+ * \brief Writes a Port pin group configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin group configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] port      Base of the PORT module to configure
+ * \param[in] mask      Mask of the port pin(s) to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct system_pinmux_config *const config)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			_system_pinmux_config(port, (1UL << i), config);
+		}
+	}
+}
+
+/**
+ * \brief Configures the input sampling mode for a group of pins.
+ *
+ * Configures the input sampling mode for a group of pins, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New pin sampling mode to configure
+ */
+void system_pinmux_group_set_input_sample_mode(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_sample mode)
+{
+	Assert(port);
+
+	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+		port->CTRL.reg |= mask;
+	} else {
+		port->CTRL.reg &= ~mask;
+	}
+}
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Configures the output slew rate mode for a group of pins.
+ *
+ * Configures the output slew rate mode for a group of pins, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New pin slew rate mode to configure
+ */
+void system_pinmux_group_set_output_slew_rate(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_slew_rate mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+				port->PINCFG[i].reg |=  PORT_PINCFG_SLEWLIM;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Configures the output driver strength mode for a group of pins.
+ *
+ * Configures the output drive strength for a group of pins, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New output driver strength mode to configure
+ */
+void system_pinmux_group_set_output_strength(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_strength mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+				port->PINCFG[i].reg |=  PORT_PINCFG_DRVSTR;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Configures the output driver mode for a group of pins.
+ *
+ * Configures the output driver mode for a group of pins, to
+ * control the pad behavior.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] mode New pad output driver mode to configure
+ */
+void system_pinmux_group_set_output_drive(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_drive mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+				port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
+			}
+		}
+	}
+}
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.h
new file mode 100644
index 0000000000..e057ad60ba
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.h
@@ -0,0 +1,676 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef PINMUX_H_INCLUDED
+#define PINMUX_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer (SYSTEM PINMUX) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's physical
+ * I/O Pins, to alter the direction and input/drive characteristics as well as
+ * to configure the pin peripheral multiplexer selection.
+ *
+ * The following peripheral is used by this module:
+ *  - PORT (Port I/O Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_pinmux_prerequisites
+ *  - \ref asfdoc_sam0_system_pinmux_module_overview
+ *  - \ref asfdoc_sam0_system_pinmux_special_considerations
+ *  - \ref asfdoc_sam0_system_pinmux_extra_info
+ *  - \ref asfdoc_sam0_system_pinmux_examples
+ *  - \ref asfdoc_sam0_system_pinmux_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_module_overview Module Overview
+ *
+ * The SAM devices contain a number of General Purpose I/O pins, used to
+ * interface the user application logic and internal hardware peripherals to
+ * an external system. The Pin Multiplexer (PINMUX) driver provides a method
+ * of configuring the individual pin peripheral multiplexers to select
+ * alternate pin functions.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH</td>
+ *    <td>SAM L21, SAM C20/C21</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
+ * SAM devices contain a peripheral MUX, which is individually controllable
+ * for each I/O pin of the device. The peripheral MUX allows you to select the
+ * function of a physical package pin - whether it will be controlled as a user
+ * controllable GPIO pin, or whether it will be connected internally to one of
+ * several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
+ * configured in GPIO mode, other peripherals connected to the same pin will be
+ * disabled.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
+ * There are several special modes that can be selected on one or more I/O pins
+ * of the device, which alter the input and output characteristics of the pad.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
+ * The Drive Strength configures the strength of the output driver on the
+ * pad. Normally, there is a fixed current limit that each I/O pin can safely
+ * drive, however some I/O pads offer a higher drive mode which increases this
+ * limit for that I/O pin at the expense of an increased power consumption.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
+ * The Slew Rate configures the slew rate of the output driver, limiting the
+ * rate at which the pad output voltage can change with time.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
+ * The Input Sample Mode configures the input sampler buffer of the pad. By
+ * default, the input buffer is only sampled "on-demand", i.e. when the user
+ * application attempts to read from the input buffer. This mode is the most
+ * power efficient, but increases the latency of the input sample by two clock
+ * cycles of the port clock. To reduce latency, the input sampler can instead
+ * be configured to always sample the input buffer on each port clock cycle, at
+ * the expense of an increased power consumption.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
+ * how this module is interconnected within the device:
+ *
+ * \anchor asfdoc_sam0_system_pinmux_intconnections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> gpio;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampling mode is set in groups of four physical
+ * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
+ * will configure the sampling mode of the entire sub-group.
+ *
+ * High Drive Strength output driver mode is not available on all device pins -
+ * refer to your device specific datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes:
+ *  - \ref asfdoc_sam0_system_pinmux_extra_acronyms
+ *  - \ref asfdoc_sam0_system_pinmux_extra_dependencies
+ *  - \ref asfdoc_sam0_system_pinmux_extra_errata
+ *  - \ref asfdoc_sam0_system_pinmux_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_pinmux_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*@{*/
+#if (SAML21) || (SAMC20) || (SAMC21) || (SAMD21) || (SAMD10) || (SAMD11) || (SAMR30) || defined(__DOXYGEN__)
+/** Output Driver Strength Selection feature support */
+#  define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+#endif
+/*@}*/
+
+/** Peripheral multiplexer index to select GPIO mode for a pin */
+#define SYSTEM_PINMUX_GPIO    (1 << 7)
+
+/**
+ * \brief Port pin direction configuration enum.
+ *
+ * Enum for the possible pin direction settings of the port pin configuration
+ * structure, to indicate the direction the pin should use.
+ */
+enum system_pinmux_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read */
+	SYSTEM_PINMUX_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set (but not read back) */
+	SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+	/** The pin's output and input buffers should both be enabled, so that the
+	 *  pin state can be set and read back */
+	SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ * \brief Port pin input pull configuration enum.
+ *
+ * Enum for the possible pin pull settings of the port pin configuration
+ * structure, to indicate the type of logic level pull the pin should use.
+ */
+enum system_pinmux_pin_pull {
+	/** No logical pull should be applied to the pin */
+	SYSTEM_PINMUX_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Pin should be pulled down when idle */
+	SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+/**
+ * \brief Port pin digital input sampling mode enum.
+ *
+ * Enum for the possible input sampling modes for the port pin configuration
+ * structure, to indicate the type of sampling a port pin should use.
+ */
+enum system_pinmux_pin_sample {
+	/** Pin input buffer should continuously sample the pin state */
+	SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
+	/** Pin input buffer should be enabled when the IN register is read */
+	SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
+};
+
+/**
+ * \brief Port pin configuration structure.
+ *
+ * Configuration structure for a port pin instance. This structure should
+ * be initialized by the \ref system_pinmux_get_config_defaults() function
+ * before being modified by the user application.
+ */
+struct system_pinmux_config {
+	/** MUX index of the peripheral that should control the pin, if peripheral
+	 *  control is desired. For GPIO use, this should be set to
+	 *  \ref SYSTEM_PINMUX_GPIO. */
+	uint8_t mux_position;
+
+	/** Port buffer input/output direction */
+	enum system_pinmux_pin_dir direction;
+
+	/** Logic level pull of the input buffer */
+	enum system_pinmux_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled.
+	 */
+	bool powersave;
+};
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes a Port pin configuration structure to defaults.
+ *
+ * Initializes a given Port pin configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Non peripheral (i.e. GPIO) controlled
+ *  \li Input mode with internal pull-up enabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_pinmux_get_config_defaults(
+		struct system_pinmux_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->mux_position = SYSTEM_PINMUX_GPIO;
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	config->powersave    = false;
+}
+
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config);
+
+void system_pinmux_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct system_pinmux_config *const config);
+
+/** @} */
+
+/** \name Special Mode Configuration (Physical Group Orientated)
+ *  @{
+ */
+
+/**
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ * Retrieves the PORT module group instance associated with a given logical
+ * GPIO pin number.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to convert
+ *
+ * \return Base address of the associated PORT module.
+ */
+static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
+		const uint8_t gpio_pin)
+{
+	uint8_t port_index  = (gpio_pin / 128);
+	uint8_t group_index = (gpio_pin / 32);
+
+	/* Array of available ports */
+	Port *const ports[PORT_INST_NUM] = PORT_INSTS;
+
+	if (port_index < PORT_INST_NUM) {
+		return &(ports[port_index]->Group[group_index]);
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+
+void system_pinmux_group_set_input_sample_mode(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_sample mode);
+
+/** @} */
+
+/** \name Special Mode Configuration (Logical Pin Orientated)
+ *  @{
+ */
+
+/**
+ * \brief Retrieves the currently selected MUX position of a logical pin.
+ *
+ * Retrieves the selected MUX peripheral on a given logical GPIO pin.
+ *
+ * \param[in]  gpio_pin  Index of the GPIO pin to configure
+ *
+ * \return Currently selected peripheral index on the specified pin.
+ */
+static inline uint8_t system_pinmux_pin_get_mux_position(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_index = (gpio_pin % 32);
+
+	if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
+		return SYSTEM_PINMUX_GPIO;
+	}
+
+	uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
+
+	if (pin_index & 1) {
+		return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	}
+	else {
+		return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	}
+}
+
+/**
+ * \brief Configures the input sampling mode for a GPIO pin.
+ *
+ * Configures the input sampling mode for a GPIO input, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] mode     New pin sampling mode to configure
+ */
+static inline void system_pinmux_pin_set_input_sample_mode(
+		const uint8_t gpio_pin,
+		const enum system_pinmux_pin_sample mode)
+{
+	PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_index = (gpio_pin % 32);
+
+	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+		port->CTRL.reg |= (1 << pin_index);
+	} else {
+		port->CTRL.reg &= ~(1 << pin_index);
+	}
+}
+
+/** @} */
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Port pin drive output strength enum.
+ *
+ * Enum for the possible output drive strengths for the port pin
+ * configuration structure, to indicate the driver strength the pin should
+ * use.
+ */
+enum system_pinmux_pin_strength {
+  /** Normal output driver strength */
+  SYSTEM_PINMUX_PIN_STRENGTH_NORMAL,
+  /** High current output driver strength */
+  SYSTEM_PINMUX_PIN_STRENGTH_HIGH,
+};
+
+/**
+ * \brief Configures the output driver strength mode for a GPIO pin.
+ *
+ * Configures the output drive strength for a GPIO output, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New output driver strength mode to configure
+ */
+static inline void system_pinmux_pin_set_output_strength(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_strength mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_DRVSTR;
+  }
+ else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR;
+ }
+}
+
+void system_pinmux_group_set_output_strength(
+    PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_strength mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Port pin output slew rate enum.
+ *
+ * Enum for the possible output drive slew rates for the port pin
+ * configuration structure, to indicate the driver slew rate the pin should
+ * use.
+ */
+enum system_pinmux_pin_slew_rate {
+  /** Normal pin output slew rate */
+  SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL,
+  /** Enable slew rate limiter on the pin */
+  SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED,
+};
+
+/**
+ * \brief Configures the output slew rate mode for a GPIO pin.
+ *
+ * Configures the output slew rate mode for a GPIO output, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New pin slew rate mode to configure
+ */
+static inline void system_pinmux_pin_set_output_slew_rate(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_slew_rate mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_SLEWLIM;
+  }
+  else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM;
+  }
+}
+
+void system_pinmux_group_set_output_slew_rate(
+   PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_slew_rate mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Port pin output drive mode enum.
+ *
+ * Enum for the possible output drive modes for the port pin configuration
+ * structure, to indicate the output mode the pin should use.
+ */
+enum system_pinmux_pin_drive {
+  /** Use totem pole output drive mode */
+  SYSTEM_PINMUX_PIN_DRIVE_TOTEM,
+  /** Use open drain output drive mode */
+  SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN,
+};
+
+/**
+ * \brief Configures the output driver mode for a GPIO pin.
+ *
+ * Configures the output driver mode for a GPIO output, to
+ * control the pad behavior.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New pad output driver mode to configure
+ */
+static inline void system_pinmux_pin_set_output_drive(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_drive mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_ODRAIN;
+  }
+  else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN;
+  }
+}
+
+void system_pinmux_group_set_output_drive(
+    PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_drive mode);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Removed code of open drain, slew limit and drive strength
+ *		features</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Fixed broken sampling mode function implementations, which wrote
+ *		    corrupt configuration values to the device registers</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added missing NULL pointer asserts to the PORT driver functions</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that a QSG can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_pinmux_basic_use_case
+ *
+ * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121F</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121E</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121D</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121C</td>
+ *		<td>09/2013</td>
+ *		<td>Fixed incorrect documentation for the device pin sampling mode</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_c/power.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_c/power.h
new file mode 100644
index 0000000000..53c02e9063
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_c/power.h
@@ -0,0 +1,392 @@
+/**
+ * \file
+ *
+ * \brief SAM C2x Power functionality
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef POWER_H_INCLUDED
+#define POWER_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Device sleep modes.
+ *
+ * List of available sleep modes in the device. A table of clocks available in
+ * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ */
+enum system_sleepmode {
+	/** IDLE 0 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_0 = PM_SLEEPCFG_SLEEPMODE(0),
+	/** IDLE 1 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_1 = PM_SLEEPCFG_SLEEPMODE(0x1),
+	/** IDLE 2 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_2 = PM_SLEEPCFG_SLEEPMODE(0x2),
+	/** Standby sleep mode */
+	SYSTEM_SLEEPMODE_STANDBY = PM_SLEEPCFG_SLEEPMODE(0x4),
+};
+
+/**
+ * \brief Voltage reference value for ADC/DAC.
+ *
+ * Voltage references selection for ADC/DAC.
+ */
+enum system_voltage_references_sel {
+	/** 1.024V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V024  = SUPC_VREF_SEL_1V024_Val,
+	/** 2.048V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V048  = SUPC_VREF_SEL_2V048_Val,
+	/** 4.096V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_4V096    = SUPC_VREF_SEL_4V096_Val,
+};
+
+
+/**
+ * \brief Voltage reference.
+ *
+ * List of available voltage references (VREF) that may be used within the
+ * device.
+ */
+enum system_voltage_reference {
+	/** Temperature sensor voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+	/** Voltage reference output for ADC/DAC */
+	SYSTEM_VOLTAGE_REFERENCE_OUTPUT,
+};
+
+/**
+ * \brief Voltage Regulator System (VREG) Control configuration.
+ *
+ * Configuration structure for VREG.
+ */
+struct system_voltage_regulator_config {
+	/** Run in standby in standby sleep mode */
+	bool run_in_standby;
+};
+
+/**
+ * \brief Voltage References System (VREF) Control configuration.
+ *
+ * Configuration structure for VREF.
+ */
+struct system_voltage_references_config {
+	/** Voltage references selection */
+	enum system_voltage_references_sel  sel;
+	/** On demand control */
+	bool on_demand;
+	/** Run in standby */
+	bool run_in_standby;
+};
+
+/**
+ * \brief Voltage Regulator switch in Standby mode.
+ *
+ */
+enum system_vreg_switch_mode {
+	/** Automatic mode */
+	SYSTEM_VREG_SWITCH_AUTO        = PM_STDBYCFG_VREGSMOD_AUTO_Val,
+	/** Performance oriented */
+	SYSTEM_VREG_SWITCH_PERFORMANCE = PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val,
+	/** Low Power consumption oriented */
+	SYSTEM_VREG_SWITCH_LP          = PM_STDBYCFG_VREGSMOD_LP_Val,
+};
+
+/**
+ * \brief Standby configuration.
+ *
+ * Configuration structure for standby mode.
+ */
+struct system_standby_config {
+	/** Regulator switch mode in standby */
+	enum system_vreg_switch_mode vreg_switch_mode;
+	/** Back bias for HMCRAMCHS (false: no, true: standby) */
+	bool hmcramchs_back_bias;
+};
+
+/**
+ * \name Voltage Regulator
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for voltage regulator.
+ *
+ * Fills a configuration structure with the default configuration:
+ *   - The voltage regulator is in low power mode in Standby sleep mode
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_voltage_regulator_get_config_defaults(
+		struct system_voltage_regulator_config *const config)
+{
+	Assert(config);
+	config->run_in_standby       = false;
+}
+
+/**
+ * \brief Configure voltage regulator.
+ *
+ * Configures voltage regulator with the given configuration.
+ *
+ * \param[in] config  Voltage regulator configuration structure containing
+ *                    the new config
+ */
+static inline void system_voltage_regulator_set_config(
+		struct system_voltage_regulator_config *const config)
+{
+	SUPC->VREG.bit.RUNSTDBY = config->run_in_standby;
+}
+
+/**
+* \brief Enable the selected voltage regulator.
+ *
+ * Enables the selected voltage regulator source.
+ */
+static inline void system_voltage_regulator_enable(void)
+{
+	SUPC->VREG.reg |= SUPC_VREG_ENABLE;
+}
+
+/**
+ * \brief Disable the selected voltage regulator.
+ *
+ * Disables the selected voltage regulator.
+ */
+static inline void system_voltage_regulator_disable(void)
+{
+	SUPC->VREG.reg &= ~SUPC_VREG_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Voltage References
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for voltage reference.
+ *
+ * Fill a configuration structure with the default configuration:
+ *   - 1.024V voltage reference typical value
+ *   - On demand control:disabled
+ *   - The voltage reference and the temperature sensor are halted during standby sleep mode
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_voltage_reference_get_config_defaults(
+		struct system_voltage_references_config *const config)
+{
+	Assert(config);
+	config->sel            = SYSTEM_VOLTAGE_REFERENCE_1V024;
+	config->on_demand      = false;
+	config->run_in_standby = false;
+}
+
+/**
+ * \brief Configure voltage reference.
+ *
+ * Configures voltage reference with the given configuration.
+ *
+ * \param[in] config  Voltage reference configuration structure containing
+ *                    the new config
+ */
+static inline void system_voltage_reference_set_config(
+		struct system_voltage_references_config *const config)
+{
+	Assert(config);
+	SUPC->VREF.bit.SEL      = config->sel;
+	SUPC->VREF.bit.ONDEMAND = config->on_demand;
+	SUPC->VREF.bit.RUNSTDBY = config->run_in_standby;
+}
+
+/**
+ * \brief Enable the selected voltage reference.
+ *
+ * Enables the selected voltage reference source, making the voltage reference
+ * available on a pin as well as an input source to the analog peripherals.
+ *
+ * \param[in] vref  Voltage reference to enable
+ */
+static inline void system_voltage_reference_enable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SUPC->VREF.reg |= SUPC_VREF_TSEN;
+			break;
+		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+			SUPC->VREF.reg |= SUPC_VREF_VREFOE;
+			break;
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * \brief Disable the selected voltage reference.
+ *
+ * Disables the selected voltage reference source.
+ *
+ * \param[in] vref  Voltage reference to disable
+ */
+static inline void system_voltage_reference_disable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SUPC->VREF.reg &= ~SUPC_VREF_TSEN;
+			break;
+		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+			SUPC->VREF.reg &= ~SUPC_VREF_VREFOE;
+			break;
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Device Sleep Control
+ * @{
+ */
+
+/**
+ * \brief Set the sleep mode of the device.
+ *
+ * Sets the sleep mode of the device; the configured sleep mode will be entered
+ * upon the next call of the \ref system_sleep() function.
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ *
+ * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
+ */
+static inline void system_set_sleepmode(
+	const enum system_sleepmode sleep_mode)
+{
+	PM->SLEEPCFG.reg = sleep_mode;
+}
+
+
+/**
+ * \brief Put the system to sleep waiting for interrupt.
+ *
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
+ * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
+ * instruction to place the device into the sleep mode specified by
+ * \ref system_set_sleepmode until woken by an interrupt.
+ */
+static inline void system_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Standby Configuration
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for standby.
+ *
+ * Fills a configuration structure with the default configuration for standby:
+ *   - Automatic VREG switching is used
+ *   - Retention back biasing mode for HMCRAMCHS
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_standby_get_config_defaults(
+		struct system_standby_config *const config)
+{
+	Assert(config);
+
+	config->vreg_switch_mode    = SYSTEM_VREG_SWITCH_AUTO;
+	config->hmcramchs_back_bias = false;
+}
+
+/**
+ * \brief Configure standby mode.
+ *
+ * Configures standby with the given configuration.
+ *
+ * \param[in] config  Standby configuration structure containing
+ *                    the new config
+ */
+static inline void system_standby_set_config(
+		struct system_standby_config *const config)
+{
+	Assert(config);
+
+	PM->STDBYCFG.reg = PM_STDBYCFG_VREGSMOD(config->vreg_switch_mode) |
+					 PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias);
+}
+
+/** @} */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* POWER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_d_r_h/power.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_d_r_h/power.h
new file mode 100644
index 0000000000..e63f1cdb62
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_d_r_h/power.h
@@ -0,0 +1,249 @@
+/**
+ * \file
+ *
+ * \brief SAM Power related functionality
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef POWER_H_INCLUDED
+#define POWER_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MCU revision number */
+#define _SYSTEM_MCU_REVISION_D 3
+#define _SYSTEM_MCU_REVISION_E 4
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Voltage references within the device.
+ *
+ * List of available voltage references (VREF) that may be used within the
+ * device.
+ */
+enum system_voltage_reference {
+	/** Temperature sensor voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+	/** Bandgap voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
+};
+
+/**
+ * \brief Device sleep modes.
+ *
+ * List of available sleep modes in the device. A table of clocks available in
+ * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ */
+enum system_sleepmode {
+	/** IDLE 0 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_0,
+	/** IDLE 1 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_1,
+	/** IDLE 2 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_2,
+	/** Standby sleep mode */
+	SYSTEM_SLEEPMODE_STANDBY,
+};
+
+
+
+/**
+ * \name Voltage References
+ * @{
+ */
+
+/**
+ * \brief Enable the selected voltage reference
+ *
+ * Enables the selected voltage reference source, making the voltage reference
+ * available on a pin as well as an input source to the analog peripherals.
+ *
+ * \param[in] vref  Voltage reference to enable
+ */
+static inline void system_voltage_reference_enable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
+			break;
+
+		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+			SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
+			break;
+
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * \brief Disable the selected voltage reference
+ *
+ * Disables the selected voltage reference source.
+ *
+ * \param[in] vref  Voltage reference to disable
+ */
+static inline void system_voltage_reference_disable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
+			break;
+
+		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
+			break;
+
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Device Sleep Control
+ * @{
+ */
+
+/**
+ * \brief Set the sleep mode of the device
+ *
+ * Sets the sleep mode of the device; the configured sleep mode will be entered
+ * upon the next call of the \ref system_sleep() function.
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ *
+ * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
+ *
+ * \retval STATUS_OK               Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG  The requested sleep mode was invalid or not
+ *                                 available
+ */
+static inline enum status_code system_set_sleepmode(
+	const enum system_sleepmode sleep_mode)
+{
+
+#if (SAMD20 || SAMD21 || SAMR21)
+
+	/* Get MCU revision */
+	uint32_t rev = DSU->DID.reg;
+
+	rev &= DSU_DID_REVISION_Msk;
+	rev = rev >> DSU_DID_REVISION_Pos;
+
+#if (SAMD20)
+	if (rev < _SYSTEM_MCU_REVISION_E) {
+		/* Errata 13140: Make sure that the Flash does not power all the way down
+		 * when in sleep mode. */
+		NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
+	}
+#endif
+
+#if (SAMD21 || SAMR21)
+	if (rev < _SYSTEM_MCU_REVISION_D) {
+		/* Errata 13140: Make sure that the Flash does not power all the way down
+		 * when in sleep mode. */
+		NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
+	}
+#endif
+
+#endif
+
+	switch (sleep_mode) {
+		case SYSTEM_SLEEPMODE_IDLE_0:
+		case SYSTEM_SLEEPMODE_IDLE_1:
+		case SYSTEM_SLEEPMODE_IDLE_2:
+			SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+			PM->SLEEP.reg = sleep_mode;
+			break;
+
+		case SYSTEM_SLEEPMODE_STANDBY:
+			SCB->SCR |=  SCB_SCR_SLEEPDEEP_Msk;
+			break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Put the system to sleep waiting for interrupt
+ *
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
+ * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
+ * instruction to place the device into the sleep mode specified by
+ * \ref system_set_sleepmode until woken by an interrupt.
+ */
+static inline void system_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* POWER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_l/power.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_l/power.h
new file mode 100644
index 0000000000..eddf533f56
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_l/power.h
@@ -0,0 +1,1000 @@
+/**
+ * \file
+ *
+ * \brief SAM L21/L22/R30 Power functionality
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef POWER_H_INCLUDED
+#define POWER_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Device sleep modes.
+ *
+ * List of available sleep modes in the device. A table of clocks available in
+ * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ */
+enum system_sleepmode {
+	/** IDLE sleep mode */
+	SYSTEM_SLEEPMODE_IDLE       = PM_SLEEPCFG_SLEEPMODE(0x2),
+	/** STANDBY sleep mode */
+	SYSTEM_SLEEPMODE_STANDBY    = PM_SLEEPCFG_SLEEPMODE_STANDBY,
+	/** BACKUP sleep mode */
+	SYSTEM_SLEEPMODE_BACKUP     = PM_SLEEPCFG_SLEEPMODE_BACKUP,
+	/** OFF sleep mode */
+	SYSTEM_SLEEPMODE_OFF        = PM_SLEEPCFG_SLEEPMODE_OFF,
+};
+
+/**
+ * \brief Performance level.
+ *
+ * List of performance levels. Performance level technique consists of
+ * adjusting the regulator output voltage to reduce power consumption.
+ */
+enum system_performance_level {
+	/** Performance level 0 */
+	SYSTEM_PERFORMANCE_LEVEL_0  = PM_PLCFG_PLSEL_PL0,
+	/** Performance level 2 */
+	SYSTEM_PERFORMANCE_LEVEL_2  = PM_PLCFG_PLSEL_PL2,
+};
+
+/**
+ * \brief RAM Back-biasing mode.
+ *
+ * List of RAM back bias modes. By default, in standby sleep mode,
+ * RAM is in low power mode (back biased) if its power domain is in
+ * retention state. This behavior can be changed by configuring the Back Bias
+ * bit groups in STDBYCFG(STDBYCFG.BBIASxx).
+ */
+enum system_ram_back_bias_mode {
+	/** Retention Back biasing mode */
+	SYSTEM_RAM_BACK_BIAS_RETENTION = 0,
+	/** Standby Back Biasing mode */
+	SYSTEM_RAM_BACK_BIAS_STANDBY,
+	/** Standby OFF mode */
+	SYSTEM_RAM_BACK_BIAS_STANDBY_OFF,
+	/** Always OFF mode */
+	SYSTEM_RAM_BACK_BIAS_OFF,
+};
+
+#if SAML21 || SAMR30
+/**
+ * \brief Linked power domain.
+ *
+ * List of linked power domains. Power domains can be linked to each other.
+ * It allows a power domain (PDn) to be kept in active state if the inferior
+ * power domain (PDn-1) is in active state too.
+ */
+enum system_linked_power_domain {
+	/** Power domains PD0/PD1/PD2 are not linked */
+	SYSTEM_LINKED_POWER_DOMAIN_DEFAULT   = PM_STDBYCFG_LINKPD_DEFAULT_Val,
+	/** Power domains PD0 and PD1 are linked */
+	SYSTEM_LINKED_POWER_DOMAIN_PD01      = PM_STDBYCFG_LINKPD_PD01_Val,
+	/** Power domains PD1 and PD2 are linked */
+	SYSTEM_LINKED_POWER_DOMAIN_PD12      = PM_STDBYCFG_LINKPD_PD12_Val,
+	/** All Power domains are linked */
+	SYSTEM_LINKED_POWER_DOMAIN_PD012     = PM_STDBYCFG_LINKPD_PD012_Val,
+};
+
+#if (SAML21XXXB) || (SAMR30)
+/**
+ * \brief VREG switching mode.
+ *
+ * List of VREG switching modes.
+ */
+enum system_vreg_switch_mode {
+	/** Automatic mode. */
+	SYSTEM_SYSTEM_VREG_SWITCH_AUTO = 0,
+	/** Performance oriented. */
+	SYSTEM_SYSTEM_VREG_SWITCH_PERFORMANCE,
+	/** Low Power consumption oriented. */
+	SYSTEM_SYSTEM_VREG_SWITCH_LP,
+};
+#endif
+
+/**
+ * \brief Power domain.
+ *
+ * List of power domains. Power domain gating technique consists of turning
+ * on or off power domain voltage to save power while keeping other domains
+ * powered up.
+ */
+enum system_power_domain {
+	/** All power domains switching are handled by hardware */
+	SYSTEM_POWER_DOMAIN_DEFAULT = PM_STDBYCFG_PDCFG_DEFAULT_Val,
+	/** Power domain 0 (PD0) is forced ACTIVE */
+	SYSTEM_POWER_DOMAIN_PD0     = PM_STDBYCFG_PDCFG_PD0_Val,
+	/** Power domain 0 and 1 (PD0 and PD1) are forced ACTIVE */
+	SYSTEM_POWER_DOMAIN_PD01    = PM_STDBYCFG_PDCFG_PD01_Val,
+	/** All power domains are forced ACTIVE */
+	SYSTEM_POWER_DOMAIN_PD012   = PM_STDBYCFG_PDCFG_PD012_Val,
+};
+#endif
+
+#if SAML22
+/**
+ * \brief Voltage Regulator switch in Standby mode.
+ *
+ */
+enum system_vreg_switch_mode {
+	/** Automatic mode. */
+	SYSTEM_VREG_SWITCH_AUTO        = PM_STDBYCFG_VREGSMOD_AUTO_Val,
+	/** Performance oriented. */
+	SYSTEM_VREG_SWITCH_PERFORMANCE = PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val,
+	/** Low Power consumption oriented. */
+	SYSTEM_VREG_SWITCH_LP          = PM_STDBYCFG_VREGSMOD_LP_Val,
+};
+
+#endif
+
+/**
+ * \brief Voltage regulator.
+ *
+ * Voltage regulators selection. In active mode, the voltage regulator
+ * can be chosen on the fly between a LDO or a Buck converter.
+ */
+enum system_voltage_regulator_sel {
+	/** The voltage regulator in active mode is a LDO voltage regulator */
+	SYSTEM_VOLTAGE_REGULATOR_LDO    = SUPC_VREG_SEL_LDO_Val,
+	/** The voltage regulator in active mode is a buck converter */
+	SYSTEM_VOLTAGE_REGULATOR_BUCK   = SUPC_VREG_SEL_BUCK_Val,
+};
+
+/**
+ * \brief Low power efficiency.
+ *
+ * Low power mode efficiency.
+ */
+enum system_voltage_regulator_low_power_efficiency {
+	/** The voltage regulator in Low power mode has the default efficiency and
+		support the whole VDD range (1.62V to 3.6V) */
+	SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT,
+	/** The voltage regulator in Low power mode has the highest efficiency and
+		support the limited VDD range (2.5V to 3.6V) */
+	SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_HIGHTEST,
+};
+
+/**
+ * \brief Voltage reference value.
+ *
+ * Voltage references selection.
+ */
+enum system_voltage_references_sel {
+	/** 1.0V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V0    = SUPC_VREF_SEL_1V0_Val,
+	/** 1.1V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V1    = SUPC_VREF_SEL_1V1_Val,
+	/** 1.2V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V2    = SUPC_VREF_SEL_1V2_Val,
+	/** 1.25V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V25   = SUPC_VREF_SEL_1V25_Val,
+	/** 2.0V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V0    = SUPC_VREF_SEL_2V0_Val,
+	/** 2.2V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V2    = SUPC_VREF_SEL_2V2_Val,
+	/** 2.4V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V4    = SUPC_VREF_SEL_2V4_Val,
+	/** 2.5V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V5    = SUPC_VREF_SEL_2V5_Val,
+};
+
+/**
+ * \brief Battery power switch configuration enum.
+ *
+ * Enum for Battery power switch modes.
+ */
+enum system_battery_power_switch {
+	/** The backup domain is always supplied by main power */
+	SYSTEM_BATTERY_POWER_SWITCH_NONE      = SUPC_BBPS_CONF_NONE_Val,
+	/** The power switch is handled by the automatic power switch */
+	SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC = SUPC_BBPS_CONF_APWS_Val,
+	/** The backup domain is always supplied by battery backup power */
+	SYSTEM_BATTERY_POWER_SWITCH_FORCED    = SUPC_BBPS_CONF_FORCED_Val,
+	/** The power switch is handled by the BOD33 */
+	SYSTEM_BATTERY_POWER_SWITCH_BOD33     = SUPC_BBPS_CONF_BOD33_Val,
+};
+
+/**
+ * \brief Voltage reference.
+ *
+ * List of available voltage references (VREF) that may be used within the
+ * device.
+ */
+enum system_voltage_reference {
+	/** Temperature sensor voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+	/** Voltage reference output */
+	SYSTEM_VOLTAGE_REFERENCE_OUTPUT,
+};
+
+/**
+ * \brief Backup IO enum.
+ *
+ * List of Backup input and output pins.
+ * If enabled (\ref system_backup_pin_output_enable), the pins can be driven
+ * by the SUPC.
+ */
+enum system_backup_pin {
+	/** Power Supply OK status pin */
+	SYSTEM_BACKUP_PIN_PSOK  = (0x1 << 0),
+	/** Backup output pin 0  */
+	SYSTEM_BACKUP_PIN_OUT_0 = (0x1 << 1),
+	/** Backup output pin 1  */
+	SYSTEM_BACKUP_PIN_OUT_1 = (0x1 << 2)
+};
+
+/**
+ * \brief Standby configuration.
+ *
+ * Configuration structure for standby mode.
+ */
+struct system_standby_config {
+#if SAML21 || SAMR30
+	/** Power domain. */
+	enum system_power_domain  power_domain;
+	/** Enable dynamic power gating for power domain 0 */
+	bool enable_dpgpd0;
+	/** Enable dynamic power gating for power domain 1 */
+	bool enable_dpgpd1;
+#if (SAML21XXXA)
+	/** Automatic VREG switching disable. */
+	bool disable_avregsd;
+#else
+	/** VREG switching mode */
+	enum system_vreg_switch_mode vregs_mode;
+#endif
+	/** Linked power domain */
+	enum system_linked_power_domain linked_power_domain;
+#elif SAML22
+	/** Regulator switch mode in standby. */
+	enum system_vreg_switch_mode vreg_switch_mode;
+#endif
+	/** Back bias for HMCRAMCHS. */
+	enum system_ram_back_bias_mode hmcramchs_back_bias;
+	/** Back bias for HMCRAMCLP */
+	enum system_ram_back_bias_mode hmcramclp_back_bias;
+};
+
+/**
+ * \brief Voltage Regulator System (VREG) Control configuration.
+ *
+ * Configuration structure for VREG.
+ */
+struct system_voltage_regulator_config {
+	/** Voltage scaling period */
+	uint8_t  voltage_scale_period;
+	/** Voltage scaling voltage step */
+	uint8_t voltage_scale_step;
+	/** Run in standby in standby sleep mode */
+	bool run_in_standby;
+	/** Voltage Regulator Selection */
+	enum system_voltage_regulator_sel  regulator_sel;
+	/** Low power efficiency */
+	enum system_voltage_regulator_low_power_efficiency low_power_efficiency;
+#if SAML22 || SAML21XXXB
+	/** Run in standby in performance level 0. */
+	bool run_in_standby_pl0;
+#endif
+};
+
+/**
+ * \brief Voltage References System (VREF) Control configuration.
+ *
+ * Configuration structure for VREF.
+ */
+struct system_voltage_references_config {
+	/** Voltage References Selection */
+	enum system_voltage_references_sel  sel;
+	/** On Demand Control */
+	bool on_demand;
+	/** Run in standby */
+	bool run_in_standby;
+#if SAML22
+	/** Temperature Sensor Selection. */
+	bool temperature_sensor_sel;
+#endif
+};
+
+/**
+ * \brief Battery Backup Power Switch (BBPS) Control configuration.
+ *
+ * Configuration structure for Battery Backup Power Switch (BBPS).
+ */
+struct system_battery_backup_power_switch_config {
+	/** Enable device wake up when BBPS switches from
+		battery backup power to main power */
+	bool wake_enabled;
+	/** Battery backup power switch configuration */
+	enum system_battery_power_switch battery_power_switch;
+};
+
+/**
+ * \name Voltage Regulator
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for voltage regulator.
+ *
+ * Fills a configuration structure with the default configuration:
+ *   - Voltage scaling period is 1渭s
+ *   - Voltage scaling voltage step is 2*min_step
+ *   - The voltage regulator is in low power mode in Standby sleep mode
+ *   - The voltage regulator in active mode is an LDO voltage regulator
+ *   - The voltage regulator in Low power mode has the default efficiency
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_voltage_regulator_get_config_defaults(
+		struct system_voltage_regulator_config *const config)
+{
+	Assert(config);
+	config->voltage_scale_period = 0;
+	config->voltage_scale_step   = 0;
+	config->run_in_standby       = false;
+	config->regulator_sel        = SYSTEM_VOLTAGE_REGULATOR_LDO;
+	config->low_power_efficiency = SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT;
+#if SAML22 || SAML21XXXB
+	config->run_in_standby_pl0   = false;
+#endif
+}
+
+/**
+ * \brief Configure voltage regulator.
+ *
+ * Configures voltage regulator with the given configuration.
+ *
+ * \param[in] config  Voltage regulator configuration structure containing
+ *                    the new config
+ */
+static inline void system_voltage_regulator_set_config(
+		struct system_voltage_regulator_config *const config)
+{
+	Assert(config);
+	SUPC->VREG.bit.VSPER    = config->voltage_scale_period;
+	SUPC->VREG.bit.VSVSTEP  = config->voltage_scale_step;
+	SUPC->VREG.bit.RUNSTDBY = config->run_in_standby;
+	SUPC->VREG.bit.SEL      = config->regulator_sel;
+#if (SAML21XXXB) || (SAMR30)
+	SUPC->VREG.bit.LPEFF    = config->low_power_efficiency;
+#endif
+#if SAML22 || SAML21XXXB
+	SUPC->VREG.bit.STDBYPL0 = config->run_in_standby_pl0;
+#endif
+	while(!(SUPC->STATUS.reg & SUPC_STATUS_VREGRDY)) {
+		;
+	}
+}
+
+/**
+* \brief Enable the selected voltage regulator.
+ *
+ * Enables the selected voltage regulator source.
+ */
+static inline void system_voltage_regulator_enable(void)
+{
+	SUPC->VREG.reg |= SUPC_VREG_ENABLE;
+}
+
+/**
+ * \brief Disable the selected voltage regulator.
+ *
+ * Disables the selected voltage regulator.
+ */
+static inline void system_voltage_regulator_disable(void)
+{
+	SUPC->VREG.reg &= ~SUPC_VREG_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Voltage References
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for voltage reference.
+ *
+ * Fill a configuration structure with the default configuration:
+ *   - 1.0V voltage reference typical value
+ *   - On demand control disabled
+ *   - The voltage reference and the temperature sensor are halted during standby sleep mode
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_voltage_reference_get_config_defaults(
+		struct system_voltage_references_config *const config)
+{
+	Assert(config);
+	config->sel            = SYSTEM_VOLTAGE_REFERENCE_1V0;
+	config->on_demand      = false;
+	config->run_in_standby = false;
+#if SAML22
+	config->temperature_sensor_sel = false;
+#endif
+}
+
+/**
+ * \brief Configure voltage reference.
+ *
+ * Configures voltage reference with the given configuration.
+ *
+ * \param[in] config  Voltage reference configuration structure containing
+ *                    the new config
+ */
+static inline void system_voltage_reference_set_config(
+		struct system_voltage_references_config *const config)
+{
+	Assert(config);
+	SUPC->VREF.bit.SEL      = config->sel;
+	SUPC->VREF.bit.ONDEMAND = config->on_demand;
+	SUPC->VREF.bit.RUNSTDBY = config->run_in_standby;
+#if SAML22
+	SUPC->VREF.bit.TSSEL    = config->temperature_sensor_sel;
+#endif
+}
+
+/**
+ * \brief Enable the selected voltage reference.
+ *
+ * Enables the selected voltage reference source, making the voltage reference
+ * available on a pin as well as an input source to the analog peripherals.
+ *
+ * \param[in] vref  Voltage reference to enable
+ */
+static inline void system_voltage_reference_enable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SUPC->VREF.reg |= SUPC_VREF_TSEN;
+			break;
+		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+			SUPC->VREF.reg |= SUPC_VREF_VREFOE;
+			break;
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * \brief Disable the selected voltage reference.
+ *
+ * Disables the selected voltage reference source.
+ *
+ * \param[in] vref  Voltage reference to disable
+ */
+static inline void system_voltage_reference_disable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SUPC->VREF.reg &= ~SUPC_VREF_TSEN;
+			break;
+		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+			SUPC->VREF.reg &= ~SUPC_VREF_VREFOE;
+			break;
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Battery Backup Power Switch
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for battery backup power switch control.
+ *
+ * Fills a configuration structure with the default configuration:
+ *   - The main Power Supply OK status is not available on the PSOK pin
+ *   - The device is not woken up when switched from battery backup power to main power
+ *   - The backup domain is always supplied by main power
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_battery_backup_power_switch_get_config_defaults(
+		struct system_battery_backup_power_switch_config *const config)
+{
+	Assert(config);
+	config->wake_enabled         = false;
+	config->battery_power_switch = SYSTEM_BATTERY_POWER_SWITCH_NONE;
+}
+
+/**
+ * \brief Configure battery backup power switch.
+ *
+ * Configures battery backup power switch with the given configuration.
+ *
+ * \param[in] config  Battery backup power switch configuration structure containing
+ *                    the new config
+ */
+static inline void system_battery_backup_power_switch_set_config(
+		struct system_battery_backup_power_switch_config *const config)
+{
+	Assert(config);
+	uint32_t new_config = SUPC->BBPS.reg & SUPC_BBPS_PSOKEN;
+
+	if(config->wake_enabled) {
+		new_config |= SUPC_BBPS_WAKEEN;
+	}
+
+	new_config |= SUPC_BBPS_CONF(config->battery_power_switch);
+
+	SUPC->BBPS.reg = new_config;
+
+	if (config->battery_power_switch == SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC) {
+		while (!(SUPC->STATUS.reg & SUPC_STATUS_APWSRDY)) {
+			;
+		}
+	}
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Output Pins in Backup Mode
+ * @{
+ */
+
+/**
+ *  \brief Enable the backup pin output.
+ *
+ *  The output is enabled and driven by the SUPC.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_enable(
+		enum system_backup_pin pin)
+{
+	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
+		SUPC->BBPS.reg |= SUPC_BBPS_PSOKEN;
+	} else {
+		SUPC->BKOUT.reg |= SUPC_BKOUT_EN(pin >> 1);
+	}
+}
+
+/**
+ *  \brief Disable the backup pin output.
+ *
+ *  The output is not enabled.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_disable(
+		enum system_backup_pin pin)
+{
+	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
+		SUPC->BBPS.reg &= ~SUPC_BBPS_PSOKEN;
+	} else {
+		SUPC->BKOUT.reg &= ~SUPC_BKOUT_EN(pin >> 1);
+	}
+}
+
+/**
+ * \brief Check if backup pin output is enabled.
+ *
+ *  \param[in] pin Backup pin index
+ *
+ * \return The enabled status.
+ * \retval true The output is enabled
+ * \retval false The output is not enabled
+ */
+static inline bool system_backup_pin_output_is_enabled(
+		enum system_backup_pin pin)
+{
+	bool enabled = false;
+
+	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
+		if (SUPC->BBPS.reg & SUPC_BBPS_PSOKEN) {
+			enabled = true;
+		}
+	} else {
+		if (SUPC->BKOUT.reg & SUPC_BKOUT_EN(pin >> 1)) {
+			enabled = true;
+		}
+	}
+	return enabled;
+}
+
+/**
+ *  \brief Enable the backup pin toggle on RTC event.
+ *
+ *  Toggle output on RTC event is enabled.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_enable_rtc_toggle(
+		enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	SUPC->BKOUT.reg |= SUPC_BKOUT_RTCTGL(pin >> 1);
+}
+
+/**
+ *  \brief Disable the backup pin toggle on RTC event.
+ *
+ *  Toggle output on RTC event is disabled.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_disable_rtc_toggle(
+		enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	SUPC->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(pin >> 1);
+}
+
+/**
+ *  \brief Set the backup pin.
+ *
+ *  Set the corresponding output pin.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_set(
+		enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	SUPC->BKOUT.reg |= SUPC_BKOUT_SET(pin >> 1);
+}
+
+/**
+ *  \brief Clear the backup pin.
+ *
+ *  Clear the corresponding output.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_clear(
+		enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	SUPC->BKOUT.reg |= SUPC_BKOUT_CLR(pin >> 1);
+}
+
+/**
+ *  \brief Get the backup I/O input values.
+ *
+ *  Get the backup I/O data input values. If the corresponding pin is enabled,
+ *  the I/O input value is given on the pin.
+ *
+ *  \param[in] pin Backup pin index
+ *
+ * \return The backup I/O input level value.
+ */
+static inline bool system_backup_pin_output_get(enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	return (SUPC->BKIN.reg & SUPC_BKIN_BKIN(pin >> 1));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Device Sleep Control
+ * @{
+ */
+
+/**
+ * \brief Set the sleep mode of the device.
+ *
+ * Sets the sleep mode of the device; the configured sleep mode will be entered
+ * upon the next call of the \ref system_sleep() function.
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ *
+ * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
+ */
+static inline void system_set_sleepmode(
+	const enum system_sleepmode sleep_mode)
+{
+	PM->SLEEPCFG.reg = sleep_mode;
+	while(PM->SLEEPCFG.reg != sleep_mode) ;
+}
+
+/**
+ * \brief Put the system to sleep waiting for interrupt.
+ *
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
+ * all ongoing memory accesses have completed. Further, a WFI (Wait For Interrupt)
+ * instruction is executed to place the device into the sleep mode specified by
+ * \ref system_set_sleepmode.
+ */
+static inline void system_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Performance Level Control
+ * @{
+ */
+
+/**
+ * \brief Switch performance level.
+ *
+ *  The bus frequency must be reduced prior to scaling down the performance level,
+ *  in order to not exceed the maximum frequency allowed for the performance level.
+ *
+ *  When scaling up the performance level (for example from PL0 to PL2), the bus
+ *  frequency can be increased first when the performance level transition is
+ *  completed. Check the performance level status before increasing the frequency.
+ *
+ * \param[in] performance_level  Performance level to switch
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code system_switch_performance_level(
+					const enum system_performance_level performance_level)
+{
+
+	if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
+		return STATUS_OK;
+	}
+
+#if SAML22 || SAML21XXXB
+	if (PM->PLCFG.reg & PM_PLCFG_PLDIS) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+#endif
+
+	/* Clear performance level status */
+	PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
+
+	/* Switch performance level */
+	PM->PLCFG.reg = performance_level;
+
+	/* Waiting performance level ready */
+	while (!PM->INTFLAG.reg) {
+		;
+	}
+	return STATUS_OK;
+}
+
+#if SAML22 || SAML21XXXB
+/**
+ * \brief Enable performance level switch.
+ *
+ * Enable performance level switch.
+ */
+static inline void system_performance_level_enable(void)
+{
+	PM->PLCFG.reg &= ~PM_PLCFG_PLDIS;
+}
+
+/**
+ * \brief Disable performance level switch.
+ *
+ * Disable performance level switch.
+ */
+static inline void system_performance_level_disable(void)
+{
+	PM->PLCFG.reg |= PM_PLCFG_PLDIS;
+}
+#endif
+
+/**
+ * \brief Get performance level.
+ *
+ * Get performance level.
+ *
+ * \return Current performance level.
+ */
+static inline enum system_performance_level system_get_performance_level(void)
+{
+	return (enum system_performance_level)PM->PLCFG.reg;
+}
+
+/**
+ * \brief Get performance level status.
+ *
+ * Get performance level status.
+ * \return Performance level status: Written to one when the performance level is ready.
+ */
+static inline uint8_t system_get_performance_level_status(void)
+{
+	return PM->INTFLAG.reg;
+}
+
+/**
+ * \brief Clear performance level status.
+ *
+ * Clear performance level status.
+ */
+static inline void system_clear_performance_level_status(void)
+{
+	PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Standby Configuration
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for standby.
+ *
+ * Fills a configuration structure with the default configuration for standby:
+ *   - Retention back biasing mode for HMCRAMCLP
+ *   - Retention back biasing mode for HMCRAMCHS
+ *   - Power domains PD0/PD1/PD2 are not linked
+ *   - Automatic VREG switching is used
+ *   - Dynamic power gating for power domain 1 is disabled
+ *   - Dynamic power gating for power domain 0 is disabled
+ *   - All power domains switching are handled by hardware
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_standby_get_config_defaults(
+		struct system_standby_config *const config)
+{
+	Assert(config);
+#if SAML21 || SAMR30
+	config->power_domain        = SYSTEM_POWER_DOMAIN_DEFAULT;
+	config->enable_dpgpd0       = false;
+	config->enable_dpgpd1       = false;
+#if (SAML21XXXB) || (SAMR30)
+	config->vregs_mode          = SYSTEM_SYSTEM_VREG_SWITCH_AUTO;
+#else
+	config->disable_avregsd     = false;
+#endif
+	config->linked_power_domain = SYSTEM_LINKED_POWER_DOMAIN_DEFAULT;
+#elif SAML22
+	config->vreg_switch_mode    = SYSTEM_VREG_SWITCH_AUTO;
+#endif
+	config->hmcramchs_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION;
+	config->hmcramclp_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION;
+}
+
+/**
+ * \brief Configure standby mode.
+ *
+ * Configures standby with the given configuration.
+ *
+ * \param[in] config  Standby configuration structure containing
+ *                    the new config
+ */
+static inline void system_standby_set_config(
+		struct system_standby_config *const config)
+{
+	Assert(config);
+#if SAML21 || SAMR30
+	PM->STDBYCFG.reg = PM_STDBYCFG_PDCFG(config->power_domain)
+					 | (config->enable_dpgpd0 << PM_STDBYCFG_DPGPD0_Pos)
+					 | (config->enable_dpgpd1 << PM_STDBYCFG_DPGPD1_Pos)
+#if (SAML21XXXB) || (SAMR30)
+					 | PM_STDBYCFG_VREGSMOD(config->vregs_mode)
+#else
+					 | (config->disable_avregsd << PM_STDBYCFG_AVREGSD_Pos)
+#endif
+					 | PM_STDBYCFG_LINKPD(config->linked_power_domain)
+					 | PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias)
+					 | PM_STDBYCFG_BBIASLP(config->hmcramclp_back_bias);
+#elif SAML22
+	PM->STDBYCFG.reg = PM_STDBYCFG_VREGSMOD(config->vreg_switch_mode) |
+					 PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias);
+#endif
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name I/O Retention
+ * @{
+ */
+
+/**
+ * \brief Enable I/O retention.
+ *
+ *  Enable I/O retention. After waking up from Backup mode, I/O lines are held
+ *  until the bit is written to 0.
+ */
+static inline void system_io_retension_enable(void)
+{
+	PM->CTRLA.reg = PM_CTRLA_IORET;
+}
+
+/**
+ * \brief Disable I/O retention.
+ *
+ * Disable IO retention. After waking up from Backup mode, I/O lines are not held.
+ */
+static inline void system_io_retension_disable(void)
+{
+	PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* POWER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_c/reset.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_c/reset.h
new file mode 100644
index 0000000000..647296be24
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_c/reset.h
@@ -0,0 +1,117 @@
+/**
+ * \file
+ *
+ * \brief SAM C2x Reset functionality
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef RESET_H_INCLUDED
+#define RESET_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Reset causes of the system.
+ *
+ * List of possible reset causes of the system.
+ */
+enum system_reset_cause {
+	/** The system was last reset by a software reset */
+	SYSTEM_RESET_CAUSE_SOFTWARE       = RSTC_RCAUSE_SYST,
+	/** The system was last reset by the watchdog timer */
+	SYSTEM_RESET_CAUSE_WDT            = RSTC_RCAUSE_WDT,
+	/** The system was last reset because the external reset 
+		line was pulled low */
+	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT,
+	/** The system was last reset by VDD brown out detector */
+	SYSTEM_RESET_CAUSE_BODVDD         = RSTC_RCAUSE_BODVDD,
+	/** The system was last reset by VDDCORE brown out detector */
+	SYSTEM_RESET_CAUSE_BODCORE        = RSTC_RCAUSE_BODCORE,
+	/** The system was last reset by the POR (Power on reset) */
+	SYSTEM_RESET_CAUSE_POR            = RSTC_RCAUSE_POR,
+};
+
+/**
+ * \name Reset Control
+ * @{
+ */
+
+/**
+ * \brief Reset the MCU.
+ *
+ * Resets the MCU and all associated peripherals and registers, except RTC,
+ * OSC32KCTRL, RSTC, GCLK(if WRTLOCK is set) and I/O retention state of PM.
+ *
+ */
+static inline void system_reset(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Get the reset cause.
+ *
+ * Retrieves the cause of the last system reset.
+ *
+ * \return An enum value indicating the cause of the last system reset.
+ */
+static inline enum system_reset_cause system_get_reset_cause(void)
+{
+	return (enum system_reset_cause)RSTC->RCAUSE.reg;
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RESET_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
new file mode 100644
index 0000000000..33ccd5030e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
@@ -0,0 +1,119 @@
+/**
+ * \file
+ *
+ * \brief SAM Reset related functionality
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef RESET_H_INCLUDED
+#define RESET_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Reset causes of the system.
+ *
+ * List of possible reset causes of the system.
+ */
+enum system_reset_cause {
+	/** The system was last reset by a software reset */
+	SYSTEM_RESET_CAUSE_SOFTWARE       = PM_RCAUSE_SYST,
+	/** The system was last reset by the watchdog timer */
+	SYSTEM_RESET_CAUSE_WDT            = PM_RCAUSE_WDT,
+	/** The system was last reset because the external reset line was pulled low */
+	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
+	/** The system was last reset by the BOD33 */
+	SYSTEM_RESET_CAUSE_BOD33          = PM_RCAUSE_BOD33,
+	/** The system was last reset by the BOD12 */
+	SYSTEM_RESET_CAUSE_BOD12          = PM_RCAUSE_BOD12,
+	/** The system was last reset by the POR (Power on reset) */
+	SYSTEM_RESET_CAUSE_POR            = PM_RCAUSE_POR,
+};
+
+
+/**
+ * \name Reset Control
+ * @{
+ */
+
+/**
+ * \brief Reset the MCU.
+ *
+ * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources,
+ * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
+ *
+ */
+static inline void system_reset(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Return the reset cause.
+ *
+ * Retrieves the cause of the last system reset.
+ *
+ * \return An enum value indicating the cause of the last system reset.
+ */
+static inline enum system_reset_cause system_get_reset_cause(void)
+{
+	return (enum system_reset_cause)PM->RCAUSE.reg;
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RESET_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_l/reset.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_l/reset.h
new file mode 100644
index 0000000000..7b5cd29611
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_l/reset.h
@@ -0,0 +1,265 @@
+/**
+ * \file
+ *
+ * \brief SAM Reset functionality
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef RESET_H_INCLUDED
+#define RESET_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Reset causes of the system.
+ *
+ * List of possible reset causes of the system.
+ */
+enum system_reset_cause {
+	/** The system was last reset by a backup reset */
+	SYSTEM_RESET_CAUSE_BACKUP         = RSTC_RCAUSE_BACKUP,
+	/** The system was last reset by a software reset */
+	SYSTEM_RESET_CAUSE_SOFTWARE       = RSTC_RCAUSE_SYST,
+	/** The system was last reset by the watchdog timer */
+	SYSTEM_RESET_CAUSE_WDT            = RSTC_RCAUSE_WDT,
+	/** The system was last reset because the external reset line was pulled low */
+	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT,
+#if SAML21 || SAMR30
+	/** The system was last reset by the BOD33. */
+	SYSTEM_RESET_CAUSE_BOD33          = RSTC_RCAUSE_BOD33,
+	/** The system was last reset by the BOD12 */
+	SYSTEM_RESET_CAUSE_BOD12          = RSTC_RCAUSE_BOD12,
+#else
+	/** The system was last reset by the BOD VDD. */
+	SYSTEM_RESET_CAUSE_BOD33          = RSTC_RCAUSE_BODVDD,
+	/** The system was last reset by the BOD CORE. */
+	SYSTEM_RESET_CAUSE_BOD12          = RSTC_RCAUSE_BODCORE,
+#endif
+	/** The system was last reset by the POR (Power on reset). */
+	SYSTEM_RESET_CAUSE_POR            = RSTC_RCAUSE_POR,
+};
+
+/**
+ * \brief Backup exit source after a backup reset occurs.
+ *
+ * List of possible backup exit source.
+ */
+enum system_reset_backup_exit_source {
+#if SAML21 || SAMR30
+	/** The backup exit source was external wakeup. */
+	SYSTEM_RESET_BACKKUP_EXIT_EXTWAKE    = RSTC_BKUPEXIT_EXTWAKE,
+#endif
+	/** The backup exit source was RTC interrupt. */
+	SYSTEM_RESET_BACKKUP_EXIT_RTC        = RSTC_BKUPEXIT_RTC,
+	/** The backup exit source was battery backup power switch */
+	SYSTEM_RESET_BACKKUP_EXIT_BBPS       = RSTC_BKUPEXIT_BBPS,
+};
+
+#if SAML21 || SAMR30
+/**
+ * \brief Wakeup debounce counter value.
+ *
+ * Wakeup debounce counter value when waking up by external wakeup pin from backup mode.
+ */
+enum system_wakeup_debounce_count {
+	/** No debouncing */
+	SYSTEM_WAKEUP_DEBOUNCE_OFF         = RSTC_WKDBCONF_WKDBCNT_OFF,
+	/** Input pin shall be active for at least two 32KHz clock period. */
+	SYSTEM_WAKEUP_DEBOUNCE_2CK32       = RSTC_WKDBCONF_WKDBCNT_2CK32,
+	/** Input pin shall be active for at least three 32KHz clock period. */
+	SYSTEM_WAKEUP_DEBOUNCE_3CK32       = RSTC_WKDBCONF_WKDBCNT_3CK32,
+	/** Input pin shall be active for at least 32 32KHz clock periods */
+	SYSTEM_WAKEUP_DEBOUNCE_32CK32      = RSTC_WKDBCONF_WKDBCNT_32CK32,
+	/** Input pin shall be active for at least 512 32KHz clock periods */
+	SYSTEM_WAKEUP_DEBOUNCE_512CK32     = RSTC_WKDBCONF_WKDBCNT_512CK32,
+	/** Input pin shall be active for at least 4096 32KHz clock periods */
+	SYSTEM_WAKEUP_DEBOUNCE_4096CK32    = RSTC_WKDBCONF_WKDBCNT_4096CK32,
+	/** Input pin shall be active for at least 32768 32KHz clock periods */
+	SYSTEM_WAKEUP_DEBOUNCE_32768CK32   = RSTC_WKDBCONF_WKDBCNT_32768CK32,
+};
+#endif
+
+/**
+ * \name Reset Control
+ * @{
+ */
+
+/**
+ * \brief Reset the MCU.
+ *
+ * Resets the MCU and all associated peripherals and registers, except RTC,
+ * OSC32KCTRL, RSTC, GCLK (if WRTLOCK is set), and I/O retention state of PM.
+ *
+ */
+static inline void system_reset(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Get the reset cause.
+ *
+ * Retrieves the cause of the last system reset.
+ *
+ * \return An enum value indicating the cause of the last system reset.
+ */
+static inline enum system_reset_cause system_get_reset_cause(void)
+{
+	return (enum system_reset_cause)RSTC->RCAUSE.reg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Backup Exit Control
+ * @{
+ */
+
+/**
+ * \brief Get the backup exit source.
+ *
+ * Get the backup exit source when a backup reset occurs.
+ *
+ * \return An enum value indicating the latest backup exit source.
+ */
+static inline enum system_reset_backup_exit_source system_get_backup_exit_source(void)
+{
+	return (enum system_reset_backup_exit_source)RSTC->BKUPEXIT.reg;
+}
+
+#if SAML21 || SAMR30
+/**
+ * \brief Set wakeup debounce counter.
+ *
+ * Set the wakeup debounce counter value with the given count.
+ *
+ * \param[in] wakeup_debounce_count Wakeup debounce counter value
+ */
+static inline void system_set_pin_wakeup_debounce_counter(
+					const enum system_wakeup_debounce_count wakeup_debounce_count)
+{
+	RSTC->WKDBCONF.reg = wakeup_debounce_count;
+}
+
+/**
+ * \brief Set low polarity of wakeup input pin.
+ *
+ * Set low polarity with the given wakeup input pin mask.
+ *
+ * \param[in] pin_mask Input pin mask
+ */
+static inline void system_set_pin_wakeup_polarity_low(const uint16_t pin_mask)
+{
+	RSTC->WKPOL.reg &= ~(RSTC_WKPOL_WKPOL(pin_mask));
+}
+
+/**
+ * \brief Set high polarity of wakeup input pin.
+ *
+ * Set high polarity with the given wakeup input pin mask.
+ *
+ * \param[in] pin_mask Input pin mask
+ */
+static inline void system_set_pin_wakeup_polarity_high(const uint16_t pin_mask)
+{
+	RSTC->WKPOL.reg |= RSTC_WKPOL_WKPOL(pin_mask);
+}
+
+/**
+ * \brief Enable wakeup of input pin from the backup mode.
+ *
+ * Enable pin wakeup from the backup mode with the given pin mask.
+ *
+ * \param[in] pin Input pin mask
+ */
+static inline void system_enable_pin_wakeup(const uint16_t pin_mask)
+{
+	RSTC->WKEN.reg |= RSTC_WKEN_WKEN(pin_mask);
+}
+
+/**
+ * \brief Disable wakeup of input pin from the backup mode.
+ *
+ * Disable pin wakeup from the backup mode with the given pin mask.
+ *
+ * \param[in] pin Input pin mask
+ */
+static inline void system_disable_pin_wakeup(const uint16_t pin_mask)
+{
+	RSTC->WKEN.reg &= ~(RSTC_WKEN_WKEN(pin_mask));
+}
+
+/**
+ * \brief Check whether any of the enabled wake up pins are active and caused the wakeup.
+ *
+ * Check whether any of the enabled wake up pins are active and caused the wakeup
+ *  from backup sleep mode when exiting backup mode.
+ *
+ * \return Pin mask, the corresponding pin is active when its pin mask is 1.
+ */
+static inline uint16_t system_get_pin_wakeup_cause(void)
+{
+	return (RSTC_WKCAUSE_MASK & (RSTC->WKCAUSE.reg >> RSTC_WKCAUSE_WKCAUSE_Pos));
+}
+#endif
+/**
+ * @}
+ */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RESET_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.c
new file mode 100644
index 0000000000..feab5f3402
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.c
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <system.h>
+
+/**
+ * \internal
+ * Dummy initialization function, used as a weak alias target for the various
+ * init functions called by \ref system_init().
+ */
+void _system_dummy_init(void);
+void _system_dummy_init(void)
+{
+	return;
+}
+
+#if !defined(__DOXYGEN__)
+#  if defined(__GNUC__) || defined(__CC_ARM)
+void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_divas_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+#  elif defined(__ICCARM__)
+void system_clock_init(void);
+void system_board_init(void);
+void _system_events_init(void);
+void _system_extint_init(void);
+void _system_divas_init(void);
+#    pragma weak system_clock_init=_system_dummy_init
+#    pragma weak system_board_init=_system_dummy_init
+#    pragma weak _system_events_init=_system_dummy_init
+#    pragma weak _system_extint_init=_system_dummy_init
+#    pragma weak _system_divas_init=_system_dummy_init
+#  endif
+#endif
+
+/**
+ * \brief Initialize system
+ *
+ * This function will call the various initialization functions within the
+ * system namespace. If a given optional system module is not available, the
+ * associated call will effectively be a NOP (No Operation).
+ *
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization (via the SYSTEM CLOCK sub-module)
+ *  - Board hardware initialization (via the Board module)
+ *  - Event system driver initialization (via the EVSYS module)
+ *  - External Interrupt driver initialization (via the EXTINT module)
+ */
+void system_init(void)
+{
+	/* Configure GCLK and clock sources according to conf_clocks.h */
+	system_clock_init();
+
+	/* Initialize board hardware */
+	system_board_init();
+
+	/* Initialize EVSYS hardware */
+	_system_events_init();
+
+	/* Initialize External hardware */
+	_system_extint_init();
+
+	/* Initialize DIVAS hardware */
+	_system_divas_init();
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.h
new file mode 100644
index 0000000000..c6dd6e8562
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.h
@@ -0,0 +1,728 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_H_INCLUDED
+#define SYSTEM_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+#include <power.h>
+#include <reset.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_group SAM System (SYSTEM) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's system relation functionality, necessary for
+ * the basic device operation. This is not limited to a single peripheral, but
+ * extends across multiple hardware peripherals.
+ *
+ * The following peripherals are used by this module:
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  - PM (Power Manager)
+ *  - RSTC (Reset Controller)
+ *  - SUPC (Supply Controller)
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  - PM (Power Manager)
+ *  - RSTC (Reset Controller)
+ *  - SUPC (Supply Controller)
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  - SYSCTRL (System Control)
+ *  - PM (Power Manager)
+ * \endif
+ *
+ * The following devices can use this module:
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM L21
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM C20/C21
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM DA1
+ * \endif
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_prerequisites
+ *  - \ref asfdoc_sam0_system_module_overview
+ *  - \ref asfdoc_sam0_system_special_considerations
+ *  - \ref asfdoc_sam0_system_extra_info
+ *  - \ref asfdoc_sam0_system_examples
+ *  - \ref asfdoc_sam0_system_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_module_overview Module Overview
+ *
+ * The System driver provides a collection of interfaces between the user
+ * application logic, and the core device functionality (such as clocks, reset
+ * cause determination, etc.) that is required for all applications. It contains
+ * a number of sub-modules that control one specific aspect of the device:
+ *
+ * - System Core (this module)
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
+ * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
+ *
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg_l21 Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE) and
+ * backup (VDDBU) domains. It sets the voltage regulators according to the sleep
+ * modes, the performance level, or the user configuration.
+ *
+ * In active mode, the voltage regulator can be chosen on the fly between a LDO
+ * or a Buck converter. In standby mode, the low power voltage regulator is used
+ * to supply VDDCORE.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch
+ * The SAM device supports connection of a battery backup to the VBAT power pin.
+ * It includes functionality that enables automatic power switching between main
+ * power and battery backup power. This will ensure power to the backup domain,
+ * when the main battery or power source is unavailable.
+ * \endif
+ *
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg_c21 Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE). It sets
+ * the voltage regulators according to the sleep modes.
+ *
+ * There are a selectable reference voltage and voltage dependent on the temperature
+ * which can be used by analog modules like the ADC.
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_vref Voltage References
+ * The various analog modules within the SAM devices (such as AC, ADC, and
+ * DAC) require a voltage reference to be configured to act as a reference point
+ * for comparisons and conversions.
+ *
+ * The SAM devices contain multiple references, including an internal
+ * temperature sensor and a fixed band-gap voltage source. When enabled, the
+ * associated voltage reference can be selected within the desired peripheral
+ * where applicable.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
+ * In some applications there may be a need to execute a different program
+ * flow based on how the device was reset. For example, if the cause of reset
+ * was the Watchdog timer (WDT), this might indicate an error in the application,
+ * and a form of error handling or error logging might be needed.
+ *
+ * For this reason, an API is provided to retrieve the cause of the last system
+ * reset, so that appropriate action can be taken.
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * There are three groups of reset sources:
+ *   - Power supply reset: Resets caused by an electrical issue. It covers POR and BOD reset.
+ *   - User reset: Resets caused by the application. It covers external reset,
+ *             system reset, and watchdog reset.
+ *   - Backup reset: Resets caused by a backup mode exit condition.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level
+ * Performance level allows the user to adjust the regulator output voltage to reduce
+ * power consumption. The user can on the fly select the most suitable performance
+ * level, depending on the application demands.
+ *
+ * The SAM device can operate at two different performance levels (PL0 and PL2).
+ * When operating at PL0, the voltage applied on the full logic area is reduced
+ * by voltage scaling. This voltage scaling technique allows to reduce the active
+ * power consumption while decreasing the maximum frequency of the device. When
+ * operating at PL2, the voltage regulator supplies the highest voltage, allowing
+ * the device to run at higher clock speeds.
+ *
+ * Performance level transition is possible only when the device is in active
+ * mode. After a reset, the device starts at the lowest performance level
+ * (lowest power consumption and lowest max. frequency). The application can then
+ * switch to another performance level at any time without any stop in the code
+ * execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure.
+ *
+ * \note When scaling down the performance level, the bus frequency should first be
+ *  scaled down in order to not exceed the maximum frequency allowed for the
+ *  low performance level.
+ *  When scaling up the performance level (e.g. from PL0 to PL2), check the performance
+ *  level status before increasing the bus frequency. It can be increased only
+ *  when the performance level transition is completed.
+ *
+ * \anchor asfdoc_sam0_system_performance_level_transition_figure
+ * \image html performance_level_transition.svg "Performance Level Transition"
+ *
+ * \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating
+ * Power domain gating allows power saving by reducing the voltage in logic
+ * areas in the device to a low-power supply. The feature is available in
+ * Standby sleep mode and will reduce the voltage in domains where all peripherals
+ * are idle. Internal logic will maintain its content, meaning the corresponding
+ * peripherals will not need to be reconfigured when normal operating voltage
+ * is returned. Most power domains can be in the following three states:
+ *
+ * - Active state: The power domain is powered on.
+ * - Retention state: The main voltage supply for the power domain is switched off,
+ * while maintaining a secondary low-power supply for the sequential cells. The
+ * logic context is restored when waking up.
+ * - Off state: The power domain is entirely powered off. The logic context is lost.
+ *
+ * The SAM L21 device  contains three power domains which can be controlled using
+ * power domain gating, namely PD0, PD1, and PD2. These power domains can be
+ * configured to the following cases:
+ * - Default with no sleepwalking peripherals: A power domain is automatically set
+ * to retention state in standby sleep mode if no activity require it. The application
+ * can force all power domains to remain in active state during standby sleep mode
+ * in order to accelerate wakeup time.
+ * - Default with sleepwalking peripherals: If one or more peripherals are enabled
+ * to perform sleepwalking tasks in standby sleep mode, the corresponding power
+ * domain (PDn) remains in active state as well as all inferior power domains (<PDn).
+ * - Sleepwalking with dynamic power domain gating: During standby sleep mode, a
+ * power domain (PDn) in active can wake up a superior power domain (>PDn) in order
+ * to perform a sleepwalking task. The superior power domain is then automatically
+ * set to active state. At the end of the sleepwalking task, the device can either
+ * be woken up or the superior power domain can return to retention state.
+ *
+ * Power domains can be linked to each other, it allows a power domain (PDn) to be kept
+ * in active state if the inferior power domain (PDn-1) is in active state too.
+ *
+ * \ref asfdoc_sam0_system_power_domain_overview_table illustrates the
+ * four cases to consider in standby mode.
+ *
+ * \anchor asfdoc_sam0_system_power_domain_overview_table
+ * <table>
+ *  <caption>Sleep Mode versus Power Domain State Overview</caption>
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>PD0</th>
+ *      <th>PD1</th>
+ *      <th>PD2</th>
+ *      <th>PDTOP</th>
+ *      <th>PDBACKUP</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 1</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 2</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 3</td>
+ *      <td>active</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 4</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Backup</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode
+ * By default, in standby sleep mode, RAM is in low power mode (back biased)
+ * if its power domain is in retention state.
+ * \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode.
+ *
+ * \anchor asfdoc_sam0_system_power_ram_state_table
+ * <table>
+ *  <caption>RAM Back-biasing Mode</caption>
+ *  <tr>
+ *      <th>RAM mode</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Retention Back-biasing mode</td>
+ *      <td>RAM is back-biased if its power domain is in retention mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby Back-biasing mode</td>
+ *      <td>RAM is back-biased if the device is in standby mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby OFF mode</td>
+ *      <td>RAM is OFF if the device is in standby mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Always OFF mode</td>
+ *      <td>RAM is OFF if the device is in RET mode</td>
+ *  </tr>
+ * </table>
+ *
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
+ * The SAM devices have several sleep modes. The sleep mode controls
+ * which clock systems on the device will remain enabled or disabled when the
+ * device enters a low power sleep mode.
+ * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
+ * clock settings of the different sleep modes.
+ *
+ * \anchor asfdoc_sam0_system_module_sleep_mode_table
+ * <table>
+ *  <caption>SAM Device Sleep Modes</caption>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>System clock</th>
+ *      <th>CPU clock</th>
+ *      <th>AHB/AHB clock</th>
+ *      <th>GCLK clocks</th>
+ *      <th>Oscillators (ONDEMAND  = 0)</th>
+ *      <th>Oscillators (ONDEMAND  = 1)</th>
+ *      <th>Regulator mode</th>
+ *      <th>RAM mode</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle</td>
+ *      <td>Run</td>
+ *      <td>Stop</td>
+ *      <td>Run if requested</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run if requested</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run if requested</td>
+ *      <td>Run if requested</td>
+ *      <td>Run if requested or RUNSTDBY  = 1</td>
+ *      <td>Run if requested</td>
+ *      <td>Low pwer</td>
+ *      <td>Low pwer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Backup</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Backup</td>
+ *      <td>Off</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *  </tr>
+ * \else
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>CPU clock</th>
+ *      <th>AHB clock</th>
+ *      <th>APB clocks</th>
+ *      <th>Clock sources</th>
+ *      <th>System clock</th>
+ *      <th>32KHz</th>
+ *      <th>Reg mode</th>
+ *      <th>RAM mode</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 0</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 1</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 2</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Low Power</td>
+ *      <td>Source/Drain biasing</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ * Before entering device sleep, one of the available sleep modes must be set.
+ * The device will automatically wake up in response to an interrupt being
+ * generated or upon any other sleep mode exit condition.
+ *
+ * Some peripheral clocks will remain enabled during sleep, depending on their
+ * configuration. If desired, the modules can remain clocked during sleep to allow
+ * them continue to operate while other parts of the system are powered down
+ * to save power.
+ *
+ *
+ * \section asfdoc_sam0_system_special_considerations Special Considerations
+ *
+ * Most of the functions in this driver have device specific restrictions and
+ * caveats; refer to your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_extra. This includes:
+ *  - \ref asfdoc_sam0_system_extra_acronyms
+ *  - \ref asfdoc_sam0_system_extra_dependencies
+ *  - \ref asfdoc_sam0_system_extra_errata
+ *  - \ref asfdoc_sam0_system_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_examples Examples
+ *
+ * For SYSTEM module related examples, refer to the sub-modules listed in
+ * the \ref asfdoc_sam0_system_module_overview "Module Overview".
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_drivers_power_exqsg.
+ * \endif
+ *
+ *
+ * \section asfdoc_sam0_system_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \name System Debugger
+ * @{
+ */
+
+/**
+ * \brief Check if debugger is present.
+ *
+ * Check if debugger is connected to the onboard debug system (DAP).
+ *
+ * \return A bool identifying if a debugger is present.
+ *
+ * \retval true  Debugger is connected to the system
+ * \retval false Debugger is not connected to the system
+ *
+ */
+static inline bool system_is_debugger_present(void)
+{
+	return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Identification
+ * @{
+ */
+
+/**
+ * \brief Retrieve the device identification signature.
+ *
+ * Retrieves the signature of the current device.
+ *
+ * \return Device ID signature as a 32-bit integer.
+ */
+static inline uint32_t system_get_device_id(void)
+{
+	return DSU->DID.reg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Initialization
+ * @{
+ */
+
+void system_init(void);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * \page asfdoc_sam0_drivers_power_exqsg Examples for SYSTEM Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_group. QSGs are simple examples with step-by-step instructions to
+ * configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_power_basic_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
+ *
+ * \section asfdoc_sam0_system_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>PM</td>
+ *      <td>Power Manager</td>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SUPC</td>
+ *      <td>Supply Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RSTC</td>
+ *      <td>Reset Controller</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SUPC</td>
+ *      <td>Supply Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RSTC</td>
+ *      <td>Reset Controller</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SYSCTRL</td>
+ *      <td>System control interface</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added new \c system_get_device_id() function to retrieved the device
+ *          ID</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ * \page asfdoc_sam0_system_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42449A</td>
+ *      <td>07/2015</td>
+ *      <td>Initial document release</td>
+ * </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42484A</td>
+ *      <td>12/2015</td>
+ *      <td>Initial document release.</td>
+ * </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42120E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM DA1 and SAM D09</td>
+ * </tr>
+ *  <tr>
+ *      <td>42120D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ * </tr>
+ * <tr>
+ *      <td>42120C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42120B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42120A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.c
new file mode 100644
index 0000000000..ea609da2c0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.c
@@ -0,0 +1,1523 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "system_sam_b.h"
+
+uint32_t system_clock_value;
+
+/**
+ * \brief System clock config
+ *
+ * Use this function to config system clock.
+ *
+ * \param[in]  resoure    Selection system clock resource
+ * \param[in]  freq       Selection clock frequency
+ *
+ * \return Status of operation.
+ * \retval STATUS_OK               Clock config correctly
+ * \retval STATUS_ERR_INVALID_ARG  If data is invalid
+ */
+enum status_code system_clock_config(enum system_clock_resource resoure, \
+				enum system_clock_freq freq)
+{
+	switch (resoure) {
+		case CLOCK_RESOURCE_XO_26_MHZ:
+			LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+					LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK | \
+					LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK;
+			system_clock_value = 26000000;
+			break;
+
+		case CLOCK_RESOURCE_LP_2_MHZ:
+			LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+					LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK;
+			LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+					~LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK;
+			AON_GP_REGS0->AON_PMU_CTRL.reg |= \
+					AON_GP_REGS_AON_PMU_CTRL_PMU_2MHZ_CLK_EN;
+			system_clock_value = 2000000;
+			break;
+
+		case CLOCK_RESOURCE_RC_26_MHZ:
+			LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+					~(LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK | \
+					LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK);
+			system_clock_value = 26000000;
+			break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+		~LPMCU_MISC_REGS_LPMCU_CTRL_LPMCU_CLK_SEL_Msk;
+	LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+		LPMCU_MISC_REGS_LPMCU_CTRL_LPMCU_CLK_SEL(freq);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the system clock value
+ *
+ * Use this function to get system clock value.
+ *
+ * \return system clock value.
+ */
+uint32_t system_clock_get_value(void)
+{
+	return system_clock_value;
+}
+
+/**
+ * \brief System clock peripheral enable
+ *
+ * Use this function to enable system clock peripheral.
+ *
+ * \param[in]  peripheral    Selection peripheral
+ *
+ * \return Status of operation.
+ * \retval STATUS_OK               Clock config correctly
+ * \retval STATUS_ERR_INVALID_ARG  If data is invalid
+ */
+enum status_code system_clock_peripheral_enable(enum system_peripheral peripheral)
+{
+	switch (peripheral) {
+		case PERIPHERAL_SPI_FLASH:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI_FLASH0_CLK_EN;
+		break;
+
+		case PERIPHERAL_SPI0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI0_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_SPI1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI1_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_I2C0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C0_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_DUALT_TIMER:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
+		break;
+
+		case PERIPHERAL_GPIO_CLK:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_GPIO_CLK_EN;
+		break;
+
+		case PERIPHERAL_TIMER:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_TIMER0_CLK_EN;
+		break;
+
+		case PERIPHERAL_WDT0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT0_CLK_EN;
+		break;
+
+		case PERIPHERAL_WDT1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT1_CLK_EN;
+		break;
+
+		case PERIPHERAL_UART0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_UART0_IF:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_IF_CLK_EN;
+		break;
+
+		case PERIPHERAL_UART1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_UART1_IF:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_IF_CLK_EN;
+		break;
+
+		case PERIPHERAL_NVIC:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IRQ_CTRLR_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_1_GL_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_2_GL_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_ROM:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ROM_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_LOW_POWER_IF:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_XBAR_IF_CLK_EN;
+		break;
+
+		case PERIPHERAL_AON_WRAPPER:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_AON_WRAPPER_CLK_EN;
+		break;
+
+		case PERIPHERAL_ARM_PCLK:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLK_EN;
+		break;
+
+		case PERIPHERAL_ARM_GATED_PCLK:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLKG_EN;
+		break;
+
+		case PERIPHERAL_ARM_BLE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_BLE_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_QDEC0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
+		break;
+
+		case PERIPHERAL_QDEC1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
+		break;
+
+		case PERIPHERAL_QDEC2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
+		break;
+
+		case PERIPHERAL_I2C1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C1_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_LOW_POWER_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE0_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE1_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE3:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE2_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE4:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE3_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE5:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE4_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE6:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE5_CLK_EN;
+		break;
+
+		case PERIPHERAL_PWM0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM0_CLK_EN;
+		break;
+
+		case PERIPHERAL_PWM1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM1_CLK_EN;
+		break;
+
+		case PERIPHERAL_PWM2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM2_CLK_EN;
+		break;
+
+		case PERIPHERAL_PWM3:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM3_CLK_EN;
+		break;
+
+		case PERIPHERAL_ADC:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SENS_ADC_CLK_EN;
+		break;
+
+		case PERIPHERAL_SPI0_SCK_PHASE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI0_SCK_PHASE_INT_CLK_EN;
+		break;
+
+		case PERIPHERAL_SPI1_SCK_PHASE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI1_SCK_PHASE_INT_CLK_EN;
+		break;
+
+		case PERIPHERAL_GPIO_GCLK:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_GPIO_GCLK_EN;
+		break;
+
+		case PERIPHERAL_TIMER0_GATE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_TIMER0_PGCLK_EN;
+		break;
+
+		case PERIPHERAL_SHA_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_SHA_AHB:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_AHB_CLK_EN;
+		break;
+
+		case PERIPHERAL_AES_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_AES_AHB:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_AHB_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM1_0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_0_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM1_1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_1_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM1_2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_2_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM2_0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_0_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM2_1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_1_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_BLE_RXTX:
+			LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
+				LPMCU_MISC_REGS_BTMCU_CTRL_RXTX_SEQ_CLK_EN;
+		break;
+
+		case PERIPHERAL_BLE_AHB:
+			LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
+				LPMCU_MISC_REGS_BTMCU_CTRL_AHB_CLK_EN;
+		break;
+
+		case PERIPHERAL_BLE_PERIPH_REGS:
+			LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
+				LPMCU_MISC_REGS_BTMCU_CTRL_PERIPH_REGS_CLK_EN;
+		break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief System clock peripheral disable
+ *
+ * Use this function to disable system clock peripheral.
+ *
+ * \param[in]  peripheral    Selection peripheral
+ *
+ * \return Status of operation.
+ * \retval STATUS_OK               Clock config correctly
+ * \retval STATUS_ERR_INVALID_ARG  If data is invalid
+ */
+enum status_code system_clock_peripheral_disable(enum system_peripheral peripheral)
+{
+	switch (peripheral) {
+		case PERIPHERAL_SPI_FLASH:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI_FLASH0_CLK_EN;
+		break;
+
+		case PERIPHERAL_SPI0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI0_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_SPI1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI1_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_I2C0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C0_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_DUALT_TIMER:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
+		break;
+
+		case PERIPHERAL_GPIO_CLK:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_GPIO_CLK_EN;
+		break;
+
+		case PERIPHERAL_TIMER:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_TIMER0_CLK_EN;
+		break;
+
+		case PERIPHERAL_WDT0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT0_CLK_EN;
+		break;
+
+		case PERIPHERAL_WDT1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT1_CLK_EN;
+		break;
+
+		case PERIPHERAL_UART0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_UART0_IF:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_IF_CLK_EN;
+		break;
+
+		case PERIPHERAL_UART1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_UART1_IF:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_IF_CLK_EN;
+		break;
+
+		case PERIPHERAL_NVIC:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IRQ_CTRLR_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_1_GL_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_2_GL_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_ROM:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ROM_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_LOW_POWER_IF:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_XBAR_IF_CLK_EN;
+		break;
+
+		case PERIPHERAL_AON_WRAPPER:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_AON_WRAPPER_CLK_EN;
+		break;
+
+		case PERIPHERAL_ARM_PCLK:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLK_EN;
+		break;
+
+		case PERIPHERAL_ARM_GATED_PCLK:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLKG_EN;
+		break;
+
+		case PERIPHERAL_ARM_BLE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_BLE_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_QDEC0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
+		break;
+
+		case PERIPHERAL_QDEC1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
+		break;
+
+		case PERIPHERAL_QDEC2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
+		break;
+
+		case PERIPHERAL_I2C1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C1_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_LOW_POWER_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE0_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE1_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE3:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE2_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE4:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE3_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE5:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE4_CLK_EN;
+		break;
+
+		case PERIPHERAL_EFUSE6:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE5_CLK_EN;
+		break;
+
+		case PERIPHERAL_PWM0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM0_CLK_EN;
+		break;
+
+		case PERIPHERAL_PWM1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM1_CLK_EN;
+		break;
+
+		case PERIPHERAL_PWM2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM2_CLK_EN;
+		break;
+
+		case PERIPHERAL_PWM3:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM3_CLK_EN;
+		break;
+
+		case PERIPHERAL_ADC:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SENS_ADC_CLK_EN;
+		break;
+
+		case PERIPHERAL_SPI0_SCK_PHASE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI0_SCK_PHASE_INT_CLK_EN;
+		break;
+
+		case PERIPHERAL_SPI1_SCK_PHASE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI1_SCK_PHASE_INT_CLK_EN;
+		break;
+
+		case PERIPHERAL_GPIO_GCLK:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_GPIO_GCLK_EN;
+		break;
+
+		case PERIPHERAL_TIMER0_GATE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_TIMER0_PGCLK_EN;
+		break;
+
+		case PERIPHERAL_SHA_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_SHA_AHB:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_AHB_CLK_EN;
+		break;
+
+		case PERIPHERAL_AES_CORE:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_CORE_CLK_EN;
+		break;
+
+		case PERIPHERAL_AES_AHB:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_AHB_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM1_0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_0_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM1_1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_1_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM1_2:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_2_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM2_0:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_0_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_IDRAM2_1:
+			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_1_MEM_CLK_EN;
+		break;
+
+		case PERIPHERAL_BLE_RXTX:
+			LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
+				~LPMCU_MISC_REGS_BTMCU_CTRL_RXTX_SEQ_CLK_EN;
+		break;
+
+		case PERIPHERAL_BLE_AHB:
+			LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
+				~LPMCU_MISC_REGS_BTMCU_CTRL_AHB_CLK_EN;
+		break;
+
+		case PERIPHERAL_BLE_PERIPH_REGS:
+			LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
+				~LPMCU_MISC_REGS_BTMCU_CTRL_PERIPH_REGS_CLK_EN;
+		break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief System clock peripheral frequency config
+ *
+ * Use this function to config system clock peripheral frequency.
+ *
+ * \param[in]  peripheral    Selection peripheral
+ * \param[in]  freq          Selection clock frequency
+ *
+ * \return Status of operation.
+ * \retval STATUS_OK               Clock config correctly
+ * \retval STATUS_ERR_INVALID_ARG  If data is invalid
+ */
+enum status_code system_clock_peripheral_freq_config( \
+		enum system_peripheral peripheral, \
+		enum system_clock_freq freq)
+{
+	switch (peripheral) {
+		case PERIPHERAL_SPI_FLASH:
+			LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+					~LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_Msk;
+			switch (freq) {
+				case CLOCK_FREQ_26_MHZ:
+					LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+						LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_3;
+					break;
+				case CLOCK_FREQ_13_MHZ:
+					LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+						LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_2;
+					break;
+				case CLOCK_FREQ_6_5_MHZ:
+					LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+						LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_1;
+				break;
+				case CLOCK_FREQ_3_25_MHZ:
+					LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+						LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_0;
+				break;
+			}
+			break;
+
+		case PERIPHERAL_DUALT_TIMER:
+			LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_CTRL_DUALTIMER0_CLK_SEL_Msk;
+			LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+				LPMCU_MISC_REGS_LPMCU_CTRL_DUALTIMER0_CLK_SEL(freq);
+			break;
+
+		case PERIPHERAL_PWM0:
+			LPMCU_MISC_REGS0->PWM0_CTRL.reg &= \
+				~LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL_Msk;
+			LPMCU_MISC_REGS0->PWM0_CTRL.reg |= \
+				LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL(freq);
+			break;
+
+		case PERIPHERAL_PWM1:
+			LPMCU_MISC_REGS0->PWM1_CTRL.reg &= \
+				~LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL_Msk;
+			LPMCU_MISC_REGS0->PWM1_CTRL.reg |= \
+				LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL(freq);
+			break;
+
+		case PERIPHERAL_PWM2:
+			LPMCU_MISC_REGS0->PWM2_CTRL.reg &= \
+				~LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL_Msk;
+			LPMCU_MISC_REGS0->PWM2_CTRL.reg |= \
+				LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL(freq);
+			break;
+
+		case PERIPHERAL_PWM3:
+			LPMCU_MISC_REGS0->PWM3_CTRL.reg &= \
+				~LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL_Msk;
+			LPMCU_MISC_REGS0->PWM3_CTRL.reg |= \
+				LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL(freq);
+			break;
+
+		case PERIPHERAL_QDEC0:
+			LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg &= \
+				~LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLOCK_SEL_Msk;
+			LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |= \
+				LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLOCK_SEL(freq);
+			break;
+
+		case PERIPHERAL_QDEC1:
+			LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg &= \
+				~LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLOCK_SEL_Msk;
+			LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |= \
+				LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLOCK_SEL(freq);
+			break;
+
+		case PERIPHERAL_QDEC2:
+			LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg &= \
+				~LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLOCK_SEL_Msk;
+			LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |= \
+				LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLOCK_SEL(freq);
+			break;
+
+		default:
+			return 	STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief System global reset
+ *
+ * Use this function to reset system global.
+ *
+ */
+void system_global_reset(void)
+{
+	LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+		~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GLOBAL_RSTN;
+	LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+		LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GLOBAL_RSTN;
+};
+
+/**
+ * \brief System peripheral reset
+ *
+ * Use this function to reset system peripheral.
+ *
+ * \param[in]  peripheral    Selection peripheral
+ *
+ * \return Status of operation.
+ * \retval STATUS_OK               Clock config correctly
+ * \retval STATUS_ERR_INVALID_ARG  If data is invalid
+ */
+enum status_code system_peripheral_reset(enum system_peripheral peripheral)
+{
+	switch (peripheral) {
+		case PERIPHERAL_LPMCU_CPU:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CPU_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CPU_RSTN;
+		break;
+
+		case PERIPHERAL_SPI_FLASH:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_SYS_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_SYS_RSTN;
+		break;
+
+		case PERIPHERAL_SPI_FLASH_IF:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_RSTN;
+		break;
+
+		case PERIPHERAL_SPI0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_CORE_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_CORE_RSTN;
+		break;
+
+		case PERIPHERAL_SPI0_IF:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_IF_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_IF_RSTN;
+		break;
+
+		case PERIPHERAL_SPI1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_CORE_RESETN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_CORE_RESETN;
+		break;
+
+		case PERIPHERAL_SPI1_IF:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_IF_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_IF_RSTN;
+		break;
+
+		case PERIPHERAL_I2C0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_CORE_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_CORE_RSTN;
+		break;
+
+		case PERIPHERAL_I2C0_IF:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_IF_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_IF_RSTN;
+		break;
+
+		case PERIPHERAL_GPIO_CLK:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GPIO_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GPIO_RSTN;
+		break;
+
+		case PERIPHERAL_TIMER:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_TIMER0_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_TIMER0_RSTN;
+		break;
+
+		case PERIPHERAL_UART0_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_CORE_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_CORE_RSTN;
+		break;
+
+		case PERIPHERAL_UART0_IF:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_IF_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_IF_RSTN;
+		break;
+
+		case PERIPHERAL_UART1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_CORE_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_CORE_RSTN;
+		break;
+
+		case PERIPHERAL_UART1_IF:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_IF_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_IF_RSTN;
+		break;
+
+		case PERIPHERAL_WDT0:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT0_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT0_RSTN;
+		break;
+
+		case PERIPHERAL_WDT1:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT1_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT1_RSTN;
+		break;
+
+		case PERIPHERAL_NVIC:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_IRQ_CTRLR_CORE_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_IRQ_CTRLR_CORE_RSTN;
+		break;
+
+		case PERIPHERAL_MBIST:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_MBIST_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_MBIST_RSTN;
+		break;
+
+		case PERIPHERAL_LOW_POWER_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_RSTN;
+		break;
+
+		case PERIPHERAL_LOW_POWER_APB:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_XBAR_IF_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_XBAR_IF_RSTN;
+		break;
+
+		case PERIPHERAL_LPMCU_DEBUG:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_DBUG_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_DBUG_RSTN;
+		break;
+
+		case PERIPHERAL_ARM_FREE_CLK:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_FREE_CLK_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_FREE_CLK_RSTN;
+		break;
+
+		case PERIPHERAL_ARM_APB:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_PRESETN_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_PRESETN_RSTN;
+		break;
+
+		case PERIPHERAL_QDEC0:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC0_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC0_RSTN;
+		break;
+
+		case PERIPHERAL_QDEC1:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC1_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC1_RSTN;
+		break;
+
+		case PERIPHERAL_QDEC2:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC2_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC2_RSTN;
+		break;
+
+		case PERIPHERAL_PWM0:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM0_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM0_RSTN;
+		break;
+
+		case PERIPHERAL_PWM1:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM1_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM1_RSTN;
+		break;
+
+		case PERIPHERAL_PWM2:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM2_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM2_RSTN;
+		break;
+
+		case PERIPHERAL_PWM3:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM3_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM3_RSTN;
+		break;
+
+		case PERIPHERAL_DUALT_TIMER:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_DUALTIMER0_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_DUALTIMER0_RSTN;
+		break;
+
+		case PERIPHERAL_I2C1_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_CORE_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_CORE_RSTN;
+		break;
+
+		case PERIPHERAL_I2C1_IF:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_IF_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_IF_RSTN;
+		break;
+
+		case PERIPHERAL_SHA_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_CORE_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_CORE_RSTN;
+		break;
+
+		case PERIPHERAL_SHA_AHB:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_AHB_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_AHB_RSTN;
+		break;
+
+		case PERIPHERAL_AES_CORE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_CORE_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_CORE_RSTN;
+		break;
+
+		case PERIPHERAL_AES_AHB:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_AHB_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_AHB_RSTN;
+		break;
+
+		case PERIPHERAL_SPI0_SCK_CLK:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_CLK_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_CLK_RSTN;
+		break;
+
+		case PERIPHERAL_SPI1_SCK_CLK:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_CLK_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_CLK_RSTN;
+		break;
+
+		case PERIPHERAL_SPI0_SCK_PHASE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_PHASE_INT_CLK_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_PHASE_INT_CLK_RSTN;
+		break;
+
+		case PERIPHERAL_SPI1_SCK_PHASE:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_PHASE_INT_CLK_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_PHASE_INT_CLK_RSTN;
+		break;
+
+		case PERIPHERAL_DMA:
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_PROV_DMA_CTRL0_RSTN;
+			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_PROV_DMA_CTRL0_RSTN;
+		break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Register the ISR
+ *
+ * Use this function to register a ISR to the RAM table.
+ *
+ * \param[in] isr_index Index of the ISR
+ * \param[in] isr_address Address of the ISR
+ *
+ */
+void system_register_isr(enum ram_isr_table_index isr_index,
+		uint32_t isr_address)
+{
+	uint32_t *temp;
+	temp = (uint32_t *)(isr_index * 4 + ISR_RAM_MAP_START_ADDRESS);
+	*temp = isr_address;
+}
+
+/**
+ * \brief Unregister the ISR
+ *
+ * Use this function to unregister a ISR to the RAM table.
+ *
+ * \param[in] isr_index Index of the ISR
+ *
+ */
+void system_unregister_isr(enum ram_isr_table_index isr_index)
+{
+	uint32_t *temp;
+	temp = (uint32_t *)(isr_index * 4 + ISR_RAM_MAP_START_ADDRESS);
+	*temp = 0;
+}
+
+/**
+ * \brief Initializes an system calibration configuration structure to default values
+ *
+ * This function will initialize a given system calibration configuration
+ * structure to a set of known default values. This function should be called
+ * on any new instance of the configuration structures before being modified by
+ * the user application.
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void system_calibration_get_config_defaults(struct system_calibration_config *config)
+{
+	config->clk_num             = CALIBRATION_CLK_NUM_1024;
+	config->interrupt_control   = CALIBRATION_INTERRUPT_OSC_DONE;
+	config->osc_fractional_part = 0;
+	config->osc_integer_part    = 0;
+	config->rtc_fractional_part = 0;
+	config->rtc_integer_part    = 0;
+}
+
+/**
+ * \brief System calibration set configuration
+ *
+ * Use this function to set system calibration configuration.
+ *
+ * \param[in]  config    Point to struct system_calibration_config
+ *
+ */
+void system_calibration_set_config(struct system_calibration_config *config)
+{
+	Assert(config);
+
+	LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
+		~(LP_CLK_CAL_REGS_CONFIG_REG_NUMBER_CALIB_CLKS_Msk | \
+		LP_CLK_CAL_REGS_CONFIG_REG_IRQ_CONTROL_Msk);
+	LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
+		LP_CLK_CAL_REGS_CONFIG_REG_NUMBER_CALIB_CLKS(config->clk_num) | \
+		LP_CLK_CAL_REGS_CONFIG_REG_IRQ_CONTROL(config->interrupt_control);
+}
+
+/**
+ * \brief System calibration get interrupt status
+ *
+ * Use this function to get system calibration interrupt status.
+ *
+ * \param[in]  config    Point to struct system_calibration_config
+ *
+ * \return Status of operation.
+ * \retval CALBRATION_NO_IN_PROGRESS     No calibration in progress
+ * \retval CALBRATION_IN_PROGRESS        Calibration in progress
+ * \retval CALBRATION_DONE               Calibration done
+ */
+enum system_calibration_status system_calibration_get_interrupt_status( \
+				struct system_calibration_config *config)
+{
+	switch (config->interrupt_control) {
+		case CALIBRATION_INTERRUPT_OSC_DONE:
+			if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING) {
+				return CALBRATION_IN_PROGRESS;
+			} else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE) {
+				return CALBRATION_DONE;
+			}
+			break;
+		case CALIBRATION_INTERRUPT_RTC_DONE:
+			if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING) {
+				return CALBRATION_IN_PROGRESS;
+			} else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
+				return CALBRATION_DONE;
+			}
+			break;
+		case CALIBRATION_INTERRUPT_OSC_OR_RTC_DONE:
+			if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE || \
+				LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
+				return CALBRATION_DONE;
+			} else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING || \
+				LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING){
+				return CALBRATION_IN_PROGRESS;
+			}
+			break;
+		case CALIBRATION_INTERRUPT_OSC_AND_RTC_DONE:
+			if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE && \
+				LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
+				return CALBRATION_DONE;
+			} else if  (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING || \
+				LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING){
+				return CALBRATION_IN_PROGRESS;
+			}
+			break;
+
+		default:
+			return CALBRATION_NO_IN_PROGRESS;
+	}
+
+	return CALBRATION_NO_IN_PROGRESS;
+}
+
+/**
+ * \brief System calibration osc enable
+ *
+ * Use this function to able system calibration osc.
+ */
+void system_osc_calibration_enable(void)
+{
+	LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
+		LP_CLK_CAL_REGS_CONFIG_REG_START_OSC_CALIB;
+}
+
+/**
+ * \brief System calibration osc disable
+ *
+ * Use this function to disable system calibration osc.
+ */
+void system_osc_calibration_disable(void)
+{
+	LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
+		~LP_CLK_CAL_REGS_CONFIG_REG_START_OSC_CALIB;
+}
+
+/**
+ * \brief System calibration osc get status
+ *
+ * Use this function to get system calibration osc status.
+ *
+ * \param[in]  config    Point to struct system_calibration_config
+ *
+ * \return Status of operation.
+ * \retval CALBRATION_NO_IN_PROGRESS     No calibration in progress
+ * \retval CALBRATION_IN_PROGRESS        Calibration in progress
+ * \retval CALBRATION_DONE               Calibration done
+ */
+enum system_calibration_status system_osc_calibration_get_status(void)
+{
+	if (LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.NO_CAL_IN_PROGRESS) {
+		return CALBRATION_NO_IN_PROGRESS;
+	} else if (LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_DONE) {
+		return CALBRATION_DONE;
+	} else {
+		return CALBRATION_IN_PROGRESS;
+	}
+}
+
+/**
+ * \brief System calibration osc clear status
+ *
+ * Use this function to clear system calibration osc status.
+ */
+void system_osc_calibration_clear_status(void)
+{
+	//LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.reg = 0x01;
+}
+
+/**
+ * \brief System calibration osc get results
+ *
+ * Use this function to get system calibration osc results.
+ *
+ * \param[in,out]  config    Point to struct system_calibration_config
+ */
+void system_osc_calibration_result(struct system_calibration_config *config)
+{
+	config->osc_fractional_part = LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_FRAC_COUNT;
+	config->osc_integer_part = LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_INT_COUNT;
+}
+
+/**
+ * \brief System calibration rtc enable
+ *
+ * Use this function to able system calibration rtc.
+ */
+void system_rtc_calibration_enable(void)
+{
+	LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
+		LP_CLK_CAL_REGS_CONFIG_REG_START_RTC_CALIB;
+}
+
+/**
+ * \brief System calibration rtc disable
+ *
+ * Use this function to disable system calibration rtc.
+ */
+void system_rtc_calibration_disable(void)
+{
+	LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
+		~LP_CLK_CAL_REGS_CONFIG_REG_START_RTC_CALIB;
+}
+
+/**
+ * \brief System calibration rtc get status
+ *
+ * Use this function to get system calibration rtc status.
+ *
+ * \param[in]  config    Point to struct system_calibration_config
+ *
+ * \return Status of operation.
+ * \retval CALBRATION_NO_IN_PROGRESS     No calibration in progress
+ * \retval CALBRATION_IN_PROGRESS        Calibration in progress
+ * \retval CALBRATION_DONE               Calibration done
+ */
+enum system_calibration_status system_rtc_calibration_get_status(void)
+{
+	if (LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.NO_CAL_IN_PROGRESS) {
+		return CALBRATION_NO_IN_PROGRESS;
+	} else if (LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_DONE) {
+		return CALBRATION_DONE;
+	} else {
+		return CALBRATION_IN_PROGRESS;
+	}
+}
+
+/**
+ * \brief System calibration rtc clear status
+ *
+ * Use this function to clear system calibration rtc status.
+ */
+void system_rtc_calibration_clear_status(void)
+{
+	//LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.reg = 0x01;
+}
+
+/**
+ * \brief System calibration rtc get results
+ *
+ * Use this function to get system calibration rtc results.
+ *
+ * \param[in,out]  config    Point to struct system_calibration_config
+ */
+void system_rtc_calibration_result(struct system_calibration_config *config)
+{
+	config->rtc_fractional_part = LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_FRAC_COUNT;
+	config->rtc_integer_part = LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_INT_COUNT;
+}
+
+/**
+ * \brief System clock aon config
+ *
+ * Use this function to config system clock aon.
+ *
+ * \param[in]  peripheral_aon  Selection system peripheral aon
+ * \param[in]  aon_resource    Selection system clock aon resource
+ *
+ * \return Status of operation.
+ * \retval STATUS_OK               Clock config correctly
+ * \retval STATUS_ERR_INVALID_ARG  If data is invalid
+ */
+enum status_code system_clock_aon_config( \
+		enum system_peripheral_aon peripheral_aon, \
+		enum system_clock_aon_resource aon_resource)
+{
+	switch (peripheral_aon) {
+		case PERIPHERAL_AON_SLEEP_TIMER:
+			if (aon_resource == CLOCK_AON_RESOURCE_31_25_KHZ) {
+					AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+						AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
+					AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+						~AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
+			} else if (aon_resource == CLOCK_AON_RESOURCE_32_768_KHZ) {
+					AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+						~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
+					AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+						AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
+			} else if (aon_resource == CLOCK_AON_DEFAULT) {
+					AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+						~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
+					AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+						~AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
+			}
+		break;
+
+		case PERIPHERAL_AON_POWER_SEQUENCER:
+			if (aon_resource == CLOCK_AON_RESOURCE_2_MHZ) {
+				AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+					AON_GP_REGS_AON_MISC_CTRL_USE_RTC_AON_PWR_SEQ_CLK;
+				AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+					AON_GP_REGS_AON_MISC_CTRL_USE_2M_AON_PWR_SEQ_CLK;
+			} else if (aon_resource == CLOCK_AON_DEFAULT) {
+				AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+					~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_AON_PWR_SEQ_CLK;
+				AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+					~AON_GP_REGS_AON_MISC_CTRL_USE_2M_AON_PWR_SEQ_CLK;
+			}
+		break;
+
+		case PERIPHERAL_AON_PD:
+			if (aon_resource == CLOCK_AON_RESOURCE_2_MHZ) {
+				AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+					AON_GP_REGS_AON_MISC_CTRL_USE_OSC2M_AS_TB_CLK;
+			} else if (aon_resource == CLOCK_AON_DEFAULT) {
+				AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+					~AON_GP_REGS_AON_MISC_CTRL_USE_OSC2M_AS_TB_CLK;
+			}
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief System clock peripheral aon enable
+ *
+ * Use this function to enable system clock peripheral aon.
+ *
+ * \param[in]  peripheral_aon    Selection peripheral
+ *
+ * \return Status of operation.
+ * \retval STATUS_OK               Clock config correctly
+ * \retval STATUS_ERR_INVALID_ARG  If data is invalid
+ */
+enum status_code system_clock_peripheral_aon_enable(enum system_peripheral_aon peripheral_aon)
+{
+	switch (peripheral_aon) {
+		case PERIPHERAL_AON_SLEEP_TIMER:
+			AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+				AON_GP_REGS_AON_MISC_CTRL_AON_SLEEP_TIMER_CLK_EN;
+		break;
+
+		case PERIPHERAL_AON_PD:
+			AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+				AON_GP_REGS_AON_MISC_CTRL_AON_EXT_32KHZ_OUT_EN;
+		break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief System clock peripheral aon disable
+ *
+ * Use this function to enable system clock peripheral aon.
+ *
+ * \param[in]  peripheral_aon    Selection peripheral
+ *
+ * \return Status of operation.
+ * \retval STATUS_OK               Clock config correctly
+ * \retval STATUS_ERR_INVALID_ARG  If data is invalid
+ */
+enum status_code system_clock_peripheral_aon_disable(enum system_peripheral_aon peripheral_aon)
+{
+	switch (peripheral_aon) {
+		case PERIPHERAL_AON_SLEEP_TIMER:
+			AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+				~AON_GP_REGS_AON_MISC_CTRL_AON_SLEEP_TIMER_CLK_EN;
+		break;
+
+		case PERIPHERAL_AON_PD:
+			AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+				~AON_GP_REGS_AON_MISC_CTRL_AON_EXT_32KHZ_OUT_EN;
+		break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.h
new file mode 100644
index 0000000000..7bfca03b8b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.h
@@ -0,0 +1,608 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_H_INCLUDED
+#define SYSTEM_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_system_group SAM System (SYSTEM) Driver
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the configuration
+ * and management of the device's system relation functionality, necessary for
+ * the basic device operation. This is not limited to a single peripheral, but
+ * extends across multiple hardware peripherals.
+ *
+ * The following peripherals are used by this module
+ *  - SYSCTRL (System Control)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_system_prerequisites
+ *  - \ref asfdoc_samb_system_module_overview
+ *  - \ref asfdoc_samb_system_special_considerations
+ *  - \ref asfdoc_samb_system_extra_info
+ *  - \ref asfdoc_samb_system_examples
+ *  - \ref asfdoc_samb_system_api_overview
+ *
+ *
+ * \section asfdoc_samb_system_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_system_module_overview Module Overview
+ *
+ * The System driver provides a collection of interfaces between the user
+ * application logic, and the core device functionality (such as clocks, reset
+ * cause determination, etc.) that is required for all applications. It contains
+ * a number of sub-modules that control one specific aspect of the device:
+ *
+ *
+ * \section asfdoc_samb_system_special_considerations Special Considerations
+ *
+ * Most of the functions in this driver have device specific restrictions and
+ * caveats; refer to your device datasheet.
+ *
+ *
+ * \section asfdoc_samb_system_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_system_extra. This includes:
+ *  - \ref asfdoc_samb_system_extra_acronyms
+ *  - \ref asfdoc_samb_system_extra_dependencies
+ *  - \ref asfdoc_samb_system_extra_errata
+ *  - \ref asfdoc_samb_system_extra_history
+ *
+ *
+ * \section asfdoc_samb_system_examples Examples
+ *
+ * For SYSTEM module related examples, refer to the sub-modules listed in
+ * the \ref asfdoc_samb_system_module_overview "system module overview".
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_drivers_power_exqsg.
+ *
+ *
+ * \section asfdoc_samb_system_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ISR RAM table address, definition from rom code, */
+#define ISR_RAM_MAP_START_ADDRESS	(0x10000000)
+/* ISR initialization status located in offset 0, definition from rom code*/
+#define ISR_RAM_MAP_INITIALIZED (0x20101985)
+
+/**
+ * \brief ISR RAM table index
+ *
+ * Enum for the index of the ISR in RAm.
+ *
+ */
+enum ram_isr_table_index {
+	RAM_ISR_TABLE_RESET_INDEX              = 1,
+	RAM_ISR_TABLE_NMI_INDEX                = 2,
+	RAM_ISR_TABLE_HARDFAULT_INDEX          = 3,
+	RAM_ISR_TABLE_SVC_INDEX                = 11,
+	RAM_ISR_TABLE_PENDSV_INDEX             = 14,
+	RAM_ISR_TABLE_SYSTICK_INDEX            = 15,
+	RAM_ISR_TABLE_UARTRX0_INDEX            = 16,
+	RAM_ISR_TABLE_UARTTX0_INDEX            = 17,
+	RAM_ISR_TABLE_UARTRX1_INDEX            = 18,
+	RAM_ISR_TABLE_UARTTX1_INDEX            = 19,
+	RAM_ISR_TABLE_SPIRX0_INDEX             = 20,
+	RAM_ISR_TABLE_SPITX0_INDEX             = 21,
+	RAM_ISR_TABLE_SPIRX1_INDEX             = 22,
+	RAM_ISR_TABLE_SPITX1_INDEX             = 23,
+	RAM_ISR_TABLE_I2CRX0_INDEX             = 24,
+	RAM_ISR_TABLE_I2CTX0_INDEX             = 25,
+	RAM_ISR_TABLE_I2CRX1_INDEX             = 26,
+	RAM_ISR_TABLE_I2CTX1_INDEX             = 27,
+	RAM_ISR_TABLE_WDT0_INDEX               = 28,
+	RAM_ISR_TABLE_WDT1_INDEX               = 29,
+	RAM_ISR_TABLE_DUALTIMER_INDEX          = 30,
+	RAM_ISR_TABLE_BLE_PERIPH_REGS_INDEX    = 31,
+	RAM_ISR_TABLE_SECURITY_INDEX           = 32,
+	RAM_ISR_TABLE_EFUSE_OUT_OF_RESET_INDEX = 33,
+	RAM_ISR_TABLE_SPI_FLASH_INDEX          = 34,
+	RAM_ISR_TABLE_LP_CLK_CAL_DONE_INDEX    = 35,	
+	RAM_ISR_TABLE_BROWNOUT_DETECTED_INDEX  = 36,	
+	RAM_ISR_TABLE_BLE_CORE_RESET_INDEX     = 37,
+	RAM_ISR_TABLE_BLE_LP_CORE_RESET_INDEX  = 38,
+	RAM_ISR_TABLE_PORT0_COMB_INDEX         = 39,
+	RAM_ISR_TABLE_PORT1_COMB_INDEX         = 40,
+	RAM_ISR_TABLE_PORT2_COMB_INDEX         = 41,
+	RAM_ISR_TABLE_TIMER0_INDEX             = 42,
+	RAM_ISR_TABLE_AON_SLEEP_TIMER_INDEX    = 43,
+	RAM_ISR_TABLE_BLE_OSC_EN_INDEX         = 44,
+	RAM_ISR_TABLE_BLE_WAKEUP_LP_INDEX      = 45,
+	RAM_ISR_TABLE_RXTX_SEQ_SLEEP_INDEX     = 46,
+	RAM_ISR_TABLE_BLE_CORE_INDEX           = 47,
+};
+
+/**
+ * \brief SYSTEM peripheral enum
+ *
+ * Enum for the possible peripheral for the system.
+ *
+ */
+enum system_peripheral {
+	/** SPI Flash */
+	PERIPHERAL_SPI_FLASH,
+	/** SPI0 Core */
+	PERIPHERAL_SPI0_CORE,
+	/** SPI1 Core */
+	PERIPHERAL_SPI1_CORE,
+	/** I2C0 Core */
+	PERIPHERAL_I2C0_CORE,
+	/** ARM Dual Timer */
+	PERIPHERAL_DUALT_TIMER,
+	/** GPIO Controller */
+	PERIPHERAL_GPIO_CLK,
+	/** ARM Timer */
+	PERIPHERAL_TIMER,
+	/** WDT0 */
+	PERIPHERAL_WDT0,
+	/** WDT1 */
+	PERIPHERAL_WDT1,
+	/** UART0 Core */
+	PERIPHERAL_UART0_CORE,
+	/** UART0 Interface */
+	PERIPHERAL_UART0_IF,
+	/** UART1 Core */
+	PERIPHERAL_UART1_CORE,
+	/** UART1 Interface */
+	PERIPHERAL_UART1_IF,
+	/** NVIC */
+	PERIPHERAL_NVIC,
+	/** IDRAM1 Glue Logic */
+	PERIPHERAL_IDRAM1,
+	/** IDRAM2 Glue Logic */
+	PERIPHERAL_IDRAM2,
+	/** ROM */
+	PERIPHERAL_ROM,
+	/** Low Power Clock Calibration Interface */
+	PERIPHERAL_LOW_POWER_IF,
+	/** AON Wrapper */
+	PERIPHERAL_AON_WRAPPER,
+	/** ARM PCLK */
+	PERIPHERAL_ARM_PCLK,
+	/** ARM Gated PCLK */
+	PERIPHERAL_ARM_GATED_PCLK,
+	/** ARM BLE 8K Retention Memory */
+	PERIPHERAL_ARM_BLE,
+	/** Quad Decoder 0 */
+	PERIPHERAL_QDEC0,
+	/** Quad Decoder 1 */
+	PERIPHERAL_QDEC1,
+	/** Quad Decoder 2 */
+	PERIPHERAL_QDEC2,
+	/** I2C1 Core */
+	PERIPHERAL_I2C1_CORE,
+	/** Low Power Clock Calibration Core */
+	PERIPHERAL_LOW_POWER_CORE,
+
+	/* LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1 */
+	/** EFUSE1 */
+	PERIPHERAL_EFUSE1,
+	/** EFUSE2 */
+	PERIPHERAL_EFUSE2,
+	/** EFUSE3 */
+	PERIPHERAL_EFUSE3,
+	/** EFUSE4 */
+	PERIPHERAL_EFUSE4,
+	/** EFUSE5 */
+	PERIPHERAL_EFUSE5,
+	/** EFUSE6 */
+	PERIPHERAL_EFUSE6,
+	/** PWM0 */
+	PERIPHERAL_PWM0,
+	/** PWM1 */
+	PERIPHERAL_PWM1,
+	/** PWM2 */
+	PERIPHERAL_PWM2,
+	/** PWM3 */
+	PERIPHERAL_PWM3,
+	/** PMU Sensor ADC */
+	PERIPHERAL_ADC,
+	/** SPI0 SCK Phase Internal */
+	PERIPHERAL_SPI0_SCK_PHASE,
+	/** SPI1 SCK Phase Internal */
+	PERIPHERAL_SPI1_SCK_PHASE,
+	/** GPIO Controller */
+	PERIPHERAL_GPIO_GCLK,
+	/** ARM Timer 0 Gated APB */
+	PERIPHERAL_TIMER0_GATE,
+	/** SHA Core */
+	PERIPHERAL_SHA_CORE,
+	/** SHA AHB */
+	PERIPHERAL_SHA_AHB,
+	/** AES Core */
+	PERIPHERAL_AES_CORE,
+	/** AES AHB */
+	PERIPHERAL_AES_AHB,
+	/** IDRAM1_0 Memory */
+	PERIPHERAL_IDRAM1_0,
+	/** IDRAM1_1 Memory */
+	PERIPHERAL_IDRAM1_1,
+	/** IDRAM1_2 Memory */
+	PERIPHERAL_IDRAM1_2,
+	/** IDRAM2_0 Memory */
+	PERIPHERAL_IDRAM2_0,
+	/** IDRAM2_1 Memory */
+	PERIPHERAL_IDRAM2_1,
+
+	/** BLE RXTX Sequencer */
+	PERIPHERAL_BLE_RXTX,
+	/** BLE HAB */
+	PERIPHERAL_BLE_AHB,
+	/** BLE Periph Regs */
+	PERIPHERAL_BLE_PERIPH_REGS,
+
+	/** LPMCU CPU */
+	PERIPHERAL_LPMCU_CPU,
+	/** SPI Flash Interface */
+	PERIPHERAL_SPI_FLASH_IF,
+	/** SPI0 Interface */
+	PERIPHERAL_SPI0_IF,
+	/** SPI1 Interface */
+	PERIPHERAL_SPI1_IF,
+	/** I2C0 Interface */
+	PERIPHERAL_I2C0_IF,
+	/** MBIST Logic */
+	PERIPHERAL_MBIST,
+	/** Low Power Clock Calibration APB */
+	PERIPHERAL_LOW_POWER_APB,
+	/** LPMCU Debug */
+	PERIPHERAL_LPMCU_DEBUG,
+	/** Free Running ARM Clock */
+	PERIPHERAL_ARM_FREE_CLK,
+	/** ARM APB */
+	PERIPHERAL_ARM_APB,
+	/** I2C1 Interface */
+	PERIPHERAL_I2C1_IF,
+	/** SPI0 SCK Clock */
+	PERIPHERAL_SPI0_SCK_CLK,
+	/** SPI1 SCK Clock */
+	PERIPHERAL_SPI1_SCK_CLK,
+	/** DMA Controller */
+	PERIPHERAL_DMA,
+
+	PERIPHERAL_SLEEP_TIMER,
+};
+
+/**
+ * \brief SYSTEM peripheral enum
+ *
+ * Enum for the possible peripheral for the system.
+ *
+ */
+enum system_peripheral_aon {
+	/** Sleep timer */
+	PERIPHERAL_AON_SLEEP_TIMER,
+	/** Power sequencer */
+	PERIPHERAL_AON_POWER_SEQUENCER,
+	/** PD0 */
+	PERIPHERAL_AON_PD,
+};
+
+/**
+ * \brief SYSTEM CLOCK frequency selection enum
+ *
+ * Enum for the possible frequency selection for the CLOCK.
+ *
+ */
+enum system_clock_freq {
+	/** 26MHz */
+	CLOCK_FREQ_26_MHZ,
+	/** 13MHz */
+	CLOCK_FREQ_13_MHZ,
+	/** 6.5MHz */
+	CLOCK_FREQ_6_5_MHZ,
+	/** 3.25MHz */
+	CLOCK_FREQ_3_25_MHZ,
+};
+
+/**
+ * \brief SYSTEM CLOCK resource selection enum
+ *
+ * Enum for the possible resource selection for the CLOCK.
+ *
+ */
+enum system_clock_resource {
+	/** Use 26MHz Crystal Oscillator XO as ARM clock */
+	CLOCK_RESOURCE_XO_26_MHZ,
+	/** Use either LP 2MHz clock */
+	CLOCK_RESOURCE_LP_2_MHZ,
+	/** 26MHz integrated RC Oscillator */
+	CLOCK_RESOURCE_RC_26_MHZ,
+};
+
+/**
+ * \brief SYSTEM CLOCK AON resource selection enum
+ *
+ * Enum for the possible AON resource selection for the CLOCK.
+ *
+ */
+enum system_clock_aon_resource {
+	/** OSC 2MHz */
+	CLOCK_AON_RESOURCE_2_MHZ,
+	/** OSC 2MHz/64 = 31.25KHz */
+	CLOCK_AON_RESOURCE_31_25_KHZ,
+	/** RTC XO 32.768KHz */
+	CLOCK_AON_RESOURCE_32_768_KHZ,
+	/** Use default clock */
+	CLOCK_AON_DEFAULT,
+};
+
+/**
+ * \brief Multiplier value for the number of calibration clocks enum
+ *
+ * Enum for the possible multiplier value for the number of calibration clocks
+ *
+ */
+enum system_calibration_clk_num {
+	/** 1 clock */
+	CALIBRATION_CLK_NUM_1,
+	/** 2 clocks */
+	CALIBRATION_CLK_NUM_2,
+	/** 4 clocks */
+	CALIBRATION_CLK_NUM_4,
+	/** 8 clocks */
+	CALIBRATION_CLK_NUM_8,
+	/** 16 clocks */
+	CALIBRATION_CLK_NUM_16,
+	/** 32 clocks */
+	CALIBRATION_CLK_NUM_32,
+	/** 64 clocks */
+	CALIBRATION_CLK_NUM_64,
+	/** 128 clocks */
+	CALIBRATION_CLK_NUM_128,
+	/** 256 clocks */
+	CALIBRATION_CLK_NUM_256,
+	/** 512 clocks */
+	CALIBRATION_CLK_NUM_512,
+	/** 1024 clocks */
+	CALIBRATION_CLK_NUM_1024,
+	/** 2048 clocks */
+	CALIBRATION_CLK_NUM_2048,
+	/** 4096 clocks */
+	CALIBRATION_CLK_NUM_4096,
+	/** 8192 clocks */
+	CALIBRATION_CLK_NUM_8192,
+	/** 16384 clocks */
+	CALIBRATION_CLK_NUM_16384,
+	/** 32768 clocks */
+	CALIBRATION_CLK_NUM_32768,
+};
+
+/**
+ * \brief Interrupt control enum
+ *
+ * Enum for the possible interrupt control
+ *
+ */
+enum system_calibration_interrput_control {
+	/** IRQ when OSC calibration done */
+	CALIBRATION_INTERRUPT_OSC_DONE,
+	/** IRQ when RTC calibration done */
+	CALIBRATION_INTERRUPT_RTC_DONE,
+	/** IRQ when OSC or RTC calibration done */
+	CALIBRATION_INTERRUPT_OSC_OR_RTC_DONE,
+	/** IRQ when OSC and RTC calibration done */
+	CALIBRATION_INTERRUPT_OSC_AND_RTC_DONE,
+};
+
+enum system_calibration_status {
+	/** No calibration in progress */
+	CALBRATION_NO_IN_PROGRESS,
+	/** Calibration in progress */
+	CALBRATION_IN_PROGRESS,
+	/** Calibration done */
+	CALBRATION_DONE,
+};
+
+struct system_calibration_config {
+	enum system_calibration_clk_num clk_num;
+	enum system_calibration_interrput_control interrupt_control;
+	uint16_t osc_fractional_part;
+	uint16_t osc_integer_part;
+	uint16_t rtc_fractional_part;
+	uint16_t rtc_integer_part;
+};
+
+/**
+ * \name System clock config, enable and disable functions
+ * @{
+ */
+enum status_code system_clock_config( \
+				enum system_clock_resource resoure, \
+				enum system_clock_freq freq);
+uint32_t system_clock_get_value(void);
+enum status_code system_clock_peripheral_enable(enum system_peripheral peripheral);
+enum status_code system_clock_peripheral_disable(enum system_peripheral peripheral);
+enum status_code system_clock_peripheral_freq_config( \
+				enum system_peripheral peripheral, \
+				enum system_clock_freq freq);
+//void system_init(void);
+/** @} */
+
+/**
+ * \name System and peripheral reset
+ * @{
+ */
+void system_global_reset(void);
+enum status_code system_peripheral_reset(enum system_peripheral peripheral);
+/** @} */
+
+/**
+ * \name System ISR register and unregister
+ * @{
+ */
+void system_register_isr(enum ram_isr_table_index isr_index,
+		uint32_t isr_address);
+void system_unregister_isr(enum ram_isr_table_index isr_index);
+/** @} */
+
+/**
+ * \name System clock OSC(32KHz) and RTC(32.768KHz) calibration
+ * @{
+ */
+void system_calibration_get_config_defaults(struct system_calibration_config *config);
+void system_calibration_set_config(struct system_calibration_config *config);
+enum system_calibration_status system_calibration_get_interrupt_status( \
+				struct system_calibration_config *config);
+
+void system_osc_calibration_enable(void);
+void system_osc_calibration_disable(void);
+enum system_calibration_status system_osc_calibration_get_status(void);
+void system_osc_calibration_clear_status(void);
+void system_osc_calibration_result(struct system_calibration_config *config);
+
+void system_rtc_calibration_enable(void);
+void system_rtc_calibration_disable(void);
+enum system_calibration_status system_rtc_calibration_get_status(void);
+void system_rtc_calibration_clear_status(void);
+void system_rtc_calibration_result(struct system_calibration_config *config);
+/** @} */
+
+/**
+ * \name System clock aon config
+ * @{
+ */
+enum status_code system_clock_aon_config( \
+				enum system_peripheral_aon peripheral_aon, \
+				enum system_clock_aon_resource aon_resource);
+enum status_code system_clock_peripheral_aon_enable(enum system_peripheral_aon peripheral_aon);
+enum status_code system_clock_peripheral_aon_disable(enum system_peripheral_aon peripheral_aon);
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+
+* \page asfdoc_samb_drivers_power_exqsg Examples for Power Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications. QSGs are simple examples with step-by-step instructions to
+ * configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * \page asfdoc_samb_system_extra Extra Information for SYSTEM Driver
+ *
+ * \section asfdoc_samb_system_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>SYSCTRL</td>
+ *      <td>System control interface</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_samb_system_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_samb_system_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_system_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ *
+ * \page asfdoc_samb_system_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>08/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ */
+
+#endif /* SYSTEM_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc.h
new file mode 100644
index 0000000000..f34e826609
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc.h
@@ -0,0 +1,1791 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TC_H_INCLUDED
+#define TC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_tc_group SAM Timer/Counter (TC) Driver 
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the timer modules within the device, for waveform
+ * generation and timing operations. The following driver API modes are covered
+ * by this manual:
+ *
+ *  - Polled APIs
+ * \if TC_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ *
+ * The following peripheral is used by this module:
+ *  - TC (Timer/Counter)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_tc_prerequisites
+ *  - \ref asfdoc_sam0_tc_module_overview
+ *  - \ref asfdoc_sam0_tc_special_considerations
+ *  - \ref asfdoc_sam0_tc_extra_info
+ *  - \ref asfdoc_sam0_tc_examples
+ *  - \ref asfdoc_sam0_tc_api_overview
+ *
+ *
+ * \section asfdoc_sam0_tc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_tc_module_overview Module Overview
+ *
+ * The Timer/Counter (TC) module provides a set of timing and counting related
+ * functionality, such as the generation of periodic waveforms, the capturing
+ * of a periodic waveform's frequency/duty cycle, and software timekeeping for
+ * periodic operations. TC modules can be configured to use an 8-, 16-, or
+ * 32-bit counter size.
+ *
+ * This TC module for the SAM is capable of the following functions:
+ *
+ * - Generation of PWM signals
+ * - Generation of timestamps for events
+ * - General time counting
+ * - Waveform period capture
+ * - Waveform frequency capture
+ *
+ * \ref asfdoc_sam0_tc_block_diagram "The diagram below" shows the overview
+ * of the TC module design.
+ *
+ * \anchor asfdoc_sam0_tc_block_diagram
+ * \image html overview.svg "Basic Overview of the TC Module"
+ *
+ *
+ * \subsection asfdoc_sam0_tc_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_TC_DOUBLE_BUFFERED</td>
+ *    <td>SAM L21/L22/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2</td>
+ *    <td>SAM L21/L22/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_TC_STAMP_PW_CAPTURE</td>
+ *    <td>SAM L21/L22/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_TC_READ_SYNC</td>
+ *    <td>SAM L21/L22/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_TC_IO_CAPTURE</td>
+ *    <td>SAM L21/L22/C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_TC_GENERATE_DMA_TRIGGER</td>
+ *    <td>SAM L21/L22</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_func_desc Functional Description
+ * Independent of the configured counter size, each TC module can be set up
+ * in one of two different modes; capture and compare.
+ *
+ * In capture mode, the counter value is stored when a configurable event
+ * occurs. This mode can be used to generate timestamps used in event capture,
+ * or it can be used for the measurement of a periodic input signal's
+ * frequency/duty cycle.
+ *
+ * In compare mode, the counter value is compared against one or more of the
+ * configured channel compare values. When the counter value coincides with a
+ * compare value an action can be taken automatically by the module, such as
+ * generating an output event or toggling a pin when used for frequency or
+ * Pulse Width Modulation (PWM) signal generation.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_tc_size Timer/Counter Size
+ * Each timer module can be configured in one of three different counter
+ * sizes; 8-, 16-, and 32-bit. The size of the counter determines the maximum
+ * value it can count to before an overflow occurs and the count is reset back
+ * to zero. \ref asfdoc_sam0_tc_count_size_vs_top "The table below" shows the
+ * maximum values for each of the possible counter sizes.
+ *
+ * \anchor asfdoc_sam0_tc_count_size_vs_top
+ * <table>
+ *  <caption>Timer Counter Sizes and Their Maximum Count Values</caption>
+ *  <tr>
+ *    <th>Counter size</th>
+ *    <th>Max. (hexadecimal)</th>
+ *    <th>Max. (decimal)</th>
+ *  </tr>
+ *  <tr>
+ *    <td>8-bit</td>
+ *    <td>0xFF</td>
+ *    <td>255</td>
+ *  </tr>
+ *  <tr>
+ *    <td>16-bit</td>
+ *    <td>0xFFFF</td>
+ *    <td>65,535</td>
+ *  </tr>
+ *  <tr>
+ *    <td>32-bit</td>
+ *    <td>0xFFFFFFFF</td>
+ *    <td>4,294,967,295</td>
+ *  </tr>
+ * </table>
+ *
+ * When using the counter in 16- or 32-bit count mode, Compare Capture
+ * register 0 (CC0) is used to store the period value when running in PWM
+ * generation match mode.
+ *
+ * When using 32-bit counter size, two 16-bit counters are chained together
+ * in a cascade formation. Except in SAM D09/D10/D11. Even numbered TC modules
+ * (e.g. TC0, TC2) can be configured as 32-bit counters. The odd numbered
+ * counters will act as slaves to the even numbered masters, and will not
+ * be reconfigurable until the master timer is disabled. The pairing of timer
+ * modules for 32-bit mode is shown in \ref asfdoc_sam0_tc_module_ms_pairs
+ * "the table below".
+ *
+ * \anchor asfdoc_sam0_tc_module_ms_pairs
+ * <table>
+ *   <caption>TC Master and Slave Module Pairings</caption>
+ *   <tr>
+ *     <th>Master TC module</th>
+ *     <th>Slave TC module</th>
+ *   </tr>
+ *   <tr>
+ *     <td>TC0</td>
+ *     <td>TC1</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TC2</td>
+ *     <td>TC3</td>
+ *   </tr>
+ *   <tr>
+ *     <td>...</td>
+ *     <td>...</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCn-1</td>
+ *     <td>TCn</td>
+ *   </tr>
+ * </table>
+ *
+ * In SAM D09/D10/D11, odd numbered TC modules (e.g. TC1) can be configured as 32-bit
+ * counters. The even numbered (e.g. TC2) counters will act as slaves to the odd
+ * numbered masters.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_clock Clock Settings
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_clock_selection Clock Selection
+ * Each TC peripheral is clocked asynchronously to the system clock by a GCLK
+ * (Generic Clock) channel. The GCLK channel connects to any of the GCLK
+ * generators. The GCLK generators are configured to use one of the available
+ * clock sources on the system such as internal oscillator, external crystals,
+ * etc. See the \ref asfdoc_sam0_system_clock_group "Generic Clock driver"
+ *for
+ * more information.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_clock_prescaler Prescaler
+ * Each TC module in the SAM has its own individual clock prescaler, which
+ * can be used to divide the input clock frequency used in the counter. This
+ * prescaler only scales the clock used to provide clock pulses for the counter
+ * to count, and does not affect the digital register interface portion of
+ * the module, thus the timer registers will synchronize to the raw GCLK
+ * frequency input to the module.
+ *
+ * As a result of this, when selecting a GCLK frequency and timer prescaler
+ * value the user application should consider both the timer resolution
+ * required and the synchronization frequency, to avoid lengthy
+ * synchronization times of the module if a very slow GCLK frequency is fed
+ * into the TC module. It is preferable to use a higher module GCLK frequency
+ * as the input to the timer, and prescale this down as much as possible to
+ * obtain a suitable counter frequency in latency-sensitive applications.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_clock_reloading Reloading
+ * Timer modules also contain a configurable reload action, used when a
+ * re-trigger event occurs. Examples of a re-trigger event are the counter
+ * reaching the maximum value when counting up, or when an event from the event
+ * system tells the counter to re-trigger. The reload action determines if the
+ * prescaler should be reset, and when this should happen. The counter will
+ * always be reloaded with the value it is set to start counting from. The user
+ * can choose between three different reload actions, described in
+ * \ref asfdoc_sam0_tc_module_reload_act "the table below".
+ *
+ * \anchor asfdoc_sam0_tc_module_reload_act
+ * <table>
+ *   <caption>TC Module Reload Actions</caption>
+ *   <tr>
+ *     <th>Reload action</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>\ref TC_RELOAD_ACTION_GCLK </td>
+ *     <td>Reload TC counter value on next GCLK cycle. Leave prescaler
+ *         as-is.</td>
+ *   </tr>
+ *   <tr>
+ *     <td>\ref TC_RELOAD_ACTION_PRESC </td>
+ *     <td>Reloads TC counter value on next prescaler clock. Leave prescaler
+ *         as-is.</td>
+ *   </tr>
+ *  <tr>
+ *    <td> \ref TC_RELOAD_ACTION_RESYNC </td>
+ *    <td>Reload TC counter value on next GCLK cycle. Clear prescaler to
+ *        zero.</td>
+ *  </tr>
+ * </table>
+ *
+ * The reload action to use will depend on the specific application being
+ * implemented. One example is when an external trigger for a reload occurs; if
+ * the TC uses the prescaler, the counter in the prescaler should not have a
+ * value between zero and the division factor. The TC counter and the counter
+ * in the prescaler should both start at zero. When the counter is set to
+ * re-trigger when it reaches the maximum value on the other hand, this is not the
+ * right option to use. In such a case it would be better if the prescaler is
+ * left unaltered when the re-trigger happens, letting the counter reset on the
+ * next GCLK cycle.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_compare_match Compare Match Operations
+ * In compare match operation, Compare/Capture registers are used in comparison
+ * with the counter value. When the timer's count value matches the value of a
+ * compare channel, a user defined action can be taken.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_timer Basic Timer
+ *
+ * A Basic Timer is a simple application where compare match operations are used
+ * to determine when a specific period has elapsed. In Basic Timer operations,
+ * one or more values in the module's Compare/Capture registers are used to
+ * specify the time (as a number of prescaled GCLK cycles) when an action should
+ * be taken by the microcontroller. This can be an Interrupt Service Routine
+ * (ISR), event generator via the event system, or a software flag that is
+ * polled via the user application.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg Waveform Generation
+ *
+ * Waveform generation enables the TC module to generate square waves, or if
+ * combined with an external passive low-pass filter; analog waveforms.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_pwm Waveform Generation - PWM
+ *
+ * Pulse width modulation is a form of waveform generation and a signalling
+ * technique that can be useful in many situations. When PWM mode is used,
+ * a digital pulse train with a configurable frequency and duty cycle can be
+ * generated by the TC module and output to a GPIO pin of the device.
+ *
+ * Often PWM is used to communicate a control or information parameter to an
+ * external circuit or component. Differing impedances of the source generator
+ * and sink receiver circuits are less of an issue when using PWM compared to
+ * using an analog voltage value, as noise will not generally affect the
+ * signal's integrity to a meaningful extent.
+ *
+ * \ref asfdoc_sam0_tc_module_pwm_normal_diag "The figure below" illustrates
+ * operations and different states of the counter and its output when running
+ * the counter in PWM normal mode. As can be seen, the TOP value is unchanged
+ * and is set to MAX. The compare match value is changed at several points to
+ * illustrate the resulting waveform output changes. The PWM output is set to
+ * normal (i.e. non-inverted) output mode.
+ *
+ * \anchor asfdoc_sam0_tc_module_pwm_normal_diag
+ * \image html pwm_normal_ex.svg "Example of PWM in Normal Mode, and Different Counter Operations"
+ *
+ *
+ * In \ref asfdoc_sam0_tc_module_pwm_match_diag "the figure below", the
+ * counter is set to generate PWM in Match mode. The PWM output is inverted via
+ * the appropriate configuration option in the TC driver configuration
+ * structure. In this example, the counter value is changed once, but the
+ * compare match value is kept unchanged. As can be seen, it is possible to
+ * change the TOP value when running in PWM match mode.
+ *
+ * \anchor asfdoc_sam0_tc_module_pwm_match_diag
+ * \image html pwm_match_ex.svg "Example of PWM in Match Mode and Different Counter Operations"
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_freq Waveform Generation - Frequency
+ *
+ * Frequency Generation mode is in many ways identical to PWM
+ * generation. However, in Frequency Generation a toggle only occurs
+ * on the output when a match on a capture channels occurs. When the
+ * match is made, the timer value is reset, resulting in a variable
+ * frequency square wave with a fixed 50% duty cycle.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt Capture Operations
+ *
+ * In capture operations, any event from the event system or a pin change can
+ * trigger a capture of the counter value. This captured counter value can be
+ * used as a timestamp for the event, or it can be used in frequency and pulse
+ * width capture.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_event_capture Capture Operations - Event
+ *
+ * Event capture is a simple use of the capture functionality,
+ * designed to create timestamps for specific events. When the TC
+ * module's input capture pin is externally toggled, the current timer
+ * count value is copied into a buffered register which can then be
+ * read out by the user application.
+ *
+ * Note that when performing any capture operation, there is a risk that the
+ * counter reaches its top value (MAX) when counting up, or the bottom value
+ * (zero) when counting down, before the capture event occurs. This can distort
+ * the result, making event timestamps to appear shorter than reality; the
+ * user application should check for timer overflow when reading a capture
+ * result in order to detect this situation and perform an appropriate
+ * adjustment.
+ *
+ * Before checking for a new capture, \ref TC_STATUS_COUNT_OVERFLOW
+ * should be checked. The response to an overflow error is left to the user
+ * application, however it may be necessary to clear both the capture overflow
+ * flag and the capture flag upon each capture reading.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_pwc Capture Operations - Pulse Width
+ *
+ * Pulse Width Capture mode makes it possible to measure the pulse width and
+ * period of PWM signals. This mode uses two capture channels of the counter.
+ * This means that the counter module used for Pulse Width Capture can not be
+ * used for any other purpose. There are two modes for pulse width capture;
+ * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture
+ * channel 0 is used for storing the pulse width and capture channel 1 stores
+ * the observed period. While in PPW mode, the roles of the two capture channels
+ * are reversed.
+ *
+ * As in the above example it is necessary to poll on interrupt flags to see
+ * if a new capture has happened and check that a capture overflow error has
+ * not occurred.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_oneshot One-shot Mode
+ *
+ * TC modules can be configured into a one-shot mode. When configured in this
+ * manner, starting the timer will cause it to count until the next overflow
+ * or underflow condition before automatically halting, waiting to be manually
+ * triggered by the user application software or an event signal from the event
+ * system.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_inversion Wave Generation Output Inversion
+ *
+ * The output of the wave generation can be inverted by hardware if desired,
+ * resulting in the logically inverted value being output to the configured
+ * device GPIO pin.
+ *
+ *
+ * \section asfdoc_sam0_tc_special_considerations Special Considerations
+ *
+ * The number of capture compare registers in each TC module is dependent on
+ * the specific SAM device being used, and in some cases the counter size.
+ *
+ * The maximum amount of capture compare registers available in any SAM
+ * device is two when running in 32-bit mode and four in 8- and 16-bit modes.
+ *
+ *
+ * \section asfdoc_sam0_tc_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_tc_extra. This includes:
+ *  - \ref asfdoc_sam0_tc_extra_acronyms
+ *  - \ref asfdoc_sam0_tc_extra_dependencies
+ *  - \ref asfdoc_sam0_tc_extra_errata
+ *  - \ref asfdoc_sam0_tc_extra_history
+ *
+ *
+ * \section asfdoc_sam0_tc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_tc_exqsg.
+ *
+ * \section asfdoc_sam0_tc_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+
+/**
+ * Define port features set according to different device family
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+/** TC double buffered. */
+#  define FEATURE_TC_DOUBLE_BUFFERED
+/** SYNCBUSY scheme version 2. */
+#  define FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2
+/** TC time stamp capture and pulse width capture. */
+#  define FEATURE_TC_STAMP_PW_CAPTURE
+/** Read synchronization of COUNT. */
+#  define FEATURE_TC_READ_SYNC
+/** I/O pin edge capture. */
+#  define FEATURE_TC_IO_CAPTURE
+#endif
+
+#if (SAML21XXXB) || (SAMR30) || defined(__DOXYGEN__)
+/** Generate Direct Memory Access (DMA) triggers. */
+#  define FEATURE_TC_GENERATE_DMA_TRIGGER
+#endif
+/*@}*/
+
+#if !defined(__DOXYGEN__)
+#if SAMD20 || SAML21 || SAML22 || SAMC20 || SAMC21 || SAMR30
+#  define TC_INSTANCE_OFFSET 0
+#endif
+#if SAMD21 || SAMR21 || SAMDA1 || SAMHA1
+#  define TC_INSTANCE_OFFSET 3
+#endif
+#if SAMD09 || SAMD10 || SAMD11
+#  define TC_INSTANCE_OFFSET 1
+#endif
+
+#if SAMD20
+#  define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC8_NUM
+#elif SAML21 || SAML22 || SAMC20 || SAMC21 || SAMR30
+#  define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC_NUM
+#elif SAMD09 || SAMD10 || SAMD11
+#  define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC1_CC8_NUM
+#else
+#  define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC3_CC8_NUM
+   /* Same number for 8-, 16- or 32-bit TC and all TC instances */
+#endif
+
+/** TC Instance MAX ID Number. */
+#if SAMD20E || SAMD20G || SAMD21G || SAMD21E || SAMR21
+#  if SAMD21GXXL || SAM_PART_IS_DEFINED(SAMD21G17AU) || SAM_PART_IS_DEFINED(SAMD21G18AU)
+#    define TC_INST_MAX_ID  7
+#  else
+#    define TC_INST_MAX_ID  5
+#  endif
+#elif SAML21 || SAMC20 || SAMC21 || SAMR30
+#  define TC_INST_MAX_ID  4
+#elif SAML22
+#  define TC_INST_MAX_ID  3
+#elif SAMD09 || SAMD10 || SAMD11
+#  define TC_INST_MAX_ID  2
+#else
+#  define TC_INST_MAX_ID  7
+#endif
+
+#endif
+
+#if TC_ASYNC == true
+#  include <system_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if TC_ASYNC == true
+/** Enum for the possible callback types for the TC module. */
+enum tc_callback {
+	/** Callback for TC overflow */
+	TC_CALLBACK_OVERFLOW,
+	/** Callback for capture overflow error */
+	TC_CALLBACK_ERROR,
+	/** Callback for capture compare channel 0 */
+	TC_CALLBACK_CC_CHANNEL0,
+	/** Callback for capture compare channel 1 */
+	TC_CALLBACK_CC_CHANNEL1,
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	TC_CALLBACK_N,
+#  endif
+};
+#endif
+
+/**
+ * \name Module Status Flags
+ *
+ * TC status flags, returned by \ref tc_get_status() and cleared by
+ * \ref tc_clear_status().
+ *
+ * @{
+ */
+
+/** Timer channel 0 has matched against its compare value, or has captured a
+ *  new value.
+ */
+#define TC_STATUS_CHANNEL_0_MATCH    (1UL << 0)
+
+/** Timer channel 1 has matched against its compare value, or has captured a
+ *  new value.
+ */
+#define TC_STATUS_CHANNEL_1_MATCH    (1UL << 1)
+
+/** Timer register synchronization has completed, and the synchronized count
+ *  value may be read.
+ */
+#define TC_STATUS_SYNC_READY         (1UL << 2)
+
+/** A new value was captured before the previous value was read, resulting in
+ *  lost data.
+ */
+#define TC_STATUS_CAPTURE_OVERFLOW   (1UL << 3)
+
+/** The timer count value has overflowed from its maximum value to its minimum
+ *  when counting upward, or from its minimum value to its maximum when
+ *  counting downward.
+ */
+#define TC_STATUS_COUNT_OVERFLOW     (1UL << 4)
+
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+/** Channel 0 compare or capture buffer valid. */
+#define TC_STATUS_CHN0_BUFFER_VALID     (1UL << 5)
+/** Channel 1 compare or capture buffer valid. */
+#define TC_STATUS_CHN1_BUFFER_VALID     (1UL << 6)
+/** Period buffer valid. */
+#define TC_STATUS_PERIOD_BUFFER_VALID     (1UL << 7)
+#endif
+/** @} */
+
+/**
+ * \brief Index of the compare capture channels.
+ *
+ * This enum is used to specify which capture/compare channel to do
+ * operations on.
+ */
+enum tc_compare_capture_channel {
+	/** Index of compare capture channel 0 */
+	TC_COMPARE_CAPTURE_CHANNEL_0,
+	/** Index of compare capture channel 1 */
+	TC_COMPARE_CAPTURE_CHANNEL_1,
+};
+
+/**
+ * \name TC Wave Generation Mode
+ *
+ * @{
+ */
+#if SAML21 || SAML22 || SAMC20 || SAMC21 || SAMR30
+/** TC wave generation mode: normal frequency. */
+#define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_WAVE_WAVEGEN_NFRQ
+/** TC wave generation mode: match frequency. */
+#define TC_WAVE_GENERATION_MATCH_FREQ_MODE  TC_WAVE_WAVEGEN_MFRQ
+/** TC wave generation mode: normal PWM. */
+#define TC_WAVE_GENERATION_NORMAL_PWM_MODE  TC_WAVE_WAVEGEN_NPWM
+/** TC wave generation mode: match PWM. */
+#define TC_WAVE_GENERATION_MATCH_PWM_MODE   TC_WAVE_WAVEGEN_MPWM
+#else
+/** TC wave generation mode: normal frequency. */
+#define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_CTRLA_WAVEGEN_NFRQ
+/** TC wave generation mode: match frequency. */
+#define TC_WAVE_GENERATION_MATCH_FREQ_MODE  TC_CTRLA_WAVEGEN_MFRQ
+/** TC wave generation mode: normal PWM. */
+#define TC_WAVE_GENERATION_NORMAL_PWM_MODE  TC_CTRLA_WAVEGEN_NPWM
+/** TC wave generation mode: match PWM. */
+#define TC_WAVE_GENERATION_MATCH_PWM_MODE   TC_CTRLA_WAVEGEN_MPWM
+#endif
+/** @} */
+
+/**
+ * \brief TC wave generation mode enum.
+ *
+ * This enum is used to select which mode to run the wave
+ * generation in.
+ *
+ */
+enum tc_wave_generation {
+	/** Top is maximum, except in 8-bit counter size where it is the PER
+	 * register
+	 */
+	TC_WAVE_GENERATION_NORMAL_FREQ      = TC_WAVE_GENERATION_NORMAL_FREQ_MODE,
+
+	/** Top is CC0, except in 8-bit counter size where it is the PER
+	 * register
+	 */
+	TC_WAVE_GENERATION_MATCH_FREQ       = TC_WAVE_GENERATION_MATCH_FREQ_MODE,
+
+	/** Top is maximum, except in 8-bit counter size where it is the PER
+	 * register
+	 */
+	TC_WAVE_GENERATION_NORMAL_PWM       = TC_WAVE_GENERATION_NORMAL_PWM_MODE,
+
+	/** Top is CC0, except in 8-bit counter size where it is the PER
+	 * register
+	 */
+	TC_WAVE_GENERATION_MATCH_PWM        = TC_WAVE_GENERATION_MATCH_PWM_MODE,
+};
+
+/**
+ * \brief Specifies if the counter is 8-, 16-, or 32-bit.
+ *
+ * This enum specifies the maximum value it is possible to count to.
+ */
+enum tc_counter_size {
+	/** The counter's maximum value is 0xFF, the period register is
+	 * available to be used as top value
+	 */
+	TC_COUNTER_SIZE_8BIT                = TC_CTRLA_MODE_COUNT8,
+
+	/** The counter's maximum value is 0xFFFF. There is no separate
+	 * period register, to modify top one of the capture compare
+	 * registers has to be used. This limits the amount of
+	 * available channels.
+	 */
+	TC_COUNTER_SIZE_16BIT               = TC_CTRLA_MODE_COUNT16,
+
+	/** The counter's maximum value is 0xFFFFFFFF. There is no separate
+	 * period register, to modify top one of the capture compare
+	 * registers has to be used. This limits the amount of
+	 * available channels.
+	 */
+	TC_COUNTER_SIZE_32BIT               = TC_CTRLA_MODE_COUNT32,
+};
+
+/**
+ * \brief TC Counter reload action enum.
+ *
+ * This enum specify how the counter and prescaler should reload.
+ */
+enum tc_reload_action {
+	/** The counter is reloaded/reset on the next GCLK and starts
+	 * counting on the prescaler clock
+	 */
+	TC_RELOAD_ACTION_GCLK               = TC_CTRLA_PRESCSYNC_GCLK,
+
+	/** The counter is reloaded/reset on the next prescaler clock
+	 */
+	TC_RELOAD_ACTION_PRESC              = TC_CTRLA_PRESCSYNC_PRESC,
+
+	/** The counter is reloaded/reset on the next GCLK, and the
+	 * prescaler is restarted as well
+	 */
+	TC_RELOAD_ACTION_RESYNC             = TC_CTRLA_PRESCSYNC_RESYNC,
+};
+
+/**
+ * \brief TC clock prescaler values.
+ *
+ * This enum is used to choose the clock prescaler
+ * configuration. The prescaler divides the clock frequency of the TC
+ * module to make the counter count slower.
+ */
+enum tc_clock_prescaler {
+	/** Divide clock by 1 */
+	TC_CLOCK_PRESCALER_DIV1             = TC_CTRLA_PRESCALER(0),
+	/** Divide clock by 2 */
+	TC_CLOCK_PRESCALER_DIV2             = TC_CTRLA_PRESCALER(1),
+	/** Divide clock by 4 */
+	TC_CLOCK_PRESCALER_DIV4             = TC_CTRLA_PRESCALER(2),
+	/** Divide clock by 8 */
+	TC_CLOCK_PRESCALER_DIV8             = TC_CTRLA_PRESCALER(3),
+	/** Divide clock by 16 */
+	TC_CLOCK_PRESCALER_DIV16            = TC_CTRLA_PRESCALER(4),
+	/** Divide clock by 64 */
+	TC_CLOCK_PRESCALER_DIV64            = TC_CTRLA_PRESCALER(5),
+	/** Divide clock by 256 */
+	TC_CLOCK_PRESCALER_DIV256           = TC_CTRLA_PRESCALER(6),
+	/** Divide clock by 1024 */
+	TC_CLOCK_PRESCALER_DIV1024          = TC_CTRLA_PRESCALER(7),
+};
+
+/**
+ * \brief TC module count direction.
+ *
+ * Timer/Counter count direction.
+ */
+enum tc_count_direction {
+	/** Timer should count upward from zero to MAX */
+	TC_COUNT_DIRECTION_UP,
+
+	/** Timer should count downward to zero from MAX */
+	TC_COUNT_DIRECTION_DOWN,
+};
+
+/**
+ * \name Waveform Inversion Mode
+ *
+ * @{
+ */
+#if SAML21 || SAML22 || SAMC20 || SAMC21 || SAMR30
+/** Waveform inversion CC0 mode. */
+#define TC_WAVEFORM_INVERT_CC0_MODE  TC_DRVCTRL_INVEN(1)
+/** Waveform inversion CC1 mode. */
+#define TC_WAVEFORM_INVERT_CC1_MODE  TC_DRVCTRL_INVEN(2)
+#else
+/** Waveform inversion CC0 mode. */
+#define TC_WAVEFORM_INVERT_CC0_MODE  TC_CTRLC_INVEN(1)
+/** Waveform inversion CC1 mode. */
+#define TC_WAVEFORM_INVERT_CC1_MODE  TC_CTRLC_INVEN(2)
+#endif
+
+/**
+ * \brief Waveform inversion mode.
+ *
+ * Output waveform inversion mode.
+ */
+enum tc_waveform_invert_output {
+	/** No inversion of the waveform output */
+	TC_WAVEFORM_INVERT_OUTPUT_NONE      = 0,
+	/** Invert output from compare channel 0 */
+	TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE,
+	/** Invert output from compare channel 1 */
+	TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE,
+};
+
+/**
+ * \brief Action to perform when the TC module is triggered by an event.
+ *
+ * Event action to perform when the module is triggered by an event.
+ */
+enum tc_event_action {
+	/** No event action */
+	TC_EVENT_ACTION_OFF                 = TC_EVCTRL_EVACT_OFF,
+	/** Re-trigger on event */
+	TC_EVENT_ACTION_RETRIGGER           = TC_EVCTRL_EVACT_RETRIGGER,
+	/** Increment counter on event */
+	TC_EVENT_ACTION_INCREMENT_COUNTER   = TC_EVCTRL_EVACT_COUNT,
+	/** Start counter on event */
+	TC_EVENT_ACTION_START               = TC_EVCTRL_EVACT_START,
+
+	/** Store period in capture register 0, pulse width in capture
+	 *  register 1
+	 */
+	TC_EVENT_ACTION_PPW                 = TC_EVCTRL_EVACT_PPW,
+
+	/** Store pulse width in capture register 0, period in capture
+	 *  register 1
+	 */
+	TC_EVENT_ACTION_PWP                 = TC_EVCTRL_EVACT_PWP,
+#ifdef FEATURE_TC_STAMP_PW_CAPTURE
+	/** Time stamp capture */
+	TC_EVENT_ACTION_STAMP               = TC_EVCTRL_EVACT_STAMP,
+	/** Pulse width capture */
+	TC_EVENT_ACTION_PW                  = TC_EVCTRL_EVACT_PW,
+#endif
+};
+
+/**
+ * \brief TC event enable/disable structure.
+ *
+ * Event flags for the \ref tc_enable_events() and \ref tc_disable_events().
+ */
+struct tc_events {
+	/** Generate an output event on a compare channel match */
+	bool generate_event_on_compare_channel
+			[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+	/** Generate an output event on counter overflow */
+	bool generate_event_on_overflow;
+	/** Perform the configured event action when an incoming event is signalled */
+	bool on_event_perform_action;
+	/** Specifies if the input event source is inverted, when used in PWP or
+	 *  PPW event action modes
+	 */
+	bool invert_event_input;
+	/** Specifies which event to trigger if an event is triggered */
+	enum tc_event_action event_action;
+};
+
+/**
+ * \brief Configuration struct for TC module in 8-bit size counter mode.
+ */
+struct tc_8bit_config {
+	/** Initial timer count value */
+	uint8_t value;
+	/** Where to count to or from depending on the direction on the counter */
+	uint8_t period;
+	/** Value to be used for compare match on each channel */
+	uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+};
+
+/**
+ * \brief Configuration struct for TC module in 16-bit size counter mode.
+ */
+struct tc_16bit_config {
+	/** Initial timer count value */
+	uint16_t value;
+	/** Value to be used for compare match on each channel */
+	uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+};
+
+/**
+ * \brief Configuration struct for TC module in 32-bit size counter mode.
+ */
+struct tc_32bit_config {
+	/** Initial timer count value */
+	uint32_t value;
+	/** Value to be used for compare match on each channel */
+	uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+};
+
+/**
+ * \brief Configuration struct for TC module in 32-bit size counter mode.
+ */
+struct tc_pwm_channel {
+	/** When \c true, PWM output for the given channel is enabled */
+	bool enabled;
+	/** Specifies pin output for each channel */
+	uint32_t pin_out;
+	/** Specifies Multiplexer (MUX) setting for each output channel pin */
+	uint32_t pin_mux;
+};
+
+/**
+ * \brief TC configuration structure.
+ *
+ * Configuration struct for a TC instance. This structure should be
+ * initialized by the \ref tc_get_config_defaults function before being
+ * modified by the user application.
+ */
+struct tc_config {
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+
+	/** When \c true the module is enabled during standby */
+	bool run_in_standby;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/** Run on demand */
+	bool on_demand;
+#endif
+	/** Specifies either 8-, 16-, or 32-bit counter size */
+	enum tc_counter_size counter_size;
+	/** Specifies the prescaler value for GCLK_TC */
+	enum tc_clock_prescaler clock_prescaler;
+	/** Specifies which waveform generation mode to use */
+	enum tc_wave_generation wave_generation;
+
+	/** Specifies the reload or reset time of the counter and prescaler
+	 *  resynchronization on a re-trigger event for the TC
+	 */
+	enum tc_reload_action reload_action;
+
+	/** Specifies which channel(s) to invert the waveform on.
+		For SAM L21/L22/C20/C21, it's also used to invert I/O input pin. */
+	uint8_t waveform_invert_output;
+
+	/** Specifies which channel(s) to enable channel capture
+	 *  operation on
+	 */
+	bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+#ifdef 	FEATURE_TC_IO_CAPTURE
+	/** Specifies which channel(s) to enable I/O capture
+	 *  operation on
+	 */
+	bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+#endif
+
+	/** When \c true, one-shot will stop the TC on next hardware or software
+	 *  re-trigger event or overflow/underflow
+	 */
+	bool oneshot;
+
+	/** Specifies the direction for the TC to count */
+	enum tc_count_direction count_direction;
+
+	/** Specifies the PWM channel for TC */
+	struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+
+	/** Access the different counter size settings through this configuration member. */
+	union {
+		/** Struct for 8-bit specific timer configuration */
+		struct tc_8bit_config counter_8_bit;
+		/** Struct for 16-bit specific timer configuration */
+		struct tc_16bit_config counter_16_bit;
+		/** Struct for 32-bit specific timer configuration */
+		struct tc_32bit_config counter_32_bit;
+	};
+
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+	/** Set to \c true to enable double buffering write. When enabled any write
+	 *  through \ref tc_set_top_value(), \ref tc_set_compare_value() and
+	 *  will direct to the buffer register as buffered
+	 *  value, and the buffered value will be committed to effective register
+	 *  on UPDATE condition, if update is not locked.
+	 */
+	bool double_buffering_enabled;
+#endif
+};
+
+#if TC_ASYNC == true
+/** Forward Declaration for the device instance. */
+struct tc_module;
+
+/** Type of the callback functions. */
+typedef void (*tc_callback_t)(struct tc_module *const module);
+#endif
+
+/**
+ * \brief TC software device instance structure.
+ *
+ * TC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct tc_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware module pointer of the associated Timer/Counter peripheral */
+	Tc *hw;
+
+	/** Size of the initialized Timer/Counter module configuration */
+	enum tc_counter_size counter_size;
+#  if TC_ASYNC == true
+	/** Array of callbacks */
+	tc_callback_t callback[TC_CALLBACK_N];
+	/** Bit mask for callbacks registered */
+	uint8_t register_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t enable_callback_mask;
+#  endif
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+	/** Set to \c true to enable double buffering write */
+	bool double_buffering_enabled;
+#endif
+#endif
+};
+
+#if !defined(__DOXYGEN__)
+uint8_t _tc_get_inst_index(
+		Tc *const hw);
+#endif
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to
+ * the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false If the module has completed synchronization
+ * \retval true  If the module synchronization is ongoing
+ */
+static inline bool tc_is_syncing(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	return (tc_module->SYNCBUSY.reg);
+#else
+	return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY);
+#endif
+}
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given TC configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structures before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li GCLK generator 0 (GCLK main) clock source
+ *  \li 16-bit counter size on the counter
+ *  \li No prescaler
+ *  \li Normal frequency wave generation
+ *  \li GCLK reload action
+ *  \li Don't run in standby
+ *  \li Don't run on demand for SAM L21/L22/C20/C21
+ *  \li No inversion of waveform output
+ *  \li No capture enabled
+ *  \li No I/O capture enabled for SAM L21/L22/C20/C21
+ *  \li No event input enabled
+ *  \li Count upward
+ *  \li Don't perform one-shot operations
+ *  \li No event action
+ *  \li No channel 0 PWM output
+ *  \li No channel 1 PWM output
+ *  \li Counter starts on 0
+ *  \li Capture compare channel 0 set to 0
+ *  \li Capture compare channel 1 set to 0
+ *  \li No PWM pin output enabled
+ *  \li Pin and MUX configuration not set
+ *  \li Double buffer disabled (if have this feature)
+ *
+ * \param[out]  config  Pointer to a TC module configuration structure to set
+ */
+static inline void tc_get_config_defaults(
+		struct tc_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Write default config to config struct */
+	config->clock_source               = GCLK_GENERATOR_0;
+	config->counter_size               = TC_COUNTER_SIZE_16BIT;
+	config->clock_prescaler            = TC_CLOCK_PRESCALER_DIV1;
+	config->wave_generation            = TC_WAVE_GENERATION_NORMAL_FREQ;
+	config->reload_action              = TC_RELOAD_ACTION_GCLK;
+	config->run_in_standby             = false;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	config->on_demand                  = false;
+#endif
+	config->waveform_invert_output     = TC_WAVEFORM_INVERT_OUTPUT_NONE;
+	config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false;
+	config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false;
+#ifdef 	FEATURE_TC_IO_CAPTURE
+	config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false;
+	config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false;
+#endif
+
+	config->count_direction            = TC_COUNT_DIRECTION_UP;
+	config->oneshot                    = false;
+
+	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false;
+	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0;
+	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0;
+
+	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false;
+	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0;
+	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0;
+
+	config->counter_16_bit.value                   = 0x0000;
+	config->counter_16_bit.compare_capture_channel\
+		[TC_COMPARE_CAPTURE_CHANNEL_0]                        = 0x0000;
+	config->counter_16_bit.compare_capture_channel\
+		[TC_COMPARE_CAPTURE_CHANNEL_1]                        = 0x0000;
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+	config->double_buffering_enabled = false;
+#endif
+
+}
+
+enum status_code tc_init(
+		struct tc_module *const module_inst,
+		Tc *const hw,
+		const struct tc_config *const config);
+
+/** @} */
+
+/**
+ * \name Event Management
+ * @{
+ */
+
+/**
+ * \brief Enables a TC module event input or output.
+ *
+ * Enables one or more input or output events to or from the TC module.
+ * See \ref tc_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in]  module_inst  Pointer to the software module instance struct
+ * \param[in]  events       Struct containing flags of events to enable
+ */
+static inline void tc_enable_events(
+		struct tc_module *const module_inst,
+		struct tc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Tc *const tc_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	if (events->invert_event_input == true) {
+		event_mask |= TC_EVCTRL_TCINV;
+	}
+
+	if (events->on_event_perform_action == true) {
+		event_mask |= TC_EVCTRL_TCEI;
+	}
+
+	if (events->generate_event_on_overflow == true) {
+		event_mask |= TC_EVCTRL_OVFEO;
+	}
+
+	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+		if (events->generate_event_on_compare_channel[i] == true) {
+			event_mask |= (TC_EVCTRL_MCEO(1) << i);
+		}
+	}
+
+	tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action;
+}
+
+/**
+ * \brief Disables a TC module event input or output.
+ *
+ * Disables one or more input or output events to or from the TC module.
+ * See \ref tc_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in]  module_inst  Pointer to the software module instance struct
+ * \param[in]  events       Struct containing flags of events to disable
+ */
+static inline void tc_disable_events(
+		struct tc_module *const module_inst,
+		struct tc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Tc *const tc_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	if (events->invert_event_input == true) {
+		event_mask |= TC_EVCTRL_TCINV;
+	}
+
+	if (events->on_event_perform_action == true) {
+		event_mask |= TC_EVCTRL_TCEI;
+	}
+
+	if (events->generate_event_on_overflow == true) {
+		event_mask |= TC_EVCTRL_OVFEO;
+	}
+
+	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+		if (events->generate_event_on_compare_channel[i] == true) {
+			event_mask |= (TC_EVCTRL_MCEO(1) << i);
+		}
+	}
+
+	tc_module->COUNT8.EVCTRL.reg &= ~event_mask;
+}
+
+/** @} */
+
+/**
+ * \name Enable/Disable/Reset
+ * @{
+ */
+
+enum status_code tc_reset(
+		const struct tc_module *const module_inst);
+
+/**
+ * \brief Enable the TC module.
+ *
+ * Enables a TC module that has been previously initialized. The counter will
+ * start when the counter is enabled.
+ *
+ * \note When the counter is configured to re-trigger on an event, the counter
+ *       will not start until the start function is used.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tc_enable(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Enable TC module */
+	tc_module->CTRLA.reg |= TC_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disables the TC module.
+ *
+ * Disables a TC module and stops the counter.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tc_disable(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Disbale interrupt */
+	tc_module->INTENCLR.reg = TC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	tc_module->INTFLAG.reg = TC_INTFLAG_MASK;
+
+	/* Disable TC module */
+	tc_module->CTRLA.reg  &= ~TC_CTRLA_ENABLE;
+}
+
+/** @} */
+
+/**
+ * \name Get/Set Count Value
+ * @{
+ */
+
+uint32_t tc_get_count_value(
+		const struct tc_module *const module_inst);
+
+enum status_code tc_set_count_value(
+		const struct tc_module *const module_inst,
+		const uint32_t count);
+
+/** @} */
+
+/**
+ * \name Start/Stop Counter
+ * @{
+ */
+
+/**
+ * \brief Stops the counter.
+ *
+ * This function will stop the counter. When the counter is stopped
+ * the value in the count value is set to 0 if the counter was
+ * counting up, or maximum if the counter was counting
+ * down when stopped.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tc_stop_counter(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Write command to execute */
+	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_STOP_Val);
+}
+
+/**
+ * \brief Starts the counter.
+ *
+ * Starts or restarts an initialized TC module's counter.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tc_start_counter(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Make certain that there are no conflicting commands in the register */
+	tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Write command to execute */
+	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_RETRIGGER_Val);
+}
+
+/** @} */
+
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+/**
+ * \name Double Buffering
+ * @{
+ */
+
+/**
+ * \brief Update double buffer.
+ *
+ * Update double buffer.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tc_update_double_buffer(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Make certain that there are no conflicting commands in the register */
+	tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Write command to execute */
+	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_UPDATE_Val);
+}
+/** @} */
+#endif
+
+#ifdef FEATURE_TC_READ_SYNC
+/**
+ * \name Count Read Synchronization
+ * @{
+ */
+
+/**
+ * \brief Read synchronization of COUNT.
+ *
+ * Read synchronization of COUNT.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tc_sync_read_count(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Make certain that there are no conflicting commands in the register */
+	tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Write command to execute */
+	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_READSYNC_Val);
+}
+/** @} */
+#endif
+
+#ifdef FEATURE_TC_GENERATE_DMA_TRIGGER
+/**
+ * \name Generate TC DMA Triggers Command
+ * @{
+ */
+
+/**
+ * \brief TC DMA Trigger.
+ *
+ * TC DMA trigger command.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tc_dma_trigger_command(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Make certain that there are no conflicting commands in the register */
+	tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+#if (SAMC20) || (SAMC21) || (SAML22) || (SAML21XXXB) || (SAMR30)
+	/* Write command to execute */
+	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_DMAOS_Val);
+#endif
+}
+/** @} */
+#endif
+
+/**
+ * \name Get Capture Set Compare
+ * @{
+ */
+
+uint32_t tc_get_capture_value(
+		const struct tc_module *const module_inst,
+		const enum tc_compare_capture_channel channel_index);
+
+enum status_code tc_set_compare_value(
+		const struct tc_module *const module_inst,
+		const enum tc_compare_capture_channel channel_index,
+		const uint32_t compare_value);
+
+/** @} */
+
+/**
+ * \name Set Top Value
+ * @{
+ */
+
+enum status_code tc_set_top_value(
+		const struct tc_module *const module_inst,
+		const uint32_t top_value);
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module_inst  Pointer to the TC software instance struct
+ *
+ * \return Bitmask of \c TC_STATUS_* flags.
+ *
+ * \retval TC_STATUS_CHANNEL_0_MATCH   Timer channel 0 compare/capture match
+ * \retval TC_STATUS_CHANNEL_1_MATCH   Timer channel 1 compare/capture match
+ * \retval TC_STATUS_SYNC_READY        Timer read synchronization has completed
+ * \retval TC_STATUS_CAPTURE_OVERFLOW  Timer capture data has overflowed
+ * \retval TC_STATUS_COUNT_OVERFLOW    Timer count value has overflowed
+ * \retval TC_STATUS_CHN0_BUFFER_VALID Timer count channel 0 compare/capture buffer valid
+ * \retval TC_STATUS_CHN1_BUFFER_VALID Timer count channel 1 compare/capture buffer valid
+ * \retval TC_STATUS_PERIOD_BUFFER_VALID Timer count period buffer valid
+ */
+static inline uint32_t tc_get_status(
+		struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	uint32_t int_flags = tc_module->INTFLAG.reg;
+
+	uint32_t status_flags = 0;
+
+	/* Check for TC channel 0 match */
+	if (int_flags & TC_INTFLAG_MC(1)) {
+		status_flags |= TC_STATUS_CHANNEL_0_MATCH;
+	}
+
+	/* Check for TC channel 1 match */
+	if (int_flags & TC_INTFLAG_MC(2)) {
+		status_flags |= TC_STATUS_CHANNEL_1_MATCH;
+	}
+
+#if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2)
+	/* Check for TC read synchronization ready */
+	if (int_flags & TC_INTFLAG_SYNCRDY) {
+		status_flags |= TC_STATUS_SYNC_READY;
+	}
+#endif
+
+	/* Check for TC capture overflow */
+	if (int_flags & TC_INTFLAG_ERR) {
+		status_flags |= TC_STATUS_CAPTURE_OVERFLOW;
+	}
+
+	/* Check for TC count overflow */
+	if (int_flags & TC_INTFLAG_OVF) {
+		status_flags |= TC_STATUS_COUNT_OVERFLOW;
+	}
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+	uint8_t double_buffer_valid_status = tc_module->STATUS.reg;
+
+	/* Check channel 0 compare or capture buffer valid */
+	if (double_buffer_valid_status & TC_STATUS_CCBUFV0) {
+		status_flags |= TC_STATUS_CHN0_BUFFER_VALID;
+	}
+	/* Check channel 0 compare or capture buffer valid */
+	if (double_buffer_valid_status & TC_STATUS_CCBUFV1) {
+		status_flags |= TC_STATUS_CHN1_BUFFER_VALID;
+	}
+	/* Check period buffer valid */
+	if (double_buffer_valid_status & TC_STATUS_PERBUFV) {
+		status_flags |= TC_STATUS_PERIOD_BUFFER_VALID;
+	}
+#endif
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst   Pointer to the TC software instance struct
+ * \param[in] status_flags  Bitmask of \c TC_STATUS_* flags to clear
+ */
+static inline void tc_clear_status(
+		struct tc_module *const module_inst,
+		const uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	uint32_t int_flags = 0;
+
+	/* Check for TC channel 0 match */
+	if (status_flags & TC_STATUS_CHANNEL_0_MATCH) {
+		int_flags |= TC_INTFLAG_MC(1);
+	}
+
+	/* Check for TC channel 1 match */
+	if (status_flags & TC_STATUS_CHANNEL_1_MATCH) {
+		int_flags |= TC_INTFLAG_MC(2);
+	}
+
+#if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2)
+	/* Check for TC read synchronization ready */
+	if (status_flags & TC_STATUS_SYNC_READY) {
+		int_flags |= TC_INTFLAG_SYNCRDY;
+	}
+#endif
+
+	/* Check for TC capture overflow */
+	if (status_flags & TC_STATUS_CAPTURE_OVERFLOW) {
+		int_flags |= TC_INTFLAG_ERR;
+	}
+
+	/* Check for TC count overflow */
+	if (status_flags & TC_STATUS_COUNT_OVERFLOW) {
+		int_flags |= TC_INTFLAG_OVF;
+	}
+
+	/* Clear interrupt flag */
+	tc_module->INTFLAG.reg = int_flags;
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_sam0_tc_extra Extra Information for TC Driver
+ *
+ * \section asfdoc_sam0_tc_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+  *	<tr>
+ *		<td>DMA</td>
+ *		<td>Direct Memory Access</td>
+ *	</tr>
+ *	<tr>
+ *		<td>TC</td>
+ *		<td>Timer Counter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PWM</td>
+ *		<td>Pulse Width Modulation</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PWP</td>
+ *		<td>Pulse Width Period</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PPW</td>
+ *		<td>Period Pulse Width</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_tc_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_tc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_tc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *    <td>Added support for SAM D21 and do some modifications as below:
+ *          \li Clean up in the configuration structure, the counter size
+ *              setting specific registers is accessed through the counter_8_bit,
+ *              counter_16_bit, and counter_32_bit structures
+ *          \li All event related settings moved into the tc_event structure </td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added automatic digital clock interface enable for the slave TC
+ *          module when a timer is initialized in 32-bit mode</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_tc_exqsg Examples for TC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_tc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_tc_basic_use_case
+ *  - \subpage asfdoc_sam0_tc_macth_freq_use_case
+ * \if TC_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_tc_timer_use_case
+ *  - \subpage asfdoc_sam0_tc_callback_use_case
+ * \endif
+ *  - \subpage asfdoc_sam0_tc_dma_use_case
+ *
+ * \page asfdoc_sam0_tc_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42123E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42123D</td>
+ *		<td>12/2014</td>
+ *		<td>Added timer use case.
+ *		    Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42123C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42123B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42123A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* TC_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.c
new file mode 100644
index 0000000000..3a5cf7e45a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.c
@@ -0,0 +1,199 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Callback Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "tc_interrupt.h"
+
+void *_tc_instances[TC_INST_NUM];
+
+void _tc_interrupt_handler(uint8_t instance);
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref tc_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_func Pointer to callback function
+ * \param[in]     callback_type Callback type given by an enum
+ */
+enum status_code tc_register_callback(
+		struct tc_module *const module,
+		tc_callback_t callback_func,
+		const enum tc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+		module->register_callback_mask |= TC_INTFLAG_MC(1);
+	}
+	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+		module->register_callback_mask |= TC_INTFLAG_MC(2);
+	}
+	else {
+		module->register_callback_mask |= (1 << callback_type);
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters a callback function implemented by the user. The callback should be
+ * disabled before it is unregistered.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+enum status_code tc_unregister_callback(
+		struct tc_module *const module,
+		const enum tc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+		module->register_callback_mask &= ~TC_INTFLAG_MC(1);
+	}
+	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+		module->register_callback_mask &= ~TC_INTFLAG_MC(2);
+	}
+	else {
+		module->register_callback_mask &= ~(1 << callback_type);
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \internal ISR handler for TC
+ *
+ * Auto-generate a set of interrupt handlers for each TC in the device.
+ */
+#define _TC_INTERRUPT_HANDLER(n, m) \
+		void TC##n##_Handler(void) \
+		{ \
+			_tc_interrupt_handler(m); \
+		}
+
+#if (SAML21E) || (SAML21G) || (SAMR30E) || (SAMR30G)
+	_TC_INTERRUPT_HANDLER(0,0)
+	_TC_INTERRUPT_HANDLER(1,1)
+	_TC_INTERRUPT_HANDLER(4,2)
+#else
+	MRECURSION(TC_INST_NUM, _TC_INTERRUPT_HANDLER, TC_INST_MAX_ID)
+#endif
+
+
+/**
+ * \internal Interrupt Handler for TC module
+ *
+ * Handles interrupts as they occur, it will run the callback functions
+ * that are registered and enabled.
+ *
+ * \param[in]  instance  ID of the TC instance calling the interrupt
+ *                       handler
+ */
+void _tc_interrupt_handler(
+		uint8_t instance)
+{
+	/* Temporary variable */
+	uint8_t interrupt_and_callback_status_mask;
+
+	/* Get device instance from the look-up table */
+	struct tc_module *module
+			= (struct tc_module *)_tc_instances[instance];
+
+	/* Read and mask interrupt flag register */
+	interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg &
+			module->register_callback_mask &
+			module->enable_callback_mask;
+
+	/* Check if an Overflow interrupt has occurred */
+	if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[TC_CALLBACK_OVERFLOW])(module);
+		/* Clear interrupt flag */
+		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
+	}
+
+	/* Check if an Error interrupt has occurred */
+	if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[TC_CALLBACK_ERROR])(module);
+		/* Clear interrupt flag */
+		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
+	}
+
+	/* Check if an Match/Capture Channel 0 interrupt has occurred */
+	if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1)) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[TC_CALLBACK_CC_CHANNEL0])(module);
+		/* Clear interrupt flag */
+		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1);
+	}
+
+	/* Check if an Match/Capture Channel 1 interrupt has occurred */
+	if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2)) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[TC_CALLBACK_CC_CHANNEL1])(module);
+		/* Clear interrupt flag */
+		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2);
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.h
new file mode 100644
index 0000000000..56c7264ad7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.h
@@ -0,0 +1,179 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Callback Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TC_INTERRUPT_H_INCLUDED
+#define TC_INTERRUPT_H_INCLUDED
+
+#include "tc.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+extern void *_tc_instances[TC_INST_NUM];
+
+#  define _TC_INTERRUPT_VECT_NUM(n, unused) \
+		  SYSTEM_INTERRUPT_MODULE_TC##n,
+/**
+ * \internal Get the interrupt vector for the given device instance
+ *
+ * \param[in] TC module instance number
+ *
+ * \return Interrupt vector for of the given TC module instance.
+ */
+static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector(
+		uint32_t inst_num)
+{
+	static uint8_t tc_interrupt_vectors[TC_INST_NUM] =
+		{
+#if (SAML21E) || (SAML21G) || (SAMR30E) || (SAMR30G)
+			SYSTEM_INTERRUPT_MODULE_TC0,
+			SYSTEM_INTERRUPT_MODULE_TC1,
+			SYSTEM_INTERRUPT_MODULE_TC4
+#else
+			MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID)
+#endif
+		};
+
+	return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num];
+}
+#endif /* !defined(__DOXYGEN__) */
+
+/**
+ * \name Callback Management
+ * {@
+ */
+
+enum status_code tc_register_callback(
+		struct tc_module *const module,
+		tc_callback_t callback_func,
+		const enum tc_callback callback_type);
+
+enum status_code tc_unregister_callback(
+		struct tc_module *const module,
+		const enum tc_callback callback_type);
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback function registered by the \ref
+ * tc_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are
+ * met. This function will also enable the appropriate interrupts.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+static inline void tc_enable_callback(
+		struct tc_module *const module,
+		const enum tc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+
+	/* Enable interrupts for this TC module */
+	system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw)));
+
+	/* Enable callback */
+	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+		module->enable_callback_mask |= TC_INTFLAG_MC(1);
+		module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1);
+	}
+	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+		module->enable_callback_mask |= TC_INTFLAG_MC(2);
+		module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2);
+	}
+	else {
+		module->enable_callback_mask |= (1 << callback_type);
+		module->hw->COUNT8.INTENSET.reg = (1 << callback_type);
+	}
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback function registered by the \ref
+ * tc_register_callback, and the callback will not be called from the
+ * interrupt routine. The function will also disable the appropriate
+ * interrupts.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+static inline void tc_disable_callback(
+		struct tc_module *const module,
+		const enum tc_callback callback_type){
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+		module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1);
+		module->enable_callback_mask &= ~TC_INTFLAG_MC(1);
+	}
+	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+		module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2);
+		module->enable_callback_mask &= ~TC_INTFLAG_MC(2);
+	}
+	else {
+		module->hw->COUNT8.INTENCLR.reg = (1 << callback_type);
+		module->enable_callback_mask &= ~(1 << callback_type);
+	}
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TC_INTERRUPT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_d_r_h/tc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_d_r_h/tc.c
new file mode 100644
index 0000000000..19e721574a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_d_r_h/tc.c
@@ -0,0 +1,685 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "tc.h"
+
+#if TC_ASYNC == true
+#  include "tc_interrupt.h"
+#  include <system_interrupt.h>
+
+/** \internal
+ * Converts a given TC index to its interrupt vector index.
+ */
+#  define _TC_INTERRUPT_VECT_NUM(n, unused) \
+		SYSTEM_INTERRUPT_MODULE_TC##n,
+#endif
+
+#if !defined(__DOXYGEN__)
+#  define _TC_GCLK_ID(n,unused)           TPASTE3(TC,n,_GCLK_ID)   ,
+#  define _TC_PM_APBCMASK(n,unused)       TPASTE2(PM_APBCMASK_TC,n) ,
+
+#  define TC_INST_GCLK_ID          { MRECURSION(TC_INST_NUM, _TC_GCLK_ID, TC_INST_MAX_ID) }
+#  define TC_INST_PM_APBCMASK      { MRECURSION(TC_INST_NUM, _TC_PM_APBCMASK, TC_INST_MAX_ID) }
+
+#endif
+
+/**
+ * \internal Find the index of given TC module instance.
+ *
+ * \param[in] TC module instance pointer
+ *
+ * \return Index of the given TC module instance.
+ */
+uint8_t _tc_get_inst_index(
+		Tc *const hw)
+{
+	/* List of available TC modules. */
+	Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+
+	/* Find index for TC instance. */
+	for (uint32_t i = 0; i < TC_INST_NUM; i++) {
+		if (hw == tc_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given. */
+	Assert(false);
+	return 0;
+}
+
+
+/**
+ * \brief Initializes a hardware TC module instance.
+ *
+ * Enables the clock and initializes the TC module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     hw           Pointer to the TC hardware module
+ * \param[in]     config       Pointer to the TC configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_BUSY         Hardware module was busy when the
+ *                             initialization procedure was attempted
+ * \retval STATUS_INVALID_ARG  An invalid configuration option or argument
+ *                             was supplied
+ * \retval STATUS_ERR_DENIED   Hardware module was already enabled, or the
+ *                             hardware module is configured in 32-bit
+ *                             slave mode
+ */
+enum status_code tc_init(
+		struct tc_module *const module_inst,
+		Tc *const hw,
+		const struct tc_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(hw);
+	Assert(module_inst);
+	Assert(config);
+
+	/* Temporary variable to hold all updates to the CTRLA
+	 * register before they are written to it */
+	uint16_t ctrla_tmp = 0;
+	/* Temporary variable to hold all updates to the CTRLBSET
+	 * register before they are written to it */
+	uint8_t ctrlbset_tmp = 0;
+	/* Temporary variable to hold all updates to the CTRLC
+	 * register before they are written to it */
+	uint8_t ctrlc_tmp = 0;
+	/* Temporary variable to hold TC instance number */
+	uint8_t instance = _tc_get_inst_index(hw);
+
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = TC_INST_GCLK_ID;
+	/* Array of PM APBC mask bit position for different TC instances */
+	uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK;
+
+	struct system_pinmux_config pin_config;
+	struct system_gclk_chan_config gclk_chan_config;
+
+#if TC_ASYNC == true
+	/* Initialize parameters */
+	for (uint8_t i = 0; i < TC_CALLBACK_N; i++) {
+		module_inst->callback[i]        = NULL;
+	}
+	module_inst->register_callback_mask     = 0x00;
+	module_inst->enable_callback_mask       = 0x00;
+
+	/* Register this instance for callbacks*/
+	_tc_instances[instance] = module_inst;
+#endif
+
+	/* Associate the given device instance with the hardware module */
+	module_inst->hw = hw;
+
+#if SAMD09 || SAMD10 || SAMD11 || SAMHA1
+	/* Check if even numbered TC modules are being configured in 32-bit
+	 * counter size. Only odd numbered counters are allowed to be
+	 * configured in 32-bit counter size.
+	 */
+	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+			!((instance + TC_INSTANCE_OFFSET) & 0x01)) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+#else
+	/* Check if odd numbered TC modules are being configured in 32-bit
+	 * counter size. Only even numbered counters are allowed to be
+	 * configured in 32-bit counter size.
+	 */
+	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+			((instance + TC_INSTANCE_OFFSET) & 0x01)) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+#endif
+
+	/* Make the counter size variable in the module_inst struct reflect
+	 * the counter size in the module
+	 */
+	module_inst->counter_size = config->counter_size;
+
+	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) {
+		/* Module is used as a slave */
+		return STATUS_ERR_DENIED;
+	}
+
+	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Set up the TC PWM out pin for channel 0 */
+	if (config->pwm_channel[0].enabled) {
+		system_pinmux_get_config_defaults(&pin_config);
+		pin_config.mux_position = config->pwm_channel[0].pin_mux;
+		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+		system_pinmux_pin_set_config(
+				config->pwm_channel[0].pin_out, &pin_config);
+	}
+
+	/* Set up the TC PWM out pin for channel 1 */
+	if (config->pwm_channel[1].enabled) {
+		system_pinmux_get_config_defaults(&pin_config);
+		pin_config.mux_position = config->pwm_channel[1].pin_mux;
+		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+		system_pinmux_pin_set_config(
+				config->pwm_channel[1].pin_out, &pin_config);
+	}
+
+	/* Enable the user interface clock in the PM */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
+			inst_pm_apbmask[instance]);
+
+	/* Enable the slave counter if counter_size is 32-bit */
+	if ((config->counter_size == TC_COUNTER_SIZE_32BIT))
+	{
+		/* Enable the user interface clock in the PM */
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
+				inst_pm_apbmask[instance + 1]);
+	}
+
+	/* Setup clock for module */
+	system_gclk_chan_get_config_defaults(&gclk_chan_config);
+	gclk_chan_config.source_generator = config->clock_source;
+	system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
+	system_gclk_chan_enable(inst_gclk_id[instance]);
+
+	/* Set ctrla register */
+	ctrla_tmp =
+			(uint32_t)config->counter_size |
+			(uint32_t)config->wave_generation |
+			(uint32_t)config->reload_action |
+			(uint32_t)config->clock_prescaler;
+
+	if (config->run_in_standby) {
+		ctrla_tmp |= TC_CTRLA_RUNSTDBY;
+	}
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.CTRLA.reg = ctrla_tmp;
+
+	/* Set ctrlb register */
+	if (config->oneshot) {
+		ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
+	}
+
+	if (config->count_direction) {
+		ctrlbset_tmp |= TC_CTRLBSET_DIR;
+	}
+
+	/* Clear old ctrlb configuration */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.CTRLBCLR.reg = 0xFF;
+
+	/* Check if we actually need to go into a wait state. */
+	if (ctrlbset_tmp) {
+		while (tc_is_syncing(module_inst)) {
+			/* Wait for sync */
+		}
+		/* Write configuration to register */
+		hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
+	}
+
+	/* Set ctrlc register*/
+	ctrlc_tmp = config->waveform_invert_output;
+	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+		if (config->enable_capture_on_channel[i] == true) {
+			ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i);
+		}
+	}
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.CTRLC.reg = ctrlc_tmp;
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Switch for TC counter size  */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.COUNT.reg =
+					config->counter_8_bit.value;
+
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.PER.reg =
+					config->counter_8_bit.period;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.CC[0].reg =
+					config->counter_8_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.CC[1].reg =
+					config->counter_8_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.COUNT.reg
+				= config->counter_16_bit.value;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.CC[0].reg =
+					config->counter_16_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.CC[1].reg =
+					config->counter_16_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.COUNT.reg
+				= config->counter_32_bit.value;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.CC[0].reg =
+					config->counter_32_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.CC[1].reg =
+					config->counter_32_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+	}
+
+	Assert(false);
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Sets TC module count value.
+ *
+ * Sets the current timer count value of a initialized TC module. The
+ * specified TC module may be started or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ * \param[in] count        New timer count value to set
+ *
+ * \return Status of the count update procedure.
+ *
+ * \retval STATUS_OK               The timer count was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG  An invalid timer counter size was specified
+ */
+enum status_code tc_set_count_value(
+		const struct tc_module *const module_inst,
+		const uint32_t count)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance*/
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Write to based on the TC counter_size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			tc_module->COUNT8.COUNT.reg  = (uint8_t)count;
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			tc_module->COUNT16.COUNT.reg = (uint16_t)count;
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			tc_module->COUNT32.COUNT.reg = (uint32_t)count;
+			return STATUS_OK;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Get TC module count value.
+ *
+ * Retrieves the current count value of a TC module. The specified TC module
+ * may be started or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ *
+ * \return Count value of the specified TC module.
+ */
+uint32_t tc_get_count_value(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read from based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			return (uint32_t)tc_module->COUNT8.COUNT.reg;
+
+		case TC_COUNTER_SIZE_16BIT:
+			return (uint32_t)tc_module->COUNT16.COUNT.reg;
+
+		case TC_COUNTER_SIZE_32BIT:
+			return tc_module->COUNT32.COUNT.reg;
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Gets the TC module capture value.
+ *
+ * Retrieves the capture value in the indicated TC module capture channel.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the Compare Capture channel to read
+ *
+ * \return Capture value stored in the specified timer channel.
+ */
+uint32_t tc_get_capture_value(
+		const struct tc_module *const module_inst,
+		const enum tc_compare_capture_channel channel_index)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read out based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT8.CC[channel_index].reg;
+			}
+
+		case TC_COUNTER_SIZE_16BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT16.CC[channel_index].reg;
+			}
+
+		case TC_COUNTER_SIZE_32BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT32.CC[channel_index].reg;
+			}
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Sets a TC module compare value.
+ *
+ * Writes a compare value to the given TC module compare/capture channel.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the compare channel to write to
+ * \param[in]  compare        New compare value to set
+ *
+ * \return Status of the compare update procedure.
+ *
+ * \retval  STATUS_OK               The compare value was updated successfully
+ * \retval  STATUS_ERR_INVALID_ARG  An invalid channel index was supplied
+ */
+enum status_code tc_set_compare_value(
+		const struct tc_module *const module_inst,
+		const enum tc_compare_capture_channel channel_index,
+		const uint32_t compare)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read out based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				tc_module->COUNT8.CC[channel_index].reg  =
+						(uint8_t)compare;
+				return STATUS_OK;
+			}
+
+		case TC_COUNTER_SIZE_16BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				tc_module->COUNT16.CC[channel_index].reg =
+						(uint16_t)compare;
+				return STATUS_OK;
+			}
+
+		case TC_COUNTER_SIZE_32BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				tc_module->COUNT32.CC[channel_index].reg =
+						(uint32_t)compare;
+				return STATUS_OK;
+			}
+	}
+
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Resets the TC module.
+ *
+ * Resets the TC module, restoring all hardware module registers to their
+ * default values and disabling the module. The TC module will not be
+ * accessible while the reset is being performed.
+ *
+ * \note When resetting a 32-bit counter only the master TC module's instance
+ *       structure should be passed to the function.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ *
+ * \return Status of the procedure.
+ * \retval STATUS_OK                   The module was reset successfully
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  A 32-bit slave TC module was passed to
+ *                                     the function. Only use reset on master
+ *                                     TC
+ */
+enum status_code tc_reset(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments  */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	if (tc_module->STATUS.reg & TC_STATUS_SLAVE) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Disable this module if it is running */
+	if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) {
+		tc_disable(module_inst);
+		while (tc_is_syncing(module_inst)) {
+			/* wait while module is disabling */
+		}
+	}
+
+	/* Reset this TC module */
+	tc_module->CTRLA.reg  |= TC_CTRLA_SWRST;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Set the timer TOP/period value.
+ *
+ * For 8-bit counter size this function writes the top value to the period
+ * register.
+ *
+ * For 16- and 32-bit counter size this function writes the top value to
+ * Capture Compare register 0. The value in this register can not be used for
+ * any other purpose.
+ *
+ * \note This function is designed to be used in PWM or frequency
+ *       match modes only, when the counter is set to 16- or 32-bit counter
+ *       size. In 8-bit counter size it will always be possible to change the
+ *       top value even in normal mode.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  top_value     New timer TOP value to set
+ *
+ * \return Status of the TOP set procedure.
+ *
+ * \retval STATUS_OK              The timer TOP value was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the
+ *                                module instance is invalid
+ */
+enum status_code tc_set_top_value (
+		const struct tc_module *const module_inst,
+		const uint32_t top_value)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(top_value);
+
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			tc_module->COUNT8.PER.reg    = (uint8_t)top_value;
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
+			return STATUS_OK;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/tc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/tc.c
new file mode 100644
index 0000000000..82daf22724
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/tc.c
@@ -0,0 +1,723 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "tc.h"
+
+#if TC_ASYNC == true
+#  include "tc_interrupt.h"
+#  include <system_interrupt.h>
+#endif
+
+/**
+ * \internal Find the index of given TC module instance.
+ *
+ * \param[in] TC module instance pointer
+ *
+ * \return Index of the given TC module instance.
+ */
+uint8_t _tc_get_inst_index(
+		Tc *const hw)
+{
+	/* List of available TC modules. */
+	Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+
+	/* Find index for TC instance. */
+	for (uint32_t i = 0; i < TC_INST_NUM; i++) {
+		if (hw == tc_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given. */
+	Assert(false);
+	return 0;
+}
+
+
+/**
+ * \brief Initializes a hardware TC module instance.
+ *
+ * Enables the clock and initializes the TC module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     hw           Pointer to the TC hardware module
+ * \param[in]     config       Pointer to the TC configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_BUSY         Hardware module was busy when the
+ *                             initialization procedure was attempted
+ * \retval STATUS_INVALID_ARG  An invalid configuration option or argument
+ *                             was supplied
+ * \retval STATUS_ERR_DENIED   Hardware module was already enabled, or the
+ *                             hardware module is configured in 32-bit
+ *                             slave mode
+ */
+enum status_code tc_init(
+		struct tc_module *const module_inst,
+		Tc *const hw,
+		const struct tc_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(hw);
+	Assert(module_inst);
+	Assert(config);
+
+	/* Temporary variable to hold all updates to the CTRLA
+	 * register before they are written to it */
+	uint32_t ctrla_tmp = 0;
+	/* Temporary variable to hold all updates to the CTRLBSET
+	 * register before they are written to it */
+	uint8_t ctrlbset_tmp = 0;
+	/* Temporary variable to hold TC instance number */
+	uint8_t instance = _tc_get_inst_index(hw);
+
+#if (SAMC20) || (SAMC21)
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID};
+	/* Array of MCLK APB mask bit position for different TC instances */
+	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC4};
+#elif (SAML21J)
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID};
+	/* Array of MCLK APB mask bit position for different TC instances */
+	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3,
+									SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4};
+#elif (SAML22)
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID};
+	/* Array of MCLK APB mask bit position for different TC instances */
+	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3};
+#else
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC4_GCLK_ID};
+	/* Array of PM APB mask bit position for different TC instances */
+	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+									SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4};
+#endif
+
+	struct system_pinmux_config pin_config;
+	struct system_gclk_chan_config gclk_chan_config;
+
+#if TC_ASYNC == true
+	/* Initialize parameters */
+	for (uint8_t i = 0; i < TC_CALLBACK_N; i++) {
+		module_inst->callback[i]        = NULL;
+	}
+	module_inst->register_callback_mask     = 0x00;
+	module_inst->enable_callback_mask       = 0x00;
+
+	/* Register this instance for callbacks*/
+	_tc_instances[instance] = module_inst;
+#endif
+
+	/* Associate the given device instance with the hardware module */
+	module_inst->hw = hw;
+
+	module_inst->double_buffering_enabled = config->double_buffering_enabled;
+
+	/* Check if odd numbered TC modules are being configured in 32-bit
+	 * counter size. Only even numbered counters are allowed to be
+	 * configured in 32-bit counter size.
+	 */
+	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+			((instance + TC_INSTANCE_OFFSET) & 0x01)) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Make the counter size variable in the module_inst struct reflect
+	 * the counter size in the module
+	 */
+	module_inst->counter_size = config->counter_size;
+
+	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) {
+		/* Module is used as a slave */
+		return STATUS_ERR_DENIED;
+	}
+
+	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Set up the TC PWM out pin for channel 0 */
+	if (config->pwm_channel[0].enabled) {
+		system_pinmux_get_config_defaults(&pin_config);
+		pin_config.mux_position = config->pwm_channel[0].pin_mux;
+		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+		system_pinmux_pin_set_config(
+				config->pwm_channel[0].pin_out, &pin_config);
+	}
+
+	/* Set up the TC PWM out pin for channel 1 */
+	if (config->pwm_channel[1].enabled) {
+		system_pinmux_get_config_defaults(&pin_config);
+		pin_config.mux_position = config->pwm_channel[1].pin_mux;
+		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+		system_pinmux_pin_set_config(
+				config->pwm_channel[1].pin_out, &pin_config);
+	}
+
+	/* Enable the user interface clock in the MCLK */
+	system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[instance*2],
+			inst_mclk_apbmask[2*instance+1]);
+
+	/* Enable the slave counter if counter_size is 32-bit */
+	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && (instance+1 < TC_INST_NUM))
+	{
+		/* Enable the user interface clock in the MCLK */
+		system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[(instance+1)*2],
+				inst_mclk_apbmask[(instance+1)*2+1]);
+	}
+
+
+	/* Setup clock for module */
+	system_gclk_chan_get_config_defaults(&gclk_chan_config);
+	gclk_chan_config.source_generator = config->clock_source;
+	system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
+	system_gclk_chan_enable(inst_gclk_id[instance]);
+
+	/* Set ctrla register */
+	ctrla_tmp =
+			(uint32_t)config->counter_size |
+			(uint32_t)config->reload_action |
+			(uint32_t)config->clock_prescaler;
+
+	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+		if (config->enable_capture_on_channel[i] == true) {
+			ctrla_tmp |= (TC_CTRLA_CAPTEN(1) << i);
+		}
+	}
+
+	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+		if (config->enable_capture_on_IO[i] == true) {
+			ctrla_tmp |= (TC_CTRLA_COPEN(1) << i);
+		}
+	}
+
+	ctrla_tmp |= (config->run_in_standby << TC_CTRLA_RUNSTDBY_Pos)
+				|(config->on_demand << TC_CTRLA_ONDEMAND_Pos);
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.CTRLA.reg = ctrla_tmp;
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.WAVE.reg = config->wave_generation;
+
+	/* Set ctrlb register */
+	if (config->oneshot) {
+		ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
+	}
+
+	if (config->count_direction) {
+		ctrlbset_tmp |= TC_CTRLBSET_DIR;
+	}
+
+	/* Clear old ctrlb configuration */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.CTRLBCLR.reg = 0xFF;
+
+	/* Check if we actually need to go into a wait state. */
+	if (ctrlbset_tmp) {
+		while (tc_is_syncing(module_inst)) {
+			/* Wait for sync */
+		}
+		/* Write configuration to register */
+		hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
+	}
+
+	/* Set drvvtrl register*/
+	hw->COUNT8.DRVCTRL.reg = config->waveform_invert_output;
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Switch for TC counter size  */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.COUNT.reg =
+					config->counter_8_bit.value;
+
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.PER.reg =
+					config->counter_8_bit.period;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.CC[0].reg =
+					config->counter_8_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.CC[1].reg =
+					config->counter_8_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.COUNT.reg
+				= config->counter_16_bit.value;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.CC[0].reg =
+					config->counter_16_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.CC[1].reg =
+					config->counter_16_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.COUNT.reg
+				= config->counter_32_bit.value;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.CC[0].reg =
+					config->counter_32_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.CC[1].reg =
+					config->counter_32_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+	}
+
+	Assert(false);
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Sets TC module count value.
+ *
+ * Sets the current timer count value of a initialized TC module. The
+ * specified TC module may be started or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ * \param[in] count        New timer count value to set
+ *
+ * \return Status of the count update procedure.
+ *
+ * \retval STATUS_OK               The timer count was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG  An invalid timer counter size was specified
+ */
+enum status_code tc_set_count_value(
+		const struct tc_module *const module_inst,
+		const uint32_t count)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance*/
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Write to based on the TC counter_size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			tc_module->COUNT8.COUNT.reg  = (uint8_t)count;
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			tc_module->COUNT16.COUNT.reg = (uint16_t)count;
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			tc_module->COUNT32.COUNT.reg = (uint32_t)count;
+			return STATUS_OK;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Get TC module count value.
+ *
+ * Retrieves the current count value of a TC module. The specified TC module
+ * may be started or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ *
+ * \return Count value of the specified TC module.
+ */
+uint32_t tc_get_count_value(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Read synchronization */
+	tc_sync_read_count(module_inst);
+	
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read from based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			return (uint32_t)tc_module->COUNT8.COUNT.reg;
+
+		case TC_COUNTER_SIZE_16BIT:
+			return (uint32_t)tc_module->COUNT16.COUNT.reg;
+
+		case TC_COUNTER_SIZE_32BIT:
+			return tc_module->COUNT32.COUNT.reg;
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Gets the TC module capture value.
+ *
+ * Retrieves the capture value in the indicated TC module capture channel.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the Compare Capture channel to read
+ *
+ * \return Capture value stored in the specified timer channel.
+ */
+uint32_t tc_get_capture_value(
+		const struct tc_module *const module_inst,
+		const enum tc_compare_capture_channel channel_index)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read out based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT8.CC[channel_index].reg;
+			}
+
+		case TC_COUNTER_SIZE_16BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT16.CC[channel_index].reg;
+			}
+
+		case TC_COUNTER_SIZE_32BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT32.CC[channel_index].reg;
+			}
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Sets a TC module compare value.
+ *
+ * Writes a compare value to the given TC module compare/capture channel.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the compare channel to write to
+ * \param[in]  compare        New compare value to set
+ *
+ * \return Status of the compare update procedure.
+ *
+ * \retval  STATUS_OK               The compare value was updated successfully
+ * \retval  STATUS_ERR_INVALID_ARG  An invalid channel index was supplied
+ */
+enum status_code tc_set_compare_value(
+		const struct tc_module *const module_inst,
+		const enum tc_compare_capture_channel channel_index,
+		const uint32_t compare)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(compare);
+
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read out based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				if (module_inst->double_buffering_enabled){
+					tc_module->COUNT8.CCBUF[channel_index].reg =
+							(uint8_t)compare;
+				} else {
+					tc_module->COUNT8.CC[channel_index].reg  =
+							(uint8_t)compare;
+				}
+				return STATUS_OK;
+			}
+		case TC_COUNTER_SIZE_16BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				if (module_inst->double_buffering_enabled){
+					tc_module->COUNT16.CCBUF[channel_index].reg =
+							(uint16_t)compare;
+				} else {
+					tc_module->COUNT16.CC[channel_index].reg =
+							(uint16_t)compare;
+				}
+				return STATUS_OK;
+			}
+
+		case TC_COUNTER_SIZE_32BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				if (module_inst->double_buffering_enabled){
+					tc_module->COUNT32.CCBUF[channel_index].reg =
+							(uint32_t)compare;
+				} else {
+					tc_module->COUNT32.CC[channel_index].reg =
+						(uint32_t)compare;
+				}
+				return STATUS_OK;
+			}
+	}
+
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Resets the TC module.
+ *
+ * Resets the TC module, restoring all hardware module registers to their
+ * default values and disabling the module. The TC module will not be
+ * accessible while the reset is being performed.
+ *
+ * \note When resetting a 32-bit counter only the master TC module's instance
+ *       structure should be passed to the function.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ *
+ * \return Status of the procedure.
+ * \retval STATUS_OK                   The module was reset successfully
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  A 32-bit slave TC module was passed to
+ *                                     the function. Only use reset on master
+ *                                     TC
+ */
+enum status_code tc_reset(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments  */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	if (tc_module->STATUS.reg & TC_STATUS_SLAVE) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Disable this module if it is running */
+	if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) {
+		tc_disable(module_inst);
+		while (tc_is_syncing(module_inst)) {
+			/* wait while module is disabling */
+		}
+	}
+
+	/* Reset this TC module */
+	tc_module->CTRLA.reg  |= TC_CTRLA_SWRST;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Set the timer TOP/period value.
+ *
+ * For 8-bit counter size this function writes the top value to the period
+ * register.
+ *
+ * For 16- and 32-bit counter size this function writes the top value to
+ * Capture Compare register 0. The value in this register can not be used for
+ * any other purpose.
+ *
+ * \note This function is designed to be used in PWM or frequency
+ *       match modes only, when the counter is set to 16- or 32-bit counter
+ *       size. In 8-bit counter size it will always be possible to change the
+ *       top value even in normal mode.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  top_value     New timer TOP value to set
+ *
+ * \return Status of the TOP set procedure.
+ *
+ * \retval STATUS_OK              The timer TOP value was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the
+ *                                module instance is invalid
+ */
+enum status_code tc_set_top_value (
+		const struct tc_module *const module_inst,
+		const uint32_t top_value)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(top_value);
+
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			if (module_inst->double_buffering_enabled){
+				tc_module->COUNT8.PERBUF.reg = (uint8_t)top_value;
+			} else {
+				tc_module->COUNT8.PER.reg = (uint8_t)top_value;
+			}
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			if (module_inst->double_buffering_enabled){
+				tc_module->COUNT16.CCBUF[0].reg = (uint16_t)top_value;
+			} else {
+				tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
+			}
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			if (module_inst->double_buffering_enabled){
+				tc_module->COUNT32.CCBUF[0].reg = (uint32_t)top_value;
+			} else {
+				tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
+			}
+			return STATUS_OK;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.c
new file mode 100644
index 0000000000..64cffc461d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.c
@@ -0,0 +1,1608 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC - Timer Counter for Control Applications Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "tcc.h"
+
+#if TCC_ASYNC == true
+#  include "tcc_callback.h"
+#  include <system_interrupt.h>
+
+/** \internal
+ * Converts a given TCC index to its interrupt vector index.
+ */
+#  define _TCC_INTERRUPT_VECT_NUM(n, unused) \
+		SYSTEM_INTERRUPT_MODULE_TCC##n,
+#endif
+
+#define _SIZE_MAX(size) ((size==32u) ? 0xFFFFFFFF : ( \
+		(1u << size) - 1))
+
+#define _SIZE_MAX_WITH_DITHER 0x03FFFFFF
+
+/* Extension support mapping bits */
+#define _TCC_DITHERING_B 16u
+#define _TCC_PG_B         8u
+#define _TCC_SWAP_B       4u
+#define _TCC_DTI_B        2u
+#define _TCC_OTMX_B       1u
+
+#if !defined(__DOXYGEN__)
+
+#  define _TCC_GCLK_ID(n,unused)           TPASTE3(TCC,n,_GCLK_ID),
+#  if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+#    define _TCC_APBCMASK(n,unused)        TPASTE2(MCLK_APBCMASK_TCC,n),
+#  else
+#    define _TCC_APBCMASK(n,unused)        TPASTE2(PM_APBCMASK_TCC,n),
+#  endif
+
+#  define _TCC_SIZE(n,unused)              TPASTE3(TCC,n,_SIZE),
+#  define _TCC_MAX(n,unused)               _SIZE_MAX(TPASTE3(TCC,n,_SIZE)),
+#  define _TCC_EXT(n,unused)               TPASTE3(TCC,n,_EXT),
+#  define _TCC_CC_NUM(n,unused)            min(TPASTE3(TCC,n,_CC_NUM),TCC_NUM_CHANNELS),
+#  define _TCC_OW_NUM(n,unused)            min(TPASTE3(TCC,n,_OW_NUM),TCC_NUM_WAVE_OUTPUTS),
+
+#  define TCC_GCLK_IDS      { MREPEAT(TCC_INST_NUM, _TCC_GCLK_ID, 0) }
+#  define TCC_APBCMASKS     { MREPEAT(TCC_INST_NUM, _TCC_APBCMASK, 0) }
+
+#  define TCC_SIZES         { MREPEAT(TCC_INST_NUM, _TCC_SIZE, 0) }
+#  define TCC_MAXS          { MREPEAT(TCC_INST_NUM, _TCC_MAX, 0) }
+#  define TCC_EXTS          { MREPEAT(TCC_INST_NUM, _TCC_EXT, 0) }
+#  define TCC_CC_NUMS       { MREPEAT(TCC_INST_NUM, _TCC_CC_NUM, 0) }
+#  define TCC_OW_NUMS       { MREPEAT(TCC_INST_NUM, _TCC_OW_NUM, 0) }
+
+#endif
+
+/* List of available TCC modules. */
+const Tcc *const tcc_modules[TCC_INST_NUM] = TCC_INSTS;
+
+/* List of TCC GCLK IDs */
+const uint8_t _tcc_gclk_ids[TCC_INST_NUM] = TCC_GCLK_IDS;
+
+/* List of TCC APBC Masks */
+const uint32_t _tcc_apbcmasks[TCC_INST_NUM] = TCC_APBCMASKS;
+
+/* List of extension support of TCC modules. */
+const uint8_t _tcc_exts[TCC_INST_NUM] = TCC_EXTS;
+
+/* List of sizes support of TCC modules. */
+const uint8_t _tcc_sizes[TCC_INST_NUM] = TCC_SIZES;
+
+/* List of maximumvalues supported of TCC modules. */
+const uint32_t _tcc_maxs[TCC_INST_NUM] = TCC_MAXS;
+
+/* List of available channel number of TCC modules. */
+const uint8_t _tcc_cc_nums[TCC_INST_NUM] = TCC_CC_NUMS;
+
+/* List of available output number of TCC modules. */
+const uint8_t _tcc_ow_nums[TCC_INST_NUM] = TCC_OW_NUMS;
+
+/**
+ * \internal Find the index of the given TCC module instance.
+ *
+ * \param[in] The TCC module instance pointer
+ *
+ * \return Index of the given TCC module instance.
+ */
+uint8_t _tcc_get_inst_index(
+		Tcc *const hw)
+{
+	/* Find index for TCC instance. */
+	for (uint32_t i = 0; i < TCC_INST_NUM; i++) {
+		if (hw == tcc_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given. */
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given TCC configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structures before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Don't run in standby
+ *  \li When setting top, compare, or pattern by API, do double buffering write
+ *  \li The base timer/counter configurations:
+ *     - GCLK generator 0 clock source
+ *     - No prescaler
+ *     - GCLK reload action
+ *     - Count upward
+ *     - Don't perform one-shot operations
+ *     - Counter starts on 0
+ *     - Period/top value set to maximum
+ *  \li The match/capture configurations:
+ *     - All Capture compare channel value set to 0
+ *     - No capture enabled (all channels use compare function)
+ *     - Normal frequency wave generation
+ *     - Waveform generation polarity set to 0
+ *     - Don't perform ramp on waveform
+ *  \li The waveform extension configurations:
+ *     - No recoverable fault is enabled, fault actions are disabled, filter
+ *          is set to 0
+ *     - No non-recoverable fault state output is enabled and filter is 0
+ *     - No inversion of waveform output
+ *  \li No channel output enabled
+ *  \li No PWM pin output enabled
+ *  \li Pin and MUX configuration not set
+ *
+ * \param[out]  config  Pointer to a TCC module configuration structure to set
+ * \param[in]   hw      Pointer to the TCC hardware module
+ *
+ */
+void tcc_get_config_defaults(
+		struct tcc_config *const config,
+		Tcc *const hw)
+{
+	/* TCC instance index */
+	uint8_t module_index = _tcc_get_inst_index(hw);
+
+	/* Base counter defaults */
+	config->counter.count                  = 0;
+
+	config->counter.period                 = _tcc_maxs[module_index];
+
+	config->counter.clock_source           = GCLK_GENERATOR_0;
+	config->counter.clock_prescaler        = TCC_CLOCK_PRESCALER_DIV1;
+	config->counter.reload_action          = TCC_RELOAD_ACTION_GCLK;
+
+	config->counter.direction              = TCC_COUNT_DIRECTION_UP;
+	config->counter.oneshot                = false;
+
+#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER
+	config->counter.dma_trigger_mode       = TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_CONTINUE;
+#endif
+
+	/* Match/Capture defaults */
+#  define _TCC_CHANNEL_MATCH_VALUE_INIT(n, value) \
+		config->compare.match[n] = value;
+	MREPEAT(TCC_NUM_CHANNELS,
+		_TCC_CHANNEL_MATCH_VALUE_INIT, 0)
+#  undef _TCC_CHANNEL_MATCH_VALUE_INIT
+
+	/* Wave polarity defaults */
+#  define _TCC_CHANNEL_WAVE_POLARITY_INIT(n, value) \
+		config->compare.wave_polarity[n] = value;
+	MREPEAT(TCC_NUM_CHANNELS,
+		_TCC_CHANNEL_WAVE_POLARITY_INIT, TCC_WAVE_POLARITY_0)
+#  undef _TCC_CHANNEL_WAVE_POLARITY_INIT
+
+	config->compare.wave_generation = TCC_WAVE_GENERATION_NORMAL_FREQ;
+	config->compare.wave_ramp       = TCC_RAMP_RAMP1;
+
+#  define _TCC_CHANNEL_FUNCTION_INIT(n, value) \
+		config->compare.channel_function[n] = value;
+	MREPEAT(TCC_NUM_CHANNELS,
+			_TCC_CHANNEL_FUNCTION_INIT, TCC_CHANNEL_FUNCTION_COMPARE)
+#  undef _TCC_CHANNEL_FUNCTION_INIT
+
+	/* Recoverable fault defaults */
+#  define _TCC_FAULT_FUNCTION_INIT(n, dummy) \
+		config->wave_ext.recoverable_fault[n].filter_value = 0;      \
+		config->wave_ext.recoverable_fault[n].blanking_cycles = 0;   \
+		config->wave_ext.recoverable_fault[n].restart = false;       \
+		config->wave_ext.recoverable_fault[n].keep = false;          \
+		config->wave_ext.recoverable_fault[n].qualification = false; \
+		config->wave_ext.recoverable_fault[n].source = TCC_FAULT_SOURCE_DISABLE;           \
+		config->wave_ext.recoverable_fault[n].blanking = TCC_FAULT_BLANKING_DISABLE;       \
+		config->wave_ext.recoverable_fault[n].halt_action = TCC_FAULT_HALT_ACTION_DISABLE; \
+		config->wave_ext.recoverable_fault[n].capture_action = TCC_FAULT_CAPTURE_DISABLE;  \
+		config->wave_ext.recoverable_fault[n].capture_channel = TCC_FAULT_CAPTURE_CHANNEL_0;
+	MREPEAT(TCC_NUM_FAULTS, _TCC_FAULT_FUNCTION_INIT, 0)
+#  undef _TCC_FAULT_FUNCTION_INIT
+
+	/* Non-recoverable fault defaults */
+#  define _TCC_NRF_FUNCTION_INIT(n, dummy) \
+		config->wave_ext.non_recoverable_fault[n].filter_value = 0; \
+		config->wave_ext.non_recoverable_fault[n].output = TCC_FAULT_STATE_OUTPUT_OFF;
+	MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_NRF_FUNCTION_INIT, 0)
+#  undef _TCC_NRF_FUNCTION_INIT
+
+	/* Output inversion defaults */
+#  define _TCC_OUT_INVERT_INIT(n, value) \
+		config->wave_ext.invert[n] = value;
+	MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_OUT_INVERT_INIT, false)
+#  undef _TCC_OUT_INVERT_INIT
+
+#  define _TCC_CHANNEL_OUT_PIN_INIT(n, dummy) \
+		config->pins.enable_wave_out_pin[n]                = false;\
+		config->pins.wave_out_pin[TCC_WAVE_OUTPUT_##n]     = 0;    \
+		config->pins.wave_out_pin_mux[TCC_WAVE_OUTPUT_##n] = 0;
+	MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_CHANNEL_OUT_PIN_INIT, 0)
+#  undef _TCC_CHANNEL_OUT_PIN_INIT
+
+	config->double_buffering_enabled  = true;
+	config->run_in_standby            = false;
+}
+
+
+/**
+ * \brief Build CTRLA register value from configuration.
+ *
+ * \param[in]  module_index The software module instance index
+ * \param[in]  config       Pointer to the TCC configuration options struct
+ * \param[out] value_buffer Pointer to the buffer to fill with built value
+ *
+ * \return Configuration validation status.
+ *
+ * \retval STATUS_OK              Configuration values are good and register
+ *                                value built and save to buffer
+ * \retval STATUS_ERR_INVALID_ARG Invalid parameter found:
+ *                                assigned dither mode is invalid for module;
+ *                                used capture channel is invalid for module
+ */
+static inline enum status_code _tcc_build_ctrla(
+		const uint8_t module_index,
+		const struct tcc_config *const config,
+		uint32_t *value_buffer)
+{
+	uint32_t ctrla = 0;
+
+	int i;
+	for (i = 0; i < TCC_NUM_CHANNELS; i ++) {
+		if (config->capture.channel_function[i] ==
+			TCC_CHANNEL_FUNCTION_CAPTURE) {
+
+			if (i > _tcc_cc_nums[module_index]) {
+				/* Channel not supported */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			ctrla |= (TCC_CTRLA_CPTEN0 << i);
+		}
+	}
+
+	if (config->run_in_standby) {
+		ctrla |= TCC_CTRLA_RUNSTDBY;
+	}
+	ctrla |= config->counter.reload_action << TCC_CTRLA_PRESCSYNC_Pos;
+	ctrla |= config->counter.clock_prescaler << TCC_CTRLA_PRESCALER_Pos;
+
+	*value_buffer = ctrla;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Build CTRLB register value from configuration.
+ *
+ * \param[in]  module_index The software module instance index
+ * \param[in]  config       Pointer to the TCC configuration options struct
+ * \param[out] value_buffer Pointer to the buffer to fill with built value
+ */
+static inline void _tcc_build_ctrlb(
+		const uint8_t module_index,
+		const struct tcc_config *const config,
+		uint8_t *value_buffer)
+{
+	uint8_t ctrlb = 0;
+
+	if (config->counter.oneshot) {
+		ctrlb |= TCC_CTRLBSET_ONESHOT;
+	}
+	if (config->counter.direction == TCC_COUNT_DIRECTION_DOWN) {
+		ctrlb |= TCC_CTRLBSET_DIR;
+	}
+
+	*value_buffer = ctrlb;
+}
+
+/**
+ * \brief Build FAULTs register values from configuration.
+ *
+ * \param[in]  module_index The software module instance index
+ * \param[in]  config       Pointer to the TCC configuration options struct
+ * \param[out] value_buffer Pointer to the buffer to fill with built values
+ *
+ * \retval STATUS_OK              Configuration values are good and register
+ *                                value built and save to buffer
+ * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned fault
+ *                                capture channel is invalid; assigned filter
+ *                                value is invalid
+ */
+static inline enum status_code _tcc_build_faults(
+		const uint8_t module_index,
+		const struct tcc_config *const config,
+		uint32_t *value_buffer)
+{
+	struct tcc_recoverable_fault_config *cfg;
+	uint8_t cc_num = _tcc_cc_nums[module_index];
+	uint32_t fault;
+	int i;
+	for (i = 0; i < TCC_NUM_FAULTS; i ++) {
+		cfg = (struct tcc_recoverable_fault_config *)
+				&config->wave_ext.recoverable_fault[i];
+		if (cfg->capture_channel >= cc_num) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		if (cfg->filter_value > 0xF) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+		fault = TCC_FCTRLA_FILTERVAL(cfg->filter_value)
+				| TCC_FCTRLA_BLANKVAL(cfg->blanking_cycles)
+				| (cfg->restart ? TCC_FCTRLA_RESTART : 0)
+				| (cfg->keep ? TCC_FCTRLA_KEEP : 0)
+				| (cfg->qualification ? TCC_FCTRLA_QUAL : 0)
+				| TCC_FCTRLA_SRC(cfg->source)
+				| TCC_FCTRLA_BLANK(cfg->blanking)
+				| TCC_FCTRLA_HALT(cfg->halt_action)
+				| TCC_FCTRLA_CAPTURE(cfg->capture_action)
+				| TCC_FCTRLA_CHSEL(cfg->capture_channel);
+		value_buffer[i] = fault;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Build DRVCTRL register values from configuration.
+ *
+ * \param[in]  module_index The software module instance index
+ * \param[in]  config       Pointer to the TCC configuration options struct
+ * \param[out] value_buffer Pointer to the buffer to fill with built value
+ *
+ * \retval STATUS_OK              Configuration values are good and register
+ *                                value built and save to buffer
+ * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned output line
+ *                                is invalid; filter value is invalid
+ */
+static inline enum status_code _tcc_build_drvctrl(
+		const uint8_t module_index,
+		const struct tcc_config *const config,
+		uint32_t *value_buffer)
+{
+	uint32_t i;
+	uint8_t ow_num = _tcc_ow_nums[module_index];
+	uint32_t drvctrl;
+
+	drvctrl = 0;
+
+	for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) {
+		if (config->wave_ext.invert[i]) {
+			if (i >= ow_num) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+			drvctrl |= (TCC_DRVCTRL_INVEN0 << i);
+		}
+		if (config->wave_ext.non_recoverable_fault[i].output !=
+			TCC_FAULT_STATE_OUTPUT_OFF) {
+			if (i >= ow_num) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+			if (config->wave_ext.non_recoverable_fault[i].output ==
+				TCC_FAULT_STATE_OUTPUT_1) {
+				drvctrl |= (TCC_DRVCTRL_NRE0 | TCC_DRVCTRL_NRV0) << i;
+			} else {
+				drvctrl |= (TCC_DRVCTRL_NRE0) << i;
+			}
+		}
+	}
+	*value_buffer = drvctrl;
+	return STATUS_OK;
+}
+
+/**
+ * \brief Build WAVE & WAVEB register values from configuration.
+ *
+ * \param[in]  module_index The software module instance index
+ * \param[in]  config       Pointer to the TCC configuration options struct
+ * \param[out] value_buffer Pointer to the buffer to fill with built value
+ *
+ * \retval STATUS_OK              Configuration values are good and register
+ *                                value built and save to buffer
+ * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned output line
+ *                                is invalid; circular and double buffering
+ *                                conflict; assigned function not supported by
+ *                                module
+ */
+static inline enum status_code _tcc_build_waves(
+		const uint8_t module_index,
+		const struct tcc_config *const config,
+		uint32_t *value_buffer)
+{
+	int n;
+
+	uint8_t cc_num = _tcc_cc_nums[module_index];
+	struct tcc_match_wave_config const *wav_cfg = &config->compare;
+
+	uint32_t wave;
+
+	wave = TCC_WAVE_RAMP(wav_cfg->wave_ramp) |
+			TCC_WAVE_WAVEGEN(wav_cfg->wave_generation);
+
+	for (n = 0; n < TCC_NUM_CHANNELS; n++) {
+		if (wav_cfg->wave_polarity[n]) {
+			if (n >= cc_num) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+			wave |= (TCC_WAVE_POL0 << n);
+		}
+	}
+
+	value_buffer[0] = wave;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes a hardware TCC module instance.
+ *
+ * Enables the clock and initializes the given TCC module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     hw           Pointer to the TCC hardware module
+ * \param[in]     config       Pointer to the TCC configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_BUSY         The hardware module was busy when the
+ *                             initialization procedure was attempted
+ * \retval STATUS_INVALID_ARG  An invalid configuration option or argument
+ *                             was supplied
+ * \retval STATUS_ERR_DENIED   The hardware module was already enabled
+ */
+enum status_code tcc_init(
+		struct tcc_module *const module_inst,
+		Tcc *const hw,
+		const struct tcc_config *const config)
+{
+	int i;
+
+	/* Sanity check arguments */
+	Assert(hw);
+	Assert(module_inst);
+	Assert(config);
+
+	/* TCC instance index */
+	uint8_t module_index = _tcc_get_inst_index(hw);
+
+	/* Enable the user interface clock for TCC */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
+			_tcc_apbcmasks[module_index]);
+
+	/* Check if it's enabled. */
+	if (hw->CTRLA.reg & TCC_CTRLA_ENABLE) {
+		return STATUS_ERR_DENIED;
+	}
+	/* Check if it's resetting */
+	if (hw->CTRLA.reg & TCC_CTRLA_SWRST) {
+		return STATUS_ERR_DENIED;
+	}
+
+	enum status_code status;
+
+	/* Check COUNT, PER, CCx */
+	uint32_t count_max  = _tcc_maxs[module_index];
+
+	/* Check all counter values */
+	if ((config->counter.count > count_max)
+		|| (config->counter.period > count_max)
+		) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check all channel values */
+	for (i = 0; i < TCC_NUM_CHANNELS; i ++) {
+		if ((config->compare.match[i] > count_max)
+			) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+	}
+
+	/* Check all outputs */
+	for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) {
+		if (!config->pins.enable_wave_out_pin[i]) {
+			continue;
+		}
+		/* Output line is not supported */
+		if (i >= _tcc_ow_nums[module_index]) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+	}
+
+	/* CTRLA settings */
+	uint32_t ctrla = 0;
+	status = _tcc_build_ctrla(module_index, config, &ctrla);
+	if (STATUS_OK != status) {
+		return status;
+	}
+
+	/* CTRLB settings */
+	uint8_t ctrlb;
+	_tcc_build_ctrlb(module_index, config, &ctrlb);
+
+	/* FAULTs settings */
+	uint32_t faults[TCC_NUM_FAULTS];
+
+	status = _tcc_build_faults(module_index, config, faults);
+	if (STATUS_OK != status) {
+		return status;
+	}
+
+	/* DRVCTRL */
+	uint32_t drvctrl = 0;
+
+	status = _tcc_build_drvctrl(module_index, config, &drvctrl);
+	if (STATUS_OK != status) {
+		return status;
+	}
+
+	/* WAVE */
+	uint32_t waves[1];
+
+	status = _tcc_build_waves(module_index, config, waves);
+	if (STATUS_OK != status) {
+		return status;
+	}
+
+	/* Initialize module */
+#if TCC_ASYNC
+	/* Initialize parameters */
+	for (i = 0; i < TCC_CALLBACK_N; i ++) {
+		module_inst->callback[i] = NULL;
+	}
+	module_inst->register_callback_mask = 0;
+	module_inst->enable_callback_mask = 0;
+	_tcc_instances[module_index] = module_inst;
+#endif
+
+	module_inst->hw = hw;
+
+	module_inst->double_buffering_enabled = config->double_buffering_enabled;
+
+	/* Setup clock for module */
+	struct system_gclk_chan_config gclk_chan_config;
+	system_gclk_chan_get_config_defaults(&gclk_chan_config);
+	gclk_chan_config.source_generator = config->counter.clock_source;
+	system_gclk_chan_set_config(_tcc_gclk_ids[module_index], &gclk_chan_config);
+	system_gclk_chan_enable(_tcc_gclk_ids[module_index]);
+
+	/* Initialize pins */
+	struct system_pinmux_config pin_config;
+	for (i = 0; i <  _tcc_ow_nums[module_index]; i ++) {
+		if (!config->pins.enable_wave_out_pin[i]) {
+			continue;
+		}
+
+		system_pinmux_get_config_defaults(&pin_config);
+		pin_config.mux_position = config->pins.wave_out_pin_mux[i];
+		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+		system_pinmux_pin_set_config(
+				config->pins.wave_out_pin[i], &pin_config);
+	}
+
+	/* Write to registers */
+
+	hw->CTRLA.reg = ctrla;
+	while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+		/* Wait for sync */
+	}
+
+	hw->CTRLBCLR.reg = 0xFF;
+	while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+		/* Wait for sync */
+	}
+	hw->CTRLBSET.reg = ctrlb;
+
+	hw->FCTRLA.reg = faults[0];
+	hw->FCTRLB.reg = faults[1];
+
+	hw->DRVCTRL.reg = drvctrl;
+
+#if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30)
+	while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_WAVE | TCC_SYNCBUSY_WAVEB)) {
+		/* Wait for sync */
+	}
+#endif
+	hw->WAVE.reg = waves[0];
+
+	while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) {
+		/* Wait for sync */
+	}
+	hw->COUNT.reg = config->counter.count;
+
+#if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30)
+	while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_PER | TCC_SYNCBUSY_PERB)) {
+		/* Wait for sync */
+	}
+#endif
+	hw->PER.reg = (config->counter.period);
+
+	for (i = 0; i <  _tcc_cc_nums[module_index]; i ++) {
+#if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30)
+		while (hw->SYNCBUSY.reg & (
+			(TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CCB0) << i)) {
+			/* Wait for sync */
+		}
+#endif
+		hw->CC[i].reg = (config->compare.match[i]);
+	}
+
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Enables the TCC module event input or output.
+ *
+ * Enables one or more input or output events to or from the TCC module.
+ * See \ref tcc_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in]  module_inst  Pointer to the software module instance struct
+ * \param[in]  events       Struct containing flags of events to enable or
+ *                          configure
+ *
+ * \return Status of the events setup procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_INVALID_ARG  An invalid configuration option or argument
+ *                             was supplied
+ */
+enum status_code tcc_enable_events(
+		struct tcc_module *const module_inst,
+		struct tcc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Tcc *const tcc_module = module_inst->hw;
+
+	/* Check if it's enabled or resetting. */
+	if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	uint32_t evctrl = tcc_module->EVCTRL.reg;
+
+	/* Setup event output action */
+	if (events->output_config.modify_generation_selection) {
+		evctrl &= ~ TCC_EVCTRL_CNTSEL_Msk;
+		switch(events->output_config.generation_selection) {
+		case TCC_EVENT_GENERATION_SELECTION_START:
+			evctrl |= TCC_EVCTRL_CNTSEL_START;
+			break;
+		case TCC_EVENT_GENERATION_SELECTION_END:
+			evctrl |= TCC_EVCTRL_CNTSEL_END;
+			break;
+		case TCC_EVENT_GENERATION_SELECTION_BETWEEN:
+			evctrl |= TCC_EVCTRL_CNTSEL_BETWEEN;
+			break;
+		case TCC_EVENT_GENERATION_SELECTION_BOUNDARY:
+			evctrl |= TCC_EVCTRL_CNTSEL_BOUNDARY;
+			break;
+		default:
+			Assert(false);
+			/* Wrong configuration */
+			return STATUS_ERR_INVALID_ARG;
+		}
+	}
+	/* Setup input event0 */
+	if (events->on_input_event_perform_action[0]) {
+		evctrl |= TCC_EVCTRL_TCEI0;
+	}
+	if (events->input_config[0].invert) {
+		evctrl |= TCC_EVCTRL_TCINV0;
+	}
+	if (events->input_config[0].modify_action) {
+		evctrl &= ~ TCC_EVCTRL_EVACT0_Msk;
+		switch(events->input_config[0].action) {
+		case TCC_EVENT0_ACTION_OFF:
+			evctrl |= TCC_EVCTRL_EVACT0_OFF;
+			break;
+		case TCC_EVENT0_ACTION_RETRIGGER:
+			evctrl |= TCC_EVCTRL_EVACT0_RETRIGGER;
+			break;
+		case TCC_EVENT0_ACTION_COUNT_EVENT:
+			evctrl |= TCC_EVCTRL_EVACT0_COUNTEV;
+			break;
+		case TCC_EVENT0_ACTION_START:
+			evctrl |= TCC_EVCTRL_EVACT0_START;
+			break;
+		case TCC_EVENT0_ACTION_INCREMENT:
+			evctrl |= TCC_EVCTRL_EVACT0_INC;
+			break;
+		case TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE:
+			evctrl |= TCC_EVCTRL_EVACT0_COUNT;
+			break;
+		case TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT:
+			evctrl |= TCC_EVCTRL_EVACT0_FAULT;
+			break;
+		default:
+			Assert(false);
+			/* Wrong configuration */
+			return STATUS_ERR_INVALID_ARG;
+		}
+	}
+	/* Setup input event1 */
+	if (events->on_input_event_perform_action[1]) {
+		evctrl |= TCC_EVCTRL_TCEI1;
+	}
+	if (events->input_config[1].invert) {
+		evctrl |= TCC_EVCTRL_TCINV1;
+	}
+	if (events->input_config[1].modify_action) {
+		evctrl &= ~ TCC_EVCTRL_EVACT1_Msk;
+		switch(events->input_config[1].action) {
+		case TCC_EVENT1_ACTION_OFF:
+			evctrl |= TCC_EVCTRL_EVACT1_OFF;
+			break;
+		case TCC_EVENT1_ACTION_RETRIGGER:
+			evctrl |= TCC_EVCTRL_EVACT1_RETRIGGER;
+			break;
+		case TCC_EVENT1_ACTION_DIR_CONTROL:
+			evctrl |= TCC_EVCTRL_EVACT1_DIR;
+			break;
+		case TCC_EVENT1_ACTION_STOP:
+			evctrl |= TCC_EVCTRL_EVACT1_STOP;
+			break;
+		case TCC_EVENT1_ACTION_DECREMENT:
+			evctrl |= TCC_EVCTRL_EVACT1_DEC;
+			break;
+		case TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE:
+			evctrl |= TCC_EVCTRL_EVACT1_PPW |
+					TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1;
+			break;
+		case TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE:
+			evctrl |= TCC_EVCTRL_EVACT1_PWP |
+					TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1;
+			break;
+		case TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT:
+			evctrl |= TCC_EVCTRL_EVACT1_FAULT;
+			break;
+		default:
+			Assert(false);
+			/* Wrong configuration */
+			return STATUS_ERR_INVALID_ARG;
+		}
+	}
+	uint32_t ch;
+	for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) {
+		if (events->generate_event_on_channel[ch]) {
+			evctrl |= (TCC_EVCTRL_MCEO(1) << ch);
+		}
+		if (events->on_event_perform_channel_action[ch]) {
+			evctrl |= (TCC_EVCTRL_MCEI(1) << ch);
+		}
+	}
+	if (events->generate_event_on_counter_overflow) {
+		evctrl |= TCC_EVCTRL_OVFEO;
+	}
+	if (events->generate_event_on_counter_retrigger) {
+		evctrl |= TCC_EVCTRL_TRGEO;
+	}
+	if (events->generate_event_on_counter_event) {
+		evctrl |= TCC_EVCTRL_CNTEO;
+	}
+
+	tcc_module->EVCTRL.reg = evctrl;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables the event input or output of a TCC instance.
+ *
+ * Disables one or more input or output events for the given TCC module.
+ * See \ref tcc_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in]  module_inst  Pointer to the software module instance struct
+ * \param[in]  events       Struct containing flags of events to disable
+ */
+void tcc_disable_events(
+		struct tcc_module *const module_inst,
+		struct tcc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Tcc *const tcc_module = module_inst->hw;
+
+	/* Check if it's enabled or resetting. */
+	if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) {
+		return;
+	}
+
+
+	uint32_t evctrl = 0;
+	uint32_t ch;
+	for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) {
+		if (events->generate_event_on_channel[ch]) {
+			evctrl |= (TCC_EVCTRL_MCEO(1) << ch);
+		}
+		if (events->on_event_perform_channel_action[ch]) {
+			evctrl |= (TCC_EVCTRL_MCEI(1) << ch);
+		}
+	}
+	if (events->generate_event_on_counter_overflow) {
+		evctrl |= TCC_EVCTRL_OVFEO;
+	}
+	if (events->generate_event_on_counter_retrigger) {
+		evctrl |= TCC_EVCTRL_TRGEO;
+	}
+	if (events->generate_event_on_counter_event) {
+		evctrl |= TCC_EVCTRL_CNTEO;
+	}
+	if (events->on_input_event_perform_action[0]) {
+		evctrl |= TCC_EVCTRL_TCEI0;
+	}
+	if (events->on_input_event_perform_action[1]) {
+		evctrl |= TCC_EVCTRL_TCEI1;
+	}
+	if (events->input_config[0].invert) {
+		evctrl |= TCC_EVCTRL_TCINV0;
+	}
+	if (events->input_config[1].invert) {
+		evctrl |= TCC_EVCTRL_TCINV1;
+	}
+
+	tcc_module->EVCTRL.reg &= ~evctrl;
+}
+
+
+
+/**
+ * \brief Sets count value for the given TCC module.
+ *
+ * Sets the timer count value of an initialized TCC module. The
+ * specified TCC module can remain running or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ * \param[in] count        New timer count value to set
+ *
+ * \return Status which indicates whether the new value is set.
+ *
+ * \retval STATUS_OK               The timer count was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG  An invalid timer counter size was specified
+ */
+enum status_code tcc_set_count_value(
+		const struct tcc_module *const module_inst,
+		const uint32_t count)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance*/
+	Tcc *const tcc_module = module_inst->hw;
+	/* Get a index of the module */
+	uint8_t module_index = _tcc_get_inst_index(tcc_module);
+
+	uint32_t max_count = _tcc_maxs[module_index];
+
+	if (count > max_count) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) {
+		/* Wait for sync */
+	}
+
+	/* Write to based on the TCC dithering */
+	tcc_module->COUNT.reg = (count);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get count value of the given TCC module.
+ *
+ * Retrieves the current count value of a TCC module. The specified TCC module
+ * can remain running or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ *
+ * \return Count value of the specified TCC module.
+ */
+uint32_t tcc_get_count_value(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance*/
+	Tcc *const tcc_module = module_inst->hw;
+	uint32_t last_cmd;
+
+	/* Wait last command done */
+	do {
+		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+			/* Wait for sync */
+		}
+		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
+		if (TCC_CTRLBSET_CMD_NONE == last_cmd) {
+			/* Issue read command and break */
+			tcc_module->CTRLBSET.bit.CMD = TCC_CTRLBSET_CMD_READSYNC_Val;
+			while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+				/* Wait for sync */
+			}
+			break;
+		} else if (TCC_CTRLBSET_CMD_READSYNC == last_cmd) {
+			/* Command have been issued */
+			break;
+		}
+	} while (1);
+
+	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) {
+		/* Wait for sync */
+	}
+	return (tcc_module->COUNT.reg);
+}
+
+
+
+/**
+ * \brief Gets the TCC module capture value.
+ *
+ * Retrieves the capture value in the indicated TCC module capture channel.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the Compare Capture channel to read
+ *
+ * \return Capture value stored in the specified timer channel.
+ */
+uint32_t tcc_get_capture_value(
+		const struct tcc_module *const module_inst,
+		const enum tcc_match_capture_channel channel_index)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Assert(channel_index < _tcc_cc_nums[_tcc_get_inst_index(module_inst->hw)]);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+
+	while(tcc_module->SYNCBUSY.reg  & (TCC_SYNCBUSY_CC0 << channel_index)) {
+		/* Sync wait */
+	}
+
+	return tcc_module->CC[channel_index].reg;
+}
+
+/**
+ * \internal
+ * \brief Sets a TCC module compare value/buffer.
+ *
+ * Writes a compare value to the given TCC module compare/capture channel or
+ * buffer one.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the compare channel to write to
+ * \param[in]  compare        New compare value/buffer value to set
+ * \param[in]  double_buffering_enabled Set to \c true to write to CCBx
+ *
+ * \return Status of the compare update procedure.
+ *
+ * \retval  STATUS_OK               The compare value was updated successfully
+ * \retval  STATUS_ERR_INVALID_ARG  An invalid channel index was supplied or
+ *                                  compare value exceed resolution
+ */
+static enum status_code _tcc_set_compare_value(
+		const struct tcc_module *const module_inst,
+		const enum tcc_match_capture_channel channel_index,
+		const uint32_t compare,
+		const bool double_buffering_enabled)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	/* Get a index of the module */
+	uint8_t module_index = _tcc_get_inst_index(tcc_module);
+
+	/* Check index */
+	if (channel_index >= _tcc_cc_nums[module_index]) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	uint32_t max_count = _tcc_maxs[module_index];
+
+	/* Check compare value */
+	if (compare > max_count) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (double_buffering_enabled) {
+#if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30)
+		tcc_module->CCBUF[channel_index].reg = compare;
+#else
+		while(tcc_module->STATUS.reg  &
+				(TCC_STATUS_CCBV0 << channel_index)) {
+			/* Valid check */
+		}
+		while(tcc_module->SYNCBUSY.reg  &
+				(TCC_SYNCBUSY_CCB0 << channel_index)) {
+			/* Sync wait */
+		}
+		tcc_module->CCB[channel_index].reg = compare;
+#endif
+	} else {
+		while(tcc_module->SYNCBUSY.reg  & (TCC_SYNCBUSY_CC0 << channel_index)) {
+			/* Sync wait */
+		}
+		tcc_module->CC[channel_index].reg = compare;
+	}
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Sets a TCC module compare value.
+ *
+ * Writes a compare value to the given TCC module compare/capture channel.
+ *
+ * If double buffering is enabled it always write to the buffer
+ * register. The value will then be updated immediately by calling
+ * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit
+ * is cleared and the UPDATE condition happen.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the compare channel to write to
+ * \param[in]  compare        New compare value to set
+ *
+ * \return Status of the compare update procedure.
+ *
+ * \retval  STATUS_OK               The compare value was updated successfully
+ * \retval  STATUS_ERR_INVALID_ARG  An invalid channel index was supplied or
+ *                                  compare value exceed resolution
+ */
+enum status_code tcc_set_compare_value(
+		const struct tcc_module *const module_inst,
+		const enum tcc_match_capture_channel channel_index,
+		const uint32_t compare)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	return _tcc_set_compare_value(module_inst, channel_index, compare,
+			module_inst->double_buffering_enabled);
+}
+
+/**
+ * \brief Sets a TCC module compare value and buffer value.
+ *
+ * Writes compare value and buffer to the given TCC module compare/capture
+ * channel. Usually as preparation for double buffer or circulared double buffer
+ * (circular buffer).
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the compare channel to write to
+ * \param[in]  compare        New compare value to set
+ * \param[in]  compare_buffer New compare buffer value to set
+ *
+ * \return Status of the compare update procedure.
+ *
+ * \retval  STATUS_OK               The compare value was updated successfully
+ * \retval  STATUS_ERR_INVALID_ARG  An invalid channel index was supplied or
+ *                                  compare value exceed resolution
+ */
+enum status_code tcc_set_double_buffer_compare_values(
+		struct tcc_module *const module_inst,
+		const enum tcc_match_capture_channel channel_index,
+		const uint32_t compare, const uint32_t compare_buffer)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	enum status_code status;
+	status = _tcc_set_compare_value(module_inst, channel_index, compare, false);
+	if (status != STATUS_OK) {
+		return status;
+	}
+	return _tcc_set_compare_value(module_inst, channel_index, compare_buffer,
+			true);
+}
+
+
+/**
+ * \internal
+ * \brief Set the timer TOP/PERIOD buffer/value.
+ *
+ * This function writes the given value to the PER/PERB register.
+ *
+ * \param[in] module_inst   Pointer to the software module instance struct
+ * \param[in] top_value     New value to be loaded into the PER/PERB register
+ * \param[in] double_buffering_enabled Set to \c true to write to PERB
+ *
+ * \return Status of the TOP set procedure.
+ *
+ * \retval STATUS_OK              The timer TOP value was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or
+ *                                top/period value exceed resolution
+ */
+static enum status_code _tcc_set_top_value(
+		const struct tcc_module *const module_inst,
+		const uint32_t top_value,
+		const bool double_buffering_enabled)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	/* Get a index of the module */
+	uint8_t module_index = _tcc_get_inst_index(tcc_module);
+
+	uint32_t max_count = _tcc_maxs[module_index];
+
+	/* Check compare value */
+	if (top_value > max_count) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (double_buffering_enabled) {
+#if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30)
+		tcc_module->PERBUF.reg = top_value;
+#else
+		while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PERB) {
+			/* Sync wait */
+		}
+		tcc_module->PERB.reg = top_value;
+#endif
+	} else {
+		while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PER) {
+			/* Sync wait */
+		}
+		tcc_module->PER.reg = top_value;
+	}
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Set the timer TOP/PERIOD value.
+ *
+ * This function writes the given value to the PER/PERB register.
+ *
+ * If double buffering is enabled it always write to the buffer
+ * register (PERB). The value will then be updated immediately by calling
+ * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit
+ * is cleared and the UPDATE condition happen.
+ *
+ * When using MFRQ, the top value is defined by the CC0 register value and the
+ * PER value is ignored, so
+ * \ref tcc_set_compare_value (module,channel_0,value) must be used instead of
+ * this function to change the actual top value in that case.
+ * For all other waveforms operation the top value is defined by PER register
+ * value.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  top_value     New value to be loaded into the PER/PERB register
+ *
+ * \return Status of the TOP set procedure.
+ *
+ * \retval STATUS_OK              The timer TOP value was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or
+ *                                top/period value exceed resolution
+ */
+enum status_code tcc_set_top_value(
+		const struct tcc_module *const module_inst,
+		const uint32_t top_value)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	return _tcc_set_top_value(module_inst, top_value,
+			module_inst->double_buffering_enabled);
+}
+
+/**
+ * \brief Set the timer TOP/PERIOD value and buffer value.
+ *
+ * This function writes the given value to the PER and PERB register. Usually as
+ * preparation for double buffer or circulared double buffer (circular buffer).
+ *
+ * When using MFRQ, the top values are defined by the CC0 and CCB0, the PER and
+ * PERB values are ignored, so
+ * \ref tcc_set_double_buffer_compare_values (module,channel_0,value,buffer) must
+ * be used instead of this function to change the actual top values in that
+ * case. For all other waveforms operation the top values are defined by PER and
+ * PERB registers values.
+ *
+ * \param[in]  module_inst      Pointer to the software module instance struct
+ * \param[in]  top_value        New value to be loaded into the PER register
+ * \param[in]  top_buffer_value New value to be loaded into the PERB register
+ *
+ * \return Status of the TOP set procedure.
+ *
+ * \retval STATUS_OK              The timer TOP value was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or
+ *                                top/period value exceed resolution
+ */
+enum status_code tcc_set_double_buffer_top_values(
+		const struct tcc_module *const module_inst,
+		const uint32_t top_value, const uint32_t top_buffer_value)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	enum status_code status;
+	status = _tcc_set_top_value(module_inst, top_value, false);
+	if (status != STATUS_OK) {
+		return status;
+	}
+	return _tcc_set_top_value(module_inst, top_buffer_value, true);
+}
+
+
+/**
+ * \brief Sets the TCC module waveform output pattern.
+ *
+ * Force waveform output line to generate specific pattern (0, 1, or as is).
+ *
+ * If double buffering is enabled it always write to the buffer
+ * register. The value will then be updated immediately by calling
+ * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit
+ * is cleared and the UPDATE condition happen.
+ *
+ * \param[in]  module_inst Pointer to the software module instance struct
+ * \param[in]  line_index  Output line index
+ * \param[in]  pattern     Output pattern to use (\ref tcc_output_pattern)
+ *
+ * \return Status of the pattern set procedure.
+ *
+ * \retval  STATUS_OK               The PATT register is updated successfully
+ * \retval  STATUS_ERR_INVALID_ARG  An invalid line index was supplied
+ */
+enum status_code tcc_set_pattern(
+		const struct tcc_module *const module_inst,
+		const uint32_t line_index,
+		const enum tcc_output_pattern pattern)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	/* Get a index of the module */
+	uint8_t module_index = _tcc_get_inst_index(tcc_module);
+	/* Get number of output lines */
+	uint8_t ow_num = _tcc_ow_nums[module_index];
+
+	/* Check if line number is OK */
+	if (line_index >= ow_num) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	uint32_t patt_value;
+
+	while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PATT) {
+		/* Sync wait */
+	}
+	patt_value = tcc_module->PATT.reg;
+	if (TCC_OUTPUT_PATTERN_DISABLE == pattern) {
+		patt_value &= ~(TCC_PATT_PGE0 << line_index);
+	} else if (TCC_OUTPUT_PATTERN_0 == pattern) {
+		patt_value &= ~(TCC_PATT_PGV0 << line_index);
+		patt_value |=  (TCC_PATT_PGE0 << line_index);
+	} else {
+		patt_value |=  ((TCC_PATT_PGE0 | TCC_PATT_PGV0) << line_index);
+	}
+
+	if (module_inst->double_buffering_enabled) {
+#if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30)
+		tcc_module->PATTBUF.reg = patt_value;
+#else
+		while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PATTB) {
+			/* Sync wait */
+		}
+		tcc_module->PATTB.reg = patt_value;
+#endif
+	} else {
+		tcc_module->PATT.reg = patt_value;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module_inst  Pointer to the TCC software instance struct
+ *
+ * \return Bitmask of \c TCC_STATUS_* flags.
+ *
+ * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n)         Channel n match/capture has occured
+ * \retval TCC_STATUS_CHANNEL_OUTPUT(n)                Channel n match/capture output state
+ * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x)   Non-recoverable fault x has occured
+ * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n)       Recoverable fault n has occured
+ * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) Non-recoverable fault x input present
+ * \retval TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n)     Recoverable fault n input present
+ * \retval TCC_STATUS_SYNC_READY          None of register is syncing
+ * \retval TCC_STATUS_CAPTURE_OVERFLOW    Timer capture data has overflowed
+ * \retval TCC_STATUS_COUNTER_EVENT       Timer counter event has occurred
+ * \retval TCC_STATUS_COUNT_OVERFLOW      Timer count value has overflowed
+ * \retval TCC_STATUS_COUNTER_RETRIGGERED Timer counter has been retriggered
+ * \retval TCC_STATUS_STOP                Timer counter has been stopped
+ * \retval TCC_STATUS_RAMP_CYCLE_INDEX    Wave ramp index for cycle
+ */
+uint32_t tcc_get_status(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint32_t int_flags = module_inst->hw->INTFLAG.reg;
+	uint32_t status_flags = module_inst->hw->STATUS.reg;
+	uint32_t status = 0;
+	int i;
+
+	/* SYNC */
+	if (module_inst->hw->SYNCBUSY.reg == 0) {
+		status |= TCC_STATUS_SYNC_READY;
+	}
+
+	/* Channels */
+	for (i = 0; i < TCC_NUM_CHANNELS; i++) {
+		if (int_flags & TCC_INTFLAG_MC(i)) {
+			status |= TCC_STATUS_CHANNEL_MATCH_CAPTURE(i);
+		}
+		if (status_flags & TCC_STATUS_CMP(i)) {
+			status |= TCC_STATUS_CHANNEL_OUTPUT(i);
+		}
+	}
+	/* Non-recoverable fault state */
+	if ((int_flags & TCC_INTFLAG_FAULT1) ||
+		(status_flags & TCC_STATUS_FAULT1)) {
+		status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1);
+	}
+	if ((int_flags & TCC_INTFLAG_FAULT0) ||
+		(status_flags & TCC_STATUS_FAULT0)) {
+		status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0);
+	}
+	/* Non-recoverable fault inputs */
+	if (status_flags & TCC_STATUS_FAULT0IN) {
+		status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(0);
+	}
+	if (status_flags & TCC_STATUS_FAULT1IN) {
+		status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(1);
+	}
+	/* Recoverable fault state */
+	if ((int_flags & TCC_INTFLAG_FAULTB) ||
+		(status_flags & TCC_STATUS_FAULTB)) {
+		status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1);
+	}
+	if ((int_flags & TCC_INTFLAG_FAULTA) ||
+		(status_flags & TCC_STATUS_FAULTA)) {
+		status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0);
+	}
+	/* Recoverable fault inputs */
+	if (status_flags & TCC_STATUS_FAULTAIN) {
+		status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(0);
+	}
+	if (status_flags & TCC_STATUS_FAULTBIN) {
+		status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(1);
+	}
+
+	/* Check for TCC capture overflow */
+	if (int_flags & TCC_INTFLAG_ERR) {
+		status |= TCC_STATUS_CAPTURE_OVERFLOW;
+	}
+	/* Check for TCC count counter */
+	if (int_flags & TCC_INTFLAG_CNT) {
+		status |= TCC_STATUS_COUNTER_EVENT;
+	}
+	/* Check for TCC count retrigger */
+	if (int_flags & TCC_INTFLAG_TRG) {
+		status |= TCC_STATUS_COUNTER_RETRIGGERED;
+	}
+	/* Check for TCC count overflow */
+	if (int_flags & TCC_INTFLAG_OVF) {
+		status |= TCC_STATUS_COUNT_OVERFLOW;
+	}
+	/* Check for TCC count stop */
+	if (status_flags & TCC_STATUS_STOP) {
+		status |= TCC_STATUS_STOPPED;
+	}
+	/* Check for TCC RAMP index */
+	if (status_flags & TCC_STATUS_IDX) {
+		status |= TCC_STATUS_RAMP_CYCLE_INDEX;
+	}
+	return status;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst   Pointer to the TCC software instance struct
+ * \param[in] status_flags  Bitmask of \c TCC_STATUS_* flags to clear
+ */
+void tcc_clear_status(
+		struct tcc_module *const module_inst,
+		const uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint32_t int_clr = 0;
+	uint32_t status_clr = 0;
+	int i;
+
+	/* Channels */
+	for (i = 0; i < TCC_NUM_CHANNELS; i++) {
+		if (status_flags & TCC_STATUS_CHANNEL_MATCH_CAPTURE(i)) {
+			int_clr |= TCC_INTFLAG_MC(i);
+		}
+	}
+	/* Faults */
+	if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1)) {
+		int_clr |= TCC_INTFLAG_FAULT1;
+		status_clr |= TCC_STATUS_FAULT1;
+	}
+	if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0)) {
+		int_clr |= TCC_INTFLAG_FAULT0;
+		status_clr |= TCC_STATUS_FAULT0;
+	}
+	if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1)) {
+		int_clr |= TCC_INTFLAG_FAULTB;
+		status_clr |= TCC_STATUS_FAULTB;
+	}
+	if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0)) {
+		int_clr |= TCC_INTFLAG_FAULTA;
+		status_clr |= TCC_STATUS_FAULTA;
+	}
+	/* Check for TCC capture overflow */
+	if (status_flags & TCC_STATUS_CAPTURE_OVERFLOW) {
+		int_clr |= TCC_INTFLAG_ERR;
+	}
+	/* Check for TCC count counter */
+	if (status_flags & TCC_STATUS_COUNTER_EVENT) {
+		int_clr |= TCC_INTFLAG_CNT;
+	}
+	/* Check for TCC count retrigger */
+	if (status_flags & TCC_STATUS_COUNTER_RETRIGGERED) {
+		int_clr = TCC_INTFLAG_TRG;
+	}
+	/* Check for TCC count overflow */
+	if (status_flags & TCC_STATUS_COUNT_OVERFLOW) {
+		int_clr |= TCC_INTFLAG_OVF;
+	}
+	/* Clear status flag */
+	module_inst->hw->STATUS.reg = status_clr;
+	/* Clear interrupt flag */
+	module_inst->hw->INTFLAG.reg = int_clr;
+}
+
+/**
+ * \brief Enable circular option for double buffered compare values.
+ *
+ * Enable circular option for the double buffered channel compare values.
+ * On each UPDATE condition, the contents of CCBx and CCx are switched, meaning
+ * that the contents of CCBx are transferred to CCx and the contents of CCx are
+ * transferred to CCBx.
+ *
+ * \param[in] module_inst     Pointer to the TCC software instance struct
+ * \param[in] channel_index   Index of the compare channel to set up to
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_INVALID_ARG  An invalid channel index is supplied
+ */
+enum status_code tcc_enable_circular_buffer_compare(
+		struct tcc_module *const module_inst,
+		enum tcc_match_capture_channel channel_index)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	/* Get a index of the module */
+	uint8_t module_index = _tcc_get_inst_index(tcc_module);
+
+	/* Check index */
+	if (channel_index > 3) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+	if (channel_index >= _tcc_cc_nums[module_index]) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	tcc_module->WAVE.reg |=  (TCC_WAVE_CICCEN0 << channel_index);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disable circular option for double buffered compare values.
+ *
+ * Stop circularing the double buffered compare values.
+ *
+ * \param[in] module_inst     Pointer to the TCC software instance struct
+ * \param[in] channel_index   Index of the compare channel to set up to
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_INVALID_ARG  An invalid channel index is supplied
+ */
+enum status_code tcc_disable_circular_buffer_compare(
+		struct tcc_module *const module_inst,
+		enum tcc_match_capture_channel channel_index)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	/* Get a index of the module */
+	uint8_t module_index = _tcc_get_inst_index(tcc_module);
+
+	/* Check index */
+	if (channel_index > 3) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+	if (channel_index >= _tcc_cc_nums[module_index]) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	tcc_module->WAVE.reg &= ~(TCC_WAVE_CICCEN0 << channel_index);
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.h
new file mode 100644
index 0000000000..4c2daa6ac5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.h
@@ -0,0 +1,2495 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC - Timer Counter for Control Applications Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TCC_H_INCLUDED
+#define TCC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_tcc_group SAM Timer Counter for Control Applications (TCC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the TCC module within the device, for waveform
+ * generation and timing operations. It also provides extended options for
+ * control applications.
+ *
+ * The following driver API modes are covered
+ * by this manual:
+ *
+ *  - Polled APIs
+ * \if TCC_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - TCC (Timer/Counter for Control Applications)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_tcc_prerequisites
+ *  - \ref asfdoc_sam0_tcc_module_overview
+ *  - \ref asfdoc_sam0_tcc_special_considerations
+ *  - \ref asfdoc_sam0_tcc_extra_info
+ *  - \ref asfdoc_sam0_tcc_examples
+ *  - \ref asfdoc_sam0_tcc_api_overview
+ *
+ * \section asfdoc_sam0_tcc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ * \section asfdoc_sam0_tcc_module_overview Module Overview
+ *
+ * The Timer/Counter for Control Applications (TCC) module provides a set of
+ * timing and counting related functionality, such as the generation of periodic
+ * waveforms, the capturing of a periodic waveform's frequency/duty cycle,
+ * software timekeeping for periodic operations, waveform extension control,
+ * fault detection etc.
+ *
+ * The counter size of the TCC modules can be 16- or 24-bit depending on
+ * the TCC instance.
+ * Refer \ref asfdoc_sam0_tcc_special_considerations_tcc_d21 and
+ * \ref asfdoc_sam0_tcc_special_considerations_tcc_d11 for details on TCC instances.
+ *
+ * The TCC module for the SAM includes the following functions:
+ *
+ * - Generation of PWM signals
+ * - Generation of timestamps for events
+ * - General time counting
+ * - Waveform period capture
+ * - Waveform frequency capture
+ * - Additional control for generated waveform outputs
+ * - Fault protection for waveform generation
+ *
+ * \ref asfdoc_sam0_tcc_block_diagram "The diagram below" shows the overview
+ * of the TCC Module.
+ *
+ * \anchor asfdoc_sam0_tcc_block_diagram
+ * \image html overview.svg "Overview of the TCC Module"
+ *
+ * \subsection asfdoc_sam0_tcc_module_overview_parts Functional Description
+ * The TCC module consists of following sections:
+ * - Base Counter
+ * - Compare/Capture channels, with waveform generation
+ * - Waveform extension control and fault detection
+ * - Interface to the event system, DMAC, and the interrupt system
+ *
+ * The base counter can be configured to either count a prescaled generic
+ * clock or events from the event system.(TCEx, with event action configured
+ * to counting).
+ * The counter value can be used by compare/capture channels which can be
+ * set up either in compare mode or capture mode.
+ *
+ * In capture mode, the counter value is stored when a configurable event
+ * occurs. This mode can be used to generate timestamps used in event capture,
+ * or it can be used for the measurement of a periodic input signal's
+ * frequency/duty cycle.
+ *
+ * In compare mode, the counter value is compared against one or more of the
+ * configured channels' compare values. When the counter value coincides with a
+ * compare value an action can be taken automatically by the module, such as
+ * generating an output event or toggling a pin when used for frequency or PWM
+ * signal generation.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * In compare mode, when output signal is generated, extended waveform controls
+ * are available, to arrange the compare outputs into specific formats.
+ * The Output matrix can change the channel output routing. Pattern generation
+ * unit can overwrite the output signal line to specific state.
+ * The Fault protection feature of the TCC supports recoverable and
+ * non-recoverable faults.
+ *
+ * \subsection asfdoc_sam0_tcc_module_overview_tc Base Timer/Counter
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_tc_size Timer/Counter Size
+ * Each TCC has a counter size of either 16- or 24-bits. The size of the
+ * counter determines the maximum value it can count to before an overflow
+ * occurs.
+ * \ref asfdoc_sam0_tcc_count_size_vs_top "The table below" shows the
+ * maximum values for each of the possible counter sizes.
+ *
+ * \anchor asfdoc_sam0_tcc_count_size_vs_top
+ * <table>
+ *  <caption>Timer Counter Sizes and Their Maximum Count Values</caption>
+ *  <tr>
+ *    <th>Counter size</th>
+ *    <th>Max. (hexadecimal)</th>
+ *    <th>Max. (decimal)</th>
+ *  </tr>
+ *  <tr>
+ *    <td>16-bit</td>
+ *    <td>0xFFFF</td>
+ *    <td>65,535</td>
+ *  </tr>
+ *  <tr>
+ *    <td>24-bit</td>
+ *    <td>0xFFFFFF</td>
+ *    <td>16,777,215</td>
+ *  </tr>
+ * </table>
+ *
+ * The period/top value of the counter can be set, to define counting period.
+ * This will allow the counter to overflow when the counter value reaches the
+ * period/top value.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_tc_clk Timer/Counter Clock and Prescaler
+ * TCC is clocked asynchronously to the system clock by a GCLK
+ * (Generic Clock) channel. The GCLK channel can be connected to any of the GCLK
+ * generators. The GCLK generators are configured to use one of the available
+ * clock sources in the system such as internal oscillator, external crystals,
+ * etc. See the \ref asfdoc_sam0_system_clock_group "Generic Clock driver" for
+ * more information.
+ *
+ * Each TCC module in the SAM has its own individual clock prescaler, which
+ * can be used to divide the input clock frequency used by the counter. This
+ * prescaler only scales the clock used to provide clock pulses for the counter
+ * to count, and does not affect the digital register interface portion of
+ * the module, thus the timer registers will be synchronized to the raw GCLK
+ * frequency input to the module.
+ *
+ * As a result of this, when selecting a GCLK frequency and timer prescaler
+ * value, the user application should consider both the timer resolution
+ * required and the synchronization frequency to avoid lengthy
+ * synchronization times of the module if a very slow GCLK frequency is fed
+ * into the TCC module. It is preferable to use a higher module GCLK frequency
+ * as the input to the timer, and prescale this down as much as possible to
+ * obtain a suitable counter frequency in latency-sensitive applications.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_tc_ctrl Timer/Counter Control Inputs (Events)
+ *
+ * The TCC can take several actions on the occurrence of an input event.
+ * The event actions are listed
+ * in \ref asfdoc_sam0_tcc_module_event_act "events action settings".
+ *
+ * \anchor asfdoc_sam0_tcc_module_event_act
+ * <table>
+ *   <caption>TCC Module Event Actions</caption>
+ *   <tr>
+ *     <th>Event action</th>
+ *     <th>Description</th>
+ *     <th>Applied event</th>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_OFF</td>
+ *     <td>No action on the event input</td>
+ *     <td>All</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_RETRIGGER</td>
+ *     <td>Re-trigger Counter on event</td>
+ *     <td>All</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT</td>
+ *     <td>Generate Non-Recoverable Fault on event</td>
+ *     <td>All</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_START</td>
+ *     <td>Counter start on event</td>
+ *     <td>EV0</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_DIR_CONTROL</td>
+ *     <td>Counter direction control</td>
+ *     <td>EV0</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_DECREMENT</td>
+ *     <td>Counter decrement on event</td>
+ *     <td>EV0</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE</td>
+ *     <td>Capture pulse period and pulse width</td>
+ *     <td>EV0</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE</td>
+ *     <td>Capture pulse width and pulse period</td>
+ *     <td>EV0</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_STOP</td>
+ *     <td>Counter stop on event</td>
+ *     <td>EV1</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_COUNT_EVENT</td>
+ *     <td>Counter count on event</td>
+ *     <td>EV1</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_INCREMENT</td>
+ *     <td>Counter increment on event</td>
+ *     <td>EV1</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_EVENT_ACTION_COUNT_DURING_ACTIVE</td>
+ *     <td>Counter count during active state of asynchronous event</td>
+ *     <td>EV1</td>
+ *   </tr>
+ * </table>
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_tc_reload Timer/Counter Reloading
+ *
+ * The TCC also has a configurable reload action, used when a
+ * re-trigger event occurs. Examples of a re-trigger event could be the counter
+ * reaching the maximum value when counting up, or when an event from the event
+ * system makes the counter to re-trigger. The reload action determines if the
+ * prescaler should be reset, and on which clock. The counter will
+ * always be reloaded with the value it is set to start counting. The user
+ * can choose between three different reload actions, described in
+ * \ref asfdoc_sam0_tcc_module_reload_act "the table below".
+ *
+ * \anchor asfdoc_sam0_tcc_module_reload_act
+ * <table>
+ *   <caption>TCC Module Reload Actions</caption>
+ *   <tr>
+ *     <th>Reload action</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_RELOAD_ACTION_GCLK</td>
+ *     <td>Reload TCC counter value on next GCLK cycle. Leave prescaler
+ *         as-is.</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_RELOAD_ACTION_PRESC</td>
+ *     <td>Reloads TCC counter value on next prescaler clock. Leave prescaler
+ *         as-is.</td>
+ *   </tr>
+ *  <tr>
+ *    <td>TCC_RELOAD_ACTION_RESYNC</td>
+ *    <td>Reload TCC counter value on next GCLK cycle. Clear prescaler to
+ *        zero.</td>
+ *  </tr>
+ * </table>
+ *
+ * The reload action to use will depend on the specific application being
+ * implemented. One example is when an external trigger for a reload occurs; if
+ * the TCC uses the prescaler, the counter in the prescaler should not have a
+ * value between zero and the division factor. The counter in the TCC module
+ * and the counter in the prescaler should both start at zero.
+ * If the counter is set to re-trigger when it reaches the maximum value,
+ * this is not the right option to use. In such a case it would be better if
+ * the prescaler is left unaltered when the re-trigger happens, letting the
+ * counter reset on the next GCLK cycle.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_tc_oneshot One-shot Mode
+ *
+ * The TCC module can be configured in one-shot mode. When configured in this
+ * manner, starting the timer will cause it to count until the next overflow
+ * or underflow condition before automatically halting, waiting to be manually
+ * triggered by the user application software or an event from the event
+ * system.
+ *
+ * \subsection asfdoc_sam0_tcc_module_overview_capt Capture Operations
+ *
+ * In capture operations, any event from the event system or a pin change can
+ * trigger a capture of the counter value. This captured counter value can be
+ * used as timestamps for the events, or it can be used in frequency and pulse
+ * width capture.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_capt_ev Capture Operations - Event
+ *
+ * Event capture is a simple use of the capture functionality,
+ * designed to create timestamps for specific events. When the input event
+ * appears, the current counter value is copied into the corresponding
+ * compare/capture register, which can then be read by the user application.
+ *
+ * Note that when performing any capture operation, there is a risk that the
+ * counter reaches its top value (MAX) when counting up, or the bottom value
+ * (zero) when counting down, before the capture event occurs. This can distort
+ * the result, making event timestamps to appear shorter than they really are.
+ * In this case, the user application should check for timer overflow when
+ * reading a capture result in order to detect this situation and perform an
+ * appropriate adjustment.
+ *
+ * Before checking for a new capture, \ref TCC_STATUS_COUNT_OVERFLOW
+ * should be checked. The response to an overflow error is left to the user
+ * application, however, it may be necessary to clear both the overflow
+ * flag and the capture flag upon each capture reading.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_capt_pulse Capture Operations - Pulse Width
+ *
+ * Pulse Width Capture mode makes it possible to measure the pulse width and
+ * period of PWM signals. This mode uses two capture channels of the counter.
+ * There are two modes for pulse width capture;
+ * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture
+ * channel 0 is used for storing the pulse width and capture channel 1 stores
+ * the observed period. While in PPW mode, the roles of the two capture channels
+ * are reversed.
+ *
+ * As in the above example it is necessary to poll on interrupt flags to see
+ * if a new capture has happened and check that a capture overflow error has
+ * not occurred.
+ *
+ * Refer to \ref asfdoc_sam0_tcc_module_overview_tc_ctrl to set up the input
+ * event to perform pulse width capture.
+ *
+ * \subsection asfdoc_sam0_tcc_module_overview_mc Compare Match Operation
+ *
+ * In compare match operation, Compare/Capture registers are compared
+ * with the counter value. When the timer's count value matches the value of a
+ * compare channel, a user defined action can be taken.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_mc_timer Basic Timer
+ *
+ * A Basic Timer is a simple application where compare match operation is used
+ * to determine when a specific period has elapsed. In Basic Timer operations,
+ * one or more values in the module's Compare/Capture registers are used to
+ * specify the time (in terms of the number of prescaled GCLK cycles, or
+ * input events) at which
+ * an action should be taken by the microcontroller. This can be an Interrupt
+ * Service Routine (ISR), event generation via the event system, or a software
+ * flag that is polled from the user application.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave Waveform Generation
+ *
+ * Waveform generation enables the TCC module to generate square waves, or, if
+ * combined with an external passive low-pass filter, analog waveforms.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave_pwm Waveform Generation - PWM
+ *
+ * Pulse width modulation is a form of waveform generation and a signalling
+ * technique that can be useful in many applications. When PWM mode is used,
+ * a digital pulse train with a configurable frequency and duty cycle can be
+ * generated by the TCC module and output to a GPIO pin of the device.
+ *
+ * Often PWM is used to communicate a control or information parameter to an
+ * external circuit or component. Differing impedances of the source generator
+ * and sink receiver circuits is less of an issue when using PWM compared to
+ * using an analog voltage value, as noise will not generally affect the
+ * signal's integrity to a meaningful extent.
+ *
+ * \ref asfdoc_sam0_tcc_module_pwm_single_diag "The figure below" illustrates
+ * operations and different states of the counter and its output when using
+ * the timer in Normal PWM mode (Single Slope). As can be seen, the TOP/PERIOD
+ * value is
+ * unchanged and is set to MAX. The compare match value is changed at several
+ * points to illustrate the resulting waveform output changes. The PWM output is
+ * set to normal (i.e. non-inverted) output mode.
+ *
+ * \anchor asfdoc_sam0_tcc_module_pwm_single_diag
+ * \image html pwm_single_ex.svg "Example Of PWM In Single-Slope Mode, and Different Counter Operations"
+ *
+ * Several PWM modes are supported by the TCC module, refer to
+ * datasheet for the details on PWM waveform generation.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave_freq Waveform Generation - Frequency
+ *
+ * Normal Frequency Generation is in many ways identical to PWM generation.
+ * However, only in Frequency Generation, a toggle occurs on the output when a
+ * match on a compare channels occurs.
+ *
+ * When the Match Frequency Generation is used, the timer value is reset on
+ * match condition, resulting in a variable frequency square wave with a
+ * fixed 50% duty cycle.
+ *
+ * \subsection asfdoc_sam0_tcc_module_overview_ext Waveform Extended Controls
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_ext_pat Pattern Generation
+ *
+ * Pattern insertion allows the TCC module to change the actual pin output level
+ * without modifying the compare/match settings.
+ *
+ * \anchor asfdoc_sam0_tcc_module_pattern_gen
+ * <table>
+ *   <caption>TCC Module Output Pattern Generation</caption>
+ *   <tr>
+ *     <th>Pattern</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_OUTPUT_PATTERN_DISABLE</td>
+ *     <td>Pattern disabled, generate output as is</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_OUTPUT_PATTERN_0</td>
+ *     <td>Generate pattern 0 on output (keep the output LOW)</td>
+ *   </tr>
+ *  <tr>
+ *    <td>TCC_OUTPUT_PATTERN_1</td>
+ *    <td>Generate pattern 1 on output (keep the output HIGH)</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_ext_r_fault Recoverable Faults
+ *
+ * The recoverable faults can trigger one or several of following fault actions:
+ * -# *Halt* action: The recoverable faults can halt the TCC timer/counter,
+ *    so that the final output wave is kept at a defined state. When the fault
+ *    state is removed it is possible to recover the counter and waveform
+ *    generation. The halt action is defined as:
+ * \anchor asfdoc_sam0_tcc_module_fault_halt_action
+ * <table>
+ *   <caption>TCC Module Recoverable Fault Halt Actions</caption>
+ *   <tr>
+ *     <th>Action</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_HALT_ACTION_DISABLE</td>
+ *     <td>Halt action is disabled</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_HALT_ACTION_HW_HALT</td>
+ *     <td>The timer/counter is halted as long as the corresponding fault is
+ *         present</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_HALT_ACTION_SW_HALT</td>
+ *     <td>The timer/counter is halted until the corresponding fault is removed
+ *         and fault state cleared by software</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_HALT_ACTION_NON_RECOVERABLE</td>
+ *     <td>Force all the TCC output pins to a pre-defined level, as what
+ *         Non-Recoverable Fault do</td>
+ *   </tr>
+ * </table>
+ * -# *Restart* action: When enabled, the recoverable faults can restart the TCC
+ *    timer/counter.
+ * -# *Keep* action: When enabled, the recoverable faults can keep the
+ *    corresponding channel output to zero when the fault condition is present.
+ * -# *Capture* action: When the recoverable fault occurs, the capture action can
+ *    time stamps the corresponding fault. The following capture mode is
+ *    supported:
+ * \anchor asfdoc_sam0_tcc_module_fault_capt_action
+ * <table>
+ *   <caption>TCC Module Recoverable Fault Capture Actions</caption>
+ *   <tr>
+ *     <th>Action</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_CAPTURE_DISABLE</td>
+ *     <td>Capture action is disabled</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_CAPTURE_EACH</td>
+ *     <td>Equivalent to standard capture operation, on each fault occurrence
+ *         the time stamp is captured</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_CAPTURE_MINIMUM</td>
+ *     <td>Get the minimum time stamped value in all time stamps</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_CAPTURE_MAXIMUM</td>
+ *     <td>Get the maximum time stamped value in all time stamps</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_CAPTURE_SMALLER</td>
+ *     <td>Time stamp the fault input if the value is smaller than last one</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_CAPTURE_BIGGER</td>
+ *     <td>Time stamp the fault input if the value is bigger than last one</td>
+ *   </tr>
+ *   <tr>
+ *     <td>TCC_FAULT_CAPTURE_CHANGE</td>
+ *     <td>Time stamp the fault input if the time stamps changes its increment
+ *         direction</td>
+ *   </tr>
+ * </table>
+ *
+ * In TCC module, only the first two compare channels (CC0 and CC1) can work
+ * with recoverable fault inputs. The corresponding event inputs (TCCx MC0
+ * and TCCx MC1) are then used as fault inputs respectively.
+ * The faults are called Fault A and Fault B.
+ *
+ * The recoverable fault can be filtered or effected by corresponding channel
+ * output. On fault condition there are many other settings that can be chosen.
+ * Refer to data sheet for more details about the recoverable fault
+ * operations.
+ *
+ * \subsubsection asfdoc_sam0_tcc_module_overview_ext_n_fault Non-Recoverable Faults
+ *
+ * The non-recoverable faults force all the TCC output pins to a pre-defined
+ * level (can be forced to 0 or 1). The input control signal of non-recoverable
+ * fault is from timer/counter event (TCCx EV0 and TCCx EV1).
+ * To enable non-recoverable fault,
+ * corresponding TCEx event action must be set to non-recoverable fault action
+ * (\ref TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT).
+ * Refer to \ref asfdoc_sam0_tcc_module_overview_tc_ctrl to see the available
+ * event input action.
+ *
+ * \subsection asfdoc_sam0_tcc_module_overview_buffering Double and Circular Buffering
+ *
+ * The pattern, period, and the compare channels registers are double buffered.
+ * For these options there are effective registers (PATT, PER, and CCx) and
+ * buffer registers (PATTB, PERB, and CCx). When writing to the buffer
+ * registers, the values are buffered and will be committed to effective
+ * registers on UPDATE condition.
+ *
+ * Usually the buffered value is cleared after it is committed, but there is also
+ * an option to circular the register buffers. The period (PER) and four lowest
+ * compare channels register (CCx, x is 0 ~ 3) support this function. When
+ * circular buffer is used, on UPDATE the previous period or compare values are
+ * copied back into the corresponding period buffer and compare buffers.
+ * This way, the register value and its buffer register value is actually
+ * switched on UPDATE condition, and will be switched back on next UPDATE
+ * condition.
+ *
+ * For input capture, the buffer register (CCBx) and the corresponding capture
+ * channel register (CCx) act like a FIFO. When regular register (CCx) is empty
+ * or read, any content in the buffer register is passed to regular one.
+ *
+ * In TCC module driver, when the double buffering write is enabled, any
+ * write through \ref tcc_set_top_value(), \ref tcc_set_compare_value(), and
+ * \ref tcc_set_pattern() will be done to the corresponding buffer register.
+ * Then the value in the buffer register will be transferred to the regular
+ * register on the next UPDATE condition or by a force UPDATE using
+ * \ref tcc_force_double_buffer_update().
+ *
+ * \subsection asfdoc_sam0_tcc_module_overview_sleep Sleep Mode
+ *
+ * TCC modules can be configured to operate in any sleep mode, with its "run
+ * in standby" function enabled. It can wake up the device using interrupts or
+ * perform internal actions with the help of the Event System.
+ *
+ * \section asfdoc_sam0_tcc_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_tcc_special_considerations_specific_features Driver Feature Macro Definition
+ * \ref asfdoc_sam0_tcc_feature_table "The table below" shows some specific features
+ * of the TCC Module.
+ *
+ * \anchor asfdoc_sam0_tcc_feature_table
+ * <table>
+ *   <caption>TCC Module Specific Features</caption>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_TCC_GENERATE_DMA_TRIGGER</td>
+ *    <td>SAM L21/L22/R30</td>
+ *  </tr>
+ * </table>
+ *
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_tcc_special_considerations_tcc_feature Module Features
+ *
+ * The features of TCC, such as timer/counter size, number of compare capture
+ * channels, and number of outputs, are dependent on the TCC module instance being
+ * used.
+ *
+ * \subsubsection asfdoc_sam0_tcc_special_considerations_tcc_d21 SAM TCC Feature List
+ * For SAM D21/R21/L21/L22/DA1/C21/R30, the TCC features are:
+ * \anchor asfdoc_sam0_tcc_features_d21
+ * <table>
+ *   <caption>TCC module features for SAM D21/R21/L21/L22/DA1/C21/R30</caption>
+ *   <tr>
+ *     <th>TCC#</th>
+ *     <th>Match/Capture channels</th>
+ *     <th>Wave outputs</th>
+ *     <th>Counter size [bits]</th>
+ *     <th>Fault</th>
+ *     <th>Dithering</th>
+ *     <th>Output matrix</th>
+ *     <th>Dead-Time insertion</th>
+ *     <th>SWAP</th>
+ *     <th>Pattern</th>
+ *   </tr>
+ *   <tr>
+ *     <td>0</td>
+ *     <td>4</td>
+ *     <td>8</td>
+ *     <td>24</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *   </tr>
+ *   <tr>
+ *     <td>1</td>
+ *     <td>2</td>
+ *     <td>4</td>
+ *     <td>24</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td></td>
+ *     <td></td>
+ *     <td></td>
+ *     <td>Y</td>
+ *   </tr>
+ *   <tr>
+ *     <td>2</td>
+ *     <td>2</td>
+ *     <td>2</td>
+ *     <td>16</td>
+ *     <td>Y</td>
+ *     <td></td>
+ *     <td></td>
+ *     <td></td>
+ *     <td></td>
+ *     <td></td>
+ *   </tr>
+ * </table>
+ *
+ * \subsubsection asfdoc_sam0_tcc_special_considerations_tcc_d11 SAM D10/D11 TCC Feature List
+ * For SAM D10/D11, the TCC features are:
+ * \anchor asfdoc_sam0_tcc_features_d11
+ * <table>
+ *   <caption>TCC Module Features For SAM D10/D11</caption>
+ *   <tr>
+ *     <th>TCC#</th>
+ *     <th>Match/Capture channels</th>
+ *     <th>Wave outputs</th>
+ *     <th>Counter size [bits]</th>
+ *     <th>Fault</th>
+ *     <th>Dithering</th>
+ *     <th>Output matrix</th>
+ *     <th>Dead-Time insertion</th>
+ *     <th>SWAP</th>
+ *     <th>Pattern</th>
+ *   </tr>
+ *   <tr>
+ *     <td>0</td>
+ *     <td>4</td>
+ *     <td>8</td>
+ *     <td>24</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *     <td>Y</td>
+ *   </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_tcc_special_considerations_tcc_pin Channels vs. Pinouts
+ *
+ * As the TCC module may have more waveform output pins than the number of
+ * compare/capture channels, the free pins (with number higher than number of
+ * channels) will reuse the waveform generated by channels subsequently. E.g.,
+ * if the number of channels is four and the number of wave output pins is eight, channel
+ * 0 output will be available on out pin 0 and 4, channel 1 output
+ * on wave out pin 1 and 5, and so on.
+ *
+ * \section asfdoc_sam0_tcc_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_tcc_extra. This includes:
+ *  - \ref asfdoc_sam0_tcc_extra_acronyms
+ *  - \ref asfdoc_sam0_tcc_extra_dependencies
+ *  - \ref asfdoc_sam0_tcc_extra_errata
+ *  - \ref asfdoc_sam0_tcc_extra_history
+ *
+ *
+ * \section asfdoc_sam0_tcc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_tcc_exqsg.
+ *
+ * \section asfdoc_sam0_tcc_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+
+/** Maximum number of channels supported by the driver
+ *  (Channel index from 0 to \c TCC_NUM_CHANNELS - 1).
+ */
+#define TCC_NUM_CHANNELS           4
+
+/** Maximum number of wave outputs lines supported by the driver
+ *  (Output line index from 0 to \c TCC_NUM_WAVE_OUTPUTS - 1).
+ */
+#define TCC_NUM_WAVE_OUTPUTS       8
+
+/** Maximum number of (recoverable) faults supported by the driver. */
+#define TCC_NUM_FAULTS             2
+
+#if TCC_ASYNC == true
+#  include <system_interrupt.h>
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define port features set according to different device family.
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMR30) || defined(__DOXYGEN__)
+/** Generate DMA triggers */
+#  define FEATURE_TCC_GENERATE_DMA_TRIGGER
+#endif
+/*@}*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generates a table enum list entry for a given type
+   and index (e.g. "TCC_CALLBACK_MC_CHANNEL_0,"). */
+#define _TCC_ENUM(n, type) TCC_##type##_##n,
+
+/** Generates table enum list entries for all channels of a
+   given type and channel number on TCC module. */
+#define _TCC_CHANNEL_ENUM_LIST(type) \
+		MREPEAT(TCC_NUM_CHANNELS, _TCC_ENUM, type##_CHANNEL)
+/** Generates table enum list entries for all output of a
+   given type and waveform output number on TCC module. */
+#define _TCC_WO_ENUM_LIST(type) \
+		MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_ENUM, type)
+
+
+#if TCC_ASYNC == true
+/** Enum for the possible callback types for the TCC module. */
+enum tcc_callback {
+	/** Callback for TCC overflow */
+	TCC_CALLBACK_OVERFLOW,
+	/** Callback for TCC Retrigger */
+	TCC_CALLBACK_RETRIGGER,
+	/** Callback for TCC counter event */
+	TCC_CALLBACK_COUNTER_EVENT,
+	/** Callback for capture overflow error */
+	TCC_CALLBACK_ERROR,
+	/** Callback for Recoverable Fault A */
+	TCC_CALLBACK_FAULTA,
+	/** Callback for Recoverable Fault B */
+	TCC_CALLBACK_FAULTB,
+	/** Callback for Non-Recoverable Fault 0 */
+	TCC_CALLBACK_FAULT0,
+	/** Callback for Non-Recoverable Fault 1 */
+	TCC_CALLBACK_FAULT1,
+
+#  if defined(__DOXYGEN__)
+	/** Channel callback type table for TCC
+	 *
+	 *  Each TCC module may contain several callback types for channels; each
+	 *  channel will have its own callback type in the table, with the channel
+	 *  index number substituted for "n" in the channel callback type
+	 *  (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0).
+	 */
+	TCC_CALLBACK_CHANNEL_n = n,
+#  else
+	/** Callbacks for Match/Capture channels, e.g., TCC_CALLBACK_CHANNEL_0 */
+	_TCC_CHANNEL_ENUM_LIST(CALLBACK)
+#  endif
+
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	TCC_CALLBACK_N
+#  endif
+};
+#endif /* #if TCC_ASYNC == true */
+
+/**
+ * \name Module Status Flags
+ *
+ * TCC status flags, returned by \ref tcc_get_status() and cleared by
+ * \ref tcc_clear_status().
+ *
+ * @{
+ */
+
+/** Timer channel \c ch (0 ~ 3) has matched against its compare value,
+ * or has captured a new value.
+ */
+#define TCC_STATUS_CHANNEL_MATCH_CAPTURE(ch)        (1UL << (ch))
+/** Timer channel \c ch (0 ~ 3) match/compare output state. */
+#define TCC_STATUS_CHANNEL_OUTPUT(ch)               (1UL << ((ch)+8))
+/** A Non-Recoverable Fault \c x (0 ~ 1) has occurred. */
+#define TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x)   (1UL << ((x)+16))
+/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occured. */
+#define TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n)       (1UL << ((n)+18))
+/** The Non-Recoverable Fault \c x (0 ~ 1) input is present. */
+#define TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) (1UL << ((x)+20))
+/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) is present. */
+#define TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n)     (1UL << ((n)+22))
+/** Timer registers synchronization has completed, and the synchronized count
+ *  value may be read.
+ */
+#define TCC_STATUS_SYNC_READY                       (1UL << 23)
+/** A new value was captured before the previous value was read, resulting in
+ *  lost data.
+ */
+#define TCC_STATUS_CAPTURE_OVERFLOW                 (1UL << 24)
+/** A counter event occurred. */
+#define TCC_STATUS_COUNTER_EVENT                    (1UL << 25)
+/** A counter retrigger occurred. */
+#define TCC_STATUS_COUNTER_RETRIGGERED              (1UL << 26)
+/** The timer count value has overflowed from its maximum value to its minimum
+ *  when counting upward, or from its minimum value to its maximum when
+ *  counting downward.
+ */
+#define TCC_STATUS_COUNT_OVERFLOW                   (1UL << 27)
+/** Ramp period cycle index.
+ *  In ramp operation, each two period cycles are marked as cycle A and B,
+ *  the index 0 represents cycle A and 1 represents cycle B. */
+#define TCC_STATUS_RAMP_CYCLE_INDEX                 (1UL << 28)
+/** The counter has been stopped (due to disable, stop command, or one-shot). */
+#define TCC_STATUS_STOPPED                          (1UL << 29)
+
+/** @} */
+
+/**
+ * \brief Index of the match capture channels
+ *
+ * This enum is used to specify which capture/match channel to do
+ * operations on.
+ */
+enum tcc_match_capture_channel {
+#  if defined(__DOXYGEN__)
+	/** Match capture channel index table for TCC
+	 *
+	 *  Each TCC module may contain several match capture channels; each channel
+	 *  will have its own index in the table, with the index number substituted
+	 *  for "n" in the index name (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0).
+	 */
+	TCC_MATCH_CAPTURE_CHANNEL_n = n,
+#  else
+	/** Indexes of match capture channels, e.g., TCC_MATCH_CAPTURE_CHANNEL_0 */
+	_TCC_CHANNEL_ENUM_LIST(MATCH_CAPTURE)
+#  endif
+#  if !defined(__DOXYGEN__)
+	/** Number of supported channels */
+	TCC_MATCH_CAPTURE_CHANNEL_N
+#  endif
+};
+
+/**
+ * \brief Index of the wave outputs
+ *
+ * This enum is used to specify which wave output to do
+ * operations on.
+ */
+enum tcc_wave_output {
+#  if defined(__DOXYGEN__)
+	/** Waveform output index table for TCC
+	 *
+	 *  Each TCC module may contain several wave outputs; each output
+	 *  will have its own index in the table, with the index number substituted
+	 *  for "n" in the index name (e.g. \c TCC_WAVE_OUTPUT_0).
+	 */
+	TCC_WAVE_OUTPUT_n = n,
+#  else
+	/** Indexes of match capture channels, e.g., TCC_WAVEFORM_OUTPUT_0 */
+	_TCC_WO_ENUM_LIST(WAVE_OUTPUT)
+#  endif
+#  if !defined(__DOXYGEN__)
+	/** Number of supported channels */
+	TCC_WAVE_OUTPUT_N
+#  endif
+};
+
+/**
+ * \brief TCC wave generation mode enum
+ *
+ * This enum is used to specify the waveform generation mode.
+ *
+ */
+enum tcc_wave_generation {
+	/** Normal Frequency: Top is the PER register, output toggled on each
+	 *  compare match */
+	TCC_WAVE_GENERATION_NORMAL_FREQ = 0,
+	/** Match Frequency: Top is CC0 register, output toggles on each update
+	 *  condition */
+	TCC_WAVE_GENERATION_MATCH_FREQ = 1,
+	/** Single-Slope PWM: Top is the PER register, CCx controls duty cycle
+	 *  (output active when count is greater than CCx) */
+	TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM = 2,
+
+	/** Double-slope (count up and down), non centre-aligned: Top is the PER
+	 *  register, CC[x] controls duty cycle while counting up and CC[x+N/2]
+	 *  controls it while counting down */
+	TCC_WAVE_GENERATION_DOUBLE_SLOPE_CRITICAL = 4,
+	/** Double-slope (count up and down), interrupt/event at Bottom (Top is the
+	 *  PER register, output active when count is greater than CCx) */
+	TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTTOM = 5,
+	/** Double-slope (count up and down), interrupt/event at Bottom and Top: (Top is the
+	 *  PER register, output active when count is lower than CCx) */
+	TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTH = 6,
+	/** Double-slope (count up and down), interrupt/event at Top (Top is the
+	 *  PER register, output active when count is greater than CCx) */
+	TCC_WAVE_GENERATION_DOUBLE_SLOPE_TOP = 7,
+};
+
+/**
+ * \brief Polarity of TCC wave generation on channels
+ *
+ * Specifies whether the wave output needs to be inverted or not.
+ */
+enum tcc_wave_polarity {
+	/** Wave output is not inverted */
+	TCC_WAVE_POLARITY_0,
+	/** Wave output is inverted */
+	TCC_WAVE_POLARITY_1
+};
+
+/**
+ * \brief TCC pattern generator for outputs
+ *
+ * Used when disabling output pattern or when selecting a specific pattern.
+ */
+enum tcc_output_pattern {
+	/** SWAP output pattern is not used */
+	TCC_OUTPUT_PATTERN_DISABLE,
+	/** Pattern 0 is applied to SWAP output */
+	TCC_OUTPUT_PATTERN_0,
+	/** Pattern 1 is applied to SWAP output */
+	TCC_OUTPUT_PATTERN_1
+};
+
+/**
+ * \brief Ramp Operations which are supported in single-slope PWM generation
+ *
+ * Ramp operations which are supported in single-slope PWM generation.
+ */
+enum tcc_ramp {
+	/** Default timer/counter PWM operation */
+	TCC_RAMP_RAMP1 = 0,
+
+	/** Uses a single channel (CC0) to control both CC0/CC1 compare outputs.
+	 *  In cycle A, the channel 0 output is disabled, and
+	 *  in cycle B, the channel 1 output is disabled. */
+	TCC_RAMP_RAMP2A,
+
+	/** Uses channels CC0 and CC1 to control compare outputs.
+	 *  In cycle A, the channel 0 output is disabled, and
+	 *  in cycle B, the channel 1 output is disabled.*/
+	TCC_RAMP_RAMP2
+};
+
+/**
+ * \brief Ramp Index for TCC wave generation
+ *
+ *  In ramp operation, each two period cycles are marked as cycle A and B,
+ *  the index 0 represents cycle A and 1 represents cycle B.
+ */
+enum tcc_ramp_index {
+	/** Default, cycle index toggles. */
+	TCC_RAMP_INDEX_DEFAULT,
+	/** Force next cycle to be cycle B (set to 1) */
+	TCC_RAMP_INDEX_FORCE_B,
+	/** Force next cycle to be cycle A (clear to 0) */
+	TCC_RAMP_INDEX_FORCE_A,
+	/** Force next cycle keeping the same as current */
+	TCC_RAMP_INDEX_FORCE_KEEP
+};
+
+/**
+ * \brief TCC output inversion
+ *
+ * Used when enabling or disabling output inversion.
+ */
+enum tcc_output_invertion {
+	/** Output inversion not to be enabled */
+	TCC_OUTPUT_INVERTION_DISABLE,
+	/** Invert the output from WO[x] */
+	TCC_OUTPUT_INVERTION_ENABLE
+};
+
+/**
+ * \brief TCC Counter reload action enum
+ *
+ * This enum specify how the counter is reloaded and whether the prescaler
+ * should be restarted.
+ */
+enum tcc_reload_action {
+	/** The counter is reloaded/reset on the next GCLK and starts
+	 * counting on the prescaler clock
+	 */
+	TCC_RELOAD_ACTION_GCLK,
+	/** The counter is reloaded/reset on the next prescaler clock
+	 */
+	TCC_RELOAD_ACTION_PRESC,
+	/** The counter is reloaded/reset on the next GCLK, and the
+	 * prescaler is restarted as well
+	 */
+	TCC_RELOAD_ACTION_RESYNC
+};
+
+
+/**
+ * \brief TCC clock prescaler values
+ *
+ * This enum is used to choose the clock prescaler
+ * configuration. The prescaler divides the clock frequency of the TCC
+ * module to operate TCC at a slower clock rate.
+ */
+enum tcc_clock_prescaler {
+	/** Divide clock by 1 */
+	TCC_CLOCK_PRESCALER_DIV1,
+	/** Divide clock by 2 */
+	TCC_CLOCK_PRESCALER_DIV2,
+	/** Divide clock by 4 */
+	TCC_CLOCK_PRESCALER_DIV4,
+	/** Divide clock by 8 */
+	TCC_CLOCK_PRESCALER_DIV8,
+	/** Divide clock by 16 */
+	TCC_CLOCK_PRESCALER_DIV16,
+	/** Divide clock by 64 */
+	TCC_CLOCK_PRESCALER_DIV64,
+	/** Divide clock by 256 */
+	TCC_CLOCK_PRESCALER_DIV256,
+	/** Divide clock by 1024 */
+	TCC_CLOCK_PRESCALER_DIV1024
+};
+
+/**
+ * \brief TCC module count direction
+ *
+ * Used when selecting the Timer/Counter count direction.
+ */
+enum tcc_count_direction {
+	/** Timer should count upward */
+	TCC_COUNT_DIRECTION_UP,
+	/** Timer should count downward */
+	TCC_COUNT_DIRECTION_DOWN,
+};
+
+#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER
+/**
+ * \brief TCC module counter overflow DMA request mode
+ *
+ * Used when selecting the Timer/Counter overflow DMA request mode.
+ */
+enum tcc_count_overflow_dma_trigger_mode {
+	/** TCC generates a DMA request on each cycle when an update condition 
+	 * is detected
+	 */
+	TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_CONTINUE,
+	/** When an update condition is detected, the TCC generates a DMA trigger 
+	 * on the cycle following the DMA One-Shot Command written to the Control 
+	 * B register
+	 */
+	TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_ONE_SHOT,
+};
+#endif
+
+/**
+ * \brief Action to perform when the TCC module is triggered by events
+ *
+ * Event action to perform when the module is triggered by events.
+ */
+enum tcc_event_action {
+	/** No event action */
+	TCC_EVENT_ACTION_OFF,
+	/** Stop counting, the counter will maintain its current value, waveforms
+	 *  are set to a defined Non-Recoverable State output
+	 *  (\ref tcc_non_recoverable_state_output). */
+	TCC_EVENT_ACTION_STOP,
+	/** Re-trigger counter on event, may generate an event if the re-trigger
+	 *  event output is enabled.
+	 *  \note When re-trigger event action is enabled, enabling the counter
+	 *        will not start until the next incoming event appears. */
+	TCC_EVENT_ACTION_RETRIGGER,
+
+	/** Start counter when previously stopped.
+	 * Start counting on the event rising edge. Further events will not
+	 * restart the counter;
+	 * the counter keeps on counting using prescaled GCLK_TCCx, until it
+	 * reaches TOP or Zero
+	 * depending on the direction. */
+	TCC_EVENT_ACTION_START,
+	/** Count events; i.e. Increment or decrement depending on count
+	 * direction. */
+	TCC_EVENT_ACTION_COUNT_EVENT,
+	/** The event source must be an asynchronous event, input value will
+	 *  overrides the direction settings (input low: counting up, input high:
+	 *  counting down). */
+	TCC_EVENT_ACTION_DIR_CONTROL,
+	/** Increment the counter on event, irrespective of count direction */
+	TCC_EVENT_ACTION_INCREMENT,
+	/** Decrement the counter on event, irrespective of count direction */
+	TCC_EVENT_ACTION_DECREMENT,
+	/** Count during active state of asynchronous event. In this case,
+	* depending	on the count direction, the  count will be incremented 
+	* or decremented on each prescaled GCLK_TCCx, as long as the input
+	* event remains active. */
+	TCC_EVENT_ACTION_COUNT_DURING_ACTIVE,
+
+	/** Store period in capture register 0, pulse width in capture
+	 *  register 1
+	 */
+	TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE,
+	/** Store pulse width in capture register 0, period in capture
+	 *  register 1
+	 */
+	TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE,
+
+	/** Generate Non-Recoverable Fault on event */
+	TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT,
+};
+
+
+/**
+ * \brief Action to be performed when the TCC module is triggered by event0
+ *
+ * Event action to perform when the module is triggered by event0.
+ */
+enum tcc_event0_action {
+	/** No event action */
+	TCC_EVENT0_ACTION_OFF                   = TCC_EVENT_ACTION_OFF,
+	/** Re-trigger Counter on event */
+	TCC_EVENT0_ACTION_RETRIGGER             = TCC_EVENT_ACTION_RETRIGGER,
+	/** Count events (increment or decrement, depending on count direction)
+	 */
+	TCC_EVENT0_ACTION_COUNT_EVENT           = TCC_EVENT_ACTION_COUNT_EVENT,
+	/** Start counter on event */
+	TCC_EVENT0_ACTION_START                 = TCC_EVENT_ACTION_START,
+	/** Increment counter on event */
+	TCC_EVENT0_ACTION_INCREMENT             = TCC_EVENT_ACTION_INCREMENT,
+	/** Count during active state of asynchronous event */
+	TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE   = TCC_EVENT_ACTION_COUNT_DURING_ACTIVE,
+
+	/** Generate Non-Recoverable Fault on event */
+	TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT
+};
+
+/**
+ * \brief Action to perform when the TCC module is triggered by event1
+ *
+ * Event action to perform when the module is triggered by event1.
+ */
+enum tcc_event1_action {
+	/** No event action */
+	TCC_EVENT1_ACTION_OFF                   = TCC_EVENT_ACTION_OFF,
+	/** Re-trigger Counter on event */
+	TCC_EVENT1_ACTION_RETRIGGER             = TCC_EVENT_ACTION_RETRIGGER,
+	/** The event source must be an asynchronous event, and the input value
+	 *  will override the direction settings.
+	 *  If TCEINVx is 0 and input event is LOW: counter will count up.
+	 *  If TCEINVx is 0 and input event is HIGH: counter will count down.
+	 */
+	TCC_EVENT1_ACTION_DIR_CONTROL           = TCC_EVENT_ACTION_DIR_CONTROL,
+	/** Stop counter on event */
+	TCC_EVENT1_ACTION_STOP                  = TCC_EVENT_ACTION_STOP,
+	/** Decrement on event */
+	TCC_EVENT1_ACTION_DECREMENT             = TCC_EVENT_ACTION_DECREMENT,
+
+	/** Store period in capture register 0, pulse width in capture
+	 *  register 1
+	 */
+	TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE  = TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE,
+	/** Store pulse width in capture register 0, period in capture
+	 *  register 1
+	 */
+	TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE  = TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE,
+
+	/** Generate Non-Recoverable Fault on event */
+	TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT
+};
+
+/**
+ * \brief On which part of the counter cycle the counter event output is generated
+ *
+ * This enum is used to define the point at which the counter event is generated.
+ */
+enum tcc_event_generation_selection {
+	/** Counter Event is generated when a new counter cycle starts */
+	TCC_EVENT_GENERATION_SELECTION_START,
+	/** Counter Event is generated when a counter cycle ends */
+	TCC_EVENT_GENERATION_SELECTION_END,
+	/** Counter Event is generated when a counter cycle ends, except for the
+	 *  first and last cycles */
+	TCC_EVENT_GENERATION_SELECTION_BETWEEN,
+	/** Counter Event is generated when a new counter cycle starts or ends */
+	TCC_EVENT_GENERATION_SELECTION_BOUNDARY
+};
+
+/**
+ * \brief TCC channel operation modes
+ *
+ * To set a timer channel either in compare or in capture mode.
+ */
+enum tcc_channel_function {
+	/** TCC channel performs compare operation */
+	TCC_CHANNEL_FUNCTION_COMPARE,
+	/** TCC channel performs capture operation */
+	TCC_CHANNEL_FUNCTION_CAPTURE
+};
+
+/**
+ * \brief TCC (recoverable) fault Halt action
+ */
+enum tcc_fault_halt_action {
+	/** Halt action disabled. */
+	TCC_FAULT_HALT_ACTION_DISABLE,
+	/** Hardware halt action, counter is halted until restart */
+	TCC_FAULT_HALT_ACTION_HW_HALT,
+	/** Software halt action, counter is halted until fault bit cleared */
+	TCC_FAULT_HALT_ACTION_SW_HALT,
+	/** Non-Recoverable fault, force output to pre-defined level */
+	TCC_FAULT_HALT_ACTION_NON_RECOVERABLE
+};
+
+/**
+ * \brief TCC (recoverable) fault Capture action
+ */
+enum tcc_fault_capture_action {
+	/** Capture disabled */
+	TCC_FAULT_CAPTURE_DISABLE,
+	/** Capture on Fault, each value is captured */
+	TCC_FAULT_CAPTURE_EACH,
+	/** Capture the minimum detection, but notify on smaller ones */
+	TCC_FAULT_CAPTURE_MINIMUM,
+	/** Capture the maximum detection, but notify on bigger ones */
+	TCC_FAULT_CAPTURE_MAXIMUM,
+	/** Capture if the value is smaller than last, notify event or interrupt
+	 *  if previous stamp is confirmed to be "local minimum" (not bigger than
+	 *  current stamp). */
+	TCC_FAULT_CAPTURE_SMALLER,
+	/** Capture if the value is bigger than last, notify event or interrupt
+	 *  if previous stamp is confirmed to be "local maximum" (not smaller than
+	 *  current stamp). */
+	TCC_FAULT_CAPTURE_BIGGER,
+	/** Capture if the time stamps changes its increment direction */
+	TCC_FAULT_CAPTURE_CHANGE
+};
+
+/**
+ * \brief Capture Channel triggered by TCC (recoverable) fault
+ */
+enum tcc_fault_capture_channel {
+	/** Recoverable fault triggers channel 0 capture operation */
+	TCC_FAULT_CAPTURE_CHANNEL_0,
+	/** Recoverable fault triggers channel 1 capture operation */
+	TCC_FAULT_CAPTURE_CHANNEL_1,
+	/** Recoverable fault triggers channel 2 capture operation */
+	TCC_FAULT_CAPTURE_CHANNEL_2,
+	/** Recoverable fault triggers channel 3 capture operation */
+	TCC_FAULT_CAPTURE_CHANNEL_3
+};
+
+/**
+ * \brief TCC (recoverable) fault Input Source
+ */
+enum tcc_fault_source {
+	/** Fault input is disabled */
+	TCC_FAULT_SOURCE_DISABLE,
+	/** Match Capture Event x (x=0,1) input */
+	TCC_FAULT_SOURCE_ENABLE,
+	/** Inverted MCEx (x=0,1) event input */
+	TCC_FAULT_SOURCE_INVERT,
+	/** Alternate fault (A or B) state at the end of the previous period */
+	TCC_FAULT_SOURCE_ALTFAULT
+};
+
+/**
+ * \brief TCC (recoverable) fault Input Blanking Start Point
+ */
+enum tcc_fault_blanking {
+	/** No blanking */
+	TCC_FAULT_BLANKING_DISABLE,
+	/** Blanking applied from rising edge of the output waveform */
+	TCC_FAULT_BLANKING_RISING_EDGE,
+	/** Blanking applied from falling edge of the output waveform */
+	TCC_FAULT_BLANKING_FALLING_EDGE,
+	/** Blanking applied from each toggle of the output waveform */
+	TCC_FAULT_BLANKING_BOTH_EDGE
+};
+
+/**
+ * \brief TCC (recoverable) fault Input Qualification Action
+ */
+enum tcc_fault_qualification {
+	/** The input is not disabled on compare condition */
+	TCC_FAULT_QUALIFICATION_DISABLE,
+	/** The input is disabled when match output signal is at inactive level */
+	TCC_FAULT_QUALIFICATION_BY_OUTPUT
+};
+
+/**
+ * \brief TCC (recoverable) fault Output Keep Action
+ */
+enum tcc_fault_keep {
+	/** Disable keeping, wave output released as soon as fault is released */
+	TCC_FAULT_KEEP_DISABLE,
+	/** Keep wave output until end of TCC cycle */
+	TCC_FAULT_KEEP_TILL_END
+};
+
+/**
+ * \brief TCC Non-recoverable State Outupt
+ */
+enum tcc_fault_state_output {
+	/** Non-recoverable fault output is tri-stated */
+	TCC_FAULT_STATE_OUTPUT_OFF,
+	/** Non-recoverable fault force output 0 */
+	TCC_FAULT_STATE_OUTPUT_0,
+	/** Non-recoverable fault force output 1 */
+	TCC_FAULT_STATE_OUTPUT_1
+};
+
+/**
+ * \brief TCC (recoverable) fault Restart Action
+ */
+enum tcc_fault_restart {
+	/** Restart Action disabled */
+	TCC_FAULT_RESTART_DISABLE,
+	/** Restart Action enabled */
+	TCC_FAULT_RESTART_ENABLE
+};
+
+/**
+ * \brief Configuration struct for TCC module recoverable fault
+ */
+struct tcc_recoverable_fault_config {
+	/** Fault filter value applied on MCEx event input line (0x0 ~ 0xF).
+	 *  Must be 0 when MCEx event is used as synchronous event.
+	 *  Apply to both recoverable and non-recoverable fault. */
+	uint8_t filter_value;
+	/** Fault blanking value (0 ~ 255), disable input source for several TCC
+	 * clocks after the detection of the waveform edge */
+	uint8_t blanking_cycles;
+
+	/** Set to \c true to enable restart action */
+	bool restart;
+	/** Set to \c true to enable keep action (keep until end of TCC cycle) */
+	bool keep;
+
+	/** Set to \c true to enable input qualification
+	 *  (disable input when output is inactive) */
+	bool qualification;
+
+	/** Specifies if the event input generates recoverable Fault.
+	 *  The event system channel connected to MCEx event input must be
+	 *  configured as asynchronous.
+	 */
+	enum tcc_fault_source source;
+	/** Fault Blanking Start Point for recoverable Fault */
+	enum tcc_fault_blanking blanking;
+
+	/** Halt action for recoverable Fault */
+	enum tcc_fault_halt_action halt_action;
+	/** Capture action for recoverable Fault */
+	enum tcc_fault_capture_action capture_action;
+	/** Channel triggered by recoverable Fault */
+	enum tcc_fault_capture_channel capture_channel;
+};
+
+/**
+ * \brief Configuration struct for TCC module non-recoverable fault
+ */
+struct tcc_non_recoverable_fault_config {
+	/** Fault filter value applied on TCEx event input line (0x0 ~ 0xF).
+	 *  Must be 0 when TCEx event is used as synchronous event. */
+	uint8_t filter_value;
+	/** Output */
+	enum tcc_fault_state_output output;
+};
+
+/**
+ * \brief TCC input event enable/disable/configure structure
+ *
+ * For configuring an input event.
+ */
+struct tcc_input_event_config {
+	/** Event action on incoming event */
+	enum tcc_event_action action;
+	/** Modify event action */
+	bool modify_action;
+	/** Invert incoming event input line */
+	bool invert;
+};
+
+/**
+ * \brief TCC output event enable/disable/configure structure
+ *
+ * Structure used for configuring an output event.
+ */
+struct tcc_output_event_config {
+	/** It decides which part of the counter cycle the counter event output
+	 * is generated */
+	enum tcc_event_generation_selection generation_selection;
+	/** A switch to allow enable/disable of events, without modifying the
+	 *  event output configuration
+	 */
+	bool modify_generation_selection;
+};
+
+/**
+ * \brief TCC event enable/disable structure
+ *
+ * Event flags for the \ref tcc_enable_events() and \ref tcc_disable_events().
+ */
+struct tcc_events {
+	/** Input events configuration */
+	struct tcc_input_event_config input_config[2];
+	/** Output event configuration */
+	struct tcc_output_event_config output_config;
+
+	/** Perform the configured event action when an incoming event is
+	 *  signalled */
+	bool on_input_event_perform_action[2];
+
+	/** Perform the configured event action when an incoming channel event is
+	 *  signalled */
+	bool on_event_perform_channel_action[TCC_NUM_CHANNELS];
+	/** Generate an output event on a channel capture/match.
+	 *  Specify which channels will generate events */
+	bool generate_event_on_channel[TCC_NUM_CHANNELS];
+
+	/** Generate an output event on counter overflow/underflow */
+	bool generate_event_on_counter_overflow;
+	/** Generate an output event on counter retrigger */
+	bool generate_event_on_counter_retrigger;
+	/** Generate an output event on counter boundary.
+	 *  See \ref tcc_event_output_action. */
+	bool generate_event_on_counter_event;
+};
+
+/**
+ * \brief Configuration struct for the TCC module base counter
+ *
+ * Structure for configuring a TCC as a counter.
+ */
+struct tcc_counter_config {
+	/** Value to initialize the count register */
+	uint32_t count;
+	/** Period/top and period/top buffer values for counter */
+	uint32_t period;
+
+	/** When \c true, the counter will be stopped on the next hardware or
+	 * software re-trigger event or overflow/underflow
+	 */
+	bool oneshot;
+
+#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER	
+	/** Counter overflow trigger a DMA request mode */
+	enum tcc_count_overflow_dma_trigger_mode dma_trigger_mode;
+#endif
+
+	/** Specifies the direction for the TCC to count */
+	enum tcc_count_direction direction;
+
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+	/** Specifies the prescaler value for GCLK_TCC */
+	enum tcc_clock_prescaler clock_prescaler;
+	/** Specifies the reload or reset time of the counter and prescaler
+	 *  resynchronization on a re-trigger event for the TCC
+	 */
+	enum tcc_reload_action reload_action;
+};
+
+/**
+ * \brief Configuration struct for the TCC module capture
+ *
+ * Structure used when configuring TCC channels in capture mode.
+ */
+struct tcc_capture_config {
+	/** Channel functions selection (capture/match) */
+	enum tcc_channel_function channel_function[TCC_NUM_CHANNELS];
+};
+
+/**
+ * \brief Configuration struct for the TCC module match/wave generation
+ *
+ * The structure, which helps to configure a TCC channel for compare
+ * operation and wave generation.
+ */
+struct tcc_match_wave_config {
+	/** Channel functions selection (capture/match) */
+	enum tcc_channel_function channel_function[TCC_NUM_CHANNELS];
+
+	/** Specifies polarity for match output waveform generation */
+	enum tcc_wave_polarity wave_polarity[TCC_NUM_CHANNELS];
+	/** Specifies which waveform generation mode to use */
+	enum tcc_wave_generation wave_generation;
+	/** Specifies Ramp mode for waveform generation */
+	enum tcc_ramp wave_ramp;
+
+	/** Value to be used for compare match on each channel */
+	uint32_t match[TCC_NUM_CHANNELS];
+};
+
+/**
+ * \brief Configuration struct for the TCC module waveform extension
+ *
+ * This structure is used to specify the waveform extension features for TCC.
+ */
+struct tcc_wave_extension_config {
+	/** Configuration for recoverable faults */
+	struct tcc_recoverable_fault_config
+			recoverable_fault[TCC_NUM_FAULTS];
+	/** Configuration for non-recoverable faults */
+	struct tcc_non_recoverable_fault_config
+			non_recoverable_fault[TCC_NUM_WAVE_OUTPUTS];
+
+	/** Invert waveform final outputs lines */
+	bool invert[TCC_NUM_WAVE_OUTPUTS];
+};
+
+/**
+ * \brief Configuration struct for the TCC module output pins
+ *
+ * Structure which is used when taking wave output from TCC.
+ */
+struct tcc_pins_config {
+	/** Specifies pin output for each channel */
+	uint32_t wave_out_pin[TCC_NUM_WAVE_OUTPUTS];
+	/** Specifies MUX setting for each output channel pin */
+	uint32_t wave_out_pin_mux[TCC_NUM_WAVE_OUTPUTS];
+	/** When \c true, PWM output pin for the given channel is enabled */
+	bool enable_wave_out_pin[TCC_NUM_WAVE_OUTPUTS];
+};
+
+/**
+ * \brief TCC configuration structure
+ *
+ * Configuration struct for a TCC instance. This structure should be
+ * initialized by the \ref tcc_get_config_defaults function before being
+ * modified by the user application.
+ */
+struct tcc_config {
+	/** Structure for configuring TCC base timer/counter */
+	struct tcc_counter_config counter;
+	/** TCC match/capture configurations */
+	union {
+		/** Helps to configure a TCC channel in capture mode */
+		struct tcc_capture_config capture;
+		/** For configuring a TCC channel in compare mode */
+		struct tcc_match_wave_config compare;
+		/** Serves the same purpose as compare. Used as an alias for
+		 * compare,
+		 *  when a TCC channel is configured for wave generation */
+		struct tcc_match_wave_config wave;
+	};
+
+	/** Structure for configuring TCC waveform extension */
+	struct tcc_wave_extension_config wave_ext;
+
+	/** Structure for configuring TCC output pins */
+	struct tcc_pins_config pins;
+
+	/** Set to \c true to enable double buffering write. When enabled any write
+	 *  through \ref tcc_set_top_value(), \ref tcc_set_compare_value() and
+	 *  \ref tcc_set_pattern() will direct to the buffer register as buffered
+	 *  value, and the buffered value will be committed to effective register
+	 *  on UPDATE condition, if update is not locked.
+	 *
+	 *  \note The init values in \ref tcc_config for \ref tcc_init are always
+	 *        filled to effective registers, no matter if double buffering is
+	 *        enabled or not.
+	 */
+	bool double_buffering_enabled;
+
+	/** When \c true the module is enabled during standby */
+	bool run_in_standby;
+};
+
+#if TCC_ASYNC == true
+/* Forward Declaration for the device instance. */
+struct tcc_module;
+
+/** Type definition for the TCC callback function. */
+typedef void (*tcc_callback_t)(struct tcc_module *const module);
+#endif
+
+/**
+ * \brief TCC software device instance structure
+ *
+ * TCC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved only for module-internal use.
+ */
+struct tcc_module {
+	/** Hardware module pointer of the associated Timer/Counter peripheral. */
+	Tcc *hw;
+
+#  if TCC_ASYNC == true
+	/** Array of callbacks */
+	tcc_callback_t callback[TCC_CALLBACK_N];
+	/** Bit mask for callbacks registered */
+	uint32_t register_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint32_t enable_callback_mask;
+#  endif
+
+	/** Set to \c true to write to buffered registers */
+	bool double_buffering_enabled;
+};
+
+#if !defined(__DOXYGEN__)
+uint8_t _tcc_get_inst_index(
+		Tcc *const hw);
+#endif
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+
+/**
+ * \brief Determines if the hardware module is currently synchronizing to the bus
+ *
+ * Checks to see if the underlying hardware peripheral module is currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ *
+ * \return Synchronization status of the underlying hardware module.
+ *
+ * \retval false If the module has completed synchronization
+ * \retval true  If the module synchronization is ongoing
+ */
+static inline bool tcc_is_syncing(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return (module_inst->hw->SYNCBUSY.reg > 0);
+}
+
+
+void tcc_get_config_defaults(
+		struct tcc_config *const config,
+		Tcc *const hw);
+
+enum status_code tcc_init(
+		struct tcc_module *const module_inst,
+		Tcc *const hw,
+		const struct tcc_config *const config);
+
+/** @} */
+
+/**
+ * \name Event Management
+ * @{
+ */
+
+enum status_code tcc_enable_events(
+		struct tcc_module *const module_inst,
+		struct tcc_events *const events);
+
+void tcc_disable_events(
+		struct tcc_module *const module_inst,
+		struct tcc_events *const events);
+
+/** @} */
+
+/**
+ * \name Enable/Disable/Reset
+ * @{
+ */
+
+/**
+ * \brief Enable the TCC module
+ *
+ * Enables a TCC module that has been previously initialized. The counter will
+ * start when the counter is enabled.
+ *
+ * \note When the counter is configured to re-trigger on an event, the counter
+ *       will not start until the next incoming event appears. Then it
+ *       restarts on any following event.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tcc_enable(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+
+	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) {
+		/* Wait for sync */
+	}
+
+	/* Enable the TCC module */
+	tcc_module->CTRLA.reg |= TCC_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disables the TCC module
+ *
+ * Disables a TCC module and stops the counter.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tcc_disable(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+
+	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) {
+		/* Wait for sync */
+	}
+
+	/* Disbale interrupt */
+	tcc_module->INTENCLR.reg = TCC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	tcc_module->INTFLAG.reg = TCC_INTFLAG_MASK;
+
+	/* Disable the TCC module */
+	tcc_module->CTRLA.reg  &= ~TC_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Resets the TCC module
+ *
+ * Resets the TCC module, restoring all hardware module registers to their
+ * default values and disabling the module. The TCC module will not be
+ * accessible while the reset is being performed.
+ *
+ * \note When resetting a 32-bit counter only the master TCC module's instance
+ *       structure should be passed to the function.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ *
+ */
+static inline void tcc_reset(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments  */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+
+	/* Disable this module if it is running */
+	if (tcc_module->CTRLA.reg & TCC_CTRLA_ENABLE) {
+		tcc_disable(module_inst);
+		while (tcc_is_syncing(module_inst)) {
+			/* wait while module is disabling */
+		}
+	}
+
+	/* Reset this TC module */
+	tcc_module->CTRLA.reg  |= TCC_CTRLA_SWRST;
+}
+
+/** @} */
+
+
+/**
+ * \name Set/Toggle Count Direction
+ * @{
+ */
+
+/**
+ * \brief Sets the TCC module count direction
+ *
+ * Sets the count direction of an initialized TCC module. The
+ * specified TCC module can remain running or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ * \param[in] dir          New timer count direction to set
+ */
+static inline void tcc_set_count_direction(
+		const struct tcc_module *const module_inst,
+		enum tcc_count_direction dir)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+
+	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+		/* Wait for sync */
+	}
+
+	/* Set count direction */
+	if (TCC_COUNT_DIRECTION_DOWN == dir) {
+		tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+		return;
+	}
+	tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR;
+}
+
+/**
+ * \brief Toggles the TCC module count direction
+ *
+ * Toggles the count direction of an initialized TCC module. The
+ * specified TCC module can remain running or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ */
+static inline void tcc_toggle_count_direction(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+
+	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+		/* Wait for sync */
+	}
+	bool dir_value_1 = tcc_module->CTRLBSET.bit.DIR;
+	if (dir_value_1) {
+		tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR;
+	} else {
+		tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+	}
+}
+
+/** @} */
+
+/**
+ * \name Get/Set Count Value
+ * @{
+ */
+
+uint32_t tcc_get_count_value(
+		const struct tcc_module *const module_inst);
+
+enum status_code tcc_set_count_value(
+		const struct tcc_module *const module_inst,
+		const uint32_t count);
+
+/** @} */
+
+/**
+ * \name Stop/Restart Counter
+ * @{
+ */
+
+/**
+ * \brief Stops the counter
+ *
+ * This function will stop the counter. When the counter is stopped
+ * the value in the count register is set to 0 if the counter was
+ * counting up, or maximum or the top value if the counter was counting
+ * down.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tcc_stop_counter(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	uint32_t last_cmd;
+
+	/* Wait until last command is done */
+	do {
+		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+			/* Wait for sync */
+		}
+		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
+		if (last_cmd == TCC_CTRLBSET_CMD_NONE) {
+			break;
+		} else if (last_cmd == TCC_CTRLBSET_CMD_STOP) {
+			/* Command have been issued */
+			return;
+		} else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) {
+			/* Cancel RETRIGGER command and issue STOP */
+			tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk;
+		}
+	} while (1);
+
+	/* Write command to execute */
+	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_STOP;
+}
+
+/**
+ * \brief Starts the counter from beginning
+ *
+ * Restarts an initialized TCC module's counter.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tcc_restart_counter(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	uint32_t last_cmd;
+
+	/* Wait until last command is done */
+	do {
+		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+			/* Wait for sync */
+		}
+		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
+		if (last_cmd == TCC_CTRLBSET_CMD_NONE) {
+			break;
+		} else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) {
+			/* Command have been issued */
+			return;
+		} else if (last_cmd == TCC_CTRLBSET_CMD_STOP) {
+			/* Cancel STOP command and issue RETRIGGER */
+			tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk;
+		}
+	} while (1);
+
+	/* Write command to execute */
+	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_RETRIGGER;
+}
+
+/** @} */
+
+#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER
+/**
+ * \name Generate TCC DMA Triggers Command
+ * @{
+ */
+
+/**
+ * \brief TCC DMA Trigger.
+ *
+ * TCC DMA trigger command.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ */
+static inline void tcc_dma_trigger_command(
+		const struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+
+	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+			/* Wait for sync */
+	}
+
+	/* Make certain that there are no conflicting commands in the register */
+	tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_NONE;
+
+	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+			/* Wait for sync */
+	}
+	
+#if !(SAML21 || SAML22 || SAMR30)
+	/* Write command to execute */
+	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMATRG;
+#endif
+
+#if (SAML21XXXB) || (SAML22) || (SAMR30)
+	/* Write command to execute */
+	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMAOS;
+#endif
+}
+/** @} */
+#endif
+
+/**
+ * \name Get/Set Compare/Capture Register
+ * @{
+ */
+
+uint32_t tcc_get_capture_value(
+		const struct tcc_module *const module_inst,
+		const enum tcc_match_capture_channel channel_index);
+
+enum status_code tcc_set_compare_value(
+		const struct tcc_module *const module_inst,
+		const enum tcc_match_capture_channel channel_index,
+		const uint32_t compare);
+
+/** @} */
+
+/**
+ * \name Set Top Value
+ * @{
+ */
+
+enum status_code tcc_set_top_value(
+		const struct tcc_module *const module_inst,
+		const uint32_t top_value);
+
+/** @} */
+
+
+/**
+ * \name Set Output Pattern
+ * @{
+ */
+
+enum status_code tcc_set_pattern(
+		const struct tcc_module *const module_inst,
+		const uint32_t line_index,
+		const enum tcc_output_pattern pattern);
+
+/** @} */
+
+
+/**
+ * \name Set Ramp Index
+ * @{
+ */
+
+/**
+ * \brief Sets the TCC module ramp index on next cycle
+ *
+ * In RAMP2 and RAMP2A operation, we can force either cycle A or cycle B at
+ * the output, on the next clock cycle.
+ * When ramp index command is disabled, cycle A and cycle B will appear at
+ * the output, on alternate clock cycles.
+ * See \ref tcc_ramp.
+ *
+ * \param[in]  module_inst Pointer to the software module instance struct
+ * \param[in]  ramp_index  Ramp index (\ref tcc_ramp_index) of the next cycle
+ */
+static inline void tcc_set_ramp_index(
+		const struct tcc_module *const module_inst,
+		const enum tcc_ramp_index ramp_index)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	uint32_t last_cmd;
+
+	/* Wait until last command is done */
+	do {
+		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+			/* Wait for sync */
+		}
+		if (TCC_RAMP_INDEX_DEFAULT == ramp_index) {
+			/* Cancel pending command */
+			tcc_module->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD_HOLD;
+			return;
+		}
+		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_IDXCMD_Msk;
+		if (last_cmd == TCC_CTRLBSET_IDXCMD_DISABLE) {
+			break;
+		} else if (last_cmd == TCC_CTRLBSET_IDXCMD(ramp_index)) {
+			/* Command have been issued */
+			return;
+		}
+	} while (1);
+
+	/* Write command to execute */
+	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(ramp_index);
+}
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Checks if the timer/counter is running
+ *
+ * \param[in] module_inst  Pointer to the TCC software instance struct
+ *
+ * \return Status which indicates whether the module is running.
+ *
+ * \retval true The timer/counter is running
+ * \retval false The timer/counter is stopped
+ */
+static inline bool tcc_is_running(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return !module_inst->hw->STATUS.bit.STOP;
+}
+
+uint32_t tcc_get_status(
+		struct tcc_module *const module_inst);
+
+void tcc_clear_status(
+		struct tcc_module *const module_inst,
+		const uint32_t status_flags);
+
+/** @} */
+
+/**
+ * \name Double Buffering Management
+ * @{
+ */
+
+/**
+ * \brief Enable TCC double buffering write
+ *
+ * When double buffering write is enabled, the following function will write
+ * values to buffered registers instead of effective ones (buffered):
+ * - PERB: through \ref tcc_set_top_value()
+ * - CCBx(x is 0~3): through \ref tcc_set_compare_value()
+ * - PATTB: through \ref tcc_set_pattern()
+ *
+ * Then, on UPDATE condition the buffered registers are committed to regular ones
+ * to take effect.
+ *
+ * \param[in] module_inst  Pointer to the TCC software instance struct
+ */
+static inline void tcc_enable_double_buffering(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	module_inst->double_buffering_enabled = true;
+}
+
+/**
+ * \brief Disable TCC double buffering Write
+ *
+ * When double buffering write is disabled, following function will write values
+ * to effective registers (not buffered):
+ * - PER: through \ref tcc_set_top_value()
+ * - CCx(x is 0~3): through \ref tcc_set_compare_value()
+ * - PATT: through \ref tcc_set_pattern()
+ *
+ * \note This function does not lock double buffer update, which means on next
+ *       UPDATE condition the last written buffered values will be committed to
+ *       take effect. Invoke \ref tcc_lock_double_buffer_update() before this
+ *       function to disable double buffering update, if this change is not
+ *       expected.
+ *
+ * \param[in] module_inst  Pointer to the TCC software instance struct
+ */
+static inline void tcc_disable_double_buffering(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->double_buffering_enabled = false;
+}
+
+/**
+ * \brief Lock the TCC double buffered registers updates
+ *
+ * Locks the double buffered registers so they will not be updated through
+ * their buffered values on UPDATE conditions.
+ *
+ * \param[in] module_inst  Pointer to the TCC software instance struct
+ *
+ */
+static inline void tcc_lock_double_buffer_update(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	while (module_inst->hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+		/* Wait for sync */
+	}
+	module_inst->hw->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+}
+
+/**
+ * \brief Unlock the TCC double buffered registers updates
+ *
+ * Unlock the double buffered registers so they will be updated through
+ * their buffered values on UPDATE conditions.
+ *
+ * \param[in] module_inst  Pointer to the TCC software instance struct
+ *
+ */
+static inline void tcc_unlock_double_buffer_update(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	while (module_inst->hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+		/* Wait for sync */
+	}
+	module_inst->hw->CTRLBCLR.reg = TCC_CTRLBCLR_LUPD;
+}
+
+/**
+ * \brief Force the TCC double buffered registers to update once
+ *
+ * \param[in] module_inst  Pointer to the TCC software instance struct
+ *
+ */
+static inline void tcc_force_double_buffer_update(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tcc *const tcc_module = module_inst->hw;
+	uint32_t last_cmd;
+
+	/* Wait until last command is done */
+	do {
+		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
+			/* Wait for sync */
+		}
+		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
+		if (last_cmd == TCC_CTRLBSET_CMD_NONE) {
+			break;
+		} else if (last_cmd == TCC_CTRLBSET_CMD_UPDATE) {
+			/* Command have been issued */
+			return;
+		}
+	} while (1);
+
+	/* Write command to execute */
+	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_UPDATE;
+}
+
+/**
+ * \brief Enable Circular option for double buffered Top/Period Values
+ *
+ * Enable circular option for the double buffered top/period values.
+ * On each UPDATE condition, the contents of PERB and PER are switched, meaning
+ * that the contents of PERB are transferred to PER and the contents of PER are
+ * transferred to PERB.
+ *
+ * \param[in] module_inst     Pointer to the TCC software instance struct
+ */
+static inline void tcc_enable_circular_buffer_top(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->WAVE.reg |=  TCC_WAVE_CIPEREN;
+}
+
+/**
+ * \brief Disable Circular option for double buffered Top/Period Values
+ *
+ * Stop circularing the double buffered top/period values.
+ *
+ * \param[in] module_inst     Pointer to the TCC software instance struct
+ */
+static inline void tcc_disable_circular_buffer_top(
+		struct tcc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->WAVE.reg &= ~TCC_WAVE_CIPEREN;
+}
+
+enum status_code tcc_set_double_buffer_top_values(
+		const struct tcc_module *const module_inst,
+		const uint32_t top_value, const uint32_t top_buffer_value);
+
+
+enum status_code tcc_enable_circular_buffer_compare(
+		struct tcc_module *const module_inst,
+		enum tcc_match_capture_channel channel_index);
+enum status_code tcc_disable_circular_buffer_compare(
+		struct tcc_module *const module_inst,
+		enum tcc_match_capture_channel channel_index);
+enum status_code tcc_set_double_buffer_compare_values(
+		struct tcc_module *const module_inst,
+		enum tcc_match_capture_channel channel_index,
+		const uint32_t compare,
+		const uint32_t compare_buffer);
+
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_sam0_tcc_extra Extra Information for TCC Driver
+ *
+ * \section asfdoc_sam0_tcc_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+  * <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ *  </tr>
+ *  <tr>
+ *      <td>TCC</td>
+ *      <td>Timer Counter for Control Applications</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PWM</td>
+ *      <td>Pulse Width Modulation</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PWP</td>
+ *      <td>Pulse Width Period</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PPW</td>
+ *      <td>Period Pulse Width</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_tcc_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_tcc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_tcc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Add double buffering functionality</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Add fault handling functionality</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_tcc_exqsg Examples for TCC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_tcc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_tcc_basic_use_case
+ *  - \subpage asfdoc_sam0_tcc_buffering_use_case
+ * \if TCC_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_tcc_timer_use_case
+ *  - \subpage asfdoc_sam0_tcc_callback_use_case
+ *  - \subpage asfdoc_sam0_tcc_faultx_use_case
+ *  - \subpage asfdoc_sam0_tcc_faultn_use_case
+ * \endif
+ *  - \subpage asfdoc_sam0_tcc_dma_use_case
+ *
+ * \page asfdoc_sam0_tcc_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42256C</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM DA1, and SAM C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42256B</td>
+ *      <td>12/2014</td>
+ *      <td>Added fault handling functionality.
+ *          Added double buffering functionality with use case.
+ *          Added timer use case.
+ *          Added SAM R21/D10/D11 support.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42256A</td>
+ *      <td>01/2014</td>
+ *      <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif /* TCC_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.c
new file mode 100644
index 0000000000..aa1d5e3e94
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.c
@@ -0,0 +1,245 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC - Timer Counter for Control Applications Callback Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "tcc_callback.h"
+
+void *_tcc_instances[TCC_INST_NUM];
+
+void _tcc_interrupt_handler(uint8_t module_index);
+
+const uint32_t _tcc_intflag[TCC_CALLBACK_N] = {
+	TCC_INTFLAG_OVF,
+	TCC_INTFLAG_TRG,
+	TCC_INTFLAG_CNT,
+	TCC_INTFLAG_ERR,
+	TCC_INTFLAG_FAULTA,
+	TCC_INTFLAG_FAULTB,
+	TCC_INTFLAG_FAULT0,
+	TCC_INTFLAG_FAULT1,
+#define _TCC_INTFLAG_MC(n,dummy) TCC_INTFLAG_MC##n,
+	/* TCC_INTFLAG_MC0 ~ ... */
+	MREPEAT(TCC_NUM_CHANNELS, _TCC_INTFLAG_MC, 0)
+#undef _TCC_INTFLAG_MC
+};
+
+#  define _TCC_INTERRUPT_VECT_NUM(n, unused) \
+		  SYSTEM_INTERRUPT_MODULE_TCC##n,
+/**
+ * \internal Get the interrupt vector for the given device instance
+ *
+ * \param[in] The TCC module instance number
+ *
+ * \return Interrupt vector for of the given TCC module instance.
+ */
+static enum system_interrupt_vector _tcc_interrupt_get_interrupt_vector(
+		uint32_t inst_num)
+{
+	static uint8_t tcc_interrupt_vectors[TCC_INST_NUM] = {
+		MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_VECT_NUM, 0)
+	};
+
+	return (enum system_interrupt_vector)tcc_interrupt_vectors[inst_num];
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref tcc_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module        Pointer to TCC software instance struct
+ * \param[in]     callback_func Pointer to callback function
+ * \param[in]     callback_type Callback type given by an enum
+ */
+enum status_code tcc_register_callback(
+		struct tcc_module *const module,
+		tcc_callback_t callback_func,
+		const enum tcc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->register_callback_mask |= _tcc_intflag[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function implemented by the user. The callback should
+ * be disabled before it is unregistered.
+ *
+ * \param[in]     module Pointer to TCC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+enum status_code tcc_unregister_callback(
+		struct tcc_module *const module,
+		const enum tcc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->register_callback_mask &= ~_tcc_intflag[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref
+ * tcc_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are
+ * met. This function will also enable the appropriate interrupts.
+ *
+ * \param[in]     module Pointer to TCC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+void tcc_enable_callback(
+		struct tcc_module *const module,
+		const enum tcc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Enable interrupts for this TCC module */
+	system_interrupt_enable(_tcc_interrupt_get_interrupt_vector(
+			_tcc_get_inst_index(module->hw)));
+
+	/* Enable channel or other callbacks */
+	module->enable_callback_mask |= _tcc_intflag[callback_type];
+	module->hw->INTENSET.reg = _tcc_intflag[callback_type];
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback function registered by the \ref
+ * tcc_register_callback, and the callback will not be called from the
+ * interrupt routine. The function will also disable the appropriate
+ * interrupts.
+ *
+ * \param[in]     module Pointer to TCC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+void tcc_disable_callback(
+		struct tcc_module *const module,
+		const enum tcc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Disable interrupts for this TCC module */
+	system_interrupt_disable(_tcc_interrupt_get_interrupt_vector(
+			_tcc_get_inst_index(module->hw)));
+
+	/* Disable channel or other callbacks */
+	module->enable_callback_mask &= ~_tcc_intflag[callback_type];
+	module->hw->INTENCLR.reg = _tcc_intflag[callback_type];
+}
+
+
+/**
+ * \internal ISR handler for TCC
+ *
+ * Auto-generate a set of interrupt handlers for each TCC in the device.
+ */
+#define _TCC_INTERRUPT_HANDLER(n, m) \
+		void TCC##n##_Handler(void) \
+		{ \
+			_tcc_interrupt_handler(n); \
+		}
+
+MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_HANDLER, 0)
+
+/**
+ * \internal Interrupt handler for the TCC module
+ *
+ * Handles interrupts as they occur, it will run the callback functions
+ * that are registered and enabled.
+ *
+ * \param[in]  module_index  ID of the TCC instance calling the interrupt
+ *                           handler
+ */
+void _tcc_interrupt_handler(
+		uint8_t module_index)
+{
+	int i;
+
+	uint32_t interrupt_and_callback_status_mask;
+
+	struct tcc_module *module =
+			(struct tcc_module *)_tcc_instances[module_index];
+
+	interrupt_and_callback_status_mask = (module->hw->INTFLAG.reg &
+			module->register_callback_mask &
+			module->enable_callback_mask);
+
+	/* Check if callback interrupt has occured */
+	for (i = 0; i < TCC_CALLBACK_N; i ++) {
+		if (interrupt_and_callback_status_mask & _tcc_intflag[i]) {
+			/* Invoke the registered and enabled callback function */
+			(module->callback[i])(module);
+			/* Clear interrupt flag */
+			module->hw->INTFLAG.reg = _tcc_intflag[i];
+		}
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.h
new file mode 100644
index 0000000000..37b0bbb727
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.h
@@ -0,0 +1,93 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC - Timer Counter for Control Applications Callback Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef TCC_CALLBACK_H_INCLUDED
+#define TCC_CALLBACK_H_INCLUDED
+
+#include "tcc.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+extern void *_tcc_instances[TCC_INST_NUM];
+#endif
+
+
+/**
+ * \name Callback Management
+ * {@
+ */
+
+enum status_code tcc_register_callback(
+		struct tcc_module *const module,
+		tcc_callback_t callback_func,
+		const enum tcc_callback callback_type);
+
+enum status_code tcc_unregister_callback(
+		struct tcc_module *const module,
+		const enum tcc_callback callback_type);
+
+void tcc_enable_callback(
+		struct tcc_module *const module,
+		const enum tcc_callback callback_type);
+
+void tcc_disable_callback(
+		struct tcc_module *const module,
+		const enum tcc_callback callback_type);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TCC_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.c
new file mode 100644
index 0000000000..707371de59
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.c
@@ -0,0 +1,192 @@
+/**
+ * \file
+ *
+ * \brief SAM TIMER Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "timer.h"
+
+static timer_callback_t timer_callback;
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given TIMER configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structures before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Timer interrupt set as disable
+ *  \li Set relaod value as 0
+ *
+ * \param[out]  config  Pointer to a TIMER module configuration structure to set
+ */
+void timer_get_config_defaults(struct timer_config *config)
+{
+	config->reload_value = 0;
+	config->interrupt_enable = true;
+}
+
+
+/**
+ * \brief Get TIMER0 module current value.
+ *
+ * \retval Current value
+ */
+uint32_t timer_get_value(void)
+{
+	return TIMER0->VALUE.reg;
+}
+
+/**
+ * \brief Set TIMER0 module value.
+ *
+ * \param[in]     value        Reload value
+ */
+void timer_set_value(uint32_t value)
+{
+	TIMER0->RELOAD.reg = value;
+}
+
+/**
+ * \brief Get TIMER0 module interrupt status
+ *
+ * \retval The status of module
+ */
+uint32_t timer_get_interrupt_status(void)
+{
+	return TIMER0->INTSTATUSCLEAR.reg;
+}
+
+/**
+ * \brief Clear TIMER0 module interrupt status
+ *
+ * Clear the TIMER0 module interrupt status
+ */
+void timer_clear_interrupt_status(void)
+{
+	TIMER0->INTSTATUSCLEAR.reg = 1;
+	/* Wait for operation finish */
+	while (TIMER0->INTSTATUSCLEAR.reg);
+}
+
+/**
+ * \brief Set TIMER0 module enable
+ *
+ * Enable the TIMER0 module
+ */
+void timer_enable(void)
+{
+	TIMER0->CTRL.reg |= TIMER_CTRL_ENABLE;
+}
+
+/**
+ * \brief Set TIMER0 disable
+ *
+ * Disable the TIMER0 module
+ */
+void timer_disable(void)
+{
+	TIMER0->CTRL.reg &= (~TIMER_CTRL_ENABLE);
+}
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers and enable a callback function which is implemented by the user.
+ *
+ * \param[in]     callback_func Pointer to callback function
+ */
+void timer_register_callback(timer_callback_t fun)
+{
+	timer_callback = fun; 
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters and disable a callback function implemented by the user.
+ *
+ */
+void timer_unregister_callback(void)
+{
+	timer_callback = NULL; 
+}
+
+/**
+ * \brief Timer ISR handler.
+ *
+ * Timer ISR handler.
+ *
+ */
+static void timer_isr_handler(void)
+{
+	if (timer_get_interrupt_status()) {
+		timer_clear_interrupt_status();
+		
+		if (timer_callback) {
+			timer_callback();
+		}
+	}
+}
+
+/**
+ * \brief Initializes TIMER0 module instance.
+ *
+ * Initializes the TIMER0 module, based on the given
+ * configuration values.
+ *
+ * \param[in]     config       Pointer to the TIMER configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ */
+void timer_init(const struct timer_config *config)
+{
+	/* Global reset */
+	system_peripheral_reset(PERIPHERAL_TIMER);
+
+	TIMER0->CTRL.reg = config->interrupt_enable << TIMER_CTRL_INTERRUPT_ENABLE_Pos;
+	TIMER0->RELOAD.reg = config->reload_value;
+	
+	timer_callback = NULL;
+	system_register_isr(RAM_ISR_TABLE_TIMER0_INDEX, (uint32_t)timer_isr_handler);
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.h
new file mode 100644
index 0000000000..d21f5f35ea
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.h
@@ -0,0 +1,257 @@
+/**
+ * \file
+ *
+ * \brief SAM TIMER Driver for SAMB11
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef TIMER_H_INCLUDED
+#define TIMER_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_timer_group SAM TIMER
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's basic Timer functionality.
+ *
+ * The following peripherals are used by this module:
+ *  - TIMER
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_timer_prerequisites
+ *  - \ref asfdoc_samb_timer_module_overview
+ *  - \ref asfdoc_samb_timer_special_considerations
+ *  - \ref asfdoc_samb_timer_extra_info
+ *  - \ref asfdoc_samb_timer_examples
+ *  - \ref asfdoc_samb_timer_api_overview
+ *
+ *
+ * \section asfdoc_samb_timer_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_timer_module_overview Module Overview
+ * This driver proiveds a basic timer for count, is a 32-bit
+ * down-counter with the following features:
+ *
+ * - You can generate an interrupt request signal, TIMERINT,
+ * when the counter reaches 0.
+ 
+ * - The interrupt request is held until it is cleared by writing to the INTCLEAR Register.
+ *
+ * - You can use the zero to one transition of the external input signal, EXTIN, as a timer enable.
+ *
+ * - If the APB timer count reaches 0 and, at the same time, the software clears a previous
+ * interrupt status, the interrupt status is set to 1.
+ *
+ * - The external clock, EXTIN, must be slower than half of the peripheral clock because it is
+ * sampled by a double flip-flop and then goes through edge-detection logic when the
+ * external inputs act as a clock. 
+ *
+ * - A separate clock pin, PCLKG, for the APB register read or write logic that permits the
+ * clock to peripheral register logic to stop when there is no APB activity.
+ *
+ * \section asfdoc_samb_timer_special_considerations Special Considerations
+ *
+ * There are no prerequisites for this module.
+ *
+ * \section asfdoc_samb_timer_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_timer_extra. This includes:
+ *  - \ref asfdoc_samb_timer_extra_acronyms
+ *  - \ref asfdoc_samb_timer_extra_dependencies
+ *  - \ref asfdoc_samb_timer_extra_errata
+ *  - \ref asfdoc_samb_timer_extra_history
+ *
+ *
+ * \section asfdoc_samb_timer_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_timer_exqsg.
+ *
+ *
+ * \section asfdoc_samb_timer_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system_sam_b.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Type definition for a TIMER module callback function. */
+typedef void (*timer_callback_t)(void);
+
+/**
+ * \brief TIMER configuration structure.
+ *
+ * Configuration struct for a TIMER instance. This structure should be
+ * initialized by the \ref timer_get_config_defaults function before being
+ * modified by the user application.
+ */
+struct timer_config {
+	/** Reload value */
+	uint32_t reload_value;
+	/** Enable timer interrupt */
+	bool interrupt_enable;
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+void timer_get_config_defaults(struct timer_config *config);
+void timer_init(const struct timer_config *config);
+/** @} */
+
+/**
+ * \name Get and set value
+ * @{
+ */
+uint32_t timer_get_value(void);
+void timer_set_value(uint32_t value);
+/** @} */
+
+/**
+ * \name Get and Clear status
+ * @{
+ */
+uint32_t timer_get_interrupt_status(void);
+void timer_clear_interrupt_status(void);
+/** @} */
+
+/**
+ * \name Enable and disable module
+ * @{
+ */
+void timer_enable(void);
+void timer_disable(void);
+/** @} */
+
+/**
+ * \name Callback
+ * @{
+ */
+void timer_register_callback(timer_callback_t fun);
+void timer_unregister_callback(void);
+/** @} */
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_samb_timer_extra Extra Information for TIMER Driver
+ *
+ * \section asfdoc_samb_timer_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>TIMER</td>
+ *		<td>Timer</td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_samb_timer_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_timer_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_timer_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_timer_exqsg Examples for TIMER Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_timer_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_timer_basic_use_case
+ *
+ * \page asfdoc_samb_timer_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *    <th>Doc. Rev.</td>
+ *    <th>Date</td>
+ *    <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *    <td>A</td>
+ *    <td>09/2015</td>
+ *    <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.c
new file mode 100644
index 0000000000..b5ce6b39f8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.c
@@ -0,0 +1,101 @@
+/**
+ * \file
+ *
+ * \brief SAM True Random Number Generator (TRNG) Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "trng.h"
+
+/**
+ * \brief Initializes a hardware TRNG module instance.
+ *
+ * Enables the clock and initializes the TRNG module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     hw           Pointer to the TRNG hardware module
+ * \param[in]     config       Pointer to the TRNG configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ */
+enum status_code trng_init(
+		struct trng_module *const module_inst,
+		Trng *const hw,
+		struct trng_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module_inst->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TRNG);
+
+#if TRNG_CALLBACK_MODE == true
+	/* Initialize parameters */
+	for (uint8_t i = 0; i < TRNG_CALLBACK_N; i++) {
+		module_inst->callback[i] = NULL;
+	}
+
+	/* Initialize software flags*/
+	module_inst->register_callback_mask = 0x00;
+	module_inst->enable_callback_mask   = 0x00;
+	module_inst->job_buffer             = NULL;
+	module_inst->remaining_number       = 0;
+	module_inst->job_status             = STATUS_OK;
+
+	/* Register this instance for callbacks*/
+	_trng_instance = module_inst;
+#endif
+
+	/* Write configuration to module */
+	hw->CTRLA.reg = ((uint32_t)config->run_in_standby << TRNG_CTRLA_RUNSTDBY_Pos);
+
+	return STATUS_OK;
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.h
new file mode 100644
index 0000000000..8fec9b98e9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.h
@@ -0,0 +1,456 @@
+/**
+ * \file
+ *
+ * \brief SAM True Random Number Generator (TRNG) Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TRNG_H_INCLUDED
+#define TRNG_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_trng_group SAM True Random Number Generator (TRNG) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's True Random Number Generator functionality.
+ *
+ * The following driver API modes are covered by this manual:
+ * - Polled APIs
+ * \if TRNG_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - TRNG (True Random Number Generator)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L21/L22
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_trng_prerequisites
+ *  - \ref asfdoc_sam0_trng_module_overview
+ *  - \ref asfdoc_sam0_trng_special_considerations
+ *  - \ref asfdoc_sam0_trng_extra_info
+ *  - \ref asfdoc_sam0_trng_examples
+ *  - \ref asfdoc_sam0_trng_api_overview
+ *
+ *
+ * \section asfdoc_sam0_trng_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_trng_module_overview Module Overview
+ *
+ * This driver provides an interface for the TRNG functions on the device.
+ *
+ * As soon as the TRNG is enabled, the module provides a new 32-bit random
+ * data, for every 84 CLK_TRNG_APB clock cycles.
+ *
+ *
+ * \section asfdoc_sam0_trng_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_trng_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_trng_extra. This includes:
+ *  - \ref asfdoc_sam0_trng_extra_acronyms
+ *  - \ref asfdoc_sam0_trng_extra_dependencies
+ *  - \ref asfdoc_sam0_trng_extra_errata
+ *  - \ref asfdoc_sam0_trng_extra_history
+ *
+ *
+ * \section asfdoc_sam0_trng_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_trng_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_trng_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if TRNG_CALLBACK_MODE == true
+/* Forward declaration of struct */
+struct trng_module;
+
+extern struct trng_module *_trng_instance;
+
+/** Type definition for a TRNG module callback function. */
+typedef void (*trng_callback_t)(struct trng_module *const module_inst);
+
+/** Enum for possible callback types for the TRNG module. */
+enum trng_callback {
+	/** Callback for specific number of random data ready */
+	TRNG_CALLBACK_READ_BUFFER = 0,
+	/** Number of available callbacks */
+#if !defined(__DOXYGEN__)
+	TRNG_CALLBACK_N,
+#endif
+};
+#endif
+
+/**
+ * \brief TRNG software device instance structure.
+ *
+ * TRNG software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct trng_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware module pointer of the associated TRNG peripheral */
+	Trng *hw;
+#  if TRNG_CALLBACK_MODE == true
+	/** Array of callbacks */
+	trng_callback_t callback[TRNG_CALLBACK_N];
+	/** Bit mask for callbacks registered */
+	uint8_t register_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t enable_callback_mask;
+	/** Holds the status of the ongoing or last read job */
+	volatile enum status_code job_status;
+	/** Pointer to buffer used for TRNG results */
+	volatile uint32_t *job_buffer;
+	/** Remaining number of TRNG results in current job */
+	volatile uint32_t remaining_number;
+#  endif
+#endif
+};
+
+/**
+ * \brief TRNG module configuration structure.
+ *
+ *  Configuration structure for a True Random Number Generator.
+ */
+struct trng_config {
+	/** If \c true, the True Random Number Generator will not be stopped in
+	 *  standby sleep mode */
+	bool run_in_standby;
+};
+
+/**
+ * \brief TRNG event enable/disable structure.
+ *
+ * Event flags for the TRNG module. This is used to enable and
+ * disable events via \ref trng_enable_events() and \ref trng_disable_events().
+ */
+struct trng_events {
+	/** Enable event generation on random data ready */
+	bool generate_event_on_data_ready;
+};
+
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+enum status_code trng_init(
+		struct trng_module *const module_inst,
+		Trng *const hw,
+		struct trng_config *const config);
+
+/**
+ * \brief Initializes all members of a TRNG configuration structure
+ *  to safe defaults.
+ *
+ *  Initializes all members of a given True Random Number Generator configuration
+ *  structure to safe known default values. This function should be called on
+ *  all new instances of these configuration structures before being modified
+ *  by the user application.
+ *
+ *  The default configuration is as follows:
+ *   \li True Random Number Generator will not be stopped in standby sleep mode
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void trng_get_config_defaults(
+		struct trng_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->run_in_standby = false;
+}
+
+/**
+ * \brief Enables a TRNG that was previously configured.
+ *
+ * Enables True Random Number Generator that was previously configured via a
+ * call to \ref trng_init().
+ *
+ * \param[in] module_inst  Software instance for the True Random Number
+ *                         Generator peripheral
+ */
+static inline void trng_enable(
+		struct trng_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Trng *const trng_module = module_inst->hw;
+
+	/* Enable TRNG */
+	trng_module->CTRLA.reg |= TRNG_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disables a TRNG that was previously enabled.
+ *
+ * Disables True Random Number Generator that was previously started via a call
+ * to \ref trng_enable().
+ *
+ * \param[in] module_inst  Software instance for the True Random Number
+ *                         Generator peripheral
+ */
+static inline void trng_disable(
+		struct trng_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Trng *const trng_module = module_inst->hw;
+
+	/* Disbale interrupt */
+	trng_module->INTENCLR.reg = TRNG_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	trng_module->INTFLAG.reg = TRNG_INTFLAG_MASK;
+
+	/* Disable TRNG */
+	trng_module->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Enables a TRNG event output.
+ *
+ *  Enables output events from the True Random Number Generator
+ *  module. See \ref Section Struct trng_events for a list of events this module
+ *  supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the TRNG peripheral
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+static inline void trng_enable_events(
+		struct trng_module *const module_inst,
+		struct trng_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Trng *const trng_module = module_inst->hw;
+
+	if (events->generate_event_on_data_ready) {
+		/* Enable data ready event output */
+		trng_module->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
+	}
+}
+
+/**
+ * \brief Disables a TRNG event output.
+ *
+ *  Disables output events from the True Random Number Generator
+ *  module. See \ref Section Struct trng_events for a list of events
+ *  this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the TRNG peripheral
+ *  \param[in] events       Struct containing flags of events to disable
+ */
+static inline void trng_disable_events(
+		struct trng_module *const module_inst,
+		struct trng_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Trng *const trng_module = module_inst->hw;
+
+	if (events->generate_event_on_data_ready) {
+		/* Disable data ready event output */
+		trng_module->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
+	}
+}
+/** @} */
+
+/**
+ * \name Read TRNG Result
+ * @{
+ */
+
+/**
+ * \brief Read the random data result
+ *
+ * Reads the random data result.
+ *
+ * \param[in]  module_inst  Pointer to the TRNG software instance struct
+ * \param[out] result       Pointer to store the result value in
+ *
+ * \return Status of the TRNG read request.
+ * \retval STATUS_OK           The result was retrieved successfully
+ * \retval STATUS_BUSY         A random result was not ready
+ */
+static inline enum status_code trng_read(
+		struct trng_module *const module_inst,
+		uint32_t *result)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(result);
+
+	Trng *const trng_hw = module_inst->hw;
+
+	if (!(trng_hw->INTFLAG.reg & TRNG_INTFLAG_DATARDY)) {
+		/* Result not ready */
+		return STATUS_BUSY;
+	}
+
+	/* Get randomly generated output data (it will clear data ready flag) */
+	*result = trng_hw->DATA.reg;
+
+	return STATUS_OK;
+}
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_trng_extra Extra Information for TRNG Driver
+ *
+ * \section asfdoc_sam0_trng_extra_acronyms Acronyms
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>TRNG</td>
+ *		<td>True Random Number Generator</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_trng_extra_dependencies Dependencies
+ * This driver has no dependencies.
+ *
+ *
+ * \section asfdoc_sam0_trng_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_trng_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+  *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_trng_exqsg Examples for TRNG Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_trng_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_trng_basic_use_case
+ * \if TRNG_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_trng_basic_use_case_callback
+ * \endif
+ *
+ * \page asfdoc_sam0_trng_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42444B</td>
+ *		<td>01/2016</td>
+ *		<td>Added support for SAM L22</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42444A</td>
+ *		<td>06/2015</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* TRNG_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.c
new file mode 100644
index 0000000000..a3a7ea5672
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.c
@@ -0,0 +1,242 @@
+/**
+ * \file
+ *
+ * \brief SAM True Random Number Generator (TRNG) Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "trng_callback.h"
+#include "system_interrupt.h"
+
+struct trng_module *_trng_instance;
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref trng_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_func Pointer to callback function
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \retval STATUS_OK  The function exited successfully
+ */
+enum status_code trng_register_callback(
+		struct trng_module *const module,
+		trng_callback_t callback_func,
+		const enum trng_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->register_callback_mask |= (1 << callback_type);
+
+	/* Enable interrupt for this TRNG module */
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_TRNG);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function implemented by the user. The callback should be
+ * disabled before it is unregistered.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \retval STATUS_OK  The function exited successfully
+ */
+enum status_code trng_unregister_callback(
+		struct trng_module *const module,
+		const enum trng_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->register_callback_mask &= ~(1 << callback_type);
+
+	/* Disable interrupt for this TRNG module */
+	if (module->register_callback_mask == 0) {
+		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_TRNG);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal ISR handler for TRNG
+ *
+ * TRNG interrupt handler for random data ready.
+ */
+void TRNG_Handler(void)
+{
+	/* Temporary variable */
+	uint8_t interrupt_and_callback_status_mask;
+
+	/* Get device instance from the look-up table */
+	struct trng_module *module = _trng_instance;
+
+	/* Read and mask interrupt flag register */
+	interrupt_and_callback_status_mask = module->hw->INTFLAG.reg &
+			(module->register_callback_mask & module->enable_callback_mask);
+
+	/* Check if data ready needs to be serviced */
+	if (interrupt_and_callback_status_mask & TRNG_INTFLAG_DATARDY) {
+		/* Store random result in job buffer (it will clear data ready flag) */
+		*(module->job_buffer++) = module->hw->DATA.reg;
+
+		module->remaining_number -= 1;
+		if (module->remaining_number == 0) {
+			if (module->job_status == STATUS_BUSY) {
+				/* Job is complete. Update status, disable interrupt
+				 * and call callback */
+				module->job_status = STATUS_OK;
+				module->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
+				(module->callback[TRNG_CALLBACK_READ_BUFFER])(module);
+			}
+		}
+	}
+
+	/* Clear interrupt flag */
+	module->hw->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+/**
+ * \brief Read multiple random data from TRNG
+ *
+ * As soon as the TRNG is enabled, the module provides a new 32-bits
+ * random data for every 84 CLK_TRNG_APB clock cycles.
+ *
+ * \param[in]  module_inst  Pointer to the TRNG software instance struct
+ * \param[in]  number       Number of random data to get
+ * \param[out] buffer       Buffer to store the random data
+ *
+ * \return Status of the job start.
+ * \retval STATUS_OK        The read job was started successfully and is
+ *                          in progress
+ * \retval STATUS_BUSY      The TRNG is already busy with another job
+ */
+enum status_code trng_read_buffer_job(
+		struct trng_module *const module_inst,
+		uint32_t *buffer,
+		uint32_t number)
+{
+	Assert(module_inst);
+	Assert(number);
+	Assert(buffer);
+
+	if (module_inst->remaining_number != 0 ||
+			module_inst->job_status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	module_inst->job_status = STATUS_BUSY;
+	module_inst->remaining_number = number;
+	module_inst->job_buffer = buffer;
+
+	/* Enable data ready interrupt */
+	module_inst->hw->INTENSET.reg = TRNG_INTENSET_DATARDY;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Gets the status of a job
+ *
+ * Gets the status of an ongoing or the last job.
+ *
+ * \param [in]  module_inst Pointer to the TRNG software instance struct
+ * \param [in]  type        Type of job to abort
+ *
+ * \return Status of the job.
+ */
+enum status_code trng_get_job_status(
+		struct trng_module *module_inst,
+		enum trng_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == TRNG_JOB_READ_BUFFER) {
+		return module_inst->job_status;
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Aborts an ongoing job
+ *
+ * \param [in]  module_inst Pointer to the TRNG software instance struct
+ * \param [in]  type        Type of job to abort
+ */
+void trng_abort_job(
+		struct trng_module *module_inst,
+		enum trng_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == TRNG_JOB_READ_BUFFER) {
+		/* Disable interrupt */
+		module_inst->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
+		/* Mark job as aborted */
+		module_inst->job_status = STATUS_ABORTED;
+		module_inst->remaining_number = 0;
+	}
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.h
new file mode 100644
index 0000000000..ee2e53f42a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.h
@@ -0,0 +1,158 @@
+/**
+ * \file
+ *
+ * \brief SAM True Random Number Generator (TRNG) Driver
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TRNG_CALLBACK_H_INCLUDED
+#define TRNG_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_trng_group
+ *
+ * @{
+ */
+
+#include <trng.h>
+
+/**
+ * Enum for the possible types of TRNG asynchronous jobs that may be issued to
+ * the driver.
+ */
+enum trng_job_type {
+	/** Asynchronous TRNG read into a user provided buffer */
+	TRNG_JOB_READ_BUFFER,
+};
+
+/**
+ * \name Callback Management
+ * @{
+ */
+enum status_code trng_register_callback(
+		struct trng_module *const module,
+		trng_callback_t callback_func,
+		enum trng_callback callback_type);
+
+enum status_code trng_unregister_callback(
+		struct trng_module *module,
+		enum trng_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by \ref
+ * trng_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are met.
+ *
+ * \param[in]     module        Pointer to TRNG software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+static inline void trng_enable_callback(
+		struct trng_module *const module,
+		enum trng_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->enable_callback_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback function registered by the \ref
+ * trng_register_callback.
+ *
+ * \param[in]     module        Pointer to TRNG software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+static inline void trng_disable_callback(
+		struct trng_module *const module,
+		enum trng_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->enable_callback_mask &= ~(1UL << callback_type);
+
+	/* Disable data ready interrupt */
+	if (callback_type == TRNG_CALLBACK_READ_BUFFER) {
+		module->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
+	}
+}
+
+/** @} */
+
+/**
+ * \name Job Management
+ * @{
+ */
+enum status_code trng_read_buffer_job(
+		struct trng_module *const module_inst,
+		uint32_t *buffer,
+		uint32_t number);
+
+enum status_code trng_get_job_status(
+		struct trng_module *module_inst,
+		enum trng_job_type type);
+
+void trng_abort_job(
+		struct trng_module *module_inst,
+		enum trng_job_type type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TRNG_CALLBACK_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.c
new file mode 100644
index 0000000000..0a5f1acbfe
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.c
@@ -0,0 +1,250 @@
+/**
+ * \file
+ *
+ * \brief SAM Temperature Sensor (TSENS) Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "tsens.h"
+
+#define WINDOW_MIN_VALUE    -40
+#define WINDOW_MAX_VALUE    105
+
+/**
+ * \internal Writes an TSENS configuration to the hardware module
+ *
+ * Writes out a given TSENS module configuration to the hardware module.
+ *
+ * \param[in]  config       Pointer to configuration struct
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               The configuration was successful
+ * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
+ */
+static enum status_code _tsens_set_config(struct tsens_config *const config)
+{
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(TSENS_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(TSENS_GCLK_ID);
+
+	/* Configure run in standby */
+	TSENS->CTRLA.reg = (config->run_in_standby << TSENS_CTRLA_RUNSTDBY_Pos);
+
+	/* Check validity of window thresholds */
+	if (config->window.window_mode != TSENS_WINDOW_MODE_DISABLE) {
+		if((config->window.window_lower_value < WINDOW_MIN_VALUE) || \
+			(config->window.window_upper_value > WINDOW_MAX_VALUE)) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+	}
+
+	/* Configure CTRLC */
+	TSENS->CTRLC.reg =
+			(config->free_running << TSENS_CTRLC_FREERUN_Pos) | \
+			(config->window.window_mode);
+
+#if ERRATA_14476
+	/* Configure lower threshold */
+	TSENS->WINLT.reg = TSENS_WINLT_WINLT(config->window.window_upper_value);
+
+	/* Configure upper threshold */
+	TSENS->WINUT.reg = TSENS_WINLT_WINLT(config->window.window_lower_value);
+#else
+	/* Configure lower threshold */
+	TSENS->WINLT.reg = TSENS_WINLT_WINLT(config->window.window_lower_value);
+
+	/* Configure upper threshold */
+	TSENS->WINUT.reg = TSENS_WINLT_WINLT(config->window.window_upper_value);
+#endif
+
+	/* Configure events */
+	TSENS->EVCTRL.reg = config->event_action;
+
+	/* Disable all interrupts */
+	TSENS->INTENCLR.reg =
+			(1 << TSENS_INTENCLR_OVF_Pos) | (1 << TSENS_INTENCLR_WINMON_Pos) | \
+			(1 << TSENS_INTENCLR_OVERRUN_Pos) | (1 << TSENS_INTENCLR_RESRDY_Pos);
+
+	/* Read calibration from NVM */
+	uint32_t tsens_bits = *((uint32_t *)NVMCTRL_TEMP_LOG);
+	uint32_t tsens_tcal = \
+				((tsens_bits & TSENS_FUSES_TCAL_Msk) >> TSENS_FUSES_TCAL_Pos);
+	uint32_t tsens_fcal = \
+				((tsens_bits & TSENS_FUSES_FCAL_Msk) >> TSENS_FUSES_FCAL_Pos);
+
+	TSENS->CAL.reg = TSENS_CAL_TCAL(tsens_tcal) | TSENS_CAL_FCAL(tsens_fcal);
+	TSENS->GAIN.reg = TSENS_GAIN_GAIN(config->calibration.gain);
+	TSENS->OFFSET.reg = TSENS_OFFSET_OFFSETC(config->calibration.offset);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the TSENS.
+ *
+ * Initializes the TSENS device struct and the hardware module based on the
+ * given configuration struct values.
+ *
+ * \param[in]  config      Pointer to the configuration struct
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK                The initialization was successful
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) were provided
+ * \retval STATUS_BUSY              The module is busy with a reset operation
+ * \retval STATUS_ERR_DENIED        The module is enabled
+ */
+enum status_code tsens_init(struct tsens_config *config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_TSENS);
+
+	if (TSENS->CTRLA.reg & TSENS_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	if (TSENS->CTRLA.reg & TSENS_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Write configuration to module */
+	return _tsens_set_config(config);
+}
+
+/**
+ * \brief Initializes an TSENS configuration structure to defaults.
+ *
+ * Initializes a given TSENS configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li GCLK generator 0 (GCLK main) clock source
+ *  \li All events (input and generation) disabled
+ *  \li Free running disabled
+ *  \li Run in standby disabled
+ *  \li Window monitor disabled
+ *  \li Register GAIN value
+ *  \li Register OFFSET value
+ *
+ * \note Register GAIN and OFFSET is loaded from NVM, or can also be fixed.
+ * If this bitfield is to be fixed, pay attention to the relationship between GCLK
+ * frequency, GAIN, and resolution. See \ref asfdoc_sam0_tsens_module_overview
+ * "Chapter Module Overview".
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+void tsens_get_config_defaults(struct tsens_config *const config)
+{
+	Assert(config);
+	config->clock_source                  = GCLK_GENERATOR_0;
+	config->free_running                  = false;
+	config->run_in_standby                = false;
+	config->window.window_mode            = TSENS_WINDOW_MODE_DISABLE;
+	config->window.window_upper_value     = 0;
+	config->window.window_lower_value     = 0;
+	config->event_action                  = TSENS_EVENT_ACTION_DISABLED;
+
+	uint32_t tsens_bits[2];
+	tsens_bits[0] = *((uint32_t *)NVMCTRL_TEMP_LOG);
+	tsens_bits[1] = *(((uint32_t *)NVMCTRL_TEMP_LOG) + 1);
+	config->calibration.offset   = \
+		((tsens_bits[0] & TSENS_FUSES_OFFSET_Msk) >> TSENS_FUSES_OFFSET_Pos);
+	config->calibration.gain     = \
+		((tsens_bits[0] & TSENS_FUSES_GAIN_0_Msk) >> TSENS_FUSES_GAIN_0_Pos) | \
+		((tsens_bits[1] & TSENS_FUSES_GAIN_1_Msk) >> TSENS_FUSES_GAIN_1_Pos);
+}
+
+/**
+ * \brief Reads the TSENS result.
+ *
+ * Reads the result from a TSENS conversion that was previously started.
+ *
+ * \param[out] result       Pointer to store the result value in
+ *
+ * \return Status of the TSENS read request.
+ * \retval STATUS_OK           The result was retrieved successfully
+ * \retval STATUS_BUSY         A conversion result was not ready
+ * \retval STATUS_ERR_OVERFLOW The result register has been overwritten by the
+ *                             TSENS module before the result was read by the software
+ */
+enum status_code tsens_read(int32_t *result)
+{
+	Assert(result);
+
+	if (!(tsens_get_status() & TSENS_STATUS_RESULT_READY)) {
+		/* Result not ready */
+		return STATUS_BUSY;
+	}
+
+	if (TSENS->STATUS.reg & TSENS_STATUS_OVF) {
+		/* The result is not valid */
+		return STATUS_ERR_BAD_DATA;
+	}
+
+	/* Get TSENS result */
+	uint32_t temp = TSENS->VALUE.reg;
+	if(temp & 0x00800000) {
+		temp |= ~TSENS_VALUE_MASK;
+	}
+#if (ERRATA_14476)
+	*result = temp * (-1);
+#endif
+
+	/* Reset ready flag */
+	tsens_clear_status(TSENS_STATUS_RESULT_READY);
+
+	if (tsens_get_status() & TSENS_STATUS_OVERRUN) {
+		tsens_clear_status(TSENS_STATUS_OVERRUN);
+		return STATUS_ERR_OVERFLOW;
+	}
+
+	return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.h
new file mode 100644
index 0000000000..2131eb2fde
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.h
@@ -0,0 +1,625 @@
+/**
+ * \file
+ *
+ * \brief SAM Temperature Sensor (TSENS) Driver
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TSENS_H_INCLUDED
+#define TSENS_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_tsens_group SAM Temperature Sensor (TSENS) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's
+ * Configurable Custom Logic functionality.
+ *
+ * The following peripheral is used by this module:
+ *  - TSENS (Temperature Sensor)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_tsens_prerequisites
+ *  - \ref asfdoc_sam0_tsens_module_overview
+ *  - \ref asfdoc_sam0_tsens_special_considerations
+ *  - \ref asfdoc_sam0_tsens_extra_info
+ *  - \ref asfdoc_sam0_tsens_examples
+ *  - \ref asfdoc_sam0_tsens_api_overview
+ *
+ *
+ * \section asfdoc_sam0_tsens_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_tsens_module_overview Module Overview
+ *
+ * The Temperature Sensor (TSENS) can be used to accurately measure the operating
+ * temperature of the device. TSENS accurately measures the operating
+ * temperature of the device by comparing the difference in two temperature
+ * dependent frequencies to a known frequency. The frequency of the
+ * temperature dependent oscillator (TOSC) is measured twice: first with the
+ * min configuration and next with the maximum configuration. The resulting signed
+ * value is proportional to the temperature and is corrected for offset by the
+ * contents of the OFFSET register.
+ *
+ * Accurately measures a temperature:
+ *  - 卤1掳C over 0掳C ~ 60掳C
+ *  - 卤3掳C over -40掳C ~ 85掳C
+ *  - 卤5掳C over -40掳C ~ 105掳C
+ *
+ * The number of periods of GCLK_TSENS used for the measurement is defined by
+ * the GAIN register. The width of the resulting pulse is measured using a
+ * counter clocked by GCLK_TSENS in the up direction for the 1<SUP>st</SUP> phase and in
+ * the down 2<SUP>nd</SUP> phase. Register GAIN and OFFSET is loaded from NVM, or can also
+ * be fixed by user.
+ * \f[
+ *    VALUE = OFFSET + (\frac{f_{TOSCMIN} - f_{TOSCMAX}}{f_{GCLK}}) \times GAIN
+ * \f]
+ *
+ * \note If fix this bitfield, the relationship between GCLK frequency, GAIN
+ * and resolution as below:
+ * <table>
+ *  <tr>
+ *	  <th>Resolution (#/掳C)</th>
+ *	  <th>GAIN@48MHz</th>
+ *	  <th>GAIN@40MHz</th>
+ *	</tr>
+ *	<tr>
+ *	  <td>&times;1 (1掳C)</td>
+ *    <td>960</td>
+ *    <td>800</td>
+ *  </tr>
+ *	<tr>
+ *	  <td>&times;10 (0.1掳C)</td>
+ *    <td>9600</td>
+ *    <td>8000</td>
+ *  </tr>
+ *	<tr>
+ *	  <td>&times;100 (0.01掳C)</td>
+ *    <td>96000</td>
+ *    <td>80000</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_tsens_module_overview_window_monitor Window Monitor
+ * The TSENS module window monitor function can be used to automatically
+ * compare the conversion result against a predefined pair of upper and
+ * lower threshold values.
+ *
+ *
+ * \subsection asfdoc_sam0_tsens_module_overview_events Events
+ * Event generation and event actions are configurable in the TSENS.
+ *
+ * The TSENS has one actions that can be triggered upon event reception:
+ * \li Start conversion
+ *
+ * The TSENS can generate the following output event:
+ * \li Window monitor
+ *
+ * If the event actions are enabled in the configuration, any incoming event
+ * will trigger the action.
+ *
+ * If the window monitor event is enabled, an event will be generated
+ * when the configured window condition is detected.
+ *
+ * \section asfdoc_sam0_tsens_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_tsens_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_tsens_extra. This includes:
+ *  - \ref asfdoc_sam0_tsens_extra_acronyms
+ *  - \ref asfdoc_sam0_tsens_extra_dependencies
+ *  - \ref asfdoc_sam0_tsens_extra_errata
+ *  - \ref asfdoc_sam0_tsens_extra_history
+ *
+ *
+ * \section asfdoc_sam0_tsens_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_tsens_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_tsens_api_overview API Overview
+ * @{
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system.h>
+
+/**
+ * The magnitude of the temperature measurement value decreases with increasing
+ * temperature, i.e. it has a negative temperature coefficient.
+ * \ref asfdoc_sam0_tsens_extra_errata "Errata reference: 14476".
+ */
+#define ERRATA_14476       true
+
+/**
+ * \name Module Status Flags
+ *
+ * TSENS status flags, returned by \ref tsens_get_status() and cleared by
+ * \ref tsens_clear_status().
+ *
+ * @{
+ */
+
+/** TSENS result ready. */
+#define TSENS_STATUS_RESULT_READY  (1UL << 0)
+/** TSENS result overwritten before read. */
+#define TSENS_STATUS_OVERRUN       (1UL << 1)
+/** Window monitor match. */
+#define TSENS_STATUS_WINDOW        (1UL << 2)
+/** TSENS result overflows. */
+#define TSENS_STATUS_OVERFLOW      (1UL << 3)
+
+/** @} */
+
+/**
+ * \brief TSENS window monitor mode enum.
+ *
+ * Enum for the possible window monitor modes for the TSENS.
+ *
+ */
+enum tsens_window_mode {
+	/** No window mode */
+	TSENS_WINDOW_MODE_DISABLE          = TSENS_CTRLC_WINMODE_DISABLE,
+	/** RESULT > WINLT */
+	TSENS_WINDOW_MODE_ABOVE            = TSENS_CTRLC_WINMODE_ABOVE,
+	/** RESULT < WINUT */
+	TSENS_WINDOW_MODE_BELOW            = TSENS_CTRLC_WINMODE_BELOW,
+	/** WINLT < RESULT < WINUT */
+	TSENS_WINDOW_MODE_INSIDE           = TSENS_CTRLC_WINMODE_INSIDE,
+	/** !(WINLT < RESULT < WINUT) */
+	TSENS_WINDOW_MODE_OUTSIDE          = TSENS_CTRLC_WINMODE_OUTSIDE,
+	/** VALUE > WINUT with hysteresis to WINLT */
+	TSENS_WINDOW_MODE_HYST_ABOVE       = TSENS_CTRLC_WINMODE_HYST_ABOVE,
+	/** VALUE < WINLT with hysteresis to WINUT */
+	TSENS_WINDOW_MODE_HYST_BELOW       = TSENS_CTRLC_WINMODE_HYST_BELOW,
+};
+
+/**
+ * \brief TSENS event action enum.
+ *
+ * Enum for the possible actions to take on an incoming event.
+ *
+ */
+enum tsens_event_action {
+	/** Event action disabled */
+	TSENS_EVENT_ACTION_DISABLED         = 0,
+	/** Start conversion */
+	TSENS_EVENT_ACTION_START_CONV       = TSENS_EVCTRL_STARTEI,
+};
+
+/**
+ * \brief Window monitor configuration structure.
+ *
+ * Window monitor configuration structure.
+ */
+struct tsens_window_config {
+	/** Selected window mode */
+	enum tsens_window_mode window_mode;
+	/** Lower window value */
+	int32_t window_lower_value;
+	/** Upper window value */
+	int32_t window_upper_value;
+};
+
+/**
+ * \brief TSENS event enable/disable structure.
+ *
+ * Event flags for the TSENS module. This is used to enable and
+ * disable events via \ref tsens_enable_events() and \ref tsens_disable_events().
+ */
+struct tsens_events {
+	/** Enable event generation on window monitor */
+	bool generate_event_on_window_monitor;
+};
+
+/**
+ * \brief Calibration configuration structure.
+ *
+ * Calibration configuration structure.
+ */
+struct tsens_calibration {
+	/** Time amplifier gain */
+	uint32_t gain;
+	/** Offset correction */
+	int32_t offset;
+};
+
+/**
+ * \brief TSENS configuration structure.
+ *
+ * Configuration structure for an TSENS instance. This structure should be
+ * initialized by the \ref tsens_get_config_defaults() function before being
+ * modified by the user application.
+ */
+struct tsens_config {
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+	/** Enables free running mode if true */
+	bool free_running;
+	/** Enables TSENS in standby sleep mode if true */
+	bool run_in_standby;
+	/** Window monitor configuration structure */
+	struct tsens_window_config window;
+	/** Event action to take on incoming event */
+	enum tsens_event_action event_action;
+	/** Calibration value */
+	struct tsens_calibration calibration;
+};
+
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+enum status_code tsens_init(struct tsens_config *config);
+void tsens_get_config_defaults(struct tsens_config *const config);
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \return Bit mask of TSENS status flags.
+ *
+ * \retval TSENS_STATUS_RESULT_READY  TSENS result is ready to be read
+ * \retval TSENS_STATUS_OVERRUN       TSENS result overwritten before read
+ * \retval TSENS_STATUS_WINDOW        TSENS has detected a value inside the set
+ *                                    window range
+ * \retval TSENS_STATUS_OVERFLOW      TSENS result overflows
+ */
+static inline uint32_t tsens_get_status(void)
+{
+	uint32_t int_flags = TSENS->INTFLAG.reg;
+
+	uint32_t status_flags = 0;
+
+	/* Check for TSENS Result Ready */
+	if (int_flags & TSENS_INTFLAG_RESRDY) {
+		status_flags |= TSENS_STATUS_RESULT_READY;
+	}
+
+	/* Check for TSENS Overrun */
+	if (int_flags & TSENS_INTFLAG_OVERRUN) {
+		status_flags |= TSENS_STATUS_OVERRUN;
+	}
+
+	/* Check for TSENS Window Match */
+	if (int_flags & TSENS_INTFLAG_WINMON) {
+		status_flags |= TSENS_STATUS_WINDOW;
+	}
+
+	/* Check for TSENS overflow */
+	if (int_flags & TSENS_INTFLAG_OVF) {
+		status_flags |= TSENS_STATUS_OVERFLOW;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst   Pointer to the TSENS software instance struct
+ * \param[in] status_flags  Bitmask of \c TSENS_STATUS_* flags to clear
+ */
+static inline void tsens_clear_status(const uint32_t status_flags)
+{
+	uint32_t int_flags = 0;
+
+	/* Check for TSENS Result Ready */
+	if (status_flags & TSENS_INTFLAG_RESRDY) {
+		 int_flags |= TSENS_STATUS_RESULT_READY;
+	}
+
+	/* Check for TSENS Overrun */
+	if (status_flags & TSENS_INTFLAG_OVERRUN) {
+		int_flags |= TSENS_STATUS_OVERRUN;
+	}
+
+	/* Check for TSENS Window Match */
+	if (status_flags & TSENS_INTFLAG_WINMON) {
+		int_flags |= TSENS_STATUS_WINDOW;
+	}
+
+	/* Check for TSENS overflow */
+	if (status_flags & TSENS_INTFLAG_OVF) {
+		int_flags |= TSENS_STATUS_OVERFLOW;
+	}
+
+	/* Clear interrupt flag */
+	TSENS->INTFLAG.reg = int_flags;
+}
+
+/** @} */
+
+/**
+ * \name Enable, Disable, and Reset TSENS Module, Start Conversion and Read Result
+ * @{
+ */
+
+/**
+ * \brief Determines if the hardware module is currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+static inline bool tsens_is_syncing(void)
+{
+	if (TSENS->SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Enables the TSENS module.
+ *
+ * Enables an TSENS module that has previously been configured.
+
+ */
+static inline void tsens_enable(void)
+{
+	TSENS->CTRLA.reg |= TSENS_CTRLA_ENABLE;
+
+	while (tsens_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Disables the TSENS module.
+ *
+ * Disables an TSENS module that was previously enabled.
+ *
+ */
+static inline void tsens_disable(void)
+{
+	TSENS->INTENCLR.reg = TSENS_INTENCLR_MASK;
+	TSENS->INTFLAG.reg = TSENS_INTFLAG_MASK;
+	TSENS->CTRLA.reg &= ~TSENS_CTRLA_ENABLE;
+
+	while (tsens_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Resets the TSENS module.
+ *
+ * Resets an TSENS module, clearing all module state and registers to their
+ * default values.
+ *
+ */
+static inline void tsens_reset(void)
+{
+	/* Disable to make sure the pipeline is flushed before reset */
+	tsens_disable();
+
+	/* Software reset the module */
+	TSENS->CTRLA.reg |= TSENS_CTRLA_SWRST;
+
+	while (tsens_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+
+/**
+ * \brief Enables an TSENS event output.
+ *
+ *  Enables one or more input or output events to or from the TSENS module. See
+ *  \ref tsens_events "tsens_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+static inline void tsens_enable_events(struct tsens_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	uint32_t event_mask = 0;
+
+	/* Configure Window Monitor event */
+	if (events->generate_event_on_window_monitor) {
+		event_mask |= TSENS_EVCTRL_WINEO;
+	}
+
+	TSENS->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables an TSENS event output.
+ *
+ *  Disables one or more output events to or from the TSENS module. See
+ *  \ref tsens_events "tsens_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events       Struct containing flags of events to disable
+ */
+static inline void tsens_disable_events(struct tsens_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	uint32_t event_mask = 0;
+
+	/* Configure Window Monitor event */
+	if (events->generate_event_on_window_monitor) {
+		event_mask |= TSENS_EVCTRL_WINEO;
+	}
+
+	TSENS->EVCTRL.reg &= ~event_mask;
+}
+
+/**
+ * \brief Start a TSENS conversion.
+ *
+ * Start a new TSENS conversion.
+ *
+ */
+static inline void tsens_start_conversion(void)
+{
+	TSENS->CTRLB.reg |= TSENS_CTRLB_START;
+
+	while (tsens_is_syncing()) {
+		/* Wait for synchronization */
+	}
+}
+
+enum status_code tsens_read(int32_t *result);
+/** @} */
+/** @} */
+
+
+/**
+ * \page asfdoc_sam0_tsens_extra Extra Information for TSENS Driver
+ *
+ * \section asfdoc_sam0_tsens_extra_acronyms Acronym
+ * Below is a table listing the acronym used in this module, along with their
+ * intended meaning.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>TSENS</td>
+ *		<td>Temperature Sensor</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_tsens_extra_dependencies Dependencies
+ * This driver has no dependencies.
+ *
+ *
+ * \section asfdoc_sam0_tsens_extra_errata Errata
+ * Errata reference: 14476.
+ *
+ * The magnitude of the temperature measurement value decreases with increasing
+ * temperature, i.e. it has a negative temperature coefficient.
+ *
+ *
+ * \section asfdoc_sam0_tsens_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+  *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_tsens_exqsg Examples for TSENS Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_tsens_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_tsens_basic_use_case
+ *  - \subpage asfdoc_sam0_tsens_basic_use_case_callback
+ *
+ * \page asfdoc_sam0_tsens_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42542A</td>
+ *		<td>12/2015</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TSENS_H_INCLUDED */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.c
new file mode 100644
index 0000000000..ef7fd46ca6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.c
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief SAM Temperature Sensor Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "tsens_callback.h"
+
+struct tsens_module *_tsens_instances;
+
+/** Interrupt handler for the TSENS module. */
+void TSENS_Handler(void)
+{
+	struct tsens_module *module = _tsens_instances;
+	Assert(module);
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = TSENS->INTFLAG.reg;
+
+	/* store TSENS result in job buffer */
+	uint32_t temp = TSENS->VALUE.reg;
+	if(temp & 0x00800000) {
+		temp |= ~TSENS_VALUE_MASK;
+	}
+#if (ERRATA_14476)
+	*(module->value) = temp * (-1);
+#endif
+
+	for(uint8_t i = 0; i < TSENS_CALLBACK_NUM; i++)
+	{
+		if (flags & ((uint32_t)0x01 << i)) {
+			/* Clear the INTFLAG anyway */
+			TSENS->INTFLAG.reg = (uint32_t)0x01 << i;
+
+			if(module->callback[i] != NULL) {
+				module->callback[i]((enum tsens_callback)i);
+			}
+		}
+	}
+}
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by for the interrupt handler to call it
+ * when the condition for the callback is met.
+ *
+ * \param[in] module         Pointer to TSENS software instance struct
+ * \param[in] callback_func  Pointer to callback function
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+enum status_code tsens_register_callback(
+		struct tsens_module *const module,
+		tsens_callback_t callback_func,
+		enum tsens_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	if(callback_type > TSENS_CALLBACK_NUM) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+	_tsens_instances = module;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in] module         Pointer to TSENS software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+enum status_code tsens_unregister_callback(
+		struct tsens_module *const module,
+		enum tsens_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	if(callback_type > TSENS_CALLBACK_NUM) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Register callback function */
+	module->callback[callback_type] = NULL;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Read result from TSENS.
+ *
+ * \param[in]  module_inst  Pointer to the TSENS software instance struct
+ * \param[out] result       Pointer to store the TSENS result
+ *
+ */
+void tsens_read_job(
+		struct tsens_module *const module_inst,
+		int32_t *result)
+{
+	Assert(module_inst);
+	Assert(result);
+
+	module_inst->value = result;
+
+	if(!(TSENS->CTRLC.reg & TSENS_CTRLC_FREERUN)) {
+		tsens_start_conversion();
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.h
new file mode 100644
index 0000000000..9ce6635707
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.h
@@ -0,0 +1,198 @@
+/**
+ * \file
+ *
+ * \brief SAM Temperature Sensor Driver
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TSENS_CALLBACK_H_INCLUDED
+#define TSENS_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system_interrupt.h>
+#include "tsens.h"
+
+/**
+ * \addtogroup asfdoc_sam0_tsens_group
+ *
+ * @{
+ */
+
+/**
+ * \brief TSENS Callback Types.
+ *
+ * Callback types for TSENS callback driver.
+ *
+ */
+enum tsens_callback {
+	/** Callback for result ready */
+	TSENS_CALLBACK_RESULT_READY,
+	/** Callback when result overwritten before read */
+	TSENS_CALLBACK_OVERRUN,
+	/** Callback when window is hit */
+	TSENS_CALLBACK_WINDOW,
+	/** Callback when the result overflows */
+	TSENS_CALLBACK_OVF,
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	TSENS_CALLBACK_NUM,
+#  endif
+};
+
+/** Type of the callback functions. */
+typedef void (*tsens_callback_t)(enum tsens_callback);
+
+/**
+ * \brief TSENS software device instance structure.
+ *
+ * TSENS software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct tsens_module {
+#if !defined(__DOXYGEN__)
+	/** Array to store callback functions. */
+	tsens_callback_t callback[TSENS_CALLBACK_NUM];
+	/** Pointer to used for TSENS results. */
+	volatile int32_t *value;
+#endif
+};
+
+/**
+ * \name Callback Management
+ * @{
+ */
+enum status_code tsens_register_callback(
+			struct tsens_module *const module,
+			tsens_callback_t callback_func,
+			enum tsens_callback callback_type);
+
+enum status_code tsens_unregister_callback(
+			struct tsens_module *const module,
+			enum tsens_callback callback_type);
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback function registered by \ref
+ * tsens_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are met.
+ *
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ */
+static inline void tsens_enable_callback(enum tsens_callback callback_type)
+{
+	uint32_t inenset_temp = 0;
+
+	switch (callback_type) {
+		case TSENS_CALLBACK_RESULT_READY:
+			inenset_temp |= TSENS_INTFLAG_RESRDY;
+			break;
+		case TSENS_CALLBACK_OVERRUN:
+			inenset_temp |= TSENS_INTENSET_OVERRUN;
+			break;
+		case TSENS_CALLBACK_WINDOW:
+			inenset_temp |= TSENS_INTENSET_WINMON;
+			break;
+		case TSENS_CALLBACK_OVF:
+			inenset_temp |= TSENS_INTENSET_OVF;
+			break;
+
+		default:
+			break;
+	}
+
+	/* Enable the interrupt for the callback */
+	TSENS->INTENSET.reg = inenset_temp;
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback function registered by the \ref
+ * tsens_register_callback.
+ *
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ */
+static inline void tsens_disable_callback(enum tsens_callback callback_type)
+{
+	uint32_t inenclr_temp = 0;
+
+	switch (callback_type) {
+		case TSENS_CALLBACK_RESULT_READY:
+			inenclr_temp |= TSENS_INTENCLR_OVERRUN;
+			break;
+		case TSENS_CALLBACK_OVERRUN:
+			inenclr_temp |= TSENS_INTENSET_OVERRUN;
+			break;
+		case TSENS_CALLBACK_WINDOW:
+			inenclr_temp |= TSENS_INTENSET_WINMON;
+			break;
+		case TSENS_CALLBACK_OVF:
+			inenclr_temp |= TSENS_INTENSET_OVF;
+			break;
+
+		default:
+			break;
+	}
+
+	/* Disable the interrupt for the callback */
+	TSENS->INTENCLR.reg = inenclr_temp;
+}
+
+void tsens_read_job(struct tsens_module *const module_inst, int32_t *result);
+/** @} */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TSENS_CALLBACK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.c
new file mode 100644
index 0000000000..057fd1cfb6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.c
@@ -0,0 +1,828 @@
+/**
+ * \file
+ *
+ * \brief SAM UART Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "uart.h"
+
+/**
+ * \internal
+ * Internal driver device instance struct.
+ */
+struct uart_module *_uart_instances[UART_INST_NUM];
+
+/**
+ * \internal
+ * Writes a character from the TX buffer to the Data register.
+ *
+ * \param[in,out]  module  Pointer to UART software instance struct
+ */
+static void _uart_write(struct uart_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	Uart *const uart_hw = module->hw;
+
+	/* Write value will be at least 8-bits long */
+	uint8_t data_to_send = *(module->tx_buffer_ptr);
+	/* Increment 8-bit pointer */
+	(module->tx_buffer_ptr)++;
+
+	/* Write the data to send*/
+	uart_hw->TRANSMIT_DATA.reg = data_to_send & UART_TRANSMIT_DATA_MASK;
+
+	/* Decrement remaining buffer length */
+	(module->remaining_tx_buffer_length)--;
+}
+
+/**
+ * \internal
+ * Reads a character from the Data register to the RX buffer.
+ *
+ * \param[in,out]  module  Pointer to UART software instance struct
+ */
+static void _uart_read(
+		struct uart_module *const module)
+{
+	/* Pointer to the hardware module instance */
+	Uart *const uart_hw = module->hw;
+
+	uint16_t received_data = (uart_hw->RECEIVE_DATA.reg & UART_RECEIVE_DATA_MASK);
+
+	/* Read value will be at least 8-bits long */
+	*(module->rx_buffer_ptr) = received_data;
+	/* Increment 8-bit pointer */
+	module->rx_buffer_ptr += 1;
+
+	/* Decrement length of the remaining buffer */
+	module->remaining_rx_buffer_length--;
+}
+
+static void uart_rx0_isr_handler(void)
+{
+	struct uart_module *module = _uart_instances[0];
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->RECEIVE_STATUS.reg;
+	if (flags & UART_RECEIVE_STATUS_FIFO_OVERRUN) {
+		/* Store the error code */
+		module->status = STATUS_ERR_OVERFLOW;
+		/* Disable interrupt */
+		module->hw->RX_INTERRUPT_MASK.reg &=
+			~(UART_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
+			SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+		if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) &&
+			(module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN))) {
+			(module->callback[UART_RX_FIFO_OVERRUN])(module);
+		}
+		/* Flush */
+		uint8_t flush = module->hw->RECEIVE_DATA.reg;
+		UNUSED(flush);
+	}
+	if (flags & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
+		_uart_read(module);
+		if (module->remaining_rx_buffer_length == 0) {
+			if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) &&
+				(module->callback_reg_mask & (1 << UART_RX_COMPLETE))) {
+				module->status = STATUS_OK;
+				module->hw->RX_INTERRUPT_MASK.reg &=
+					~(UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+				(module->callback[UART_RX_COMPLETE])(module);
+			}
+		}
+	}
+}
+
+static void uart_tx0_isr_handler(void)
+{
+	struct uart_module *module = _uart_instances[0];
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
+	if (flags & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL) {
+		_uart_write(module);
+		if (module->remaining_tx_buffer_length == 0) {
+			module->hw->TX_INTERRUPT_MASK.reg &=
+					~UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+			module->hw->TX_INTERRUPT_MASK.reg |=
+					UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+		}
+	}
+	if (flags & UART_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
+		if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) &&
+			(module->callback_reg_mask & (1 << UART_TX_COMPLETE))) {
+			module->status = STATUS_OK;
+			/* Disable interrupt */
+			module->hw->TX_INTERRUPT_MASK.reg &=
+				~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+			(module->callback[UART_TX_COMPLETE])(module);
+		}
+
+	}
+	if (flags & UART_TRANSMIT_STATUS_CTS_ACTIVE) {
+		if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) &&
+			(module->callback_reg_mask & (1 << UART_CTS_ACTIVE))) {
+			(module->callback[UART_CTS_ACTIVE])(module);
+		}
+
+	}
+}
+
+static void uart_rx1_isr_handler(void)
+{
+	struct uart_module *module = _uart_instances[1];
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->RECEIVE_STATUS.reg;
+	if (flags & UART_RECEIVE_STATUS_FIFO_OVERRUN) {
+		/* Store the error code */
+		module->status = STATUS_ERR_OVERFLOW;
+		/* Disable interrupt */
+		module->hw->RX_INTERRUPT_MASK.reg &=
+			~(UART_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
+			SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+		if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) &&
+			(module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN))) {
+			(module->callback[UART_RX_FIFO_OVERRUN])(module);
+		}
+		/* Flush */
+		uint8_t flush = module->hw->RECEIVE_DATA.reg;
+		UNUSED(flush);
+	}
+	if (flags & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
+		_uart_read(module);
+		if (module->remaining_rx_buffer_length == 0) {
+			if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) &&
+				(module->callback_reg_mask & (1 << UART_RX_COMPLETE))) {
+				module->status = STATUS_OK;
+				module->hw->RX_INTERRUPT_MASK.reg &=
+					~(UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+				(module->callback[UART_RX_COMPLETE])(module);
+			}
+		}
+	}
+}
+
+static void uart_tx1_isr_handler(void)
+{
+	struct uart_module *module = _uart_instances[1];
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
+	if (flags & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL) {
+		_uart_write(module);
+		if (module->remaining_tx_buffer_length == 0) {
+			module->hw->TX_INTERRUPT_MASK.reg &=
+					~UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+			module->hw->TX_INTERRUPT_MASK.reg |=
+					UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+		}
+	}
+	if (flags & UART_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
+		if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) &&
+			(module->callback_reg_mask & (1 << UART_TX_COMPLETE))) {
+			module->status = STATUS_OK;
+			/* Disable interrupt */
+			module->hw->TX_INTERRUPT_MASK.reg &=
+				~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+			(module->callback[UART_TX_COMPLETE])(module);
+		}
+
+	}
+	if (flags & UART_TRANSMIT_STATUS_CTS_ACTIVE) {
+		if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) &&
+			(module->callback_reg_mask & (1 << UART_CTS_ACTIVE))) {
+			(module->callback[UART_CTS_ACTIVE])(module);
+		}
+
+	}
+}
+
+static void uart_set_baudrate(struct uart_module *const module,
+		const uint32_t baud_rate)
+{
+	uint32_t clock;
+	uint16_t integerpart = 0;
+	uint8_t fractionalpart = 0;
+	uint32_t diff;
+	uint8_t i = 0;
+
+	clock = system_clock_get_value();
+	integerpart = clock / baud_rate;
+	diff = clock - (baud_rate * integerpart);
+	i = 0;
+	while(diff > (baud_rate / 16)) {
+		i++;
+		diff -= (baud_rate / 16);
+	}
+	fractionalpart = (i + 1) / 2;
+
+	module->hw->UART_CLOCK_SOURCE.reg = UART_CLOCK_SOURCE_CLOCK_SELECT_0;
+	module->hw->UART_BAUD_RATE.reg =
+		UART_BAUD_RATE_INTEGER_DIVISION(integerpart) |
+		UART_BAUD_RATE_FRACTIONAL_DIVISION(fractionalpart);
+}
+
+/**
+ * \brief Gets the UART default configurations
+ *
+ * Use to initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Baudrate 115200
+ * - parity   UART_NO_PARITY
+ * - flow_control 0 - No Flow control
+ * - stop_bits 1 - 1 stop bit
+ * - pinmux_pad[] - Pinmux default are UART0.
+ *
+ * \param[out] config  Pointer to configuration structure to be initiated
+ */
+void uart_get_config_defaults(
+		struct uart_config *const config)
+{
+	config->baud_rate = 115200;
+	config->data_bits = UART_8_BITS;
+	config->stop_bits = UART_1_STOP_BIT;
+	config->parity = UART_NO_PARITY;
+	config->flow_control = false;
+
+	config->pin_number_pad[0] = PIN_LP_GPIO_2;
+	config->pin_number_pad[1] = PIN_LP_GPIO_3;
+	config->pin_number_pad[2] = PIN_LP_GPIO_4;
+	config->pin_number_pad[3] = PIN_LP_GPIO_5;
+
+	config->pinmux_sel_pad[0] = MUX_LP_GPIO_2_UART0_RXD;
+	config->pinmux_sel_pad[1] = MUX_LP_GPIO_3_UART0_TXD;
+	config->pinmux_sel_pad[2] = MUX_LP_GPIO_4_UART0_CTS;
+	config->pinmux_sel_pad[3] = MUX_LP_GPIO_5_UART0_RTS;
+}
+
+/**
+ * \brief Initializes the device
+ *
+ * Initializes the UART device based on the setting specified in the
+ * configuration struct.
+ *
+ * \param[in]  module  enumeration UART hw module
+ * \param[in]  hw      Pointer to USART hardware instance
+ * \param[in]  config  Pointer to configuration struct
+ *
+ * \return Status of the initialization.
+ *
+ * \retval STATUS_OK                       The initialization was successful
+ */
+enum status_code uart_init(struct uart_module *const module, Uart * const hw,
+		const struct uart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	uint8_t config_temp = 0;
+	uint8_t i,index;
+
+	/* Assign module pointer to software instance struct */
+	module->hw = hw;
+
+	for (i = 0; i < UART_CALLBACK_N; i++) {
+		module->callback[i] = NULL;
+	}
+	module->rx_buffer_ptr = NULL;
+	module->tx_buffer_ptr = NULL;
+	module->remaining_rx_buffer_length = 0;
+	module->remaining_tx_buffer_length = 0;
+	module->callback_reg_mask = 0;
+	module->callback_enable_mask = 0;
+	module->status = STATUS_OK;
+
+	if (hw == UART0) {
+		system_peripheral_reset(PERIPHERAL_UART0_CORE);
+		system_peripheral_reset(PERIPHERAL_UART0_IF);
+		system_clock_peripheral_enable(PERIPHERAL_UART0_CORE);
+		system_clock_peripheral_enable(PERIPHERAL_UART0_IF);
+		_uart_instances[0] = module;
+		system_register_isr(RAM_ISR_TABLE_UARTRX0_INDEX, (uint32_t)uart_rx0_isr_handler);
+		system_register_isr(RAM_ISR_TABLE_UARTTX0_INDEX, (uint32_t)uart_tx0_isr_handler);
+		NVIC_EnableIRQ(UART0_RX_IRQn);
+		NVIC_EnableIRQ(UART0_TX_IRQn);
+	} else if (hw == UART1) {
+		system_peripheral_reset(PERIPHERAL_UART1_CORE);
+		system_peripheral_reset(PERIPHERAL_UART1_IF);
+		system_clock_peripheral_enable(PERIPHERAL_UART1_CORE);
+		system_clock_peripheral_enable(PERIPHERAL_UART1_IF);
+		_uart_instances[1] = module;
+		system_register_isr(RAM_ISR_TABLE_UARTRX1_INDEX, (uint32_t)uart_rx1_isr_handler);
+		system_register_isr(RAM_ISR_TABLE_UARTTX1_INDEX, (uint32_t)uart_tx1_isr_handler);
+		NVIC_EnableIRQ(UART1_RX_IRQn);
+		NVIC_EnableIRQ(UART1_TX_IRQn);
+	}
+
+	/* Set the pinmux for this UART module. */
+	if(config->flow_control) {
+		index = 4;
+	} else {
+		index = 2;
+	}
+
+#if (BTLC1000)
+    index = 2;  /* BTLC1000 has no flow control function. */
+#endif
+
+	for(i = 0; i < index; i++) {
+		gpio_pinmux_cofiguration(config->pin_number_pad[i], \
+								(uint16_t)(config->pinmux_sel_pad[i]));
+	}
+
+	/* empty UART FIFO */
+	while (module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
+		i = module->hw->RECEIVE_DATA.reg;
+	}
+	
+	/* reset configuration register */
+	module->hw->UART_CONFIGURATION.reg = 0;
+
+	/* program the uart configuration. */
+	if(config->flow_control) {
+		config_temp |= UART_CONFIGURATION_CTS_ENABLE_1;
+	}
+	config_temp |= config->data_bits;
+	config_temp |= config->stop_bits;
+	switch(config->parity) {
+		case UART_NO_PARITY:
+			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_0;
+			break;
+
+		case UART_EVEN_PARITY:
+			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
+			config_temp |= UART_CONFIGURATION_PARITY_MODE_0;
+			break;
+
+		case UART_ODD_PARITY:
+			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
+			config_temp |= UART_CONFIGURATION_PARITY_MODE_1;
+			break;
+
+		case UART_SPACE_PARITY:
+			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
+			config_temp |= UART_CONFIGURATION_PARITY_MODE_2;
+			break;
+
+		case UART_MARK_PARITY:
+			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
+			config_temp |= UART_CONFIGURATION_PARITY_MODE_3;
+			break;
+
+		default:
+			break;
+	}	
+	module->hw->UART_CONFIGURATION.reg = config_temp;
+
+	/* Calculate the baud rate. */
+	uart_set_baudrate(module, config->baud_rate);
+
+	module->hw->RX_INTERRUPT_MASK.reg = 0;	// disable int at initialization, enable it at read time
+	module->hw->TX_INTERRUPT_MASK.reg = 0;	// disable int at initialization, enable it at write time
+	
+	return STATUS_OK;
+}
+
+/**
+* \brief Transmit a character via the UART
+*
+* This blocking function will transmit a single character via the
+* UART.
+*
+* \param[in]  module  enumeration UART hw module
+* \param[in]  tx_data  Data to transfer
+*
+* \return Status of the operation.
+* \retval STATUS_OK         If the operation was completed
+*/
+enum status_code uart_write_wait(struct uart_module *const module,
+		const uint8_t tx_data)
+{
+	while (!(module->hw->TRANSMIT_STATUS.reg & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL));
+
+	module->hw->TRANSMIT_DATA.reg = tx_data;
+	
+	return STATUS_OK;
+}
+
+/**
+* \brief Receive a character via the UART
+*
+* This blocking function will receive a character via the UART.
+*
+* \param[in]   module  enumeration UART hw module
+* \param[out]  rx_data  Pointer to received data
+*
+* \return Status of the operation.
+* \retval STATUS_OK                If the operation was completed
+*/
+enum status_code uart_read_wait(struct uart_module *const module,
+		uint8_t *const rx_data)
+{
+	while (!(module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY));
+
+	*rx_data = module->hw->RECEIVE_DATA.reg;
+	
+	return STATUS_OK;
+}
+
+/**
+* \brief Transmit a buffer of characters via the UART
+*
+* This blocking function will transmit a block of \c length characters
+* via the UART.
+*
+* \note Using this function in combination with the interrupt (\c _job) functions is
+*       not recommended as it has no functionality to check if there is an
+*       ongoing interrupt driven operation running or not.
+*
+* \param[in]  module  enumeration UART hw module
+* \param[in]  tx_data  Pointer to data to transmit
+* \param[in]  length   Number of characters to transmit
+* 
+* \return Status of the operation.
+* \retval STATUS_OK              If operation was completed
+*/
+enum status_code uart_write_buffer_wait(struct uart_module *const module, 
+		const uint8_t *tx_data, uint32_t length)
+{
+	while(length--)
+		uart_write_wait(module, *tx_data++);
+	
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a buffer of \c length characters via the UART
+ *
+ * This blocking function will receive a block of \c length characters
+ * via the UART.
+ *
+ * \note Using this function in combination with the interrupt (\c *_job)
+ *       functions is not recommended as it has no functionality to check if
+ *       there is an ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module  enumeration UART hw module
+ * \param[out] rx_data  Pointer to receive buffer
+ * \param[in]  length   Number of characters to receive
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If operation was completed
+ */
+enum status_code uart_read_buffer_wait(struct uart_module *const module,
+		uint8_t *rx_data, uint16_t length)
+{
+	while(length--)
+		uart_read_wait(module, rx_data++);
+	
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Starts write of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to UART software instance struct
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+static void _uart_write_buffer(
+		struct uart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(tx_data);
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+	module->tx_buffer_ptr = tx_data;
+	module->status = STATUS_BUSY;
+
+	module->hw->TX_INTERRUPT_MASK.reg = UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+}
+
+/**
+ * \internal
+ * Setup UART to read a buffer with a given length
+ *
+ * \param[in]  module   Pointer to UART software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  length   Length of data buffer
+ *
+ */
+static void _uart_read_buffer(
+		struct uart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	Assert(module);
+	Assert(rx_data);
+
+	/* Set length for the buffer and the pointer, and let
+	 * the interrupt handler do the rest */
+	module->remaining_rx_buffer_length = length;
+	module->rx_buffer_ptr = rx_data;
+	module->status = STATUS_BUSY;
+
+	module->hw->RX_INTERRUPT_MASK.reg = UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+}
+
+/**
+ * \brief Asynchronous buffer write
+ *
+ * Sets up the driver to write to the UART from a given buffer. If registered
+ * and enabled, a callback function will be called when the write is finished.
+ *
+ * \param[in]  module   Pointer to UART software instance struct
+ * \param[out] tx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \returns Status of the write request operation.
+ * \retval STATUS_OK               If the operation completed successfully
+ * \retval STATUS_ERR_BUSY         If the UART was already busy with a write
+ *                                 operation
+ * \retval STATUS_ERR_INVALID_ARG  If requested write length was zero
+ */
+enum status_code uart_write_buffer_job(struct uart_module *const module,
+		uint8_t *tx_data, uint32_t length)
+{
+	Assert(module);
+	Assert(tx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check if the UART is busy transmitting or slave waiting for TXC*/
+	if (module->status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Issue internal write */
+	_uart_write_buffer(module, tx_data, length);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Asynchronous buffer read
+ *
+ * Sets up the driver to read from the UART to a given buffer. If registered
+ * and enabled, a callback function will be called when the read is finished.
+ *
+ * \note If address matching is enabled for the slave, the first character
+ *       received and placed in the RX buffer will be the address.
+ *
+ * \param[in]  module   Pointer to UART software instance struct
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ * \param[in]  dummy    Dummy character to send when reading in master mode
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK               If the operation completed successfully
+ * \retval  STATUS_ERR_BUSY         If the UART was already busy with a read
+ *                                  operation
+ * \retval  STATUS_ERR_DENIED       If the receiver is not enabled
+ * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
+ */
+enum status_code uart_read_buffer_job(struct uart_module *const module,
+		uint8_t *rx_data, uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check if the UART is busy transmitting or slave waiting for TXC*/
+	if (module->status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Issue internal read */
+	_uart_read_buffer(module, rx_data, length);
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref uart_enable_callback,
+ *       in order for the interrupt handler to call it when the conditions for
+ *       the callback type are met.
+ *
+ * \param[in]  module         Pointer to UART software instance struct
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void uart_register_callback(struct uart_module *const module,
+		uart_callback_t callback_func,
+		enum uart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+	/* Set the bit corresponding to the callback_type */
+	module->callback_reg_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in,out]  module         Pointer to UART software instance struct
+ * \param[in]      callback_type  Callback type given by an enum
+ *
+ */
+void uart_unregister_callback(struct uart_module *module,
+		enum uart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+	/* Clear the bit corresponding to the callback_type */
+	module->callback_reg_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref usart_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in]  module         Pointer to UART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+void uart_enable_callback(struct uart_module *const module,
+		enum uart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->callback_enable_mask |= (1 << callback_type);
+
+	if (callback_type == UART_CTS_ACTIVE) {
+		module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK;
+	}
+}
+
+/**
+ * \brief Disable callback
+ *
+ * Disables the callback function registered by the \ref usart_register_callback,
+ * and the callback will not be called from the interrupt routine.
+ *
+ * \param[in]  module         Pointer to UART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+void uart_disable_callback(struct uart_module *const module,
+		enum uart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->callback_enable_mask &= ~(1 << callback_type);
+
+	if (callback_type == UART_CTS_ACTIVE) {
+		module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK;
+	}
+
+}
+
+/**
+ * \brief Enables UART transmit DMA
+ *
+ * \param[in]  module         Pointer to UART software instance struct
+ */
+void uart_enable_transmit_dma(struct uart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* DMA need the interrupt signal to trigger */
+	module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+
+	/* Disable NVIC to avoid trigger the CPU interrupt */
+	if (module->hw == UART0) {
+		NVIC_DisableIRQ(UART0_TX_IRQn);
+	} else if (module->hw == UART1) {
+		NVIC_DisableIRQ(UART1_TX_IRQn);
+	}
+}
+
+/**
+ * \brief Disables UART transmit DMA
+ *
+ * \param[in]  module         Pointer to UART software instance struct
+ */
+void uart_disable_transmit_dma(struct uart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+
+	/* Enable NVIC to restore the callback functions */
+	if (module->hw == UART0) {
+		NVIC_EnableIRQ(UART0_TX_IRQn);
+	} else if (module->hw == UART1) {
+		NVIC_EnableIRQ(UART1_TX_IRQn);
+	}
+}
+
+/**
+ * \brief Enables UART receive DMA
+ *
+ * \param[in]  module         Pointer to UART software instance struct
+ */
+void uart_enable_receive_dma(struct uart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* DMA need the interrupt signal to trigger */
+	module->hw->RX_INTERRUPT_MASK.reg |= UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+
+	/* Disable NVIC to avoid trigger the CPU interrupt */
+	if (module->hw == UART0) {
+		NVIC_DisableIRQ(UART0_TX_IRQn);
+	} else if (module->hw == UART1) {
+		NVIC_DisableIRQ(UART1_TX_IRQn);
+	}
+}
+
+/**
+ * \brief Disables UART receive DMA
+ *
+ * \param[in]  module         Pointer to UART software instance struct
+ */
+void uart_disable_receive_dma(struct uart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	module->hw->RX_INTERRUPT_MASK.reg &= ~UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+
+	/* Enable NVIC to restore the callback functions */
+	if (module->hw == UART0) {
+		NVIC_EnableIRQ(UART0_TX_IRQn);
+	} else if (module->hw == UART1) {
+		NVIC_EnableIRQ(UART1_TX_IRQn);
+	}
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.h
new file mode 100644
index 0000000000..6f17ab4a1b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.h
@@ -0,0 +1,370 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM UART Driver for SAMB11
+ *
+ * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef UART_H_INCLUDED
+#define UART_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_uart_group SAM UART Driver (UART)
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the
+ * configuration and management of the device's Universal Asynchronous
+ * Receiver/Transmitter (UART) interfaces functionality.
+ *
+ * The following peripherals are used by this module:
+ *  - UART (Universal Asynchronous Receiver/Transmitter)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_uart_prerequisites
+ *  - \ref asfdoc_samb_uart_module_overview
+ *  - \ref asfdoc_samb_uart_special_considerations
+ *  - \ref asfdoc_samb_uart_extra_info
+ *  - \ref asfdoc_samb_uart_examples
+ *  - \ref asfdoc_samb_uart_api_overview
+ *
+ *
+ * \section asfdoc_samb_uart_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_uart_module_overview Module Overview
+ *
+ * The device UART module provides an interface between the user application
+ * logic and hardware peripheral. This driver provides an easy-to-use interface
+ * to transfer and receive data.
+ *
+ * \section asfdoc_samb_uart_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_samb_uart_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_uart_extra. This includes:
+ *  - \ref asfdoc_samb_uart_extra_acronyms
+ *  - \ref asfdoc_samb_uart_extra_dependencies
+ *  - \ref asfdoc_samb_uart_extra_errata
+ *  - \ref asfdoc_samb_uart_extra_history
+ *
+ *
+ * \section asfdoc_samb_uart_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_uart_exqsg.
+ *
+ *
+ * \section asfdoc_samb_uart_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system_sam_b.h>
+#include <gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \brief UART byte bit selection
+ *
+ * Number of bit per byte selection for UART communication.
+ */
+enum uart_number_of_bit_selection{
+	/** 8 bit per byte*/
+	UART_8_BITS = UART_CONFIGURATION_NUMBER_OF_BITS_0,
+	/** 7 bit per byte*/
+	UART_7_BITS = UART_CONFIGURATION_NUMBER_OF_BITS_1,
+};
+
+/** \brief UART stop bit selection
+ *
+ * Number of stop bit selection for UART communication.
+ */
+enum uart_stop_bit_selection{
+	/** 1 stop bit per byte*/
+	UART_1_STOP_BIT = UART_CONFIGURATION_STOP_BITS_0,
+	/** 2 stop bit per byte*/
+	UART_2_STOP_BITS = UART_CONFIGURATION_STOP_BITS_1,
+};
+
+
+/** \brief UART Parity selection
+ *
+ * Parity type selection for UART communication.
+ */
+enum uart_parity_selection{
+	/** No parity bit */
+	UART_NO_PARITY = 0,
+	/** Even parity */
+	UART_EVEN_PARITY,
+	/** Odd parity */
+	UART_ODD_PARITY,
+	/** Space parity */
+	UART_SPACE_PARITY,
+	/** Mark parity */
+	UART_MARK_PARITY
+};
+
+/**
+ * \brief UART module instance
+ *
+ * Forward Declaration for the device instance.
+ */
+struct uart_module;
+
+/**
+ * \brief UART callback type
+ *
+ * Type of the callback functions.
+ */
+typedef void (*uart_callback_t)(struct uart_module *const module);
+
+/**
+ * \brief UART Callback enum
+ *
+ * Callbacks for the UART driver.
+ */
+enum uart_callback {
+	/** Callback for TX FIFO not full. */
+	UART_TX_COMPLETE,
+	/** Callback for CTS active. */
+	UART_CTS_ACTIVE,
+	/** Callback for RX FIFO overrun. */
+	UART_RX_COMPLETE,
+	/** Callback for RX FIFO overrun. */
+	UART_RX_FIFO_OVERRUN,
+	/** Number of available callbacks. */
+	UART_CALLBACK_N,
+};
+
+
+/**
+ * \brief Configuration structure for the UART module
+ *
+ * This is the configuration structure for the UART Module in SAMB11. It
+ * is used as an argument for \ref uart_init to provide the desired
+ * configurations for the module. The structure should be initialized using the
+ * \ref uart_get_config_defaults .
+ */
+struct uart_config{
+	/** Baud rate */
+	uint32_t baud_rate;
+	/** Number of data bits */
+	enum uart_number_of_bit_selection data_bits;
+	/** Number of stop bits */
+	enum uart_stop_bit_selection stop_bits;
+	/** Parity type */
+	enum uart_parity_selection parity;
+	/** flow control type */
+	bool flow_control;
+	/** UART PAD pin number */
+	uint32_t pin_number_pad[4];
+	/** UART PAD pinmux selection */
+	uint32_t pinmux_sel_pad[4];
+};
+
+/**
+ * \brief UART driver software device instance structure.
+ *
+ * UART driver software instance structure, used to retain software
+ * state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct uart_module {
+	/** Pointer to the hardware instance. */
+	Uart *hw;
+	/** Array to store callback function pointers in. */
+	uart_callback_t callback[UART_CALLBACK_N];
+	/** Buffer pointer to where the next received character will be put */
+	volatile uint8_t *rx_buffer_ptr;
+	/** Buffer pointer to where the next character will be transmitted from
+	**/
+	volatile uint8_t *tx_buffer_ptr;
+	/** Remaining characters to receive */
+	volatile uint16_t remaining_rx_buffer_length;
+	/** Remaining characters to transmit */
+	volatile uint16_t remaining_tx_buffer_length;
+	/** Bit mask for callbacks registered. */
+	uint8_t callback_reg_mask;
+	/** Bit mask for callbacks enabled. */
+	uint8_t callback_enable_mask;
+	/** Holds the status of the ongoing or last operation */
+	volatile enum status_code status;
+};
+
+/** \name UART Configuration and initialization
+ * @{
+ */
+void uart_get_config_defaults(struct uart_config *const config);
+enum status_code uart_init(struct uart_module *const module, Uart * const hw,
+		const struct uart_config *const config);
+/** @} */
+
+/** \name UART read and write functions
+ * @{
+ */
+enum status_code uart_write_wait(struct uart_module *const module,
+		const uint8_t tx_data);
+enum status_code uart_read_wait(struct uart_module *const module,
+		uint8_t *const rx_data);
+enum status_code uart_write_buffer_wait(struct uart_module *const module,
+		const uint8_t *tx_data, uint32_t length);
+enum status_code uart_read_buffer_wait(struct uart_module *const module,
+		uint8_t *rx_data, uint16_t length);
+enum status_code uart_write_buffer_job(struct uart_module *const module,
+		uint8_t *tx_data, uint32_t length);
+enum status_code uart_read_buffer_job(struct uart_module *const module,
+		uint8_t *rx_data, uint16_t length);
+/** @} */
+
+/** \name UART callback config
+ * @{
+ */
+void uart_register_callback(struct uart_module *const module,
+		uart_callback_t callback_func,
+		enum uart_callback callback_type);
+void uart_unregister_callback(struct uart_module *module,
+		enum uart_callback callback_type);
+void uart_enable_callback(struct uart_module *const module,
+		enum uart_callback callback_type);
+void uart_disable_callback(struct uart_module *const module,
+		enum uart_callback callback_type);
+/** @}*/
+
+/** \name UART DAM enable/disable functions
+ * @{
+ */
+void uart_enable_transmit_dma(struct uart_module *const module);
+void uart_disable_transmit_dma(struct uart_module *const module);
+void uart_enable_receive_dma(struct uart_module *const module);
+void uart_disable_receive_dma(struct uart_module *const module);
+/** @}*/
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \page asfdoc_samb_uart_extra Extra Information for UART Driver
+ *
+ * \section asfdoc_samb_uart_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>UART</td>
+ *		<td>Universal Asynchronous Receiver/Transmitter</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_samb_uart_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_uart_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_uart_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_uart_exqsg Examples for UART Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_uart_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_uart_basic_use_case
+ *  - \subpage asfdoc_samb_uart_dma_use_case
+ *
+ * \page asfdoc_samb_uart_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>A</td>
+ *		<td>09/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_device_udd.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_device_udd.c
new file mode 100644
index 0000000000..7d3eaee192
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_device_udd.c
@@ -0,0 +1,1280 @@
+/**
+ * \file
+ *
+ * \brief USB Device wrapper layer for compliance with common driver UDD
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <string.h>
+#include <stdlib.h>
+
+// Get USB device configuration
+#include "conf_usb.h"
+#include "udd.h"
+#include "usb.h"
+#include "usb_dual.h"
+#include "sleepmgr.h"
+
+/**
+ * \ingroup usb_device_group
+ * \defgroup usb_device_udd_group USB Device Driver Implement (UDD)
+ * USB low-level driver for USB device mode
+ * @{
+ */
+// Check USB device configuration
+#ifdef USB_DEVICE_HS_SUPPORT
+#  error The High speed mode is not supported on this part, please remove USB_DEVICE_HS_SUPPORT in conf_usb.h
+#endif
+
+#if !(SAMD21) && !(SAMR21) && !(SAMD11) && !(SAML21) && !(SAML22) && !(SAMDA1) && !(SAMR30)
+# error The current USB Device Driver supports only SAMD21/R21/D11/L21/L22/DA1
+#endif
+
+#ifndef UDC_REMOTEWAKEUP_LPM_ENABLE
+#define UDC_REMOTEWAKEUP_LPM_ENABLE()
+#endif
+#ifndef UDC_REMOTEWAKEUP_LPM_DISABLE
+#define UDC_REMOTEWAKEUP_LPM_DISABLE()
+#endif
+#ifndef UDC_SUSPEND_LPM_EVENT
+#define UDC_SUSPEND_LPM_EVENT()
+#endif
+
+/* for debug text */
+#ifdef USB_DEBUG
+#   define dbg_print printf
+#else
+#   define dbg_print(...)
+#endif
+
+/** Maximum size of a transfer in multi-packet mode */
+#define UDD_ENDPOINT_MAX_TRANS ((8*1024)-1)
+
+/** USB software device instance structure */
+struct usb_module usb_device;
+
+/**
+ * \name Clock management
+ *
+ * @{
+ */
+#ifndef UDD_CLOCK_GEN
+#if (SAML21) || (SAML22) || (SAMR30)
+#  define UDD_CLOCK_GEN      GCLK_GENERATOR_3
+#elif (SAMDA1)
+#  define UDD_CLOCK_GEN      GCLK_GENERATOR_1
+#else
+#  define UDD_CLOCK_GEN      GCLK_GENERATOR_0
+#endif
+#endif
+#ifndef UDD_CLOCK_SOURCE
+#  define UDD_CLOCK_SOURCE   SYSTEM_CLOCK_SOURCE_DFLL
+#endif
+static inline void udd_wait_clock_ready(void)
+{
+
+	if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DPLL) {
+#if (SAML21) || (SAML22) || (SAMR30)
+	#define DPLL_READY_FLAG (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK)
+
+		while((OSCCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG);
+	}
+#else
+#define DPLL_READY_FLAG (SYSCTRL_DPLLSTATUS_ENABLE | \
+		SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)
+
+		while((SYSCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG);
+	}
+#endif
+
+	if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DFLL) {
+#if (SAML21) || (SAML22) || (SAMR30)
+#define DFLL_READY_FLAG (OSCCTRL_STATUS_DFLLRDY | \
+		OSCCTRL_STATUS_DFLLLCKF | OSCCTRL_STATUS_DFLLLCKC)
+
+		/* In USB recovery mode the status is not checked */
+		if (!(OSCCTRL->DFLLCTRL.reg & OSCCTRL_DFLLCTRL_USBCRM)) {
+			while((OSCCTRL->STATUS.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG);
+		} else {
+			while((OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) != OSCCTRL_STATUS_DFLLRDY);
+		}
+	}
+#else
+#define DFLL_READY_FLAG (SYSCTRL_PCLKSR_DFLLRDY | \
+		SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC)
+
+		/* In USB recovery mode the status is not checked */
+		if (!(SYSCTRL->DFLLCTRL.reg & SYSCTRL_DFLLCTRL_USBCRM)) {
+			while((SYSCTRL->PCLKSR.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG);
+		} else {
+			while((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) != SYSCTRL_PCLKSR_DFLLRDY);
+		}
+	}
+#endif
+}
+/** @} */
+
+/**
+ * \name Power management
+ *
+ * @{
+ */
+#ifndef UDD_NO_SLEEP_MGR
+
+#include "sleepmgr.h"
+/** States of USB interface */
+enum udd_usb_state_enum {
+	UDD_STATE_OFF,
+	UDD_STATE_SUSPEND,
+	UDD_STATE_SUSPEND_LPM,
+	UDD_STATE_IDLE,
+};
+
+/** \brief Manages the sleep mode following the USB state
+ *
+ * \param new_state  New USB state
+ */
+static void udd_sleep_mode(enum udd_usb_state_enum new_state)
+{
+	enum sleepmgr_mode sleep_mode[] = {
+		SLEEPMGR_ACTIVE,  /* UDD_STATE_OFF (not used) */
+	#if (SAML21) || (SAML22) || (SAMR30)
+		SLEEPMGR_IDLE,  /* UDD_STATE_SUSPEND */
+		SLEEPMGR_IDLE,  /* UDD_STATE_SUSPEND_LPM */
+		SLEEPMGR_IDLE,  /* UDD_STATE_IDLE */
+	#else
+		SLEEPMGR_IDLE_2,  /* UDD_STATE_SUSPEND */
+		SLEEPMGR_IDLE_1,  /* UDD_STATE_SUSPEND_LPM */
+		SLEEPMGR_IDLE_0,  /* UDD_STATE_IDLE */
+	#endif	
+	};
+
+	static enum udd_usb_state_enum udd_state = UDD_STATE_OFF;
+
+	if (udd_state == new_state) {
+		return; // No change
+	}
+	if (new_state != UDD_STATE_OFF) {
+		/* Lock new limit */
+		sleepmgr_lock_mode(sleep_mode[new_state]);
+	}
+	if (udd_state != UDD_STATE_OFF) {
+		/* Unlock old limit */
+		sleepmgr_unlock_mode(sleep_mode[udd_state]);
+	}
+	udd_state = new_state;
+}
+
+#else
+#  define udd_sleep_mode(arg)
+#endif
+/** @} */
+
+/**
+ * \name Control endpoint low level management routine.
+ *
+ * This function performs control endpoint management.
+ * It handles the SETUP/DATA/HANDSHAKE phases of a control transaction.
+ *
+ * @{
+ */
+
+/**
+ * \brief Buffer to store the data received on control endpoint (SETUP/OUT endpoint 0)
+ *
+ * Used to avoid a RAM buffer overflow in case of the payload buffer
+ * is smaller than control endpoint size
+ */
+UDC_BSS(4)
+uint8_t udd_ctrl_buffer[USB_DEVICE_EP_CTRL_SIZE];
+
+/** Bit definitions about endpoint control state machine for udd_ep_control_state */
+typedef enum {
+	UDD_EPCTRL_SETUP                  = 0, //!< Wait a SETUP packet
+	UDD_EPCTRL_DATA_OUT               = 1, //!< Wait a OUT data packet
+	UDD_EPCTRL_DATA_IN                = 2, //!< Wait a IN data packet
+	UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP  = 3, //!< Wait a IN ZLP packet
+	UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP = 4, //!< Wait a OUT ZLP packet
+	UDD_EPCTRL_STALL_REQ              = 5, //!< STALL enabled on IN & OUT packet
+} udd_ctrl_ep_state_t;
+
+/** Global variable to give and record information of the set up request management */
+udd_ctrl_request_t udd_g_ctrlreq;
+
+/** State of the endpoint control management */
+static udd_ctrl_ep_state_t udd_ep_control_state;
+
+/** Total number of data received/sent during data packet phase with previous payload buffers */
+static uint16_t udd_ctrl_prev_payload_nb_trans;
+
+/** Number of data received/sent to/from udd_g_ctrlreq.payload buffer */
+static uint16_t udd_ctrl_payload_nb_trans;
+
+/** @} */
+
+/**
+ * \name Management of bulk/interrupt/isochronous endpoints
+ *
+ * The UDD manages the data transfer on endpoints:
+ * - Start data transfer on endpoint with USB Device DMA
+ * - Send a ZLP packet if requested
+ * - Call callback registered to signal end of transfer
+ * The transfer abort and stall feature are supported.
+ *
+ * @{
+ */
+
+/**
+ * \brief Buffer to store the data received on bulk/interrupt endpoints
+ *
+ * Used to avoid a RAM buffer overflow in case of the user buffer
+ * is smaller than endpoint size
+ *
+ * \warning The protected interrupt endpoint size is 512 bytes maximum.
+ * \warning The isochronous and endpoint is not protected by this system and
+ *          the user must always use a buffer corresponding at endpoint size.
+ */
+#if (defined USB_DEVICE_LOW_SPEED)
+UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][8];
+#elif (defined USB_DEVICE_HS_SUPPORT)
+UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][512];
+#else
+UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][64];
+#endif
+
+/** Structure definition about job registered on an endpoint */
+typedef struct {
+	union {
+		//! Callback to call at the end of transfer
+		udd_callback_trans_t call_trans;
+		//! Callback to call when the endpoint halt is cleared
+		udd_callback_halt_cleared_t call_nohalt;
+	};
+	//! Buffer located in internal RAM to send or fill during job
+	uint8_t *buf;
+	//! Size of buffer to send or fill
+	iram_size_t buf_size;
+	//! Total number of data transferred on endpoint
+	iram_size_t nb_trans;
+	//! Endpoint size
+	uint16_t ep_size;
+	//! A job is registered on this endpoint
+	uint8_t busy:1;
+	//! A short packet is requested for this job on endpoint IN
+	uint8_t b_shortpacket:1;
+	//! The cache buffer is currently used on endpoint OUT
+	uint8_t b_use_out_cache_buffer:1;
+} udd_ep_job_t;
+
+/** Array to register a job on bulk/interrupt/isochronous endpoint */
+static udd_ep_job_t udd_ep_job[2 * USB_DEVICE_MAX_EP];
+
+/** @} */
+
+/**
+ * \brief     Get the detailed job by endpoint number
+ * \param[in] ep  Endpoint Address
+ * \retval    pointer to an udd_ep_job_t structure instance
+ */
+static udd_ep_job_t* udd_ep_get_job(udd_ep_id_t ep)
+{
+	if ((ep == 0) || (ep == 0x80)) {
+		return NULL;
+	} else {
+		return &udd_ep_job[(2 * (ep & USB_EP_ADDR_MASK) + ((ep & USB_EP_DIR_IN) ? 1 : 0)) - 2];
+	}
+}
+
+/**
+ * \brief     Endpoint IN process, continue to send packets or zero length packet
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ep_trans_in_next(void* pointer)
+{
+	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+	udd_ep_id_t ep = ep_callback_para->endpoint_address;
+	uint16_t ep_size, nb_trans;
+	uint16_t next_trans;
+	udd_ep_id_t ep_num;
+	udd_ep_job_t *ptr_job;
+
+	ptr_job = udd_ep_get_job(ep);
+	ep_num = ep & USB_EP_ADDR_MASK;
+
+	ep_size = ptr_job->ep_size;
+	/* Update number of data transferred */
+	nb_trans = ep_callback_para->sent_bytes;
+	ptr_job->nb_trans += nb_trans;
+
+	/* Need to send other data */
+	if (ptr_job->nb_trans != ptr_job->buf_size) {
+		next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+		if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
+		/* The USB hardware support a maximum
+		 * transfer size of UDD_ENDPOINT_MAX_TRANS Bytes */
+			next_trans = UDD_ENDPOINT_MAX_TRANS -(UDD_ENDPOINT_MAX_TRANS % ep_size);
+		}
+		/* Need ZLP, if requested and last packet is not a short packet */
+		ptr_job->b_shortpacket = ptr_job->b_shortpacket && (0 == (next_trans % ep_size));
+		usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans);
+		return;
+	}
+
+	/* Need to send a ZLP after all data transfer */
+	if (ptr_job->b_shortpacket) {
+		ptr_job->b_shortpacket = false;
+		/* Start new transfer */
+		usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],0);
+		return;
+	}
+
+	/* Job complete then call callback */
+	ptr_job->busy = false;
+	if (NULL != ptr_job->call_trans) {
+		ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
+	}
+}
+
+/**
+ * \brief     Endpoint OUT process, continue to receive packets or zero length packet
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ep_trans_out_next(void* pointer)
+{
+	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+	udd_ep_id_t ep = ep_callback_para->endpoint_address;
+	uint16_t ep_size, nb_trans;
+	uint16_t next_trans;
+	udd_ep_id_t ep_num;
+	udd_ep_job_t *ptr_job;
+
+	ptr_job = udd_ep_get_job(ep);
+	ep_num = ep & USB_EP_ADDR_MASK;
+
+	ep_size = ptr_job->ep_size;
+	/* Update number of data transferred */
+	nb_trans = ep_callback_para->received_bytes;
+
+	/* Can be necessary to copy data receive from cache buffer to user buffer */
+	if (ptr_job->b_use_out_cache_buffer) {
+		memcpy(&ptr_job->buf[ptr_job->nb_trans], udd_ep_out_cache_buffer[ep_num - 1], ptr_job->buf_size % ep_size);
+	}
+
+	/* Update number of data transferred */
+	ptr_job->nb_trans += nb_trans;
+	if (ptr_job->nb_trans > ptr_job->buf_size) {
+		ptr_job->nb_trans = ptr_job->buf_size;
+	}
+
+	/* If all previous data requested are received and user buffer not full
+	 * then need to receive other data */
+	if ((nb_trans == ep_callback_para->out_buffer_size) && (ptr_job->nb_trans != ptr_job->buf_size)) {
+		next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+		if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
+		/* The USB hardware support a maximum transfer size
+		 * of UDD_ENDPOINT_MAX_TRANS Bytes */
+		next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ep_size);
+		} else {
+			next_trans -= next_trans % ep_size;
+		}
+
+		if (next_trans < ep_size) {
+			/* Use the cache buffer for Bulk or Interrupt size endpoint */
+			ptr_job->b_use_out_cache_buffer = true;
+			usb_device_endpoint_read_buffer_job(&usb_device,ep_num,udd_ep_out_cache_buffer[ep_num - 1],ep_size);
+		} else {
+			usb_device_endpoint_read_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans);
+		}
+		return;
+	}
+
+	/* Job complete then call callback */
+	ptr_job->busy = false;
+	if (NULL != ptr_job->call_trans) {
+		ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
+	}
+}
+
+/**
+ * \brief     Endpoint Transfer Complete callback function, to do the next transfer depends on the direction(IN or OUT)
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ep_transfer_process(struct usb_module *module_inst, void* pointer)
+{
+	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+	udd_ep_id_t ep = ep_callback_para->endpoint_address;
+
+	if (ep & USB_EP_DIR_IN) {
+		udd_ep_trans_in_next(pointer);
+	} else {
+		udd_ep_trans_out_next(pointer);
+	}
+}
+
+void udd_ep_abort(udd_ep_id_t ep)
+{
+	udd_ep_job_t *ptr_job;
+
+	usb_device_endpoint_abort_job(&usb_device, ep);
+
+	/* Job complete then call callback */
+	ptr_job = udd_ep_get_job(ep);
+	if (!ptr_job->busy) {
+		return;
+	}
+	ptr_job->busy = false;
+	if (NULL != ptr_job->call_trans) {
+		/* It can be a Transfer or stall callback */
+		ptr_job->call_trans(UDD_EP_TRANSFER_ABORT, ptr_job->nb_trans, ep);
+	}
+}
+
+bool udd_is_high_speed(void)
+{
+#if SAMD21 || SAMR21 || SAMD11 || SAML21  || SAML22 || SAMDA1 || SAMR30
+	return false;
+#endif
+}
+
+uint16_t udd_get_frame_number(void)
+{
+	return usb_device_get_frame_number(&usb_device);
+}
+
+uint16_t udd_get_micro_frame_number(void)
+{
+	return usb_device_get_micro_frame_number(&usb_device);
+}
+
+void udd_ep_free(udd_ep_id_t ep)
+{
+	struct usb_device_endpoint_config config_ep;
+	usb_device_endpoint_get_config_defaults(&config_ep);
+
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+	udd_ep_abort(ep);
+
+	config_ep.ep_address = ep;
+	config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_DISABLE;
+	usb_device_endpoint_set_config(&usb_device, &config_ep);
+	usb_device_endpoint_unregister_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+	usb_device_endpoint_disable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+}
+
+bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, uint16_t MaxEndpointSize)
+{
+	struct usb_device_endpoint_config config_ep;
+	usb_device_endpoint_get_config_defaults(&config_ep);
+
+	config_ep.ep_address = ep;
+
+	if(MaxEndpointSize <= 8) {
+		config_ep.ep_size = USB_ENDPOINT_8_BYTE;
+	} else if(MaxEndpointSize <= 16) {
+		config_ep.ep_size = USB_ENDPOINT_16_BYTE;
+	} else if(MaxEndpointSize <= 32) {
+		config_ep.ep_size = USB_ENDPOINT_32_BYTE;
+	} else if(MaxEndpointSize <= 64) {
+		config_ep.ep_size = USB_ENDPOINT_64_BYTE;
+	} else if(MaxEndpointSize <= 128) {
+		config_ep.ep_size = USB_ENDPOINT_128_BYTE;
+	} else if(MaxEndpointSize <= 256) {
+		config_ep.ep_size = USB_ENDPOINT_256_BYTE;
+	} else if(MaxEndpointSize <= 512) {
+		config_ep.ep_size = USB_ENDPOINT_512_BYTE;
+	} else if(MaxEndpointSize <= 1023) {
+		config_ep.ep_size = USB_ENDPOINT_1023_BYTE;
+	} else {
+		return false;
+	}
+	udd_ep_job_t *ptr_job = udd_ep_get_job(ep);
+	ptr_job->ep_size = MaxEndpointSize;
+
+	bmAttributes = bmAttributes & USB_EP_TYPE_MASK;
+
+	/* Check endpoint type */
+	if(USB_EP_TYPE_ISOCHRONOUS == bmAttributes) {
+		config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS;
+	} else if (USB_EP_TYPE_BULK == bmAttributes) {
+		config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_BULK;
+	} else if (USB_EP_TYPE_INTERRUPT == bmAttributes) {
+		config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_INTERRUPT;
+	} else {
+		return false;
+	}
+
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	if (STATUS_OK != usb_device_endpoint_set_config(&usb_device, &config_ep)) {
+		return false;
+	}
+	usb_device_endpoint_register_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,udd_ep_transfer_process);
+	usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+	usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
+
+	return true;
+}
+
+bool udd_ep_is_halted(udd_ep_id_t ep)
+{
+	return usb_device_endpoint_is_halted(&usb_device, ep);
+}
+
+bool udd_ep_set_halt(udd_ep_id_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	if (USB_DEVICE_MAX_EP < ep_num) {
+		return false;
+	}
+
+	usb_device_endpoint_set_halt(&usb_device, ep);
+
+	udd_ep_abort(ep);
+	return true;
+}
+
+bool udd_ep_clear_halt(udd_ep_id_t ep)
+{
+	udd_ep_job_t *ptr_job;
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	if (USB_DEVICE_MAX_EP < ep_num) {
+		return false;
+	}
+	ptr_job = udd_ep_get_job(ep);
+
+	usb_device_endpoint_clear_halt(&usb_device, ep);
+
+	/* If a job is register on clear halt action then execute callback */
+	if (ptr_job->busy == true) {
+		ptr_job->busy = false;
+		ptr_job->call_nohalt();
+	}
+
+	return true;
+}
+
+bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callback)
+{
+	udd_ep_id_t ep_num;
+	udd_ep_job_t *ptr_job;
+
+	ep_num = ep & USB_EP_ADDR_MASK;
+	if (USB_DEVICE_MAX_EP < ep_num) {
+		return false;
+	}
+
+	ptr_job = udd_ep_get_job(ep);
+	if (ptr_job->busy == true) {
+		return false; /* Job already on going */
+	}
+
+	/* Wait clear halt endpoint */
+	if (usb_device_endpoint_is_halted(&usb_device, ep)) {
+		/* Endpoint halted then registers the callback */
+		ptr_job->busy = true;
+		ptr_job->call_nohalt = callback;
+		return true;
+	} else if (usb_device_endpoint_is_configured(&usb_device, ep)) {
+		callback(); /* Endpoint not halted then call directly callback */
+		return true;
+	} else {
+		return false;
+	}
+}
+
+/**
+ * \brief Control Endpoint stall sending data
+ */
+static void udd_ctrl_stall_data(void)
+{
+	udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+
+	usb_device_endpoint_set_halt(&usb_device, USB_EP_DIR_IN);
+	usb_device_endpoint_clear_halt(&usb_device, USB_EP_DIR_OUT);
+}
+
+bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, uint8_t * buf, iram_size_t buf_size, udd_callback_trans_t callback)
+{
+	udd_ep_id_t ep_num;
+	udd_ep_job_t *ptr_job;
+	irqflags_t flags;
+
+	ep_num = ep & USB_EP_ADDR_MASK;
+
+	if ((USB_DEVICE_MAX_EP < ep_num) || (udd_ep_is_halted(ep))) {
+		return false;
+	}
+
+	ptr_job = udd_ep_get_job(ep);
+
+	flags = cpu_irq_save();
+	if (ptr_job->busy == true) {
+		cpu_irq_restore(flags);
+		return false; /* Job already on going */
+	}
+	ptr_job->busy = true;
+	cpu_irq_restore(flags);
+
+	/* No job running, set up a new one */
+	ptr_job->buf = buf;
+	ptr_job->buf_size = buf_size;
+	ptr_job->nb_trans = 0;
+	ptr_job->call_trans = callback;
+	ptr_job->b_shortpacket = b_shortpacket;
+	ptr_job->b_use_out_cache_buffer = false;
+
+	/* Initialize value to simulate a empty transfer */
+	uint16_t next_trans;
+
+	if (ep & USB_EP_DIR_IN) {
+		if (0 != ptr_job->buf_size) {
+			next_trans = ptr_job->buf_size;
+			if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
+				next_trans = UDD_ENDPOINT_MAX_TRANS -
+						(UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
+			}
+			ptr_job->b_shortpacket = ptr_job->b_shortpacket &&
+					(0 == (next_trans % ptr_job->ep_size));
+		} else if (true == ptr_job->b_shortpacket) {
+			ptr_job->b_shortpacket = false; /* avoid to send zero length packet again */
+			next_trans = 0;
+		} else {
+			ptr_job->busy = false;
+			if (NULL != ptr_job->call_trans) {
+				ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
+			}
+			return true;
+		}
+		return (STATUS_OK ==
+				usb_device_endpoint_write_buffer_job(&usb_device,
+						ep_num,&ptr_job->buf[0],next_trans));
+	} else {
+		if (0 != ptr_job->buf_size) {
+			next_trans = ptr_job->buf_size;
+			if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
+				/* The USB hardware support a maximum transfer size
+				 * of UDD_ENDPOINT_MAX_TRANS Bytes */
+				next_trans = UDD_ENDPOINT_MAX_TRANS -
+						(UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
+			} else {
+				next_trans -= next_trans % ptr_job->ep_size;
+			}
+			if (next_trans < ptr_job->ep_size) {
+				ptr_job->b_use_out_cache_buffer = true;
+				return (STATUS_OK ==
+						usb_device_endpoint_read_buffer_job(&usb_device, ep_num,
+								udd_ep_out_cache_buffer[ep_num - 1],
+								ptr_job->ep_size));
+			} else {
+				return (STATUS_OK ==
+						usb_device_endpoint_read_buffer_job(&usb_device, ep_num,
+								&ptr_job->buf[0],next_trans));
+			}
+		} else {
+			ptr_job->busy = false;
+			if (NULL != ptr_job->call_trans) {
+				ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
+			}
+			return true;
+		}
+	}
+}
+
+void udd_set_address(uint8_t address)
+{
+	usb_device_set_address(&usb_device,address);
+}
+
+uint8_t udd_getaddress(void)
+{
+	return usb_device_get_address(&usb_device);
+}
+
+void udd_send_remotewakeup(void)
+{
+	uint32_t try = 5;
+	udd_wait_clock_ready();
+	udd_sleep_mode(UDD_STATE_IDLE);
+	while(2 != usb_get_state_machine_status(&usb_device) && try --) {
+		usb_device_send_remote_wake_up(&usb_device);
+	}
+}
+
+void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size )
+{
+	udd_g_ctrlreq.payload = payload;
+	udd_g_ctrlreq.payload_size = payload_size;
+}
+
+/**
+ * \brief Control Endpoint translate the data in buffer into Device Request Struct
+ */
+static void udd_ctrl_fetch_ram(void)
+{
+	udd_g_ctrlreq.req.bmRequestType = udd_ctrl_buffer[0];
+	udd_g_ctrlreq.req.bRequest = udd_ctrl_buffer[1];
+	udd_g_ctrlreq.req.wValue = ((uint16_t)(udd_ctrl_buffer[3]) << 8) + udd_ctrl_buffer[2];
+	udd_g_ctrlreq.req.wIndex = ((uint16_t)(udd_ctrl_buffer[5]) << 8) + udd_ctrl_buffer[4];
+	udd_g_ctrlreq.req.wLength = ((uint16_t)(udd_ctrl_buffer[7]) << 8) + udd_ctrl_buffer[6];
+}
+
+/**
+ * \brief Control Endpoint send out zero length packet
+ */
+static void udd_ctrl_send_zlp_in(void)
+{
+	udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP;
+	usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer);
+	usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload,0);
+}
+
+/**
+ * \brief Process control endpoint IN transaction
+ */
+static void udd_ctrl_in_sent(void)
+{
+	static bool b_shortpacket = false;
+	uint16_t nb_remain;
+
+	nb_remain = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
+
+	if (0 == nb_remain) {
+		/* All content of current buffer payload are sent Update number of total data sending by previous payload buffer */
+		udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
+		if ((udd_g_ctrlreq.req.wLength == udd_ctrl_prev_payload_nb_trans) || b_shortpacket) {
+			/* All data requested are transferred or a short packet has been sent, then it is the end of data phase.
+			 * Generate an OUT ZLP for handshake phase */
+			udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
+			usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer);
+			return;
+		}
+		/* Need of new buffer because the data phase is not complete */
+		if ((!udd_g_ctrlreq.over_under_run) || (!udd_g_ctrlreq.over_under_run())) {
+			/* Under run then send zlp on IN
+			 * Here nb_remain=0, this allows to send a IN ZLP */
+		} else {
+			/* A new payload buffer is given */
+			udd_ctrl_payload_nb_trans = 0;
+			nb_remain = udd_g_ctrlreq.payload_size;
+		}
+	}
+
+	/* Continue transfer and send next data */
+	if (nb_remain >= USB_DEVICE_EP_CTRL_SIZE) {
+		nb_remain = USB_DEVICE_EP_CTRL_SIZE;
+		b_shortpacket = false;
+	} else {
+		b_shortpacket = true;
+	}
+
+	/* Link payload buffer directly on USB hardware */
+	usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans,nb_remain);
+
+	udd_ctrl_payload_nb_trans += nb_remain;
+}
+
+/**
+ * \brief Process control endpoint OUT transaction
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ctrl_out_received(void* pointer)
+{
+	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+	uint16_t nb_data;
+	nb_data = ep_callback_para->received_bytes; /* Read data received during OUT phase */
+
+	if (udd_g_ctrlreq.payload_size < (udd_ctrl_payload_nb_trans + nb_data)) {
+		/* Payload buffer too small */
+		nb_data = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
+	}
+
+	memcpy((uint8_t *) (udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans), udd_ctrl_buffer, nb_data);
+	udd_ctrl_payload_nb_trans += nb_data;
+
+	if ((USB_DEVICE_EP_CTRL_SIZE != nb_data) || \
+	(udd_g_ctrlreq.req.wLength <= (udd_ctrl_prev_payload_nb_trans + udd_ctrl_payload_nb_trans))) {
+		/* End of reception because it is a short packet
+		 * or all data are transferred */
+
+		/* Before send ZLP, call intermediate callback
+		 * in case of data receive generate a stall */
+		udd_g_ctrlreq.payload_size = udd_ctrl_payload_nb_trans;
+		if (NULL != udd_g_ctrlreq.over_under_run) {
+			if (!udd_g_ctrlreq.over_under_run()) {
+				/* Stall ZLP */
+				udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+				/* Stall all packets on IN & OUT control endpoint */
+				udd_ep_set_halt(0);
+				/* Ack reception of OUT to replace NAK by a STALL */
+				return;
+			}
+		}
+		/* Send IN ZLP to ACK setup request */
+		udd_ctrl_send_zlp_in();
+		return;
+	}
+
+	if (udd_g_ctrlreq.payload_size == udd_ctrl_payload_nb_trans) {
+		/* Overrun then request a new payload buffer */
+		if (!udd_g_ctrlreq.over_under_run) {
+			/* No callback available to request a new payload buffer
+			 * Stall ZLP */
+			udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+			/* Stall all packets on IN & OUT control endpoint */
+			udd_ep_set_halt(0);
+			return;
+		}
+		if (!udd_g_ctrlreq.over_under_run()) {
+			/* No new payload buffer delivered
+			 * Stall ZLP */
+			udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+			/* Stall all packets on IN & OUT control endpoint */
+			udd_ep_set_halt(0);
+			return;
+		}
+		/* New payload buffer available
+		 * Update number of total data received */
+		udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
+
+		/* Reinitialize reception on payload buffer */
+		udd_ctrl_payload_nb_trans = 0;
+	}
+	usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+}
+
+/**
+ * \internal
+ * \brief     Endpoint 0 (control) SETUP received callback
+ * \param[in] module_inst pointer to USB module instance
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void _usb_ep0_on_setup(struct usb_module *module_inst, void* pointer)
+{
+	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+	if (UDD_EPCTRL_SETUP != udd_ep_control_state) {
+		if (NULL != udd_g_ctrlreq.callback) {
+			udd_g_ctrlreq.callback();
+		}
+		udd_ep_control_state = UDD_EPCTRL_SETUP;
+	}
+	if ( 8 != ep_callback_para->received_bytes) {
+		udd_ctrl_stall_data();
+		return;
+	} else {
+		udd_ctrl_fetch_ram();
+		if (false == udc_process_setup()) {
+			udd_ctrl_stall_data();
+			return;
+		} else if (Udd_setup_is_in()) {
+			udd_ctrl_prev_payload_nb_trans = 0;
+			udd_ctrl_payload_nb_trans = 0;
+			udd_ep_control_state = UDD_EPCTRL_DATA_IN;
+			usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+			udd_ctrl_in_sent();
+		} else {
+			if(0 == udd_g_ctrlreq.req.wLength) {
+				udd_ctrl_send_zlp_in();
+				return;
+			} else {
+				udd_ctrl_prev_payload_nb_trans = 0;
+				udd_ctrl_payload_nb_trans = 0;
+				udd_ep_control_state = UDD_EPCTRL_DATA_OUT;
+				/* Initialize buffer size and enable OUT bank */
+				usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+			}
+		}
+	}
+}
+
+/**
+ * \brief Control Endpoint Process when underflow condition has occurred
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ctrl_underflow(void* pointer)
+{
+	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+	if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) {
+		/* Host want to stop OUT transaction
+		 * then stop to wait OUT data phase and wait IN ZLP handshake */
+		udd_ctrl_send_zlp_in();
+	} else if (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state) {
+		/* A OUT handshake is waiting by device,
+		 * but host want extra IN data then stall extra IN data */
+		usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
+	}
+}
+
+/**
+ * \brief Control Endpoint Process when overflow condition has occurred
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ctrl_overflow(void* pointer)
+{
+	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+	if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) {
+		/* Host want to stop IN transaction
+		 * then stop to wait IN data phase and wait OUT ZLP handshake */
+		udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
+	} else if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) {
+		/* A IN handshake is waiting by device,
+		 * but host want extra OUT data then stall extra OUT data and following status stage */
+		usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
+	}
+}
+
+/**
+ * \internal
+ * \brief Control endpoint transfer fail callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void _usb_ep0_on_tansfer_fail(struct usb_module *module_inst, void* pointer)
+{
+	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+	if(ep_callback_para->endpoint_address & USB_EP_DIR_IN) {
+		udd_ctrl_underflow(pointer);
+	} else {
+		udd_ctrl_overflow(pointer);
+	}
+}
+
+/**
+ * \internal
+ * \brief Control endpoint transfer complete callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void _usb_ep0_on_tansfer_ok(struct usb_module *module_inst, void * pointer)
+{
+		if (UDD_EPCTRL_DATA_OUT  == udd_ep_control_state) { /* handshake Out for status stage */
+			udd_ctrl_out_received(pointer);
+		} else if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) { /* handshake In for status stage */
+			udd_ctrl_in_sent();
+		} else {
+			if (NULL != udd_g_ctrlreq.callback) {
+				udd_g_ctrlreq.callback();
+			}
+			udd_ep_control_state = UDD_EPCTRL_SETUP;
+		}
+}
+
+/**
+ * \brief Enable Control Endpoint
+ * \param[in] module_inst Pointer to USB module instance
+ */
+static void udd_ctrl_ep_enable(struct usb_module *module_inst)
+{
+	/* USB Device Endpoint0 Configuration */
+	 struct usb_device_endpoint_config config_ep0;
+
+	 usb_device_endpoint_get_config_defaults(&config_ep0);
+	 config_ep0.ep_size = (enum usb_endpoint_size)(32 - clz(((uint32_t)Min(Max(USB_DEVICE_EP_CTRL_SIZE, 8), 1024) << 1) - 1) - 1 - 3);
+	 usb_device_endpoint_set_config(module_inst,&config_ep0);
+
+	 usb_device_endpoint_setup_buffer_job(module_inst,udd_ctrl_buffer);
+
+	 usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP, _usb_ep0_on_setup );
+	 usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,_usb_ep0_on_tansfer_ok );
+	 usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,_usb_ep0_on_tansfer_fail );
+	 usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP);
+	 usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+	 usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
+
+#ifdef  USB_DEVICE_LPM_SUPPORT
+	 // Enable LPM feature
+	 usb_device_set_lpm_mode(module_inst, USB_DEVICE_LPM_ACK);
+#endif
+
+	 udd_ep_control_state = UDD_EPCTRL_SETUP;
+}
+
+/**
+ * \internal
+ * \brief Control endpoint Suspend callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the callback parameter from driver layer.
+ */
+static void _usb_on_suspend(struct usb_module *module_inst, void *pointer)
+{
+	usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+	udd_sleep_mode(UDD_STATE_SUSPEND);
+#ifdef UDC_SUSPEND_EVENT
+	UDC_SUSPEND_EVENT();
+#endif
+}
+
+#ifdef  USB_DEVICE_LPM_SUPPORT
+static void _usb_device_lpm_suspend(struct usb_module *module_inst, void *pointer)
+{
+	dbg_print("LPM_SUSP\n");
+
+	uint32_t *lpm_wakeup_enable;
+	lpm_wakeup_enable = (uint32_t *)pointer;
+
+	usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+	usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+
+//#warning Here the sleep mode must be choose to have a DFLL startup time < bmAttribut.HIRD
+	udd_sleep_mode(UDD_STATE_SUSPEND_LPM);  // Enter in LPM SUSPEND mode
+	if ((*lpm_wakeup_enable)) {
+		UDC_REMOTEWAKEUP_LPM_ENABLE();
+	}
+	if (!(*lpm_wakeup_enable)) {
+		UDC_REMOTEWAKEUP_LPM_DISABLE();
+	}
+	UDC_SUSPEND_LPM_EVENT();
+}
+#endif
+
+/**
+ * \internal
+ * \brief Control endpoint SOF callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the callback parameter from driver layer.
+ */
+static void _usb_on_sof_notify(struct usb_module *module_inst, void *pointer)
+{
+	udc_sof_notify();
+#ifdef UDC_SOF_EVENT
+	UDC_SOF_EVENT();
+#endif
+}
+
+/**
+ * \internal
+ * \brief Control endpoint Reset callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the callback parameter from driver layer.
+ */
+static void _usb_on_bus_reset(struct usb_module *module_inst, void *pointer)
+{
+	// Reset USB Device Stack Core
+	udc_reset();
+	usb_device_set_address(module_inst,0);
+	udd_ctrl_ep_enable(module_inst);
+}
+
+/**
+ * \internal
+ * \brief Control endpoint Wakeup callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the callback parameter from driver layer.
+ */
+static void _usb_on_wakeup(struct usb_module *module_inst, void *pointer)
+{
+	udd_wait_clock_ready();
+
+	usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+#ifdef  USB_DEVICE_LPM_SUPPORT
+	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+#endif
+	udd_sleep_mode(UDD_STATE_IDLE);
+#ifdef UDC_RESUME_EVENT
+	UDC_RESUME_EVENT();
+#endif
+}
+
+void udd_detach(void)
+{
+	usb_device_detach(&usb_device);
+	udd_sleep_mode(UDD_STATE_SUSPEND);
+}
+
+void udd_attach(void)
+{
+	udd_sleep_mode(UDD_STATE_IDLE);
+	usb_device_attach(&usb_device);
+
+	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND, _usb_on_suspend);
+	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SOF, _usb_on_sof_notify);
+	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_RESET, _usb_on_bus_reset);
+	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP, _usb_on_wakeup);
+
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SOF);
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_RESET);
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+#ifdef  USB_DEVICE_LPM_SUPPORT
+	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
+	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+#endif
+}
+
+#if USB_VBUS_EIC
+/**
+ * \name USB VBUS PAD management
+ *
+ * @{
+ */
+
+ /** Check if USB VBus is available */
+# define is_usb_vbus_high()           port_pin_get_input_level(USB_VBUS_PIN)
+
+/**
+ * \internal
+ * \brief USB VBUS pin change handler
+ */
+static void _uhd_vbus_handler(void)
+{
+	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+# ifndef USB_DEVICE_ATTACH_AUTO_DISABLE
+	if (is_usb_vbus_high()) {
+		udd_attach();
+	} else {
+		udd_detach();
+	}
+# endif
+# ifdef UDC_VBUS_EVENT
+	UDC_VBUS_EVENT(is_usb_vbus_high());
+# endif
+	extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+}
+
+/**
+ * \internal
+ * \brief USB VBUS pin configuration
+ */
+static void _usb_vbus_config(void)
+{
+
+	/* Initialize EIC for vbus checking */
+	struct extint_chan_conf eint_chan_conf;
+	extint_chan_get_config_defaults(&eint_chan_conf);
+
+	eint_chan_conf.gpio_pin           = USB_VBUS_PIN;
+	eint_chan_conf.gpio_pin_mux       = USB_VBUS_EIC_MUX;
+	eint_chan_conf.gpio_pin_pull      = EXTINT_PULL_NONE;
+	eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
+	eint_chan_conf.filter_input_signal = true;
+
+	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	extint_chan_set_config(USB_VBUS_EIC_LINE, &eint_chan_conf);
+	extint_register_callback(_uhd_vbus_handler,
+			USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+}
+/** @} */
+#endif
+
+bool udd_include_vbus_monitoring(void)
+{
+#if USB_VBUS_EIC
+	return true;
+#else
+	return false;
+#endif
+}
+
+void udd_enable(void)
+{
+	irqflags_t flags;
+
+	/* To avoid USB interrupt before end of initialization */
+	flags = cpu_irq_save();
+
+#if USB_ID_EIC
+	if (usb_dual_enable()) {
+		/* The current mode has been started by otg_dual_enable() */
+		cpu_irq_restore(flags);
+		return;
+	}
+#endif
+	struct usb_config config_usb;
+
+	/* USB Module configuration */
+	usb_get_config_defaults(&config_usb);
+	config_usb.source_generator = UDD_CLOCK_GEN;
+	usb_init(&usb_device, USB, &config_usb);
+
+	/* USB Module Enable */
+	usb_enable(&usb_device);
+
+	/* Check clock after enable module, request the clock */
+	udd_wait_clock_ready();
+
+	udd_sleep_mode(UDD_STATE_SUSPEND);
+
+#if USB_VBUS_EIC
+	_usb_vbus_config();
+	if (is_usb_vbus_high()) {
+		/* USB Attach */
+		_uhd_vbus_handler();
+	}
+#else
+	// No VBus detect, assume always high
+# ifndef USB_DEVICE_ATTACH_AUTO_DISABLE
+	udd_attach();
+# endif
+#endif
+
+	cpu_irq_restore(flags);
+}
+
+void udd_disable(void)
+{
+	irqflags_t flags;
+
+	udd_detach();
+
+	udd_sleep_mode(UDD_STATE_OFF);
+
+	flags = cpu_irq_save();
+	usb_dual_disable();
+	cpu_irq_restore(flags);
+}
+/** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.c
new file mode 100644
index 0000000000..4b9adee94a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.c
@@ -0,0 +1,178 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Dual Role driver file.
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <compiler.h>
+#include "usb_dual.h"
+
+#ifndef UDD_ENABLE
+# define udc_start()
+# define udc_stop()
+#else
+#include <udc.h>
+#endif
+
+#ifndef UHD_ENABLE
+# define uhc_start(void)
+# define uhc_stop(b_id_stop)
+#else
+#include <uhc.h>
+#endif
+
+/* State of USB dual role initialization */
+static bool _initialized = false;
+
+#define _usb_is_id_device()         port_pin_get_input_level(USB_ID_PIN)
+
+#if USB_ID_EIC
+static void usb_id_handler(void);
+
+/**
+ * \name USB ID PAD management
+ *
+ * @{
+ */
+
+/**
+ * USB ID pin configuration
+ */
+static void usb_id_config(void)
+{
+	struct extint_chan_conf eint_chan_conf;
+	extint_chan_get_config_defaults(&eint_chan_conf);
+
+	eint_chan_conf.gpio_pin           = USB_ID_PIN;
+	eint_chan_conf.gpio_pin_mux       = USB_ID_EIC_MUX;
+	eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
+	eint_chan_conf.filter_input_signal = true;
+
+	extint_chan_disable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	extint_chan_set_config(USB_ID_EIC_LINE, &eint_chan_conf);
+	extint_register_callback(usb_id_handler,
+			USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	extint_chan_enable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+}
+
+/**
+ * USB ID pin change handler
+ */
+static void usb_id_handler(void)
+{
+	extint_chan_disable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	if (_usb_is_id_device()) {
+		uhc_stop(false);
+		UHC_MODE_CHANGE(false);
+		udc_start();
+	} else {
+		udc_stop();
+		UHC_MODE_CHANGE(true);
+		uhc_start();
+	}
+	extint_chan_enable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+}
+#endif
+/** @} */
+
+/**
+ * \brief Initialize the USB peripheral and set right role according to ID pin
+ *
+ * \return \c true if the ID pin management has been started, otherwise \c false.
+ */
+bool usb_dual_enable(void)
+{
+	if (_initialized) {
+		return false; // Dual role already initialized
+	}
+
+#if USB_ID_EIC
+	_initialized = true;
+
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Set USB ID Pin as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+	port_pin_set_config(USB_ID_PIN, &pin_conf);
+
+	usb_id_config();
+	if (_usb_is_id_device()) {
+		UHC_MODE_CHANGE(false);
+		udc_start();
+	} else {
+		UHC_MODE_CHANGE(true);
+		uhc_start();
+	}
+
+	/**
+	 * End of host or device startup,
+	 * the current mode selected is already started now
+	 */
+	return true; // ID pin management has been enabled
+#else
+	return false; // ID pin management has not been enabled
+#endif
+}
+
+/**
+ * \brief Deinitialize the dual role driver
+ */
+void usb_dual_disable(void)
+{
+	if (!_initialized) {
+		return; // Dual role not initialized
+	}
+	_initialized = false;
+
+#if USB_ID_EIC
+	extint_chan_disable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+#endif
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.h
new file mode 100644
index 0000000000..60125d3d6f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Dual Role driver header file.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _USB_DUAL_H_
+#define _USB_DUAL_H_
+
+#include "compiler.h"
+#include "preprocessor.h"
+
+/* Get USB pads pins configuration in board configuration */
+#include "conf_board.h"
+#include "board.h"
+#include "extint.h"
+#include "port.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_dual_group USB dual role driver
+ * USB low-level driver for dual role features
+ *
+ * @{
+ */
+
+bool usb_dual_enable(void);
+void usb_dual_disable(void);
+
+/**
+ * @name USB ID pin management
+ *
+ * The ID pin come from the USB connector (A and B receptable) and
+ * allows to select the USB mode between host or device.
+ * The ID pin can be managed through EIC pin.
+ * This feature is optional, and it is enabled if USB_ID_PIN
+ * is defined in board.h and CONF_BOARD_USB_ID_DETECT defined in
+ * conf_board.h.
+*
+* @{
+*/
+#define USB_ID_DETECT        (defined(CONF_BOARD_USB_ID_DETECT))
+#define USB_ID_EIC           (defined(USB_ID_PIN) && USB_ID_DETECT)
+/** @} */
+
+/**
+ * @name USB Vbus management
+ *
+ * The VBus line can be monitored through a EIC pin and
+ * a basic resistor voltage divider.
+ * This feature is optional, and it is enabled if USB_VBUS_PIN
+ * is defined in board.h and CONF_BOARD_USB_VBUS_DETECT defined in
+ * conf_board.h.
+ *
+ * @{
+ */
+#define USB_VBUS_DETECT      (defined(CONF_BOARD_USB_VBUS_DETECT))
+#define USB_VBUS_EIC         (defined(USB_VBUS_PIN) && USB_VBUS_DETECT)
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _USB_DUAL_H_
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_host_uhd.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_host_uhd.c
new file mode 100644
index 0000000000..46f57c9096
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_host_uhd.c
@@ -0,0 +1,1667 @@
+/**
+ * \file
+ *
+ * \brief USB peripheral host wrapper for ASF Stack USB Host Driver (UHD)
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <string.h>
+#include <stdlib.h>
+
+/* Get USB host configuration */
+#include "conf_usb_host.h"
+#include "uhd.h"
+#include "usb.h"
+#include "usb_dual.h"
+
+/* Optional UHC callbacks */
+#ifndef UHC_MODE_CHANGE
+# define UHC_MODE_CHANGE(arg)
+#endif
+#ifndef UHC_SOF_EVENT
+# define UHC_SOF_EVENT()
+#endif
+#ifndef UHC_VBUS_CHANGE
+# define UHC_VBUS_CHANGE(b_present)
+#endif
+#ifndef UHC_VBUS_ERROR
+# define UHC_VBUS_ERROR()
+#endif
+
+/**
+ * \ingroup usb_host_group
+ * \defgroup usb_host_uhd_group USB Host Driver Implement (UHD)
+ * USB low-level driver for USB Host mode
+ * @{
+ */
+
+/* Function declare */
+static void _uhd_ctrl_phase_setup(void);
+static void _uhd_ctrl_phase_data_in_start(void);
+static void _uhd_ctrl_phase_data_in(uint16_t nb_byte_received);
+static void _uhd_ctrl_phase_zlp_in(void);
+static void _uhd_ctrl_phase_data_out(void);
+static void _uhd_ctrl_phase_zlp_out(void);
+static void _uhd_ctrl_request_end(uhd_trans_status_t status);
+static uint8_t _uhd_get_pipe(usb_add_t add, usb_ep_t endp);
+static void _uhd_pipe_trans_complete(struct usb_module *module_inst, void *);
+static void _uhd_ep_abort_pipe(uint8_t pipe, uhd_trans_status_t status);
+static void _uhd_pipe_finish_job(uint8_t pipe, uhd_trans_status_t status);
+
+/* for debug text */
+#ifdef USB_DEBUG
+#   define dbg_print printf
+#else
+#   define dbg_print(...)
+#endif
+
+/* Maximum size of a transfer in multipacket mode */
+#define UHD_ENDPOINT_MAX_TRANS ((8 *1024 ) - 1)
+
+/* pipe error status */
+#define USB_STATUS_PIPE_DTGLER    (1 << 0)
+#define USB_STATUS_PIPE_DAPIDER   (1 << 1)
+#define USB_STATUS_PIPE_PIDER     (1 << 2)
+#define USB_STATUS_PIPE_TOUTER    (1 << 3)
+#define USB_STATUS_PIPE_CRC16ER   (1 << 4)
+
+/* Check USB host configuration */
+#ifdef USB_HOST_HS_SUPPORT
+#  error The High speed mode is not supported on this part, please remove USB_HOST_HS_SUPPORT in conf_usb_host.h
+#endif
+
+#if (!(SAMD21) && !(SAMR21) && !(SAML21)) && !(SAMDA1) && !(SAMR30)
+# error The current USB Host Driver supports only SAMD21/R21/L21/R30
+#endif
+
+#ifdef USB_HOST_LPM_SUPPORT
+/** Notify that USB Host is enter in suspend LPM state */
+static bool uhd_lpm_suspend = false;
+#endif
+
+/** Store the callback to be called at the end of reset signal */
+static uhd_callback_reset_t uhd_reset_callback = NULL;
+
+/**
+ * \name Power management
+ *
+ * @{
+ */
+#ifndef UHD_NO_SLEEP_MGR
+
+#include "sleepmgr.h"
+/** States of USB interface */
+enum uhd_usb_state_enum {
+	UHD_STATE_OFF = 0,
+	UHD_STATE_WAIT_ID_HOST = 1,
+	UHD_STATE_NO_VBUS = 2,
+	UHD_STATE_DISCONNECT = 3,
+	UHD_STATE_SUSPEND = 4,
+	UHD_STATE_SUSPEND_LPM = 5,
+	UHD_STATE_IDLE = 6,
+};
+
+enum sleepmgr_mode sleep_mode[] = {
+	SLEEPMGR_STANDBY,  // UHD_STATE_OFF (not used)
+#if SAML21 || SAMR30
+	SLEEPMGR_IDLE,   // UHD_STATE_WAIT_ID_HOST
+	SLEEPMGR_IDLE,   // UHD_STATE_NO_VBUS
+	SLEEPMGR_IDLE,   // UHD_STATE_DISCONNECT
+	SLEEPMGR_IDLE,   // UHD_STATE_SUSPEND
+	SLEEPMGR_IDLE,   // UHD_STATE_SUSPEND_LPM
+	SLEEPMGR_IDLE,   // UHD_STATE_IDLE
+#else
+	SLEEPMGR_IDLE_0,   // UHD_STATE_WAIT_ID_HOST
+	SLEEPMGR_IDLE_0,   // UHD_STATE_NO_VBUS
+	SLEEPMGR_IDLE_0,   // UHD_STATE_DISCONNECT
+	SLEEPMGR_IDLE_2,   // UHD_STATE_SUSPEND
+	SLEEPMGR_IDLE_2,   // UHD_STATE_SUSPEND_LPM
+	SLEEPMGR_IDLE_0,   // UHD_STATE_IDLE
+#endif	
+};
+
+static enum uhd_usb_state_enum uhd_state = UHD_STATE_OFF;
+
+/** \brief Manages the sleep mode following the USB state
+ *
+ * \param new_state  New USB state
+ */
+static void uhd_sleep_mode(enum uhd_usb_state_enum new_state)
+{
+	if (uhd_state == new_state) {
+		return; // No change
+	}
+	if (new_state != UHD_STATE_OFF) {
+		/* Lock new limit */
+		sleepmgr_lock_mode(sleep_mode[new_state]);
+	}
+	if (uhd_state != UHD_STATE_OFF) {
+		/* Unlock old limit */
+		sleepmgr_unlock_mode(sleep_mode[uhd_state]);
+	}
+	uhd_state = new_state;
+}
+
+#else
+#  define uhd_sleep_mode(arg)
+#endif
+/** @} */
+
+/**
+ * \name Control endpoint low level management routine.
+ *
+ * This function performs control endpoint management.
+ * It handles the SETUP/DATA/HANDSHAKE phases of a control transaction.
+ *
+ * @{
+ */
+
+/**
+ * \brief Buffer to store the sent/received data on control endpoint
+ *
+ * Used to avoid a RAM buffer overflow when the payload buffer
+ * is smaller than control endpoint size.
+ * Also used when payload buffer is not word aligned.
+ */
+UHC_BSS(4)
+uint8_t uhd_ctrl_buffer[64];
+
+/**
+ * \brief Structure to store the high level setup request
+ */
+
+struct uhd_ctrl_request_t{
+	/** Buffer to store the setup DATA phase */
+	uint8_t *payload;
+	/** Callback called when buffer is empty or full */
+	uhd_callback_setup_run_t callback_run;
+	/** Callback called when request is completed */
+	uhd_callback_setup_end_t callback_end;
+	/** Next setup request to process */
+	struct uhd_ctrl_request_t *next_request;
+	/** Setup request definition */
+	usb_setup_req_t req;
+	/** Size of buffer used in DATA phase */
+	uint16_t payload_size;
+	/** USB address of control endpoint */
+	usb_add_t add;
+};
+
+/** Entry points of setup request list */
+struct uhd_ctrl_request_t *uhd_ctrl_request_first;
+struct uhd_ctrl_request_t *uhd_ctrl_request_last;
+
+/** Remaining time for on-going setup request (No request on-going if equal 0) */
+volatile uint16_t uhd_ctrl_request_timeout;
+
+/** Number of transfered byte on DATA phase of current setup request */
+uint16_t uhd_ctrl_nb_trans;
+
+/** Flag to delay a suspend request after all on-going setup request */
+static bool uhd_b_suspend_requested;
+
+/** Bit definitions to store setup request state machine */
+typedef enum {
+	/** Wait a SETUP packet */
+	UHD_CTRL_REQ_PHASE_SETUP = 0,
+	/** Wait a OUT data packet */
+	UHD_CTRL_REQ_PHASE_DATA_OUT = 1,
+	/** Wait a IN data packet */
+	UHD_CTRL_REQ_PHASE_DATA_IN = 2,
+	/** Wait a IN ZLP packet */
+	UHD_CTRL_REQ_PHASE_ZLP_IN = 3,
+	/** Wait a OUT ZLP packet */
+	UHD_CTRL_REQ_PHASE_ZLP_OUT = 4,
+} uhd_ctrl_request_phase_t;
+uhd_ctrl_request_phase_t uhd_ctrl_request_phase;
+
+/** @} */
+
+/**
+ * \name Management of bulk/interrupt/isochronous endpoints
+ *
+ * The UHD manages the data transfer on endpoints:
+ * - Start data transfer on endpoint with USB DMA
+ * - Send a ZLP packet if requested
+ * - Call registered callback to signal end of transfer
+ * The transfer abort and stall feature are supported.
+ *
+ * @{
+ */
+
+/** Structure definition to store registered jobs on a pipe */
+typedef struct {
+	/** Buffer located in internal RAM to send or fill during job */
+	uint8_t *buf;
+	/** Internal buffer allocated in internal RAM to receive data in case of small user buffer */
+	uint8_t *buf_internal;
+	/** Size of buffer to send or fill */
+	iram_size_t buf_size;
+	/** Total number of transferred data on endpoint */
+	iram_size_t nb_trans;
+	/** Callback to call at the end of transfer */
+	uhd_callback_trans_t call_end;
+
+	/** timeout on this request (ms) */
+	uint16_t timeout;
+
+	/** A job is registered on this pipe */
+	uint8_t busy:1;
+	/** A short packet is requested for this job on endpoint IN */
+	uint8_t b_shortpacket:1;
+} uhd_pipe_job_t;
+
+/** Array to register a job on bulk/interrupt/isochronous endpoint */
+static uhd_pipe_job_t uhd_pipe_job[USB_PIPE_NUM- 1];
+
+/** Variables to manage the suspend/resume sequence */
+static uint8_t uhd_suspend_start;
+static uint8_t uhd_resume_start;
+static uint8_t uhd_pipes_unfreeze;
+
+/** @} */
+
+
+struct usb_module dev;
+
+/**
+ * \internal
+ * \brief Sends a USB setup packet to start a control request sequence
+ */
+static void _uhd_ctrl_phase_setup(void)
+{
+	usb_setup_req_t setup_req;
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_SETUP;
+	memcpy( &setup_req, &uhd_ctrl_request_first->req, sizeof(usb_setup_req_t));
+	/* Manage LSB/MSB to fit with CPU usage */
+	setup_req.wValue = cpu_to_le16(setup_req.wValue);
+	setup_req.wIndex = cpu_to_le16(setup_req.wIndex);
+	setup_req.wLength = cpu_to_le16(setup_req.wLength);
+	uhd_ctrl_nb_trans = 0;
+
+  	/* Check pipe */
+#ifdef USB_HOST_HUB_SUPPORT
+	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE) {
+		_uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
+		return; // Endpoint not valid
+	}
+#error TODO check address in list
+	/* Reconfigure USB address of pipe 0 used for all control endpoints */
+	uhd_udesc_set_uhaddr(0, uhd_ctrl_request_first->add);
+#else
+	if ((cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE) ||
+			(uhd_ctrl_request_first->add != cfg.device_address)) {
+		_uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
+		return; // Endpoint not valid
+	}
+#endif
+
+	/* Fill pipe */
+	memcpy(uhd_ctrl_buffer, &setup_req, sizeof(setup_req));
+	uhd_ctrl_request_timeout = 5000;
+
+	/* Start transfer */
+	usb_host_pipe_setup_job(&dev, 0, uhd_ctrl_buffer);
+	usb_host_pipe_enable_callback(&dev, 0, USB_HOST_PIPE_CALLBACK_SETUP);
+}
+
+/**
+ * \internal
+ * \brief Starts the DATA IN phase on control endpoint
+ */
+static void _uhd_ctrl_phase_data_in_start(void)
+{
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_DATA_IN;
+
+	usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, cfg.size);
+}
+
+/**
+ * \internal
+ * \brief Manages the DATA IN phase on control endpoint
+ *
+ * \param nb_byte_received Number of bytes received
+ */
+static void _uhd_ctrl_phase_data_in(uint16_t nb_byte_received)
+{
+	bool b_short_packet;
+	uint8_t *ptr_ep_data;
+
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+	/** In HUB mode, the control pipe is always configured to 64B */
+	/** thus the short packet flag must be computed */
+	b_short_packet = (nb_byte_received != cfg.size);
+
+	ptr_ep_data = uhd_ctrl_buffer;
+uhd_ctrl_receiv_in_read_data:
+	/* Copy data from pipe to payload buffer */
+	while (uhd_ctrl_request_first->payload_size && nb_byte_received) {
+		*uhd_ctrl_request_first->payload++ = *ptr_ep_data++;
+		uhd_ctrl_nb_trans++;
+		uhd_ctrl_request_first->payload_size--;
+		nb_byte_received--;
+	}
+
+	if (!uhd_ctrl_request_first->payload_size && nb_byte_received) {
+		/* payload buffer is full to store data remaining */
+		if (uhd_ctrl_request_first->callback_run == NULL
+				|| !uhd_ctrl_request_first->callback_run(
+				cfg.device_address,
+				&uhd_ctrl_request_first->payload,
+				&uhd_ctrl_request_first->payload_size)) {
+			/* DATA phase aborted by host */
+			goto uhd_ctrl_phase_data_in_end;
+		}
+		/*
+		 * The payload buffer has been updated by the callback
+		 *  thus the data load can restart.
+		 */
+		goto uhd_ctrl_receiv_in_read_data;
+	}
+
+	/* Test short packet */
+	if ((uhd_ctrl_nb_trans == uhd_ctrl_request_first->req.wLength)
+			|| b_short_packet) {
+		/* End of DATA phase or DATA phase abort from device */
+uhd_ctrl_phase_data_in_end:
+		_uhd_ctrl_phase_zlp_out();
+		return;
+	}
+
+	usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, cfg.size);
+}
+
+/**
+ * \internal
+ * \brief Starts the ZLP IN phase on control endpoint
+ */
+static void _uhd_ctrl_phase_zlp_in(void)
+{
+	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_ZLP_IN;
+
+	usb_host_pipe_set_toggle(&dev, 0);
+
+	usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, 0);
+}
+
+/**
+ * \internal
+ * \brief Manages the DATA OUT phase on control endpoint
+ */
+static void _uhd_ctrl_phase_data_out(void)
+{
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_DATA_OUT;
+	uint16_t nb_trans;
+
+	if (uhd_ctrl_nb_trans == uhd_ctrl_request_first->req.wLength) {
+		/* End of DATA phase */
+		_uhd_ctrl_phase_zlp_in();
+		return;
+	}
+
+	if (!uhd_ctrl_request_first->payload_size) {
+		/* Buffer empty, then request a new buffer */
+		if (uhd_ctrl_request_first->callback_run==NULL
+				|| !uhd_ctrl_request_first->callback_run(
+				cfg.device_address,
+				&uhd_ctrl_request_first->payload,
+				&uhd_ctrl_request_first->payload_size)) {
+			/* DATA phase aborted by host */
+			_uhd_ctrl_phase_zlp_in();
+			return;
+		}
+	}
+
+	nb_trans = uhd_ctrl_request_first->payload_size;
+	if (nb_trans > cfg.size) {
+		nb_trans = cfg.size;
+	}
+
+	/* Link the user buffer directly on USB hardware DMA */
+	memcpy(uhd_ctrl_buffer, uhd_ctrl_request_first->payload, nb_trans);
+
+	/* Update counters */
+	uhd_ctrl_request_first->payload += nb_trans;
+	uhd_ctrl_nb_trans += nb_trans;
+	uhd_ctrl_request_first->payload_size -= nb_trans;
+
+	/* Start transfer */
+	usb_host_pipe_write_job(&dev, 0, uhd_ctrl_buffer, nb_trans);
+}
+
+/**
+ * \internal
+ * \brief Starts the ZLP OUT phase on control endpoint
+ */
+static void _uhd_ctrl_phase_zlp_out(void)
+{
+	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_ZLP_OUT;
+
+	usb_host_pipe_set_toggle(&dev, 0);
+
+	/* No need to link a user buffer directly on USB hardware DMA */
+	/* Start transfer */
+	usb_host_pipe_write_job(&dev, 0, uhd_ctrl_buffer, 0);
+}
+
+/**
+ * \internal
+ * \brief Call the callback linked to control request and start the next request
+ *
+ * \param status Request finish status passed to callback
+ */
+static void _uhd_ctrl_request_end(uhd_trans_status_t status)
+{
+	irqflags_t flags;
+	uhd_callback_setup_end_t callback_end;
+	struct uhd_ctrl_request_t *request_to_free;
+	bool b_new_request;
+
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+	Assert (uhd_ctrl_request_first != NULL);
+
+	uhd_ctrl_request_timeout = 0;
+
+	/* Remove request from the control request list */
+	callback_end = uhd_ctrl_request_first->callback_end;
+	request_to_free = uhd_ctrl_request_first;
+	flags = cpu_irq_save();
+	uhd_ctrl_request_first = uhd_ctrl_request_first->next_request;
+	b_new_request = (uhd_ctrl_request_first != NULL);
+	cpu_irq_restore(flags);
+	free(request_to_free);
+
+	/* Call callback */
+	if (callback_end != NULL) {
+		callback_end(cfg.device_address, status, uhd_ctrl_nb_trans);
+	}
+
+	/* If a setup request is pending and no started by previous callback */
+	if (b_new_request) {
+		_uhd_ctrl_phase_setup();
+	}
+	if (uhd_b_suspend_requested) {
+		/* A suspend request has been delay after all setup request */
+		uhd_b_suspend_requested = false;
+		uhd_suspend();
+	}
+}
+
+/**
+ * \internal
+ * \brief Manages timeouts and actions based on SOF events
+ * - Suspend delay
+ * - Resume delay
+ * - Setup packet delay
+ * - Timeout on endpoint control transfer
+ * - Timeouts on bulk/interrupt/isochronous endpoint transfers
+ * - UHC user notification
+ * - SOF user notification
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static void _uhd_sof_interrupt(struct usb_module *module_inst)
+{
+	/* Manage a delay to enter in suspend */
+	if (uhd_suspend_start) {
+		if (--uhd_suspend_start == 0) {
+			/* In case of high CPU frequency,
+			 *  the current Keep-Alive/SOF can be always on-going
+			 *  then wait end of SOF generation
+			 *  to be sure that disable SOF has been accepted
+			 */
+			dbg_print("SUSP\n");
+			usb_host_disable_sof(&dev);
+			/* Enable wakeup/resumes interrupts */
+			usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+			usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+			usb_host_enable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+
+			/* Check that the hardware state machine has left the IDLE/Active mode
+			 * before freeze USB clock
+			 */
+			while (2==usb_get_state_machine_status(&dev));
+			uhd_sleep_mode(UHD_STATE_SUSPEND);
+		}
+		return; // Abort SOF events
+	}
+	/* Manage a delay to exit of suspend */
+	if (uhd_resume_start) {
+		if (--uhd_resume_start == 0) {
+			/* Restore pipes unfrozen */
+			for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++) {
+				if ((uhd_pipes_unfreeze >> pipe) & 0x01) {
+					usb_host_pipe_unfreeze(&dev, pipe);
+				}
+			}
+			uhc_notify_resume();
+		}
+		return; // Abort SOF events
+	}
+	/* Manage the timeout on endpoint control transfer */
+	if (uhd_ctrl_request_timeout) {
+		/* Setup request on-going */
+		if (--uhd_ctrl_request_timeout == 0) {
+			/* Stop request */
+			usb_host_pipe_freeze(&dev, 0);
+			_uhd_ctrl_request_end(UHD_TRANS_TIMEOUT);
+		}
+	}
+	/* Manage the timeouts on endpoint transfer */
+	uhd_pipe_job_t *ptr_job;
+	for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++) {
+		ptr_job = &uhd_pipe_job[pipe - 1];
+		if (ptr_job->busy == true) {
+			if (ptr_job->timeout) {
+				/* Timeout enabled on this job */
+				if (--ptr_job->timeout == 0) {
+					/* Abort job */
+					_uhd_ep_abort_pipe(pipe,UHD_TRANS_TIMEOUT);
+				}
+			}
+		}
+	}
+
+	/* Notify the UHC */
+	uhc_notify_sof(false);
+
+	/* Notify the user application */
+	UHC_SOF_EVENT();
+}
+
+/**
+ * \internal
+ * \brief Manages bus reset interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static void _uhd_reset(struct usb_module *module_inst)
+{
+	if (uhd_reset_callback != NULL) {
+		uhd_reset_callback();
+	}
+}
+
+/**
+ * \internal
+ * \brief Manages wakeup interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static void _uhd_wakeup(struct usb_module *module_inst)
+{
+	/* Here the wakeup interrupt has been used to detect:
+	 * - connection with an asynchronous interrupt
+	 * - down/upstream resume with an asynchronous interrupt
+	 */
+	dbg_print("WAKEUP\n");
+#ifdef USB_HOST_LPM_SUPPORT
+	if (uhd_lpm_suspend) {
+		usb_host_send_l1_resume(&dev);
+		uhd_lpm_suspend = false;
+		uhc_notify_resume_lpm();
+	} else
+#endif
+	{
+		usb_host_send_resume(&dev);
+		/* Wait 50ms before restarting transfer */
+		uhd_resume_start = 50;
+	}
+	/* Disable wakeup/resumes interrupts */
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+	uhd_sleep_mode(UHD_STATE_IDLE);
+}
+
+/**
+ * \internal
+ * \brief Manages downstream resume interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static void _uhd_downstream_resume(struct usb_module *module_inst)
+{
+	dbg_print("DOWN RES\n");
+	/* Disable wakeup/resumes interrupts */
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+#ifdef USB_HOST_LPM_SUPPORT
+	if (uhd_lpm_suspend) {
+		uhd_lpm_suspend = false;
+		uhc_notify_resume_lpm();
+	} else
+#endif
+	{
+		/* Wait 50ms before restarting transfer */
+		uhd_resume_start = 50;
+	}
+	uhd_sleep_mode(UHD_STATE_IDLE);
+}
+
+/**
+ * \internal
+ * \brief Manages upstream resume interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static void _uhd_upstream_resume(struct usb_module *module_inst)
+{
+	dbg_print("UP RES\n");
+#ifdef USB_HOST_LPM_SUPPORT
+	if (uhd_lpm_suspend) {
+		usb_host_send_l1_resume(&dev);
+		uhd_lpm_suspend = false;
+		uhc_notify_resume_lpm();
+	} else
+#endif
+	{
+		usb_host_send_resume(&dev);
+		/* Wait 50ms before restarting transfer */
+		uhd_resume_start = 50;
+	}
+	/* Disable wakeup/resumes interrupts */
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+	uhd_sleep_mode(UHD_STATE_IDLE);
+}
+
+/**
+ * \internal
+ * \brief Manages ram access error interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static void _uhd_ram_error(struct usb_module *module_inst)
+{
+#ifdef UHC_RAM_ACCESS_ERR_EVENT
+	UHC_RAM_ACCESS_ERR_EVENT();
+#endif	
+	dbg_print("!!!! RAM ERR !!!!\n");
+}
+
+/**
+ * \internal
+ * \brief Manages connection interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static void _uhd_connect(struct usb_module *module_inst)
+{
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
+	dbg_print("CONN\n");
+	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+	usb_host_enable_sof(&dev);
+	uhd_sleep_mode(UHD_STATE_IDLE);
+	uhd_suspend_start = 0;
+	uhd_resume_start = 0;
+	uhc_notify_connection(true);
+}
+
+/**
+ * \internal
+ * \brief Manages disconnection interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static void _uhd_disconnect(struct usb_module *module_inst)
+{
+	/* This should be the normal way to handle this event. */
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
+	dbg_print("DISC\n");
+	/* Disable wakeup/resumes interrupts,
+	 * in case of disconnection during suspend mode
+	 */
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+	/* Enable asynchronous wakeup interrupt to allow a CPU wakeup
+	 * when a connection occurs.
+	 */
+	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
+	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+	uhd_suspend_start = 0;
+	uhd_resume_start = 0;
+	uhd_sleep_mode(UHD_STATE_DISCONNECT);
+	uhc_notify_connection(false);
+}
+
+#if USB_VBUS_EIC
+/**
+ * \name USB VBUS PAD management
+ *
+ * @{
+ */
+
+ /** Check if USB VBus is available */
+# define is_usb_vbus_high()           port_pin_get_input_level(USB_VBUS_PIN)
+
+/**
+ * USB VBUS pin change handler
+ */
+static void _uhd_vbus_handler(void)
+{
+	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	if (is_usb_vbus_high()) {
+		UHC_VBUS_CHANGE(true);
+	}
+	if (!is_usb_vbus_high()) {
+		uhd_sleep_mode(UHD_STATE_NO_VBUS);
+		UHC_VBUS_CHANGE(false);
+	}
+	extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+}
+
+/**
+ * USB VBUS pin config
+ */
+static void _usb_vbus_config(void)
+{
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Set USB VBUS Pin as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+	port_pin_set_config(USB_VBUS_PIN, &pin_conf);
+
+	/* Initialize EIC for vbus checking */
+	struct extint_chan_conf eint_chan_conf;
+	extint_chan_get_config_defaults(&eint_chan_conf);
+
+	eint_chan_conf.gpio_pin           = USB_VBUS_PIN;
+	eint_chan_conf.gpio_pin_mux       = USB_VBUS_EIC_MUX;
+	eint_chan_conf.detection_criteria = EXTINT_DETECT_LOW;
+	eint_chan_conf.filter_input_signal = true;
+
+	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	extint_chan_set_config(USB_VBUS_EIC_LINE, &eint_chan_conf);
+	extint_register_callback(_uhd_vbus_handler,
+			USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+}
+/** @} */
+#endif
+
+void uhd_enable(void)
+{
+	irqflags_t flags;
+
+	/* To avoid USB interrupt before end of initialization */
+	flags = cpu_irq_save();
+
+#if USB_ID_EIC
+	if (usb_dual_enable()) {
+		/* The current mode has been started by otg_dual_enable() */
+		cpu_irq_restore(flags);
+		return;
+	}
+#endif
+	uhd_ctrl_request_first = NULL;
+	uhd_ctrl_request_last = NULL;
+	uhd_ctrl_request_timeout = 0;
+	uhd_suspend_start = 0;
+	uhd_resume_start = 0;
+	uhd_b_suspend_requested = false;
+
+	struct usb_config cfg;
+	usb_get_config_defaults(&cfg);
+	cfg.select_host_mode = 1;
+	usb_init(&dev,USB, &cfg);
+	usb_enable(&dev);
+
+	uhd_sleep_mode(UHD_STATE_NO_VBUS);
+
+#if USB_VBUS_EIC
+	_usb_vbus_config();
+	if (is_usb_vbus_high()) {
+		/* Force Vbus interrupt when Vbus is always high */
+		_uhd_vbus_handler();
+		usb_host_enable(&dev);
+		uhd_sleep_mode(UHD_STATE_DISCONNECT);
+	} else {
+		dbg_print("VBUS low, there is some power issue on board!!! \n");
+	}
+#else
+	usb_host_enable(&dev);
+#endif
+
+	usb_host_register_callback(&dev, USB_HOST_CALLBACK_SOF, _uhd_sof_interrupt);
+	usb_host_register_callback(&dev, USB_HOST_CALLBACK_RESET, _uhd_reset);
+	usb_host_register_callback(&dev, USB_HOST_CALLBACK_WAKEUP, _uhd_wakeup);
+	usb_host_register_callback(&dev, USB_HOST_CALLBACK_DNRSM, _uhd_downstream_resume);
+	usb_host_register_callback(&dev, USB_HOST_CALLBACK_UPRSM, _uhd_upstream_resume);
+	usb_host_register_callback(&dev, USB_HOST_CALLBACK_RAMACER, _uhd_ram_error);
+	usb_host_register_callback(&dev, USB_HOST_CALLBACK_CONNECT, _uhd_connect);
+	usb_host_register_callback(&dev, USB_HOST_CALLBACK_DISCONNECT, _uhd_disconnect);
+
+	/* Enable main control interrupt */
+	/* Connection, SOF and reset */
+	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_SOF);
+	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_RESET);
+	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_RAMACER);
+	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
+	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
+
+	cpu_irq_restore(flags);
+}
+
+void uhd_disable(bool b_id_stop)
+{
+	irqflags_t flags;
+	UNUSED(b_id_stop);
+
+	/* Disable Vbus change interrupts */
+#if USB_VBUS_EIC
+	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+#endif
+
+ 	/* Disable main control interrupts */
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_SOF);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_RESET);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_RAMACER);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
+	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
+	usb_host_disable_sof(&dev);
+	uhc_notify_connection(false);
+
+#if USB_ID_EIC
+	uhd_sleep_mode(UHD_STATE_WAIT_ID_HOST);
+	if (!b_id_stop) {
+		return; // No need to disable host, it is done automatically by hardware
+	}
+#endif
+
+	flags = cpu_irq_save();
+	usb_dual_disable();
+	cpu_irq_restore(flags);
+}
+
+uhd_speed_t uhd_get_speed(void)
+{
+	switch (usb_host_get_speed(&dev)) {
+	case USB_SPEED_LOW:
+		return UHD_SPEED_LOW;
+	case USB_SPEED_FULL:
+		return UHD_SPEED_FULL;
+	default:
+		Assert(false);
+		return UHD_SPEED_LOW;
+	}
+}
+
+uint16_t uhd_get_frame_number(void)
+{
+	return usb_host_get_frame_number(&dev);
+}
+
+uint16_t uhd_get_microframe_number(void)
+{
+	/* nothing to do */
+	return 0;
+}
+
+void uhd_send_reset(uhd_callback_reset_t callback)
+{
+	uhd_reset_callback = callback;
+	usb_host_send_reset(&dev);
+}
+
+void uhd_suspend(void)
+{
+	if (uhd_ctrl_request_timeout) {
+		/* Delay suspend after setup requests */
+		uhd_b_suspend_requested = true;
+		return;
+	}
+	/* Save pipe freeze states and freeze pipes */
+	uhd_pipes_unfreeze = 0;
+	for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++) {
+		uhd_pipes_unfreeze |= (!usb_host_pipe_is_frozen(&dev, pipe)) << pipe;
+		usb_host_pipe_freeze(&dev, pipe);
+	}
+	/* Wait three SOFs before entering in suspend state */
+	uhd_suspend_start = 3;
+}
+
+bool uhd_is_suspend(void)
+{
+	return !usb_host_is_sof_enabled(&dev);
+}
+
+void uhd_resume(void)
+{
+	if (usb_host_is_sof_enabled(&dev)) {
+		/* Currently in IDLE mode (!=Suspend) */
+		if (uhd_suspend_start) {
+			/* Suspend mode on going
+			 * then stop it and start resume event
+			 */
+			uhd_suspend_start = 0;
+			uhd_resume_start = 1;
+		}
+		return;
+	}
+
+#ifdef USB_HOST_LPM_SUPPORT
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED) {
+		/* LPM Suspend command is on going, then ignore resume */
+		return;
+	}
+
+	if (uhd_lpm_suspend) {
+		dbg_print("SEND_RESUME_L1\n");
+		usb_host_send_l1_resume(&dev);
+	} else
+#endif
+	{
+		dbg_print("SEND_RESUME\n");
+		usb_host_send_resume(&dev);
+	}
+	uhd_sleep_mode(UHD_STATE_IDLE);
+}
+
+#ifdef USB_HOST_LPM_SUPPORT
+bool uhd_suspend_lpm(bool b_remotewakeup, uint8_t hird)
+{
+	if (uhd_ctrl_request_timeout) {
+		return false;
+	}
+	/* Do not freeze pipe to restart its immediatly after resume */
+	dbg_print("EXT_LPM\n");
+
+	/* Set the LPM job */
+	usb_host_pipe_lpm_job(&dev, 0, b_remotewakeup, hird);	
+
+	/* Wait LPM ACK through interrupt */
+	return true;
+}
+#endif
+
+bool uhd_setup_request(
+		usb_add_t add,
+		usb_setup_req_t *req,
+		uint8_t *payload,
+		uint16_t payload_size,
+		uhd_callback_setup_run_t callback_run,
+		uhd_callback_setup_end_t callback_end)
+{
+	irqflags_t flags;
+	struct uhd_ctrl_request_t *request;
+	bool b_start_request = false;
+
+	request = malloc(sizeof(struct uhd_ctrl_request_t));
+	if (request == NULL) {
+		Assert(false);
+		return false;
+	}
+
+	/* Fill structure */
+	request->add = (uint8_t) add;
+	memcpy(&request->req, req, sizeof(usb_setup_req_t));
+	request->payload = payload;
+	request->payload_size = payload_size;
+	request->callback_run = callback_run;
+	request->callback_end = callback_end;
+	request->next_request = NULL;
+
+	/* Add this request in the queue */
+	flags = cpu_irq_save();
+	if (uhd_ctrl_request_first == NULL) {
+		uhd_ctrl_request_first = request;
+		b_start_request = true;
+	} else {
+		uhd_ctrl_request_last->next_request = request;
+	}
+	uhd_ctrl_request_last = request;
+	cpu_irq_restore(flags);
+
+	if (b_start_request) {
+		/* Start immediately request */
+		_uhd_ctrl_phase_setup();
+	}
+	return true;
+}
+
+/**
+ * \internal
+ * \brief Manages endpoint 0 transfer complete interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pointer     Pointer to USB pipe transfer callback status parameters
+ */
+static void _uhd_ep0_transfer_complete(struct usb_module *module_inst, void *pointer)
+{
+	struct usb_pipe_callback_parameter *p_callback_para;
+	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+#ifdef USB_HOST_LPM_SUPPORT
+	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED) {
+		dbg_print("EXT_LPM_ACK\n");
+		cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+		usb_host_pipe_set_config(&dev, 0, &cfg);
+		/* Enable wakeup/resumes interrupts */
+		usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+		usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+		usb_host_enable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+		uhd_lpm_suspend = true;
+		uhd_sleep_mode(UHD_STATE_SUSPEND_LPM);
+		return;
+	}
+#endif
+
+	usb_host_pipe_freeze(&dev, 0);
+	switch(uhd_ctrl_request_phase) {
+	case UHD_CTRL_REQ_PHASE_DATA_IN:
+		_uhd_ctrl_phase_data_in(p_callback_para->transfered_size);
+		break;
+	case UHD_CTRL_REQ_PHASE_ZLP_IN:
+		_uhd_ctrl_request_end(UHD_TRANS_NOERROR);
+		break;
+	case UHD_CTRL_REQ_PHASE_DATA_OUT:
+		_uhd_ctrl_phase_data_out();
+		break;
+	case UHD_CTRL_REQ_PHASE_ZLP_OUT:
+		_uhd_ctrl_request_end(UHD_TRANS_NOERROR);
+		break;
+	default:
+		Assert(false);
+		break;
+	}
+}
+
+/**
+ * \internal
+ * \brief Manages endpoint 0 error interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pointer     Pointer to USB pipe transfer callback status parameters
+ */
+static void _uhd_ep0_error(struct usb_module *module_inst, void *pointer)
+{
+#ifdef USB_HOST_LPM_SUPPORT
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED) {
+		dbg_print("EXT_LPM_ERROR\n");
+		cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+		usb_host_pipe_set_config(&dev, 0, &cfg);
+		return;
+	}
+#endif
+
+	dbg_print("CTRL Error\n");
+	struct usb_pipe_callback_parameter *p_callback_para;
+	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+
+	uhd_trans_status_t uhd_error;
+
+	/* Get and ack error */
+	switch(p_callback_para->pipe_error_status) {
+	case USB_STATUS_PIPE_DTGLER:
+		uhd_error = UHD_TRANS_DT_MISMATCH;
+		break;
+	case USB_STATUS_PIPE_TOUTER:
+		uhd_error = UHD_TRANS_NOTRESPONDING;
+		break;
+	case USB_STATUS_PIPE_CRC16ER:
+		uhd_error = UHD_TRANS_CRC;
+		break;
+	case USB_STATUS_PIPE_DAPIDER:
+	case USB_STATUS_PIPE_PIDER:
+		uhd_error = UHD_TRANS_PIDFAILURE;
+		break;
+	default:
+		uhd_error = UHD_TRANS_TIMEOUT;
+		break;
+	}
+
+	/* Get and ack error */
+	_uhd_ctrl_request_end(uhd_error);
+}
+
+/**
+ * \internal
+ * \brief Manages endpoint 0 setup interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param null        Not used
+ */
+static void _uhd_ep0_setup(struct usb_module *module_inst, void *null)
+{
+	/* SETUP packet sent */
+	usb_host_pipe_freeze(&dev, 0);
+	dbg_print("CTRL Setup\n");
+	Assert(uhd_ctrl_request_phase == UHD_CTRL_REQ_PHASE_SETUP);
+
+	/* Start DATA phase */
+	if ((uhd_ctrl_request_first->req.bmRequestType & USB_REQ_DIR_MASK)
+			== USB_REQ_DIR_IN ) {
+		_uhd_ctrl_phase_data_in_start();
+	} else {
+		if (uhd_ctrl_request_first->req.wLength) {
+			_uhd_ctrl_phase_data_out();
+		} else {
+			/* No DATA phase */
+			_uhd_ctrl_phase_zlp_in();
+		}
+	}
+}
+
+/**
+ * \internal
+ * \brief Manages endpoint 0 stall interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param null        Not used
+ */
+static void _uhd_ep0_stall(struct usb_module *module_inst, void *null)
+{
+#ifdef USB_HOST_LPM_SUPPORT
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, 0, &cfg);
+
+	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED) {
+		dbg_print("EXT_LPM_STALL\n");
+		cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+		usb_host_pipe_set_config(&dev, 0, &cfg);
+		return;
+	}
+#endif
+
+	dbg_print("CTRL Stall\n");
+	/* Stall Handshake received */
+	_uhd_ctrl_request_end(UHD_TRANS_STALL);
+}
+
+
+/**
+ * \internal
+ * \brief Returns the pipe number matching a USB endpoint
+ *
+ * \param add   USB device address
+ * \param endp  Endpoint Address
+ *
+ * \return Pipe number
+ */
+static uint8_t _uhd_get_pipe(usb_add_t add, usb_ep_t endp)
+{
+	struct usb_host_pipe_config cfg;
+	uint8_t usb_pipe = 1;
+	for (;usb_pipe < USB_PIPE_NUM;usb_pipe ++) {
+		usb_host_pipe_get_config(&dev, usb_pipe, &cfg);
+		if ((add == cfg.device_address) && (endp == cfg.endpoint_address)) {
+			return usb_pipe;
+		}
+	}
+	return 0;
+}
+
+/**
+ * \internal
+ * \brief Computes and starts the next transfer on a pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pointer     Pointer to USB pipe transfer callback status parameters
+ */
+static void _uhd_pipe_trans_complete(struct usb_module *module_inst, void *pointer)
+{
+	struct usb_pipe_callback_parameter *p_callback_para;
+	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, p_callback_para->pipe_num, &cfg);
+
+	uhd_pipe_job_t *ptr_job;
+	uint16_t pipe_size, nb_trans;
+	uint16_t max_trans;
+	iram_size_t next_trans;
+	irqflags_t flags;
+
+	pipe_size = cfg.size;
+
+	/* Get job corresponding at endpoint */
+	ptr_job = &uhd_pipe_job[p_callback_para->pipe_num - 1];
+
+	if (!ptr_job->busy) {
+		return; // No job is running, then ignore it (system error)
+	}
+
+	if (!(cfg.endpoint_address & USB_EP_DIR_IN)) {
+		usb_host_pipe_freeze(&dev, p_callback_para->pipe_num);
+		/* Transfer complete on OUT */
+		nb_trans = p_callback_para->transfered_size;
+
+		/* Update number of transferred data */
+		ptr_job->nb_trans += nb_trans;
+
+		/* Need to send other data */
+		if ((ptr_job->nb_trans != ptr_job->buf_size)
+				|| ptr_job->b_shortpacket) {
+			next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+			if (UHD_ENDPOINT_MAX_TRANS < next_trans) {
+				/**
+				 * The USB hardware supports a maximum
+				 * transfer size of UHD_ENDPOINT_MAX_TRANS Bytes
+				 */
+				next_trans = UHD_ENDPOINT_MAX_TRANS -
+					(UHD_ENDPOINT_MAX_TRANS % pipe_size);
+				usb_host_pipe_set_auto_zlp(&dev, p_callback_para->pipe_num, false);
+			} else {
+				/* Need ZLP, if requested and last packet is not a short packet */
+				usb_host_pipe_set_auto_zlp(&dev, p_callback_para->pipe_num, ptr_job->b_shortpacket);
+				ptr_job->b_shortpacket = false; // No need to request another ZLP
+			}
+			usb_host_pipe_write_job(&dev, p_callback_para->pipe_num, &ptr_job->buf[ptr_job->nb_trans], next_trans);
+
+			/* Enable interrupt */
+			flags = cpu_irq_save();
+			usb_host_pipe_enable_callback(&dev,p_callback_para->pipe_num,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
+			cpu_irq_restore(flags);
+			return;
+		}
+	} else {
+		/* Transfer complete on IN */
+		nb_trans = p_callback_para->transfered_size;
+
+		/* May be required to copy received data from cache buffer to user buffer */
+		if (ptr_job->buf_internal != NULL) {
+			memcpy(&ptr_job->buf[ptr_job->nb_trans],
+					ptr_job->buf_internal,
+					ptr_job->buf_size % pipe_size);
+			free(ptr_job->buf_internal);
+			ptr_job->buf_internal = NULL;
+		}
+
+		/* Update number of transfered data */
+		ptr_job->nb_trans += nb_trans;
+		if (ptr_job->nb_trans > ptr_job->buf_size) {
+			ptr_job->nb_trans = ptr_job->buf_size;
+		}
+
+		/**
+		 * If all previous requested data have been received and user buffer not full
+		 * then need to receive other data
+		 */
+		if ((nb_trans == p_callback_para->required_size)
+			&& (ptr_job->nb_trans != ptr_job->buf_size)) {
+			next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+			max_trans = UHD_ENDPOINT_MAX_TRANS;
+			/* 256 is the maximum of IN requests via UPINRQ */
+			if ((256L * pipe_size) < UHD_ENDPOINT_MAX_TRANS) {
+				max_trans = 256L * pipe_size;
+			}
+			if (max_trans < next_trans) {
+				/* The USB hardware support a maximum transfer size
+				  * of UHD_ENDPOINT_MAX_TRANS Bytes
+				  */
+				next_trans = max_trans;
+			}
+
+			if (next_trans < pipe_size) {
+				/* Use the cache buffer for Bulk or Interrupt size endpoint */
+				ptr_job->buf_internal = malloc(pipe_size);
+				if (ptr_job->buf_internal == NULL) {
+					Assert(ptr_job->buf_internal != NULL);
+					goto uhd_pipe_trans_complet_end;
+				}
+				usb_host_pipe_read_job(&dev, p_callback_para->pipe_num, ptr_job->buf_internal, pipe_size);
+			} else {
+				next_trans -= next_trans % pipe_size;
+				/* Link the user buffer directly on USB hardware DMA */
+				usb_host_pipe_read_job(&dev, p_callback_para->pipe_num, &ptr_job->buf[ptr_job->nb_trans], next_trans);
+			}
+			/* Enable interrupt */
+			flags = cpu_irq_save();
+			usb_host_pipe_enable_callback(&dev,p_callback_para->pipe_num,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
+			cpu_irq_restore(flags);
+			return;
+		}
+	}
+
+uhd_pipe_trans_complet_end:
+	/* Call callback to signal end of transfer */
+	_uhd_pipe_finish_job(p_callback_para->pipe_num, UHD_TRANS_NOERROR);
+	return;
+}
+
+/**
+ * \internal
+ * \brief Aborts the on-going transfer on a pipe
+ *
+ * \param pipe   Pipe number
+ * \param status Reason of abort
+ */
+static void _uhd_ep_abort_pipe(uint8_t pipe, uhd_trans_status_t status)
+{
+	usb_host_pipe_freeze(&dev, pipe);
+	_uhd_pipe_finish_job(pipe, status);
+}
+
+/**
+ * \internal
+ * \brief Call the callback linked to the end of pipe transfer
+ *
+ * \param pipe   Pipe number
+ * \param status Status of the transfer
+ */
+static void _uhd_pipe_finish_job(uint8_t pipe, uhd_trans_status_t status)
+{
+	uhd_pipe_job_t *ptr_job;
+
+	struct usb_host_pipe_config cfg;
+	usb_host_pipe_get_config(&dev, pipe, &cfg);
+
+	/* Get job corresponding at endpoint */
+	ptr_job = &uhd_pipe_job[pipe - 1];
+	if (ptr_job->busy == false) {
+		return; // No job running
+	}
+	/* In case of abort, free the internal buffer */
+	if (ptr_job->buf_internal != NULL) {
+		free(ptr_job->buf_internal);
+		ptr_job->buf_internal = NULL;
+	}
+	ptr_job->busy = false;
+	if (NULL == ptr_job->call_end) {
+		return; // No callback linked to job
+	}
+	ptr_job->call_end(cfg.device_address,
+			cfg.endpoint_address,
+			status, ptr_job->nb_trans);
+}
+
+/**
+ * \internal
+ * \brief Manages pipe endpoint error callback
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pointer     Pointer to USB pipe transfer callback status parameters
+ */
+static void _uhd_ep_error(struct usb_module *module_inst, void *pointer)
+{
+	uhd_trans_status_t uhd_error;
+	struct usb_pipe_callback_parameter *p_callback_para;
+	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+
+	dbg_print("Tr Error %x\n", p_callback_para->pipe_num);
+	/* Get and ack error */
+	switch(p_callback_para->pipe_error_status) {
+	case USB_STATUS_PIPE_DTGLER:
+		uhd_error = UHD_TRANS_DT_MISMATCH;
+		break;
+	case USB_STATUS_PIPE_TOUTER:
+		uhd_error = UHD_TRANS_NOTRESPONDING;
+		break;
+	case USB_STATUS_PIPE_CRC16ER:
+		uhd_error = UHD_TRANS_CRC;
+		break;
+	case USB_STATUS_PIPE_DAPIDER:
+	case USB_STATUS_PIPE_PIDER:
+		uhd_error = UHD_TRANS_PIDFAILURE;
+		break;
+	default:
+		uhd_error = UHD_TRANS_TIMEOUT;
+		break;
+	}
+
+	_uhd_ep_abort_pipe(p_callback_para->pipe_num, uhd_error);
+}
+
+/**
+ * \internal
+ * \brief Manages pipe endpoint stall interrupt
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pointer     Pointer to USB pipe transfer callback status parameters
+ */
+static void _uhd_ep_stall(struct usb_module *module_inst, void *pointer)
+{
+	struct usb_pipe_callback_parameter *p_callback_para;
+	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+
+	dbg_print("Tr Stall %x\n", p_callback_para->pipe_num);
+	usb_host_pipe_clear_toggle(&dev, p_callback_para->pipe_num);
+	_uhd_ep_abort_pipe(p_callback_para->pipe_num, UHD_TRANS_STALL);
+}
+
+bool uhd_ep0_alloc(usb_add_t add, uint8_t ep_size)
+{
+	struct usb_host_pipe_config cfg;
+
+	if (ep_size < 8) {
+		return false;
+	}
+
+	usb_host_pipe_get_config_defaults(&cfg);
+	cfg.device_address = add;
+	cfg.size = ep_size;
+	cfg.binterval = 0;
+	usb_host_pipe_set_config(&dev,0,&cfg);
+	usb_host_pipe_register_callback(&dev, 0,
+			USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE, _uhd_ep0_transfer_complete);
+	usb_host_pipe_register_callback(&dev, 0,
+			USB_HOST_PIPE_CALLBACK_ERROR, _uhd_ep0_error);
+	usb_host_pipe_register_callback(&dev, 0,
+			USB_HOST_PIPE_CALLBACK_SETUP, _uhd_ep0_setup);
+	usb_host_pipe_register_callback(&dev, 0,
+			USB_HOST_PIPE_CALLBACK_STALL, _uhd_ep0_stall);
+	/* Always enable stall and error interrupts of control endpoint */
+	usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
+	usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_ERROR);
+	usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_SETUP);
+	usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_STALL);
+	return true;
+}
+
+bool uhd_ep_alloc(usb_add_t add, usb_ep_desc_t *ep_desc)
+{
+	uint8_t pipe = 1;
+	struct usb_host_pipe_config cfg;
+	uint8_t ep_type;
+	uint8_t ep_interval;
+
+	for (pipe = 1; pipe < USB_PIPE_NUM; pipe++) {
+		usb_host_pipe_get_config(&dev, pipe, &cfg);
+		if (cfg.pipe_type != USB_HOST_PIPE_TYPE_DISABLE) {
+			continue;
+		}
+		usb_host_pipe_get_config_defaults(&cfg);
+		/* Enable pipe */
+		ep_type = (ep_desc->bmAttributes & USB_EP_TYPE_MASK) + 1;
+		if (ep_type == USB_HOST_PIPE_TYPE_BULK) {
+			ep_interval = 0; // Ignore bInterval for bulk endpoint
+		} else {
+			ep_interval = ep_desc->bInterval;
+		}
+		cfg.device_address = add;
+		cfg.endpoint_address = ep_desc->bEndpointAddress;
+		cfg.pipe_type = (enum usb_host_pipe_type)ep_type;
+		cfg.binterval = ep_interval;
+		cfg.size = le16_to_cpu(ep_desc->wMaxPacketSize);
+		usb_host_pipe_set_config(&dev,pipe,&cfg);
+
+		usb_host_pipe_register_callback(&dev, pipe,
+				USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE, _uhd_pipe_trans_complete);
+		usb_host_pipe_register_callback(&dev,pipe,
+				USB_HOST_PIPE_CALLBACK_ERROR, _uhd_ep_error);
+		usb_host_pipe_register_callback(&dev,pipe,
+				USB_HOST_PIPE_CALLBACK_STALL, _uhd_ep_stall);
+		/* Enable endpoint interrupts */
+		usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
+		usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_ERROR);
+		usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_STALL);
+		return true;
+	}
+	return false;
+}
+
+
+void uhd_ep_free(usb_add_t add, usb_ep_t endp)
+{
+	uint8_t usb_pipe = 0;
+	struct usb_host_pipe_config cfg;
+
+	/* Search endpoint(s) in all pipes */
+	for (usb_pipe = 0; usb_pipe < USB_PIPE_NUM; usb_pipe++) {
+		usb_host_pipe_get_config(&dev, usb_pipe, &cfg);
+
+		if (cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE) {
+			continue;
+		}
+
+		if (add != cfg.device_address) {
+			continue;
+		}
+
+		if (endp != 0xFF) {
+			/* Disable specific endpoint number */
+			if (!((endp == 0) && (0 == cfg.endpoint_address))) {
+				/* It is not the control endpoint */
+				if (endp != cfg.endpoint_address) {
+					continue; // Mismatch
+				}
+			}
+		}
+
+		if (usb_pipe == 0) {
+			/* Disable and stop transfer on control endpoint */
+			if (cfg.device_address == add) {
+				usb_host_pipe_freeze(&dev, 0);
+				if (uhd_ctrl_request_timeout ||
+						(uhd_ctrl_request_first != NULL)) {
+					_uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
+				}
+				continue;
+			}
+		}
+
+		/* Endpoint interrupt, bulk or isochronous */
+		/* Disable and stop transfer on this pipe */
+		usb_host_pipe_freeze(&dev, usb_pipe);
+		_uhd_pipe_finish_job(usb_pipe, UHD_TRANS_DISCONNECT);
+	}
+}
+
+bool uhd_ep_run(
+		usb_add_t add,
+		usb_ep_t endp,
+		bool b_shortpacket,
+		uint8_t *buf,
+		iram_size_t buf_size,
+		uint16_t timeout,
+		uhd_callback_trans_t callback)
+{
+	irqflags_t flags;
+	uhd_pipe_job_t *ptr_job;
+	uint8_t pipe = 0;
+
+	struct usb_pipe_callback_parameter callback_para;
+
+	pipe = _uhd_get_pipe(add,endp);
+	if (!pipe) {
+		return false;
+	}
+	/* Get job about pipe */
+	ptr_job = &uhd_pipe_job[pipe - 1];
+	flags = cpu_irq_save();
+	if (ptr_job->busy == true) {
+		cpu_irq_restore(flags);
+		return false; // Job already on going
+	}
+	ptr_job->busy = true;
+
+	/* No job running. Let's setup a new one. */
+	ptr_job->buf = buf;
+	ptr_job->buf_size = buf_size;
+	ptr_job->nb_trans = 0;
+	ptr_job->timeout = timeout;
+	ptr_job->b_shortpacket = b_shortpacket;
+	ptr_job->call_end = callback;
+	cpu_irq_restore(flags);
+
+	/* Request first transfer */
+	callback_para.pipe_num = pipe;
+	callback_para.transfered_size = 0;
+	callback_para.required_size = 0;
+	_uhd_pipe_trans_complete(&dev, &callback_para);
+	return true;
+}
+
+void uhd_ep_abort(usb_add_t add, usb_ep_t endp)
+{
+	uint8_t usb_pipe = 0;
+
+	usb_pipe = _uhd_get_pipe(add, endp);
+	if (usb_pipe) {
+		_uhd_ep_abort_pipe(usb_pipe, UHD_TRANS_ABORTED);
+	}
+}
+
+/** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb.h
new file mode 100644
index 0000000000..fa29b1ffed
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb.h
@@ -0,0 +1,833 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef USB_H_INCLUDED
+#define USB_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_usb_group SAM Universal Serial Bus (USB)
+ *
+ * The Universal Serial Bus (USB) module complies with the USB 2.1 specification.
+ *
+ * The following peripherals are used by this module:
+ *  - USB (Universal Serial Bus)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D11 (Only USB device support on SAM D11 device)
+ *  - Atmel | SMART SAM L21
+ *  - Atmel | SMART SAM L22 (Only USB device support on SAM L22 device)
+ *  - Atmel | SMART SAM DA1
+ *
+ * The USB module covers following mode:
+ * \if USB_DEVICE_MODE
+ *  - USB Device Mode
+ * \endif
+ * \if USB_HOST_MODE
+ *  - USB Host Mode
+ * \endif
+ *
+ * The USB module covers following speed:
+ * \if USB_HS_MODE
+ *  - USB High Speed (480Mbit/s)
+ * \endif
+ *  - USB Full Speed (12Mbit/s)
+ * \if USB_LS_MODE
+ *  - USB Low Speed (1.5Mbit/s)
+ * \endif
+ *
+ * \if USB_LPM_MODE
+ * The USB module supports Link Power Management (LPM-L1) protocol.
+ * \endif
+ *
+ * USB support needs whole set of enumeration process, to make the device
+ * recognizable and usable. The USB driver is designed to interface to the
+ * USB Stack in Atmel Software Framework (ASF).
+ *
+ * \if USB_DEVICE_MODE
+ * \section asfdoc_sam0_usb_device USB Device Mode
+ * The ASF USB Device Stack has defined the USB Device Driver (UDD) interface,
+ * to support USB device operations. The USB module device driver complies with
+ * this interface, so that the USB Device Stack can work based on the
+ * USB module.
+ *
+ * Refer to <a href="http://www.atmel.com/images/doc8360.pdf">
+ * "ASF - USB Device Stack"</a> for more details.
+ * \endif
+ *
+ * \if USB_HOST_MODE
+ * \section adfdoc_sam0_usb_host USB Host Mode
+ * The ASF USB Host Stack has defined the USB Host Driver (UHD) interface,
+ * to support USB host operations. The USB module host driver complies with
+ * this interface, so that the USB Host Stack can work based on the USB module.
+ *
+ * Refer to <a href="http://www.atmel.com/images/doc8486.pdf">
+ * "ASF - USB Host Stack"</a> for more details.
+ * \endif
+ */
+
+/** Enum for the speed status for the USB module */
+enum usb_speed {
+	USB_SPEED_LOW,
+	USB_SPEED_FULL,
+};
+
+/** Enum for the possible callback types for the USB in host module */
+enum usb_host_callback {
+	USB_HOST_CALLBACK_SOF,
+	USB_HOST_CALLBACK_RESET,
+	USB_HOST_CALLBACK_WAKEUP,
+	USB_HOST_CALLBACK_DNRSM,
+	USB_HOST_CALLBACK_UPRSM,
+	USB_HOST_CALLBACK_RAMACER,
+	USB_HOST_CALLBACK_CONNECT,
+	USB_HOST_CALLBACK_DISCONNECT,
+	USB_HOST_CALLBACK_N,
+};
+
+/** Enum for the possible callback types for the USB pipe in host module */
+enum usb_host_pipe_callback {
+	USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE,
+	USB_HOST_PIPE_CALLBACK_ERROR,
+	USB_HOST_PIPE_CALLBACK_SETUP,
+	USB_HOST_PIPE_CALLBACK_STALL,
+	USB_HOST_PIPE_CALLBACK_N,
+};
+
+/**
+ * \brief Host pipe types.
+ */
+enum usb_host_pipe_type {
+	USB_HOST_PIPE_TYPE_DISABLE,
+	USB_HOST_PIPE_TYPE_CONTROL,
+	USB_HOST_PIPE_TYPE_ISO,
+	USB_HOST_PIPE_TYPE_BULK,
+	USB_HOST_PIPE_TYPE_INTERRUPT,
+	USB_HOST_PIPE_TYPE_EXTENDED,
+};
+
+/**
+ * \brief Host pipe token types.
+ */
+enum usb_host_pipe_token {
+	USB_HOST_PIPE_TOKEN_SETUP,
+	USB_HOST_PIPE_TOKEN_IN,
+	USB_HOST_PIPE_TOKEN_OUT,
+};
+
+/**
+ * \brief Enumeration for the possible callback types for the USB in device module
+ */
+enum usb_device_callback {
+	USB_DEVICE_CALLBACK_SOF,
+	USB_DEVICE_CALLBACK_RESET,
+	USB_DEVICE_CALLBACK_WAKEUP,
+	USB_DEVICE_CALLBACK_RAMACER,
+	USB_DEVICE_CALLBACK_SUSPEND,
+	USB_DEVICE_CALLBACK_LPMNYET,
+	USB_DEVICE_CALLBACK_LPMSUSP,
+	USB_DEVICE_CALLBACK_N,
+};
+
+/**
+ * \brief Enumeration for the possible callback types for the USB endpoint in device module
+ */
+enum usb_device_endpoint_callback {
+	USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,
+	USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,
+	USB_DEVICE_ENDPOINT_CALLBACK_RXSTP,
+	USB_DEVICE_ENDPOINT_CALLBACK_STALL,
+	USB_DEVICE_EP_CALLBACK_N,
+};
+
+/**
+ * \brief Device Endpoint types.
+ */
+enum usb_device_endpoint_type {
+	USB_DEVICE_ENDPOINT_TYPE_DISABLE,
+	USB_DEVICE_ENDPOINT_TYPE_CONTROL,
+	USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS,
+	USB_DEVICE_ENDPOINT_TYPE_BULK,
+	USB_DEVICE_ENDPOINT_TYPE_INTERRUPT,
+};
+
+/**
+ * \brief Endpoint Size
+ */
+enum usb_endpoint_size {
+	USB_ENDPOINT_8_BYTE,
+	USB_ENDPOINT_16_BYTE,
+	USB_ENDPOINT_32_BYTE,
+    USB_ENDPOINT_64_BYTE,
+	USB_ENDPOINT_128_BYTE,
+	USB_ENDPOINT_256_BYTE,
+	USB_ENDPOINT_512_BYTE,
+	USB_ENDPOINT_1023_BYTE,
+};
+
+/**
+ * \brief Link Power Management Handshake.
+ */
+enum usb_device_lpm_mode {
+	USB_DEVICE_LPM_NOT_SUPPORT,
+	USB_DEVICE_LPM_ACK,
+	USB_DEVICE_LPM_NYET,
+};
+
+/**
+ * \brief Module structure
+ */
+struct usb_module;
+
+/**
+ * \name Host Callback Functions Types
+ * @{
+ */
+typedef void (*usb_host_callback_t)(struct usb_module *module_inst);
+typedef void (*usb_host_pipe_callback_t)(struct usb_module *module_inst, void *);
+/** @} */
+
+/**
+ * \name Device Callback Functions Types
+ * @{
+ */
+typedef void (*usb_device_callback_t)(struct usb_module *module_inst, void* pointer);
+typedef void (*usb_device_endpoint_callback_t)(struct usb_module *module_inst, void* pointer);
+/** @} */
+
+
+/** USB configurations */
+struct usb_config {
+	/** \c true for host, \c false for device. */
+	bool select_host_mode;
+	/** When \c true the module is enabled during standby. */
+	bool run_in_standby;
+	/** Generic Clock Generator source channel. */
+	enum gclk_generator source_generator;
+	/** Speed mode */
+	enum usb_speed speed_mode;
+};
+
+/**
+ * \brief USB software module instance structure.
+ *
+ * USB software module instance structure, used to retain software state
+ * information of an associated hardware module instance.
+ *
+ */
+struct usb_module {
+	/** Hardware module pointer of the associated USB peripheral. */
+	Usb *hw;
+
+#if !SAMD11 && !SAML22
+	/** Array to store host related callback functions */
+	usb_host_callback_t host_callback[USB_HOST_CALLBACK_N];
+	usb_host_pipe_callback_t host_pipe_callback[USB_PIPE_NUM][USB_HOST_PIPE_CALLBACK_N];
+	/** Bit mask for host callbacks registered */
+	uint8_t host_registered_callback_mask;
+	/** Bit mask for host callbacks enabled */
+	uint8_t host_enabled_callback_mask;
+	/** Bit mask for host pipe callbacks registered */
+	uint8_t host_pipe_registered_callback_mask[USB_PIPE_NUM];
+	/** Bit mask for host pipe callbacks enabled */
+	uint8_t host_pipe_enabled_callback_mask[USB_PIPE_NUM];
+#endif
+
+	/** Array to store device related callback functions */
+	usb_device_callback_t device_callback[USB_DEVICE_CALLBACK_N];
+	usb_device_endpoint_callback_t device_endpoint_callback[USB_EPT_NUM][USB_DEVICE_EP_CALLBACK_N];
+	/** Bit mask for device callbacks registered */
+	uint16_t device_registered_callback_mask;
+	/** Bit mask for device callbacks enabled */
+	uint16_t device_enabled_callback_mask;
+	/** Bit mask for device endpoint callbacks registered */
+	uint8_t device_endpoint_registered_callback_mask[USB_EPT_NUM];
+	/** Bit mask for device endpoint callbacks enabled */
+	uint8_t device_endpoint_enabled_callback_mask[USB_EPT_NUM];
+};
+
+/** USB host pipe configurations */
+struct usb_host_pipe_config {
+	/** device address */
+	uint8_t device_address;
+	/** endpoint address  */
+	uint8_t endpoint_address;
+	/** Pipe type */
+	enum usb_host_pipe_type pipe_type;
+	/** interval */
+	uint8_t binterval;
+	/** pipe size */
+	uint16_t size;
+};
+
+/** USB device endpoint configurations */
+struct usb_device_endpoint_config {
+	/** device address */
+	uint8_t ep_address;
+	/** endpoint size */
+	enum usb_endpoint_size ep_size;
+	/** automatic zero length packet mode, \c true to enable */
+	bool auto_zlp;
+	/** type of endpoint with Bank */
+	enum usb_device_endpoint_type ep_type;
+};
+
+/** USB host pipe callback status parameter structure */
+struct usb_pipe_callback_parameter {
+	/** current pipe number */
+	uint8_t pipe_num;
+	/** pipe error status */
+	uint8_t pipe_error_status;
+	/** actual transferred data size */
+	uint16_t transfered_size;
+	/** required data size */
+	uint16_t required_size;
+};
+
+/** USB device endpoint callback status parameter structure */
+struct usb_endpoint_callback_parameter {
+	uint16_t received_bytes;
+	uint16_t sent_bytes;
+	uint16_t out_buffer_size;
+	uint8_t endpoint_address;
+};
+
+void usb_enable(struct usb_module *module_inst);
+void usb_disable(struct usb_module *module_inst);
+
+/**
+ * \brief Get the status of USB module's state machine
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static inline uint8_t usb_get_state_machine_status(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return module_inst->hw->DEVICE.FSMSTATUS.reg;
+}
+
+void usb_get_config_defaults(struct usb_config *module_config);
+enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
+		struct usb_config *module_config);
+
+#if !SAMD11 && !SAML22
+/**
+ * \brief Enable the USB host by setting the VBUS OK
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_enable(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.VBUSOK = 1;
+}
+
+/**
+ * \brief Send the USB reset
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_reset(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.BUSRESET = 1;
+}
+
+/**
+ * \brief Enable the USB SOF generation
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_enable_sof(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.SOFE = 1;
+}
+
+/**
+ * \brief Disable the USB SOF generation
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_disable_sof(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.SOFE = 0;
+}
+
+/**
+ * \brief Check the USB SOF generation status
+ *
+ * \param module_inst Pointer to USB software instance struct
+ *
+ * \return USB SOF generation status, \c true if SOF generation is ON.
+ */
+static inline bool usb_host_is_sof_enabled(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return module_inst->hw->HOST.CTRLB.bit.SOFE;
+}
+
+/**
+ * \brief Send the USB host resume
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_resume(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.RESUME= 1;
+}
+
+/**
+ * \brief Send the USB host LPM resume
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_l1_resume(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.L1RESUME = 1;
+}
+
+/**
+ * \brief Get the speed mode of USB host
+ *
+ * \param module_inst Pointer to USB module instance struct
+ *
+ * \return USB speed mode (\ref usb_speed).
+ */
+static inline enum usb_speed usb_host_get_speed(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	if (module_inst->hw->HOST.STATUS.bit.SPEED == 0) {
+		return USB_SPEED_FULL;
+	} else {
+		return USB_SPEED_LOW;
+	}
+}
+
+/**
+ * \brief Get the frame number
+ *
+ * \param module_inst Pointer to USB software instance struct
+ *
+ * \return frame number value.
+ */
+static inline uint16_t usb_host_get_frame_number(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return (uint16_t)(module_inst->hw->HOST.FNUM.bit.FNUM);
+}
+#endif
+
+/**
+ * \brief Attach USB device to the bus
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_attach(struct usb_module *module_inst)
+{
+	module_inst->hw->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+}
+
+/**
+ * \brief Detach USB device from the bus
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_detach(struct usb_module *module_inst)
+{
+	module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+}
+
+/**
+ * \brief Get the speed mode of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB Speed mode (\ref usb_speed).
+ */
+static inline enum usb_speed usb_device_get_speed(struct usb_module *module_inst)
+{
+	if (!(module_inst->hw->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk)) {
+		return USB_SPEED_FULL;
+	} else {
+		return USB_SPEED_LOW;
+	}
+}
+
+/**
+ * \brief Get the address of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device address value.
+ */
+static inline uint8_t usb_device_get_address(struct usb_module *module_inst)
+{
+	return ((uint8_t)(module_inst->hw->DEVICE.DADD.bit.DADD));
+}
+
+/**
+ * \brief Set the speed mode of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param address     USB device address value
+ */
+static inline void usb_device_set_address(struct usb_module *module_inst, uint8_t address)
+{
+	module_inst->hw->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | address;
+}
+
+/**
+ * \brief Get the frame number of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device frame number value.
+ */
+static inline uint16_t usb_device_get_frame_number(struct usb_module *module_inst)
+{
+	return ((uint16_t)(module_inst->hw->DEVICE.FNUM.bit.FNUM));
+}
+
+/**
+ * \brief Get the micro-frame number of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device micro-frame number value.
+ */
+static inline uint16_t usb_device_get_micro_frame_number(struct usb_module *module_inst)
+{
+	return ((uint16_t)(module_inst->hw->DEVICE.FNUM.reg));
+}
+
+/**
+ * \brief USB device send the resume wakeup
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_send_remote_wake_up(struct usb_module *module_inst)
+{
+	module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+}
+
+/**
+ * \brief USB device set the LPM mode
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param lpm_mode    LPM mode
+ */
+static inline void usb_device_set_lpm_mode(struct usb_module *module_inst,
+		enum usb_device_lpm_mode lpm_mode)
+{
+	module_inst->hw->DEVICE.CTRLB.bit.LPMHDSK = lpm_mode;
+}
+
+/**
+ * \name USB Host Callback Management
+ * @{
+ */
+enum status_code usb_host_register_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type,
+		usb_host_callback_t callback_func);
+enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type);
+enum status_code usb_host_enable_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type);
+enum status_code usb_host_disable_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Device Callback Management
+ * @{
+ */
+enum status_code usb_device_register_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type,
+		usb_device_callback_t callback_func);
+enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type);
+enum status_code usb_device_enable_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type);
+enum status_code usb_device_disable_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Host Pipe Configuration
+ * @{
+ */
+void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config);
+enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
+		struct usb_host_pipe_config *ep_config);
+enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
+		struct usb_host_pipe_config *ep_config);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Configuration
+ * @{
+ */
+void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config);
+enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
+		struct usb_device_endpoint_config *ep_config);
+bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep);
+/** @} */
+
+/**
+ * \name USB Host Pipe Callback Management
+ * @{
+ */
+enum status_code usb_host_pipe_register_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type,
+		usb_host_pipe_callback_t callback_func);
+enum status_code usb_host_pipe_unregister_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type);
+enum status_code usb_host_pipe_enable_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type);
+enum status_code usb_host_pipe_disable_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Callback Management
+ * @{
+ */
+enum status_code usb_device_endpoint_register_callback(
+		struct usb_module *module_inst, uint8_t ep_num,
+		enum usb_device_endpoint_callback callback_type,
+		usb_device_endpoint_callback_t callback_func);
+enum status_code usb_device_endpoint_unregister_callback(
+		struct usb_module *module_inst, uint8_t ep_num,
+		enum usb_device_endpoint_callback callback_type);
+enum status_code usb_device_endpoint_enable_callback(
+		struct usb_module *module_inst, uint8_t ep,
+		enum usb_device_endpoint_callback callback_type);
+enum status_code usb_device_endpoint_disable_callback(
+		struct usb_module *module_inst, uint8_t ep,
+		enum usb_device_endpoint_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Host Pipe Job Management
+ * @{
+ */
+enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf);
+enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
+enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
+enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num);
+enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
+		uint8_t pipe_num, bool b_remotewakeup, uint8_t hird);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Job Management
+ * @{
+ */
+enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+		uint8_t* pbuf, uint32_t buf_size);
+enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+		uint8_t* pbuf, uint32_t buf_size);
+enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
+		uint8_t* pbuf);
+void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep);
+/** @} */
+
+#if !SAMD11 && !SAML22
+/**
+ * \name USB Host Pipe Operations
+ * @{
+ */
+
+/**
+ * \brief Freeze a pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline void usb_host_pipe_freeze(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+}
+
+/**
+ * \brief Unfreeze a pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline void usb_host_pipe_unfreeze(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
+}
+
+/**
+ * \brief Check if the pipe is frozen
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline bool usb_host_pipe_is_frozen(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return (module_inst->hw->HOST.HostPipe[pipe_num].PSTATUS.bit.PFREEZE == 1);
+}
+
+/**
+ * \brief Set the data toggle bit of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline void usb_host_pipe_set_toggle(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_DTGL;
+}
+
+/**
+ * \brief Clear the data toggle bit of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline void usb_host_pipe_clear_toggle(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
+}
+
+/**
+ * \brief Set the auto zero length packet of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ * \param value       \c true to enable auto ZLP and \c false to disable
+ */
+void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value);
+
+/** @} */
+#endif
+
+/**
+ * \name USB Device Endpoint Operations
+ * @{
+ */
+
+bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep);
+void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep);
+void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_d_r/usb.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_d_r/usb.c
new file mode 100644
index 0000000000..a6fe3420d7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_d_r/usb.c
@@ -0,0 +1,2041 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Driver.
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <string.h>
+#include "usb.h"
+
+/** Fields definition from a LPM TOKEN  */
+#define  USB_LPM_ATTRIBUT_BLINKSTATE_MASK      (0xF << 0)
+#define  USB_LPM_ATTRIBUT_HIRD_MASK            (0xF << 4)
+#define  USB_LPM_ATTRIBUT_REMOTEWAKE_MASK      (1 << 8)
+#define  USB_LPM_ATTRIBUT_BLINKSTATE(value)    ((value & 0xF) << 0)
+#define  USB_LPM_ATTRIBUT_HIRD(value)          ((value & 0xF) << 4)
+#define  USB_LPM_ATTRIBUT_REMOTEWAKE(value)    ((value & 1) << 8)
+#define  USB_LPM_ATTRIBUT_BLINKSTATE_L1        USB_LPM_ATTRIBUT_BLINKSTATE(1)
+
+/**
+ * \brief Mask selecting the index part of an endpoint address
+ */
+#define  USB_EP_ADDR_MASK     0x0f
+
+/**
+ * \brief Endpoint transfer direction is IN
+ */
+#define  USB_EP_DIR_IN        0x80
+
+/**
+ * \brief Endpoint transfer direction is OUT
+ */
+#define  USB_EP_DIR_OUT       0x00
+
+/**
+ * \name USB SRAM data containing pipe descriptor table
+ * The content of the USB SRAM can be :
+ * - modified by USB hardware interface to update pipe status.
+ *   Thereby, it is read by software.
+ * - modified by USB software to control pipe.
+ *   Thereby, it is read by hardware.
+ * This data section is volatile.
+ *
+ * @{
+ */
+COMPILER_PACK_SET(1)
+COMPILER_WORD_ALIGNED
+union {
+	UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM];
+#if !SAMD11
+	UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM];
+#endif
+} usb_descriptor_table;
+COMPILER_PACK_RESET()
+/** @} */
+
+/**
+ * \brief Local USB module instance
+ */
+static struct usb_module *_usb_instances;
+
+#if !SAMD11
+/**
+ * \brief Host pipe callback structure variable
+ */
+static struct usb_pipe_callback_parameter pipe_callback_para;
+#endif
+
+/* Device LPM callback variable */
+static uint32_t device_callback_lpm_wakeup_enable;
+
+/**
+ * \brief Device endpoint callback parameter variable, used to transfer info to UDD wrapper layer
+ */
+static struct usb_endpoint_callback_parameter ep_callback_para;
+
+/**
+ * \internal USB Device IRQ Mask Bits Map
+ */
+static const uint16_t _usb_device_irq_bits[USB_DEVICE_CALLBACK_N] = {
+	USB_DEVICE_INTFLAG_SOF,
+	USB_DEVICE_INTFLAG_EORST,
+	USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM,
+	USB_DEVICE_INTFLAG_RAMACER,
+	USB_DEVICE_INTFLAG_SUSPEND,
+	USB_DEVICE_INTFLAG_LPMNYET,
+	USB_DEVICE_INTFLAG_LPMSUSP,
+};
+
+/**
+ * \internal USB Device IRQ Mask Bits Map
+ */
+static const uint8_t _usb_endpoint_irq_bits[USB_DEVICE_EP_CALLBACK_N] = {
+	USB_DEVICE_EPINTFLAG_TRCPT_Msk,
+	USB_DEVICE_EPINTFLAG_TRFAIL_Msk,
+	USB_DEVICE_EPINTFLAG_RXSTP,
+	USB_DEVICE_EPINTFLAG_STALL_Msk
+};
+
+#if !SAMD11
+/**
+ * \brief Bit mask for pipe job busy status
+ */
+uint32_t host_pipe_job_busy_status = 0;
+
+/**
+ * \brief Registers a USB host callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_host_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ * \param[in]     callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK    The callback was registered successfully.
+ */
+enum status_code usb_host_register_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type,
+		usb_host_callback_t callback_func)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module_inst->host_callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module_inst->host_registered_callback_mask |= (1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB host callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK    The callback was unregistered successfully.
+ */
+enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	/* Unregister callback function */
+	module_inst->host_callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module_inst->host_registered_callback_mask &= ~(1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB host callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB host generate callback events.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK    The callback was enabled successfully.
+ */
+enum status_code usb_host_enable_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Enable callback */
+	module_inst->host_enabled_callback_mask |= (1 << callback_type);
+
+	if (callback_type == USB_HOST_CALLBACK_SOF) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+	}
+	if (callback_type == USB_HOST_CALLBACK_RESET) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+	}
+	if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+	}
+	if (callback_type == USB_HOST_CALLBACK_DNRSM) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+	}
+	if (callback_type == USB_HOST_CALLBACK_UPRSM) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+	}
+	if (callback_type == USB_HOST_CALLBACK_RAMACER) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+	}
+	if (callback_type == USB_HOST_CALLBACK_CONNECT) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+	}
+	if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB host callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK    The callback was disabled successfully.
+ */
+enum status_code usb_host_disable_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Disable callback */
+	module_inst->host_enabled_callback_mask &= ~(1 << callback_type);
+
+	if (callback_type == USB_HOST_CALLBACK_SOF) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_HSOF;
+	}
+	if (callback_type == USB_HOST_CALLBACK_RESET) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RST;
+	}
+	if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_WAKEUP;
+	}
+	if (callback_type == USB_HOST_CALLBACK_DNRSM) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DNRSM;
+	}
+	if (callback_type == USB_HOST_CALLBACK_UPRSM) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_UPRSM;
+	}
+	if (callback_type == USB_HOST_CALLBACK_RAMACER) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RAMACER;
+	}
+	if (callback_type == USB_HOST_CALLBACK_CONNECT) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN;
+	}
+	if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes an USB host pipe configuration structure to defaults.
+ *
+ * Initializes a given USB host pipe configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li device address is 0
+ * \li endpoint address is 0
+ * \li pipe type is control
+ * \li interval is 0
+ * \li pipe size is 8
+ *
+ * \param[out] ep_config  Configuration structure to initialize to default values
+ */
+void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config)
+{
+	/* Sanity check arguments */
+	Assert(ep_config);
+	/* Write default config to config struct */
+	ep_config->device_address = 0;
+	ep_config->endpoint_address = 0;
+	ep_config->pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+	ep_config->binterval = 0;
+	ep_config->size = 8;
+}
+
+/**
+ * \brief Writes an USB host pipe configuration to the hardware module.
+ *
+ * Writes out a given configuration of an USB host pipe
+ * configuration to the hardware module. If the pipe is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] module_inst    Pointer to USB software instance struct
+ * \param[in] pipe_num       Pipe to configure
+ * \param[in] ep_config      Configuration settings for the pipe
+ *
+ * \return Status of the host pipe configuration operation.
+ * \retval STATUS_OK    The host pipe was configured successfully.
+ */
+enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
+		struct usb_host_pipe_config *ep_config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+	Assert(ep_config);
+
+	/* set pipe config */
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.BK = 0;
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = ep_config->pipe_type;
+	module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg =
+			ep_config->binterval;
+	if (ep_config->endpoint_address == 0) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+				USB_HOST_PIPE_TOKEN_SETUP;
+	} else if (ep_config->endpoint_address & USB_EP_DIR_IN) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+				USB_HOST_PIPE_TOKEN_IN;
+		module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg =
+				USB_HOST_PSTATUSSET_BK0RDY;
+	} else {
+		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+				USB_HOST_PIPE_TOKEN_OUT;
+		module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg =
+				USB_HOST_PSTATUSCLR_BK0RDY;
+	}
+
+	memset((uint8_t *)&usb_descriptor_table.usb_pipe_table[pipe_num], 0,
+			sizeof(usb_descriptor_table.usb_pipe_table[0]));
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR =
+			ep_config->device_address;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM =
+			ep_config->endpoint_address & USB_EP_ADDR_MASK;
+	if (ep_config->size == 1023) {
+		usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = 0x07;
+	} else {
+		usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE =
+				(32 - clz(((uint32_t)min(max(ep_config->size, 8), 1024) << 1) - 1) - 1 - 3);
+	}
+
+	/* Clear busy status */
+	host_pipe_job_busy_status &= ~(1 << pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Gets an USB host pipe configuration.
+ *
+ * Gets out the configuration of an USB host pipe from the hardware module.
+ *
+ * \param[in] module_inst    Pointer to USB software instance struct
+ * \param[in] pipe_num       Pipe to configure
+ * \param[out] ep_config     Configuration settings for the pipe
+ *
+ * \return Status of the get host pipe configuration operation.
+ * \retval STATUS_OK    The host pipe configuration was read successfully.
+ */
+enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
+		struct usb_host_pipe_config *ep_config)
+{
+	uint32_t size;
+
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+	Assert(ep_config);
+	/* get pipe config from setting register */
+	ep_config->device_address =
+			usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR;
+	ep_config->endpoint_address =
+			usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN ==
+				USB_HOST_PIPE_TOKEN_IN) {
+		ep_config->endpoint_address |= USB_EP_DIR_IN;
+	}
+
+	ep_config->pipe_type = (enum usb_host_pipe_type)module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE;
+	ep_config->binterval =
+			module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg;
+	size = usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE;
+	if (size == 0x07) {
+		ep_config->size = 1023;
+	} else {
+		ep_config->size = (8 << size);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a USB host pipe callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_host_pipe_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     callback_type Callback type given by an enum
+ * \param[in]     callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK    The callback was registered successfully.
+ */
+enum status_code usb_host_pipe_register_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type,
+		usb_host_pipe_callback_t callback_func)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(pipe_num < USB_PIPE_NUM);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module_inst->host_pipe_callback[pipe_num][callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module_inst->host_pipe_registered_callback_mask[pipe_num] |= (1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB host pipe callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK    The callback was unregistered successfully.
+ */
+enum status_code usb_host_pipe_unregister_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	/* Unregister callback function */
+	module_inst->host_pipe_callback[pipe_num][callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module_inst->host_pipe_registered_callback_mask[pipe_num] &= ~(1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB host pipe callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB host pipe generate callback events.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK    The callback was enabled successfully.
+ */
+enum status_code usb_host_pipe_enable_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	/* Enable callback */
+	module_inst->host_pipe_enabled_callback_mask[pipe_num] |= (1 << callback_type);
+
+	if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg =
+				USB_HOST_PINTENSET_TRFAIL | USB_HOST_PINTENSET_PERR;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB host callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK    The callback was disabled successfully.
+ */
+enum status_code usb_host_pipe_disable_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	/* Enable callback */
+	module_inst->host_pipe_enabled_callback_mask[pipe_num] &= ~(1 << callback_type);
+
+	if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TRCPT_Msk;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg =
+				USB_HOST_PINTENCLR_TRFAIL| USB_HOST_PINTENCLR_PERR;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TXSTP;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_STALL;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Sends the setup package.
+ *
+ * Sends the setup package.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     buf           Pointer to data buffer
+ *
+ * \return Status of the setup operation.
+ * \retval STATUS_OK    The setup job was set successfully.
+ * \retval STATUS_BUSY    The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (host_pipe_job_busy_status & (1 << pipe_num)) {
+		return STATUS_BUSY;
+	}
+
+	/* Set busy status */
+	host_pipe_job_busy_status |= 1 << pipe_num;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* get pipe config from setting register */
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+			8;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+			0;
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+			USB_HOST_PIPE_TOKEN_SETUP;
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+	usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief USB host pipe read job.
+ *
+ * USB host pipe read job by set and start an in transaction transfer.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     buf           Pointer to data buffer
+ * \param[in]     buf_size      Data buffer size
+ * \note The buffer length should not larger than 0x3FFF
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK    The read job was set successfully.
+ * \retval STATUS_BUSY    The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (host_pipe_job_busy_status & (1 << pipe_num)) {
+		return STATUS_BUSY;
+	}
+
+	/* Set busy status */
+	host_pipe_job_busy_status |= 1 << pipe_num;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* get pipe config from setting register */
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+			0;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+			buf_size;
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+			USB_HOST_PIPE_TOKEN_IN;
+
+	/* Start transfer */
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
+	usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief USB host pipe write job.
+ *
+ * USB host pipe write job by set and start an out transaction transfer.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     buf           Pointer to data buffer
+ * \param[in]     buf_size      Data buffer size
+ * \note The buffer length should not larger than 0x3FFF
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK    The write job was set successfully.
+ * \retval STATUS_BUSY    The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (host_pipe_job_busy_status & (1 << pipe_num)) {
+		return STATUS_BUSY;
+	}
+
+	/* Set busy status */
+	host_pipe_job_busy_status |= 1 << pipe_num;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* get pipe config from setting register */
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+			buf_size;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+			0;
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+			USB_HOST_PIPE_TOKEN_OUT;
+
+	/* Start transfer */
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+	usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief USB host abort a pipe job.
+ *
+ * USB host pipe abort job by freeze the pipe.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK    The abort job was set successfully.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+
+	/* Clear busy status */
+	host_pipe_job_busy_status &= ~(1 << pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Sends the LPM package.
+ *
+ * Sends the LPM package.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     b_remotewakeup  Remote wake up flag
+ * \param[in]     hird  Host Initiated Resume Duration
+ *
+ * \return Status of the setup operation.
+ * \retval STATUS_OK    The setup job was set successfully.
+ * \retval STATUS_BUSY    The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
+		uint8_t pipe_num, bool b_remotewakeup, uint8_t hird)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (host_pipe_job_busy_status & (1 << pipe_num)) {
+		return STATUS_BUSY;
+	}
+
+	/* Set busy status */
+	host_pipe_job_busy_status |= 1 << pipe_num;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE =
+				USB_HOST_PIPE_TYPE_EXTENDED;
+
+	/* get pipe config from setting register */
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.SUBPID = 0x3;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.VARIABLE =
+			USB_LPM_ATTRIBUT_REMOTEWAKE(b_remotewakeup) |
+			USB_LPM_ATTRIBUT_HIRD(hird) |
+			USB_LPM_ATTRIBUT_BLINKSTATE_L1;
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+	usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * \brief Function called by USB interrupt to manage USB host interrupts
+ *
+ * USB host interrupt events are split into four sections:
+ * - USB line events
+ *   (Device dis/connection, SOF, reset, resume, wakeup, error)
+ * - Pipe events
+ *   (End of data transfer, setup, stall, error)
+ */
+static void _usb_host_interrupt_handler(void)
+{
+	uint32_t pipe_int;
+	uint32_t flags;
+
+	/* Manage pipe interrupts */
+	pipe_int = ctz(_usb_instances->hw->HOST.PINTSMRY.reg);
+	if (pipe_int < 32) {
+		/* pipe interrupts */
+
+		/* get interrupt flags */
+		flags = _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg;
+
+		/* host pipe transfer complete interrupt */
+		if (flags & USB_HOST_PINTFLAG_TRCPT_Msk) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_TRCPT_Msk;
+			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+					(1 << USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)) {
+				pipe_callback_para.pipe_num = pipe_int;
+				if (_usb_instances->hw->HOST.HostPipe[pipe_int].PCFG.bit.PTOKEN ==
+							USB_HOST_PIPE_TOKEN_IN) {
+					/* in  */
+					pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+					pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+					usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+				} else {
+					/* out */
+					pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+					pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+					usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+					if (0 == pipe_callback_para.transfered_size) {
+						pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+					}
+				}
+				(_usb_instances->host_pipe_callback[pipe_int]
+						[USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE])(_usb_instances, &pipe_callback_para);
+			}
+		}
+
+		/* host pipe transfer fail interrupt */
+		if (flags & USB_HOST_PINTFLAG_TRFAIL) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_TRFAIL;
+		}
+
+		/* host pipe error interrupt */
+		if (flags & USB_HOST_PINTFLAG_PERR) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_PERR;
+			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+					(1 << USB_HOST_PIPE_CALLBACK_ERROR)) {
+				pipe_callback_para.pipe_num = pipe_int;
+				pipe_callback_para.pipe_error_status =
+						usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].STATUS_PIPE.reg & 0x1F;
+				(_usb_instances->host_pipe_callback[pipe_int]
+						[USB_HOST_PIPE_CALLBACK_ERROR])(_usb_instances, &pipe_callback_para);
+			}
+		}
+
+		/* host pipe transmitted setup interrupt */
+		if (flags & USB_HOST_PINTFLAG_TXSTP) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_TXSTP;
+			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+					(1 << USB_HOST_PIPE_CALLBACK_SETUP)) {
+				pipe_callback_para.pipe_num = pipe_int;
+				pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+				(_usb_instances->host_pipe_callback[pipe_int]
+						[USB_HOST_PIPE_CALLBACK_SETUP])(_usb_instances, NULL);
+			}
+		}
+
+		/* host pipe stall interrupt */
+		if (flags & USB_HOST_PINTFLAG_STALL) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_STALL;
+			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+					(1 << USB_HOST_PIPE_CALLBACK_STALL)) {
+				pipe_callback_para.pipe_num = pipe_int;
+				(_usb_instances->host_pipe_callback[pipe_int]
+						[USB_HOST_PIPE_CALLBACK_STALL])(_usb_instances, &pipe_callback_para);
+			}
+		}
+
+	} else {
+		/* host interrupts */
+
+		/* get interrupt flags */
+		flags = _usb_instances->hw->HOST.INTFLAG.reg;
+
+		/* host SOF interrupt */
+		if (flags & USB_HOST_INTFLAG_HSOF) {
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_SOF)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_SOF])(_usb_instances);
+			}
+		}
+
+		/* host reset interrupt */
+		if (flags & USB_HOST_INTFLAG_RST) {
+			/* Clear busy status */
+			host_pipe_job_busy_status = 0;
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RESET)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_RESET])(_usb_instances);
+			}
+		}
+
+		/* host upstream resume interrupts */
+		if (flags & USB_HOST_INTFLAG_UPRSM) {
+			/* clear the flags */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_UPRSM)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_UPRSM])(_usb_instances);
+			}
+		}
+
+		/* host downstream resume interrupts */
+		if (flags & USB_HOST_INTFLAG_DNRSM) {
+			/* clear the flags */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DNRSM)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_DNRSM])(_usb_instances);
+			}
+		}
+
+		/* host wakeup interrupts */
+		if (flags & USB_HOST_INTFLAG_WAKEUP) {
+			/* clear the flags */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_WAKEUP)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_WAKEUP])(_usb_instances);
+			}
+		}
+
+		/* host ram access interrupt  */
+		if (flags & USB_HOST_INTFLAG_RAMACER) {
+			/* Clear busy status */
+			host_pipe_job_busy_status = 0;
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RAMACER)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_RAMACER])(_usb_instances);
+			}
+		}
+
+		/* host connect interrupt */
+		if (flags & USB_HOST_INTFLAG_DCONN) {
+			/* Clear busy status */
+			host_pipe_job_busy_status = 0;
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_CONNECT)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_CONNECT])(_usb_instances);
+			}
+		}
+
+		/* host disconnect interrupt 	*/
+		if (flags & USB_HOST_INTFLAG_DDISC) {
+			/* Clear busy status */
+			host_pipe_job_busy_status = 0;
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DISCONNECT)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_DISCONNECT])(_usb_instances);
+			}
+		}
+
+	}
+}
+
+/**
+ * \brief Sets USB host pipe auto ZLP setting value
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     value         Auto ZLP setting value, \c true to enable
+ *
+ */
+void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value)
+{
+	Assert(module_inst);
+
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = value;
+}
+#endif
+
+/**
+ * \brief Registers a USB device callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_device_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ * \param[in]     callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK    The callback was registered successfully.
+ */
+enum status_code usb_device_register_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type,
+		usb_device_callback_t callback_func)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module_inst->device_callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB device callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK    The callback was unregistered successfully.
+ */
+enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	/* Unregister callback function */
+	module_inst->device_callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB device callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB device generate callback events.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK    The callback was enabled successfully.
+ */
+enum status_code usb_device_enable_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* clear related flag */
+	module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type];
+
+	/* Enable callback */
+	module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type];
+
+	module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB device callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK    The callback was disabled successfully.
+ */
+enum status_code usb_device_disable_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Disable callback */
+	module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type];
+
+	module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a USB device endpoint callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_device_endpoint_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     ep_num        Endpoint to configure
+ * \param[in]     callback_type Callback type given by an enum
+ * \param[in]     callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK    The callback was registered successfully.
+ */
+enum status_code usb_device_endpoint_register_callback(
+		struct usb_module *module_inst, uint8_t ep_num,
+		enum usb_device_endpoint_callback callback_type,
+		usb_device_endpoint_callback_t callback_func)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(ep_num < USB_EPT_NUM);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module_inst->device_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB device endpoint callback
+ *
+ * Unregisters an callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     ep_num        Endpoint to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK    The callback was unregistered successfully.
+ */
+enum status_code usb_device_endpoint_unregister_callback(
+		struct usb_module *module_inst, uint8_t ep_num,
+		enum usb_device_endpoint_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(ep_num < USB_EPT_NUM);
+
+	/* Unregister callback function */
+	module_inst->device_endpoint_callback[ep_num][callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module_inst->device_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB device endpoint callback generation for a given type.
+ *
+ * Enables callbacks for a given logical type.
+ * This must be called before USB device pipe generate callback events.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     ep            Endpoint to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK    The callback was enabled successfully.
+ */
+enum status_code usb_device_endpoint_enable_callback(
+		struct usb_module *module_inst, uint8_t ep,
+		enum usb_device_endpoint_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+	Assert(ep_num < USB_EPT_NUM);
+
+	/* Enable callback */
+	module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
+		if (ep_num == 0) { // control endpoint
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1;
+		} else if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+		}
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
+		if (ep_num == 0) { // control endpoint
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1;
+		} else if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+		}
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
+		if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB device endpoint callback generation for a given type.
+ *
+ * Disables callbacks for a given logical type.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     ep            Endpoint to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK    The callback was disabled successfully.
+ */
+enum status_code usb_device_endpoint_disable_callback(
+		struct usb_module *module_inst, uint8_t ep,
+		enum usb_device_endpoint_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+	Assert(ep_num < USB_EPT_NUM);
+
+	/* Enable callback */
+	module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
+		if (ep_num == 0) { // control endpoint
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1;
+		} else if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0;
+		}
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
+		if (ep_num == 0) { // control endpoint
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1;
+		} else if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0;
+		}
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP;
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
+		if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes an USB device endpoint configuration structure to defaults.
+ *
+ * Initializes a given USB device endpoint configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li endpoint address is 0
+ * \li endpoint size is 8 bytes
+ * \li auto_zlp is false
+ * \li endpoint type is control
+ *
+ * \param[out] ep_config  Configuration structure to initialize to default values
+ */
+void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config)
+{
+	/* Sanity check arguments */
+	Assert(ep_config);
+
+	/* Write default config to config struct */
+	ep_config->ep_address = 0;
+	ep_config->ep_size = USB_ENDPOINT_8_BYTE;
+	ep_config->auto_zlp = false;
+	ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL;
+}
+
+/**
+ * \brief Writes an USB device endpoint configuration to the hardware module.
+ *
+ * Writes out a given configuration of an USB device endpoint
+ * configuration to the hardware module. If the pipe is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] module_inst    Pointer to USB software instance struct
+ * \param[in] ep_config      Configuration settings for the endpoint
+ *
+ * \return Status of the device endpoint configuration operation
+ * \retval STATUS_OK         The device endpoint was configured successfully
+ * \retval STATUS_ERR_DENIED The endpoint address is already configured
+ */
+enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
+		struct usb_device_endpoint_config *ep_config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(ep_config);
+
+	uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK;
+	uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0;
+
+	switch (ep_config->ep_type) {
+		case USB_DEVICE_ENDPOINT_TYPE_DISABLE:
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) |  USB_DEVICE_EPCFG_EPTYPE1(0);
+			return STATUS_OK;
+
+		case USB_DEVICE_ENDPOINT_TYPE_CONTROL:
+			if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && \
+				(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+			} else {
+				return STATUS_ERR_DENIED;
+			}
+			if (true == ep_config->auto_zlp) {
+				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+			} else {
+				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+			}
+			usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size;
+			usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size;
+			return STATUS_OK;
+
+		case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS:
+			if (ep_bank) {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			} else {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			}
+			break;
+
+		case USB_DEVICE_ENDPOINT_TYPE_BULK:
+			if (ep_bank) {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			} else {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			}
+			break;
+
+		case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT:
+			if (ep_bank) {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			} else {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			}
+			break;
+
+		default:
+			break;
+	}
+
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size;
+
+	if (true == ep_config->auto_zlp) {
+		usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+		} else {
+		usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Check if current endpoint is configured
+ *
+ * \param module_inst   Pointer to USB software instance struct
+ * \param ep            Endpoint address (direction & number)
+ *
+ * \return \c true if endpoint is configured and ready to use
+ */
+bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+	uint8_t flag;
+
+	if (ep & USB_EP_DIR_IN) {
+		flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+	} else {
+		flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+	}
+	return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE);
+}
+
+
+/**
+ * \brief Abort ongoing job on the endpoint
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep          Endpoint address
+ */
+void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num;
+	ep_num = ep & USB_EP_ADDR_MASK;
+
+	// Stop transfer
+	if (ep & USB_EP_DIR_IN) {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+		// Eventually ack a transfer occur during abort
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+	} else {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+		// Eventually ack a transfer occur during abort
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+	}
+}
+
+/**
+ * \brief Check if endpoint is halted
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep          Endpoint address
+ *
+ * \return \c true if the endpoint is halted
+ */
+bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	if (ep & USB_EP_DIR_IN) {
+		return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1);
+	} else {
+		return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0);
+	}
+}
+
+/**
+ * \brief Halt the endpoint (send STALL)
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep          Endpoint address
+ */
+void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	// Stall endpoint
+	if (ep & USB_EP_DIR_IN) {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
+	} else {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
+	}
+}
+
+/**
+ * \brief Clear endpoint halt state
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep          Endpoint address
+ */
+void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	if (ep & USB_EP_DIR_IN) {
+		if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1) {
+			// Remove stall request
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1;
+			if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+				// The Stall has occurred, then reset data toggle
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN;
+			}
+		}
+	} else {
+		if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0) {
+			// Remove stall request
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0;
+			if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+				// The Stall has occurred, then reset data toggle
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT;
+			}
+		}
+	}
+}
+
+/**
+ * \brief Start write buffer job on a endpoint
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param ep_num      Endpoint number
+ * \param pbuf        Pointer to buffer
+ * \param buf_size    Size of buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+		uint8_t* pbuf, uint32_t buf_size)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(ep_num < USB_EPT_NUM);
+
+	uint8_t flag;
+	flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+	if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
+		return STATUS_ERR_DENIED;
+	};
+
+	/* get endpoint configuration from setting register */
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf;
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size;
+	module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Start read buffer job on a endpoint
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param ep_num      Endpoint number
+ * \param pbuf        Pointer to buffer
+ * \param buf_size    Size of buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+		uint8_t* pbuf, uint32_t buf_size)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(ep_num < USB_EPT_NUM);
+
+	uint8_t flag;
+	flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+	if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
+		return STATUS_ERR_DENIED;
+	};
+
+	/* get endpoint configuration from setting register */
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+	module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Start setup packet read job on a endpoint
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param pbuf        Pointer to buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
+		uint8_t* pbuf)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* get endpoint configuration from setting register */
+	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
+	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+	module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+	return STATUS_OK;
+}
+
+static void _usb_device_interrupt_handler(void)
+{
+	uint16_t ep_inst;
+	uint16_t flags, flags_run;
+	ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg;
+
+	/* device interrupt */
+	if (0 == ep_inst) {
+		int i;
+
+		/* get interrupt flags */
+		flags = _usb_instances->hw->DEVICE.INTFLAG.reg;
+		flags_run = flags &
+				_usb_instances->device_enabled_callback_mask &
+				_usb_instances->device_registered_callback_mask;
+
+		for (i = 0; i < USB_DEVICE_CALLBACK_N; i ++) {
+			if (flags & _usb_device_irq_bits[i]) {
+				_usb_instances->hw->DEVICE.INTFLAG.reg =
+						_usb_device_irq_bits[i];
+			}
+			if (flags_run & _usb_device_irq_bits[i]) {
+				if (i == USB_DEVICE_CALLBACK_LPMSUSP) {
+					device_callback_lpm_wakeup_enable =
+							usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE
+							& USB_LPM_ATTRIBUT_REMOTEWAKE_MASK;
+				}
+				(_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable);
+			}
+		}
+
+	} else {
+		/* endpoint interrupt */
+
+		for (uint8_t i = 0; i < USB_EPT_NUM; i++) {
+
+			if (ep_inst & (1 << i)) {
+				flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg;
+				flags_run = flags &
+						_usb_instances->device_endpoint_enabled_callback_mask[i] &
+						_usb_instances->device_endpoint_registered_callback_mask[i];
+
+				// endpoint transfer stall interrupt
+				if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk) {
+					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+					} else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+					}
+
+					if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk) {
+						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances,&ep_callback_para);
+					}
+					return;
+				}
+
+				// endpoint received setup interrupt
+				if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
+					_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+					if(_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP]) {
+						ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances,&ep_callback_para);
+					}
+					return;
+				}
+
+				// endpoint transfer complete interrupt
+				if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
+					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+						ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT);
+
+					} else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+						ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+						ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE);
+					}
+					if(flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
+						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances,&ep_callback_para);
+					}
+					return;
+				}
+
+				// endpoint transfer fail interrupt
+				if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
+					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+						if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
+							usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+						}
+						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+						if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
+							return;
+						}
+					} else if(_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+						if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
+							usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+						}
+						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+						if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
+							return;
+						}
+					}
+
+					if(flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
+						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances,&ep_callback_para);
+					}
+					return;
+				}
+			}
+		}
+	}
+}
+
+/**
+ * \brief Enable the USB module peripheral
+ *
+ * \param module_inst pointer to USB module instance
+ */
+void usb_enable(struct usb_module *module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
+	while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+}
+
+/**
+ * \brief Disable the USB module peripheral
+ *
+ * \param module_inst pointer to USB module instance
+ */
+void usb_disable(struct usb_module *module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
+	module_inst->hw->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
+	module_inst->hw->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+}
+
+/**
+ * \brief Interrupt handler for the USB module.
+ */
+void USB_Handler(void)
+{
+	if (_usb_instances->hw->DEVICE.CTRLA.bit.MODE) {
+#if !SAMD11
+		/*host mode ISR */
+		_usb_host_interrupt_handler();
+#endif
+	} else {
+		/*device mode ISR */
+		_usb_device_interrupt_handler();
+	}
+}
+
+/**
+ * \brief Get the default USB module settings
+ *
+ * \param[out] module_config  Configuration structure to initialize to default values
+ */
+void usb_get_config_defaults(struct usb_config *module_config)
+{
+	Assert(module_config);
+
+	/* Sanity check arguments */
+	Assert(module_config);
+	/* Write default configuration to config struct */
+	module_config->select_host_mode = 0;
+	module_config->run_in_standby = 1;
+	module_config->source_generator = GCLK_GENERATOR_0;
+	module_config->speed_mode = USB_SPEED_FULL;
+}
+
+#define NVM_USB_PAD_TRANSN_POS  45
+#define NVM_USB_PAD_TRANSN_SIZE 5
+#define NVM_USB_PAD_TRANSP_POS  50
+#define NVM_USB_PAD_TRANSP_SIZE 5
+#define NVM_USB_PAD_TRIM_POS  55
+#define NVM_USB_PAD_TRIM_SIZE 3
+
+/**
+ * \brief Initializes USB module instance
+ *
+ * Enables the clock and initializes the USB module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst   Pointer to the software module instance struct
+ * \param[in]     hw            Pointer to the USB hardware module
+ * \param[in]     module_config Pointer to the USB configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ */
+enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
+		struct usb_config *module_config)
+{
+	/* Sanity check arguments */
+	Assert(hw);
+	Assert(module_inst);
+	Assert(module_config);
+
+	uint32_t i,j;
+	uint32_t pad_transn, pad_transp, pad_trim;
+	struct system_pinmux_config pin_config;
+	struct system_gclk_chan_config gclk_chan_config;
+
+#if !SAMD11
+	host_pipe_job_busy_status = 0;
+#endif
+
+	_usb_instances = module_inst;
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_USB);
+
+	/* Set up the USB DP/DN pins */
+	system_pinmux_get_config_defaults(&pin_config);
+	pin_config.mux_position = MUX_PA24G_USB_DM;
+	system_pinmux_pin_set_config(PIN_PA24G_USB_DM, &pin_config);
+	pin_config.mux_position = MUX_PA25G_USB_DP;
+	system_pinmux_pin_set_config(PIN_PA25G_USB_DP, &pin_config);
+
+	/* Setup clock for module */
+	system_gclk_chan_get_config_defaults(&gclk_chan_config);
+	gclk_chan_config.source_generator = module_config->source_generator;
+	system_gclk_chan_set_config(USB_GCLK_ID, &gclk_chan_config);
+	system_gclk_chan_enable(USB_GCLK_ID);
+
+	/* Reset */
+	hw->DEVICE.CTRLA.bit.SWRST = 1;
+	while (hw->DEVICE.SYNCBUSY.bit.SWRST) {
+		/* Sync wait */
+	}
+
+	/* Change QOS values to have the best performance and correct USB behaviour */
+	USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+	USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+
+	/* Load Pad Calibration */
+	pad_transn =( *((uint32_t *)(NVMCTRL_OTP4)
+			+ (NVM_USB_PAD_TRANSN_POS / 32))
+		>> (NVM_USB_PAD_TRANSN_POS % 32))
+		& ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
+
+	if (pad_transn == 0x1F) {
+		pad_transn = 5;
+	}
+
+	hw->DEVICE.PADCAL.bit.TRANSN = pad_transn;
+
+	pad_transp =( *((uint32_t *)(NVMCTRL_OTP4)
+			+ (NVM_USB_PAD_TRANSP_POS / 32))
+			>> (NVM_USB_PAD_TRANSP_POS % 32))
+			& ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
+
+	if (pad_transp == 0x1F) {
+		pad_transp = 29;
+	}
+
+	hw->DEVICE.PADCAL.bit.TRANSP = pad_transp;
+
+	pad_trim =( *((uint32_t *)(NVMCTRL_OTP4)
+			+ (NVM_USB_PAD_TRIM_POS / 32))
+			>> (NVM_USB_PAD_TRIM_POS % 32))
+			& ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
+
+	if (pad_trim == 0x7) {
+		pad_trim = 3;
+	}
+
+	hw->DEVICE.PADCAL.bit.TRIM = pad_trim;
+
+	/* Set the configuration */
+	hw->DEVICE.CTRLA.bit.MODE = module_config->select_host_mode;
+	hw->DEVICE.CTRLA.bit.RUNSTDBY = module_config->run_in_standby;
+	hw->DEVICE.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]);
+	if (USB_SPEED_FULL == module_config->speed_mode) {
+		module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
+	} else if(USB_SPEED_LOW == module_config->speed_mode) {
+		module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val;
+	}
+
+	memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0,
+			sizeof(usb_descriptor_table.usb_endpoint_table));
+
+#if !SAMD11
+	/* callback related init */
+	for (i = 0; i < USB_HOST_CALLBACK_N; i++) {
+		module_inst->host_callback[i] = NULL;
+	};
+	for (i = 0; i < USB_PIPE_NUM; i++) {
+		for (j = 0; j < USB_HOST_PIPE_CALLBACK_N; j++) {
+			module_inst->host_pipe_callback[i][j] = NULL;
+		}
+	};
+	module_inst->host_registered_callback_mask = 0;
+	module_inst->host_enabled_callback_mask = 0;
+	for (i = 0; i < USB_PIPE_NUM; i++) {
+		module_inst->host_pipe_registered_callback_mask[i] = 0;
+		module_inst->host_pipe_enabled_callback_mask[i] = 0;
+	}
+#endif
+
+	/*  device callback related */
+	for (i = 0; i < USB_DEVICE_CALLBACK_N; i++) {
+		module_inst->device_callback[i] = NULL;
+	}
+	for (i = 0; i < USB_EPT_NUM; i++) {
+		for(j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++) {
+			module_inst->device_endpoint_callback[i][j] = NULL;
+		}
+	}
+	module_inst->device_registered_callback_mask = 0;
+	module_inst->device_enabled_callback_mask = 0;
+	for (j = 0; j < USB_EPT_NUM; j++) {
+		module_inst->device_endpoint_registered_callback_mask[j] = 0;
+		module_inst->device_endpoint_enabled_callback_mask[j] = 0;
+	}
+
+	/* Enable interrupts for this USB module */
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_USB);
+
+	return STATUS_OK;
+}
+
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_l/usb.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_l/usb.c
new file mode 100644
index 0000000000..ea612c47bc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_l/usb.c
@@ -0,0 +1,2037 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Driver.
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <string.h>
+#include "usb.h"
+
+/** Fields definition from a LPM TOKEN  */
+#define  USB_LPM_ATTRIBUT_BLINKSTATE_MASK      (0xF << 0)
+#define  USB_LPM_ATTRIBUT_HIRD_MASK            (0xF << 4)
+#define  USB_LPM_ATTRIBUT_REMOTEWAKE_MASK      (1 << 8)
+#define  USB_LPM_ATTRIBUT_BLINKSTATE(value)    ((value & 0xF) << 0)
+#define  USB_LPM_ATTRIBUT_HIRD(value)          ((value & 0xF) << 4)
+#define  USB_LPM_ATTRIBUT_REMOTEWAKE(value)    ((value & 1) << 8)
+#define  USB_LPM_ATTRIBUT_BLINKSTATE_L1        USB_LPM_ATTRIBUT_BLINKSTATE(1)
+
+/**
+ * \brief Mask selecting the index part of an endpoint address
+ */
+#define  USB_EP_ADDR_MASK     0x0f
+
+/**
+ * \brief Endpoint transfer direction is IN
+ */
+#define  USB_EP_DIR_IN        0x80
+
+/**
+ * \brief Endpoint transfer direction is OUT
+ */
+#define  USB_EP_DIR_OUT       0x00
+
+/**
+ * \name USB SRAM data containing pipe descriptor table
+ * The content of the USB SRAM can be :
+ * - modified by USB hardware interface to update pipe status.
+ *   Thereby, it is read by software.
+ * - modified by USB software to control pipe.
+ *   Thereby, it is read by hardware.
+ * This data section is volatile.
+ *
+ * @{
+ */
+COMPILER_PACK_SET(1)
+COMPILER_WORD_ALIGNED
+union {
+	UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM];
+#if !SAML22
+	UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM];
+#endif
+} usb_descriptor_table;
+COMPILER_PACK_RESET()
+/** @} */
+
+/**
+ * \brief Local USB module instance
+ */
+static struct usb_module *_usb_instances;
+
+#if !SAML22
+/**
+ * \brief Host pipe callback structure variable
+ */
+static struct usb_pipe_callback_parameter pipe_callback_para;
+#endif
+
+/* Device LPM callback variable */
+static uint32_t device_callback_lpm_wakeup_enable;
+
+/**
+ * \brief Device endpoint callback parameter variable, used to transfer info to UDD wrapper layer
+ */
+static struct usb_endpoint_callback_parameter ep_callback_para;
+
+/**
+ * \internal USB Device IRQ Mask Bits Map
+ */
+static const uint16_t _usb_device_irq_bits[USB_DEVICE_CALLBACK_N] = {
+	USB_DEVICE_INTFLAG_SOF,
+	USB_DEVICE_INTFLAG_EORST,
+	USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM,
+	USB_DEVICE_INTFLAG_RAMACER,
+	USB_DEVICE_INTFLAG_SUSPEND,
+	USB_DEVICE_INTFLAG_LPMNYET,
+	USB_DEVICE_INTFLAG_LPMSUSP,
+};
+
+/**
+ * \internal USB Device IRQ Mask Bits Map
+ */
+static const uint8_t _usb_endpoint_irq_bits[USB_DEVICE_EP_CALLBACK_N] = {
+	USB_DEVICE_EPINTFLAG_TRCPT_Msk,
+	USB_DEVICE_EPINTFLAG_TRFAIL_Msk,
+	USB_DEVICE_EPINTFLAG_RXSTP,
+	USB_DEVICE_EPINTFLAG_STALL_Msk
+};
+
+#if !SAML22
+/**
+ * \brief Bit mask for pipe job busy status
+ */
+uint32_t host_pipe_job_busy_status = 0;
+
+/**
+ * \brief Registers a USB host callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_host_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ * \param[in]     callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK    The callback was registered successfully.
+ */
+enum status_code usb_host_register_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type,
+		usb_host_callback_t callback_func)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module_inst->host_callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module_inst->host_registered_callback_mask |= (1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB host callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK    The callback was unregistered successfully.
+ */
+enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	/* Unregister callback function */
+	module_inst->host_callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module_inst->host_registered_callback_mask &= ~(1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB host callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB host generate callback events.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK    The callback was enabled successfully.
+ */
+enum status_code usb_host_enable_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Enable callback */
+	module_inst->host_enabled_callback_mask |= (1 << callback_type);
+
+	if (callback_type == USB_HOST_CALLBACK_SOF) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+	}
+	if (callback_type == USB_HOST_CALLBACK_RESET) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+	}
+	if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+	}
+	if (callback_type == USB_HOST_CALLBACK_DNRSM) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+	}
+	if (callback_type == USB_HOST_CALLBACK_UPRSM) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+	}
+	if (callback_type == USB_HOST_CALLBACK_RAMACER) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+	}
+	if (callback_type == USB_HOST_CALLBACK_CONNECT) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+	}
+	if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
+		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB host callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK    The callback was disabled successfully.
+ */
+enum status_code usb_host_disable_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Disable callback */
+	module_inst->host_enabled_callback_mask &= ~(1 << callback_type);
+
+	if (callback_type == USB_HOST_CALLBACK_SOF) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_HSOF;
+	}
+	if (callback_type == USB_HOST_CALLBACK_RESET) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RST;
+	}
+	if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_WAKEUP;
+	}
+	if (callback_type == USB_HOST_CALLBACK_DNRSM) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DNRSM;
+	}
+	if (callback_type == USB_HOST_CALLBACK_UPRSM) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_UPRSM;
+	}
+	if (callback_type == USB_HOST_CALLBACK_RAMACER) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RAMACER;
+	}
+	if (callback_type == USB_HOST_CALLBACK_CONNECT) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN;
+	}
+	if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
+		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes an USB host pipe configuration structure to defaults.
+ *
+ * Initializes a given USB host pipe configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li device address is 0
+ * \li endpoint address is 0
+ * \li pipe type is control
+ * \li interval is 0
+ * \li pipe size is 8
+ *
+ * \param[out] ep_config  Configuration structure to initialize to default values
+ */
+void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config)
+{
+	/* Sanity check arguments */
+	Assert(ep_config);
+	/* Write default config to config struct */
+	ep_config->device_address = 0;
+	ep_config->endpoint_address = 0;
+	ep_config->pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+	ep_config->binterval = 0;
+	ep_config->size = 8;
+}
+
+/**
+ * \brief Writes an USB host pipe configuration to the hardware module.
+ *
+ * Writes out a given configuration of an USB host pipe
+ * configuration to the hardware module. If the pipe is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] module_inst    Pointer to USB software instance struct
+ * \param[in] pipe_num       Pipe to configure
+ * \param[in] ep_config      Configuration settings for the pipe
+ *
+ * \return Status of the host pipe configuration operation.
+ * \retval STATUS_OK    The host pipe was configured successfully.
+ */
+enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
+		struct usb_host_pipe_config *ep_config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+	Assert(ep_config);
+
+	/* set pipe config */
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.BK = 0;
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = ep_config->pipe_type;
+	module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg =
+			ep_config->binterval;
+	if (ep_config->endpoint_address == 0) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+				USB_HOST_PIPE_TOKEN_SETUP;
+	} else if (ep_config->endpoint_address & USB_EP_DIR_IN) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+				USB_HOST_PIPE_TOKEN_IN;
+		module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg =
+				USB_HOST_PSTATUSSET_BK0RDY;
+	} else {
+		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+				USB_HOST_PIPE_TOKEN_OUT;
+		module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg =
+				USB_HOST_PSTATUSCLR_BK0RDY;
+	}
+
+	memset((uint8_t *)&usb_descriptor_table.usb_pipe_table[pipe_num], 0,
+			sizeof(usb_descriptor_table.usb_pipe_table[0]));
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR =
+			ep_config->device_address;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM =
+			ep_config->endpoint_address & USB_EP_ADDR_MASK;
+	if (ep_config->size == 1023) {
+		usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = 0x07;
+	} else {
+		usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE =
+				(32 - clz(((uint32_t)min(max(ep_config->size, 8), 1024) << 1) - 1) - 1 - 3);
+	}
+
+	/* Clear busy status */
+	host_pipe_job_busy_status &= ~(1 << pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Gets an USB host pipe configuration.
+ *
+ * Gets out the configuration of an USB host pipe from the hardware module.
+ *
+ * \param[in] module_inst    Pointer to USB software instance struct
+ * \param[in] pipe_num       Pipe to configure
+ * \param[out] ep_config     Configuration settings for the pipe
+ *
+ * \return Status of the get host pipe configuration operation.
+ * \retval STATUS_OK    The host pipe configuration was read successfully.
+ */
+enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
+		struct usb_host_pipe_config *ep_config)
+{
+	uint32_t size;
+
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+	Assert(ep_config);
+	/* get pipe config from setting register */
+	ep_config->device_address =
+			usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR;
+	ep_config->endpoint_address =
+			usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN ==
+				USB_HOST_PIPE_TOKEN_IN) {
+		ep_config->endpoint_address |= USB_EP_DIR_IN;
+	}
+
+	ep_config->pipe_type = (enum usb_host_pipe_type)module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE;
+	ep_config->binterval =
+			module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg;
+	size = usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE;
+	if (size == 0x07) {
+		ep_config->size = 1023;
+	} else {
+		ep_config->size = (8 << size);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a USB host pipe callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_host_pipe_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     callback_type Callback type given by an enum
+ * \param[in]     callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK    The callback was registered successfully.
+ */
+enum status_code usb_host_pipe_register_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type,
+		usb_host_pipe_callback_t callback_func)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(pipe_num < USB_PIPE_NUM);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module_inst->host_pipe_callback[pipe_num][callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module_inst->host_pipe_registered_callback_mask[pipe_num] |= (1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB host pipe callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK    The callback was unregistered successfully.
+ */
+enum status_code usb_host_pipe_unregister_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	/* Unregister callback function */
+	module_inst->host_pipe_callback[pipe_num][callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module_inst->host_pipe_registered_callback_mask[pipe_num] &= ~(1 << callback_type);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB host pipe callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB host pipe generate callback events.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK    The callback was enabled successfully.
+ */
+enum status_code usb_host_pipe_enable_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	/* Enable callback */
+	module_inst->host_pipe_enabled_callback_mask[pipe_num] |= (1 << callback_type);
+
+	if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg =
+				USB_HOST_PINTENSET_TRFAIL | USB_HOST_PINTENSET_PERR;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB host callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK    The callback was disabled successfully.
+ */
+enum status_code usb_host_pipe_disable_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	/* Enable callback */
+	module_inst->host_pipe_enabled_callback_mask[pipe_num] &= ~(1 << callback_type);
+
+	if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TRCPT_Msk;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg =
+				USB_HOST_PINTENCLR_TRFAIL| USB_HOST_PINTENCLR_PERR;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TXSTP;
+	}
+	if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
+		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_STALL;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Sends the setup package.
+ *
+ * Sends the setup package.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     buf           Pointer to data buffer
+ *
+ * \return Status of the setup operation.
+ * \retval STATUS_OK    The setup job was set successfully.
+ * \retval STATUS_BUSY    The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (host_pipe_job_busy_status & (1 << pipe_num)) {
+		return STATUS_BUSY;
+	}
+
+	/* Set busy status */
+	host_pipe_job_busy_status |= 1 << pipe_num;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* get pipe config from setting register */
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+			8;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+			0;
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+			USB_HOST_PIPE_TOKEN_SETUP;
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+	usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief USB host pipe read job.
+ *
+ * USB host pipe read job by set and start an in transaction transfer.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     buf           Pointer to data buffer
+ * \param[in]     buf_size      Data buffer size
+ * \note The buffer length should not larger than 0x3FFF
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK    The read job was set successfully.
+ * \retval STATUS_BUSY    The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (host_pipe_job_busy_status & (1 << pipe_num)) {
+		return STATUS_BUSY;
+	}
+
+	/* Set busy status */
+	host_pipe_job_busy_status |= 1 << pipe_num;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* get pipe config from setting register */
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+			0;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+			buf_size;
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+			USB_HOST_PIPE_TOKEN_IN;
+
+	/* Start transfer */
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
+	usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief USB host pipe write job.
+ *
+ * USB host pipe write job by set and start an out transaction transfer.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     buf           Pointer to data buffer
+ * \param[in]     buf_size      Data buffer size
+ * \note The buffer length should not larger than 0x3FFF
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK    The write job was set successfully.
+ * \retval STATUS_BUSY    The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (host_pipe_job_busy_status & (1 << pipe_num)) {
+		return STATUS_BUSY;
+	}
+
+	/* Set busy status */
+	host_pipe_job_busy_status |= 1 << pipe_num;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* get pipe config from setting register */
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+			buf_size;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+			0;
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+			USB_HOST_PIPE_TOKEN_OUT;
+
+	/* Start transfer */
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+	usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief USB host abort a pipe job.
+ *
+ * USB host pipe abort job by freeze the pipe.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK    The abort job was set successfully.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+
+	/* Clear busy status */
+	host_pipe_job_busy_status &= ~(1 << pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Sends the LPM package.
+ *
+ * Sends the LPM package.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     b_remotewakeup  Remote wake up flag
+ * \param[in]     hird  Host Initiated Resume Duration
+ *
+ * \return Status of the setup operation.
+ * \retval STATUS_OK    The setup job was set successfully.
+ * \retval STATUS_BUSY    The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
+		uint8_t pipe_num, bool b_remotewakeup, uint8_t hird)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(pipe_num < USB_PIPE_NUM);
+
+	if (host_pipe_job_busy_status & (1 << pipe_num)) {
+		return STATUS_BUSY;
+	}
+
+	/* Set busy status */
+	host_pipe_job_busy_status |= 1 << pipe_num;
+
+	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+			USB_HOST_PIPE_TYPE_DISABLE) {
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE =
+				USB_HOST_PIPE_TYPE_EXTENDED;
+
+	/* get pipe config from setting register */
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.SUBPID = 0x3;
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.VARIABLE =
+			USB_LPM_ATTRIBUT_REMOTEWAKE(b_remotewakeup) |
+			USB_LPM_ATTRIBUT_HIRD(hird) |
+			USB_LPM_ATTRIBUT_BLINKSTATE_L1;
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+	usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * \brief Function called by USB interrupt to manage USB host interrupts
+ *
+ * USB host interrupt events are split into four sections:
+ * - USB line events
+ *   (Device dis/connection, SOF, reset, resume, wakeup, error)
+ * - Pipe events
+ *   (End of data transfer, setup, stall, error)
+ */
+static void _usb_host_interrupt_handler(void)
+{
+	uint32_t pipe_int;
+	uint32_t flags;
+
+	/* Manage pipe interrupts */
+	pipe_int = ctz(_usb_instances->hw->HOST.PINTSMRY.reg);
+	if (pipe_int < 32) {
+		/* pipe interrupts */
+
+		/* get interrupt flags */
+		flags = _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg;
+
+		/* host pipe transfer complete interrupt */
+		if (flags & USB_HOST_PINTFLAG_TRCPT_Msk) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_TRCPT_Msk;
+			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+					(1 << USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)) {
+				pipe_callback_para.pipe_num = pipe_int;
+				if (_usb_instances->hw->HOST.HostPipe[pipe_int].PCFG.bit.PTOKEN ==
+							USB_HOST_PIPE_TOKEN_IN) {
+					/* in  */
+					pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+					pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+					usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+				} else {
+					/* out */
+					pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+					pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+					usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+					if (0 == pipe_callback_para.transfered_size) {
+						pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+					}
+				}
+				(_usb_instances->host_pipe_callback[pipe_int]
+						[USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE])(_usb_instances, &pipe_callback_para);
+			}
+		}
+
+		/* host pipe transfer fail interrupt */
+		if (flags & USB_HOST_PINTFLAG_TRFAIL) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_TRFAIL;
+		}
+
+		/* host pipe error interrupt */
+		if (flags & USB_HOST_PINTFLAG_PERR) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_PERR;
+			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+					(1 << USB_HOST_PIPE_CALLBACK_ERROR)) {
+				pipe_callback_para.pipe_num = pipe_int;
+				pipe_callback_para.pipe_error_status =
+						usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].STATUS_PIPE.reg & 0x1F;
+				(_usb_instances->host_pipe_callback[pipe_int]
+						[USB_HOST_PIPE_CALLBACK_ERROR])(_usb_instances, &pipe_callback_para);
+			}
+		}
+
+		/* host pipe transmitted setup interrupt */
+		if (flags & USB_HOST_PINTFLAG_TXSTP) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_TXSTP;
+			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+					(1 << USB_HOST_PIPE_CALLBACK_SETUP)) {
+				pipe_callback_para.pipe_num = pipe_int;
+				pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+				(_usb_instances->host_pipe_callback[pipe_int]
+						[USB_HOST_PIPE_CALLBACK_SETUP])(_usb_instances, NULL);
+			}
+		}
+
+		/* host pipe stall interrupt */
+		if (flags & USB_HOST_PINTFLAG_STALL) {
+			/* Clear busy status */
+			host_pipe_job_busy_status &= ~(1 << pipe_int);
+			/* clear the flag */
+			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+					USB_HOST_PINTFLAG_STALL;
+			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+					(1 << USB_HOST_PIPE_CALLBACK_STALL)) {
+				pipe_callback_para.pipe_num = pipe_int;
+				(_usb_instances->host_pipe_callback[pipe_int]
+						[USB_HOST_PIPE_CALLBACK_STALL])(_usb_instances, &pipe_callback_para);
+			}
+		}
+
+	} else {
+		/* host interrupts */
+
+		/* get interrupt flags */
+		flags = _usb_instances->hw->HOST.INTFLAG.reg;
+
+		/* host SOF interrupt */
+		if (flags & USB_HOST_INTFLAG_HSOF) {
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_SOF)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_SOF])(_usb_instances);
+			}
+		}
+
+		/* host reset interrupt */
+		if (flags & USB_HOST_INTFLAG_RST) {
+			/* Clear busy status */
+			host_pipe_job_busy_status = 0;
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RESET)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_RESET])(_usb_instances);
+			}
+		}
+
+		/* host upstream resume interrupts */
+		if (flags & USB_HOST_INTFLAG_UPRSM) {
+			/* clear the flags */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_UPRSM)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_UPRSM])(_usb_instances);
+			}
+		}
+
+		/* host downstream resume interrupts */
+		if (flags & USB_HOST_INTFLAG_DNRSM) {
+			/* clear the flags */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DNRSM)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_DNRSM])(_usb_instances);
+			}
+		}
+
+		/* host wakeup interrupts */
+		if (flags & USB_HOST_INTFLAG_WAKEUP) {
+			/* clear the flags */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_WAKEUP)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_WAKEUP])(_usb_instances);
+			}
+		}
+
+		/* host ram access interrupt  */
+		if (flags & USB_HOST_INTFLAG_RAMACER) {
+			/* Clear busy status */
+			host_pipe_job_busy_status = 0;
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RAMACER)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_RAMACER])(_usb_instances);
+			}
+		}
+
+		/* host connect interrupt */
+		if (flags & USB_HOST_INTFLAG_DCONN) {
+			/* Clear busy status */
+			host_pipe_job_busy_status = 0;
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_CONNECT)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_CONNECT])(_usb_instances);
+			}
+		}
+
+		/* host disconnect interrupt 	*/
+		if (flags & USB_HOST_INTFLAG_DDISC) {
+			/* Clear busy status */
+			host_pipe_job_busy_status = 0;
+			/* clear the flag */
+			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DISCONNECT)) {
+				(_usb_instances->host_callback[USB_HOST_CALLBACK_DISCONNECT])(_usb_instances);
+			}
+		}
+
+	}
+}
+
+/**
+ * \brief Sets USB host pipe auto ZLP setting value
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     pipe_num      Pipe to configure
+ * \param[in]     value         Auto ZLP setting value, \c true to enable
+ *
+ */
+void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value)
+{
+	Assert(module_inst);
+
+	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = value;
+}
+#endif
+
+/**
+ * \brief Registers a USB device callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_device_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ * \param[in]     callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK    The callback was registered successfully.
+ */
+enum status_code usb_device_register_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type,
+		usb_device_callback_t callback_func)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module_inst->device_callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB device callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK    The callback was unregistered successfully.
+ */
+enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	/* Unregister callback function */
+	module_inst->device_callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB device callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB device generate callback events.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK    The callback was enabled successfully.
+ */
+enum status_code usb_device_enable_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* clear related flag */
+	module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type];
+
+	/* Enable callback */
+	module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type];
+
+	module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB device callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK    The callback was disabled successfully.
+ */
+enum status_code usb_device_disable_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Disable callback */
+	module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type];
+
+	module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a USB device endpoint callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_device_endpoint_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     ep_num        Endpoint to configure
+ * \param[in]     callback_type Callback type given by an enum
+ * \param[in]     callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK    The callback was registered successfully.
+ */
+enum status_code usb_device_endpoint_register_callback(
+		struct usb_module *module_inst, uint8_t ep_num,
+		enum usb_device_endpoint_callback callback_type,
+		usb_device_endpoint_callback_t callback_func)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(ep_num < USB_EPT_NUM);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module_inst->device_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB device endpoint callback
+ *
+ * Unregisters an callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     ep_num        Endpoint to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK    The callback was unregistered successfully.
+ */
+enum status_code usb_device_endpoint_unregister_callback(
+		struct usb_module *module_inst, uint8_t ep_num,
+		enum usb_device_endpoint_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(ep_num < USB_EPT_NUM);
+
+	/* Unregister callback function */
+	module_inst->device_endpoint_callback[ep_num][callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module_inst->device_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB device endpoint callback generation for a given type.
+ *
+ * Enables callbacks for a given logical type.
+ * This must be called before USB device pipe generate callback events.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     ep            Endpoint to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK    The callback was enabled successfully.
+ */
+enum status_code usb_device_endpoint_enable_callback(
+		struct usb_module *module_inst, uint8_t ep,
+		enum usb_device_endpoint_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+	Assert(ep_num < USB_EPT_NUM);
+
+	/* Enable callback */
+	module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
+		if (ep_num == 0) { // control endpoint
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1;
+		} else if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+		}
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
+		if (ep_num == 0) { // control endpoint
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1;
+		} else if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+		}
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
+		if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB device endpoint callback generation for a given type.
+ *
+ * Disables callbacks for a given logical type.
+ *
+ * \param[in]     module_inst   Pointer to USB software instance struct
+ * \param[in]     ep            Endpoint to configure
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK    The callback was disabled successfully.
+ */
+enum status_code usb_device_endpoint_disable_callback(
+		struct usb_module *module_inst, uint8_t ep,
+		enum usb_device_endpoint_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+	Assert(ep_num < USB_EPT_NUM);
+
+	/* Enable callback */
+	module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
+		if (ep_num == 0) { // control endpoint
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1;
+		} else if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0;
+		}
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
+		if (ep_num == 0) { // control endpoint
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1;
+		} else if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0;
+		}
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP;
+	}
+
+	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
+		if (ep & USB_EP_DIR_IN) {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1;
+		} else {
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes an USB device endpoint configuration structure to defaults.
+ *
+ * Initializes a given USB device endpoint configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li endpoint address is 0
+ * \li endpoint size is 8 bytes
+ * \li auto_zlp is false
+ * \li endpoint type is control
+ *
+ * \param[out] ep_config  Configuration structure to initialize to default values
+ */
+void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config)
+{
+	/* Sanity check arguments */
+	Assert(ep_config);
+
+	/* Write default config to config struct */
+	ep_config->ep_address = 0;
+	ep_config->ep_size = USB_ENDPOINT_8_BYTE;
+	ep_config->auto_zlp = false;
+	ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL;
+}
+
+/**
+ * \brief Writes an USB device endpoint configuration to the hardware module.
+ *
+ * Writes out a given configuration of an USB device endpoint
+ * configuration to the hardware module. If the pipe is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] module_inst    Pointer to USB software instance struct
+ * \param[in] ep_config      Configuration settings for the endpoint
+ *
+ * \return Status of the device endpoint configuration operation
+ * \retval STATUS_OK         The device endpoint was configured successfully
+ * \retval STATUS_ERR_DENIED The endpoint address is already configured
+ */
+enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
+		struct usb_device_endpoint_config *ep_config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(ep_config);
+
+	uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK;
+	uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0;
+
+	switch (ep_config->ep_type) {
+		case USB_DEVICE_ENDPOINT_TYPE_DISABLE:
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) |  USB_DEVICE_EPCFG_EPTYPE1(0);
+			return STATUS_OK;
+
+		case USB_DEVICE_ENDPOINT_TYPE_CONTROL:
+			if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && \
+				(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+			} else {
+				return STATUS_ERR_DENIED;
+			}
+			if (true == ep_config->auto_zlp) {
+				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+			} else {
+				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+			}
+			usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size;
+			usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size;
+			return STATUS_OK;
+
+		case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS:
+			if (ep_bank) {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			} else {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			}
+			break;
+
+		case USB_DEVICE_ENDPOINT_TYPE_BULK:
+			if (ep_bank) {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			} else {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			}
+			break;
+
+		case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT:
+			if (ep_bank) {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			} else {
+				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4);
+					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+				} else {
+					return STATUS_ERR_DENIED;
+				}
+			}
+			break;
+
+		default:
+			break;
+	}
+
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size;
+
+	if (true == ep_config->auto_zlp) {
+		usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+		} else {
+		usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Check if current endpoint is configured
+ *
+ * \param module_inst   Pointer to USB software instance struct
+ * \param ep            Endpoint address (direction & number)
+ *
+ * \return \c true if endpoint is configured and ready to use
+ */
+bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+	uint8_t flag;
+
+	if (ep & USB_EP_DIR_IN) {
+		flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+	} else {
+		flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+	}
+	return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE);
+}
+
+
+/**
+ * \brief Abort ongoing job on the endpoint
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep          Endpoint address
+ */
+void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num;
+	ep_num = ep & USB_EP_ADDR_MASK;
+
+	// Stop transfer
+	if (ep & USB_EP_DIR_IN) {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+		// Eventually ack a transfer occur during abort
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+	} else {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+		// Eventually ack a transfer occur during abort
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+	}
+}
+
+/**
+ * \brief Check if endpoint is halted
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep          Endpoint address
+ *
+ * \return \c true if the endpoint is halted
+ */
+bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	if (ep & USB_EP_DIR_IN) {
+		return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1);
+	} else {
+		return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0);
+	}
+}
+
+/**
+ * \brief Halt the endpoint (send STALL)
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep          Endpoint address
+ */
+void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	// Stall endpoint
+	if (ep & USB_EP_DIR_IN) {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
+	} else {
+		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
+	}
+}
+
+/**
+ * \brief Clear endpoint halt state
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep          Endpoint address
+ */
+void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep)
+{
+	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+	if (ep & USB_EP_DIR_IN) {
+		if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1) {
+			// Remove stall request
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1;
+			if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+				// The Stall has occurred, then reset data toggle
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN;
+			}
+		}
+	} else {
+		if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0) {
+			// Remove stall request
+			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0;
+			if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+				// The Stall has occurred, then reset data toggle
+				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT;
+			}
+		}
+	}
+}
+
+/**
+ * \brief Start write buffer job on a endpoint
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param ep_num      Endpoint number
+ * \param pbuf        Pointer to buffer
+ * \param buf_size    Size of buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+		uint8_t* pbuf, uint32_t buf_size)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(ep_num < USB_EPT_NUM);
+
+	uint8_t flag;
+	flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+	if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
+		return STATUS_ERR_DENIED;
+	};
+
+	/* get endpoint configuration from setting register */
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf;
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size;
+	module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Start read buffer job on a endpoint
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param ep_num      Endpoint number
+ * \param pbuf        Pointer to buffer
+ * \param buf_size    Size of buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+		uint8_t* pbuf, uint32_t buf_size)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(ep_num < USB_EPT_NUM);
+
+	uint8_t flag;
+	flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+	if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
+		return STATUS_ERR_DENIED;
+	};
+
+	/* get endpoint configuration from setting register */
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
+	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+	module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Start setup packet read job on a endpoint
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param pbuf        Pointer to buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
+		uint8_t* pbuf)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* get endpoint configuration from setting register */
+	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
+	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+	module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+	return STATUS_OK;
+}
+
+static void _usb_device_interrupt_handler(void)
+{
+	uint16_t ep_inst;
+	uint16_t flags, flags_run;
+	ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg;
+
+	/* device interrupt */
+	if (0 == ep_inst) {
+		int i;
+
+		/* get interrupt flags */
+		flags = _usb_instances->hw->DEVICE.INTFLAG.reg;
+		flags_run = flags &
+				_usb_instances->device_enabled_callback_mask &
+				_usb_instances->device_registered_callback_mask;
+
+		for (i = 0; i < USB_DEVICE_CALLBACK_N; i ++) {
+			if (flags & _usb_device_irq_bits[i]) {
+				_usb_instances->hw->DEVICE.INTFLAG.reg =
+						_usb_device_irq_bits[i];
+			}
+			if (flags_run & _usb_device_irq_bits[i]) {
+				if (i == USB_DEVICE_CALLBACK_LPMSUSP) {
+					device_callback_lpm_wakeup_enable =
+							usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE
+							& USB_LPM_ATTRIBUT_REMOTEWAKE_MASK;
+				}
+				(_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable);
+			}
+		}
+
+	} else {
+		/* endpoint interrupt */
+
+		for (uint8_t i = 0; i < USB_EPT_NUM; i++) {
+
+			if (ep_inst & (1 << i)) {
+				flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg;
+				flags_run = flags &
+						_usb_instances->device_endpoint_enabled_callback_mask[i] &
+						_usb_instances->device_endpoint_registered_callback_mask[i];
+
+				// endpoint transfer stall interrupt
+				if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk) {
+					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+					} else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+					}
+
+					if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk) {
+						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances,&ep_callback_para);
+					}
+					return;
+				}
+
+				// endpoint received setup interrupt
+				if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
+					_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+					if(_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP]) {
+						ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances,&ep_callback_para);
+					}
+					return;
+				}
+
+				// endpoint transfer complete interrupt
+				if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
+					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+						ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT);
+
+					} else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+						ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+						ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE);
+					}
+					if(flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
+						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances,&ep_callback_para);
+					}
+					return;
+				}
+
+				// endpoint transfer fail interrupt
+				if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
+					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+						if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
+							usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+						}
+						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+						if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
+							return;
+						}
+					} else if(_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) {
+						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+						if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
+							usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+						}
+						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+						if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
+							return;
+						}
+					}
+
+					if(flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
+						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances,&ep_callback_para);
+					}
+					return;
+				}
+			}
+		}
+	}
+}
+
+/**
+ * \brief Enable the USB module peripheral
+ *
+ * \param module_inst pointer to USB module instance
+ */
+void usb_enable(struct usb_module *module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
+	while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+}
+
+/**
+ * \brief Disable the USB module peripheral
+ *
+ * \param module_inst pointer to USB module instance
+ */
+void usb_disable(struct usb_module *module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
+	module_inst->hw->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
+	module_inst->hw->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+}
+
+/**
+ * \brief Interrupt handler for the USB module.
+ */
+void USB_Handler(void)
+{
+	if (_usb_instances->hw->DEVICE.CTRLA.bit.MODE) {
+#if !SAML22
+		/*host mode ISR */
+		_usb_host_interrupt_handler();
+#endif
+	} else {
+		/*device mode ISR */
+		_usb_device_interrupt_handler();
+	}
+}
+
+/**
+ * \brief Get the default USB module settings
+ *
+ * \param[out] module_config  Configuration structure to initialize to default values
+ */
+void usb_get_config_defaults(struct usb_config *module_config)
+{
+	Assert(module_config);
+
+	/* Sanity check arguments */
+	Assert(module_config);
+	/* Write default configuration to config struct */
+	module_config->select_host_mode = 0;
+	module_config->run_in_standby = 1;
+	module_config->source_generator = GCLK_GENERATOR_3;
+	module_config->speed_mode = USB_SPEED_FULL;
+}
+
+#define NVM_USB_PAD_TRANSN_POS  45
+#define NVM_USB_PAD_TRANSN_SIZE 5
+#define NVM_USB_PAD_TRANSP_POS  50
+#define NVM_USB_PAD_TRANSP_SIZE 5
+#define NVM_USB_PAD_TRIM_POS  55
+#define NVM_USB_PAD_TRIM_SIZE 3
+
+/**
+ * \brief Initializes USB module instance
+ *
+ * Enables the clock and initializes the USB module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst   Pointer to the software module instance struct
+ * \param[in]     hw            Pointer to the USB hardware module
+ * \param[in]     module_config Pointer to the USB configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ */
+enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
+		struct usb_config *module_config)
+{
+	/* Sanity check arguments */
+	Assert(hw);
+	Assert(module_inst);
+	Assert(module_config);
+
+	uint32_t i,j;
+	uint32_t pad_transn, pad_transp, pad_trim;
+	struct system_pinmux_config pin_config;
+	struct system_gclk_chan_config gclk_chan_config;
+
+#if !SAML22
+	host_pipe_job_busy_status = 0;
+#endif
+
+	_usb_instances = module_inst;
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_USB);
+
+	/* Set up the USB DP/DN pins */
+	system_pinmux_get_config_defaults(&pin_config);
+	pin_config.mux_position = MUX_PA24G_USB_DM;
+	system_pinmux_pin_set_config(PIN_PA24G_USB_DM, &pin_config);
+	pin_config.mux_position = MUX_PA25G_USB_DP;
+	system_pinmux_pin_set_config(PIN_PA25G_USB_DP, &pin_config);
+
+	/* Setup clock for module */
+	system_gclk_chan_get_config_defaults(&gclk_chan_config);
+	gclk_chan_config.source_generator = module_config->source_generator;
+	system_gclk_chan_set_config(USB_GCLK_ID, &gclk_chan_config);
+	system_gclk_chan_enable(USB_GCLK_ID);
+
+	/* Reset */
+	hw->DEVICE.CTRLA.bit.SWRST = 1;
+	while (hw->DEVICE.SYNCBUSY.bit.SWRST) {
+		/* Sync wait */
+	}
+
+	/* Load Pad Calibration */
+	pad_transn =( *((uint32_t *)(NVMCTRL_OTP4)
+			+ (NVM_USB_PAD_TRANSN_POS / 32))
+		>> (NVM_USB_PAD_TRANSN_POS % 32))
+		& ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
+
+	if (pad_transn == 0x1F) {
+		pad_transn = 5;
+	}
+
+	hw->DEVICE.PADCAL.bit.TRANSN = pad_transn;
+
+	pad_transp =( *((uint32_t *)(NVMCTRL_OTP4)
+			+ (NVM_USB_PAD_TRANSP_POS / 32))
+			>> (NVM_USB_PAD_TRANSP_POS % 32))
+			& ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
+
+	if (pad_transp == 0x1F) {
+		pad_transp = 29;
+	}
+
+	hw->DEVICE.PADCAL.bit.TRANSP = pad_transp;
+
+	pad_trim =( *((uint32_t *)(NVMCTRL_OTP4)
+			+ (NVM_USB_PAD_TRIM_POS / 32))
+			>> (NVM_USB_PAD_TRIM_POS % 32))
+			& ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
+
+	if (pad_trim == 0x7) {
+		pad_trim = 3;
+	}
+
+	hw->DEVICE.PADCAL.bit.TRIM = pad_trim;
+
+	/* Set the configuration */
+	hw->DEVICE.CTRLA.bit.MODE = module_config->select_host_mode;
+	hw->DEVICE.CTRLA.bit.RUNSTDBY = module_config->run_in_standby;
+	hw->DEVICE.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]);
+	if (USB_SPEED_FULL == module_config->speed_mode) {
+		module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
+	} else if(USB_SPEED_LOW == module_config->speed_mode) {
+		module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val;
+	}
+
+	memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0,
+			sizeof(usb_descriptor_table.usb_endpoint_table));
+
+#if !SAML22
+	/* callback related init */
+	for (i = 0; i < USB_HOST_CALLBACK_N; i++) {
+		module_inst->host_callback[i] = NULL;
+	};
+	for (i = 0; i < USB_PIPE_NUM; i++) {
+		for (j = 0; j < USB_HOST_PIPE_CALLBACK_N; j++) {
+			module_inst->host_pipe_callback[i][j] = NULL;
+		}
+	};
+	module_inst->host_registered_callback_mask = 0;
+	module_inst->host_enabled_callback_mask = 0;
+	for (i = 0; i < USB_PIPE_NUM; i++) {
+		module_inst->host_pipe_registered_callback_mask[i] = 0;
+		module_inst->host_pipe_enabled_callback_mask[i] = 0;
+	}
+#endif
+
+	/*  device callback related */
+	for (i = 0; i < USB_DEVICE_CALLBACK_N; i++) {
+		module_inst->device_callback[i] = NULL;
+	}
+	for (i = 0; i < USB_EPT_NUM; i++) {
+		for(j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++) {
+			module_inst->device_endpoint_callback[i][j] = NULL;
+		}
+	}
+	module_inst->device_registered_callback_mask = 0;
+	module_inst->device_enabled_callback_mask = 0;
+	for (j = 0; j < USB_EPT_NUM; j++) {
+		module_inst->device_endpoint_registered_callback_mask[j] = 0;
+		module_inst->device_endpoint_enabled_callback_mask[j] = 0;
+	}
+
+	/* Enable interrupts for this USB module */
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_USB);
+
+	return STATUS_OK;
+}
+
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.c
new file mode 100644
index 0000000000..d6a0b115b4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.c
@@ -0,0 +1,264 @@
+/**
+ * \file
+ *
+ * \brief SAM Watchdog Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "wdt.h"
+#include <system.h>
+
+/**
+ * \brief Sets up the WDT hardware module based on the configuration.
+ *
+ * Writes a given configuration of a WDT configuration to the
+ * hardware module, and initializes the internal device struct.
+ *
+ * \param[in]  config  Pointer to the configuration struct
+ *
+ * \return Status of the configuration procedure.
+ *
+ * \retval STATUS_OK     If the module was configured correctly
+ * \retval STATUS_ERR_INVALID_ARG   If invalid argument(s) were supplied
+ * \retval STATUS_ERR_IO  If the Watchdog module is locked to be always on
+ */
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+enum status_code wdt_set_config(
+		const struct wdt_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	Wdt *const WDT_module = WDT;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_WDT);
+
+	/* Check of the Watchdog has been locked to be always on, if so, abort */
+	if (wdt_is_locked()) {
+		return STATUS_ERR_IO;
+	}
+
+	/* Check for an invalid timeout period, abort if found */
+	if (config->timeout_period == WDT_PERIOD_NONE) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Make sure the Window and Early Warning periods are not more than the
+	 * reset period, abort if either is invalid */
+	if ((config->timeout_period < config->window_period) ||
+			(config->timeout_period < config->early_warning_period)) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Disable the Watchdog module */
+	WDT_module->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
+
+	while (wdt_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	if(config->enable == false) {
+		return STATUS_OK;
+	}
+
+	uint32_t new_config = 0;
+
+	/* Update the timeout period value with the requested period */
+	new_config |= (config->timeout_period - 1) << WDT_CONFIG_PER_Pos;
+
+	/* Check if the user has requested a reset window period */
+	if (config->window_period != WDT_PERIOD_NONE) {
+		WDT_module->CTRLA.reg |= WDT_CTRLA_WEN;
+
+		/* Update and enable the timeout period value */
+		new_config |= (config->window_period - 1) << WDT_CONFIG_WINDOW_Pos;
+	} else {
+		/* Ensure the window enable control flag is cleared */
+		WDT_module->CTRLA.reg &= ~WDT_CTRLA_WEN;
+	}
+
+	while (wdt_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	/* Write the new Watchdog configuration */
+	WDT_module->CONFIG.reg = new_config;
+
+	/* Check if the user has requested an early warning period */
+	if (config->early_warning_period != WDT_PERIOD_NONE) {
+		/* Set the Early Warning period */
+		WDT_module->EWCTRL.reg
+			= (config->early_warning_period - 1) << WDT_EWCTRL_EWOFFSET_Pos;
+	}
+
+	/* Either enable or lock-enable the Watchdog timer depending on the user
+	 * settings */
+	if (config->always_on) {
+		WDT_module->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
+	} else {
+		WDT_module->CTRLA.reg |= WDT_CTRLA_ENABLE;
+	}
+
+	while (wdt_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	return STATUS_OK;
+}
+#else
+enum status_code wdt_set_config(
+		const struct wdt_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	Wdt *const WDT_module = WDT;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_WDT);
+
+	/* Check of the Watchdog has been locked to be always on, if so, abort */
+	if (wdt_is_locked()) {
+		return STATUS_ERR_IO;
+	}
+
+	/* Check for an invalid timeout period, abort if found */
+	if (config->timeout_period == WDT_PERIOD_NONE) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Make sure the Window and Early Warning periods are not more than the
+	 * reset period, abort if either is invalid */
+	if ((config->timeout_period < config->window_period) ||
+			(config->timeout_period < config->early_warning_period)) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Disable the Watchdog module */
+	WDT_module->CTRL.reg &= ~WDT_CTRL_ENABLE;
+
+	while (wdt_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	if(config->enable == false) {
+		return STATUS_OK;
+	}
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(WDT_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(WDT_GCLK_ID);
+	if (config->always_on) {
+		system_gclk_chan_lock(WDT_GCLK_ID);
+	}
+
+	uint32_t new_config = 0;
+
+	/* Update the timeout period value with the requested period */
+	new_config |= (config->timeout_period - 1) << WDT_CONFIG_PER_Pos;
+
+	/* Check if the user has requested a reset window period */
+	if (config->window_period != WDT_PERIOD_NONE) {
+		WDT_module->CTRL.reg |= WDT_CTRL_WEN;
+
+		/* Update and enable the timeout period value */
+		new_config |= (config->window_period - 1) << WDT_CONFIG_WINDOW_Pos;
+	} else {
+		/* Ensure the window enable control flag is cleared */
+		WDT_module->CTRL.reg &= ~WDT_CTRL_WEN;
+	}
+
+	while (wdt_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	/* Write the new Watchdog configuration */
+	WDT_module->CONFIG.reg = new_config;
+
+	/* Check if the user has requested an early warning period */
+	if (config->early_warning_period != WDT_PERIOD_NONE) {
+		while (wdt_is_syncing()) {
+			/* Wait for all hardware modules to complete synchronization */
+		}
+
+		/* Set the Early Warning period */
+		WDT_module->EWCTRL.reg
+			= (config->early_warning_period - 1) << WDT_EWCTRL_EWOFFSET_Pos;
+	}
+
+	/* Either enable or lock-enable the Watchdog timer depending on the user
+	 * settings */
+	if (config->always_on) {
+		WDT_module->CTRL.reg |= WDT_CTRL_ALWAYSON;
+	} else {
+		WDT_module->CTRL.reg |= WDT_CTRL_ENABLE;
+	}
+
+	while (wdt_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	return STATUS_OK;
+}
+#endif
+
+/**
+ * \brief Resets the count of the running Watchdog Timer that was previously enabled.
+ *
+ * Resets the current count of the Watchdog Timer, restarting the timeout
+ * period count elapsed. This function should be called after the window
+ * period (if one was set in the module configuration) but before the timeout
+ * period to prevent a reset of the system.
+ */
+void wdt_reset_count(void)
+{
+	Wdt *const WDT_module = WDT;
+
+	/* Disable the Watchdog module */
+	WDT_module->CLEAR.reg = WDT_CLEAR_CLEAR_KEY;
+
+	while (wdt_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.h
new file mode 100644
index 0000000000..0109e9def6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.h
@@ -0,0 +1,503 @@
+/**
+ * \file
+ *
+ * \brief SAM Watchdog Driver
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef WDT_H_INCLUDED
+#define WDT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_wdt_group SAM Watchdog (WDT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's Watchdog
+ * Timer module, including the enabling, disabling, and kicking within the device.
+ * The following driver API modes are covered by this manual:
+ *
+ *  - Polled APIs
+ * \if WDT_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripherals are used by this module:
+ *  - WDT (Watchdog Timer)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_wdt_prerequisites
+ *  - \ref asfdoc_sam0_wdt_module_overview
+ *  - \ref asfdoc_sam0_wdt_special_considerations
+ *  - \ref asfdoc_sam0_wdt_extra_info
+ *  - \ref asfdoc_sam0_wdt_examples
+ *  - \ref asfdoc_sam0_wdt_api_overview
+ *
+ *
+ * \section asfdoc_sam0_wdt_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_wdt_module_overview Module Overview
+ *
+ * The Watchdog module (WDT) is designed to give an added level of safety in
+ * critical systems, to ensure a system reset is triggered in the case of a
+ * deadlock or other software malfunction that prevents normal device operation.
+ *
+ * At a basic level, the Watchdog is a system timer with a fixed period; once
+ * enabled, it will continue to count ticks of its asynchronous clock until
+ * it is periodically reset, or the timeout period is reached. In the event of a
+ * Watchdog timeout, the module will trigger a system reset identical to a pulse
+ * of the device's reset pin, resetting all peripherals to their power-on
+ * default states and restarting the application software from the reset vector.
+ *
+ * In many systems, there is an obvious upper bound to the amount of time each
+ * iteration of the main application loop can be expected to run, before a
+ * malfunction can be assumed (either due to a deadlock waiting on hardware or
+ * software, or due to other means). When the Watchdog is configured with a
+ * timeout period equal to this upper bound, a malfunction in the system will
+ * force a full system reset to allow for a graceful recovery.
+ *
+ * \subsection asfdoc_sam0_wdt_module_locked_mode Locked Mode
+ * The Watchdog configuration can be set in the device fuses and locked in
+ * hardware, so that no software changes can be made to the Watchdog
+ * configuration. Additionally, the Watchdog can be locked on in software if it
+ * is not already locked, so that the module configuration cannot be modified
+ * until a power on reset of the device.
+ *
+ * The locked configuration can be used to ensure that faulty software does not
+ * cause the Watchdog configuration to be changed, preserving the level of
+ * safety given by the module.
+ *
+ * \subsection asfdoc_sam0_wdt_module_window_mode Window Mode
+ * Just as there is a reasonable upper bound to the time the main program loop
+ * should take for each iteration, there is also in many applications a lower
+ * bound, i.e. a \a minimum time for which each loop iteration should run for
+ * under normal circumstances. To guard against a system failure resetting the
+ * Watchdog in a tight loop (or a failure in the system application causing the
+ * main loop to run faster than expected) a "Window" mode can be enabled to
+ * disallow resetting of the Watchdog counter before a certain period of time.
+ * If the Watchdog is not reset \a after the window opens but not \a before the
+ * Watchdog expires, the system will reset.
+ *
+ * \subsection asfdoc_sam0_wdt_module_early_warning Early Warning
+ * In some cases it is desirable to receive an early warning that the Watchdog is
+ * about to expire, so that some system action (such as saving any system
+ * configuration data for failure analysis purposes) can be performed before the
+ * system reset occurs. The Early Warning feature of the Watchdog module allows
+ * such a notification to be requested; after the configured early warning time
+ * (but before the expiry of the Watchdog counter) the Early Warning flag will
+ * become set, so that the user application can take an appropriate action.
+ *
+ * \note It is important to note that the purpose of the Early Warning feature
+ *       is \a not to allow the user application to reset the Watchdog; doing
+ *       so will defeat the safety the module gives to the user application.
+ *       Instead, this feature should be used purely to perform any tasks that
+ *       need to be undertaken before the system reset occurs.
+ *
+ * \subsection asfdoc_sam0_wdt_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_wdt_module_int_connections "The figure below" shows how
+ * this module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_wdt_module_int_connections
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="GCLK*\nGeneric Clock" shape=square] wdt_clock;
+ *
+ *   subgraph driver {
+ *     node [label="<f0> WDT | <f1> Watchdog Counter" shape=record] wdt_module;
+ *     node [label="System Reset Logic" shape=ellipse style=filled fillcolor=lightgray] sys_reset;
+ *   }
+ *
+ *   wdt_clock     -> wdt_module:f1;
+ *   wdt_module:f1 -> sys_reset;
+ * }
+ * \enddot
+ *
+ * \note Watchdog Counter of SAM L21/L22/R30 is \a not provided by GCLK, but it uses an
+ *       internal 1KHz OSCULP32K output clock.
+ *
+ * \section asfdoc_sam0_wdt_special_considerations Special Considerations
+ *
+ * On some devices the Watchdog configuration can be fused to be always on in
+ * a particular configuration; if this mode is enabled the Watchdog is not
+ * software configurable and can have its count reset and early warning state
+ * checked/cleared only.
+ *
+ * \section asfdoc_sam0_wdt_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_wdt_extra. This includes:
+ *  - \ref asfdoc_sam0_wdt_extra_acronyms
+ *  - \ref asfdoc_sam0_wdt_extra_dependencies
+ *  - \ref asfdoc_sam0_wdt_extra_errata
+ *  - \ref asfdoc_sam0_wdt_extra_history
+ *
+ *
+ * \section asfdoc_sam0_wdt_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_wdt_exqsg.
+ *
+ * \section asfdoc_sam0_wdt_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+
+#if WDT_CALLBACK_MODE == true
+#  include "wdt_callback.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Watchdog Timer period configuration enum.
+ *
+ * Enum for the possible period settings of the Watchdog timer module, for
+ * values requiring a period as a number of Watchdog timer clock ticks.
+ */
+enum wdt_period {
+	/** No Watchdog period. This value can only be used when setting the
+	 *  Window and Early Warning periods; its use as the Watchdog Reset
+	 *  Period is invalid. */
+	WDT_PERIOD_NONE     = 0,
+	/** Watchdog period of 8 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_8CLK     = 1,
+	/** Watchdog period of 16 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_16CLK    = 2,
+	/** Watchdog period of 32 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_32CLK    = 3,
+	/** Watchdog period of 64 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_64CLK    = 4,
+	/** Watchdog period of 128 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_128CLK   = 5,
+	/** Watchdog period of 256 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_256CLK   = 6,
+	/** Watchdog period of 512 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_512CLK   = 7,
+	/** Watchdog period of 1024 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_1024CLK  = 8,
+	/** Watchdog period of 2048 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_2048CLK  = 9,
+	/** Watchdog period of 4096 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_4096CLK  = 10,
+	/** Watchdog period of 8192 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_8192CLK  = 11,
+	/** Watchdog period of 16384 clocks of the Watchdog Timer Generic Clock */
+	WDT_PERIOD_16384CLK = 12,
+};
+
+/**
+ * \brief Watchdog Timer configuration structure.
+ *
+ *  Configuration structure for a Watchdog Timer instance. This
+ *  structure should be initialized by the \ref wdt_get_config_defaults()
+ *  function before being modified by the user application.
+ */
+struct wdt_conf {
+	/** If \c true, the Watchdog will be locked to the current configuration
+	 *  settings when the Watchdog is enabled */
+	bool always_on;
+	/** Enable/Disable the Watchdog Timer */
+	bool enable;
+#if !(SAML21) && !(SAML22) && !(SAMC20) && !(SAMC21) && !(SAMR30)
+	/** GCLK generator used to clock the peripheral except SAM L21/L22/C21/C20/R30*/
+	enum gclk_generator clock_source;
+#endif
+	/** Number of Watchdog timer clock ticks until the Watchdog expires */
+	enum wdt_period timeout_period;
+	/** Number of Watchdog timer clock ticks until the reset window opens */
+	enum wdt_period window_period;
+	/** Number of Watchdog timer clock ticks until the early warning flag is
+	 *  set */
+	enum wdt_period early_warning_period;
+};
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false If the module has completed synchronization
+ * \retval true If the module synchronization is ongoing
+ */
+static inline bool wdt_is_syncing(void)
+{
+	Wdt *const WDT_module = WDT;
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	if (WDT_module->SYNCBUSY.reg) {
+#else
+	if (WDT_module->STATUS.reg & WDT_STATUS_SYNCBUSY) {
+#endif
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Initializes a Watchdog Timer configuration structure to defaults.
+ *
+ *  Initializes a given Watchdog Timer configuration structure to a set of
+ *  known default values. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Not locked, to allow for further (re-)configuration
+ *   \li Enable WDT
+ *   \li Watchdog timer sourced from Generic Clock Channel 4
+ *   \li A timeout period of 16384 clocks of the Watchdog module clock
+ *   \li No window period, so that the Watchdog count can be reset at any time
+ *   \li No early warning period to indicate the Watchdog will soon expire
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void wdt_get_config_defaults(
+		struct wdt_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->always_on            = false;
+	config->enable               = true;
+#if !(SAML21) && !(SAML22) && !(SAMC20) && !(SAMC21) && !(SAMR30)
+	config->clock_source         = GCLK_GENERATOR_4;
+#endif
+	config->timeout_period       = WDT_PERIOD_16384CLK;
+	config->window_period        = WDT_PERIOD_NONE;
+	config->early_warning_period = WDT_PERIOD_NONE;
+}
+
+enum status_code wdt_set_config(
+		const struct wdt_conf *const config);
+
+/** \brief Determines if the Watchdog timer is currently locked in an enabled state.
+ *
+ *  Determines if the Watchdog timer is currently enabled and locked, so that
+ *  it cannot be disabled or otherwise reconfigured.
+ *
+ *  \return Current Watchdog lock state.
+ */
+static inline bool wdt_is_locked(void)
+{
+	Wdt *const WDT_module = WDT;
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	return (WDT_module->CTRLA.reg & WDT_CTRLA_ALWAYSON);
+#else
+	return (WDT_module->CTRL.reg & WDT_CTRL_ALWAYSON);
+#endif
+}
+
+/** @} */
+
+/** \name Timeout and Early Warning Management
+ * @{
+ */
+
+/** \brief Clears the Watchdog timer early warning period elapsed flag.
+ *
+ *  Clears the Watchdog timer early warning period elapsed flag, so that a new
+ *  early warning period can be detected.
+ */
+static inline void wdt_clear_early_warning(void)
+{
+	Wdt *const WDT_module = WDT;
+
+	WDT_module->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+/** \brief Determines if the Watchdog timer early warning period has elapsed.
+ *
+ *  Determines if the Watchdog timer early warning period has elapsed.
+ *
+ *  \note If no early warning period was configured, the value returned by this
+ *        function is invalid.
+ *
+ *  \return Current Watchdog Early Warning state.
+ */
+static inline bool wdt_is_early_warning(void)
+{
+	Wdt *const WDT_module = WDT;
+
+	return (WDT_module->INTFLAG.reg & WDT_INTFLAG_EW);
+}
+
+void wdt_reset_count(void);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_wdt_extra Extra Information for WDT Driver
+ *
+ * \section asfdoc_sam0_wdt_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>WDT</td>
+ *		<td>Watchdog Timer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_wdt_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_clock_group "System Clock Driver"
+ *
+ *
+ * \section asfdoc_sam0_wdt_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_wdt_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Driver updated to follow driver type convention:
+ *             \li wdt_init, wdt_enable, wdt_disable functions removed
+ *             \li wdt_set_config function added
+ *             \li WDT module enable state moved inside the configuration struct </td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_wdt_exqsg Examples for WDT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_wdt_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_wdt_basic_use_case
+ * \if WDT_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_wdt_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_wdt_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42124E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, SAM R30, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42124D</td>
+ *		<td>12/2014</td>
+ *		<td>Added SAM R21 and SAM D10/D11 support</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42124C</td>
+ *		<td>01/2014</td>
+ *		<td>Add SAM D21 support</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42124B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42124A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* WDT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.c
new file mode 100644
index 0000000000..89429595a4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.c
@@ -0,0 +1,174 @@
+/**
+ * \file
+ *
+ * \brief SAM Watchdog Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "wdt.h"
+#include <system.h>
+#include <system_interrupt.h>
+
+wdt_callback_t wdt_early_warning_callback;
+
+/**
+ * \brief Registers an asynchronous callback function with the driver.
+ *
+ * Registers an asynchronous callback with the WDT driver, fired when a
+ * given criteria (such as an Early Warning) is met. Callbacks are fired once
+ * for each event.
+ *
+ * \param[in] callback  Pointer to the callback function to register
+ * \param[in] type      Type of callback function to register
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK               The callback was registered successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code wdt_register_callback(
+		const wdt_callback_t callback,
+		const enum wdt_callback type)
+{
+	/* Sanity check arguments */
+	Assert(callback);
+
+	switch (type)
+	{
+	case WDT_CALLBACK_EARLY_WARNING:
+		wdt_early_warning_callback = callback;
+		return STATUS_OK;
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Unregisters an asynchronous callback function with the driver.
+ *
+ * Unregisters an asynchronous callback with the WDT driver, removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] type  Type of callback function to unregister
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK               The callback was Unregistered successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code wdt_unregister_callback(
+		const enum wdt_callback type)
+{
+	switch (type)
+	{
+	case WDT_CALLBACK_EARLY_WARNING:
+		wdt_early_warning_callback = NULL;
+		return STATUS_OK;
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Enables asynchronous callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given callback type. This must be
+ * called before an external interrupt channel will generate callback events.
+ *
+ * \param[in] type  Type of callback function to enable
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK               The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code wdt_enable_callback(
+		const enum wdt_callback type)
+{
+	Wdt *const WDT_module = WDT;
+
+	switch (type)
+	{
+	case WDT_CALLBACK_EARLY_WARNING:
+		WDT_module->INTENSET.reg = WDT_INTENSET_EW;
+		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_WDT);
+		return STATUS_OK;
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Disables asynchronous callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given callback type.
+ *
+ * \param[in] type  Type of callback function to disable
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK               The callback was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code wdt_disable_callback(
+		const enum wdt_callback type)
+{
+	Wdt *const WDT_module = WDT;
+
+	switch (type)
+	{
+	case WDT_CALLBACK_EARLY_WARNING:
+		WDT_module->INTENCLR.reg = WDT_INTENCLR_EW;
+		return STATUS_OK;
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/** Handler for the WDT hardware module interrupt. */
+void WDT_Handler(void)
+{
+	wdt_clear_early_warning();
+
+	if (wdt_early_warning_callback) {
+		wdt_early_warning_callback();
+	}
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.h
new file mode 100644
index 0000000000..af76dc344b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.h
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief SAM Watchdog Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef WDT_CALLBACK_H_INCLUDED
+#define WDT_CALLBACK_H_INCLUDED
+
+#include <compiler.h>
+#include "wdt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_wdt_group
+ *
+ * @{
+ */
+
+/** \name Callback Configuration and Initialization
+ * @{
+ */
+
+/** Type definition for a WDT module callback function. */
+typedef void (*wdt_callback_t)(void);
+
+/** Enum for the possible callback types for the WDT module. */
+enum wdt_callback
+{
+	/** Callback type for when an early warning callback from the WDT module
+	 *  is issued
+	 */
+	WDT_CALLBACK_EARLY_WARNING,
+};
+
+enum status_code wdt_register_callback(
+		const wdt_callback_t callback,
+		const enum wdt_callback type);
+
+enum status_code wdt_unregister_callback(
+		const enum wdt_callback type);
+
+/** @} */
+
+/** \name Callback Enabling and Disabling
+ * @{
+ */
+
+enum status_code wdt_enable_callback(
+		const enum wdt_callback type);
+
+enum status_code wdt_disable_callback(
+		const enum wdt_callback type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.c
new file mode 100644
index 0000000000..14276b3b3a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.c
@@ -0,0 +1,349 @@
+/**
+ * \file
+ *
+ * \brief SAM Watchdog Driver for SAMB
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "wdt_sam_b.h"
+
+struct wdt_module *_wdt_instances[WDT_INST_NUM];
+
+static void wdt_isr_handler(void)
+{
+	struct wdt_module *module = NULL;
+	
+	if (WDT0->WDOGMIS.reg) {
+		module = _wdt_instances[0];
+		if (!(module->hw->WDOGCONTROL.reg & WDT_WDOGCONTROL_RESEN)) {
+			module->hw->WDOGINTCLR.reg = 0x01;
+		}
+		if ((module->callback_enable_mask & (1 << WDT_CALLBACK_EARLY_WARNING)) &&
+			(module->callback_reg_mask & (1 << WDT_CALLBACK_EARLY_WARNING))) {
+			(module->callback[WDT_CALLBACK_EARLY_WARNING])();
+		}
+	}
+	if (WDT1->WDOGMIS.reg) {
+		module = _wdt_instances[1];
+		if (!(module->hw->WDOGCONTROL.reg & WDT_WDOGCONTROL_RESEN)) {
+			module->hw->WDOGINTCLR.reg = 0x01;
+		}
+		if ((module->callback_enable_mask & (1 << WDT_CALLBACK_EARLY_WARNING)) &&
+			(module->callback_reg_mask & (1 << WDT_CALLBACK_EARLY_WARNING))) {
+			(module->callback[WDT_CALLBACK_EARLY_WARNING])();
+		}
+	}
+}
+
+/**
+ * \brief Initializes a Watchdog Timer configuration structure to defaults.
+ *
+ *  Initializes a given Watchdog Timer configuration structure to a set of
+ *  known default values. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Load register value
+ *   \li Enable reset output
+ *   \li Open write access
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+void wdt_get_config_defaults(struct wdt_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	config->load_value = 0xFFFFFFFF;
+	config->enable_reset = true;
+	config->write_access = true;
+}
+
+/**
+ * \brief Sets up the WDT hardware module based on the configuration.
+ *
+ * Writes a given configuration of a WDT configuration to the
+ * hardware module, and initializes the internal device struct.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ * \param[in]  hw      Pointer to WDT hardware instance
+ * \param[in]  config  Pointer to configuration struct
+ *
+ * \return Status of the initialization.
+ *
+ * \retval STATUS_OK            The initialization was successful
+ * \retval STATUS_ERR_BAD_DATA  If the value isn't available
+ */
+enum status_code wdt_set_config(struct wdt_module *const module, Wdt * const hw,
+		const struct wdt_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Assign module pointer to software instance struct */
+	module->hw = hw;
+
+	if (config->load_value == 0) {
+		return STATUS_ERR_BAD_DATA;
+	}
+	
+	if (module->hw == WDT0) {
+		system_clock_peripheral_disable(PERIPHERAL_WDT0);
+	} else if (module->hw ==WDT1) {
+		system_clock_peripheral_disable(PERIPHERAL_WDT1);
+	}
+
+	/* Unlock register */
+	module->hw->WDOGLOCK.reg = WDT_WRITE_ACCESS_KEY;
+
+	module->hw->WDOGLOAD.reg = config->load_value;
+
+	if (config->enable_reset) {
+		module->hw->WDOGCONTROL.reg |= WDT_WDOGCONTROL_RESEN;
+	}
+	module->hw->WDOGCONTROL.reg |= WDT_WDOGCONTROL_INTEN;
+	
+	/* Lock register */
+	if (config->write_access == false) {
+		module->hw->WDOGLOCK.reg = WDT_WDOGLOCK_ENABLE_STATUS;
+	}
+	
+	system_register_isr(RAM_ISR_TABLE_NMI_INDEX, (uint32_t)wdt_isr_handler);
+	
+	/* Enable WDT clock */
+	if (module->hw == WDT0) {
+		_wdt_instances[0] = module;
+		system_clock_peripheral_enable(PERIPHERAL_WDT0);
+	} else if (module->hw == WDT1) {
+		_wdt_instances[1] = module;
+		system_clock_peripheral_enable(PERIPHERAL_WDT1);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Reset WDT module.
+ *
+ * Reset WDT module.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ */
+void wdt_reset(struct wdt_module *const module)
+{
+	if (module->hw == WDT0) {
+		system_peripheral_reset(PERIPHERAL_WDT0);
+	} else if (module->hw == WDT1) {
+		system_peripheral_reset(PERIPHERAL_WDT1);
+	}
+}
+
+/**
+ * \brief Get WDT interrupt status.
+ *
+ * Get WDT interrupt status.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ */
+uint8_t wdt_get_interrupt_status(struct wdt_module *const module)
+{
+	return module->hw->WDOGMIS.reg;
+}
+
+/**
+ * \brief Get WDT raw interrupt status.
+ *
+ * Get WDT raw interrupt status.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ */
+uint8_t wdt_get_status(struct wdt_module *const module)
+{
+	return module->hw->WDOGRIS.reg;
+}
+
+/**
+ * \brief Clear WDT interrupt status.
+ *
+ * Clear WDT interrupt status.
+ *
+ * \param[in]  module  Pointer to the software instance struct
+ */
+void wdt_clear_status(struct wdt_module *const module)
+{
+	module->hw->WDOGINTCLR.reg = 0x01;
+}
+
+/**
+ * \brief Reload the count of the running Watchdog Timer.
+ *
+ * Reload the value of WDT Load register. When this register is written to,
+ * the count is immediately restarted from the new value.
+ *
+ * \param[in]  module      Pointer to the software instance struct
+ * \param[in]  load_value  Reload value
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK            If the operation was completed
+ * \retval STATUS_ERR_BAD_DATA  If the value isn't available
+ */
+enum status_code wdt_set_reload_count(struct wdt_module *const module, uint32_t load_value)
+{
+	if (load_value == 0) {
+		return STATUS_ERR_BAD_DATA;
+	} else {
+		if (module->hw->WDOGLOCK.bit.ENABLE_STATUS) {
+			module->hw->WDOGLOCK.reg = WDT_WRITE_ACCESS_KEY;
+			module->hw->WDOGLOAD.reg = load_value;
+			module->hw->WDOGLOCK.reg = WDT_WDOGLOCK_ENABLE_STATUS;
+		} else {
+			module->hw->WDOGLOAD.reg = load_value;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current count value of the running Watchdog Timer.
+ *
+ * Get the current count value of the running Watchdog Timer.
+ *
+ * \param[in]      module       Pointer to the software instance struct
+ * \param[in,out]  count_value  Pointer to store the current count value
+ *
+ */
+void wdt_get_current_count(struct wdt_module *const module, \
+			uint32_t * count_value)
+{
+	*count_value = module->hw->WDOGVALUE.reg;
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref wdt_enable_callback,
+ *       in order for the interrupt handler to call it when the conditions for
+ *       the callback type are met.
+ *
+ * \param[in]  module         Pointer to WDT software instance struct
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void wdt_register_callback(struct wdt_module *const module,
+		wdt_callback_t callback_func,
+		enum wdt_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+	/* Set the bit corresponding to the callback_type */
+	module->callback_reg_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in,out]  module         Pointer to WDT software instance struct
+ * \param[in]      callback_type  Callback type given by an enum
+ *
+ */
+void wdt_unregister_callback(struct wdt_module *module,
+		enum wdt_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+	/* Clear the bit corresponding to the callback_type */
+	module->callback_reg_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref usart_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in]  module         Pointer to WDT software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+void wdt_enable_callback(struct wdt_module *const module,
+		enum wdt_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->callback_enable_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Disable callback
+ *
+ * Disables the callback function registered by the \ref usart_register_callback,
+ * and the callback will not be called from the interrupt routine.
+ *
+ * \param[in]  module         Pointer to WDT software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+void wdt_disable_callback(struct wdt_module *const module,
+		enum wdt_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->callback_enable_mask &= ~(1 << callback_type);
+}
\ No newline at end of file
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.h
new file mode 100644
index 0000000000..3cd162211b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.h
@@ -0,0 +1,304 @@
+/**
+ * \file
+ *
+ * \brief SAM Watchdog Driver for SAMB
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef WDT_SAM_B_H_INCLUDED
+#define WDT_SAM_B_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_samb_wdt_group SAM Watchdog Driver (WDT)
+ *
+ * This driver for Atmel&reg; | SMART SAM devices provides an interface for the configuration
+ * and management of the device's Watchdog Timer module, including the enabling,
+ * disabling, and kicking within the device.
+ *
+ * The following peripherals are used by this module:
+ *  - WDT (Watchdog Timer)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM B11
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_samb_wdt_prerequisites
+ *  - \ref asfdoc_samb_wdt_module_overview
+ *  - \ref asfdoc_samb_wdt_special_considerations
+ *  - \ref asfdoc_samb_wdt_extra_info
+ *  - \ref asfdoc_samb_wdt_examples
+ *  - \ref asfdoc_samb_wdt_api_overview
+ *
+ *
+ * \section asfdoc_samb_wdt_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_samb_wdt_module_overview Module Overview
+ * The watchdog module is based on a 32-bit down-counter that is initialized
+ * from the Reload Register. The watchdog module generates a regular interrupt,
+ * depending on a programmed value. The counter decrements by one on each
+ * positive clock edge of clock when the clock is enable. The watchdog monitors
+ * the interrupt and asserts a reset request signal when the counter reaches 0,
+ * and the counter is stopped. On the next enabled clock edge, the counter is
+ * reloaded from the WDT load Register and the countdown sequence continues. If
+ * the interrupt is not cleared by the time the counter next reaches 0, the
+ * watchdog module reasserts the reset signal.
+ *
+ * A simplified block diagram of the WDT can be seen in
+ * \ref asfdoc_samb_wdt_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_samb_wdt_module_block_diagram
+ * \image html wdt_block_diagram.svg "WDT Block Diagram"
+ *
+ * \section asfdoc_samb_wdt_special_considerations Special Considerations
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_samb_wdt_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_samb_wdt_extra. This includes:
+ *  - \ref asfdoc_samb_wdt_extra_acronyms
+ *  - \ref asfdoc_samb_wdt_extra_dependencies
+ *  - \ref asfdoc_samb_wdt_extra_errata
+ *  - \ref asfdoc_samb_wdt_extra_history
+ *
+ *
+ * \section asfdoc_samb_wdt_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_samb_wdt_exqsg.
+ *
+ * \section asfdoc_samb_wdt_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system_sam_b.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define WDT_WRITE_ACCESS_KEY    0x1ACCE551
+
+struct wdt_module;
+/** Type definition for a WDT module callback function. */
+typedef void (*wdt_callback_t)(void);
+
+/** Enum for the possible callback types for the WDT module. */
+enum wdt_callback
+{
+	/** 
+	 * Callback type for when an early warning callback from the WDT module
+	 * is issued
+	 */
+	WDT_CALLBACK_EARLY_WARNING,
+	/** Number of available callbacks */
+	WDT_CALLBACK_N,
+};
+
+/**
+ * \brief Watchdog Timer configuration structure.
+ *
+ *  Configuration structure for a Watchdog Timer instance. This
+ *  structure should be initialized by the \ref wdt_get_config_defaults()
+ *  function before being modified by the user application.
+ */
+struct wdt_config {
+	/** Watchdog load value */
+	uint32_t load_value;
+	/** Enable reset output */
+	bool enable_reset;
+	/** Enable write access */
+	bool write_access;
+};
+
+/**
+ * \brief WDT driver software device instance structure.
+ *
+ * WDT driver software instance structure, used to retain software
+ * state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct wdt_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to the hardware instance */
+	Wdt *hw;
+	/** Array to store callback function pointers in */
+	wdt_callback_t callback[WDT_CALLBACK_N];
+	/** Bit mask for callbacks registered */
+	uint8_t callback_reg_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t callback_enable_mask;
+#endif
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+void wdt_get_config_defaults(struct wdt_config *const config);
+enum status_code wdt_set_config(struct wdt_module *const module, Wdt * const hw, \
+			const struct wdt_config *const config);
+/** @} */
+
+/**
+ * \name Reset
+ * @{
+ */
+void wdt_reset(struct wdt_module *const module);
+/** @} */
+
+/**
+ * \name Get and Clear status
+ * @{
+ */
+uint8_t wdt_get_interrupt_status(struct wdt_module *const module);
+uint8_t wdt_get_status(struct wdt_module *const module);
+void wdt_clear_status(struct wdt_module *const module);
+/** @} */
+
+/**
+ * \name Reload and get count value
+ * @{
+ */
+enum status_code wdt_set_reload_count(struct wdt_module *const module, \
+			uint32_t load_value);
+void wdt_get_current_count(struct wdt_module *const module, \
+			uint32_t * count_value);
+/** @} */
+
+/**
+ * \name Callback
+ * @{
+ */
+void wdt_register_callback(struct wdt_module *const module,
+		wdt_callback_t callback_func,
+		enum wdt_callback callback_type);
+void wdt_unregister_callback(struct wdt_module *module,
+		enum wdt_callback callback_type);
+void wdt_enable_callback(struct wdt_module *module,
+		enum wdt_callback callback_type);
+void wdt_disable_callback(struct wdt_module *const module,
+		enum wdt_callback callback_type);
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_samb_wdt_extra Extra Information for WDT Driver
+ *
+ * \section asfdoc_samb_wdt_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>WDT</td>
+ *		<td>Watchdog Timer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_samb_wdt_extra_dependencies Dependencies
+ * There are no dependencies related to this driver.
+ *
+ *
+ * \section asfdoc_samb_wdt_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_samb_wdt_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_samb_wdt_exqsg Examples for WDT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_samb_wdt_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_samb_wdt_basic_use_case
+ *
+ * \page asfdoc_samb_wdt_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>A</td>
+ *		<td>09/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* WDT_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/ac.h
new file mode 100644
index 0000000000..a457f83bd9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/ac.h
@@ -0,0 +1,562 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_AC_COMPONENT_
+#define _SAMD20_AC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMD20_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2205
+#define REV_AC                      0x111
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  LPMUX:1;          /*!< bit:      7  Low-Power Mux                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE         0x00ul       /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST              (0x1ul << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE             (0x1ul << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_RUNSTDBY_Pos       2            /**< \brief (AC_CTRLA) Run in Standby */
+#define AC_CTRLA_RUNSTDBY_Msk       (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY(value)    ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))
+#define AC_CTRLA_LPMUX_Pos          7            /**< \brief (AC_CTRLA) Low-Power Mux */
+#define AC_CTRLA_LPMUX              (0x1ul << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK               0x87ul       /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START0:1;         /*!< bit:      0  Comparator 0 Start Comparison      */
+    uint8_t  START1:1;         /*!< bit:      1  Comparator 1 Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  START:2;          /*!< bit:  0.. 1  Comparator x Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE         0x00ul       /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0             (1 << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1             (1 << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk          (0x3ul << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value)       ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)))
+#define AC_CTRLB_MASK               0x03ul       /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMPEO0:1;        /*!< bit:      0  Comparator 0 Event Output Enable   */
+    uint16_t COMPEO1:1;        /*!< bit:      1  Comparator 1 Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO0:1;         /*!< bit:      4  Window 0 Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI0:1;        /*!< bit:      8  Comparator 0 Event Input           */
+    uint16_t COMPEI1:1;        /*!< bit:      9  Comparator 1 Event Input           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t COMPEO:2;         /*!< bit:  0.. 1  Comparator x Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO:1;          /*!< bit:      4  Window x Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI:2;         /*!< bit:  8.. 9  Comparator x Event Input           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0           (1 << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1           (1 << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk        (0x3ul << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value)     ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)))
+#define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0            (1 << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk         (0x1ul << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value)      ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)))
+#define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
+#define AC_EVCTRL_COMPEI0           (1 << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
+#define AC_EVCTRL_COMPEI1           (1 << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input */
+#define AC_EVCTRL_COMPEI_Msk        (0x3ul << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value)     ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)))
+#define AC_EVCTRL_MASK              0x0313ul     /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0           (1 << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1           (1 << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk        (0x3ul << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value)     ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)))
+#define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0            (1 << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk         (0x1ul << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value)      ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)))
+#define AC_INTENCLR_MASK            0x13ul       /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE      0x00ul       /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0           (1 << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1           (1 << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk        (0x3ul << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value)     ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)))
+#define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0            (1 << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk         (0x1ul << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value)      ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)))
+#define AC_INTENSET_MASK            0x13ul       /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0                           */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x                       */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x                           */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0            (1 << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1            (1 << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk         (0x3ul << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value)      ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)))
+#define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0             (1 << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk          (0x1ul << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value)       ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)))
+#define AC_INTFLAG_MASK             0x13ul       /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/   8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET           0x08         /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE       0x00ul       /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0           (1 << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1           (1 << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk        (0x3ul << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value)     ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)))
+#define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk      (0x3ul << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value)   ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))
+#define   AC_STATUSA_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSA) Signal is above window */
+#define   AC_STATUSA_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSA) Signal is inside window */
+#define   AC_STATUSA_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK             0x33ul       /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY0:1;         /*!< bit:      0  Comparator 0 Ready                 */
+    uint8_t  READY1:1;         /*!< bit:      1  Comparator 1 Ready                 */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  READY:2;          /*!< bit:  0.. 1  Comparator x Ready                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET           0x09         /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE       0x00ul       /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0           (1 << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1           (1 << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk        (0x3ul << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value)     ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)))
+#define AC_STATUSB_SYNCBUSY_Pos     7            /**< \brief (AC_STATUSB) Synchronization Busy */
+#define AC_STATUSB_SYNCBUSY         (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK             0x83ul       /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/   8) Status C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSC_OFFSET           0x0A         /**< \brief (AC_STATUSC offset) Status C */
+#define AC_STATUSC_RESETVALUE       0x00ul       /**< \brief (AC_STATUSC reset_value) Status C */
+
+#define AC_STATUSC_STATE0_Pos       0            /**< \brief (AC_STATUSC) Comparator 0 Current State */
+#define AC_STATUSC_STATE0           (1 << AC_STATUSC_STATE0_Pos)
+#define AC_STATUSC_STATE1_Pos       1            /**< \brief (AC_STATUSC) Comparator 1 Current State */
+#define AC_STATUSC_STATE1           (1 << AC_STATUSC_STATE1_Pos)
+#define AC_STATUSC_STATE_Pos        0            /**< \brief (AC_STATUSC) Comparator x Current State */
+#define AC_STATUSC_STATE_Msk        (0x3ul << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE(value)     ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)))
+#define AC_STATUSC_WSTATE0_Pos      4            /**< \brief (AC_STATUSC) Window 0 Current State */
+#define AC_STATUSC_WSTATE0_Msk      (0x3ul << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0(value)   ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))
+#define   AC_STATUSC_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSC) Signal is above window */
+#define   AC_STATUSC_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSC) Signal is inside window */
+#define   AC_STATUSC_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSC) Signal is below window */
+#define AC_STATUSC_WSTATE0_ABOVE    (AC_STATUSC_WSTATE0_ABOVE_Val  << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_INSIDE   (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_BELOW    (AC_STATUSC_WSTATE0_BELOW_Val  << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_MASK             0x33ul       /**< \brief (AC_STATUSC) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W  8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WEN0:1;           /*!< bit:      0  Window 0 Mode Enable               */
+    uint8_t  WINTSEL0:2;       /*!< bit:  1.. 2  Window 0 Interrupt Selection       */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET           0x0C         /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE       0x00ul       /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0             (0x1ul << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk     (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value)  ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))
+#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   0x0ul  /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  0x1ul  /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define   AC_WINCTRL_WINTSEL0_BELOW_Val   0x2ul  /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul  /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK             0x07ul       /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ENABLE:1;         /*!< bit:      0  Enable                             */
+    uint32_t SINGLE:1;         /*!< bit:      1  Single-Shot Mode                   */
+    uint32_t SPEED:2;          /*!< bit:  2.. 3  Speed Selection                    */
+    uint32_t :1;               /*!< bit:      4  Reserved                           */
+    uint32_t INTSEL:2;         /*!< bit:  5.. 6  Interrupt Selection                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MUXNEG:3;         /*!< bit:  8..10  Negative Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t MUXPOS:2;         /*!< bit: 12..13  Positive Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     14  Reserved                           */
+    uint32_t SWAP:1;           /*!< bit:     15  Swap Inputs and Invert             */
+    uint32_t OUT:2;            /*!< bit: 16..17  Output                             */
+    uint32_t :1;               /*!< bit:     18  Reserved                           */
+    uint32_t HYST:1;           /*!< bit:     19  Hysteresis Enable                  */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t FLEN:3;           /*!< bit: 24..26  Filter Length                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE      0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos      0            /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE          (0x1ul << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos      1            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE          (0x1ul << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SPEED_Pos       2            /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk       (0x3ul << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value)    ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))
+#define   AC_COMPCTRL_SPEED_LOW_Val       0x0ul  /**< \brief (AC_COMPCTRL) Low speed */
+#define   AC_COMPCTRL_SPEED_HIGH_Val      0x1ul  /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW       (AC_COMPCTRL_SPEED_LOW_Val     << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_INTSEL_Pos      5            /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk      (0x3ul << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value)   ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))
+#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   0x0ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define   AC_COMPCTRL_INTSEL_RISING_Val   0x1ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define   AC_COMPCTRL_INTSEL_FALLING_Val  0x2ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define   AC_COMPCTRL_INTSEL_EOC_Val      0x3ul  /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk      (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value)   ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))
+#define   AC_COMPCTRL_MUXNEG_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXNEG_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXNEG_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXNEG_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXNEG_GND_Val      0x4ul  /**< \brief (AC_COMPCTRL) Ground */
+#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   0x5ul  /**< \brief (AC_COMPCTRL) VDD scaler */
+#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  0x6ul  /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define   AC_COMPCTRL_MUXNEG_DAC_Val      0x7ul  /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3     (AC_COMPCTRL_MUXNEG_PIN3_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND      (AC_COMPCTRL_MUXNEG_GND_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE   (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk      (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value)   ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))
+#define   AC_COMPCTRL_MUXPOS_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXPOS_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXPOS_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXPOS_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP            (0x1ul << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_OUT_Pos         16           /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk         (0x3ul << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value)      ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))
+#define   AC_COMPCTRL_OUT_OFF_Val         0x0ul  /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_ASYNC_Val       0x1ul  /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_SYNC_Val        0x2ul  /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_HYST_Pos        19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYST            (0x1ul << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk        (0x7ul << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value)     ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))
+#define   AC_COMPCTRL_FLEN_OFF_Val        0x0ul  /**< \brief (AC_COMPCTRL) No filtering */
+#define   AC_COMPCTRL_FLEN_MAJ3_Val       0x1ul  /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define   AC_COMPCTRL_FLEN_MAJ5_Val       0x2ul  /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_MASK            0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W  8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:6;          /*!< bit:  0.. 5  Scaler Value                       */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET            0x20         /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE        0x00ul       /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk         (0x3Ful << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value)      ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))
+#define AC_SCALER_MASK              0x3Ful       /**< \brief (AC_SCALER) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO AC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __O  AC_CTRLB_Type             CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B */
+  __IO AC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x02 (R/W 16) Event Control */
+  __IO AC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO AC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO AC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __I  AC_STATUSA_Type           STATUSA;     /**< \brief Offset: 0x08 (R/   8) Status A */
+  __I  AC_STATUSB_Type           STATUSB;     /**< \brief Offset: 0x09 (R/   8) Status B */
+  __I  AC_STATUSC_Type           STATUSC;     /**< \brief Offset: 0x0A (R/   8) Status C */
+       RoReg8                    Reserved2[0x1];
+  __IO AC_WINCTRL_Type           WINCTRL;     /**< \brief Offset: 0x0C (R/W  8) Window Control */
+       RoReg8                    Reserved3[0x3];
+  __IO AC_COMPCTRL_Type          COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+       RoReg8                    Reserved4[0x8];
+  __IO AC_SCALER_Type            SCALER[2];   /**< \brief Offset: 0x20 (R/W  8) Scaler n */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_AC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/adc.h
new file mode 100644
index 0000000000..1c65643bb8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/adc.h
@@ -0,0 +1,702 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_ADC_COMPONENT_
+#define _SAMD20_ADC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMD20_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2204
+#define REV_ADC                     0x111
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE        0x00ul       /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST             (0x1ul << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE            (0x1ul << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY          (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK              0x07ul       /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W  8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  REFSEL:4;         /*!< bit:  0.. 3  Reference Selection                */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  REFCOMP:1;        /*!< bit:      7  Reference Buffer Offset Compensation Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET          0x01         /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk      (0xFul << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value)   ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))
+#define   ADC_REFCTRL_REFSEL_INT1V_Val    0x0ul  /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  0x1ul  /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  0x2ul  /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define   ADC_REFCTRL_REFSEL_AREFA_Val    0x3ul  /**< \brief (ADC_REFCTRL) External reference */
+#define   ADC_REFCTRL_REFSEL_AREFB_Val    0x4ul  /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_INT1V    (ADC_REFCTRL_REFSEL_INT1V_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP         (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK            0x8Ful       /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W  8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLENUM:4;      /*!< bit:  0.. 3  Number of Samples to be Collected  */
+    uint8_t  ADJRES:3;         /*!< bit:  4.. 6  Adjusting Result / Division Coefficient */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET          0x02         /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk   (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))
+#define   ADC_AVGCTRL_SAMPLENUM_1_Val     0x0ul  /**< \brief (ADC_AVGCTRL) 1 sample */
+#define   ADC_AVGCTRL_SAMPLENUM_2_Val     0x1ul  /**< \brief (ADC_AVGCTRL) 2 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_4_Val     0x2ul  /**< \brief (ADC_AVGCTRL) 4 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_8_Val     0x3ul  /**< \brief (ADC_AVGCTRL) 8 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_16_Val    0x4ul  /**< \brief (ADC_AVGCTRL) 16 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_32_Val    0x5ul  /**< \brief (ADC_AVGCTRL) 32 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_64_Val    0x6ul  /**< \brief (ADC_AVGCTRL) 64 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_128_Val   0x7ul  /**< \brief (ADC_AVGCTRL) 128 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_256_Val   0x8ul  /**< \brief (ADC_AVGCTRL) 256 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_512_Val   0x9ul  /**< \brief (ADC_AVGCTRL) 512 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  0xAul  /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk      (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value)   ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))
+#define ADC_AVGCTRL_MASK            0x7Ful       /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W  8) Sampling Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLEN:6;        /*!< bit:  0.. 5  Sampling Time Length               */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET         0x03         /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE     0x00ul       /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk    (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))
+#define ADC_SAMPCTRL_MASK           0x3Ful       /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DIFFMODE:1;       /*!< bit:      0  Differential Mode                  */
+    uint16_t LEFTADJ:1;        /*!< bit:      1  Left Adjusted Result               */
+    uint16_t FREERUN:1;        /*!< bit:      2  Free Running Mode                  */
+    uint16_t CORREN:1;         /*!< bit:      3  Digital Correction Logic Enabled   */
+    uint16_t RESSEL:2;         /*!< bit:  4.. 5  Conversion Result Resolution       */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler Configuration            */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET            0x04         /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE        0x0000ul     /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_DIFFMODE_Pos      0            /**< \brief (ADC_CTRLB) Differential Mode */
+#define ADC_CTRLB_DIFFMODE          (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_LEFTADJ_Pos       1            /**< \brief (ADC_CTRLB) Left Adjusted Result */
+#define ADC_CTRLB_LEFTADJ           (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos       2            /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN           (0x1ul << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos        3            /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
+#define ADC_CTRLB_CORREN            (0x1ul << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos        4            /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk        (0x3ul << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value)     ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))
+#define   ADC_CTRLB_RESSEL_12BIT_Val      0x0ul  /**< \brief (ADC_CTRLB) 12-bit result */
+#define   ADC_CTRLB_RESSEL_16BIT_Val      0x1ul  /**< \brief (ADC_CTRLB) For averaging mode output */
+#define   ADC_CTRLB_RESSEL_10BIT_Val      0x2ul  /**< \brief (ADC_CTRLB) 10-bit result */
+#define   ADC_CTRLB_RESSEL_8BIT_Val       0x3ul  /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_PRESCALER_Pos     8            /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk     (0x7ul << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value)  ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))
+#define   ADC_CTRLB_PRESCALER_DIV4_Val    0x0ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define   ADC_CTRLB_PRESCALER_DIV8_Val    0x1ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define   ADC_CTRLB_PRESCALER_DIV16_Val   0x2ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define   ADC_CTRLB_PRESCALER_DIV32_Val   0x3ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define   ADC_CTRLB_PRESCALER_DIV64_Val   0x4ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define   ADC_CTRLB_PRESCALER_DIV128_Val  0x5ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define   ADC_CTRLB_PRESCALER_DIV256_Val  0x6ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define   ADC_CTRLB_PRESCALER_DIV512_Val  0x7ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define ADC_CTRLB_PRESCALER_DIV4    (ADC_CTRLB_PRESCALER_DIV4_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8    (ADC_CTRLB_PRESCALER_DIV8_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16   (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32   (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64   (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128  (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256  (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV512  (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK              0x073Ful     /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W  8) Window Monitor Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WINMODE:3;        /*!< bit:  0.. 2  Window Monitor Mode                */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINCTRL_OFFSET          0x08         /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+
+#define ADC_WINCTRL_WINMODE_Pos     0            /**< \brief (ADC_WINCTRL) Window Monitor Mode */
+#define ADC_WINCTRL_WINMODE_Msk     (0x7ul << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE(value)  ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))
+#define   ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul  /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define   ADC_WINCTRL_WINMODE_MODE1_Val   0x1ul  /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define   ADC_WINCTRL_WINMODE_MODE2_Val   0x2ul  /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE3_Val   0x3ul  /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE4_Val   0x4ul  /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE1   (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE2   (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE3   (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE4   (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_MASK            0x07ul       /**< \brief (ADC_WINCTRL) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W  8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLUSH:1;          /*!< bit:      0  ADC Conversion Flush               */
+    uint8_t  START:1;          /*!< bit:      1  ADC Start Conversion               */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET           0x0C         /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE       0x00ul       /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH            (0x1ul << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) ADC Start Conversion */
+#define ADC_SWTRIG_START            (0x1ul << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK             0x03ul       /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Inputs Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUXPOS:5;         /*!< bit:  0.. 4  Positive MUX Input Selection       */
+    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint32_t MUXNEG:5;         /*!< bit:  8..12  Negative MUX Input Selection       */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t INPUTSCAN:4;      /*!< bit: 16..19  Number of Input Channels Included in Scan */
+    uint32_t INPUTOFFSET:4;    /*!< bit: 20..23  Positive MUX Setting Offset        */
+    uint32_t GAIN:4;           /*!< bit: 24..27  Gain Factor Selection              */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET        0x10         /**< \brief (ADC_INPUTCTRL offset) Inputs Control */
+#define ADC_INPUTCTRL_RESETVALUE    0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Inputs Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive MUX Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk    (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))
+#define   ADC_INPUTCTRL_MUXPOS_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN8_Val   0x8ul  /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN9_Val   0x9ul  /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN10_Val  0xAul  /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN11_Val  0xBul  /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN12_Val  0xCul  /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN13_Val  0xDul  /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN14_Val  0xEul  /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN15_Val  0xFul  /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN16_Val  0x10ul  /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN17_Val  0x11ul  /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN18_Val  0x12ul  /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN19_Val  0x13ul  /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_TEMP_Val   0x18ul  /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul  /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled Core Supply */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled I/O Supply */
+#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    0x1Cul  /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PIN0   (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN1   (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN2   (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN3   (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN4   (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN5   (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN6   (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN7   (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN8   (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN9   (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN10  (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN11  (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN12  (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN13  (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN14  (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN15  (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN16  (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN17  (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN18  (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN19  (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP   (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative MUX Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk    (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))
+#define   ADC_INPUTCTRL_MUXNEG_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_GND_Val    0x18ul  /**< \brief (ADC_INPUTCTRL) Internal ground */
+#define   ADC_INPUTCTRL_MUXNEG_IOGND_Val  0x19ul  /**< \brief (ADC_INPUTCTRL) IO ground */
+#define ADC_INPUTCTRL_MUXNEG_PIN0   (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN1   (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN2   (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN3   (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN4   (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN5   (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN6   (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN7   (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_IOGND  (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16           /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20           /**< \brief (ADC_INPUTCTRL) Positive MUX Setting Offset */
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
+#define ADC_INPUTCTRL_GAIN_Pos      24           /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
+#define ADC_INPUTCTRL_GAIN_Msk      (0xFul << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN(value)   ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))
+#define   ADC_INPUTCTRL_GAIN_1X_Val       0x0ul  /**< \brief (ADC_INPUTCTRL) 1x */
+#define   ADC_INPUTCTRL_GAIN_2X_Val       0x1ul  /**< \brief (ADC_INPUTCTRL) 2x */
+#define   ADC_INPUTCTRL_GAIN_4X_Val       0x2ul  /**< \brief (ADC_INPUTCTRL) 4x */
+#define   ADC_INPUTCTRL_GAIN_8X_Val       0x3ul  /**< \brief (ADC_INPUTCTRL) 8x */
+#define   ADC_INPUTCTRL_GAIN_16X_Val      0x4ul  /**< \brief (ADC_INPUTCTRL) 16x */
+#define   ADC_INPUTCTRL_GAIN_DIV2_Val     0xFul  /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define ADC_INPUTCTRL_GAIN_1X       (ADC_INPUTCTRL_GAIN_1X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_2X       (ADC_INPUTCTRL_GAIN_2X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_4X       (ADC_INPUTCTRL_GAIN_4X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_8X       (ADC_INPUTCTRL_GAIN_8X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_16X      (ADC_INPUTCTRL_GAIN_16X_Val    << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_DIV2     (ADC_INPUTCTRL_GAIN_DIV2_Val   << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_MASK          0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event In          */
+    uint8_t  SYNCEI:1;         /*!< bit:      1  Synchronization Event In           */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  RESRDYEO:1;       /*!< bit:      4  Result Ready Event Out             */
+    uint8_t  WINMONEO:1;       /*!< bit:      5  Window Monitor Event Out           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET           0x14         /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_STARTEI_Pos      0            /**< \brief (ADC_EVCTRL) Start Conversion Event In */
+#define ADC_EVCTRL_STARTEI          (0x1ul << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_SYNCEI_Pos       1            /**< \brief (ADC_EVCTRL) Synchronization Event In */
+#define ADC_EVCTRL_SYNCEI           (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO         (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO         (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK             0x33ul       /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET         0x16         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
+#define ADC_INTENCLR_RESRDY         (0x1ul << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
+#define ADC_INTENCLR_OVERRUN        (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
+#define ADC_INTENCLR_WINMON         (0x1ul << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_SYNCRDY_Pos    3            /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define ADC_INTENCLR_SYNCRDY        (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK           0x0Ful       /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET         0x17         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE     0x00ul       /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY         (0x1ul << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN        (0x1ul << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON         (0x1ul << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_SYNCRDY_Pos    3            /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
+#define ADC_INTENSET_SYNCRDY        (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK           0x0Ful       /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready                       */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun                            */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor                     */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET          0x18         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready */
+#define ADC_INTFLAG_RESRDY          (0x1ul << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun */
+#define ADC_INTFLAG_OVERRUN         (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor */
+#define ADC_INTFLAG_WINMON          (0x1ul << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_SYNCRDY_Pos     3            /**< \brief (ADC_INTFLAG) Synchronization Ready */
+#define ADC_INTFLAG_SYNCRDY         (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK            0x0Ful       /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET           0x19         /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE       0x00ul       /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_SYNCBUSY_Pos     7            /**< \brief (ADC_STATUS) Synchronization Busy */
+#define ADC_STATUS_SYNCBUSY         (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK             0x80ul       /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/  16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESULT:16;        /*!< bit:  0..15  Result Conversion Value            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET           0x1A         /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE       0x0000ul     /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk       (0xFFFFul << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value)    ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))
+#define ADC_RESULT_MASK             0xFFFFul     /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINLT:16;         /*!< bit:  0..15  Window Lower Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET            0x1C         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk         (0xFFFFul << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value)      ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))
+#define ADC_WINLT_MASK              0xFFFFul     /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINUT:16;         /*!< bit:  0..15  Window Upper Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET            0x20         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk         (0xFFFFul << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value)      ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))
+#define ADC_WINUT_MASK              0xFFFFul     /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GAINCORR:12;      /*!< bit:  0..11  Gain Correction Value              */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET         0x24         /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE     0x0000ul     /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk   (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))
+#define ADC_GAINCORR_MASK           0x0FFFul     /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t OFFSETCORR:12;    /*!< bit:  0..11  Offset Correction Value            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET       0x26         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE   0x0000ul     /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))
+#define ADC_OFFSETCORR_MASK         0x0FFFul     /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LINEARITY_CAL:8;  /*!< bit:  0.. 7  Linearity Calibration Value        */
+    uint16_t BIAS_CAL:3;       /*!< bit:  8..10  Bias Calibration Value             */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET            0x28         /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE        0x0000ul     /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_LINEARITY_CAL_Pos 0            /**< \brief (ADC_CALIB) Linearity Calibration Value */
+#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))
+#define ADC_CALIB_BIAS_CAL_Pos      8            /**< \brief (ADC_CALIB) Bias Calibration Value */
+#define ADC_CALIB_BIAS_CAL_Msk      (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL(value)   ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))
+#define ADC_CALIB_MASK              0x07FFul     /**< \brief (ADC_CALIB) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET          0x2A         /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN          (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK            0x01ul       /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO ADC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO ADC_REFCTRL_Type          REFCTRL;     /**< \brief Offset: 0x01 (R/W  8) Reference Control */
+  __IO ADC_AVGCTRL_Type          AVGCTRL;     /**< \brief Offset: 0x02 (R/W  8) Average Control */
+  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    /**< \brief Offset: 0x03 (R/W  8) Sampling Time Control */
+  __IO ADC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W 16) Control B */
+       RoReg8                    Reserved1[0x2];
+  __IO ADC_WINCTRL_Type          WINCTRL;     /**< \brief Offset: 0x08 (R/W  8) Window Monitor Control */
+       RoReg8                    Reserved2[0x3];
+  __IO ADC_SWTRIG_Type           SWTRIG;      /**< \brief Offset: 0x0C (R/W  8) Software Trigger */
+       RoReg8                    Reserved3[0x3];
+  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   /**< \brief Offset: 0x10 (R/W 32) Inputs Control */
+  __IO ADC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x14 (R/W  8) Event Control */
+       RoReg8                    Reserved4[0x1];
+  __IO ADC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x16 (R/W  8) Interrupt Enable Clear */
+  __IO ADC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x17 (R/W  8) Interrupt Enable Set */
+  __IO ADC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) Interrupt Flag Status and Clear */
+  __I  ADC_STATUS_Type           STATUS;      /**< \brief Offset: 0x19 (R/   8) Status */
+  __I  ADC_RESULT_Type           RESULT;      /**< \brief Offset: 0x1A (R/  16) Result */
+  __IO ADC_WINLT_Type            WINLT;       /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+       RoReg8                    Reserved5[0x2];
+  __IO ADC_WINUT_Type            WINUT;       /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+       RoReg8                    Reserved6[0x2];
+  __IO ADC_GAINCORR_Type         GAINCORR;    /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+  __IO ADC_CALIB_Type            CALIB;       /**< \brief Offset: 0x28 (R/W 16) Calibration */
+  __IO ADC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x2A (R/W  8) Debug Control */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_ADC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/dac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/dac.h
new file mode 100644
index 0000000000..dd446c6989
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/dac.h
@@ -0,0 +1,286 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_DAC_COMPONENT_
+#define _SAMD20_DAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMD20_DAC Digital Analog Converter */
+/*@{*/
+
+#define DAC_U2214
+#define REV_DAC                     0x101
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET            0x0          /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST             (0x1ul << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable */
+#define DAC_CTRLA_ENABLE            (0x1ul << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (DAC_CTRLA) Run in Standby */
+#define DAC_CTRLA_RUNSTDBY          (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK              0x07ul       /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EOEN:1;           /*!< bit:      0  External Output Enable             */
+    uint8_t  IOEN:1;           /*!< bit:      1  Internal Output Enable             */
+    uint8_t  LEFTADJ:1;        /*!< bit:      2  Left Adjusted Data                 */
+    uint8_t  VPD:1;            /*!< bit:      3  Voltage Pump Disable               */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  REFSEL:2;         /*!< bit:  6.. 7  Reference Selection                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET            0x1          /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_EOEN_Pos          0            /**< \brief (DAC_CTRLB) External Output Enable */
+#define DAC_CTRLB_EOEN              (0x1ul << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_IOEN_Pos          1            /**< \brief (DAC_CTRLB) Internal Output Enable */
+#define DAC_CTRLB_IOEN              (0x1ul << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_LEFTADJ_Pos       2            /**< \brief (DAC_CTRLB) Left Adjusted Data */
+#define DAC_CTRLB_LEFTADJ           (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_VPD_Pos           3            /**< \brief (DAC_CTRLB) Voltage Pump Disable */
+#define DAC_CTRLB_VPD               (0x1ul << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_REFSEL_Pos        6            /**< \brief (DAC_CTRLB) Reference Selection */
+#define DAC_CTRLB_REFSEL_Msk        (0x3ul << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value)     ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
+#define   DAC_CTRLB_REFSEL_INT1V_Val      0x0ul  /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define   DAC_CTRLB_REFSEL_AVCC_Val       0x1ul  /**< \brief (DAC_CTRLB) AVCC */
+#define   DAC_CTRLB_REFSEL_VREFP_Val      0x2ul  /**< \brief (DAC_CTRLB) External reference */
+#define DAC_CTRLB_REFSEL_INT1V      (DAC_CTRLB_REFSEL_INT1V_Val    << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_AVCC       (DAC_CTRLB_REFSEL_AVCC_Val     << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFP      (DAC_CTRLB_REFSEL_VREFP_Val    << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK              0xCFul       /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event Input       */
+    uint8_t  EMPTYEO:1;        /*!< bit:      1  Data Buffer Empty Event Output     */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET           0x2          /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
+#define DAC_EVCTRL_STARTEI          (0x1ul << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos      1            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
+#define DAC_EVCTRL_EMPTYEO          (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK             0x03ul       /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET         0x4          /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN       (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_EMPTY_Pos      1            /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY          (0x1ul << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_SYNCRDY_Pos    2            /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define DAC_INTENCLR_SYNCRDY        (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK           0x07ul       /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET         0x5          /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE     0x00ul       /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN       (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_EMPTY_Pos      1            /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY          (0x1ul << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_SYNCRDY_Pos    2            /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
+#define DAC_INTENSET_SYNCRDY        (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK           0x07ul       /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun                           */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty                  */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready              */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET          0x6          /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) Underrun */
+#define DAC_INTFLAG_UNDERRUN        (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_EMPTY_Pos       1            /**< \brief (DAC_INTFLAG) Data Buffer Empty */
+#define DAC_INTFLAG_EMPTY           (0x1ul << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_SYNCRDY_Pos     2            /**< \brief (DAC_INTFLAG) Synchronization Ready */
+#define DAC_INTFLAG_SYNCRDY         (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK            0x07ul       /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET           0x7          /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE       0x00ul       /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_SYNCBUSY_Pos     7            /**< \brief (DAC_STATUS) Synchronization Busy Status */
+#define DAC_STATUS_SYNCBUSY         (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK             0x80ul       /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:16;          /*!< bit:  0..15  Data to be converted               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET             0x8          /**< \brief (DAC_DATA offset) Data */
+#define DAC_DATA_RESETVALUE         0x0000ul     /**< \brief (DAC_DATA reset_value) Data */
+
+#define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) Data to be converted */
+#define DAC_DATA_DATA_Msk           (0xFFFFul << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value)        ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
+#define DAC_DATA_MASK               0xFFFFul     /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATABUF:16;       /*!< bit:  0..15  Data Buffer                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET          0xC          /**< \brief (DAC_DATABUF offset) Data Buffer */
+#define DAC_DATABUF_RESETVALUE      0x0000ul     /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk     (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value)  ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
+#define DAC_DATABUF_MASK            0xFFFFul     /**< \brief (DAC_DATABUF) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DAC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x0 (R/W  8) Control A */
+  __IO DAC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x1 (R/W  8) Control B */
+  __IO DAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x2 (R/W  8) Event Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO DAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO DAC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+  __I  DAC_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
+  __IO DAC_DATA_Type             DATA;        /**< \brief Offset: 0x8 (R/W 16) Data */
+       RoReg8                    Reserved2[0x2];
+  __IO DAC_DATABUF_Type          DATABUF;     /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_DAC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/dsu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/dsu.h
new file mode 100644
index 0000000000..cc33e81014
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/dsu.h
@@ -0,0 +1,631 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_DSU_COMPONENT_
+#define _SAMD20_DSU_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAMD20_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2209
+#define REV_DSU                     0x103
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CRC:1;            /*!< bit:      2  32-bit Cyclic Redundancy Code      */
+    uint8_t  MBIST:1;          /*!< bit:      3  Memory built-in self-test          */
+    uint8_t  CE:1;             /*!< bit:      4  Chip-Erase                         */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  ARR:1;            /*!< bit:      6  Auxiliary Row Read                 */
+    uint8_t  SMSA:1;           /*!< bit:      7  Start Memory Stream Access         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE         0x00ul       /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST              (0x1ul << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */
+#define DSU_CTRL_CRC                (0x1ul << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory built-in self-test */
+#define DSU_CTRL_MBIST              (0x1ul << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip-Erase */
+#define DSU_CTRL_CE                 (0x1ul << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_ARR_Pos            6            /**< \brief (DSU_CTRL) Auxiliary Row Read */
+#define DSU_CTRL_ARR                (0x1ul << DSU_CTRL_ARR_Pos)
+#define DSU_CTRL_SMSA_Pos           7            /**< \brief (DSU_CTRL) Start Memory Stream Access */
+#define DSU_CTRL_SMSA               (0x1ul << DSU_CTRL_SMSA_Pos)
+#define DSU_CTRL_MASK               0xDDul       /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DONE:1;           /*!< bit:      0  Done                               */
+    uint8_t  CRSTEXT:1;        /*!< bit:      1  CPU Reset Phase Extension          */
+    uint8_t  BERR:1;           /*!< bit:      2  Bus Error                          */
+    uint8_t  FAIL:1;           /*!< bit:      3  Failure                            */
+    uint8_t  PERR:1;           /*!< bit:      4  Protection Error                   */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE      0x00ul       /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE            (0x1ul << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT         (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR            (0x1ul << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL            (0x1ul << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR            (0x1ul << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK            0x1Ful       /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PROT:1;           /*!< bit:      0  Protected                          */
+    uint8_t  DBGPRES:1;        /*!< bit:      1  Debugger Present                   */
+    uint8_t  DCCD0:1;          /*!< bit:      2  Debug Communication Channel 0 Dirty */
+    uint8_t  DCCD1:1;          /*!< bit:      3  Debug Communication Channel 1 Dirty */
+    uint8_t  HPE:1;            /*!< bit:      4  Hot-Plugging Enable                */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  DCCD:2;           /*!< bit:  2.. 3  Debug Communication Channel x Dirty */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE      0x00ul       /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT            (0x1ul << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES         (0x1ul << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0           (1 << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1           (1 << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk        (0x3ul << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value)     ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
+#define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE             (0x1ul << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK            0x1Ful       /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t AMOD:2;           /*!< bit:  0.. 1  Access Mode                        */
+    uint32_t ADDR:30;          /*!< bit:  2..31  Address                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE         0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_AMOD_Pos           0            /**< \brief (DSU_ADDR) Access Mode */
+#define DSU_ADDR_AMOD_Msk           (0x3ul << DSU_ADDR_AMOD_Pos)
+#define DSU_ADDR_AMOD(value)        ((DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos)))
+#define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk           (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value)        ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
+#define DSU_ADDR_MASK               0xFFFFFFFFul /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t LENGTH:30;        /*!< bit:  2..31  Length                             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE       0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk       (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value)    ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
+#define DSU_LENGTH_MASK             0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE         0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk           (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value)        ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
+#define DSU_DATA_MASK               0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE          0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk            (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value)         ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
+#define DSU_DCC_MASK                0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DEVSEL:8;         /*!< bit:  0.. 7  Device Select                      */
+    uint32_t REVISION:4;       /*!< bit:  8..11  Revision Number                    */
+    uint32_t DIE:4;            /*!< bit: 12..15  Die Number                         */
+    uint32_t SERIES:6;         /*!< bit: 16..21  Series                             */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t FAMILY:5;         /*!< bit: 23..27  Family                             */
+    uint32_t PROCESSOR:4;      /*!< bit: 28..31  Processor                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk          (0xFFul << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value)       ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
+#define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision Number */
+#define DSU_DID_REVISION_Msk        (0xFul << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value)     ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
+#define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Number */
+#define DSU_DID_DIE_Msk             (0xFul << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value)          ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
+#define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Series */
+#define DSU_DID_SERIES_Msk          (0x3Ful << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value)       ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
+#define   DSU_DID_SERIES_0_Val            0x0ul  /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */
+#define   DSU_DID_SERIES_1_Val            0x1ul  /**< \brief (DSU_DID) Cortex-M0+ processor, USB */
+#define DSU_DID_SERIES_0            (DSU_DID_SERIES_0_Val          << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES_1            (DSU_DID_SERIES_1_Val          << DSU_DID_SERIES_Pos)
+#define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Family */
+#define DSU_DID_FAMILY_Msk          (0x1Ful << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value)       ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
+#define   DSU_DID_FAMILY_0_Val            0x0ul  /**< \brief (DSU_DID) General purpose microcontroller */
+#define   DSU_DID_FAMILY_1_Val            0x1ul  /**< \brief (DSU_DID) PicoPower */
+#define DSU_DID_FAMILY_0            (DSU_DID_FAMILY_0_Val          << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY_1            (DSU_DID_FAMILY_1_Val          << DSU_DID_FAMILY_Pos)
+#define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk       (0xFul << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value)    ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
+#define   DSU_DID_PROCESSOR_0_Val         0x0ul  /**< \brief (DSU_DID) Cortex-M0 */
+#define   DSU_DID_PROCESSOR_1_Val         0x1ul  /**< \brief (DSU_DID) Cortex-M0+ */
+#define   DSU_DID_PROCESSOR_2_Val         0x2ul  /**< \brief (DSU_DID) Cortex-M3 */
+#define   DSU_DID_PROCESSOR_3_Val         0x3ul  /**< \brief (DSU_DID) Cortex-M4 */
+#define DSU_DID_PROCESSOR_0         (DSU_DID_PROCESSOR_0_Val       << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_1         (DSU_DID_PROCESSOR_1_Val       << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_2         (DSU_DID_PROCESSOR_2_Val       << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_3         (DSU_DID_PROCESSOR_3_Val       << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_MASK                0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DCFG:32;          /*!< bit:  0..31  Device Configuration               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCFG_OFFSET             0x00F0       /**< \brief (DSU_DCFG offset) Device Configuration */
+#define DSU_DCFG_RESETVALUE         0x00000000ul /**< \brief (DSU_DCFG reset_value) Device Configuration */
+
+#define DSU_DCFG_DCFG_Pos           0            /**< \brief (DSU_DCFG) Device Configuration */
+#define DSU_DCFG_DCFG_Msk           (0xFFFFFFFFul << DSU_DCFG_DCFG_Pos)
+#define DSU_DCFG_DCFG(value)        ((DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos)))
+#define DSU_DCFG_MASK               0xFFFFFFFFul /**< \brief (DSU_DCFG) MASK Register */
+
+/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/  32) Coresight ROM Table Entry n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EPRES:1;          /*!< bit:      0  Entry Present                      */
+    uint32_t FMT:1;            /*!< bit:      1  Format                             */
+    uint32_t :10;              /*!< bit:  2..11  Reserved                           */
+    uint32_t ADDOFF:20;        /*!< bit: 12..31  Address Offset                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ENTRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY_OFFSET            0x1000       /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
+#define DSU_ENTRY_RESETVALUE        0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
+
+#define DSU_ENTRY_EPRES_Pos         0            /**< \brief (DSU_ENTRY) Entry Present */
+#define DSU_ENTRY_EPRES             (0x1ul << DSU_ENTRY_EPRES_Pos)
+#define DSU_ENTRY_FMT_Pos           1            /**< \brief (DSU_ENTRY) Format */
+#define DSU_ENTRY_FMT               (0x1ul << DSU_ENTRY_FMT_Pos)
+#define DSU_ENTRY_ADDOFF_Pos        12           /**< \brief (DSU_ENTRY) Address Offset */
+#define DSU_ENTRY_ADDOFF_Msk        (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
+#define DSU_ENTRY_ADDOFF(value)     ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
+#define DSU_ENTRY_MASK              0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) Coresight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t END:32;           /*!< bit:  0..31  End Marker                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) Coresight ROM Table End */
+#define DSU_END_RESETVALUE          0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+
+#define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk             (0xFFFFFFFFul << DSU_END_END_Pos)
+#define DSU_END_END(value)          ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
+#define DSU_END_MASK                0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) Coresight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SMEMP:1;          /*!< bit:      0  System Memory Present              */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE      0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP           (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK            0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPCC:4;          /*!< bit:  0.. 3  JEP-106 Continuation Code          */
+    uint32_t FKBC:4;           /*!< bit:  4.. 7  4KB count                          */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE         0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk          (0xFul << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value)       ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
+#define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB count */
+#define DSU_PID4_FKBC_Msk           (0xFul << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value)        ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
+#define DSU_PID4_MASK               0x000000FFul /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/  32) Peripheral Identification 5 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID5_OFFSET             0x1FD4       /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */
+#define DSU_PID5_MASK               0x00000000ul /**< \brief (DSU_PID5) MASK Register */
+
+/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/  32) Peripheral Identification 6 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID6_OFFSET             0x1FD8       /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */
+#define DSU_PID6_MASK               0x00000000ul /**< \brief (DSU_PID6) MASK Register */
+
+/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/  32) Peripheral Identification 7 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID7_OFFSET             0x1FDC       /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */
+#define DSU_PID7_MASK               0x00000000ul /**< \brief (DSU_PID7) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBL:8;        /*!< bit:  0.. 7  Part Number Low                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE         0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk        (0xFFul << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value)     ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
+#define DSU_PID0_MASK               0x000000FFul /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBH:4;        /*!< bit:  0.. 3  Part Number High                   */
+    uint32_t JEPIDCL:4;        /*!< bit:  4.. 7  Low part of the JEP-106 Identity Code */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE         0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk        (0xFul << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value)     ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
+#define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk        (0xFul << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value)     ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
+#define DSU_PID1_MASK               0x000000FFul /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPIDCH:3;        /*!< bit:  0.. 2  JEP-106 Identity Code High         */
+    uint32_t JEPU:1;           /*!< bit:      3  JEP-106 Identity Code is used      */
+    uint32_t REVISION:4;       /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE         0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk        (0x7ul << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value)     ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
+#define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU               (0x1ul << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk       (0xFul << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value)    ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
+#define DSU_PID2_MASK               0x000000FFul /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CUSMOD:4;         /*!< bit:  0.. 3  ARM CUSMOD                         */
+    uint32_t REVAND:4;         /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE         0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk         (0xFul << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value)      ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
+#define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk         (0xFul << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value)      ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
+#define DSU_PID3_MASK               0x000000FFul /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB0:8;     /*!< bit:  0.. 7  Preamble Byte 0                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE         0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk     (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value)  ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
+#define DSU_CID0_MASK               0x000000FFul /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLE:4;       /*!< bit:  0.. 3  Preamble                           */
+    uint32_t CCLASS:4;         /*!< bit:  4.. 7  Component Class                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE         0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk       (0xFul << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value)    ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
+#define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk         (0xFul << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value)      ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
+#define DSU_CID1_MASK               0x000000FFul /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB2:8;     /*!< bit:  0.. 7  Preamble Byte 2                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE         0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk     (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value)  ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
+#define DSU_CID2_MASK               0x000000FFul /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB3:8;     /*!< bit:  0.. 7  Preamble Byte 3                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE         0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk     (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value)  ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
+#define DSU_CID3_MASK               0x000000FFul /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  DSU_CTRL_Type             CTRL;        /**< \brief Offset: 0x0000 ( /W  8) Control */
+  __IO DSU_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x0001 (R/W  8) Status A */
+  __I  DSU_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x0002 (R/   8) Status B */
+       RoReg8                    Reserved1[0x1];
+  __IO DSU_ADDR_Type             ADDR;        /**< \brief Offset: 0x0004 (R/W 32) Address */
+  __IO DSU_LENGTH_Type           LENGTH;      /**< \brief Offset: 0x0008 (R/W 32) Length */
+  __IO DSU_DATA_Type             DATA;        /**< \brief Offset: 0x000C (R/W 32) Data */
+  __IO DSU_DCC_Type              DCC[2];      /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+  __I  DSU_DID_Type              DID;         /**< \brief Offset: 0x0018 (R/  32) Device Identification */
+       RoReg8                    Reserved2[0xD4];
+  __IO DSU_DCFG_Type             DCFG[2];     /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */
+       RoReg8                    Reserved3[0xF08];
+  __I  DSU_ENTRY_Type            ENTRY[2];    /**< \brief Offset: 0x1000 (R/  32) Coresight ROM Table Entry n */
+  __I  DSU_END_Type              END;         /**< \brief Offset: 0x1008 (R/  32) Coresight ROM Table End */
+       RoReg8                    Reserved4[0xFC0];
+  __I  DSU_MEMTYPE_Type          MEMTYPE;     /**< \brief Offset: 0x1FCC (R/  32) Coresight ROM Table Memory Type */
+  __I  DSU_PID4_Type             PID4;        /**< \brief Offset: 0x1FD0 (R/  32) Peripheral Identification 4 */
+  __I  DSU_PID5_Type             PID5;        /**< \brief Offset: 0x1FD4 (R/  32) Peripheral Identification 5 */
+  __I  DSU_PID6_Type             PID6;        /**< \brief Offset: 0x1FD8 (R/  32) Peripheral Identification 6 */
+  __I  DSU_PID7_Type             PID7;        /**< \brief Offset: 0x1FDC (R/  32) Peripheral Identification 7 */
+  __I  DSU_PID0_Type             PID0;        /**< \brief Offset: 0x1FE0 (R/  32) Peripheral Identification 0 */
+  __I  DSU_PID1_Type             PID1;        /**< \brief Offset: 0x1FE4 (R/  32) Peripheral Identification 1 */
+  __I  DSU_PID2_Type             PID2;        /**< \brief Offset: 0x1FE8 (R/  32) Peripheral Identification 2 */
+  __I  DSU_PID3_Type             PID3;        /**< \brief Offset: 0x1FEC (R/  32) Peripheral Identification 3 */
+  __I  DSU_CID0_Type             CID0;        /**< \brief Offset: 0x1FF0 (R/  32) Component Identification 0 */
+  __I  DSU_CID1_Type             CID1;        /**< \brief Offset: 0x1FF4 (R/  32) Component Identification 1 */
+  __I  DSU_CID2_Type             CID2;        /**< \brief Offset: 0x1FF8 (R/  32) Component Identification 2 */
+  __I  DSU_CID3_Type             CID3;        /**< \brief Offset: 0x1FFC (R/  32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_DSU_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/eic.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/eic.h
new file mode 100644
index 0000000000..7fe2e1ef56
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/eic.h
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_EIC_COMPONENT_
+#define _SAMD20_EIC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAMD20_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2217
+#define REV_EIC                     0x101
+
+/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRL_OFFSET             0x00         /**< \brief (EIC_CTRL offset) Control */
+#define EIC_CTRL_RESETVALUE         0x00ul       /**< \brief (EIC_CTRL reset_value) Control */
+
+#define EIC_CTRL_SWRST_Pos          0            /**< \brief (EIC_CTRL) Software Reset */
+#define EIC_CTRL_SWRST              (0x1ul << EIC_CTRL_SWRST_Pos)
+#define EIC_CTRL_ENABLE_Pos         1            /**< \brief (EIC_CTRL) Enable */
+#define EIC_CTRL_ENABLE             (0x1ul << EIC_CTRL_ENABLE_Pos)
+#define EIC_CTRL_MASK               0x03ul       /**< \brief (EIC_CTRL) MASK Register */
+
+/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_STATUS_OFFSET           0x01         /**< \brief (EIC_STATUS offset) Status */
+#define EIC_STATUS_RESETVALUE       0x00ul       /**< \brief (EIC_STATUS reset_value) Status */
+
+#define EIC_STATUS_SYNCBUSY_Pos     7            /**< \brief (EIC_STATUS) Synchronization Busy */
+#define EIC_STATUS_SYNCBUSY         (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
+#define EIC_STATUS_MASK             0x80ul       /**< \brief (EIC_STATUS) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W  8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMISENSE:3;       /*!< bit:  0.. 2  Non-Maskable Interrupt Sense       */
+    uint8_t  NMIFILTEN:1;      /*!< bit:      3  Non-Maskable Interrupt Filter Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET          0x02         /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE      0x00ul       /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
+#define EIC_NMICTRL_NMISENSE_Msk    (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)))
+#define   EIC_NMICTRL_NMISENSE_NONE_Val   0x0ul  /**< \brief (EIC_NMICTRL) No detection */
+#define   EIC_NMICTRL_NMISENSE_RISE_Val   0x1ul  /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define   EIC_NMICTRL_NMISENSE_FALL_Val   0x2ul  /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define   EIC_NMICTRL_NMISENSE_BOTH_Val   0x3ul  /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define   EIC_NMICTRL_NMISENSE_HIGH_Val   0x4ul  /**< \brief (EIC_NMICTRL) High-level detection */
+#define   EIC_NMICTRL_NMISENSE_LOW_Val    0x5ul  /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH   (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN       (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_MASK            0x0Ful       /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W  8) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMI:1;            /*!< bit:      0  Non-Maskable Interrupt             */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET          0x03         /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE      0x00ul       /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI             (0x1ul << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK            0x01ul       /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINTEO0:1;      /*!< bit:      0  External Interrupt 0 Event Output Enable */
+    uint32_t EXTINTEO1:1;      /*!< bit:      1  External Interrupt 1 Event Output Enable */
+    uint32_t EXTINTEO2:1;      /*!< bit:      2  External Interrupt 2 Event Output Enable */
+    uint32_t EXTINTEO3:1;      /*!< bit:      3  External Interrupt 3 Event Output Enable */
+    uint32_t EXTINTEO4:1;      /*!< bit:      4  External Interrupt 4 Event Output Enable */
+    uint32_t EXTINTEO5:1;      /*!< bit:      5  External Interrupt 5 Event Output Enable */
+    uint32_t EXTINTEO6:1;      /*!< bit:      6  External Interrupt 6 Event Output Enable */
+    uint32_t EXTINTEO7:1;      /*!< bit:      7  External Interrupt 7 Event Output Enable */
+    uint32_t EXTINTEO8:1;      /*!< bit:      8  External Interrupt 8 Event Output Enable */
+    uint32_t EXTINTEO9:1;      /*!< bit:      9  External Interrupt 9 Event Output Enable */
+    uint32_t EXTINTEO10:1;     /*!< bit:     10  External Interrupt 10 Event Output Enable */
+    uint32_t EXTINTEO11:1;     /*!< bit:     11  External Interrupt 11 Event Output Enable */
+    uint32_t EXTINTEO12:1;     /*!< bit:     12  External Interrupt 12 Event Output Enable */
+    uint32_t EXTINTEO13:1;     /*!< bit:     13  External Interrupt 13 Event Output Enable */
+    uint32_t EXTINTEO14:1;     /*!< bit:     14  External Interrupt 14 Event Output Enable */
+    uint32_t EXTINTEO15:1;     /*!< bit:     15  External Interrupt 15 Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINTEO:16;      /*!< bit:  0..15  External Interrupt x Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET           0x04         /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO0_Pos    0            /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO0        (1 << EIC_EVCTRL_EXTINTEO0_Pos)
+#define EIC_EVCTRL_EXTINTEO1_Pos    1            /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO1        (1 << EIC_EVCTRL_EXTINTEO1_Pos)
+#define EIC_EVCTRL_EXTINTEO2_Pos    2            /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO2        (1 << EIC_EVCTRL_EXTINTEO2_Pos)
+#define EIC_EVCTRL_EXTINTEO3_Pos    3            /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO3        (1 << EIC_EVCTRL_EXTINTEO3_Pos)
+#define EIC_EVCTRL_EXTINTEO4_Pos    4            /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO4        (1 << EIC_EVCTRL_EXTINTEO4_Pos)
+#define EIC_EVCTRL_EXTINTEO5_Pos    5            /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO5        (1 << EIC_EVCTRL_EXTINTEO5_Pos)
+#define EIC_EVCTRL_EXTINTEO6_Pos    6            /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO6        (1 << EIC_EVCTRL_EXTINTEO6_Pos)
+#define EIC_EVCTRL_EXTINTEO7_Pos    7            /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO7        (1 << EIC_EVCTRL_EXTINTEO7_Pos)
+#define EIC_EVCTRL_EXTINTEO8_Pos    8            /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO8        (1 << EIC_EVCTRL_EXTINTEO8_Pos)
+#define EIC_EVCTRL_EXTINTEO9_Pos    9            /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO9        (1 << EIC_EVCTRL_EXTINTEO9_Pos)
+#define EIC_EVCTRL_EXTINTEO10_Pos   10           /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO10       (1 << EIC_EVCTRL_EXTINTEO10_Pos)
+#define EIC_EVCTRL_EXTINTEO11_Pos   11           /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO11       (1 << EIC_EVCTRL_EXTINTEO11_Pos)
+#define EIC_EVCTRL_EXTINTEO12_Pos   12           /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO12       (1 << EIC_EVCTRL_EXTINTEO12_Pos)
+#define EIC_EVCTRL_EXTINTEO13_Pos   13           /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO13       (1 << EIC_EVCTRL_EXTINTEO13_Pos)
+#define EIC_EVCTRL_EXTINTEO14_Pos   14           /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO14       (1 << EIC_EVCTRL_EXTINTEO14_Pos)
+#define EIC_EVCTRL_EXTINTEO15_Pos   15           /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO15       (1 << EIC_EVCTRL_EXTINTEO15_Pos)
+#define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk     (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value)  ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)))
+#define EIC_EVCTRL_MASK             0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET         0x08         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT0_Pos    0            /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
+#define EIC_INTENCLR_EXTINT0        (1 << EIC_INTENCLR_EXTINT0_Pos)
+#define EIC_INTENCLR_EXTINT1_Pos    1            /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
+#define EIC_INTENCLR_EXTINT1        (1 << EIC_INTENCLR_EXTINT1_Pos)
+#define EIC_INTENCLR_EXTINT2_Pos    2            /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
+#define EIC_INTENCLR_EXTINT2        (1 << EIC_INTENCLR_EXTINT2_Pos)
+#define EIC_INTENCLR_EXTINT3_Pos    3            /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
+#define EIC_INTENCLR_EXTINT3        (1 << EIC_INTENCLR_EXTINT3_Pos)
+#define EIC_INTENCLR_EXTINT4_Pos    4            /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
+#define EIC_INTENCLR_EXTINT4        (1 << EIC_INTENCLR_EXTINT4_Pos)
+#define EIC_INTENCLR_EXTINT5_Pos    5            /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
+#define EIC_INTENCLR_EXTINT5        (1 << EIC_INTENCLR_EXTINT5_Pos)
+#define EIC_INTENCLR_EXTINT6_Pos    6            /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
+#define EIC_INTENCLR_EXTINT6        (1 << EIC_INTENCLR_EXTINT6_Pos)
+#define EIC_INTENCLR_EXTINT7_Pos    7            /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
+#define EIC_INTENCLR_EXTINT7        (1 << EIC_INTENCLR_EXTINT7_Pos)
+#define EIC_INTENCLR_EXTINT8_Pos    8            /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
+#define EIC_INTENCLR_EXTINT8        (1 << EIC_INTENCLR_EXTINT8_Pos)
+#define EIC_INTENCLR_EXTINT9_Pos    9            /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
+#define EIC_INTENCLR_EXTINT9        (1 << EIC_INTENCLR_EXTINT9_Pos)
+#define EIC_INTENCLR_EXTINT10_Pos   10           /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
+#define EIC_INTENCLR_EXTINT10       (1 << EIC_INTENCLR_EXTINT10_Pos)
+#define EIC_INTENCLR_EXTINT11_Pos   11           /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
+#define EIC_INTENCLR_EXTINT11       (1 << EIC_INTENCLR_EXTINT11_Pos)
+#define EIC_INTENCLR_EXTINT12_Pos   12           /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
+#define EIC_INTENCLR_EXTINT12       (1 << EIC_INTENCLR_EXTINT12_Pos)
+#define EIC_INTENCLR_EXTINT13_Pos   13           /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
+#define EIC_INTENCLR_EXTINT13       (1 << EIC_INTENCLR_EXTINT13_Pos)
+#define EIC_INTENCLR_EXTINT14_Pos   14           /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
+#define EIC_INTENCLR_EXTINT14       (1 << EIC_INTENCLR_EXTINT14_Pos)
+#define EIC_INTENCLR_EXTINT15_Pos   15           /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
+#define EIC_INTENCLR_EXTINT15       (1 << EIC_INTENCLR_EXTINT15_Pos)
+#define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
+#define EIC_INTENCLR_EXTINT_Msk     (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value)  ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)))
+#define EIC_INTENCLR_MASK           0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET         0x0C         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT0_Pos    0            /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
+#define EIC_INTENSET_EXTINT0        (1 << EIC_INTENSET_EXTINT0_Pos)
+#define EIC_INTENSET_EXTINT1_Pos    1            /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
+#define EIC_INTENSET_EXTINT1        (1 << EIC_INTENSET_EXTINT1_Pos)
+#define EIC_INTENSET_EXTINT2_Pos    2            /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
+#define EIC_INTENSET_EXTINT2        (1 << EIC_INTENSET_EXTINT2_Pos)
+#define EIC_INTENSET_EXTINT3_Pos    3            /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
+#define EIC_INTENSET_EXTINT3        (1 << EIC_INTENSET_EXTINT3_Pos)
+#define EIC_INTENSET_EXTINT4_Pos    4            /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
+#define EIC_INTENSET_EXTINT4        (1 << EIC_INTENSET_EXTINT4_Pos)
+#define EIC_INTENSET_EXTINT5_Pos    5            /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
+#define EIC_INTENSET_EXTINT5        (1 << EIC_INTENSET_EXTINT5_Pos)
+#define EIC_INTENSET_EXTINT6_Pos    6            /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
+#define EIC_INTENSET_EXTINT6        (1 << EIC_INTENSET_EXTINT6_Pos)
+#define EIC_INTENSET_EXTINT7_Pos    7            /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
+#define EIC_INTENSET_EXTINT7        (1 << EIC_INTENSET_EXTINT7_Pos)
+#define EIC_INTENSET_EXTINT8_Pos    8            /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
+#define EIC_INTENSET_EXTINT8        (1 << EIC_INTENSET_EXTINT8_Pos)
+#define EIC_INTENSET_EXTINT9_Pos    9            /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
+#define EIC_INTENSET_EXTINT9        (1 << EIC_INTENSET_EXTINT9_Pos)
+#define EIC_INTENSET_EXTINT10_Pos   10           /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
+#define EIC_INTENSET_EXTINT10       (1 << EIC_INTENSET_EXTINT10_Pos)
+#define EIC_INTENSET_EXTINT11_Pos   11           /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
+#define EIC_INTENSET_EXTINT11       (1 << EIC_INTENSET_EXTINT11_Pos)
+#define EIC_INTENSET_EXTINT12_Pos   12           /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
+#define EIC_INTENSET_EXTINT12       (1 << EIC_INTENSET_EXTINT12_Pos)
+#define EIC_INTENSET_EXTINT13_Pos   13           /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
+#define EIC_INTENSET_EXTINT13       (1 << EIC_INTENSET_EXTINT13_Pos)
+#define EIC_INTENSET_EXTINT14_Pos   14           /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
+#define EIC_INTENSET_EXTINT14       (1 << EIC_INTENSET_EXTINT14_Pos)
+#define EIC_INTENSET_EXTINT15_Pos   15           /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
+#define EIC_INTENSET_EXTINT15       (1 << EIC_INTENSET_EXTINT15_Pos)
+#define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt x Enable */
+#define EIC_INTENSET_EXTINT_Msk     (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value)  ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)))
+#define EIC_INTENSET_MASK           0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0               */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1               */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2               */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3               */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4               */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5               */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6               */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7               */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8               */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9               */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10              */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11              */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12              */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13              */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14              */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15              */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x               */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET          0x10         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT0_Pos     0            /**< \brief (EIC_INTFLAG) External Interrupt 0 */
+#define EIC_INTFLAG_EXTINT0         (1 << EIC_INTFLAG_EXTINT0_Pos)
+#define EIC_INTFLAG_EXTINT1_Pos     1            /**< \brief (EIC_INTFLAG) External Interrupt 1 */
+#define EIC_INTFLAG_EXTINT1         (1 << EIC_INTFLAG_EXTINT1_Pos)
+#define EIC_INTFLAG_EXTINT2_Pos     2            /**< \brief (EIC_INTFLAG) External Interrupt 2 */
+#define EIC_INTFLAG_EXTINT2         (1 << EIC_INTFLAG_EXTINT2_Pos)
+#define EIC_INTFLAG_EXTINT3_Pos     3            /**< \brief (EIC_INTFLAG) External Interrupt 3 */
+#define EIC_INTFLAG_EXTINT3         (1 << EIC_INTFLAG_EXTINT3_Pos)
+#define EIC_INTFLAG_EXTINT4_Pos     4            /**< \brief (EIC_INTFLAG) External Interrupt 4 */
+#define EIC_INTFLAG_EXTINT4         (1 << EIC_INTFLAG_EXTINT4_Pos)
+#define EIC_INTFLAG_EXTINT5_Pos     5            /**< \brief (EIC_INTFLAG) External Interrupt 5 */
+#define EIC_INTFLAG_EXTINT5         (1 << EIC_INTFLAG_EXTINT5_Pos)
+#define EIC_INTFLAG_EXTINT6_Pos     6            /**< \brief (EIC_INTFLAG) External Interrupt 6 */
+#define EIC_INTFLAG_EXTINT6         (1 << EIC_INTFLAG_EXTINT6_Pos)
+#define EIC_INTFLAG_EXTINT7_Pos     7            /**< \brief (EIC_INTFLAG) External Interrupt 7 */
+#define EIC_INTFLAG_EXTINT7         (1 << EIC_INTFLAG_EXTINT7_Pos)
+#define EIC_INTFLAG_EXTINT8_Pos     8            /**< \brief (EIC_INTFLAG) External Interrupt 8 */
+#define EIC_INTFLAG_EXTINT8         (1 << EIC_INTFLAG_EXTINT8_Pos)
+#define EIC_INTFLAG_EXTINT9_Pos     9            /**< \brief (EIC_INTFLAG) External Interrupt 9 */
+#define EIC_INTFLAG_EXTINT9         (1 << EIC_INTFLAG_EXTINT9_Pos)
+#define EIC_INTFLAG_EXTINT10_Pos    10           /**< \brief (EIC_INTFLAG) External Interrupt 10 */
+#define EIC_INTFLAG_EXTINT10        (1 << EIC_INTFLAG_EXTINT10_Pos)
+#define EIC_INTFLAG_EXTINT11_Pos    11           /**< \brief (EIC_INTFLAG) External Interrupt 11 */
+#define EIC_INTFLAG_EXTINT11        (1 << EIC_INTFLAG_EXTINT11_Pos)
+#define EIC_INTFLAG_EXTINT12_Pos    12           /**< \brief (EIC_INTFLAG) External Interrupt 12 */
+#define EIC_INTFLAG_EXTINT12        (1 << EIC_INTFLAG_EXTINT12_Pos)
+#define EIC_INTFLAG_EXTINT13_Pos    13           /**< \brief (EIC_INTFLAG) External Interrupt 13 */
+#define EIC_INTFLAG_EXTINT13        (1 << EIC_INTFLAG_EXTINT13_Pos)
+#define EIC_INTFLAG_EXTINT14_Pos    14           /**< \brief (EIC_INTFLAG) External Interrupt 14 */
+#define EIC_INTFLAG_EXTINT14        (1 << EIC_INTFLAG_EXTINT14_Pos)
+#define EIC_INTFLAG_EXTINT15_Pos    15           /**< \brief (EIC_INTFLAG) External Interrupt 15 */
+#define EIC_INTFLAG_EXTINT15        (1 << EIC_INTFLAG_EXTINT15_Pos)
+#define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt x */
+#define EIC_INTFLAG_EXTINT_Msk      (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value)   ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)))
+#define EIC_INTFLAG_MASK            0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAKEUPEN0:1;      /*!< bit:      0  External Interrupt 0 Wake-up Enable */
+    uint32_t WAKEUPEN1:1;      /*!< bit:      1  External Interrupt 1 Wake-up Enable */
+    uint32_t WAKEUPEN2:1;      /*!< bit:      2  External Interrupt 2 Wake-up Enable */
+    uint32_t WAKEUPEN3:1;      /*!< bit:      3  External Interrupt 3 Wake-up Enable */
+    uint32_t WAKEUPEN4:1;      /*!< bit:      4  External Interrupt 4 Wake-up Enable */
+    uint32_t WAKEUPEN5:1;      /*!< bit:      5  External Interrupt 5 Wake-up Enable */
+    uint32_t WAKEUPEN6:1;      /*!< bit:      6  External Interrupt 6 Wake-up Enable */
+    uint32_t WAKEUPEN7:1;      /*!< bit:      7  External Interrupt 7 Wake-up Enable */
+    uint32_t WAKEUPEN8:1;      /*!< bit:      8  External Interrupt 8 Wake-up Enable */
+    uint32_t WAKEUPEN9:1;      /*!< bit:      9  External Interrupt 9 Wake-up Enable */
+    uint32_t WAKEUPEN10:1;     /*!< bit:     10  External Interrupt 10 Wake-up Enable */
+    uint32_t WAKEUPEN11:1;     /*!< bit:     11  External Interrupt 11 Wake-up Enable */
+    uint32_t WAKEUPEN12:1;     /*!< bit:     12  External Interrupt 12 Wake-up Enable */
+    uint32_t WAKEUPEN13:1;     /*!< bit:     13  External Interrupt 13 Wake-up Enable */
+    uint32_t WAKEUPEN14:1;     /*!< bit:     14  External Interrupt 14 Wake-up Enable */
+    uint32_t WAKEUPEN15:1;     /*!< bit:     15  External Interrupt 15 Wake-up Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t WAKEUPEN:16;      /*!< bit:  0..15  External Interrupt x Wake-up Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_WAKEUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_WAKEUP_OFFSET           0x14         /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
+#define EIC_WAKEUP_RESETVALUE       0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
+
+#define EIC_WAKEUP_WAKEUPEN0_Pos    0            /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN0        (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
+#define EIC_WAKEUP_WAKEUPEN1_Pos    1            /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN1        (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
+#define EIC_WAKEUP_WAKEUPEN2_Pos    2            /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN2        (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
+#define EIC_WAKEUP_WAKEUPEN3_Pos    3            /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN3        (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
+#define EIC_WAKEUP_WAKEUPEN4_Pos    4            /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN4        (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
+#define EIC_WAKEUP_WAKEUPEN5_Pos    5            /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN5        (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
+#define EIC_WAKEUP_WAKEUPEN6_Pos    6            /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN6        (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
+#define EIC_WAKEUP_WAKEUPEN7_Pos    7            /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN7        (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
+#define EIC_WAKEUP_WAKEUPEN8_Pos    8            /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN8        (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
+#define EIC_WAKEUP_WAKEUPEN9_Pos    9            /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN9        (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
+#define EIC_WAKEUP_WAKEUPEN10_Pos   10           /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN10       (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
+#define EIC_WAKEUP_WAKEUPEN11_Pos   11           /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN11       (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
+#define EIC_WAKEUP_WAKEUPEN12_Pos   12           /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN12       (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
+#define EIC_WAKEUP_WAKEUPEN13_Pos   13           /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN13       (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
+#define EIC_WAKEUP_WAKEUPEN14_Pos   14           /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN14       (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
+#define EIC_WAKEUP_WAKEUPEN15_Pos   15           /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN15       (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
+#define EIC_WAKEUP_WAKEUPEN_Pos     0            /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN_Msk     (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
+#define EIC_WAKEUP_WAKEUPEN(value)  ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)))
+#define EIC_WAKEUP_MASK             0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SENSE0:3;         /*!< bit:  0.. 2  Input Sense 0 Configuration        */
+    uint32_t FILTEN0:1;        /*!< bit:      3  Filter 0 Enable                    */
+    uint32_t SENSE1:3;         /*!< bit:  4.. 6  Input Sense 1 Configuration        */
+    uint32_t FILTEN1:1;        /*!< bit:      7  Filter 1 Enable                    */
+    uint32_t SENSE2:3;         /*!< bit:  8..10  Input Sense 2 Configuration        */
+    uint32_t FILTEN2:1;        /*!< bit:     11  Filter 2 Enable                    */
+    uint32_t SENSE3:3;         /*!< bit: 12..14  Input Sense 3 Configuration        */
+    uint32_t FILTEN3:1;        /*!< bit:     15  Filter 3 Enable                    */
+    uint32_t SENSE4:3;         /*!< bit: 16..18  Input Sense 4 Configuration        */
+    uint32_t FILTEN4:1;        /*!< bit:     19  Filter 4 Enable                    */
+    uint32_t SENSE5:3;         /*!< bit: 20..22  Input Sense 5 Configuration        */
+    uint32_t FILTEN5:1;        /*!< bit:     23  Filter 5 Enable                    */
+    uint32_t SENSE6:3;         /*!< bit: 24..26  Input Sense 6 Configuration        */
+    uint32_t FILTEN6:1;        /*!< bit:     27  Filter 6 Enable                    */
+    uint32_t SENSE7:3;         /*!< bit: 28..30  Input Sense 7 Configuration        */
+    uint32_t FILTEN7:1;        /*!< bit:     31  Filter 7 Enable                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET           0x18         /**< \brief (EIC_CONFIG offset) Configuration n */
+#define EIC_CONFIG_RESETVALUE       0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
+
+#define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
+#define EIC_CONFIG_SENSE0_Msk       (0x7ul << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value)    ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)))
+#define   EIC_CONFIG_SENSE0_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE0_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising-edge detection */
+#define   EIC_CONFIG_SENSE0_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling-edge detection */
+#define   EIC_CONFIG_SENSE0_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both-edges detection */
+#define   EIC_CONFIG_SENSE0_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High-level detection */
+#define   EIC_CONFIG_SENSE0_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low-level detection */
+#define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH      (EIC_CONFIG_SENSE0_BOTH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter 0 Enable */
+#define EIC_CONFIG_FILTEN0          (0x1ul << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
+#define EIC_CONFIG_SENSE1_Msk       (0x7ul << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value)    ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)))
+#define   EIC_CONFIG_SENSE1_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE1_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE1_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE1_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE1_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE1_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH      (EIC_CONFIG_SENSE1_BOTH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter 1 Enable */
+#define EIC_CONFIG_FILTEN1          (0x1ul << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
+#define EIC_CONFIG_SENSE2_Msk       (0x7ul << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value)    ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)))
+#define   EIC_CONFIG_SENSE2_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE2_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE2_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE2_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE2_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE2_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH      (EIC_CONFIG_SENSE2_BOTH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter 2 Enable */
+#define EIC_CONFIG_FILTEN2          (0x1ul << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
+#define EIC_CONFIG_SENSE3_Msk       (0x7ul << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value)    ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)))
+#define   EIC_CONFIG_SENSE3_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE3_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE3_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE3_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE3_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE3_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH      (EIC_CONFIG_SENSE3_BOTH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter 3 Enable */
+#define EIC_CONFIG_FILTEN3          (0x1ul << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
+#define EIC_CONFIG_SENSE4_Msk       (0x7ul << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value)    ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)))
+#define   EIC_CONFIG_SENSE4_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE4_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE4_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE4_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE4_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE4_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH      (EIC_CONFIG_SENSE4_BOTH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter 4 Enable */
+#define EIC_CONFIG_FILTEN4          (0x1ul << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
+#define EIC_CONFIG_SENSE5_Msk       (0x7ul << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value)    ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)))
+#define   EIC_CONFIG_SENSE5_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE5_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE5_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE5_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE5_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE5_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH      (EIC_CONFIG_SENSE5_BOTH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter 5 Enable */
+#define EIC_CONFIG_FILTEN5          (0x1ul << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
+#define EIC_CONFIG_SENSE6_Msk       (0x7ul << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value)    ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)))
+#define   EIC_CONFIG_SENSE6_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE6_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE6_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE6_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE6_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE6_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH      (EIC_CONFIG_SENSE6_BOTH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter 6 Enable */
+#define EIC_CONFIG_FILTEN6          (0x1ul << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
+#define EIC_CONFIG_SENSE7_Msk       (0x7ul << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value)    ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)))
+#define   EIC_CONFIG_SENSE7_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE7_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE7_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE7_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE7_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE7_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH      (EIC_CONFIG_SENSE7_BOTH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter 7 Enable */
+#define EIC_CONFIG_FILTEN7          (0x1ul << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK             0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EIC_CTRL_Type             CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __I  EIC_STATUS_Type           STATUS;      /**< \brief Offset: 0x01 (R/   8) Status */
+  __IO EIC_NMICTRL_Type          NMICTRL;     /**< \brief Offset: 0x02 (R/W  8) Non-Maskable Interrupt Control */
+  __IO EIC_NMIFLAG_Type          NMIFLAG;     /**< \brief Offset: 0x03 (R/W  8) Non-Maskable Interrupt Flag Status and Clear */
+  __IO EIC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) Event Control */
+  __IO EIC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+  __IO EIC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+  __IO EIC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+  __IO EIC_WAKEUP_Type           WAKEUP;      /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+  __IO EIC_CONFIG_Type           CONFIG[2];   /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_EIC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/evsys.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/evsys.h
new file mode 100644
index 0000000000..9c32507553
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/evsys.h
@@ -0,0 +1,469 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_EVSYS_COMPONENT_
+#define _SAMD20_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMD20_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2208
+#define REV_EVSYS                   0x101
+
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint8_t  GCLKREQ:1;        /*!< bit:      4  Generic Clock Requests             */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
+#define EVSYS_CTRL_RESETVALUE       0x00ul       /**< \brief (EVSYS_CTRL reset_value) Control */
+
+#define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
+#define EVSYS_CTRL_SWRST            (0x1ul << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
+#define EVSYS_CTRL_GCLKREQ          (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK             0x11ul       /**< \brief (EVSYS_CTRL) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL:3;        /*!< bit:  0.. 2  Channel Selection                  */
+    uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint32_t SWEVT:1;          /*!< bit:      8  Software Event                     */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t EVGEN:6;          /*!< bit: 16..21  Event Generator Selection          */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t PATH:2;           /*!< bit: 24..25  Path Selection                     */
+    uint32_t EDGSEL:2;         /*!< bit: 26..27  Edge Detection Selection           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
+#define EVSYS_CHANNEL_RESETVALUE    0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+
+#define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
+#define EVSYS_CHANNEL_CHANNEL_Msk   (0x7ul << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
+#define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
+#define EVSYS_CHANNEL_SWEVT         (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk     (0x3Ful << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value)  ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
+#define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk      (0x3ul << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value)   ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
+#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk    (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul  /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_MASK          0x0F3F0107ul /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t USER:4;           /*!< bit:  0.. 3  User Multiplexer Selection         */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t CHANNEL:4;        /*!< bit:  8..11  Channel Event Selection            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
+#define EVSYS_USER_RESETVALUE       0x0000ul     /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+
+#define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
+#define EVSYS_USER_USER_Msk         (0xFul << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER(value)      ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
+#define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk      (0xFul << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value)   ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
+#define EVSYS_USER_MASK             0x0F0Ful     /**< \brief (EVSYS_USER) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
+    uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
+    uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
+    uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
+    uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
+    uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
+    uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
+    uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
+    uint32_t CHBUSY0:1;        /*!< bit:      8  Channel 0 Busy                     */
+    uint32_t CHBUSY1:1;        /*!< bit:      9  Channel 1 Busy                     */
+    uint32_t CHBUSY2:1;        /*!< bit:     10  Channel 2 Busy                     */
+    uint32_t CHBUSY3:1;        /*!< bit:     11  Channel 3 Busy                     */
+    uint32_t CHBUSY4:1;        /*!< bit:     12  Channel 4 Busy                     */
+    uint32_t CHBUSY5:1;        /*!< bit:     13  Channel 5 Busy                     */
+    uint32_t CHBUSY6:1;        /*!< bit:     14  Channel 6 Busy                     */
+    uint32_t CHBUSY7:1;        /*!< bit:     15  Channel 7 Busy                     */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t USRRDY:8;         /*!< bit:  0.. 7  Channel x User Ready               */
+    uint32_t CHBUSY:8;         /*!< bit:  8..15  Channel x Busy                     */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE   0x00000000ul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1      (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2      (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3      (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4      (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5      (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6      (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk   (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1      (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos  10           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2      (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos  11           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3      (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos  12           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4      (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos  13           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5      (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos  14           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6      (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk   (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
+#define EVSYS_CHSTATUS_MASK         0x0000FFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1         (1 << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2         (1 << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3         (1 << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4         (1 << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5         (1 << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6         (1 << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk      (0xFFul << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value)   ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
+#define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1         (1 << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos     10           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2         (1 << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos     11           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3         (1 << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos     12           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4         (1 << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos     13           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5         (1 << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos     14           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6         (1 << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk      (0xFFul << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value)   ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
+#define EVSYS_INTENCLR_MASK         0x0000FFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1         (1 << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2         (1 << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3         (1 << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4         (1 << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5         (1 << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6         (1 << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk      (0xFFul << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value)   ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
+#define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1         (1 << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos     10           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2         (1 << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos     11           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3         (1 << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos     12           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4         (1 << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos     13           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5         (1 << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos     14           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6         (1 << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk      (0xFFul << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value)   ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
+#define EVSYS_INTENSET_MASK         0x0000FFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection          */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection          */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection          */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection          */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection          */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection          */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection          */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection          */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun                  */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection          */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE    0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1          (1 << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2          (1 << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3          (1 << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4          (1 << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5          (1 << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6          (1 << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk       (0xFFul << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value)    ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
+#define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1          (1 << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos      10           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2          (1 << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos      11           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3          (1 << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos      12           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4          (1 << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos      13           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5          (1 << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos      14           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6          (1 << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk       (0xFFul << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value)    ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
+#define EVSYS_INTFLAG_MASK          0x0000FFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  EVSYS_CTRL_Type           CTRL;        /**< \brief Offset: 0x00 ( /W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x04 (R/W 32) Channel */
+  __IO EVSYS_USER_Type           USER;        /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+       RoReg8                    Reserved2[0x2];
+  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
+  __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+  __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+  __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_EVSYS_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/gclk.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/gclk.h
new file mode 100644
index 0000000000..ce48516320
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/gclk.h
@@ -0,0 +1,325 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_GCLK_COMPONENT_
+#define _SAMD20_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAMD20_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2102
+#define REV_GCLK                    0x210
+
+/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRL_OFFSET            0x0          /**< \brief (GCLK_CTRL offset) Control */
+#define GCLK_CTRL_RESETVALUE        0x00ul       /**< \brief (GCLK_CTRL reset_value) Control */
+
+#define GCLK_CTRL_SWRST_Pos         0            /**< \brief (GCLK_CTRL) Software Reset */
+#define GCLK_CTRL_SWRST             (0x1ul << GCLK_CTRL_SWRST_Pos)
+#define GCLK_CTRL_MASK              0x01ul       /**< \brief (GCLK_CTRL) MASK Register */
+
+/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_STATUS_OFFSET          0x1          /**< \brief (GCLK_STATUS offset) Status */
+#define GCLK_STATUS_RESETVALUE      0x00ul       /**< \brief (GCLK_STATUS reset_value) Status */
+
+#define GCLK_STATUS_SYNCBUSY_Pos    7            /**< \brief (GCLK_STATUS) Synchronization Busy Status */
+#define GCLK_STATUS_SYNCBUSY        (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
+#define GCLK_STATUS_MASK            0x80ul       /**< \brief (GCLK_STATUS) MASK Register */
+
+/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:6;             /*!< bit:  0.. 5  Generic Clock Selection ID         */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t GEN:4;            /*!< bit:  8..11  Generic Clock Generator            */
+    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint16_t CLKEN:1;          /*!< bit:     14  Clock Enable                       */
+    uint16_t WRTLOCK:1;        /*!< bit:     15  Write Lock                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} GCLK_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CLKCTRL_OFFSET         0x2          /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
+#define GCLK_CLKCTRL_RESETVALUE     0x0000ul     /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
+
+#define GCLK_CLKCTRL_ID_Pos         0            /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
+#define GCLK_CLKCTRL_ID_Msk         (0x3Ful << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID(value)      ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))
+#define   GCLK_CLKCTRL_ID_DFLL48M_Val     0x0ul  /**< \brief (GCLK_CLKCTRL) DFLL48M Reference */
+#define   GCLK_CLKCTRL_ID_WDT_Val         0x1ul  /**< \brief (GCLK_CLKCTRL) WDT */
+#define   GCLK_CLKCTRL_ID_RTC_Val         0x2ul  /**< \brief (GCLK_CLKCTRL) RTC */
+#define   GCLK_CLKCTRL_ID_EIC_Val         0x3ul  /**< \brief (GCLK_CLKCTRL) EIC */
+#define   GCLK_CLKCTRL_ID_EVSYS_CHANNEL_0_Val 0x4ul  /**< \brief (GCLK_CLKCTRL) EVSYS_CHANNEL_0 */
+#define   GCLK_CLKCTRL_ID_EVSYS_CHANNEL_1_Val 0x5ul  /**< \brief (GCLK_CLKCTRL) EVSYS_CHANNEL_1 */
+#define   GCLK_CLKCTRL_ID_EVSYS_CHANNEL_2_Val 0x6ul  /**< \brief (GCLK_CLKCTRL) EVSYS_CHANNEL_2 */
+#define   GCLK_CLKCTRL_ID_EVSYS_CHANNEL_3_Val 0x7ul  /**< \brief (GCLK_CLKCTRL) EVSYS_CHANNEL_3 */
+#define   GCLK_CLKCTRL_ID_EVSYS_CHANNEL_4_Val 0x8ul  /**< \brief (GCLK_CLKCTRL) EVSYS_CHANNEL_4 */
+#define   GCLK_CLKCTRL_ID_EVSYS_CHANNEL_5_Val 0x9ul  /**< \brief (GCLK_CLKCTRL) EVSYS_CHANNEL_5 */
+#define   GCLK_CLKCTRL_ID_EVSYS_CHANNEL_6_Val 0xAul  /**< \brief (GCLK_CLKCTRL) EVSYS_CHANNEL_6 */
+#define   GCLK_CLKCTRL_ID_EVSYS_CHANNEL_7_Val 0xBul  /**< \brief (GCLK_CLKCTRL) EVSYS_CHANNEL_7 */
+#define   GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0xCul  /**< \brief (GCLK_CLKCTRL) SERCOMx_SLOW */
+#define   GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0xDul  /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0xEul  /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0xFul  /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x10ul  /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x11ul  /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x12ul  /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
+#define   GCLK_CLKCTRL_ID_TC0_TC1_Val     0x13ul  /**< \brief (GCLK_CLKCTRL) TC0,TC1 */
+#define   GCLK_CLKCTRL_ID_TC2_TC3_Val     0x14ul  /**< \brief (GCLK_CLKCTRL) TC2,TC3 */
+#define   GCLK_CLKCTRL_ID_TC4_TC5_Val     0x15ul  /**< \brief (GCLK_CLKCTRL) TC4,TC5 */
+#define   GCLK_CLKCTRL_ID_TC6_TC7_Val     0x16ul  /**< \brief (GCLK_CLKCTRL) TC6,TC7 */
+#define   GCLK_CLKCTRL_ID_ADC_Val         0x17ul  /**< \brief (GCLK_CLKCTRL) ADC */
+#define   GCLK_CLKCTRL_ID_AC_DIG_Val      0x18ul  /**< \brief (GCLK_CLKCTRL) AC_DIG */
+#define   GCLK_CLKCTRL_ID_AC_ANA_Val      0x19ul  /**< \brief (GCLK_CLKCTRL) AC_ANA */
+#define   GCLK_CLKCTRL_ID_DAC_Val         0x1Aul  /**< \brief (GCLK_CLKCTRL) DAC */
+#define   GCLK_CLKCTRL_ID_PTC_Val         0x1Bul  /**< \brief (GCLK_CLKCTRL) PTC */
+#define GCLK_CLKCTRL_ID_DFLL48M     (GCLK_CLKCTRL_ID_DFLL48M_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_WDT         (GCLK_CLKCTRL_ID_WDT_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_RTC         (GCLK_CLKCTRL_ID_RTC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EIC         (GCLK_CLKCTRL_ID_EIC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_CHANNEL_0 (GCLK_CLKCTRL_ID_EVSYS_CHANNEL_0_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_CHANNEL_1 (GCLK_CLKCTRL_ID_EVSYS_CHANNEL_1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_CHANNEL_2 (GCLK_CLKCTRL_ID_EVSYS_CHANNEL_2_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_CHANNEL_3 (GCLK_CLKCTRL_ID_EVSYS_CHANNEL_3_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_CHANNEL_4 (GCLK_CLKCTRL_ID_EVSYS_CHANNEL_4_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_CHANNEL_5 (GCLK_CLKCTRL_ID_EVSYS_CHANNEL_5_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_CHANNEL_6 (GCLK_CLKCTRL_ID_EVSYS_CHANNEL_6_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_CHANNEL_7 (GCLK_CLKCTRL_ID_EVSYS_CHANNEL_7_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC0_TC1     (GCLK_CLKCTRL_ID_TC0_TC1_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC2_TC3     (GCLK_CLKCTRL_ID_TC2_TC3_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC4_TC5     (GCLK_CLKCTRL_ID_TC4_TC5_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC6_TC7     (GCLK_CLKCTRL_ID_TC6_TC7_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_ADC         (GCLK_CLKCTRL_ID_ADC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_DIG      (GCLK_CLKCTRL_ID_AC_DIG_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_ANA      (GCLK_CLKCTRL_ID_AC_ANA_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_DAC         (GCLK_CLKCTRL_ID_DAC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_PTC         (GCLK_CLKCTRL_ID_PTC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_GEN_Pos        8            /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
+#define GCLK_CLKCTRL_GEN_Msk        (0xFul << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN(value)     ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))
+#define   GCLK_CLKCTRL_GEN_GCLK0_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
+#define   GCLK_CLKCTRL_GEN_GCLK1_Val      0x1ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
+#define   GCLK_CLKCTRL_GEN_GCLK2_Val      0x2ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
+#define   GCLK_CLKCTRL_GEN_GCLK3_Val      0x3ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
+#define   GCLK_CLKCTRL_GEN_GCLK4_Val      0x4ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
+#define   GCLK_CLKCTRL_GEN_GCLK5_Val      0x5ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
+#define   GCLK_CLKCTRL_GEN_GCLK6_Val      0x6ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
+#define   GCLK_CLKCTRL_GEN_GCLK7_Val      0x7ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
+#define GCLK_CLKCTRL_GEN_GCLK0      (GCLK_CLKCTRL_GEN_GCLK0_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK1      (GCLK_CLKCTRL_GEN_GCLK1_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK2      (GCLK_CLKCTRL_GEN_GCLK2_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK3      (GCLK_CLKCTRL_GEN_GCLK3_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK4      (GCLK_CLKCTRL_GEN_GCLK4_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK5      (GCLK_CLKCTRL_GEN_GCLK5_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK6      (GCLK_CLKCTRL_GEN_GCLK6_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK7      (GCLK_CLKCTRL_GEN_GCLK7_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_CLKEN_Pos      14           /**< \brief (GCLK_CLKCTRL) Clock Enable */
+#define GCLK_CLKCTRL_CLKEN          (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
+#define GCLK_CLKCTRL_WRTLOCK_Pos    15           /**< \brief (GCLK_CLKCTRL) Write Lock */
+#define GCLK_CLKCTRL_WRTLOCK        (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
+#define GCLK_CLKCTRL_MASK           0xCF3Ful     /**< \brief (GCLK_CLKCTRL) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t SRC:5;            /*!< bit:  8..12  Source Select                      */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t GENEN:1;          /*!< bit:     16  Generic Clock Generator Enable     */
+    uint32_t IDC:1;            /*!< bit:     17  Improve Duty Cycle                 */
+    uint32_t OOV:1;            /*!< bit:     18  Output Off Value                   */
+    uint32_t OE:1;             /*!< bit:     19  Output Enable                      */
+    uint32_t DIVSEL:1;         /*!< bit:     20  Divide Selection                   */
+    uint32_t RUNSTDBY:1;       /*!< bit:     21  Run in Standby                     */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET         0x4          /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE     0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_ID_Pos         0            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
+#define GCLK_GENCTRL_ID_Msk         (0xFul << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID(value)      ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))
+#define   GCLK_GENCTRL_ID_GCLK0_Val       0x0ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 0 */
+#define   GCLK_GENCTRL_ID_GCLK1_Val       0x1ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 1 */
+#define   GCLK_GENCTRL_ID_GCLK2_Val       0x2ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 2 */
+#define   GCLK_GENCTRL_ID_GCLK3_Val       0x3ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 3 */
+#define   GCLK_GENCTRL_ID_GCLK4_Val       0x4ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 4 */
+#define   GCLK_GENCTRL_ID_GCLK5_Val       0x5ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 5 */
+#define   GCLK_GENCTRL_ID_GCLK6_Val       0x6ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 6 */
+#define   GCLK_GENCTRL_ID_GCLK7_Val       0x7ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 7 */
+#define GCLK_GENCTRL_ID_GCLK0       (GCLK_GENCTRL_ID_GCLK0_Val     << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID_GCLK1       (GCLK_GENCTRL_ID_GCLK1_Val     << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID_GCLK2       (GCLK_GENCTRL_ID_GCLK2_Val     << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID_GCLK3       (GCLK_GENCTRL_ID_GCLK3_Val     << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID_GCLK4       (GCLK_GENCTRL_ID_GCLK4_Val     << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID_GCLK5       (GCLK_GENCTRL_ID_GCLK5_Val     << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID_GCLK6       (GCLK_GENCTRL_ID_GCLK6_Val     << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID_GCLK7       (GCLK_GENCTRL_ID_GCLK7_Val     << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_SRC_Pos        8            /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk        (0x1Ful << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value)     ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
+#define   GCLK_GENCTRL_SRC_XOSC_Val       0x0ul  /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define   GCLK_GENCTRL_SRC_GCLKIN_Val     0x1ul  /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   0x2ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  0x3ul  /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC32K_Val     0x4ul  /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val    0x5ul  /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC8M_Val      0x6ul  /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
+#define   GCLK_GENCTRL_SRC_DFLL48M_Val    0x7ul  /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define GCLK_GENCTRL_SRC_XOSC       (GCLK_GENCTRL_SRC_XOSC_Val     << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K  (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC32K     (GCLK_GENCTRL_SRC_OSC32K_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC8M      (GCLK_GENCTRL_SRC_OSC8M_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL48M    (GCLK_GENCTRL_SRC_DFLL48M_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos      16           /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN          (0x1ul << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos        17           /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC            (0x1ul << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos        18           /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV            (0x1ul << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos         19           /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE             (0x1ul << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos     20           /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL         (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos   21           /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY       (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_MASK           0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t DIV:16;           /*!< bit:  8..23  Division Factor                    */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENDIV_OFFSET          0x8          /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
+#define GCLK_GENDIV_RESETVALUE      0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
+
+#define GCLK_GENDIV_ID_Pos          0            /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
+#define GCLK_GENDIV_ID_Msk          (0xFul << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID(value)       ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))
+#define   GCLK_GENDIV_ID_GCLK0_Val        0x0ul  /**< \brief (GCLK_GENDIV) Generic clock generator 0 */
+#define   GCLK_GENDIV_ID_GCLK1_Val        0x1ul  /**< \brief (GCLK_GENDIV) Generic clock generator 1 */
+#define   GCLK_GENDIV_ID_GCLK2_Val        0x2ul  /**< \brief (GCLK_GENDIV) Generic clock generator 2 */
+#define   GCLK_GENDIV_ID_GCLK3_Val        0x3ul  /**< \brief (GCLK_GENDIV) Generic clock generator 3 */
+#define   GCLK_GENDIV_ID_GCLK4_Val        0x4ul  /**< \brief (GCLK_GENDIV) Generic clock generator 4 */
+#define   GCLK_GENDIV_ID_GCLK5_Val        0x5ul  /**< \brief (GCLK_GENDIV) Generic clock generator 5 */
+#define   GCLK_GENDIV_ID_GCLK6_Val        0x6ul  /**< \brief (GCLK_GENDIV) Generic clock generator 6 */
+#define   GCLK_GENDIV_ID_GCLK7_Val        0x7ul  /**< \brief (GCLK_GENDIV) Generic clock generator 7 */
+#define GCLK_GENDIV_ID_GCLK0        (GCLK_GENDIV_ID_GCLK0_Val      << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID_GCLK1        (GCLK_GENDIV_ID_GCLK1_Val      << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID_GCLK2        (GCLK_GENDIV_ID_GCLK2_Val      << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID_GCLK3        (GCLK_GENDIV_ID_GCLK3_Val      << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID_GCLK4        (GCLK_GENDIV_ID_GCLK4_Val      << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID_GCLK5        (GCLK_GENDIV_ID_GCLK5_Val      << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID_GCLK6        (GCLK_GENDIV_ID_GCLK6_Val      << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID_GCLK7        (GCLK_GENDIV_ID_GCLK7_Val      << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_DIV_Pos         8            /**< \brief (GCLK_GENDIV) Division Factor */
+#define GCLK_GENDIV_DIV_Msk         (0xFFFFul << GCLK_GENDIV_DIV_Pos)
+#define GCLK_GENDIV_DIV(value)      ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))
+#define GCLK_GENDIV_MASK            0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO GCLK_CTRL_Type            CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+  __I  GCLK_STATUS_Type          STATUS;      /**< \brief Offset: 0x1 (R/   8) Status */
+  __IO GCLK_CLKCTRL_Type         CLKCTRL;     /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+  __IO GCLK_GENCTRL_Type         GENCTRL;     /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+  __IO GCLK_GENDIV_Type          GENDIV;      /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_GCLK_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/nvmctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/nvmctrl.h
new file mode 100644
index 0000000000..9dad35e26f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/nvmctrl.h
@@ -0,0 +1,524 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_NVMCTRL_COMPONENT_
+#define _SAMD20_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD20_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL                 0x1061
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE    0x0000ul     /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk       (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value)    ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)))
+#define   NVMCTRL_CTRLA_CMD_ER_Val        0x2ul  /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_WP_Val        0x4ul  /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_EAR_Val       0x5ul  /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_WAP_Val       0x6ul  /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_SF_Val        0xAul  /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define   NVMCTRL_CTRLA_CMD_WL_Val        0xFul  /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define   NVMCTRL_CTRLA_CMD_LR_Val        0x40ul  /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_UR_Val        0x41ul  /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_SPRM_Val      0x42ul  /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_CPRM_Val      0x43ul  /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_PBC_Val       0x44ul  /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define   NVMCTRL_CTRLA_CMD_SSB_Val       0x45ul  /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define   NVMCTRL_CTRLA_CMD_INVALL_Val    0x46ul  /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP       (NVMCTRL_CTRLA_CMD_WAP_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF        (NVMCTRL_CTRLA_CMD_SF_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL        (NVMCTRL_CTRLA_CMD_WL_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR        (NVMCTRL_CTRLA_CMD_LR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR        (NVMCTRL_CTRLA_CMD_UR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM      (NVMCTRL_CTRLA_CMD_SPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM      (NVMCTRL_CTRLA_CMD_CPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC       (NVMCTRL_CTRLA_CMD_PBC_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk     (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value)  ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)))
+#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     0xA5ul  /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK          0xFF7Ful     /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t RWS:4;            /*!< bit:  1.. 4  NVM Read Wait States               */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t MANW:1;           /*!< bit:      7  Manual Write                       */
+    uint32_t SLEEPPRM:2;       /*!< bit:  8.. 9  Power Reduction Mode during Sleep  */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t READMODE:2;       /*!< bit: 16..17  NVMCTRL Read Mode                  */
+    uint32_t CACHEDIS:1;       /*!< bit:     18  Cache Disable                      */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk       (0xFul << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value)    ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)))
+#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    0x0ul  /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_HALF_Val      0x1ul  /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_DUAL_Val      0x2ul  /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW          (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)))
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul  /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk  (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)))
+#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul  /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS      (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK          0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
+    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk      (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value)   ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)))
+#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk       (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value)    ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)))
+#define   NVMCTRL_PARAM_PSZ_8_Val         0x0ul  /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define   NVMCTRL_PARAM_PSZ_16_Val        0x1ul  /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define   NVMCTRL_PARAM_PSZ_32_Val        0x2ul  /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define   NVMCTRL_PARAM_PSZ_64_Val        0x3ul  /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define   NVMCTRL_PARAM_PSZ_128_Val       0x4ul  /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define   NVMCTRL_PARAM_PSZ_256_Val       0x5ul  /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define   NVMCTRL_PARAM_PSZ_512_Val       0x6ul  /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define   NVMCTRL_PARAM_PSZ_1024_Val      0x7ul  /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_MASK          0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY      (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR      (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK       0x03ul       /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY      (0x1ul << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR      (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK       0x03ul       /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE  0x00ul       /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY       (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR       (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK        0x03ul       /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PRM:1;            /*!< bit:      0  Power Reduction Mode               */
+    uint16_t LOAD:1;           /*!< bit:      1  NVM Page Buffer Active Loading     */
+    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Status           */
+    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Status                  */
+    uint16_t NVME:1;           /*!< bit:      4  NVM Error                          */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t SB:1;             /*!< bit:      8  Security Bit Status                */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE   0x0000ul     /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM          (0x1ul << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD         (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE        (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE        (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME         (0x1ul << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB           (0x1ul << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK         0x011Ful     /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:22;          /*!< bit:  0..21  NVM Address                        */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE     0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk       (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value)    ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)))
+#define NVMCTRL_ADDR_MASK           0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LOCK:16;          /*!< bit:  0..15  Region Lock Bits                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+#define NVMCTRL_LOCK_RESETVALUE     0x0000ul     /**< \brief (NVMCTRL_LOCK reset_value) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk       (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value)    ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)))
+#define NVMCTRL_LOCK_MASK           0xFFFFul     /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+       RoReg8                    Reserved1[0x2];
+  __IO NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
+  __IO NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x3];
+  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x10 (R/W  8) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x3];
+  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x14 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x3];
+  __IO NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x18 (R/W 16) Status */
+       RoReg8                    Reserved5[0x2];
+  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x1C (R/W 32) Address */
+  __IO NVMCTRL_LOCK_Type         LOCK;        /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_NVMCTRL_CAL
+#define SECTION_NVMCTRL_LOCKBIT
+#define SECTION_NVMCTRL_OTP1
+#define SECTION_NVMCTRL_OTP2
+#define SECTION_NVMCTRL_OTP4
+#define SECTION_NVMCTRL_TEMP_LOG
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCAL_ADDR      (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_BIASCAL_Pos       3            /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
+#define ADC_FUSES_BIASCAL_Msk       (0x7ul << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL(value)    ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)))
+
+#define ADC_FUSES_LINEARITY_0_ADDR  NVMCTRL_OTP4
+#define ADC_FUSES_LINEARITY_0_Pos   27           /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
+#define ADC_FUSES_LINEARITY_0_Msk   (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)))
+
+#define ADC_FUSES_LINEARITY_1_ADDR  (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_LINEARITY_1_Pos   0            /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
+#define ADC_FUSES_LINEARITY_1_Msk   (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)))
+
+#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk    (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)))
+
+#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk      (0x3ul << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value)   ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)))
+
+#define FUSES_BOD33_EN_ADDR         NVMCTRL_USER
+#define FUSES_BOD33_EN_Pos          14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define FUSES_BOD33_EN_Msk          (0x1ul << FUSES_BOD33_EN_Pos)
+
+#define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
+#define FUSES_BOD33_HYST_Pos        8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk        (0x1ul << FUSES_BOD33_HYST_Pos)
+
+#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
+#define FUSES_DFLL48M_COARSE_CAL(value) ((FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos)))
+
+#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
+#define FUSES_DFLL48M_FINE_CAL_Pos  0            /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
+#define FUSES_DFLL48M_FINE_CAL_Msk  (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
+#define FUSES_DFLL48M_FINE_CAL(value) ((FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos)))
+
+#define FUSES_OSC32KCAL_ADDR        (NVMCTRL_OTP4 + 4)
+#define FUSES_OSC32KCAL_Pos         6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define FUSES_OSC32KCAL_Msk         (0x7Ful << FUSES_OSC32KCAL_Pos)
+#define FUSES_OSC32KCAL(value)      ((FUSES_OSC32KCAL_Msk & ((value) << FUSES_OSC32KCAL_Pos)))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk  (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)))
+
+#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFul << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFul << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
+
+#define NVMCTRL_FUSES_NVMP_ADDR     NVMCTRL_OTP1
+#define NVMCTRL_FUSES_NVMP_Pos      16           /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
+#define NVMCTRL_FUSES_NVMP_Msk      (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos)
+#define NVMCTRL_FUSES_NVMP(value)   ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)))
+
+#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_NVM_LOCK_Pos  0            /**< \brief (NVMCTRL_OTP1) NVM Lock */
+#define NVMCTRL_FUSES_NVM_LOCK_Msk  (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos)
+#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)))
+
+#define NVMCTRL_FUSES_PSZ_ADDR      NVMCTRL_OTP1
+#define NVMCTRL_FUSES_PSZ_Pos       8            /**< \brief (NVMCTRL_OTP1) NVM Page Size */
+#define NVMCTRL_FUSES_PSZ_Msk       (0xFul << NVMCTRL_FUSES_PSZ_Pos)
+#define NVMCTRL_FUSES_PSZ(value)    ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFul << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFul << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
+
+#define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos      26           /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk      (0x1ul << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos        25           /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk        (0x1ul << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos      3            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk      (0xFul << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value)   ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)))
+
+#define WDT_FUSES_PER_ADDR          NVMCTRL_USER
+#define WDT_FUSES_PER_Pos           27           /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk           (0xFul << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value)        ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)))
+
+#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos           7            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk           (0x1ul << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_0_ADDR     NVMCTRL_USER
+#define WDT_FUSES_WINDOW_0_Pos      31           /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
+#define WDT_FUSES_WINDOW_0_Msk      (0x1ul << WDT_FUSES_WINDOW_0_Pos)
+
+#define WDT_FUSES_WINDOW_1_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_1_Pos      0            /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
+#define WDT_FUSES_WINDOW_1_Msk      (0x7ul << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1(value)   ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)))
+
+/*@}*/
+
+#endif /* _SAMD20_NVMCTRL_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/pac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/pac.h
new file mode 100644
index 0000000000..215b4c5945
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/pac.h
@@ -0,0 +1,107 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_PAC_COMPONENT_
+#define _SAMD20_PAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAMD20_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2211
+#define REV_PAC                     0x101
+
+/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Clear             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WPCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPCLR_OFFSET            0x0          /**< \brief (PAC_WPCLR offset) Write Protection Clear */
+#define PAC_WPCLR_RESETVALUE        0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
+
+#define PAC_WPCLR_WP_Pos            1            /**< \brief (PAC_WPCLR) Write Protection Clear */
+#define PAC_WPCLR_WP_Msk            (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
+#define PAC_WPCLR_WP(value)         ((PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)))
+#define PAC_WPCLR_MASK              0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
+
+/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Set               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WPSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPSET_OFFSET            0x4          /**< \brief (PAC_WPSET offset) Write Protection Set */
+#define PAC_WPSET_RESETVALUE        0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */
+
+#define PAC_WPSET_WP_Pos            1            /**< \brief (PAC_WPSET) Write Protection Set */
+#define PAC_WPSET_WP_Msk            (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
+#define PAC_WPSET_WP(value)         ((PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)))
+#define PAC_WPSET_MASK              0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PAC_WPCLR_Type            WPCLR;       /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+  __IO PAC_WPSET_Type            WPSET;       /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_PAC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/pm.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/pm.h
new file mode 100644
index 0000000000..853c896403
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/pm.h
@@ -0,0 +1,518 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_PM_COMPONENT_
+#define _SAMD20_PM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMD20_PM Power Manager */
+/*@{*/
+
+#define PM_U2206
+#define REV_PM                      0x202
+
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRL_OFFSET              0x00         /**< \brief (PM_CTRL offset) Control */
+#define PM_CTRL_RESETVALUE          0x00ul       /**< \brief (PM_CTRL reset_value) Control */
+
+#define PM_CTRL_MASK                0x00ul       /**< \brief (PM_CTRL) MASK Register */
+
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W  8) Sleep Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  IDLE:2;           /*!< bit:  0.. 1  Idle Mode Configuration            */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_SLEEP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEP_OFFSET             0x01         /**< \brief (PM_SLEEP offset) Sleep Mode */
+#define PM_SLEEP_RESETVALUE         0x00ul       /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+
+#define PM_SLEEP_IDLE_Pos           0            /**< \brief (PM_SLEEP) Idle Mode Configuration */
+#define PM_SLEEP_IDLE_Msk           (0x3ul << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE(value)        ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
+#define   PM_SLEEP_IDLE_CPU_Val           0x0ul  /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define   PM_SLEEP_IDLE_AHB_Val           0x1ul  /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define   PM_SLEEP_IDLE_APB_Val           0x2ul  /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define PM_SLEEP_IDLE_CPU           (PM_SLEEP_IDLE_CPU_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_AHB           (PM_SLEEP_IDLE_AHB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_APB           (PM_SLEEP_IDLE_APB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_MASK               0x03ul       /**< \brief (PM_SLEEP) MASK Register */
+
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W  8) CPU Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CPUDIV:3;         /*!< bit:  0.. 2  CPU Prescaler Selection            */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CPUSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CPUSEL_OFFSET            0x08         /**< \brief (PM_CPUSEL offset) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE        0x00ul       /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+
+#define PM_CPUSEL_CPUDIV_Pos        0            /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
+#define PM_CPUSEL_CPUDIV_Msk        (0x7ul << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV(value)     ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
+#define   PM_CPUSEL_CPUDIV_DIV1_Val       0x0ul  /**< \brief (PM_CPUSEL) Divide by 1 */
+#define   PM_CPUSEL_CPUDIV_DIV2_Val       0x1ul  /**< \brief (PM_CPUSEL) Divide by 2 */
+#define   PM_CPUSEL_CPUDIV_DIV4_Val       0x2ul  /**< \brief (PM_CPUSEL) Divide by 4 */
+#define   PM_CPUSEL_CPUDIV_DIV8_Val       0x3ul  /**< \brief (PM_CPUSEL) Divide by 8 */
+#define   PM_CPUSEL_CPUDIV_DIV16_Val      0x4ul  /**< \brief (PM_CPUSEL) Divide by 16 */
+#define   PM_CPUSEL_CPUDIV_DIV32_Val      0x5ul  /**< \brief (PM_CPUSEL) Divide by 32 */
+#define   PM_CPUSEL_CPUDIV_DIV64_Val      0x6ul  /**< \brief (PM_CPUSEL) Divide by 64 */
+#define   PM_CPUSEL_CPUDIV_DIV128_Val     0x7ul  /**< \brief (PM_CPUSEL) Divide by 128 */
+#define PM_CPUSEL_CPUDIV_DIV1       (PM_CPUSEL_CPUDIV_DIV1_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV2       (PM_CPUSEL_CPUDIV_DIV2_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV4       (PM_CPUSEL_CPUDIV_DIV4_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV8       (PM_CPUSEL_CPUDIV_DIV8_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV16      (PM_CPUSEL_CPUDIV_DIV16_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV32      (PM_CPUSEL_CPUDIV_DIV32_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV64      (PM_CPUSEL_CPUDIV_DIV64_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV128     (PM_CPUSEL_CPUDIV_DIV128_Val   << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_MASK              0x07ul       /**< \brief (PM_CPUSEL) MASK Register */
+
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W  8) APBA Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBADIV:3;        /*!< bit:  0.. 2  APBA Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBASEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBASEL_OFFSET           0x09         /**< \brief (PM_APBASEL offset) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE       0x00ul       /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+
+#define PM_APBASEL_APBADIV_Pos      0            /**< \brief (PM_APBASEL) APBA Prescaler Selection */
+#define PM_APBASEL_APBADIV_Msk      (0x7ul << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV(value)   ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
+#define   PM_APBASEL_APBADIV_DIV1_Val     0x0ul  /**< \brief (PM_APBASEL) Divide by 1 */
+#define   PM_APBASEL_APBADIV_DIV2_Val     0x1ul  /**< \brief (PM_APBASEL) Divide by 2 */
+#define   PM_APBASEL_APBADIV_DIV4_Val     0x2ul  /**< \brief (PM_APBASEL) Divide by 4 */
+#define   PM_APBASEL_APBADIV_DIV8_Val     0x3ul  /**< \brief (PM_APBASEL) Divide by 8 */
+#define   PM_APBASEL_APBADIV_DIV16_Val    0x4ul  /**< \brief (PM_APBASEL) Divide by 16 */
+#define   PM_APBASEL_APBADIV_DIV32_Val    0x5ul  /**< \brief (PM_APBASEL) Divide by 32 */
+#define   PM_APBASEL_APBADIV_DIV64_Val    0x6ul  /**< \brief (PM_APBASEL) Divide by 64 */
+#define   PM_APBASEL_APBADIV_DIV128_Val   0x7ul  /**< \brief (PM_APBASEL) Divide by 128 */
+#define PM_APBASEL_APBADIV_DIV1     (PM_APBASEL_APBADIV_DIV1_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV2     (PM_APBASEL_APBADIV_DIV2_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV4     (PM_APBASEL_APBADIV_DIV4_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV8     (PM_APBASEL_APBADIV_DIV8_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV16    (PM_APBASEL_APBADIV_DIV16_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV32    (PM_APBASEL_APBADIV_DIV32_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV64    (PM_APBASEL_APBADIV_DIV64_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV128   (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_MASK             0x07ul       /**< \brief (PM_APBASEL) MASK Register */
+
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W  8) APBB Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBBDIV:3;        /*!< bit:  0.. 2  APBB Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBBSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBSEL_OFFSET           0x0A         /**< \brief (PM_APBBSEL offset) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+
+#define PM_APBBSEL_APBBDIV_Pos      0            /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
+#define PM_APBBSEL_APBBDIV_Msk      (0x7ul << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV(value)   ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
+#define   PM_APBBSEL_APBBDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBBSEL) Divide by 1 */
+#define   PM_APBBSEL_APBBDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBBSEL) Divide by 2 */
+#define   PM_APBBSEL_APBBDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBBSEL) Divide by 4 */
+#define   PM_APBBSEL_APBBDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBBSEL) Divide by 8 */
+#define   PM_APBBSEL_APBBDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBBSEL) Divide by 16 */
+#define   PM_APBBSEL_APBBDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBBSEL) Divide by 32 */
+#define   PM_APBBSEL_APBBDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBBSEL) Divide by 64 */
+#define   PM_APBBSEL_APBBDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBBSEL) Divide by 128 */
+#define PM_APBBSEL_APBBDIV_DIV1     (PM_APBBSEL_APBBDIV_DIV1_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV2     (PM_APBBSEL_APBBDIV_DIV2_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV4     (PM_APBBSEL_APBBDIV_DIV4_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV8     (PM_APBBSEL_APBBDIV_DIV8_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV16    (PM_APBBSEL_APBBDIV_DIV16_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV32    (PM_APBBSEL_APBBDIV_DIV32_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV64    (PM_APBBSEL_APBBDIV_DIV64_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV128   (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_MASK             0x07ul       /**< \brief (PM_APBBSEL) MASK Register */
+
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W  8) APBC Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBCDIV:3;        /*!< bit:  0.. 2  APBC Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBCSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCSEL_OFFSET           0x0B         /**< \brief (PM_APBCSEL offset) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+
+#define PM_APBCSEL_APBCDIV_Pos      0            /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
+#define PM_APBCSEL_APBCDIV_Msk      (0x7ul << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV(value)   ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
+#define   PM_APBCSEL_APBCDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBCSEL) Divide by 1 */
+#define   PM_APBCSEL_APBCDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBCSEL) Divide by 2 */
+#define   PM_APBCSEL_APBCDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBCSEL) Divide by 4 */
+#define   PM_APBCSEL_APBCDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBCSEL) Divide by 8 */
+#define   PM_APBCSEL_APBCDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBCSEL) Divide by 16 */
+#define   PM_APBCSEL_APBCDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBCSEL) Divide by 32 */
+#define   PM_APBCSEL_APBCDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBCSEL) Divide by 64 */
+#define   PM_APBCSEL_APBCDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBCSEL) Divide by 128 */
+#define PM_APBCSEL_APBCDIV_DIV1     (PM_APBCSEL_APBCDIV_DIV1_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV2     (PM_APBCSEL_APBCDIV_DIV2_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV4     (PM_APBCSEL_APBCDIV_DIV4_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV8     (PM_APBCSEL_APBCDIV_DIV8_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV16    (PM_APBCSEL_APBCDIV_DIV16_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV32    (PM_APBCSEL_APBCDIV_DIV32_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV64    (PM_APBCSEL_APBCDIV_DIV64_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV128   (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_MASK             0x07ul       /**< \brief (PM_APBCSEL) MASK Register */
+
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
+    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
+    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
+    uint32_t DSU_:1;           /*!< bit:      3  DSU AHB Clock Mask                 */
+    uint32_t NVMCTRL_:1;       /*!< bit:      4  NVMCTRL AHB Clock Mask             */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_AHBMASK_OFFSET           0x14         /**< \brief (PM_AHBMASK offset) AHB Mask */
+#define PM_AHBMASK_RESETVALUE       0x0000001Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+
+#define PM_AHBMASK_HPB0_Pos         0            /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
+#define PM_AHBMASK_HPB0             (0x1ul << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB1_Pos         1            /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
+#define PM_AHBMASK_HPB1             (0x1ul << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB2_Pos         2            /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
+#define PM_AHBMASK_HPB2             (0x1ul << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_DSU_Pos          3            /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
+#define PM_AHBMASK_DSU              (0x1ul << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_NVMCTRL_Pos      4            /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
+#define PM_AHBMASK_NVMCTRL          (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_MASK             0x0000001Ful /**< \brief (PM_AHBMASK) MASK Register */
+
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC0_:1;          /*!< bit:      0  PAC0 APB Clock Enable              */
+    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
+    uint32_t SYSCTRL_:1;       /*!< bit:      2  SYSCTRL APB Clock Enable           */
+    uint32_t GCLK_:1;          /*!< bit:      3  GCLK APB Clock Enable              */
+    uint32_t WDT_:1;           /*!< bit:      4  WDT APB Clock Enable               */
+    uint32_t RTC_:1;           /*!< bit:      5  RTC APB Clock Enable               */
+    uint32_t EIC_:1;           /*!< bit:      6  EIC APB Clock Enable               */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBAMASK_OFFSET          0x18         /**< \brief (PM_APBAMASK offset) APBA Mask */
+#define PM_APBAMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+
+#define PM_APBAMASK_PAC0_Pos        0            /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
+#define PM_APBAMASK_PAC0            (0x1ul << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PM_Pos          1            /**< \brief (PM_APBAMASK) PM APB Clock Enable */
+#define PM_APBAMASK_PM              (0x1ul << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_SYSCTRL_Pos     2            /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
+#define PM_APBAMASK_SYSCTRL         (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_GCLK_Pos        3            /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
+#define PM_APBAMASK_GCLK            (0x1ul << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_WDT_Pos         4            /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
+#define PM_APBAMASK_WDT             (0x1ul << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_RTC_Pos         5            /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
+#define PM_APBAMASK_RTC             (0x1ul << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_EIC_Pos         6            /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
+#define PM_APBAMASK_EIC             (0x1ul << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK            0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
+
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC1_:1;          /*!< bit:      0  PAC1 APB Clock Enable              */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
+    uint32_t PORT_:1;          /*!< bit:      3  PORT APB Clock Enable              */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBMASK_OFFSET          0x1C         /**< \brief (PM_APBBMASK offset) APBB Mask */
+#define PM_APBBMASK_RESETVALUE      0x0000001Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+
+#define PM_APBBMASK_PAC1_Pos        0            /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
+#define PM_APBBMASK_PAC1            (0x1ul << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_DSU_Pos         1            /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
+#define PM_APBBMASK_DSU             (0x1ul << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_NVMCTRL_Pos     2            /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
+#define PM_APBBMASK_NVMCTRL         (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_PORT_Pos        3            /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
+#define PM_APBBMASK_PORT            (0x1ul << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_MASK            0x0000000Ful /**< \brief (PM_APBBMASK) MASK Register */
+
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC2_:1;          /*!< bit:      0  PAC2 APB Clock Enable              */
+    uint32_t EVSYS_:1;         /*!< bit:      1  EVSYS APB Clock Enable             */
+    uint32_t SERCOM0_:1;       /*!< bit:      2  SERCOM0 APB Clock Enable           */
+    uint32_t SERCOM1_:1;       /*!< bit:      3  SERCOM1 APB Clock Enable           */
+    uint32_t SERCOM2_:1;       /*!< bit:      4  SERCOM2 APB Clock Enable           */
+    uint32_t SERCOM3_:1;       /*!< bit:      5  SERCOM3 APB Clock Enable           */
+    uint32_t SERCOM4_:1;       /*!< bit:      6  SERCOM4 APB Clock Enable           */
+    uint32_t SERCOM5_:1;       /*!< bit:      7  SERCOM5 APB Clock Enable           */
+    uint32_t TC0_:1;           /*!< bit:      8  TC0 APB Clock Enable               */
+    uint32_t TC1_:1;           /*!< bit:      9  TC1 APB Clock Enable               */
+    uint32_t TC2_:1;           /*!< bit:     10  TC2 APB Clock Enable               */
+    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Clock Enable               */
+    uint32_t TC4_:1;           /*!< bit:     12  TC4 APB Clock Enable               */
+    uint32_t TC5_:1;           /*!< bit:     13  TC5 APB Clock Enable               */
+    uint32_t TC6_:1;           /*!< bit:     14  TC6 APB Clock Enable               */
+    uint32_t TC7_:1;           /*!< bit:     15  TC7 APB Clock Enable               */
+    uint32_t ADC_:1;           /*!< bit:     16  ADC APB Clock Enable               */
+    uint32_t AC_:1;            /*!< bit:     17  AC APB Clock Enable                */
+    uint32_t DAC_:1;           /*!< bit:     18  DAC APB Clock Enable               */
+    uint32_t PTC_:1;           /*!< bit:     19  PTC APB Clock Enable               */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCMASK_OFFSET          0x20         /**< \brief (PM_APBCMASK offset) APBC Mask */
+#define PM_APBCMASK_RESETVALUE      0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+
+#define PM_APBCMASK_PAC2_Pos        0            /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
+#define PM_APBCMASK_PAC2            (0x1ul << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_EVSYS_Pos       1            /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
+#define PM_APBCMASK_EVSYS           (0x1ul << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_SERCOM0_Pos     2            /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
+#define PM_APBCMASK_SERCOM0         (0x1ul << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM1_Pos     3            /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
+#define PM_APBCMASK_SERCOM1         (0x1ul << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM2_Pos     4            /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
+#define PM_APBCMASK_SERCOM2         (0x1ul << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM3_Pos     5            /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
+#define PM_APBCMASK_SERCOM3         (0x1ul << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM4_Pos     6            /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
+#define PM_APBCMASK_SERCOM4         (0x1ul << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM5_Pos     7            /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
+#define PM_APBCMASK_SERCOM5         (0x1ul << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_TC0_Pos         8            /**< \brief (PM_APBCMASK) TC0 APB Clock Enable */
+#define PM_APBCMASK_TC0             (0x1ul << PM_APBCMASK_TC0_Pos)
+#define PM_APBCMASK_TC1_Pos         9            /**< \brief (PM_APBCMASK) TC1 APB Clock Enable */
+#define PM_APBCMASK_TC1             (0x1ul << PM_APBCMASK_TC1_Pos)
+#define PM_APBCMASK_TC2_Pos         10           /**< \brief (PM_APBCMASK) TC2 APB Clock Enable */
+#define PM_APBCMASK_TC2             (0x1ul << PM_APBCMASK_TC2_Pos)
+#define PM_APBCMASK_TC3_Pos         11           /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
+#define PM_APBCMASK_TC3             (0x1ul << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC4_Pos         12           /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
+#define PM_APBCMASK_TC4             (0x1ul << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC5_Pos         13           /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
+#define PM_APBCMASK_TC5             (0x1ul << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC6_Pos         14           /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
+#define PM_APBCMASK_TC6             (0x1ul << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC7_Pos         15           /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
+#define PM_APBCMASK_TC7             (0x1ul << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_ADC_Pos         16           /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
+#define PM_APBCMASK_ADC             (0x1ul << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_AC_Pos          17           /**< \brief (PM_APBCMASK) AC APB Clock Enable */
+#define PM_APBCMASK_AC              (0x1ul << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_DAC_Pos         18           /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
+#define PM_APBCMASK_DAC             (0x1ul << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_PTC_Pos         19           /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
+#define PM_APBCMASK_PTC             (0x1ul << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_MASK            0x000FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET          0x34         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE      0x00ul       /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_CKRDY_Pos       0            /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
+#define PM_INTENCLR_CKRDY           (0x1ul << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK            0x01ul       /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET          0x35         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE      0x00ul       /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_CKRDY_Pos       0            /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
+#define PM_INTENSET_CKRDY           (0x1ul << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK            0x01ul       /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET           0x36         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE       0x00ul       /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_CKRDY_Pos        0            /**< \brief (PM_INTFLAG) Clock Ready */
+#define PM_INTFLAG_CKRDY            (0x1ul << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK             0x01ul       /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/   8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
+    uint8_t  BOD12:1;          /*!< bit:      1  Brown Out 12 Detector Reset        */
+    uint8_t  BOD33:1;          /*!< bit:      2  Brown Out 33 Detector Reset        */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
+    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
+    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_RCAUSE_OFFSET            0x38         /**< \brief (PM_RCAUSE offset) Reset Cause */
+#define PM_RCAUSE_RESETVALUE        0x01ul       /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+
+#define PM_RCAUSE_POR_Pos           0            /**< \brief (PM_RCAUSE) Power On Reset */
+#define PM_RCAUSE_POR               (0x1ul << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_BOD12_Pos         1            /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
+#define PM_RCAUSE_BOD12             (0x1ul << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD33_Pos         2            /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
+#define PM_RCAUSE_BOD33             (0x1ul << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_EXT_Pos           4            /**< \brief (PM_RCAUSE) External Reset */
+#define PM_RCAUSE_EXT               (0x1ul << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_WDT_Pos           5            /**< \brief (PM_RCAUSE) Watchdog Reset */
+#define PM_RCAUSE_WDT               (0x1ul << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_SYST_Pos          6            /**< \brief (PM_RCAUSE) System Reset Request */
+#define PM_RCAUSE_SYST              (0x1ul << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK              0x77ul       /**< \brief (PM_RCAUSE) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PM_CTRL_Type              CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __IO PM_SLEEP_Type             SLEEP;       /**< \brief Offset: 0x01 (R/W  8) Sleep Mode */
+       RoReg8                    Reserved1[0x6];
+  __IO PM_CPUSEL_Type            CPUSEL;      /**< \brief Offset: 0x08 (R/W  8) CPU Clock Select */
+  __IO PM_APBASEL_Type           APBASEL;     /**< \brief Offset: 0x09 (R/W  8) APBA Clock Select */
+  __IO PM_APBBSEL_Type           APBBSEL;     /**< \brief Offset: 0x0A (R/W  8) APBB Clock Select */
+  __IO PM_APBCSEL_Type           APBCSEL;     /**< \brief Offset: 0x0B (R/W  8) APBC Clock Select */
+       RoReg8                    Reserved2[0x8];
+  __IO PM_AHBMASK_Type           AHBMASK;     /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+  __IO PM_APBAMASK_Type          APBAMASK;    /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+  __IO PM_APBBMASK_Type          APBBMASK;    /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+  __IO PM_APBCMASK_Type          APBCMASK;    /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+       RoReg8                    Reserved3[0x10];
+  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x34 (R/W  8) Interrupt Enable Clear */
+  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x35 (R/W  8) Interrupt Enable Set */
+  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x36 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __I  PM_RCAUSE_Type            RCAUSE;      /**< \brief Offset: 0x38 (R/   8) Reset Cause */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_PM_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/port.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/port.h
new file mode 100644
index 0000000000..3c64c7a3b0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/port.h
@@ -0,0 +1,398 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_PORT_COMPONENT_
+#define _SAMD20_PORT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAMD20_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT                    0x100
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIR:32;           /*!< bit:  0..31  Port Data Direction                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET             0x00         /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE         0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos            0            /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk            (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value)         ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
+#define PORT_DIR_MASK               0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRCLR:32;        /*!< bit:  0..31  Port Data Direction Clear          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET          0x04         /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos      0            /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk      (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value)   ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
+#define PORT_DIRCLR_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRSET:32;        /*!< bit:  0..31  Port Data Direction Set            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET          0x08         /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos      0            /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk      (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value)   ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
+#define PORT_DIRSET_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRTGL:32;        /*!< bit:  0..31  Port Data Direction Toggle         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET          0x0C         /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos      0            /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk      (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value)   ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
+#define PORT_DIRTGL_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUT:32;           /*!< bit:  0..31  Port Data Output Value             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET             0x10         /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE         0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos            0            /**< \brief (PORT_OUT) Port Data Output Value */
+#define PORT_OUT_OUT_Msk            (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value)         ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
+#define PORT_OUT_MASK               0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTCLR:32;        /*!< bit:  0..31  Port Data Output Value Clear       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET          0x14         /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos      0            /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk      (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value)   ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
+#define PORT_OUTCLR_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTSET:32;        /*!< bit:  0..31  Port Data Output Value Set         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET          0x18         /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos      0            /**< \brief (PORT_OUTSET) Port Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk      (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value)   ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
+#define PORT_OUTSET_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTTGL:32;        /*!< bit:  0..31  Port Data Output Value Toggle      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET          0x1C         /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos      0            /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk      (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value)   ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
+#define PORT_OUTTGL_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/  32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t IN:32;            /*!< bit:  0..31  Port Data Input Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET              0x20         /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE          0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos              0            /**< \brief (PORT_IN) Port Data Input Value */
+#define PORT_IN_IN_Msk              (0xFFFFFFFFul << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value)           ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
+#define PORT_IN_MASK                0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SAMPLING:32;      /*!< bit:  0..31  Input Sampling Mode                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET            0x24         /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE        0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos      0            /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk      (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value)   ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
+#define PORT_CTRL_MASK              0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PINMASK:16;       /*!< bit:  0..15  Pin Mask for Multiple Pin Configuration */
+    uint32_t PMUXEN:1;         /*!< bit:     16  Peripheral Multiplexer Enable      */
+    uint32_t INEN:1;           /*!< bit:     17  Input Enable                       */
+    uint32_t PULLEN:1;         /*!< bit:     18  Pull Enable                        */
+    uint32_t :3;               /*!< bit: 19..21  Reserved                           */
+    uint32_t DRVSTR:1;         /*!< bit:     22  Output Driver Strength Selection   */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PMUX:4;           /*!< bit: 24..27  Peripheral Multiplexing            */
+    uint32_t WRPMUX:1;         /*!< bit:     28  Write PMUX                         */
+    uint32_t :1;               /*!< bit:     29  Reserved                           */
+    uint32_t WRPINCFG:1;       /*!< bit:     30  Write PINCFG                       */
+    uint32_t HWSEL:1;          /*!< bit:     31  Half-Word Select                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET        0x28         /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE    0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos   0            /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk   (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
+#define PORT_WRCONFIG_PMUXEN_Pos    16           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN        (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos      17           /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN          (0x1ul << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos    18           /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN        (0x1ul << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos    22           /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR        (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos      24           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk      (0xFul << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value)   ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
+#define PORT_WRCONFIG_WRPMUX_Pos    28           /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX        (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos  30           /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG      (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos     31           /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL         (0x1ul << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK          0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W  8) GROUP Peripheral Multiplexing n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXE:4;          /*!< bit:  0.. 3  Peripheral Multiplexing Even       */
+    uint8_t  PMUXO:4;          /*!< bit:  4.. 7  Peripheral Multiplexing Odd        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET            0x30         /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
+#define PORT_PMUX_RESETVALUE        0x00ul       /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
+
+#define PORT_PMUX_PMUXE_Pos         0            /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
+#define PORT_PMUX_PMUXE_Msk         (0xFul << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value)      ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
+#define   PORT_PMUX_PMUXE_A_Val           0x0ul  /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define   PORT_PMUX_PMUXE_B_Val           0x1ul  /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define   PORT_PMUX_PMUXE_C_Val           0x2ul  /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define   PORT_PMUX_PMUXE_D_Val           0x3ul  /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define   PORT_PMUX_PMUXE_E_Val           0x4ul  /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define   PORT_PMUX_PMUXE_F_Val           0x5ul  /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define   PORT_PMUX_PMUXE_G_Val           0x6ul  /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define   PORT_PMUX_PMUXE_H_Val           0x7ul  /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXE_A           (PORT_PMUX_PMUXE_A_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_B           (PORT_PMUX_PMUXE_B_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_C           (PORT_PMUX_PMUXE_C_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_D           (PORT_PMUX_PMUXE_D_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_E           (PORT_PMUX_PMUXE_E_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_F           (PORT_PMUX_PMUXE_F_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_G           (PORT_PMUX_PMUXE_G_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_H           (PORT_PMUX_PMUXE_H_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXO_Pos         4            /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
+#define PORT_PMUX_PMUXO_Msk         (0xFul << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value)      ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
+#define   PORT_PMUX_PMUXO_A_Val           0x0ul  /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define   PORT_PMUX_PMUXO_B_Val           0x1ul  /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define   PORT_PMUX_PMUXO_C_Val           0x2ul  /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define   PORT_PMUX_PMUXO_D_Val           0x3ul  /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define   PORT_PMUX_PMUXO_E_Val           0x4ul  /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define   PORT_PMUX_PMUXO_F_Val           0x5ul  /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define   PORT_PMUX_PMUXO_G_Val           0x6ul  /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define   PORT_PMUX_PMUXO_H_Val           0x7ul  /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXO_A           (PORT_PMUX_PMUXO_A_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_B           (PORT_PMUX_PMUXO_B_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_C           (PORT_PMUX_PMUXO_C_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_D           (PORT_PMUX_PMUXO_D_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_E           (PORT_PMUX_PMUXO_E_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_F           (PORT_PMUX_PMUXO_F_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_G           (PORT_PMUX_PMUXO_G_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_H           (PORT_PMUX_PMUXO_H_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_MASK              0xFFul       /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W  8) GROUP Pin Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXEN:1;         /*!< bit:      0  Peripheral Multiplexer Enable      */
+    uint8_t  INEN:1;           /*!< bit:      1  Input Enable                       */
+    uint8_t  PULLEN:1;         /*!< bit:      2  Pull Enable                        */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  DRVSTR:1;         /*!< bit:      6  Output Driver Strength Selection   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET          0x40         /**< \brief (PORT_PINCFG offset) Pin Configuration n */
+#define PORT_PINCFG_RESETVALUE      0x00ul       /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
+
+#define PORT_PINCFG_PMUXEN_Pos      0            /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN          (0x1ul << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos        1            /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN            (0x1ul << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos      2            /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN          (0x1ul << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos      6            /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR          (0x1ul << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK            0x47ul       /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PORT_DIR_Type             DIR;         /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+  __IO PORT_DIRCLR_Type          DIRCLR;      /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+  __IO PORT_DIRSET_Type          DIRSET;      /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+  __IO PORT_DIRTGL_Type          DIRTGL;      /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+  __IO PORT_OUT_Type             OUT;         /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+  __IO PORT_OUTCLR_Type          OUTCLR;      /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+  __IO PORT_OUTSET_Type          OUTSET;      /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+  __IO PORT_OUTTGL_Type          OUTTGL;      /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+  __I  PORT_IN_Type              IN;          /**< \brief Offset: 0x20 (R/  32) Data Input Value */
+  __IO PORT_CTRL_Type            CTRL;        /**< \brief Offset: 0x24 (R/W 32) Control */
+  __O  PORT_WRCONFIG_Type        WRCONFIG;    /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+       RoReg8                    Reserved1[0x4];
+  __IO PORT_PMUX_Type            PMUX[16];    /**< \brief Offset: 0x30 (R/W  8) Peripheral Multiplexing n */
+  __IO PORT_PINCFG_Type          PINCFG[32];  /**< \brief Offset: 0x40 (R/W  8) Pin Configuration n */
+       RoReg8                    Reserved2[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       PortGroup                 Group[2];    /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_PORT_IOBUS
+
+/*@}*/
+
+#endif /* _SAMD20_PORT_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/rtc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/rtc.h
new file mode 100644
index 0000000000..018d25e194
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/rtc.h
@@ -0,0 +1,1065 @@
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_RTC_COMPONENT_
+#define _SAMD20_RTC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAMD20_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2202
+#define REV_RTC                     0x101
+
+/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
+#define RTC_MODE0_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
+
+#define RTC_MODE0_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE0_CTRL) Software Reset */
+#define RTC_MODE0_CTRL_SWRST        (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
+#define RTC_MODE0_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE0_CTRL) Enable */
+#define RTC_MODE0_CTRL_ENABLE       (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
+#define RTC_MODE0_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE0_CTRL) Operating Mode */
+#define RTC_MODE0_CTRL_MODE_Msk     (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE(value)  ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)))
+#define   RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE0_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_CLOCK   (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE0_CTRL) Clear on Match */
+#define RTC_MODE0_CTRL_MATCHCLR     (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE0_CTRL) Prescaler */
+#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)))
+#define   RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_MASK         0x0F8Ful     /**< \brief (RTC_MODE0_CTRL) MASK Register */
+
+/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
+#define RTC_MODE1_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
+
+#define RTC_MODE1_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE1_CTRL) Software Reset */
+#define RTC_MODE1_CTRL_SWRST        (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
+#define RTC_MODE1_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE1_CTRL) Enable */
+#define RTC_MODE1_CTRL_ENABLE       (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
+#define RTC_MODE1_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE1_CTRL) Operating Mode */
+#define RTC_MODE1_CTRL_MODE_Msk     (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE(value)  ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)))
+#define   RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE1_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_CLOCK   (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE1_CTRL) Prescaler */
+#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)))
+#define   RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_MASK         0x0F0Ful     /**< \brief (RTC_MODE1_CTRL) MASK Register */
+
+/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint16_t CLKREP:1;         /*!< bit:      6  Clock Representation               */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
+#define RTC_MODE2_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
+
+#define RTC_MODE2_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE2_CTRL) Software Reset */
+#define RTC_MODE2_CTRL_SWRST        (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
+#define RTC_MODE2_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE2_CTRL) Enable */
+#define RTC_MODE2_CTRL_ENABLE       (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
+#define RTC_MODE2_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE2_CTRL) Operating Mode */
+#define RTC_MODE2_CTRL_MODE_Msk     (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE(value)  ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)))
+#define   RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE2_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_CLOCK   (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_CLKREP_Pos   6            /**< \brief (RTC_MODE2_CTRL) Clock Representation */
+#define RTC_MODE2_CTRL_CLKREP       (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
+#define RTC_MODE2_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE2_CTRL) Clear on Match */
+#define RTC_MODE2_CTRL_MATCHCLR     (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE2_CTRL) Prescaler */
+#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)))
+#define   RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_MASK         0x0FCFul     /**< \brief (RTC_MODE2_CTRL) MASK Register */
+
+/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ADDR:6;           /*!< bit:  0.. 5  Address                            */
+    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
+    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
+    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_READREQ_OFFSET          0x02         /**< \brief (RTC_READREQ offset) Read Request */
+#define RTC_READREQ_RESETVALUE      0x0010ul     /**< \brief (RTC_READREQ reset_value) Read Request */
+
+#define RTC_READREQ_ADDR_Pos        0            /**< \brief (RTC_READREQ) Address */
+#define RTC_READREQ_ADDR_Msk        (0x3Ful << RTC_READREQ_ADDR_Pos)
+#define RTC_READREQ_ADDR(value)     ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)))
+#define RTC_READREQ_RCONT_Pos       14           /**< \brief (RTC_READREQ) Read Continuously */
+#define RTC_READREQ_RCONT           (0x1ul << RTC_READREQ_RCONT_Pos)
+#define RTC_READREQ_RREQ_Pos        15           /**< \brief (RTC_READREQ) Read Request */
+#define RTC_READREQ_RREQ            (0x1ul << RTC_READREQ_RREQ_Pos)
+#define RTC_READREQ_MASK            0xC03Ful     /**< \brief (RTC_READREQ) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t CMPEO:1;          /*!< bit:      8  Compare x Event Output Enable      */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0     (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1     (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2     (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3     (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4     (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5     (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6     (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7     (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0     (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk  (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)))
+#define RTC_MODE0_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO      (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_MASK       0x81FFul     /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint16_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
+    uint16_t :5;               /*!< bit: 10..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t CMPEO:2;          /*!< bit:  8.. 9  Compare x Event Output Enable      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0     (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1     (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2     (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3     (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4     (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5     (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6     (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7     (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0     (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1     (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk  (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)))
+#define RTC_MODE1_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO      (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_MASK       0x83FFul     /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t ALARMEO0:1;       /*!< bit:      8  Alarm 0 Event Output Enable        */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t ALARMEO:1;        /*!< bit:      8  Alarm x Event Output Enable        */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0     (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1     (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2     (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3     (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4     (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5     (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6     (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7     (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0   (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)))
+#define RTC_MODE2_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO      (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_MASK       0x81FFul     /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0     (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk  (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)))
+#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF      (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK     0xC1ul       /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0     (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1     (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk  (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)))
+#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF      (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK     0xC3ul       /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0   (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)))
+#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF      (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK     0xC1ul       /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0     (1 << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk  (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)))
+#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENSET_SYNCRDY  (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF      (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK     0xC1ul       /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0     (1 << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1     (1 << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk  (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)))
+#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENSET_SYNCRDY  (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF      (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK     0xC3ul       /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0   (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)))
+#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENSET_SYNCRDY  (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF      (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK     0xC1ul       /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0      (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk   (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)))
+#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
+#define RTC_MODE0_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF       (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK      0xC1ul       /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1                          */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x                          */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0      (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos  1            /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1      (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk   (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)))
+#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
+#define RTC_MODE1_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF       (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK      0xC3ul       /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0                            */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x                            */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0    (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)))
+#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
+#define RTC_MODE2_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF       (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK      0xC1ul       /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W  8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_STATUS_OFFSET           0x0A         /**< \brief (RTC_STATUS offset) Status */
+#define RTC_STATUS_RESETVALUE       0x00ul       /**< \brief (RTC_STATUS reset_value) Status */
+
+#define RTC_STATUS_SYNCBUSY_Pos     7            /**< \brief (RTC_STATUS) Synchronization Busy */
+#define RTC_STATUS_SYNCBUSY         (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
+#define RTC_STATUS_MASK             0x80ul       /**< \brief (RTC_STATUS) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET          0x0B         /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN          (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK            0x01ul       /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W  8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:7;          /*!< bit:  0.. 6  Correction Value                   */
+    uint8_t  SIGN:1;           /*!< bit:      7  Correction Sign                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET         0x0C         /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE     0x00ul       /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos      0            /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk      (0x7Ful << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value)   ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)))
+#define RTC_FREQCORR_SIGN_Pos       7            /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN           (0x1ul << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK           0xFFul       /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk   (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)))
+#define RTC_MODE0_COUNT_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE  0x0000ul     /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk   (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)))
+#define RTC_MODE1_COUNT_MASK        0xFFFFul     /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET      0x10         /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos  0            /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk  (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)))
+#define RTC_MODE2_CLOCK_MINUTE_Pos  6            /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk  (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)))
+#define RTC_MODE2_CLOCK_HOUR_Pos    12           /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk    (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)))
+#define   RTC_MODE2_CLOCK_HOUR_PM_Val     0x10ul  /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
+#define RTC_MODE2_CLOCK_HOUR_PM     (RTC_MODE2_CLOCK_HOUR_PM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos     17           /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk     (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value)  ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)))
+#define RTC_MODE2_CLOCK_MONTH_Pos   22           /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk   (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)))
+#define RTC_MODE2_CLOCK_YEAR_Pos    26           /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk    (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)))
+#define RTC_MODE2_CLOCK_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER:16;           /*!< bit:  0..15  Counter Period                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET        0x14         /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE    0x0000ul     /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos       0            /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk       (0xFFFFul << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value)    ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)))
+#define RTC_MODE1_PER_MASK          0xFFFFul     /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COMP:32;          /*!< bit:  0..31  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET       0x18         /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE   0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos     0            /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk     (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value)  ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)))
+#define RTC_MODE0_COMP_MASK         0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMP:16;          /*!< bit:  0..15  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET       0x18         /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos     0            /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk     (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value)  ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)))
+#define RTC_MODE1_COMP_MASK         0xFFFFul     /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET      0x18         /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos  0            /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk  (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)))
+#define RTC_MODE2_ALARM_MINUTE_Pos  6            /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk  (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)))
+#define RTC_MODE2_ALARM_HOUR_Pos    12           /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk    (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)))
+#define RTC_MODE2_ALARM_DAY_Pos     17           /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk     (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value)  ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)))
+#define RTC_MODE2_ALARM_MONTH_Pos   22           /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk   (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)))
+#define RTC_MODE2_ALARM_YEAR_Pos    26           /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk    (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)))
+#define RTC_MODE2_ALARM_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W  8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SEL:3;            /*!< bit:  0.. 2  Alarm Mask Selection               */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET       0x1C         /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE   0x00ul       /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos      0            /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk      (0x7ul << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value)   ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)))
+#define   RTC_MODE2_MASK_SEL_OFF_Val      0x0ul  /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define   RTC_MODE2_MASK_SEL_SS_Val       0x1ul  /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define   RTC_MODE2_MASK_SEL_MMSS_Val     0x2ul  /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define   RTC_MODE2_MASK_SEL_HHMMSS_Val   0x3ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF      (RTC_MODE2_MASK_SEL_OFF_Val    << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS       (RTC_MODE2_MASK_SEL_SS_Val     << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS     (RTC_MODE2_MASK_SEL_MMSS_Val   << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS   (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK         0x07ul       /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO RTC_MODE2_ALARM_Type      ALARM;       /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+  __IO RTC_MODE2_MASK_Type       MASK;        /**< \brief Offset: 0x04 (R/W  8) MODE2_ALARM Alarm n Mask */
+       RoReg8                    Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+  __IO RTC_MODE0_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE0_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+  __IO RTC_MODE0_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE0 Interrupt Enable Clear */
+  __IO RTC_MODE0_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE0 Interrupt Enable Set */
+  __IO RTC_MODE0_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE0 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE0_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO RTC_MODE0_COMP_Type       COMP[1];     /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+  __IO RTC_MODE1_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE1_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+  __IO RTC_MODE1_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE1 Interrupt Enable Clear */
+  __IO RTC_MODE1_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE1 Interrupt Enable Set */
+  __IO RTC_MODE1_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE1 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE1_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+       RoReg8                    Reserved3[0x2];
+  __IO RTC_MODE1_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+       RoReg8                    Reserved4[0x2];
+  __IO RTC_MODE1_COMP_Type       COMP[2];     /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+  __IO RTC_MODE2_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE2_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+  __IO RTC_MODE2_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE2 Interrupt Enable Clear */
+  __IO RTC_MODE2_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE2 Interrupt Enable Set */
+  __IO RTC_MODE2_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE2 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE2_CLOCK_Type      CLOCK;       /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+       RoReg8                    Reserved3[0x4];
+       RtcMode2Alarm             Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       RtcMode0                  MODE0;       /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+       RtcMode1                  MODE1;       /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+       RtcMode2                  MODE2;       /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_RTC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/sercom.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/sercom.h
new file mode 100644
index 0000000000..d151edebd5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/sercom.h
@@ -0,0 +1,1227 @@
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SERCOM_COMPONENT_
+#define _SAMD20_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAMD20_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM                  0x102
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t :6;               /*!< bit: 22..27  Reserved                           */
+    uint32_t INACTOUT:2;       /*!< bit: 28..29  Inactive Time-out                  */
+    uint32_t LOWTOUT:1;        /*!< bit:     30  SCL Low Time-out                   */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST     (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE    (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk  (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))
+#define   SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY  (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT    (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28           /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))
+#define SERCOM_I2CM_CTRLA_LOWTOUT_Pos 30           /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Time-out */
+#define SERCOM_I2CM_CTRLA_LOWTOUT   (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_MASK      0x7031009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t :8;               /*!< bit: 22..29  Reserved                           */
+    uint32_t LOWTOUT:1;        /*!< bit:     30  SCL Low Time-out                   */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST     (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE    (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk  (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))
+#define   SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CS_CTRLA) Run in Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY  (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT    (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_DIS_Val 0x0ul  /**< \brief (SERCOM_I2CS_CTRLA) Disabled */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_75_Val 0x1ul  /**< \brief (SERCOM_I2CS_CTRLA) 50-100 ns hold time */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_450_Val 0x2ul  /**< \brief (SERCOM_I2CS_CTRLA) 300-600 ns hold time */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_600_Val 0x3ul  /**< \brief (SERCOM_I2CS_CTRLA) 400-800 ns hold time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_DIS (SERCOM_I2CS_CTRLA_SDAHOLD_DIS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_75 (SERCOM_I2CS_CTRLA_SDAHOLD_75_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_450 (SERCOM_I2CS_CTRLA_SDAHOLD_450_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_600 (SERCOM_I2CS_CTRLA_SDAHOLD_600_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUT_Pos 30           /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Time-out */
+#define SERCOM_I2CS_CTRLA_LOWTOUT   (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUT_Pos)
+#define SERCOM_I2CS_CTRLA_MASK      0x4031009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run In Standby                     */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t DOPO:2;           /*!< bit: 16..17  Data Out Pinout                    */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t DIPO:2;           /*!< bit: 20..21  Data In Pinout                     */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CPHA:1;           /*!< bit:     28  Clock Phase                        */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET     0x00         /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos  0            /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST      (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE     (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos   2            /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk   (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))
+#define   SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
+#define   SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
+#define   SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_SPI_CTRLA) Run In Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY   (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos   8            /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON       (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos   16           /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk   (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)))
+#define SERCOM_SPI_CTRLA_DIPO_Pos   20           /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk   (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))
+#define SERCOM_SPI_CTRLA_FORM_Pos   24           /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk   (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))
+#define   SERCOM_SPI_CTRLA_FORM_SPI_Val   0x0ul  /**< \brief (SERCOM_SPI_CTRLA) SPI frame */
+#define   SERCOM_SPI_CTRLA_FORM_SPI_ADDR_Val 0x2ul  /**< \brief (SERCOM_SPI_CTRLA) SPI frame with address */
+#define SERCOM_SPI_CTRLA_FORM_SPI   (SERCOM_SPI_CTRLA_FORM_SPI_Val << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM_SPI_ADDR (SERCOM_SPI_CTRLA_FORM_SPI_ADDR_Val << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_CPHA_Pos   28           /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA       (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos   29           /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL       (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos   30           /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD       (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK       0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run In Standby                     */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t TXPO:1;           /*!< bit:     16  Transmit Data Pinout               */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t RXPO:2;           /*!< bit: 20..21  Receive Data Pinout                */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CMODE:1;          /*!< bit:     28  Communication Mode                 */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET   0x00         /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST    (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE   (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2            /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))
+#define   SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
+#define   SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
+#define   SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_USART_CTRLA) Run In Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8            /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON     (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_TXPO_Pos 16           /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO     (0x1ul << SERCOM_USART_CTRLA_TXPO_Pos)
+#define   SERCOM_USART_CTRLA_TXPO_PAD0_Val 0x0ul  /**< \brief (SERCOM_USART_CTRLA) TXD at PAD0, XCK at PAD1 */
+#define   SERCOM_USART_CTRLA_TXPO_PAD2_Val 0x1ul  /**< \brief (SERCOM_USART_CTRLA) TXD at PAD2, XCK at PAD3 */
+#define SERCOM_USART_CTRLA_TXPO_PAD0 (SERCOM_USART_CTRLA_TXPO_PAD0_Val << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO_PAD2 (SERCOM_USART_CTRLA_TXPO_PAD2_Val << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO_Pos 20           /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
+#define   SERCOM_USART_CTRLA_RXPO_PAD0_Val 0x0ul  /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD0 */
+#define   SERCOM_USART_CTRLA_RXPO_PAD1_Val 0x1ul  /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD1 */
+#define   SERCOM_USART_CTRLA_RXPO_PAD2_Val 0x2ul  /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD2 */
+#define   SERCOM_USART_CTRLA_RXPO_PAD3_Val 0x3ul  /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD3 */
+#define SERCOM_USART_CTRLA_RXPO_PAD0 (SERCOM_USART_CTRLA_RXPO_PAD0_Val << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO_PAD1 (SERCOM_USART_CTRLA_RXPO_PAD1_Val << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO_PAD2 (SERCOM_USART_CTRLA_RXPO_PAD2_Val << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO_PAD3 (SERCOM_USART_CTRLA_RXPO_PAD3_Val << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_FORM_Pos 24           /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))
+#define   SERCOM_USART_CTRLA_FORM_0_Val   0x0ul  /**< \brief (SERCOM_USART_CTRLA) USART frame */
+#define   SERCOM_USART_CTRLA_FORM_1_Val   0x1ul  /**< \brief (SERCOM_USART_CTRLA) USART frame with parity */
+#define SERCOM_USART_CTRLA_FORM_0   (SERCOM_USART_CTRLA_FORM_0_Val << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM_1   (SERCOM_USART_CTRLA_FORM_1_Val << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_CMODE_Pos 28           /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE    (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29           /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL     (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30           /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD     (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK     0x7F31019Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t QCEN:1;           /*!< bit:      9  Quick Command Enable               */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN      (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos  9            /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN      (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk   (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT    (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK      0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t :5;               /*!< bit:  9..13  Reserved                           */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN      (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14           /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))
+#define SERCOM_I2CS_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk   (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT    (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK      0x0007C100ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t PLOADEN:1;        /*!< bit:      6  Slave Data Preload Enable          */
+    uint32_t :7;               /*!< bit:  7..13  Reserved                           */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET     0x04         /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6            /**< \brief (SERCOM_SPI_CTRLB) Slave Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN    (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos  14           /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk  (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))
+#define   SERCOM_SPI_CTRLB_AMODE_MASK_Val 0x0ul  /**< \brief (SERCOM_SPI_CTRLB) ADDRMASK is used as a mask to the ADDR register. */
+#define   SERCOM_SPI_CTRLB_AMODE_2ADDR_Val 0x1ul  /**< \brief (SERCOM_SPI_CTRLB) The slave responds to the 2 unique addresses in ADDR and ADDRMASK. */
+#define   SERCOM_SPI_CTRLB_AMODE_RANGE_Val 0x2ul  /**< \brief (SERCOM_SPI_CTRLB) The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. */
+#define SERCOM_SPI_CTRLB_AMODE_MASK (SERCOM_SPI_CTRLB_AMODE_MASK_Val << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_2ADDR (SERCOM_SPI_CTRLB_AMODE_2ADDR_Val << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_RANGE (SERCOM_SPI_CTRLB_AMODE_RANGE_Val << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_RXEN_Pos   17           /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN       (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK       0x0002C047ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t SBMODE:1;         /*!< bit:      6  Stop Bit Mode                      */
+    uint32_t :2;               /*!< bit:  7.. 8  Reserved                           */
+    uint32_t SFDE:1;           /*!< bit:      9  Start of Frame Detection Enable    */
+    uint32_t :3;               /*!< bit: 10..12  Reserved                           */
+    uint32_t PMODE:1;          /*!< bit:     13  Parity Mode                        */
+    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
+    uint32_t TXEN:1;           /*!< bit:     16  Transmitter Enable                 */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET   0x04         /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6            /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE   (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9            /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE     (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13           /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE    (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16           /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN     (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17           /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN     (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_MASK     0x00032247ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x08) (R/W  8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Stop Mode                    */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET  0x08         /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Stop Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK    0x01ul       /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x08) (R/W  8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Stop Mode                    */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET   0x08         /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_SPI_DBGCTRL) Debug Stop Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP  (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK     0x01ul       /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x08) (R/W  8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Stop Mode                    */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x08         /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_USART_DBGCTRL) Debug Stop Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK   0x01ul       /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0A) (R/W 16) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BAUD:8;           /*!< bit:  0.. 7  Master Baud Rate                   */
+    uint16_t BAUDLOW:8;        /*!< bit:  8..15  Master Baud Rate Low               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET     0x0A         /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos   0            /**< \brief (SERCOM_I2CM_BAUD) Master Baud Rate */
+#define SERCOM_I2CM_BAUD_BAUD_Msk   (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8            /**< \brief (SERCOM_I2CM_BAUD) Master Baud Rate Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))
+#define SERCOM_I2CM_BAUD_MASK       0xFFFFul     /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0A) (R/W  8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BAUD:8;           /*!< bit:  0.. 7  Baud Register                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET      0x0A         /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE  0x00ul       /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos    0            /**< \brief (SERCOM_SPI_BAUD) Baud Register */
+#define SERCOM_SPI_BAUD_BAUD_Msk    (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))
+#define SERCOM_SPI_BAUD_MASK        0xFFul       /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0A) (R/W 16) USART USART Baud -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET    0x0A         /**< \brief (SERCOM_USART_BAUD offset) USART Baud */
+#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud */
+
+#define SERCOM_USART_BAUD_BAUD_Pos  0            /**< \brief (SERCOM_USART_BAUD) Baud Value */
+#define SERCOM_USART_BAUD_BAUD_Msk  (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))
+#define SERCOM_USART_BAUD_MASK      0xFFFFul     /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x0C) (R/W  8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master on Bus Interrupt Enable     */
+    uint8_t  SB:1;             /*!< bit:      1  Slave on Bus Interrupt Enable      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x0C         /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENCLR) Master on Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENCLR_MB     (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENCLR) Slave on Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENCLR_SB     (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK   0x03ul       /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x0C) (R/W  8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Ready Interrupt Enable        */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x0C         /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENCLR_PREC   (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENCLR) Data Ready Interrupt Enable */
+#define SERCOM_I2CS_INTENCLR_DRDY   (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK   0x07ul       /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x0C) (R/W  8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET  0x0C         /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENCLR_DRE     (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENCLR_TXC     (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENCLR_RXC     (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_MASK    0x07ul       /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x0C) (R/W  8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Disable    */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x0C         /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENCLR_DRE   (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENCLR_TXC   (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENCLR_RXC   (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS   (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_MASK  0x0Ful       /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x0D) (R/W  8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master on Bus Interrupt Enable     */
+    uint8_t  SB:1;             /*!< bit:      1  Slave on Bus Interrupt Enable      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x0D         /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENSET) Master on Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB     (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENSET) Slave on Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB     (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_MASK   0x03ul       /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x0D) (R/W  8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Ready Interrupt Enable        */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x0D         /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC   (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENSET) Data Ready Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY   (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_MASK   0x07ul       /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x0D) (R/W  8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET  0x0D         /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE     (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC     (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC     (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_MASK    0x07ul       /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x0D) (R/W  8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Enable     */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x0D         /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE   (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC   (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC   (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS   (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_MASK  0x0Ful       /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x0E) (R/W  8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master on Bus                      */
+    uint8_t  SB:1;             /*!< bit:      1  Slave on Bus                       */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET  0x0E         /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos  0            /**< \brief (SERCOM_I2CM_INTFLAG) Master on Bus */
+#define SERCOM_I2CM_INTFLAG_MB      (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos  1            /**< \brief (SERCOM_I2CM_INTFLAG) Slave on Bus */
+#define SERCOM_I2CM_INTFLAG_SB      (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK    0x03ul       /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x0E) (R/W  8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received                      */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match                      */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Ready                         */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET  0x0E         /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received */
+#define SERCOM_I2CS_INTFLAG_PREC    (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTFLAG) Address Match */
+#define SERCOM_I2CS_INTFLAG_AMATCH  (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTFLAG) Data Ready */
+#define SERCOM_I2CS_INTFLAG_DRDY    (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK    0x07ul       /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x0E) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty                */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete                  */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete                   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET   0x0E         /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos  0            /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty */
+#define SERCOM_SPI_INTFLAG_DRE      (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos  1            /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete */
+#define SERCOM_SPI_INTFLAG_TXC      (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos  2            /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete */
+#define SERCOM_SPI_INTFLAG_RXC      (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_MASK     0x07ul       /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x0E) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty                */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete                  */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete                   */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x0E         /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0            /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty */
+#define SERCOM_USART_INTFLAG_DRE    (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1            /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete */
+#define SERCOM_USART_INTFLAG_TXC    (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2            /**< \brief (SERCOM_USART_INTFLAG) Receive Complete */
+#define SERCOM_USART_INTFLAG_RXC    (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3            /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS    (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_MASK   0x0Ful       /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x10) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t ARBLOST:1;        /*!< bit:      1  Arbitration Lost                   */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t BUSSTATE:2;       /*!< bit:  4.. 5  Bus State                          */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Time-out                   */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t :7;               /*!< bit:  8..14  Reserved                           */
+    uint16_t SYNCBUSY:1;       /*!< bit:     15  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET   0x10         /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR   (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1            /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST  (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK   (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4            /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CM_STATUS) SCL Low Time-out */
+#define SERCOM_I2CM_STATUS_LOWTOUT  (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD  (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_SYNCBUSY_Pos 15           /**< \brief (SERCOM_I2CM_STATUS) Synchronization Busy */
+#define SERCOM_I2CM_STATUS_SYNCBUSY (0x1ul << SERCOM_I2CM_STATUS_SYNCBUSY_Pos)
+#define SERCOM_I2CM_STATUS_MASK     0x80F7ul     /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x10) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t COLL:1;           /*!< bit:      1  Transmit Collision                 */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t DIR:1;            /*!< bit:      3  Read / Write Direction             */
+    uint16_t SR:1;             /*!< bit:      4  Repeated Start                     */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Time-out                   */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t :7;               /*!< bit:  8..14  Reserved                           */
+    uint16_t SYNCBUSY:1;       /*!< bit:     15  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET   0x10         /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR   (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1            /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL     (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK   (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos  3            /**< \brief (SERCOM_I2CS_STATUS) Read / Write Direction */
+#define SERCOM_I2CS_STATUS_DIR      (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos   4            /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR       (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CS_STATUS) SCL Low Time-out */
+#define SERCOM_I2CS_STATUS_LOWTOUT  (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD  (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SYNCBUSY_Pos 15           /**< \brief (SERCOM_I2CS_STATUS) Synchronization Busy */
+#define SERCOM_I2CS_STATUS_SYNCBUSY (0x1ul << SERCOM_I2CS_STATUS_SYNCBUSY_Pos)
+#define SERCOM_I2CS_STATUS_MASK     0x80DFul     /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x10) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t :12;              /*!< bit:  3..14  Reserved                           */
+    uint16_t SYNCBUSY:1;       /*!< bit:     15  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET    0x10         /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF    (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_SYNCBUSY_Pos 15           /**< \brief (SERCOM_SPI_STATUS) Synchronization Busy */
+#define SERCOM_SPI_STATUS_SYNCBUSY  (0x1ul << SERCOM_SPI_STATUS_SYNCBUSY_Pos)
+#define SERCOM_SPI_STATUS_MASK      0x8004ul     /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x10) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PERR:1;           /*!< bit:      0  Parity Error                       */
+    uint16_t FERR:1;           /*!< bit:      1  Frame Error                        */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t :12;              /*!< bit:  3..14  Reserved                           */
+    uint16_t SYNCBUSY:1;       /*!< bit:     15  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET  0x10         /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0            /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR    (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1            /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR    (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF  (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_SYNCBUSY_Pos 15           /**< \brief (SERCOM_USART_STATUS) Synchronization Busy */
+#define SERCOM_USART_STATUS_SYNCBUSY (0x1ul << SERCOM_USART_STATUS_SYNCBUSY_Pos)
+#define SERCOM_USART_STATUS_MASK    0x8007ul     /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x14) (R/W  8) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ADDR:8;           /*!< bit:  0.. 7  Address                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET     0x14         /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos   0            /**< \brief (SERCOM_I2CM_ADDR) Address */
+#define SERCOM_I2CM_ADDR_ADDR_Msk   (0xFFul << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))
+#define SERCOM_I2CM_ADDR_MASK       0xFFul       /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x14) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GENCEN:1;         /*!< bit:      0  General Call Address Enable        */
+    uint32_t ADDR:7;           /*!< bit:  1.. 7  Address                            */
+    uint32_t :9;               /*!< bit:  8..16  Reserved                           */
+    uint32_t ADDRMASK:7;       /*!< bit: 17..23  Address Mask                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET     0x14         /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0            /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN     (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos   1            /**< \brief (SERCOM_I2CS_ADDR) Address */
+#define SERCOM_I2CS_ADDR_ADDR_Msk   (0x7Ful << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17           /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x7Ful << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))
+#define SERCOM_I2CS_ADDR_MASK       0x00FE00FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x14) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:8;           /*!< bit:  0.. 7  Address                            */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t ADDRMASK:8;       /*!< bit: 16..23  Address Mask                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET      0x14         /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE  0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos    0            /**< \brief (SERCOM_SPI_ADDR) Address */
+#define SERCOM_SPI_ADDR_ADDR_Msk    (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16           /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))
+#define SERCOM_SPI_ADDR_MASK        0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x18) (R/W  8) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET     0x18         /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CM_DATA) Data */
+#define SERCOM_I2CM_DATA_DATA_Msk   (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))
+#define SERCOM_I2CM_DATA_MASK       0xFFul       /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x18) (R/W  8) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET     0x18         /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CS_DATA) Data */
+#define SERCOM_I2CS_DATA_DATA_Msk   (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))
+#define SERCOM_I2CS_DATA_MASK       0xFFul       /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x18) (R/W 16) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:9;           /*!< bit:  0.. 8  Data                               */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET      0x18         /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE  0x0000ul     /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos    0            /**< \brief (SERCOM_SPI_DATA) Data */
+#define SERCOM_SPI_DATA_DATA_Msk    (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))
+#define SERCOM_SPI_DATA_MASK        0x01FFul     /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x18) (R/W 16) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:9;           /*!< bit:  0.. 8  Data                               */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET    0x18         /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos  0            /**< \brief (SERCOM_USART_DATA) Data */
+#define SERCOM_USART_DATA_DATA_Msk  (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))
+#define SERCOM_USART_DATA_MASK      0x01FFul     /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+  __IO SERCOM_I2CM_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+  __IO SERCOM_I2CM_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+  __IO SERCOM_I2CM_DBGCTRL_Type  DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) I2CM Debug Control */
+       RoReg8                    Reserved1[0x1];
+  __IO SERCOM_I2CM_BAUD_Type     BAUD;        /**< \brief Offset: 0x0A (R/W 16) I2CM Baud Rate */
+  __IO SERCOM_I2CM_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) I2CM Interrupt Enable Clear */
+  __IO SERCOM_I2CM_INTENSET_Type INTENSET;    /**< \brief Offset: 0x0D (R/W  8) I2CM Interrupt Enable Set */
+  __IO SERCOM_I2CM_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) I2CM Interrupt Flag Status and Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_I2CM_STATUS_Type   STATUS;      /**< \brief Offset: 0x10 (R/W 16) I2CM Status */
+       RoReg8                    Reserved3[0x2];
+  __IO SERCOM_I2CM_ADDR_Type     ADDR;        /**< \brief Offset: 0x14 (R/W  8) I2CM Address */
+       RoReg8                    Reserved4[0x3];
+  __IO SERCOM_I2CM_DATA_Type     DATA;        /**< \brief Offset: 0x18 (R/W  8) I2CM Data */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+  __IO SERCOM_I2CS_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+  __IO SERCOM_I2CS_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_I2CS_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) I2CS Interrupt Enable Clear */
+  __IO SERCOM_I2CS_INTENSET_Type INTENSET;    /**< \brief Offset: 0x0D (R/W  8) I2CS Interrupt Enable Set */
+  __IO SERCOM_I2CS_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) I2CS Interrupt Flag Status and Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_I2CS_STATUS_Type   STATUS;      /**< \brief Offset: 0x10 (R/W 16) I2CS Status */
+       RoReg8                    Reserved3[0x2];
+  __IO SERCOM_I2CS_ADDR_Type     ADDR;        /**< \brief Offset: 0x14 (R/W 32) I2CS Address */
+  __IO SERCOM_I2CS_DATA_Type     DATA;        /**< \brief Offset: 0x18 (R/W  8) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+  __IO SERCOM_SPI_CTRLA_Type     CTRLA;       /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+  __IO SERCOM_SPI_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+  __IO SERCOM_SPI_DBGCTRL_Type   DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) SPI Debug Control */
+       RoReg8                    Reserved1[0x1];
+  __IO SERCOM_SPI_BAUD_Type      BAUD;        /**< \brief Offset: 0x0A (R/W  8) SPI Baud Rate */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_SPI_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) SPI Interrupt Enable Clear */
+  __IO SERCOM_SPI_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x0D (R/W  8) SPI Interrupt Enable Set */
+  __IO SERCOM_SPI_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) SPI Interrupt Flag Status and Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_SPI_STATUS_Type    STATUS;      /**< \brief Offset: 0x10 (R/W 16) SPI Status */
+       RoReg8                    Reserved4[0x2];
+  __IO SERCOM_SPI_ADDR_Type      ADDR;        /**< \brief Offset: 0x14 (R/W 32) SPI Address */
+  __IO SERCOM_SPI_DATA_Type      DATA;        /**< \brief Offset: 0x18 (R/W 16) SPI Data */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+  __IO SERCOM_USART_CTRLA_Type   CTRLA;       /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+  __IO SERCOM_USART_CTRLB_Type   CTRLB;       /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+  __IO SERCOM_USART_DBGCTRL_Type DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) USART Debug Control */
+       RoReg8                    Reserved1[0x1];
+  __IO SERCOM_USART_BAUD_Type    BAUD;        /**< \brief Offset: 0x0A (R/W 16) USART Baud */
+  __IO SERCOM_USART_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) USART Interrupt Enable Clear */
+  __IO SERCOM_USART_INTENSET_Type INTENSET;    /**< \brief Offset: 0x0D (R/W  8) USART Interrupt Enable Set */
+  __IO SERCOM_USART_INTFLAG_Type INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) USART Interrupt Flag Status and Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_USART_STATUS_Type  STATUS;      /**< \brief Offset: 0x10 (R/W 16) USART Status */
+       RoReg8                    Reserved3[0x6];
+  __IO SERCOM_USART_DATA_Type    DATA;        /**< \brief Offset: 0x18 (R/W 16) USART Data */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       SercomI2cm                I2CM;        /**< \brief Offset: 0x00 I2C Master Mode */
+       SercomI2cs                I2CS;        /**< \brief Offset: 0x00 I2C Slave Mode */
+       SercomSpi                 SPI;         /**< \brief Offset: 0x00 SPI Mode */
+       SercomUsart               USART;       /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_SERCOM_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/sysctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/sysctrl.h
new file mode 100644
index 0000000000..23609655c0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/sysctrl.h
@@ -0,0 +1,691 @@
+/**
+ * \file
+ *
+ * \brief Component description for SYSCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SYSCTRL_COMPONENT_
+#define _SAMD20_SYSCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SYSCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD20_SYSCTRL System Control */
+/*@{*/
+
+#define SYSCTRL_U2100
+#define REV_SYSCTRL                 0x201
+
+/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENCLR_OFFSET     0x00         /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENCLR) XOSC Ready */
+#define SYSCTRL_INTENCLR_XOSCRDY    (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos)
+#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready */
+#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready */
+#define SYSCTRL_INTENCLR_OSC32KRDY  (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready */
+#define SYSCTRL_INTENCLR_OSC8MRDY   (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENCLR) DFLL Ready */
+#define SYSCTRL_INTENCLR_DFLLRDY    (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds */
+#define SYSCTRL_INTENCLR_DFLLOOB    (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine */
+#define SYSCTRL_INTENCLR_DFLLLCKF   (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse */
+#define SYSCTRL_INTENCLR_DFLLLCKC   (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
+#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTENCLR_DFLLRCS    (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos)
+#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready */
+#define SYSCTRL_INTENCLR_BOD33RDY   (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos)
+#define SYSCTRL_INTENCLR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection */
+#define SYSCTRL_INTENCLR_BOD33DET   (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos)
+#define SYSCTRL_INTENCLR_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready */
+#define SYSCTRL_INTENCLR_B33SRDY    (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos)
+#define SYSCTRL_INTENCLR_MASK       0x00000FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */
+
+/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENSET_OFFSET     0x04         /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
+#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define SYSCTRL_INTENSET_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENSET) XOSC Ready */
+#define SYSCTRL_INTENSET_XOSCRDY    (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos)
+#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready */
+#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENSET) OSC32K Ready */
+#define SYSCTRL_INTENSET_OSC32KRDY  (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENSET) OSC8M Ready */
+#define SYSCTRL_INTENSET_OSC8MRDY   (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENSET) DFLL Ready */
+#define SYSCTRL_INTENSET_DFLLRDY    (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds */
+#define SYSCTRL_INTENSET_DFLLOOB    (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine */
+#define SYSCTRL_INTENSET_DFLLLCKF   (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse */
+#define SYSCTRL_INTENSET_DFLLLCKC   (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos)
+#define SYSCTRL_INTENSET_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTENSET_DFLLRCS    (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos)
+#define SYSCTRL_INTENSET_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENSET) BOD33 Ready */
+#define SYSCTRL_INTENSET_BOD33RDY   (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos)
+#define SYSCTRL_INTENSET_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENSET) BOD33 Detection */
+#define SYSCTRL_INTENSET_BOD33DET   (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos)
+#define SYSCTRL_INTENSET_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready */
+#define SYSCTRL_INTENSET_B33SRDY    (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos)
+#define SYSCTRL_INTENSET_MASK       0x00000FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */
+
+/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTFLAG_OFFSET      0x08         /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SYSCTRL_INTFLAG_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
+#define SYSCTRL_INTFLAG_XOSCRDY     (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos)
+#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
+#define SYSCTRL_INTFLAG_XOSC32KRDY  (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
+#define SYSCTRL_INTFLAG_OSC32KRDY   (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
+#define SYSCTRL_INTFLAG_OSC8MRDY    (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
+#define SYSCTRL_INTFLAG_DFLLRDY     (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
+#define SYSCTRL_INTFLAG_DFLLOOB     (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
+#define SYSCTRL_INTFLAG_DFLLLCKF    (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
+#define SYSCTRL_INTFLAG_DFLLLCKC    (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
+#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTFLAG_DFLLRCS     (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos)
+#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
+#define SYSCTRL_INTFLAG_BOD33RDY    (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos)
+#define SYSCTRL_INTFLAG_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
+#define SYSCTRL_INTFLAG_BOD33DET    (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos)
+#define SYSCTRL_INTFLAG_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
+#define SYSCTRL_INTFLAG_B33SRDY     (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos)
+#define SYSCTRL_INTFLAG_MASK        0x00000FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */
+
+/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_PCLKSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_PCLKSR_OFFSET       0x0C         /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
+#define SYSCTRL_PCLKSR_RESETVALUE   0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
+
+#define SYSCTRL_PCLKSR_XOSCRDY_Pos  0            /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
+#define SYSCTRL_PCLKSR_XOSCRDY      (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos)
+#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
+#define SYSCTRL_PCLKSR_XOSC32KRDY   (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
+#define SYSCTRL_PCLKSR_OSC32KRDY    (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
+#define SYSCTRL_PCLKSR_OSC8MRDY     (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLRDY_Pos  4            /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
+#define SYSCTRL_PCLKSR_DFLLRDY      (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLOOB_Pos  5            /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
+#define SYSCTRL_PCLKSR_DFLLOOB      (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
+#define SYSCTRL_PCLKSR_DFLLLCKF     (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
+#define SYSCTRL_PCLKSR_DFLLLCKC     (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
+#define SYSCTRL_PCLKSR_DFLLRCS_Pos  8            /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
+#define SYSCTRL_PCLKSR_DFLLRCS      (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos)
+#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
+#define SYSCTRL_PCLKSR_BOD33RDY     (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos)
+#define SYSCTRL_PCLKSR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
+#define SYSCTRL_PCLKSR_BOD33DET     (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos)
+#define SYSCTRL_PCLKSR_B33SRDY_Pos  11           /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
+#define SYSCTRL_PCLKSR_B33SRDY      (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos)
+#define SYSCTRL_PCLKSR_MASK         0x00000FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */
+
+/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) XOSC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  Enable on Demand                   */
+    uint16_t GAIN:3;           /*!< bit:  8..10  Gain Value                         */
+    uint16_t AMPGC:1;          /*!< bit:     11  Automatic Amplitude Gain Control   */
+    uint16_t STARTUP:4;        /*!< bit: 12..15  Start-Up Time                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_XOSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC_OFFSET         0x10         /**< \brief (SYSCTRL_XOSC offset) XOSC Control */
+#define SYSCTRL_XOSC_RESETVALUE     0x0080ul     /**< \brief (SYSCTRL_XOSC reset_value) XOSC Control */
+
+#define SYSCTRL_XOSC_ENABLE_Pos     1            /**< \brief (SYSCTRL_XOSC) Enable */
+#define SYSCTRL_XOSC_ENABLE         (0x1ul << SYSCTRL_XOSC_ENABLE_Pos)
+#define SYSCTRL_XOSC_XTALEN_Pos     2            /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC_XTALEN         (0x1ul << SYSCTRL_XOSC_XTALEN_Pos)
+#define SYSCTRL_XOSC_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_XOSC) Run during Standby */
+#define SYSCTRL_XOSC_RUNSTDBY       (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC_ONDEMAND_Pos   7            /**< \brief (SYSCTRL_XOSC) Enable on Demand */
+#define SYSCTRL_XOSC_ONDEMAND       (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
+#define SYSCTRL_XOSC_GAIN_Pos       8            /**< \brief (SYSCTRL_XOSC) Gain Value */
+#define SYSCTRL_XOSC_GAIN_Msk       (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN(value)    ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
+#define SYSCTRL_XOSC_AMPGC_Pos      11           /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
+#define SYSCTRL_XOSC_AMPGC          (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
+#define SYSCTRL_XOSC_STARTUP_Pos    12           /**< \brief (SYSCTRL_XOSC) Start-Up Time */
+#define SYSCTRL_XOSC_STARTUP_Msk    (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
+#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
+#define SYSCTRL_XOSC_MASK           0xFFC6ul     /**< \brief (SYSCTRL_XOSC) MASK Register */
+
+/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) XOSC32K Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t EN32K:1;          /*!< bit:      3  32kHz Output Enable                */
+    uint16_t EN1K:1;           /*!< bit:      4  1kHz Output Enable                 */
+    uint16_t AAMPEN:1;         /*!< bit:      5  Automatic Amplitude Control Enable */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  Enable on Demand                   */
+    uint16_t STARTUP:3;        /*!< bit:  8..10  Start-Up Time                      */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC32K_OFFSET      0x14         /**< \brief (SYSCTRL_XOSC32K offset) XOSC32K Control */
+#define SYSCTRL_XOSC32K_RESETVALUE  0x0080ul     /**< \brief (SYSCTRL_XOSC32K reset_value) XOSC32K Control */
+
+#define SYSCTRL_XOSC32K_ENABLE_Pos  1            /**< \brief (SYSCTRL_XOSC32K) Enable */
+#define SYSCTRL_XOSC32K_ENABLE      (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos)
+#define SYSCTRL_XOSC32K_XTALEN_Pos  2            /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC32K_XTALEN      (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos)
+#define SYSCTRL_XOSC32K_EN32K_Pos   3            /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN32K       (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos)
+#define SYSCTRL_XOSC32K_EN1K_Pos    4            /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN1K        (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos)
+#define SYSCTRL_XOSC32K_AAMPEN_Pos  5            /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
+#define SYSCTRL_XOSC32K_AAMPEN      (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos)
+#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_XOSC32K) Run during Standby */
+#define SYSCTRL_XOSC32K_RUNSTDBY    (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_XOSC32K) Enable on Demand */
+#define SYSCTRL_XOSC32K_ONDEMAND    (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
+#define SYSCTRL_XOSC32K_STARTUP_Pos 8            /**< \brief (SYSCTRL_XOSC32K) Start-Up Time */
+#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
+#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
+#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12           /**< \brief (SYSCTRL_XOSC32K) Write Lock */
+#define SYSCTRL_XOSC32K_WRTLOCK     (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
+#define SYSCTRL_XOSC32K_MASK        0x17FEul     /**< \brief (SYSCTRL_XOSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) OSC32K Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t EN32K:1;          /*!< bit:      2  32kHz Output Enable                */
+    uint32_t EN1K:1;           /*!< bit:      3  1kHz Output Enable                 */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  Enable on Demand                   */
+    uint32_t STARTUP:3;        /*!< bit:  8..10  Start-Up Time                      */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t CALIB:7;          /*!< bit: 16..22  Calibration Value                  */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_OSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC32K_OFFSET       0x18         /**< \brief (SYSCTRL_OSC32K offset) OSC32K Control */
+#define SYSCTRL_OSC32K_RESETVALUE   0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) OSC32K Control */
+
+#define SYSCTRL_OSC32K_ENABLE_Pos   1            /**< \brief (SYSCTRL_OSC32K) Enable */
+#define SYSCTRL_OSC32K_ENABLE       (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos)
+#define SYSCTRL_OSC32K_EN32K_Pos    2            /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
+#define SYSCTRL_OSC32K_EN32K        (0x1ul << SYSCTRL_OSC32K_EN32K_Pos)
+#define SYSCTRL_OSC32K_EN1K_Pos     3            /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
+#define SYSCTRL_OSC32K_EN1K         (0x1ul << SYSCTRL_OSC32K_EN1K_Pos)
+#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_OSC32K) Run during Standby */
+#define SYSCTRL_OSC32K_RUNSTDBY     (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_OSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_OSC32K) Enable on Demand */
+#define SYSCTRL_OSC32K_ONDEMAND     (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
+#define SYSCTRL_OSC32K_STARTUP_Pos  8            /**< \brief (SYSCTRL_OSC32K) Start-Up Time */
+#define SYSCTRL_OSC32K_STARTUP_Msk  (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
+#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
+#define SYSCTRL_OSC32K_WRTLOCK_Pos  12           /**< \brief (SYSCTRL_OSC32K) Write Lock */
+#define SYSCTRL_OSC32K_WRTLOCK      (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
+#define SYSCTRL_OSC32K_CALIB_Pos    16           /**< \brief (SYSCTRL_OSC32K) Calibration Value */
+#define SYSCTRL_OSC32K_CALIB_Msk    (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
+#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
+#define SYSCTRL_OSC32K_MASK         0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W  8) OSCULP32K Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CALIB:5;          /*!< bit:  0.. 4  Calibration Value                  */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  WRTLOCK:1;        /*!< bit:      7  Write Lock                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSCULP32K_OFFSET    0x1C         /**< \brief (SYSCTRL_OSCULP32K offset) OSCULP32K Control */
+#define SYSCTRL_OSCULP32K_RESETVALUE 0x0Ful       /**< \brief (SYSCTRL_OSCULP32K reset_value) OSCULP32K Control */
+
+#define SYSCTRL_OSCULP32K_CALIB_Pos 0            /**< \brief (SYSCTRL_OSCULP32K) Calibration Value */
+#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
+#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
+#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7            /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
+#define SYSCTRL_OSCULP32K_WRTLOCK   (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
+#define SYSCTRL_OSCULP32K_MASK      0x9Ful       /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
+
+/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) OSC8M Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  Enable on Demand                   */
+    uint32_t PRESC:2;          /*!< bit:  8.. 9  Prescaler Select                   */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CALIB:12;         /*!< bit: 16..27  Calibration Value                  */
+    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
+    uint32_t FRANGE:2;         /*!< bit: 30..31  Frequency Range                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_OSC8M_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC8M_OFFSET        0x20         /**< \brief (SYSCTRL_OSC8M offset) OSC8M Control A */
+#define SYSCTRL_OSC8M_RESETVALUE    0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) OSC8M Control A */
+
+#define SYSCTRL_OSC8M_ENABLE_Pos    1            /**< \brief (SYSCTRL_OSC8M) Enable */
+#define SYSCTRL_OSC8M_ENABLE        (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos)
+#define SYSCTRL_OSC8M_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_OSC8M) Run during Standby */
+#define SYSCTRL_OSC8M_RUNSTDBY      (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos)
+#define SYSCTRL_OSC8M_ONDEMAND_Pos  7            /**< \brief (SYSCTRL_OSC8M) Enable on Demand */
+#define SYSCTRL_OSC8M_ONDEMAND      (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
+#define SYSCTRL_OSC8M_PRESC_Pos     8            /**< \brief (SYSCTRL_OSC8M) Prescaler Select */
+#define SYSCTRL_OSC8M_PRESC_Msk     (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC(value)  ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
+#define SYSCTRL_OSC8M_CALIB_Pos     16           /**< \brief (SYSCTRL_OSC8M) Calibration Value */
+#define SYSCTRL_OSC8M_CALIB_Msk     (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
+#define SYSCTRL_OSC8M_CALIB(value)  ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
+#define SYSCTRL_OSC8M_FRANGE_Pos    30           /**< \brief (SYSCTRL_OSC8M) Frequency Range */
+#define SYSCTRL_OSC8M_FRANGE_Msk    (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
+#define SYSCTRL_OSC8M_MASK          0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */
+
+/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL Config -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:1;           /*!< bit:      2  Mode Selection                     */
+    uint16_t STABLE:1;         /*!< bit:      3  Stable Frequency                   */
+    uint16_t LLAW:1;           /*!< bit:      4  Lose Lock After Wake               */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  Enable on Demand                   */
+    uint16_t CCDIS:1;          /*!< bit:      8  Chill Cycle Disable                */
+    uint16_t QLDIS:1;          /*!< bit:      9  Quick Lock Disable                 */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLCTRL_OFFSET     0x24         /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL Config */
+#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul     /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL Config */
+
+#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1            /**< \brief (SYSCTRL_DFLLCTRL) Enable */
+#define SYSCTRL_DFLLCTRL_ENABLE     (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos)
+#define SYSCTRL_DFLLCTRL_MODE_Pos   2            /**< \brief (SYSCTRL_DFLLCTRL) Mode Selection */
+#define SYSCTRL_DFLLCTRL_MODE       (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos)
+#define SYSCTRL_DFLLCTRL_STABLE_Pos 3            /**< \brief (SYSCTRL_DFLLCTRL) Stable Frequency */
+#define SYSCTRL_DFLLCTRL_STABLE     (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos)
+#define SYSCTRL_DFLLCTRL_LLAW_Pos   4            /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
+#define SYSCTRL_DFLLCTRL_LLAW       (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos)
+#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DFLLCTRL) Run during Standby */
+#define SYSCTRL_DFLLCTRL_RUNSTDBY   (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
+#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DFLLCTRL) Enable on Demand */
+#define SYSCTRL_DFLLCTRL_ONDEMAND   (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
+#define SYSCTRL_DFLLCTRL_CCDIS_Pos  8            /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
+#define SYSCTRL_DFLLCTRL_CCDIS      (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos)
+#define SYSCTRL_DFLLCTRL_QLDIS_Pos  9            /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
+#define SYSCTRL_DFLLCTRL_QLDIS      (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos)
+#define SYSCTRL_DFLLCTRL_MASK       0x03DEul     /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
+
+/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL Calibration Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FINE:10;          /*!< bit:  0.. 9  Fine Calibration Value             */
+    uint32_t COARSE:6;         /*!< bit: 10..15  Coarse Calibration Value           */
+    uint32_t DIFF:16;          /*!< bit: 16..31  Multiplication Ratio Difference    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLVAL_OFFSET      0x28         /**< \brief (SYSCTRL_DFLLVAL offset) DFLL Calibration Value */
+#define SYSCTRL_DFLLVAL_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL Calibration Value */
+
+#define SYSCTRL_DFLLVAL_FINE_Pos    0            /**< \brief (SYSCTRL_DFLLVAL) Fine Calibration Value */
+#define SYSCTRL_DFLLVAL_FINE_Msk    (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
+#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
+#define SYSCTRL_DFLLVAL_COARSE_Pos  10           /**< \brief (SYSCTRL_DFLLVAL) Coarse Calibration Value */
+#define SYSCTRL_DFLLVAL_COARSE_Msk  (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
+#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
+#define SYSCTRL_DFLLVAL_DIFF_Pos    16           /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define SYSCTRL_DFLLVAL_DIFF_Msk    (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
+#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
+#define SYSCTRL_DFLLVAL_MASK        0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
+
+/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUL:16;           /*!< bit:  0..15  Multiplication Value               */
+    uint32_t FSTEP:10;         /*!< bit: 16..25  Maximum Fine Step Size             */
+    uint32_t CSTEP:6;          /*!< bit: 26..31  Maximum Coarse Step Size           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLMUL_OFFSET      0x2C         /**< \brief (SYSCTRL_DFLLMUL offset) DFLL Multiplier */
+#define SYSCTRL_DFLLMUL_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL Multiplier */
+
+#define SYSCTRL_DFLLMUL_MUL_Pos     0            /**< \brief (SYSCTRL_DFLLMUL) Multiplication Value */
+#define SYSCTRL_DFLLMUL_MUL_Msk     (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
+#define SYSCTRL_DFLLMUL_MUL(value)  ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
+#define SYSCTRL_DFLLMUL_FSTEP_Pos   16           /**< \brief (SYSCTRL_DFLLMUL) Maximum Fine Step Size */
+#define SYSCTRL_DFLLMUL_FSTEP_Msk   (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
+#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
+#define SYSCTRL_DFLLMUL_CSTEP_Pos   26           /**< \brief (SYSCTRL_DFLLMUL) Maximum Coarse Step Size */
+#define SYSCTRL_DFLLMUL_CSTEP_Msk   (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
+#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
+#define SYSCTRL_DFLLMUL_MASK        0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
+
+/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W  8) DFLL Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  READREQ:1;        /*!< bit:      7  Read Request Synchronization       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLSYNC_OFFSET     0x30         /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL Synchronization */
+#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul       /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL Synchronization */
+
+#define SYSCTRL_DFLLSYNC_READREQ_Pos 7            /**< \brief (SYSCTRL_DFLLSYNC) Read Request Synchronization */
+#define SYSCTRL_DFLLSYNC_READREQ    (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos)
+#define SYSCTRL_DFLLSYNC_MASK       0x80ul       /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
+
+/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t HYST:1;           /*!< bit:      2  Hysteresis Enable                  */
+    uint32_t ACTION:2;         /*!< bit:  3.. 4  Action when Threshold Crossed      */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MODE:1;           /*!< bit:      8  Operation Modes                    */
+    uint32_t CEN:1;            /*!< bit:      9  Clock Enable                       */
+    uint32_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint32_t PSEL:4;           /*!< bit: 12..15  Prescaler Select                   */
+    uint32_t LEVEL:6;          /*!< bit: 16..21  Threshold Level                    */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_BOD33_OFFSET        0x34         /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
+#define SYSCTRL_BOD33_RESETVALUE    0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
+
+#define SYSCTRL_BOD33_ENABLE_Pos    1            /**< \brief (SYSCTRL_BOD33) Enable */
+#define SYSCTRL_BOD33_ENABLE        (0x1ul << SYSCTRL_BOD33_ENABLE_Pos)
+#define SYSCTRL_BOD33_HYST_Pos      2            /**< \brief (SYSCTRL_BOD33) Hysteresis Enable */
+#define SYSCTRL_BOD33_HYST          (0x1ul << SYSCTRL_BOD33_HYST_Pos)
+#define SYSCTRL_BOD33_ACTION_Pos    3            /**< \brief (SYSCTRL_BOD33) Action when Threshold Crossed */
+#define SYSCTRL_BOD33_ACTION_Msk    (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
+#define SYSCTRL_BOD33_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_BOD33) Run during Standby */
+#define SYSCTRL_BOD33_RUNSTDBY      (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos)
+#define SYSCTRL_BOD33_MODE_Pos      8            /**< \brief (SYSCTRL_BOD33) Operation Modes */
+#define SYSCTRL_BOD33_MODE          (0x1ul << SYSCTRL_BOD33_MODE_Pos)
+#define SYSCTRL_BOD33_CEN_Pos       9            /**< \brief (SYSCTRL_BOD33) Clock Enable */
+#define SYSCTRL_BOD33_CEN           (0x1ul << SYSCTRL_BOD33_CEN_Pos)
+#define SYSCTRL_BOD33_PSEL_Pos      12           /**< \brief (SYSCTRL_BOD33) Prescaler Select */
+#define SYSCTRL_BOD33_PSEL_Msk      (0xFul << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL(value)   ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
+#define SYSCTRL_BOD33_LEVEL_Pos     16           /**< \brief (SYSCTRL_BOD33) Threshold Level */
+#define SYSCTRL_BOD33_LEVEL_Msk     (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
+#define SYSCTRL_BOD33_LEVEL(value)  ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
+#define SYSCTRL_BOD33_MASK          0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
+
+/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) VREG Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint16_t :6;               /*!< bit:  7..12  Reserved                           */
+    uint16_t FORCELDO:1;       /*!< bit:     13  Force LDO Voltage Regulator        */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREG_OFFSET         0x3C         /**< \brief (SYSCTRL_VREG offset) VREG Control */
+#define SYSCTRL_VREG_RESETVALUE     0x0402ul     /**< \brief (SYSCTRL_VREG reset_value) VREG Control */
+
+#define SYSCTRL_VREG_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_VREG) Run during Standby */
+#define SYSCTRL_VREG_RUNSTDBY       (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
+#define SYSCTRL_VREG_FORCELDO_Pos   13           /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
+#define SYSCTRL_VREG_FORCELDO       (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
+#define SYSCTRL_VREG_MASK           0x2040ul     /**< \brief (SYSCTRL_VREG) MASK Register */
+
+/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) VREF Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t TSEN:1;           /*!< bit:      1  Temperature Sensor Output Enable   */
+    uint32_t BGOUTEN:1;        /*!< bit:      2  Bandgap Output Enable              */
+    uint32_t :13;              /*!< bit:  3..15  Reserved                           */
+    uint32_t CALIB:11;         /*!< bit: 16..26  Voltage Reference Calibration Value */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREF_OFFSET         0x40         /**< \brief (SYSCTRL_VREF offset) VREF Control A */
+#define SYSCTRL_VREF_RESETVALUE     0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) VREF Control A */
+
+#define SYSCTRL_VREF_TSEN_Pos       1            /**< \brief (SYSCTRL_VREF) Temperature Sensor Output Enable */
+#define SYSCTRL_VREF_TSEN           (0x1ul << SYSCTRL_VREF_TSEN_Pos)
+#define SYSCTRL_VREF_BGOUTEN_Pos    2            /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
+#define SYSCTRL_VREF_BGOUTEN        (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
+#define SYSCTRL_VREF_CALIB_Pos      16           /**< \brief (SYSCTRL_VREF) Voltage Reference Calibration Value */
+#define SYSCTRL_VREF_CALIB_Msk      (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
+#define SYSCTRL_VREF_CALIB(value)   ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
+#define SYSCTRL_VREF_MASK           0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
+
+/** \brief SYSCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO SYSCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+  __IO SYSCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+  __IO SYSCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+  __I  SYSCTRL_PCLKSR_Type       PCLKSR;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
+  __IO SYSCTRL_XOSC_Type         XOSC;        /**< \brief Offset: 0x10 (R/W 16) XOSC Control */
+       RoReg8                    Reserved1[0x2];
+  __IO SYSCTRL_XOSC32K_Type      XOSC32K;     /**< \brief Offset: 0x14 (R/W 16) XOSC32K Control */
+       RoReg8                    Reserved2[0x2];
+  __IO SYSCTRL_OSC32K_Type       OSC32K;      /**< \brief Offset: 0x18 (R/W 32) OSC32K Control */
+  __IO SYSCTRL_OSCULP32K_Type    OSCULP32K;   /**< \brief Offset: 0x1C (R/W  8) OSCULP32K Control */
+       RoReg8                    Reserved3[0x3];
+  __IO SYSCTRL_OSC8M_Type        OSC8M;       /**< \brief Offset: 0x20 (R/W 32) OSC8M Control A */
+  __IO SYSCTRL_DFLLCTRL_Type     DFLLCTRL;    /**< \brief Offset: 0x24 (R/W 16) DFLL Config */
+       RoReg8                    Reserved4[0x2];
+  __IO SYSCTRL_DFLLVAL_Type      DFLLVAL;     /**< \brief Offset: 0x28 (R/W 32) DFLL Calibration Value */
+  __IO SYSCTRL_DFLLMUL_Type      DFLLMUL;     /**< \brief Offset: 0x2C (R/W 32) DFLL Multiplier */
+  __IO SYSCTRL_DFLLSYNC_Type     DFLLSYNC;    /**< \brief Offset: 0x30 (R/W  8) DFLL Synchronization */
+       RoReg8                    Reserved5[0x3];
+  __IO SYSCTRL_BOD33_Type        BOD33;       /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+       RoReg8                    Reserved6[0x4];
+  __IO SYSCTRL_VREG_Type         VREG;        /**< \brief Offset: 0x3C (R/W 16) VREG Control */
+       RoReg8                    Reserved7[0x2];
+  __IO SYSCTRL_VREF_Type         VREF;        /**< \brief Offset: 0x40 (R/W 32) VREF Control A */
+} Sysctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_SYSCTRL_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/tc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/tc.h
new file mode 100644
index 0000000000..20ecd705af
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/tc.h
@@ -0,0 +1,687 @@
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC_COMPONENT_
+#define _SAMD20_TC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAMD20_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2212
+#define REV_TC                      0x112
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  TC Mode                            */
+    uint16_t :1;               /*!< bit:      4  Reserved                           */
+    uint16_t WAVEGEN:2;        /*!< bit:  5.. 6  Waveform Generation Operation      */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint16_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint16_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET             0x00         /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE         0x0000ul     /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos          0            /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST              (0x1ul << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos         1            /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE             (0x1ul << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos           2            /**< \brief (TC_CTRLA) TC Mode */
+#define TC_CTRLA_MODE_Msk           (0x3ul << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value)        ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))
+#define   TC_CTRLA_MODE_COUNT16_Val       0x0ul  /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define   TC_CTRLA_MODE_COUNT8_Val        0x1ul  /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define   TC_CTRLA_MODE_COUNT32_Val       0x2ul  /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16       (TC_CTRLA_MODE_COUNT16_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8        (TC_CTRLA_MODE_COUNT8_Val      << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32       (TC_CTRLA_MODE_COUNT32_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_WAVEGEN_Pos        5            /**< \brief (TC_CTRLA) Waveform Generation Operation */
+#define TC_CTRLA_WAVEGEN_Msk        (0x3ul << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN(value)     ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))
+#define   TC_CTRLA_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_MPWM_Val       0x3ul  /**< \brief (TC_CTRLA)  */
+#define TC_CTRLA_WAVEGEN_NFRQ       (TC_CTRLA_WAVEGEN_NFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MFRQ       (TC_CTRLA_WAVEGEN_MFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_NPWM       (TC_CTRLA_WAVEGEN_NPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MPWM       (TC_CTRLA_WAVEGEN_MPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_PRESCALER_Pos      8            /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk      (0x7ul << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value)   ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))
+#define   TC_CTRLA_PRESCALER_DIV1_Val     0x0ul  /**< \brief (TC_CTRLA) GCLK_TC */
+#define   TC_CTRLA_PRESCALER_DIV2_Val     0x1ul  /**< \brief (TC_CTRLA) GCLK_TC/2 */
+#define   TC_CTRLA_PRESCALER_DIV4_Val     0x2ul  /**< \brief (TC_CTRLA) GCLK_TC/4 */
+#define   TC_CTRLA_PRESCALER_DIV8_Val     0x3ul  /**< \brief (TC_CTRLA) GCLK_TC/8 */
+#define   TC_CTRLA_PRESCALER_DIV16_Val    0x4ul  /**< \brief (TC_CTRLA) GCLK_TC/16 */
+#define   TC_CTRLA_PRESCALER_DIV64_Val    0x5ul  /**< \brief (TC_CTRLA) GCLK_TC/64 */
+#define   TC_CTRLA_PRESCALER_DIV256_Val   0x6ul  /**< \brief (TC_CTRLA) GCLK_TC/256 */
+#define   TC_CTRLA_PRESCALER_DIV1024_Val  0x7ul  /**< \brief (TC_CTRLA) GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1     (TC_CTRLA_PRESCALER_DIV1_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2     (TC_CTRLA_PRESCALER_DIV2_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4     (TC_CTRLA_PRESCALER_DIV4_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8     (TC_CTRLA_PRESCALER_DIV8_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16    (TC_CTRLA_PRESCALER_DIV16_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64    (TC_CTRLA_PRESCALER_DIV64_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256   (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024  (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos       11           /**< \brief (TC_CTRLA) Run in Standby */
+#define TC_CTRLA_RUNSTDBY           (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos      12           /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk      (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value)   ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))
+#define   TC_CTRLA_PRESCSYNC_GCLK_Val     0x0ul  /**< \brief (TC_CTRLA) Reload or reset Counter on next GCLK */
+#define   TC_CTRLA_PRESCSYNC_PRESC_Val    0x1ul  /**< \brief (TC_CTRLA) Reload or reset Counter on next prescaler clock */
+#define   TC_CTRLA_PRESCSYNC_RESYNC_Val   0x2ul  /**< \brief (TC_CTRLA) Reload or reset Counter on next GCLK. Reset prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK     (TC_CTRLA_PRESCSYNC_GCLK_Val   << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC    (TC_CTRLA_PRESCSYNC_PRESC_Val  << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC   (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_MASK               0x3F6Ful     /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ADDR:5;           /*!< bit:  0.. 4  Address                            */
+    uint16_t :9;               /*!< bit:  5..13  Reserved                           */
+    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
+    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_READREQ_OFFSET           0x02         /**< \brief (TC_READREQ offset) Read Request */
+#define TC_READREQ_RESETVALUE       0x0000ul     /**< \brief (TC_READREQ reset_value) Read Request */
+
+#define TC_READREQ_ADDR_Pos         0            /**< \brief (TC_READREQ) Address */
+#define TC_READREQ_ADDR_Msk         (0x1Ful << TC_READREQ_ADDR_Pos)
+#define TC_READREQ_ADDR(value)      ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))
+#define TC_READREQ_RCONT_Pos        14           /**< \brief (TC_READREQ) Read Continuously */
+#define TC_READREQ_RCONT            (0x1ul << TC_READREQ_RCONT_Pos)
+#define TC_READREQ_RREQ_Pos         15           /**< \brief (TC_READREQ) Read Request */
+#define TC_READREQ_RREQ             (0x1ul << TC_READREQ_RREQ_Pos)
+#define TC_READREQ_MASK             0xC01Ful     /**< \brief (TC_READREQ) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET          0x04         /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE      0x02ul       /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos         0            /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR             (0x1ul << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos     2            /**< \brief (TC_CTRLBCLR) One-Shot */
+#define TC_CTRLBCLR_ONESHOT         (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos         6            /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk         (0x3ul << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value)      ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))
+#define   TC_CTRLBCLR_CMD_NONE_Val        0x0ul  /**< \brief (TC_CTRLBCLR) No action */
+#define   TC_CTRLBCLR_CMD_RETRIGGER_Val   0x1ul  /**< \brief (TC_CTRLBCLR) Force start, restart or retrigger */
+#define   TC_CTRLBCLR_CMD_STOP_Val        0x2ul  /**< \brief (TC_CTRLBCLR) Force stop */
+#define TC_CTRLBCLR_CMD_NONE        (TC_CTRLBCLR_CMD_NONE_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER   (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP        (TC_CTRLBCLR_CMD_STOP_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK            0xC5ul       /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-shot                           */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET          0x05         /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE      0x00ul       /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos         0            /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR             (0x1ul << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos     2            /**< \brief (TC_CTRLBSET) One-shot */
+#define TC_CTRLBSET_ONESHOT         (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos         6            /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk         (0x3ul << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value)      ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))
+#define   TC_CTRLBSET_CMD_NONE_Val        0x0ul  /**< \brief (TC_CTRLBSET) No action */
+#define   TC_CTRLBSET_CMD_RETRIGGER_Val   0x1ul  /**< \brief (TC_CTRLBSET) Force start, restart or retrigger */
+#define   TC_CTRLBSET_CMD_STOP_Val        0x2ul  /**< \brief (TC_CTRLBSET) Force stop */
+#define TC_CTRLBSET_CMD_NONE        (TC_CTRLBSET_CMD_NONE_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER   (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP        (TC_CTRLBSET_CMD_STOP_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK            0xC5ul       /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W  8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  INVEN0:1;         /*!< bit:      0  Output Waveform 0 Invert Enable    */
+    uint8_t  INVEN1:1;         /*!< bit:      1  Output Waveform 1 Invert Enable    */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CPTEN0:1;         /*!< bit:      4  Capture Channel 0 Enable           */
+    uint8_t  CPTEN1:1;         /*!< bit:      5  Capture Channel 1 Enable           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  INVEN:2;          /*!< bit:  0.. 1  Output Waveform x Invert Enable    */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CPTEN:2;          /*!< bit:  4.. 5  Capture Channel x Enable           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLC_OFFSET             0x06         /**< \brief (TC_CTRLC offset) Control C */
+#define TC_CTRLC_RESETVALUE         0x00ul       /**< \brief (TC_CTRLC reset_value) Control C */
+
+#define TC_CTRLC_INVEN0_Pos         0            /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
+#define TC_CTRLC_INVEN0             (1 << TC_CTRLC_INVEN0_Pos)
+#define TC_CTRLC_INVEN1_Pos         1            /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
+#define TC_CTRLC_INVEN1             (1 << TC_CTRLC_INVEN1_Pos)
+#define TC_CTRLC_INVEN_Pos          0            /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
+#define TC_CTRLC_INVEN_Msk          (0x3ul << TC_CTRLC_INVEN_Pos)
+#define TC_CTRLC_INVEN(value)       ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))
+#define TC_CTRLC_CPTEN0_Pos         4            /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
+#define TC_CTRLC_CPTEN0             (1 << TC_CTRLC_CPTEN0_Pos)
+#define TC_CTRLC_CPTEN1_Pos         5            /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
+#define TC_CTRLC_CPTEN1             (1 << TC_CTRLC_CPTEN1_Pos)
+#define TC_CTRLC_CPTEN_Pos          4            /**< \brief (TC_CTRLC) Capture Channel x Enable */
+#define TC_CTRLC_CPTEN_Msk          (0x3ul << TC_CTRLC_CPTEN_Pos)
+#define TC_CTRLC_CPTEN(value)       ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))
+#define TC_CTRLC_MASK               0x33ul       /**< \brief (TC_CTRLC) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run Mode                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET           0x08         /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE       0x00ul       /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (TC_DBGCTRL) Debug Run Mode */
+#define TC_DBGCTRL_DBGRUN           (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK             0x01ul       /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EVACT:3;          /*!< bit:  0.. 2  Event Action                       */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t TCINV:1;          /*!< bit:      4  TC Inverted Event Input            */
+    uint16_t TCEI:1;           /*!< bit:      5  TC Event Input                     */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Event Output Enable */
+    uint16_t :3;               /*!< bit:  9..11  Reserved                           */
+    uint16_t MCEO0:1;          /*!< bit:     12  Match or Capture Channel 0 Event Output Enable */
+    uint16_t MCEO1:1;          /*!< bit:     13  Match or Capture Channel 1 Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint16_t MCEO:2;           /*!< bit: 12..13  Match or Capture Channel x Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET            0x0A         /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos         0            /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk         (0x7ul << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value)      ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))
+#define   TC_EVCTRL_EVACT_OFF_Val         0x0ul  /**< \brief (TC_EVCTRL) Event action disabled */
+#define   TC_EVCTRL_EVACT_RETRIGGER_Val   0x1ul  /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define   TC_EVCTRL_EVACT_COUNT_Val       0x2ul  /**< \brief (TC_EVCTRL) Count on event */
+#define   TC_EVCTRL_EVACT_START_Val       0x3ul  /**< \brief (TC_EVCTRL) Start TC on event */
+#define   TC_EVCTRL_EVACT_PPW_Val         0x5ul  /**< \brief (TC_EVCTRL) Period captured into CC0 Pulse Width in CC1 */
+#define   TC_EVCTRL_EVACT_PWP_Val         0x6ul  /**< \brief (TC_EVCTRL) Period captured into CC1 Pulse Width on CC0 */
+#define TC_EVCTRL_EVACT_OFF         (TC_EVCTRL_EVACT_OFF_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER   (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT       (TC_EVCTRL_EVACT_COUNT_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START       (TC_EVCTRL_EVACT_START_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW         (TC_EVCTRL_EVACT_PPW_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP         (TC_EVCTRL_EVACT_PWP_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos         4            /**< \brief (TC_EVCTRL) TC Inverted Event Input */
+#define TC_EVCTRL_TCINV             (0x1ul << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos          5            /**< \brief (TC_EVCTRL) TC Event Input */
+#define TC_EVCTRL_TCEI              (0x1ul << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos         8            /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
+#define TC_EVCTRL_OVFEO             (0x1ul << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos         12           /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TC_EVCTRL_MCEO0             (1 << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos         13           /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TC_EVCTRL_MCEO1             (1 << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos          12           /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TC_EVCTRL_MCEO_Msk          (0x3ul << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value)       ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))
+#define TC_EVCTRL_MASK              0x3137ul     /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET          0x0C         /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos         0            /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
+#define TC_INTENCLR_OVF             (0x1ul << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos         1            /**< \brief (TC_INTENCLR) Error Interrupt Enable */
+#define TC_INTENCLR_ERR             (0x1ul << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_SYNCRDY_Pos     3            /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define TC_INTENCLR_SYNCRDY         (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
+#define TC_INTENCLR_MC0_Pos         4            /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENCLR_MC0             (1 << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos         5            /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENCLR_MC1             (1 << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos          4            /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENCLR_MC_Msk          (0x3ul << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value)       ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))
+#define TC_INTENCLR_MASK            0x3Bul       /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET          0x0D         /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE      0x00ul       /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos         0            /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
+#define TC_INTENSET_OVF             (0x1ul << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos         1            /**< \brief (TC_INTENSET) Error Interrupt Enable */
+#define TC_INTENSET_ERR             (0x1ul << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_SYNCRDY_Pos     3            /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
+#define TC_INTENSET_SYNCRDY         (0x1ul << TC_INTENSET_SYNCRDY_Pos)
+#define TC_INTENSET_MC0_Pos         4            /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENSET_MC0             (1 << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos         5            /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENSET_MC1             (1 << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos          4            /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENSET_MC_Msk          (0x3ul << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value)       ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))
+#define TC_INTENSET_MASK            0x3Bul       /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow                           */
+    uint8_t  ERR:1;            /*!< bit:      1  Error                              */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0         */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1         */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x         */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET           0x0E         /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos          0            /**< \brief (TC_INTFLAG) Overflow */
+#define TC_INTFLAG_OVF              (0x1ul << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos          1            /**< \brief (TC_INTFLAG) Error */
+#define TC_INTFLAG_ERR              (0x1ul << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_SYNCRDY_Pos      3            /**< \brief (TC_INTFLAG) Synchronization Ready */
+#define TC_INTFLAG_SYNCRDY          (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
+#define TC_INTFLAG_MC0_Pos          4            /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
+#define TC_INTFLAG_MC0              (1 << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos          5            /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
+#define TC_INTFLAG_MC1              (1 << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos           4            /**< \brief (TC_INTFLAG) Match or Capture Channel x */
+#define TC_INTFLAG_MC_Msk           (0x3ul << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value)        ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))
+#define TC_INTFLAG_MASK             0x3Bul       /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0F) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :3;               /*!< bit:  0.. 2  Reserved                           */
+    uint8_t  STOP:1;           /*!< bit:      3  Stop                               */
+    uint8_t  SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET            0x0F         /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE        0x08ul       /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos          3            /**< \brief (TC_STATUS) Stop */
+#define TC_STATUS_STOP              (0x1ul << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos         4            /**< \brief (TC_STATUS) Slave */
+#define TC_STATUS_SLAVE             (0x1ul << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_SYNCBUSY_Pos      7            /**< \brief (TC_STATUS) Synchronization Busy */
+#define TC_STATUS_SYNCBUSY          (0x1ul << TC_STATUS_SYNCBUSY_Pos)
+#define TC_STATUS_MASK              0x98ul       /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
+#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul     /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
+
+#define TC_COUNT16_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT16_COUNT) Counter Value */
+#define TC_COUNT16_COUNT_COUNT_Msk  (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))
+#define TC_COUNT16_COUNT_MASK       0xFFFFul     /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
+#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
+
+#define TC_COUNT32_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT32_COUNT) Counter Value */
+#define TC_COUNT32_COUNT_COUNT_Msk  (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))
+#define TC_COUNT32_COUNT_MASK       0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W  8) COUNT8 COUNT8 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COUNT:8;          /*!< bit:  0.. 7  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET      0x10         /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
+#define TC_COUNT8_COUNT_RESETVALUE  0x00ul       /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
+
+#define TC_COUNT8_COUNT_COUNT_Pos   0            /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk   (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))
+#define TC_COUNT8_COUNT_MASK        0xFFul       /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W  8) COUNT8 COUNT8 Period Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:8;            /*!< bit:  0.. 7  Period Value                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET        0x14         /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
+#define TC_COUNT8_PER_RESETVALUE    0xFFul       /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
+
+#define TC_COUNT8_PER_PER_Pos       0            /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk       (0xFFul << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value)    ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))
+#define TC_COUNT8_PER_MASK          0xFFul       /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CC:16;            /*!< bit:  0..15  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET        0x18         /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
+#define TC_COUNT16_CC_RESETVALUE    0x0000ul     /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
+
+#define TC_COUNT16_CC_CC_Pos        0            /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
+#define TC_COUNT16_CC_CC_Msk        (0xFFFFul << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value)     ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))
+#define TC_COUNT16_CC_MASK          0xFFFFul     /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CC:32;            /*!< bit:  0..31  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET        0x18         /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
+#define TC_COUNT32_CC_RESETVALUE    0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
+
+#define TC_COUNT32_CC_CC_Pos        0            /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
+#define TC_COUNT32_CC_CC_Msk        (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value)     ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))
+#define TC_COUNT32_CC_MASK          0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W  8) COUNT8 COUNT8 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CC:8;             /*!< bit:  0.. 7  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET         0x18         /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
+#define TC_COUNT8_CC_RESETVALUE     0x00ul       /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
+
+#define TC_COUNT8_CC_CC_Pos         0            /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
+#define TC_COUNT8_CC_CC_Msk         (0xFFul << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value)      ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))
+#define TC_COUNT8_CC_MASK           0xFFul       /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT8_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W  8) COUNT8 Counter Value */
+       RoReg8                    Reserved3[0x3];
+  __IO TC_COUNT8_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W  8) COUNT8 Period Value */
+       RoReg8                    Reserved4[0x3];
+  __IO TC_COUNT8_CC_Type         CC[2];       /**< \brief Offset: 0x18 (R/W  8) COUNT8 Compare/Capture */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT16_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+       RoReg8                    Reserved3[0x6];
+  __IO TC_COUNT16_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT32_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO TC_COUNT32_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       TcCount8                  COUNT8;      /**< \brief Offset: 0x00 8-bit Counter Mode */
+       TcCount16                 COUNT16;     /**< \brief Offset: 0x00 16-bit Counter Mode */
+       TcCount32                 COUNT32;     /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_TC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/wdt.h
new file mode 100644
index 0000000000..664cc354a0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/wdt.h
@@ -0,0 +1,306 @@
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_WDT_COMPONENT_
+#define _SAMD20_WDT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAMD20_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2203
+#define REV_WDT                     0x200
+
+/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  WEN:1;            /*!< bit:      2  Watchdog Timer Window Mode Enable  */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ALWAYSON:1;       /*!< bit:      7  Always-On                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRL_OFFSET             0x0          /**< \brief (WDT_CTRL offset) Control */
+#define WDT_CTRL_RESETVALUE         0x00ul       /**< \brief (WDT_CTRL reset_value) Control */
+
+#define WDT_CTRL_ENABLE_Pos         1            /**< \brief (WDT_CTRL) Enable */
+#define WDT_CTRL_ENABLE             (0x1ul << WDT_CTRL_ENABLE_Pos)
+#define WDT_CTRL_WEN_Pos            2            /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
+#define WDT_CTRL_WEN                (0x1ul << WDT_CTRL_WEN_Pos)
+#define WDT_CTRL_ALWAYSON_Pos       7            /**< \brief (WDT_CTRL) Always-On */
+#define WDT_CTRL_ALWAYSON           (0x1ul << WDT_CTRL_ALWAYSON_Pos)
+#define WDT_CTRL_MASK               0x86ul       /**< \brief (WDT_CTRL) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W  8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:4;            /*!< bit:  0.. 3  Time-Out Period                    */
+    uint8_t  WINDOW:4;         /*!< bit:  4.. 7  Window Mode Time-Out Period        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET           0x1          /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE       0xBBul       /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos          0            /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk          (0xFul << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value)       ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))
+#define   WDT_CONFIG_PER_8_Val            0x0ul  /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_PER_16_Val           0x1ul  /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_PER_32_Val           0x2ul  /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_PER_64_Val           0x3ul  /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_PER_128_Val          0x4ul  /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_PER_256_Val          0x5ul  /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_PER_512_Val          0x6ul  /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_PER_1K_Val           0x7ul  /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_PER_2K_Val           0x8ul  /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_PER_4K_Val           0x9ul  /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_PER_8K_Val           0xAul  /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_PER_16K_Val          0xBul  /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_8            (WDT_CONFIG_PER_8_Val          << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16           (WDT_CONFIG_PER_16_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_32           (WDT_CONFIG_PER_32_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_64           (WDT_CONFIG_PER_64_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_128          (WDT_CONFIG_PER_128_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_256          (WDT_CONFIG_PER_256_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_512          (WDT_CONFIG_PER_512_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_1K           (WDT_CONFIG_PER_1K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_2K           (WDT_CONFIG_PER_2K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_4K           (WDT_CONFIG_PER_4K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_8K           (WDT_CONFIG_PER_8K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16K          (WDT_CONFIG_PER_16K_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos       4            /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk       (0xFul << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value)    ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))
+#define   WDT_CONFIG_WINDOW_8_Val         0x0ul  /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_WINDOW_16_Val        0x1ul  /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_WINDOW_32_Val        0x2ul  /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_WINDOW_64_Val        0x3ul  /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_WINDOW_128_Val       0x4ul  /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_WINDOW_256_Val       0x5ul  /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_WINDOW_512_Val       0x6ul  /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_WINDOW_1K_Val        0x7ul  /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_WINDOW_2K_Val        0x8ul  /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_WINDOW_4K_Val        0x9ul  /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_WINDOW_8K_Val        0xAul  /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_WINDOW_16K_Val       0xBul  /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_8         (WDT_CONFIG_WINDOW_8_Val       << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16        (WDT_CONFIG_WINDOW_16_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_32        (WDT_CONFIG_WINDOW_32_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_64        (WDT_CONFIG_WINDOW_64_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_128       (WDT_CONFIG_WINDOW_128_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_256       (WDT_CONFIG_WINDOW_256_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_512       (WDT_CONFIG_WINDOW_512_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_1K        (WDT_CONFIG_WINDOW_1K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_2K        (WDT_CONFIG_WINDOW_2K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_4K        (WDT_CONFIG_WINDOW_4K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_8K        (WDT_CONFIG_WINDOW_8K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16K       (WDT_CONFIG_WINDOW_16K_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK             0xFFul       /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W  8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EWOFFSET:4;       /*!< bit:  0.. 3  Early Warning Interrupt Time Offset */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET           0x2          /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE       0x0Bul       /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos     0            /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk     (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value)  ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))
+#define   WDT_EWCTRL_EWOFFSET_8_Val       0x0ul  /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_16_Val      0x1ul  /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_32_Val      0x2ul  /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_64_Val      0x3ul  /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_128_Val     0x4ul  /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_256_Val     0x5ul  /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_512_Val     0x6ul  /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_1K_Val      0x7ul  /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_2K_Val      0x8ul  /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_4K_Val      0x9ul  /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_8K_Val      0xAul  /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_16K_Val     0xBul  /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8       (WDT_EWCTRL_EWOFFSET_8_Val     << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16      (WDT_EWCTRL_EWOFFSET_16_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_32      (WDT_EWCTRL_EWOFFSET_32_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_64      (WDT_EWCTRL_EWOFFSET_64_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_128     (WDT_EWCTRL_EWOFFSET_128_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_256     (WDT_EWCTRL_EWOFFSET_256_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_512     (WDT_EWCTRL_EWOFFSET_512_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_1K      (WDT_EWCTRL_EWOFFSET_1K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_2K      (WDT_EWCTRL_EWOFFSET_2K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_4K      (WDT_EWCTRL_EWOFFSET_4K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_8K      (WDT_EWCTRL_EWOFFSET_8K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16K     (WDT_EWCTRL_EWOFFSET_16K_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK             0x0Ful       /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET         0x4          /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE     0x00ul       /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos         0            /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW             (0x1ul << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK           0x01ul       /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET         0x5          /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE     0x00ul       /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos         0            /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW             (0x1ul << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK           0x01ul       /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning                      */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET          0x6          /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE      0x00ul       /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos          0            /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW              (0x1ul << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK            0x01ul       /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_STATUS_OFFSET           0x7          /**< \brief (WDT_STATUS offset) Status */
+#define WDT_STATUS_RESETVALUE       0x00ul       /**< \brief (WDT_STATUS reset_value) Status */
+
+#define WDT_STATUS_SYNCBUSY_Pos     7            /**< \brief (WDT_STATUS) Synchronization Busy */
+#define WDT_STATUS_SYNCBUSY         (0x1ul << WDT_STATUS_SYNCBUSY_Pos)
+#define WDT_STATUS_MASK             0x80ul       /**< \brief (WDT_STATUS) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W  8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CLEAR:8;          /*!< bit:  0.. 7  Watchdog Clear                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET            0x8          /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE        0x00ul       /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos         0            /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk         (0xFFul << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value)      ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))
+#define   WDT_CLEAR_CLEAR_KEY_Val         0xA5ul  /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY         (WDT_CLEAR_CLEAR_KEY_Val       << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK              0xFFul       /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO WDT_CTRL_Type             CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+  __IO WDT_CONFIG_Type           CONFIG;      /**< \brief Offset: 0x1 (R/W  8) Configuration */
+  __IO WDT_EWCTRL_Type           EWCTRL;      /**< \brief Offset: 0x2 (R/W  8) Early Warning Interrupt Control */
+       RoReg8                    Reserved1[0x1];
+  __IO WDT_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO WDT_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO WDT_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+  __I  WDT_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
+  __O  WDT_CLEAR_Type            CLEAR;       /**< \brief Offset: 0x8 ( /W  8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD20_WDT_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/ac.h
new file mode 100644
index 0000000000..1f3db56dc4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/ac.h
@@ -0,0 +1,90 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_AC_INSTANCE_
+#define _SAMD20_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA               (0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC             (0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL             (0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0           (0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0             (0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (0x42004421U) /**< \brief (AC) Scaler 1 */
+#else
+#define REG_AC_CTRLA               (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC             (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL             (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0           (*(RwReg  *)0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (*(RwReg  *)0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0             (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_CMP_NUM                  2        // Number of comparators
+#define AC_GCLK_ID_ANA              25       // Index of Generic Clock for analog
+#define AC_GCLK_ID_DIG              24       // Index of Generic Clock for digital
+#define AC_NUM_CMP                  2       
+#define AC_PAIRS                    1        // Number of pairs of comparators
+
+#endif /* _SAMD20_AC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/adc.h
new file mode 100644
index 0000000000..1966ef8684
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/adc.h
@@ -0,0 +1,101 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_ADC_INSTANCE_
+#define _SAMD20_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CTRLA              (0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL            (0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL            (0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL           (0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB              (0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL            (0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG             (0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL          (0x42004010U) /**< \brief (ADC) Inputs Control */
+#define REG_ADC_EVCTRL             (0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR           (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET           (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG            (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS             (0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT             (0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT              (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT              (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR           (0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR         (0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB              (0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL            (0x4200402AU) /**< \brief (ADC) Debug Control */
+#else
+#define REG_ADC_CTRLA              (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL            (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL            (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL           (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB              (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL            (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG             (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL          (*(RwReg  *)0x42004010U) /**< \brief (ADC) Inputs Control */
+#define REG_ADC_EVCTRL             (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR           (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET           (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG            (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS             (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT             (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT              (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT              (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR           (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR         (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB              (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL            (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC peripheral ========== */
+#define ADC_EXTCHANNEL_MSB          19       // Number of external channels
+#define ADC_GCLK_ID                 23       // Index of Generic Clock
+#define ADC_RESULT_BITS             16       // Size of RESULT.RESULT bitfield
+#define ADC_RESULT_MSB              15       // Size of Result
+
+#endif /* _SAMD20_ADC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/dac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/dac.h
new file mode 100644
index 0000000000..f3876751d0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/dac.h
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DAC
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_DAC_INSTANCE_
+#define _SAMD20_DAC_INSTANCE_
+
+/* ========== Register definition for DAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DAC_CTRLA              (0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA               (0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF            (0x4200480CU) /**< \brief (DAC) Data Buffer */
+#else
+#define REG_DAC_CTRLA              (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA               (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF            (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DAC peripheral ========== */
+#define DAC_GCLK_ID                 26
+
+#endif /* _SAMD20_DAC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/dsu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/dsu.h
new file mode 100644
index 0000000000..6ba5d96f56
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/dsu.h
@@ -0,0 +1,112 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_DSU_INSTANCE_
+#define _SAMD20_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL               (0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_DCFG0              (0x410020F0U) /**< \brief (DSU) Device Configuration 0 */
+#define REG_DSU_DCFG1              (0x410020F4U) /**< \brief (DSU) Device Configuration 1 */
+#define REG_DSU_ENTRY0             (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END                (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE            (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4               (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID5               (0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */
+#define REG_DSU_PID6               (0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */
+#define REG_DSU_PID7               (0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */
+#define REG_DSU_PID0               (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL               (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (*(RwReg  *)0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (*(RwReg  *)0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (*(RwReg  *)0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (*(RwReg  *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (*(RwReg  *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (*(RoReg  *)0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_DCFG0              (*(RwReg  *)0x410020F0U) /**< \brief (DSU) Device Configuration 0 */
+#define REG_DSU_DCFG1              (*(RwReg  *)0x410020F4U) /**< \brief (DSU) Device Configuration 1 */
+#define REG_DSU_ENTRY0             (*(RoReg  *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (*(RoReg  *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END                (*(RoReg  *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE            (*(RoReg  *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4               (*(RoReg  *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID5               (*(RoReg  *)0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */
+#define REG_DSU_PID6               (*(RoReg  *)0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */
+#define REG_DSU_PID7               (*(RoReg  *)0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */
+#define REG_DSU_PID0               (*(RoReg  *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (*(RoReg  *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (*(RoReg  *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (*(RoReg  *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (*(RoReg  *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (*(RoReg  *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (*(RoReg  *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (*(RoReg  *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_HSB_ID              3
+
+#endif /* _SAMD20_DSU_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/eic.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/eic.h
new file mode 100644
index 0000000000..6da39681b1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/eic.h
@@ -0,0 +1,84 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_EIC_INSTANCE_
+#define _SAMD20_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRL               (0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS             (0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL            (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL             (0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP             (0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0            (0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1            (0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#else
+#define REG_EIC_CTRL               (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS             (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL            (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL             (*(RwReg  *)0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (*(RwReg  *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (*(RwReg  *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (*(RwReg  *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP             (*(RwReg  *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0            (*(RwReg  *)0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1            (*(RwReg  *)0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_CONFIG_NUM              2        // Number of CONFIG registers
+#define EIC_EXTINT_NUM              16       // Number of External Interrupts
+#define EIC_GCLK_ID                 3        // Index of Generic Clock
+#define EIC_NUMBER_OF_CONFIG_REGS   2        // Number of CONFIG registers (obsolete)
+#define EIC_NUMBER_OF_INTERRUPTS    16       // Number of External Interrupts (obsolete)
+
+#endif /* _SAMD20_EIC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/evsys.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/evsys.h
new file mode 100644
index 0000000000..e91ca9d734
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/evsys.h
@@ -0,0 +1,168 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_EVSYS_INSTANCE_
+#define _SAMD20_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRL             (0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#else
+#define REG_EVSYS_CTRL             (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (*(RwReg  *)0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (*(RoReg  *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (*(RwReg  *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (*(RwReg  *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (*(RwReg  *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_CHANNELS              8        // Number of Channels
+#define EVSYS_CHANNELS_BITS         3        // Number of bits to select Channel
+#define EVSYS_CHANNELS_MSB          7        // Number of Channels - 1
+#define EVSYS_EXTEVT_NUM                     // Number of External Event Generators
+#define EVSYS_EXT_EVT_MSB           0        // Number of External Event Generators - 1
+#define EVSYS_GCLK_ID_0             4
+#define EVSYS_GCLK_ID_1             5
+#define EVSYS_GCLK_ID_2             6
+#define EVSYS_GCLK_ID_3             7
+#define EVSYS_GCLK_ID_4             8
+#define EVSYS_GCLK_ID_5             9
+#define EVSYS_GCLK_ID_6             10
+#define EVSYS_GCLK_ID_7             11
+#define EVSYS_GCLK_ID_LSB           4
+#define EVSYS_GCLK_ID_MSB           11
+#define EVSYS_GCLK_ID_SIZE          8
+#define EVSYS_GENERATORS            59       // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS       6        // Number of bits to select Event Generator
+#define EVSYS_USERS                 14       // Total Number of Event Users
+#define EVSYS_USERS_BITS            4        // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_RTC_CMP_0      1
+#define EVSYS_ID_GEN_RTC_CMP_1      2
+#define EVSYS_ID_GEN_RTC_OVF        3
+#define EVSYS_ID_GEN_RTC_PER_0      4
+#define EVSYS_ID_GEN_RTC_PER_1      5
+#define EVSYS_ID_GEN_RTC_PER_2      6
+#define EVSYS_ID_GEN_RTC_PER_3      7
+#define EVSYS_ID_GEN_RTC_PER_4      8
+#define EVSYS_ID_GEN_RTC_PER_5      9
+#define EVSYS_ID_GEN_RTC_PER_6      10
+#define EVSYS_ID_GEN_RTC_PER_7      11
+#define EVSYS_ID_GEN_EIC_EXTINT_0   12
+#define EVSYS_ID_GEN_EIC_EXTINT_1   13
+#define EVSYS_ID_GEN_EIC_EXTINT_2   14
+#define EVSYS_ID_GEN_EIC_EXTINT_3   15
+#define EVSYS_ID_GEN_EIC_EXTINT_4   16
+#define EVSYS_ID_GEN_EIC_EXTINT_5   17
+#define EVSYS_ID_GEN_EIC_EXTINT_6   18
+#define EVSYS_ID_GEN_EIC_EXTINT_7   19
+#define EVSYS_ID_GEN_EIC_EXTINT_8   20
+#define EVSYS_ID_GEN_EIC_EXTINT_9   21
+#define EVSYS_ID_GEN_EIC_EXTINT_10  22
+#define EVSYS_ID_GEN_EIC_EXTINT_11  23
+#define EVSYS_ID_GEN_EIC_EXTINT_12  24
+#define EVSYS_ID_GEN_EIC_EXTINT_13  25
+#define EVSYS_ID_GEN_EIC_EXTINT_14  26
+#define EVSYS_ID_GEN_EIC_EXTINT_15  27
+#define EVSYS_ID_GEN_TC0_OVF        28
+#define EVSYS_ID_GEN_TC0_MCX_0      29
+#define EVSYS_ID_GEN_TC0_MCX_1      30
+#define EVSYS_ID_GEN_TC1_OVF        31
+#define EVSYS_ID_GEN_TC1_MCX_0      32
+#define EVSYS_ID_GEN_TC1_MCX_1      33
+#define EVSYS_ID_GEN_TC2_OVF        34
+#define EVSYS_ID_GEN_TC2_MCX_0      35
+#define EVSYS_ID_GEN_TC2_MCX_1      36
+#define EVSYS_ID_GEN_TC3_OVF        37
+#define EVSYS_ID_GEN_TC3_MCX_0      38
+#define EVSYS_ID_GEN_TC3_MCX_1      39
+#define EVSYS_ID_GEN_TC4_OVF        40
+#define EVSYS_ID_GEN_TC4_MCX_0      41
+#define EVSYS_ID_GEN_TC4_MCX_1      42
+#define EVSYS_ID_GEN_TC5_OVF        43
+#define EVSYS_ID_GEN_TC5_MCX_0      44
+#define EVSYS_ID_GEN_TC5_MCX_1      45
+#define EVSYS_ID_GEN_TC6_OVF        46
+#define EVSYS_ID_GEN_TC6_MCX_0      47
+#define EVSYS_ID_GEN_TC6_MCX_1      48
+#define EVSYS_ID_GEN_TC7_OVF        49
+#define EVSYS_ID_GEN_TC7_MCX_0      50
+#define EVSYS_ID_GEN_TC7_MCX_1      51
+#define EVSYS_ID_GEN_ADC_RESRDY     52
+#define EVSYS_ID_GEN_ADC_WINMON     53
+#define EVSYS_ID_GEN_AC_COMP_0      54
+#define EVSYS_ID_GEN_AC_COMP_1      55
+#define EVSYS_ID_GEN_AC_WIN_0       56
+#define EVSYS_ID_GEN_DAC_EMPTY      57
+#define EVSYS_ID_GEN_PTC_EOC        58
+#define EVSYS_ID_GEN_PTC_WCOMP      59
+
+// USERS
+#define EVSYS_ID_USER_TC0_EVU       0
+#define EVSYS_ID_USER_TC1_EVU       1
+#define EVSYS_ID_USER_TC2_EVU       2
+#define EVSYS_ID_USER_TC3_EVU       3
+#define EVSYS_ID_USER_TC4_EVU       4
+#define EVSYS_ID_USER_TC5_EVU       5
+#define EVSYS_ID_USER_TC6_EVU       6
+#define EVSYS_ID_USER_TC7_EVU       7
+#define EVSYS_ID_USER_ADC_START     8
+#define EVSYS_ID_USER_ADC_SYNC      9
+#define EVSYS_ID_USER_AC_SOC_0      10
+#define EVSYS_ID_USER_AC_SOC_1      11
+#define EVSYS_ID_USER_DAC_START     12
+#define EVSYS_ID_USER_PTC_STCONV    13
+
+#endif /* _SAMD20_EVSYS_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/gclk.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/gclk.h
new file mode 100644
index 0000000000..b6f6bde59e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/gclk.h
@@ -0,0 +1,82 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_GCLK_INSTANCE_
+#define _SAMD20_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRL              (0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS            (0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL           (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL           (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV            (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#else
+#define REG_GCLK_CTRL              (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS            (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL           (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL           (*(RwReg  *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV            (*(RwReg  *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENDIV_BITS            16      
+#define GCLK_GEN_NUM                8        // Number of Generic Clock Generators
+#define GCLK_GEN_NUM_MSB            7        // Number of Generic Clock Generators - 1
+#define GCLK_GEN_SOURCE_NUM_MSB     7        // Number of Generic Clock Sources - 1
+#define GCLK_NUM                    28       // Number of Generic Clock Users
+#define GCLK_SOURCE_DFLL48M         7       
+#define GCLK_SOURCE_FDPLL                   
+#define GCLK_SOURCE_GCLKGEN1        2       
+#define GCLK_SOURCE_GCLKIN          1       
+#define GCLK_SOURCE_NUM             8        // Number of Generic Clock Sources
+#define GCLK_SOURCE_OSCULP32K       3       
+#define GCLK_SOURCE_OSC8M           6       
+#define GCLK_SOURCE_OSC32K          4       
+#define GCLK_SOURCE_XOSC            0       
+#define GCLK_SOURCE_XOSC32K         5       
+
+#endif /* _SAMD20_GCLK_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/nvmctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/nvmctrl.h
new file mode 100644
index 0000000000..e00b812b9d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/nvmctrl.h
@@ -0,0 +1,95 @@
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_NVMCTRL_INSTANCE_
+#define _SAMD20_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA          (0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#else
+#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (*(RwReg  *)0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (*(RwReg  *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_AUX0_ADDRESS        0x00804000
+#define NVMCTRL_AUX1_ADDRESS        0x00806000
+#define NVMCTRL_AUX2_ADDRESS        0x00808000
+#define NVMCTRL_AUX3_ADDRESS        0x0080A000
+#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
+#define NVMCTRL_FLASH_SIZE          262144  
+#define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
+#define NVMCTRL_PAGES               4096    
+#define NVMCTRL_PAGE_HW             32      
+#define NVMCTRL_PAGE_SIZE           64      
+#define NVMCTRL_PAGE_W              16      
+#define NVMCTRL_PMSB                3       
+#define NVMCTRL_PSZ_BITS            6       
+#define NVMCTRL_ROW_PAGES           4       
+#define NVMCTRL_ROW_SIZE            256     
+#define NVMCTRL_TEMP_LOG_ADDRESS    0x00806030
+#define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
+#define NVMCTRL_USER_PAGE_OFFSET    0x00800000
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
+
+#endif /* _SAMD20_NVMCTRL_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac0.h
new file mode 100644
index 0000000000..9ce0996098
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac0.h
@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC0
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_PAC0_INSTANCE_
+#define _SAMD20_PAC0_INSTANCE_
+
+/* ========== Register definition for PAC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC0_WPCLR             (0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET             (0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#else
+#define REG_PAC0_WPCLR             (*(RwReg  *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET             (*(RwReg  *)0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC0 peripheral ========== */
+#define PAC0_WPROT_DEFAULT_VAL      0x00000000 // PAC protection mask at reset
+
+#endif /* _SAMD20_PAC0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac1.h
new file mode 100644
index 0000000000..613cd3a4f6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac1.h
@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC1
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_PAC1_INSTANCE_
+#define _SAMD20_PAC1_INSTANCE_
+
+/* ========== Register definition for PAC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC1_WPCLR             (0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET             (0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#else
+#define REG_PAC1_WPCLR             (*(RwReg  *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET             (*(RwReg  *)0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC1 peripheral ========== */
+#define PAC1_WPROT_DEFAULT_VAL      0x00000002 // PAC protection mask at reset
+
+#endif /* _SAMD20_PAC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac2.h
new file mode 100644
index 0000000000..8fddf58573
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac2.h
@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC2
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_PAC2_INSTANCE_
+#define _SAMD20_PAC2_INSTANCE_
+
+/* ========== Register definition for PAC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC2_WPCLR             (0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET             (0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#else
+#define REG_PAC2_WPCLR             (*(RwReg  *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET             (*(RwReg  *)0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC2 peripheral ========== */
+#define PAC2_WPROT_DEFAULT_VAL      0x00100000 // PAC protection mask at reset
+
+#endif /* _SAMD20_PAC2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pm.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pm.h
new file mode 100644
index 0000000000..ad094fbf08
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pm.h
@@ -0,0 +1,91 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_PM_INSTANCE_
+#define _SAMD20_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRL                (0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP               (0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_CPUSEL              (0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL             (0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL             (0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL             (0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK             (0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK            (0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK            (0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK            (0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR            (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE              (0x40000438U) /**< \brief (PM) Reset Cause */
+#else
+#define REG_PM_CTRL                (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP               (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_CPUSEL              (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL             (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL             (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL             (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK             (*(RwReg  *)0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK            (*(RwReg  *)0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK            (*(RwReg  *)0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK            (*(RwReg  *)0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR            (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE              (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_CTRL_MCSEL_DFLL48M       3       
+#define PM_CTRL_MCSEL_GCLK          0       
+#define PM_CTRL_MCSEL_OSC8M         1       
+#define PM_CTRL_MCSEL_XOSC          2       
+#define PM_PM_CLK_APB_NUM           2       
+#define PM_SYSTEM_CLOCK             1000000  // System Clock Frequency at Reset
+
+#endif /* _SAMD20_PM_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/port.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/port.h
new file mode 100644
index 0000000000..5872ed858f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/port.h
@@ -0,0 +1,139 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_PORT_INSTANCE_
+#define _SAMD20_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0              (0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#else
+#define REG_PORT_DIR0              (*(RwReg  *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (*(RwReg  *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (*(RwReg  *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (*(RwReg  *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (*(RoReg  *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (*(RwReg  *)0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (*(RwReg  *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (*(RwReg  *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (*(RwReg  *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (*(RwReg  *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (*(RwReg  *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (*(RwReg  *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (*(RoReg  *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (*(RwReg  *)0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (*(RwReg  *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (*(RwReg  *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS                   64       // Number of PORT pins
+#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
+#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
+#define PORT_DRVSTR                 1        // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL     { 0xDBFFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
+#define PORT_DRVSTR_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
+#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
+#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
+#define PORT_ODRAIN                 0        // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
+#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
+#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
+#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
+#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
+#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
+#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
+#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
+#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
+#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
+#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
+#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
+#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
+#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
+#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
+#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
+#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
+#define PORT_SLEWLIM                0        // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
+#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+
+#endif /* _SAMD20_PORT_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/rtc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/rtc.h
new file mode 100644
index 0000000000..dec6f6ec24
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/rtc.h
@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_RTC_INSTANCE_
+#define _SAMD20_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_READREQ            (0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS             (0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL            (0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL         (0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT        (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL         (0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT        (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL         (0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK        (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#else
+#define REG_RTC_READREQ            (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS             (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL            (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT        (*(RwReg  *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (*(RwReg  *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT        (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK        (*(RwReg  *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg  *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (*(RwReg  *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_ALARM_NUM               1        // Number of Alarms
+#define RTC_COMP16_NUM              2        // Number of 16-bit Comparators
+#define RTC_COMP32_NUM              1        // Number of 32-bit Comparators
+#define RTC_GCLK_ID                 2        // Index of Generic Clock
+#define RTC_NUM_OF_ALARMS           1        // Number of Alarms (obsolete)
+#define RTC_NUM_OF_COMP16           2        // Number of 16-bit Comparators (obsolete)
+#define RTC_NUM_OF_COMP32           1        // Number of 32-bit Comparators (obsolete)
+
+#endif /* _SAMD20_RTC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom0.h
new file mode 100644
index 0000000000..32f7026324
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom0.h
@@ -0,0 +1,135 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SERCOM0_INSTANCE_
+#define _SAMD20_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA     (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_DBGCTRL   (0x42000808U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CM_BAUD      (0x4200080AU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (0x4200080CU) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (0x4200080DU) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (0x4200080EU) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (0x42000810U) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_ADDR      (0x42000814U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (0x42000818U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CS_CTRLA     (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR  (0x4200080CU) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (0x4200080DU) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (0x4200080EU) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (0x42000810U) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_ADDR      (0x42000814U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (0x42000818U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_DBGCTRL    (0x42000808U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_SPI_BAUD       (0x4200080AU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (0x4200080CU) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (0x4200080DU) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (0x4200080EU) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (0x42000810U) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_ADDR       (0x42000814U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (0x42000818U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_USART_CTRLA    (0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_DBGCTRL  (0x42000808U) /**< \brief (SERCOM0) USART Debug Control */
+#define REG_SERCOM0_USART_BAUD     (0x4200080AU) /**< \brief (SERCOM0) USART Baud */
+#define REG_SERCOM0_USART_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x4200080DU) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (0x4200080EU) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (0x42000810U) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_DATA     (0x42000818U) /**< \brief (SERCOM0) USART Data */
+#else
+#define REG_SERCOM0_I2CM_CTRLA     (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_DBGCTRL   (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CM_BAUD      (*(RwReg16*)0x4200080AU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_ADDR      (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CS_CTRLA     (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR  (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_ADDR      (*(RwReg  *)0x42000814U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_DBGCTRL    (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_SPI_BAUD       (*(RwReg8 *)0x4200080AU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_ADDR       (*(RwReg  *)0x42000814U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (*(RwReg16*)0x42000818U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_USART_CTRLA    (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_DBGCTRL  (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) USART Debug Control */
+#define REG_SERCOM0_USART_BAUD     (*(RwReg16*)0x4200080AU) /**< \brief (SERCOM0) USART Baud */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_DATA     (*(RwReg16*)0x42000818U) /**< \brief (SERCOM0) USART Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_GCLK_ID_CORE        13
+#define SERCOM0_GCLK_ID_SLOW        12
+#define SERCOM0_INT_MSB             3
+#define SERCOM0_PMSB                3
+
+#endif /* _SAMD20_SERCOM0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom1.h
new file mode 100644
index 0000000000..be4e606c4a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom1.h
@@ -0,0 +1,135 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SERCOM1_INSTANCE_
+#define _SAMD20_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA     (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_DBGCTRL   (0x42000C08U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CM_BAUD      (0x42000C0AU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (0x42000C0CU) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (0x42000C0DU) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (0x42000C0EU) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (0x42000C10U) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_ADDR      (0x42000C14U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (0x42000C18U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CS_CTRLA     (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR  (0x42000C0CU) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (0x42000C0DU) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (0x42000C0EU) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (0x42000C10U) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_ADDR      (0x42000C14U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (0x42000C18U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_DBGCTRL    (0x42000C08U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_SPI_BAUD       (0x42000C0AU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (0x42000C0CU) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (0x42000C0DU) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (0x42000C0EU) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (0x42000C10U) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_ADDR       (0x42000C14U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (0x42000C18U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_USART_CTRLA    (0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_DBGCTRL  (0x42000C08U) /**< \brief (SERCOM1) USART Debug Control */
+#define REG_SERCOM1_USART_BAUD     (0x42000C0AU) /**< \brief (SERCOM1) USART Baud */
+#define REG_SERCOM1_USART_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (0x42000C0EU) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (0x42000C10U) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_DATA     (0x42000C18U) /**< \brief (SERCOM1) USART Data */
+#else
+#define REG_SERCOM1_I2CM_CTRLA     (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_DBGCTRL   (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CM_BAUD      (*(RwReg16*)0x42000C0AU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_ADDR      (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CS_CTRLA     (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR  (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_ADDR      (*(RwReg  *)0x42000C14U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_DBGCTRL    (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_SPI_BAUD       (*(RwReg8 *)0x42000C0AU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_ADDR       (*(RwReg  *)0x42000C14U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (*(RwReg16*)0x42000C18U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_USART_CTRLA    (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_DBGCTRL  (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) USART Debug Control */
+#define REG_SERCOM1_USART_BAUD     (*(RwReg16*)0x42000C0AU) /**< \brief (SERCOM1) USART Baud */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_DATA     (*(RwReg16*)0x42000C18U) /**< \brief (SERCOM1) USART Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_GCLK_ID_CORE        14
+#define SERCOM1_GCLK_ID_SLOW        12
+#define SERCOM1_INT_MSB             3
+#define SERCOM1_PMSB                3
+
+#endif /* _SAMD20_SERCOM1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom2.h
new file mode 100644
index 0000000000..1eafbeef32
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom2.h
@@ -0,0 +1,135 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SERCOM2_INSTANCE_
+#define _SAMD20_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA     (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_DBGCTRL   (0x42001008U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CM_BAUD      (0x4200100AU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (0x4200100CU) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (0x4200100DU) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (0x4200100EU) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (0x42001010U) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_ADDR      (0x42001014U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (0x42001018U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CS_CTRLA     (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR  (0x4200100CU) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (0x4200100DU) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (0x4200100EU) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (0x42001010U) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_ADDR      (0x42001014U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (0x42001018U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_DBGCTRL    (0x42001008U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_SPI_BAUD       (0x4200100AU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (0x4200100CU) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (0x4200100DU) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (0x4200100EU) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (0x42001010U) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_ADDR       (0x42001014U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (0x42001018U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_USART_CTRLA    (0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_DBGCTRL  (0x42001008U) /**< \brief (SERCOM2) USART Debug Control */
+#define REG_SERCOM2_USART_BAUD     (0x4200100AU) /**< \brief (SERCOM2) USART Baud */
+#define REG_SERCOM2_USART_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x4200100DU) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (0x4200100EU) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (0x42001010U) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_DATA     (0x42001018U) /**< \brief (SERCOM2) USART Data */
+#else
+#define REG_SERCOM2_I2CM_CTRLA     (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_DBGCTRL   (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CM_BAUD      (*(RwReg16*)0x4200100AU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_ADDR      (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CS_CTRLA     (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR  (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_ADDR      (*(RwReg  *)0x42001014U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_DBGCTRL    (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_SPI_BAUD       (*(RwReg8 *)0x4200100AU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_ADDR       (*(RwReg  *)0x42001014U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (*(RwReg16*)0x42001018U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_USART_CTRLA    (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_DBGCTRL  (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) USART Debug Control */
+#define REG_SERCOM2_USART_BAUD     (*(RwReg16*)0x4200100AU) /**< \brief (SERCOM2) USART Baud */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_DATA     (*(RwReg16*)0x42001018U) /**< \brief (SERCOM2) USART Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_GCLK_ID_CORE        15
+#define SERCOM2_GCLK_ID_SLOW        12
+#define SERCOM2_INT_MSB             3
+#define SERCOM2_PMSB                3
+
+#endif /* _SAMD20_SERCOM2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom3.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom3.h
new file mode 100644
index 0000000000..8edc6a8bcc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom3.h
@@ -0,0 +1,135 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SERCOM3_INSTANCE_
+#define _SAMD20_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA     (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_DBGCTRL   (0x42001408U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CM_BAUD      (0x4200140AU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (0x4200140CU) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (0x4200140DU) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (0x4200140EU) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (0x42001410U) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_ADDR      (0x42001414U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (0x42001418U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CS_CTRLA     (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR  (0x4200140CU) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (0x4200140DU) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (0x4200140EU) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (0x42001410U) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_ADDR      (0x42001414U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (0x42001418U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_DBGCTRL    (0x42001408U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_SPI_BAUD       (0x4200140AU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (0x4200140CU) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (0x4200140DU) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (0x4200140EU) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (0x42001410U) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_ADDR       (0x42001414U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (0x42001418U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_USART_CTRLA    (0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_DBGCTRL  (0x42001408U) /**< \brief (SERCOM3) USART Debug Control */
+#define REG_SERCOM3_USART_BAUD     (0x4200140AU) /**< \brief (SERCOM3) USART Baud */
+#define REG_SERCOM3_USART_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x4200140DU) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (0x4200140EU) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (0x42001410U) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_DATA     (0x42001418U) /**< \brief (SERCOM3) USART Data */
+#else
+#define REG_SERCOM3_I2CM_CTRLA     (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_DBGCTRL   (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CM_BAUD      (*(RwReg16*)0x4200140AU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_ADDR      (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CS_CTRLA     (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR  (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_ADDR      (*(RwReg  *)0x42001414U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_DBGCTRL    (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_SPI_BAUD       (*(RwReg8 *)0x4200140AU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_ADDR       (*(RwReg  *)0x42001414U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (*(RwReg16*)0x42001418U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_USART_CTRLA    (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_DBGCTRL  (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) USART Debug Control */
+#define REG_SERCOM3_USART_BAUD     (*(RwReg16*)0x4200140AU) /**< \brief (SERCOM3) USART Baud */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_DATA     (*(RwReg16*)0x42001418U) /**< \brief (SERCOM3) USART Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_GCLK_ID_CORE        16
+#define SERCOM3_GCLK_ID_SLOW        12
+#define SERCOM3_INT_MSB             3
+#define SERCOM3_PMSB                3
+
+#endif /* _SAMD20_SERCOM3_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom4.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom4.h
new file mode 100644
index 0000000000..8e9f3732f6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom4.h
@@ -0,0 +1,135 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SERCOM4_INSTANCE_
+#define _SAMD20_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA     (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_DBGCTRL   (0x42001808U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CM_BAUD      (0x4200180AU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (0x4200180CU) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (0x4200180DU) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (0x4200180EU) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (0x42001810U) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_ADDR      (0x42001814U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (0x42001818U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CS_CTRLA     (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR  (0x4200180CU) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (0x4200180DU) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (0x4200180EU) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (0x42001810U) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_ADDR      (0x42001814U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (0x42001818U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_DBGCTRL    (0x42001808U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_SPI_BAUD       (0x4200180AU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (0x4200180CU) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (0x4200180DU) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (0x4200180EU) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (0x42001810U) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_ADDR       (0x42001814U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (0x42001818U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_USART_CTRLA    (0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_DBGCTRL  (0x42001808U) /**< \brief (SERCOM4) USART Debug Control */
+#define REG_SERCOM4_USART_BAUD     (0x4200180AU) /**< \brief (SERCOM4) USART Baud */
+#define REG_SERCOM4_USART_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x4200180DU) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (0x4200180EU) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (0x42001810U) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_DATA     (0x42001818U) /**< \brief (SERCOM4) USART Data */
+#else
+#define REG_SERCOM4_I2CM_CTRLA     (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_DBGCTRL   (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CM_BAUD      (*(RwReg16*)0x4200180AU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_ADDR      (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CS_CTRLA     (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR  (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_ADDR      (*(RwReg  *)0x42001814U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_DBGCTRL    (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_SPI_BAUD       (*(RwReg8 *)0x4200180AU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_ADDR       (*(RwReg  *)0x42001814U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (*(RwReg16*)0x42001818U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_USART_CTRLA    (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_DBGCTRL  (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) USART Debug Control */
+#define REG_SERCOM4_USART_BAUD     (*(RwReg16*)0x4200180AU) /**< \brief (SERCOM4) USART Baud */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_DATA     (*(RwReg16*)0x42001818U) /**< \brief (SERCOM4) USART Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_GCLK_ID_CORE        17
+#define SERCOM4_GCLK_ID_SLOW        12
+#define SERCOM4_INT_MSB             3
+#define SERCOM4_PMSB                3
+
+#endif /* _SAMD20_SERCOM4_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom5.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom5.h
new file mode 100644
index 0000000000..28cccf6816
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sercom5.h
@@ -0,0 +1,135 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SERCOM5_INSTANCE_
+#define _SAMD20_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA     (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_DBGCTRL   (0x42001C08U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CM_BAUD      (0x42001C0AU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (0x42001C0CU) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (0x42001C0DU) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (0x42001C0EU) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (0x42001C10U) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_ADDR      (0x42001C14U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (0x42001C18U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CS_CTRLA     (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR  (0x42001C0CU) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (0x42001C0DU) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (0x42001C0EU) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (0x42001C10U) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_ADDR      (0x42001C14U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (0x42001C18U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_DBGCTRL    (0x42001C08U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_SPI_BAUD       (0x42001C0AU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (0x42001C0CU) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (0x42001C0DU) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (0x42001C0EU) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (0x42001C10U) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_ADDR       (0x42001C14U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (0x42001C18U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_USART_CTRLA    (0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_DBGCTRL  (0x42001C08U) /**< \brief (SERCOM5) USART Debug Control */
+#define REG_SERCOM5_USART_BAUD     (0x42001C0AU) /**< \brief (SERCOM5) USART Baud */
+#define REG_SERCOM5_USART_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (0x42001C0EU) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (0x42001C10U) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_DATA     (0x42001C18U) /**< \brief (SERCOM5) USART Data */
+#else
+#define REG_SERCOM5_I2CM_CTRLA     (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_DBGCTRL   (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CM_BAUD      (*(RwReg16*)0x42001C0AU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_ADDR      (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CS_CTRLA     (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR  (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_ADDR      (*(RwReg  *)0x42001C14U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_DBGCTRL    (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_SPI_BAUD       (*(RwReg8 *)0x42001C0AU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_ADDR       (*(RwReg  *)0x42001C14U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (*(RwReg16*)0x42001C18U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_USART_CTRLA    (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_DBGCTRL  (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) USART Debug Control */
+#define REG_SERCOM5_USART_BAUD     (*(RwReg16*)0x42001C0AU) /**< \brief (SERCOM5) USART Baud */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_DATA     (*(RwReg16*)0x42001C18U) /**< \brief (SERCOM5) USART Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_GCLK_ID_CORE        18
+#define SERCOM5_GCLK_ID_SLOW        12
+#define SERCOM5_INT_MSB             3
+#define SERCOM5_PMSB                3
+
+#endif /* _SAMD20_SERCOM5_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sysctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sysctrl.h
new file mode 100644
index 0000000000..76bc298ac7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sysctrl.h
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SYSCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_SYSCTRL_INSTANCE_
+#define _SAMD20_SYSCTRL_INSTANCE_
+
+/* ========== Register definition for SYSCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SYSCTRL_INTENCLR       (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET       (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG        (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR         (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC           (0x40000810U) /**< \brief (SYSCTRL) XOSC Control */
+#define REG_SYSCTRL_XOSC32K        (0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control */
+#define REG_SYSCTRL_OSC32K         (0x40000818U) /**< \brief (SYSCTRL) OSC32K Control */
+#define REG_SYSCTRL_OSCULP32K      (0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control */
+#define REG_SYSCTRL_OSC8M          (0x40000820U) /**< \brief (SYSCTRL) OSC8M Control A */
+#define REG_SYSCTRL_DFLLCTRL       (0x40000824U) /**< \brief (SYSCTRL) DFLL Config */
+#define REG_SYSCTRL_DFLLVAL        (0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value */
+#define REG_SYSCTRL_DFLLMUL        (0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier */
+#define REG_SYSCTRL_DFLLSYNC       (0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization */
+#define REG_SYSCTRL_BOD33          (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG           (0x4000083CU) /**< \brief (SYSCTRL) VREG Control */
+#define REG_SYSCTRL_VREF           (0x40000840U) /**< \brief (SYSCTRL) VREF Control A */
+#else
+#define REG_SYSCTRL_INTENCLR       (*(RwReg  *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET       (*(RwReg  *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG        (*(RwReg  *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR         (*(RoReg  *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC           (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) XOSC Control */
+#define REG_SYSCTRL_XOSC32K        (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control */
+#define REG_SYSCTRL_OSC32K         (*(RwReg  *)0x40000818U) /**< \brief (SYSCTRL) OSC32K Control */
+#define REG_SYSCTRL_OSCULP32K      (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control */
+#define REG_SYSCTRL_OSC8M          (*(RwReg  *)0x40000820U) /**< \brief (SYSCTRL) OSC8M Control A */
+#define REG_SYSCTRL_DFLLCTRL       (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL Config */
+#define REG_SYSCTRL_DFLLVAL        (*(RwReg  *)0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value */
+#define REG_SYSCTRL_DFLLMUL        (*(RwReg  *)0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier */
+#define REG_SYSCTRL_DFLLSYNC       (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization */
+#define REG_SYSCTRL_BOD33          (*(RwReg  *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG           (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) VREG Control */
+#define REG_SYSCTRL_VREF           (*(RwReg  *)0x40000840U) /**< \brief (SYSCTRL) VREF Control A */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SYSCTRL peripheral ========== */
+#define SYSCTRL_BGAP_CALIB_MSB      11
+#define SYSCTRL_BOD33_CALIB_MSB     5
+#define SYSCTRL_DFLL48M_COARSE_MSB  4
+#define SYSCTRL_DFLL48M_FINE_MSB    7
+#define SYSCTRL_GCLK_ID_DFLL48      0
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
+#define SYSCTRL_POR33_ENTEST_MSB    1
+#define SYSCTRL_ULPVREF_DIVLEV_MSB  3
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
+#define SYSCTRL_VREF_CONTROL_MSB    48
+#define SYSCTRL_VREF_STATUS_MSB     7
+#define SYSCTRL_VREG_LEVEL_MSB      2
+#define SYSCTRL_BOD12_VERSION       0x111
+#define SYSCTRL_BOD33_VERSION       0x111
+#define SYSCTRL_DFLL48M_VERSION     0x211   
+#define SYSCTRL_GCLK_VERSION        0x210
+#define SYSCTRL_OSCULP32K_VERSION   0x111
+#define SYSCTRL_OSC8M_VERSION       0x120
+#define SYSCTRL_OSC32K_VERSION      0x1101  
+#define SYSCTRL_VREF_VERSION        0x200
+#define SYSCTRL_VREG_VERSION        0x201
+#define SYSCTRL_XOSC_VERSION        0x1101  
+#define SYSCTRL_XOSC32K_VERSION     0x1101  
+
+#endif /* _SAMD20_SYSCTRL_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc0.h
new file mode 100644
index 0000000000..c8fd8971fd
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc0.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC0
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC0_INSTANCE_
+#define _SAMD20_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CTRLA              (0x42002000U) /**< \brief (TC0) Control A */
+#define REG_TC0_READREQ            (0x42002002U) /**< \brief (TC0) Read Request */
+#define REG_TC0_CTRLBCLR           (0x42002004U) /**< \brief (TC0) Control B Clear */
+#define REG_TC0_CTRLBSET           (0x42002005U) /**< \brief (TC0) Control B Set */
+#define REG_TC0_CTRLC              (0x42002006U) /**< \brief (TC0) Control C */
+#define REG_TC0_DBGCTRL            (0x42002008U) /**< \brief (TC0) Debug Control */
+#define REG_TC0_EVCTRL             (0x4200200AU) /**< \brief (TC0) Event Control */
+#define REG_TC0_INTENCLR           (0x4200200CU) /**< \brief (TC0) Interrupt Enable Clear */
+#define REG_TC0_INTENSET           (0x4200200DU) /**< \brief (TC0) Interrupt Enable Set */
+#define REG_TC0_INTFLAG            (0x4200200EU) /**< \brief (TC0) Interrupt Flag Status and Clear */
+#define REG_TC0_STATUS             (0x4200200FU) /**< \brief (TC0) Status */
+#define REG_TC0_COUNT16_COUNT      (0x42002010U) /**< \brief (TC0) COUNT16 Counter Value */
+#define REG_TC0_COUNT16_CC0        (0x42002018U) /**< \brief (TC0) COUNT16 Compare/Capture 0 */
+#define REG_TC0_COUNT16_CC1        (0x4200201AU) /**< \brief (TC0) COUNT16 Compare/Capture 1 */
+#define REG_TC0_COUNT32_COUNT      (0x42002010U) /**< \brief (TC0) COUNT32 Counter Value */
+#define REG_TC0_COUNT32_CC0        (0x42002018U) /**< \brief (TC0) COUNT32 Compare/Capture 0 */
+#define REG_TC0_COUNT32_CC1        (0x4200201CU) /**< \brief (TC0) COUNT32 Compare/Capture 1 */
+#define REG_TC0_COUNT8_COUNT       (0x42002010U) /**< \brief (TC0) COUNT8 Counter Value */
+#define REG_TC0_COUNT8_PER         (0x42002014U) /**< \brief (TC0) COUNT8 Period Value */
+#define REG_TC0_COUNT8_CC0         (0x42002018U) /**< \brief (TC0) COUNT8 Compare/Capture 0 */
+#define REG_TC0_COUNT8_CC1         (0x42002019U) /**< \brief (TC0) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC0_CTRLA              (*(RwReg16*)0x42002000U) /**< \brief (TC0) Control A */
+#define REG_TC0_READREQ            (*(RwReg16*)0x42002002U) /**< \brief (TC0) Read Request */
+#define REG_TC0_CTRLBCLR           (*(RwReg8 *)0x42002004U) /**< \brief (TC0) Control B Clear */
+#define REG_TC0_CTRLBSET           (*(RwReg8 *)0x42002005U) /**< \brief (TC0) Control B Set */
+#define REG_TC0_CTRLC              (*(RwReg8 *)0x42002006U) /**< \brief (TC0) Control C */
+#define REG_TC0_DBGCTRL            (*(RwReg8 *)0x42002008U) /**< \brief (TC0) Debug Control */
+#define REG_TC0_EVCTRL             (*(RwReg16*)0x4200200AU) /**< \brief (TC0) Event Control */
+#define REG_TC0_INTENCLR           (*(RwReg8 *)0x4200200CU) /**< \brief (TC0) Interrupt Enable Clear */
+#define REG_TC0_INTENSET           (*(RwReg8 *)0x4200200DU) /**< \brief (TC0) Interrupt Enable Set */
+#define REG_TC0_INTFLAG            (*(RwReg8 *)0x4200200EU) /**< \brief (TC0) Interrupt Flag Status and Clear */
+#define REG_TC0_STATUS             (*(RoReg8 *)0x4200200FU) /**< \brief (TC0) Status */
+#define REG_TC0_COUNT16_COUNT      (*(RwReg16*)0x42002010U) /**< \brief (TC0) COUNT16 Counter Value */
+#define REG_TC0_COUNT16_CC0        (*(RwReg16*)0x42002018U) /**< \brief (TC0) COUNT16 Compare/Capture 0 */
+#define REG_TC0_COUNT16_CC1        (*(RwReg16*)0x4200201AU) /**< \brief (TC0) COUNT16 Compare/Capture 1 */
+#define REG_TC0_COUNT32_COUNT      (*(RwReg  *)0x42002010U) /**< \brief (TC0) COUNT32 Counter Value */
+#define REG_TC0_COUNT32_CC0        (*(RwReg  *)0x42002018U) /**< \brief (TC0) COUNT32 Compare/Capture 0 */
+#define REG_TC0_COUNT32_CC1        (*(RwReg  *)0x4200201CU) /**< \brief (TC0) COUNT32 Compare/Capture 1 */
+#define REG_TC0_COUNT8_COUNT       (*(RwReg8 *)0x42002010U) /**< \brief (TC0) COUNT8 Counter Value */
+#define REG_TC0_COUNT8_PER         (*(RwReg8 *)0x42002014U) /**< \brief (TC0) COUNT8 Period Value */
+#define REG_TC0_COUNT8_CC0         (*(RwReg8 *)0x42002018U) /**< \brief (TC0) COUNT8 Compare/Capture 0 */
+#define REG_TC0_COUNT8_CC1         (*(RwReg8 *)0x42002019U) /**< \brief (TC0) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC0 peripheral ========== */
+#define TC0_CC8_NUM                 2
+#define TC0_CC16_NUM                2
+#define TC0_CC32_NUM                2
+#define TC0_DITHERING_EXT           0
+#define TC0_GCLK_ID                 19
+#define TC0_MASTER                  1
+#define TC0_OW_NUM                  2
+#define TC0_PERIOD_EXT              0
+#define TC0_SHADOW_EXT              0
+
+#endif /* _SAMD20_TC0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc1.h
new file mode 100644
index 0000000000..2999e7c942
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc1.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC1
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC1_INSTANCE_
+#define _SAMD20_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CTRLA              (0x42002400U) /**< \brief (TC1) Control A */
+#define REG_TC1_READREQ            (0x42002402U) /**< \brief (TC1) Read Request */
+#define REG_TC1_CTRLBCLR           (0x42002404U) /**< \brief (TC1) Control B Clear */
+#define REG_TC1_CTRLBSET           (0x42002405U) /**< \brief (TC1) Control B Set */
+#define REG_TC1_CTRLC              (0x42002406U) /**< \brief (TC1) Control C */
+#define REG_TC1_DBGCTRL            (0x42002408U) /**< \brief (TC1) Debug Control */
+#define REG_TC1_EVCTRL             (0x4200240AU) /**< \brief (TC1) Event Control */
+#define REG_TC1_INTENCLR           (0x4200240CU) /**< \brief (TC1) Interrupt Enable Clear */
+#define REG_TC1_INTENSET           (0x4200240DU) /**< \brief (TC1) Interrupt Enable Set */
+#define REG_TC1_INTFLAG            (0x4200240EU) /**< \brief (TC1) Interrupt Flag Status and Clear */
+#define REG_TC1_STATUS             (0x4200240FU) /**< \brief (TC1) Status */
+#define REG_TC1_COUNT16_COUNT      (0x42002410U) /**< \brief (TC1) COUNT16 Counter Value */
+#define REG_TC1_COUNT16_CC0        (0x42002418U) /**< \brief (TC1) COUNT16 Compare/Capture 0 */
+#define REG_TC1_COUNT16_CC1        (0x4200241AU) /**< \brief (TC1) COUNT16 Compare/Capture 1 */
+#define REG_TC1_COUNT32_COUNT      (0x42002410U) /**< \brief (TC1) COUNT32 Counter Value */
+#define REG_TC1_COUNT32_CC0        (0x42002418U) /**< \brief (TC1) COUNT32 Compare/Capture 0 */
+#define REG_TC1_COUNT32_CC1        (0x4200241CU) /**< \brief (TC1) COUNT32 Compare/Capture 1 */
+#define REG_TC1_COUNT8_COUNT       (0x42002410U) /**< \brief (TC1) COUNT8 Counter Value */
+#define REG_TC1_COUNT8_PER         (0x42002414U) /**< \brief (TC1) COUNT8 Period Value */
+#define REG_TC1_COUNT8_CC0         (0x42002418U) /**< \brief (TC1) COUNT8 Compare/Capture 0 */
+#define REG_TC1_COUNT8_CC1         (0x42002419U) /**< \brief (TC1) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC1_CTRLA              (*(RwReg16*)0x42002400U) /**< \brief (TC1) Control A */
+#define REG_TC1_READREQ            (*(RwReg16*)0x42002402U) /**< \brief (TC1) Read Request */
+#define REG_TC1_CTRLBCLR           (*(RwReg8 *)0x42002404U) /**< \brief (TC1) Control B Clear */
+#define REG_TC1_CTRLBSET           (*(RwReg8 *)0x42002405U) /**< \brief (TC1) Control B Set */
+#define REG_TC1_CTRLC              (*(RwReg8 *)0x42002406U) /**< \brief (TC1) Control C */
+#define REG_TC1_DBGCTRL            (*(RwReg8 *)0x42002408U) /**< \brief (TC1) Debug Control */
+#define REG_TC1_EVCTRL             (*(RwReg16*)0x4200240AU) /**< \brief (TC1) Event Control */
+#define REG_TC1_INTENCLR           (*(RwReg8 *)0x4200240CU) /**< \brief (TC1) Interrupt Enable Clear */
+#define REG_TC1_INTENSET           (*(RwReg8 *)0x4200240DU) /**< \brief (TC1) Interrupt Enable Set */
+#define REG_TC1_INTFLAG            (*(RwReg8 *)0x4200240EU) /**< \brief (TC1) Interrupt Flag Status and Clear */
+#define REG_TC1_STATUS             (*(RoReg8 *)0x4200240FU) /**< \brief (TC1) Status */
+#define REG_TC1_COUNT16_COUNT      (*(RwReg16*)0x42002410U) /**< \brief (TC1) COUNT16 Counter Value */
+#define REG_TC1_COUNT16_CC0        (*(RwReg16*)0x42002418U) /**< \brief (TC1) COUNT16 Compare/Capture 0 */
+#define REG_TC1_COUNT16_CC1        (*(RwReg16*)0x4200241AU) /**< \brief (TC1) COUNT16 Compare/Capture 1 */
+#define REG_TC1_COUNT32_COUNT      (*(RwReg  *)0x42002410U) /**< \brief (TC1) COUNT32 Counter Value */
+#define REG_TC1_COUNT32_CC0        (*(RwReg  *)0x42002418U) /**< \brief (TC1) COUNT32 Compare/Capture 0 */
+#define REG_TC1_COUNT32_CC1        (*(RwReg  *)0x4200241CU) /**< \brief (TC1) COUNT32 Compare/Capture 1 */
+#define REG_TC1_COUNT8_COUNT       (*(RwReg8 *)0x42002410U) /**< \brief (TC1) COUNT8 Counter Value */
+#define REG_TC1_COUNT8_PER         (*(RwReg8 *)0x42002414U) /**< \brief (TC1) COUNT8 Period Value */
+#define REG_TC1_COUNT8_CC0         (*(RwReg8 *)0x42002418U) /**< \brief (TC1) COUNT8 Compare/Capture 0 */
+#define REG_TC1_COUNT8_CC1         (*(RwReg8 *)0x42002419U) /**< \brief (TC1) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC1 peripheral ========== */
+#define TC1_CC8_NUM                 2
+#define TC1_CC16_NUM                2
+#define TC1_CC32_NUM                2
+#define TC1_DITHERING_EXT           0
+#define TC1_GCLK_ID                 19
+#define TC1_MASTER                  0
+#define TC1_OW_NUM                  2
+#define TC1_PERIOD_EXT              0
+#define TC1_SHADOW_EXT              0
+
+#endif /* _SAMD20_TC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc2.h
new file mode 100644
index 0000000000..513733ddf9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc2.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC2
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC2_INSTANCE_
+#define _SAMD20_TC2_INSTANCE_
+
+/* ========== Register definition for TC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC2_CTRLA              (0x42002800U) /**< \brief (TC2) Control A */
+#define REG_TC2_READREQ            (0x42002802U) /**< \brief (TC2) Read Request */
+#define REG_TC2_CTRLBCLR           (0x42002804U) /**< \brief (TC2) Control B Clear */
+#define REG_TC2_CTRLBSET           (0x42002805U) /**< \brief (TC2) Control B Set */
+#define REG_TC2_CTRLC              (0x42002806U) /**< \brief (TC2) Control C */
+#define REG_TC2_DBGCTRL            (0x42002808U) /**< \brief (TC2) Debug Control */
+#define REG_TC2_EVCTRL             (0x4200280AU) /**< \brief (TC2) Event Control */
+#define REG_TC2_INTENCLR           (0x4200280CU) /**< \brief (TC2) Interrupt Enable Clear */
+#define REG_TC2_INTENSET           (0x4200280DU) /**< \brief (TC2) Interrupt Enable Set */
+#define REG_TC2_INTFLAG            (0x4200280EU) /**< \brief (TC2) Interrupt Flag Status and Clear */
+#define REG_TC2_STATUS             (0x4200280FU) /**< \brief (TC2) Status */
+#define REG_TC2_COUNT16_COUNT      (0x42002810U) /**< \brief (TC2) COUNT16 Counter Value */
+#define REG_TC2_COUNT16_CC0        (0x42002818U) /**< \brief (TC2) COUNT16 Compare/Capture 0 */
+#define REG_TC2_COUNT16_CC1        (0x4200281AU) /**< \brief (TC2) COUNT16 Compare/Capture 1 */
+#define REG_TC2_COUNT32_COUNT      (0x42002810U) /**< \brief (TC2) COUNT32 Counter Value */
+#define REG_TC2_COUNT32_CC0        (0x42002818U) /**< \brief (TC2) COUNT32 Compare/Capture 0 */
+#define REG_TC2_COUNT32_CC1        (0x4200281CU) /**< \brief (TC2) COUNT32 Compare/Capture 1 */
+#define REG_TC2_COUNT8_COUNT       (0x42002810U) /**< \brief (TC2) COUNT8 Counter Value */
+#define REG_TC2_COUNT8_PER         (0x42002814U) /**< \brief (TC2) COUNT8 Period Value */
+#define REG_TC2_COUNT8_CC0         (0x42002818U) /**< \brief (TC2) COUNT8 Compare/Capture 0 */
+#define REG_TC2_COUNT8_CC1         (0x42002819U) /**< \brief (TC2) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC2_CTRLA              (*(RwReg16*)0x42002800U) /**< \brief (TC2) Control A */
+#define REG_TC2_READREQ            (*(RwReg16*)0x42002802U) /**< \brief (TC2) Read Request */
+#define REG_TC2_CTRLBCLR           (*(RwReg8 *)0x42002804U) /**< \brief (TC2) Control B Clear */
+#define REG_TC2_CTRLBSET           (*(RwReg8 *)0x42002805U) /**< \brief (TC2) Control B Set */
+#define REG_TC2_CTRLC              (*(RwReg8 *)0x42002806U) /**< \brief (TC2) Control C */
+#define REG_TC2_DBGCTRL            (*(RwReg8 *)0x42002808U) /**< \brief (TC2) Debug Control */
+#define REG_TC2_EVCTRL             (*(RwReg16*)0x4200280AU) /**< \brief (TC2) Event Control */
+#define REG_TC2_INTENCLR           (*(RwReg8 *)0x4200280CU) /**< \brief (TC2) Interrupt Enable Clear */
+#define REG_TC2_INTENSET           (*(RwReg8 *)0x4200280DU) /**< \brief (TC2) Interrupt Enable Set */
+#define REG_TC2_INTFLAG            (*(RwReg8 *)0x4200280EU) /**< \brief (TC2) Interrupt Flag Status and Clear */
+#define REG_TC2_STATUS             (*(RoReg8 *)0x4200280FU) /**< \brief (TC2) Status */
+#define REG_TC2_COUNT16_COUNT      (*(RwReg16*)0x42002810U) /**< \brief (TC2) COUNT16 Counter Value */
+#define REG_TC2_COUNT16_CC0        (*(RwReg16*)0x42002818U) /**< \brief (TC2) COUNT16 Compare/Capture 0 */
+#define REG_TC2_COUNT16_CC1        (*(RwReg16*)0x4200281AU) /**< \brief (TC2) COUNT16 Compare/Capture 1 */
+#define REG_TC2_COUNT32_COUNT      (*(RwReg  *)0x42002810U) /**< \brief (TC2) COUNT32 Counter Value */
+#define REG_TC2_COUNT32_CC0        (*(RwReg  *)0x42002818U) /**< \brief (TC2) COUNT32 Compare/Capture 0 */
+#define REG_TC2_COUNT32_CC1        (*(RwReg  *)0x4200281CU) /**< \brief (TC2) COUNT32 Compare/Capture 1 */
+#define REG_TC2_COUNT8_COUNT       (*(RwReg8 *)0x42002810U) /**< \brief (TC2) COUNT8 Counter Value */
+#define REG_TC2_COUNT8_PER         (*(RwReg8 *)0x42002814U) /**< \brief (TC2) COUNT8 Period Value */
+#define REG_TC2_COUNT8_CC0         (*(RwReg8 *)0x42002818U) /**< \brief (TC2) COUNT8 Compare/Capture 0 */
+#define REG_TC2_COUNT8_CC1         (*(RwReg8 *)0x42002819U) /**< \brief (TC2) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC2 peripheral ========== */
+#define TC2_CC8_NUM                 2
+#define TC2_CC16_NUM                2
+#define TC2_CC32_NUM                2
+#define TC2_DITHERING_EXT           0
+#define TC2_GCLK_ID                 20
+#define TC2_MASTER                  1
+#define TC2_OW_NUM                  2
+#define TC2_PERIOD_EXT              0
+#define TC2_SHADOW_EXT              0
+
+#endif /* _SAMD20_TC2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc3.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc3.h
new file mode 100644
index 0000000000..39b2804a7e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc3.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC3_INSTANCE_
+#define _SAMD20_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA              (0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ            (0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR           (0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC              (0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL             (0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT      (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0        (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1        (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT      (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0        (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1        (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT       (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER         (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0         (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1         (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC3_CTRLA              (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ            (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR           (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC              (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL             (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT      (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0        (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1        (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT      (*(RwReg  *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0        (*(RwReg  *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1        (*(RwReg  *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT       (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER         (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0         (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1         (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC8_NUM                 2
+#define TC3_CC16_NUM                2
+#define TC3_CC32_NUM                2
+#define TC3_DITHERING_EXT           0
+#define TC3_GCLK_ID                 20
+#define TC3_MASTER                  0
+#define TC3_OW_NUM                  2
+#define TC3_PERIOD_EXT              0
+#define TC3_SHADOW_EXT              0
+
+#endif /* _SAMD20_TC3_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc4.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc4.h
new file mode 100644
index 0000000000..cd3b732784
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc4.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC4
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC4_INSTANCE_
+#define _SAMD20_TC4_INSTANCE_
+
+/* ========== Register definition for TC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC4_CTRLA              (0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ            (0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR           (0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC              (0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL             (0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT      (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0        (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1        (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT      (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0        (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1        (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT       (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER         (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0         (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1         (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC4_CTRLA              (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ            (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR           (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC              (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL             (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT      (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0        (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1        (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT      (*(RwReg  *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0        (*(RwReg  *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1        (*(RwReg  *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT       (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER         (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0         (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1         (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC4 peripheral ========== */
+#define TC4_CC8_NUM                 2
+#define TC4_CC16_NUM                2
+#define TC4_CC32_NUM                2
+#define TC4_DITHERING_EXT           0
+#define TC4_GCLK_ID                 21
+#define TC4_MASTER                  1
+#define TC4_OW_NUM                  2
+#define TC4_PERIOD_EXT              0
+#define TC4_SHADOW_EXT              0
+
+#endif /* _SAMD20_TC4_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc5.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc5.h
new file mode 100644
index 0000000000..d57b1b4b16
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc5.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC5
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC5_INSTANCE_
+#define _SAMD20_TC5_INSTANCE_
+
+/* ========== Register definition for TC5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC5_CTRLA              (0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ            (0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR           (0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC              (0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL             (0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT      (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0        (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1        (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT      (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0        (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1        (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT       (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER         (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0         (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1         (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC5_CTRLA              (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ            (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR           (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC              (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL             (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT      (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0        (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1        (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT      (*(RwReg  *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0        (*(RwReg  *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1        (*(RwReg  *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT       (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER         (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0         (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1         (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC5 peripheral ========== */
+#define TC5_CC8_NUM                 2
+#define TC5_CC16_NUM                2
+#define TC5_CC32_NUM                2
+#define TC5_DITHERING_EXT           0
+#define TC5_GCLK_ID                 21
+#define TC5_MASTER                  0
+#define TC5_OW_NUM                  2
+#define TC5_PERIOD_EXT              0
+#define TC5_SHADOW_EXT              0
+
+#endif /* _SAMD20_TC5_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc6.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc6.h
new file mode 100644
index 0000000000..632334f64b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc6.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC6
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC6_INSTANCE_
+#define _SAMD20_TC6_INSTANCE_
+
+/* ========== Register definition for TC6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC6_CTRLA              (0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ            (0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR           (0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC              (0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL             (0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT      (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0        (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1        (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT      (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0        (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1        (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT       (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER         (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0         (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1         (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC6_CTRLA              (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ            (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR           (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC              (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL             (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT      (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0        (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1        (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT      (*(RwReg  *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0        (*(RwReg  *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1        (*(RwReg  *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT       (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER         (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0         (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1         (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC6 peripheral ========== */
+#define TC6_CC8_NUM                 2
+#define TC6_CC16_NUM                2
+#define TC6_CC32_NUM                2
+#define TC6_DITHERING_EXT           0
+#define TC6_GCLK_ID                 22
+#define TC6_MASTER                  1
+#define TC6_OW_NUM                  2
+#define TC6_PERIOD_EXT              0
+#define TC6_SHADOW_EXT              0
+
+#endif /* _SAMD20_TC6_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc7.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc7.h
new file mode 100644
index 0000000000..0b439eb6e6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/tc7.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC7
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_TC7_INSTANCE_
+#define _SAMD20_TC7_INSTANCE_
+
+/* ========== Register definition for TC7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC7_CTRLA              (0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ            (0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR           (0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC              (0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL             (0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT      (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0        (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1        (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT      (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0        (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1        (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT       (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER         (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0         (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1         (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC7_CTRLA              (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ            (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR           (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC              (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL             (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT      (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0        (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1        (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT      (*(RwReg  *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0        (*(RwReg  *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1        (*(RwReg  *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT       (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER         (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0         (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1         (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC7 peripheral ========== */
+#define TC7_CC8_NUM                 2
+#define TC7_CC16_NUM                2
+#define TC7_CC32_NUM                2
+#define TC7_DITHERING_EXT           0
+#define TC7_GCLK_ID                 22
+#define TC7_MASTER                  0
+#define TC7_OW_NUM                  2
+#define TC7_PERIOD_EXT              0
+#define TC7_SHADOW_EXT              0
+
+#endif /* _SAMD20_TC7_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/wdt.h
new file mode 100644
index 0000000000..22470ad3b1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/wdt.h
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_WDT_INSTANCE_
+#define _SAMD20_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRL               (0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS             (0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR              (0x40001008U) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRL               (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS             (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR              (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for WDT peripheral ========== */
+#define WDT_GCLK_ID                 1        // Index of Generic Clock
+
+#endif /* _SAMD20_WDT_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e14.h
new file mode 100644
index 0000000000..4695c94213
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e14.h
@@ -0,0 +1,550 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20E14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E14_PIO_
+#define _SAMD20E14_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20E14_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e15.h
new file mode 100644
index 0000000000..ce79eec08c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e15.h
@@ -0,0 +1,550 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20E15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E15_PIO_
+#define _SAMD20E15_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20E15_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e16.h
new file mode 100644
index 0000000000..3cfe1bbf77
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e16.h
@@ -0,0 +1,550 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20E16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E16_PIO_
+#define _SAMD20E16_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20E16_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e17.h
new file mode 100644
index 0000000000..ccd7183443
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e17.h
@@ -0,0 +1,550 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20E17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E17_PIO_
+#define _SAMD20E17_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20E17_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e18.h
new file mode 100644
index 0000000000..e9192136c0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20e18.h
@@ -0,0 +1,550 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20E18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E18_PIO_
+#define _SAMD20E18_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20E18_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g14.h
new file mode 100644
index 0000000000..0a2275acc9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g14.h
@@ -0,0 +1,781 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20G14
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G14_PIO_
+#define _SAMD20G14_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20G14_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g15.h
new file mode 100644
index 0000000000..c5ae2df381
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g15.h
@@ -0,0 +1,781 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20G15
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G15_PIO_
+#define _SAMD20G15_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20G15_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g16.h
new file mode 100644
index 0000000000..9b58f375d2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g16.h
@@ -0,0 +1,781 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20G16
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G16_PIO_
+#define _SAMD20G16_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20G16_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g17.h
new file mode 100644
index 0000000000..ea4730f5c2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g17.h
@@ -0,0 +1,781 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20G17
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G17_PIO_
+#define _SAMD20G17_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20G17_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g17u.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g17u.h
new file mode 100644
index 0000000000..b23e707977
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g17u.h
@@ -0,0 +1,727 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20G17U
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G17U_PIO_
+#define _SAMD20G17U_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20G17U_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g18.h
new file mode 100644
index 0000000000..2e08c8f98c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g18.h
@@ -0,0 +1,781 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20G18
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G18_PIO_
+#define _SAMD20G18_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20G18_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g18u.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g18u.h
new file mode 100644
index 0000000000..12019610e5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20g18u.h
@@ -0,0 +1,727 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20G18U
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G18U_PIO_
+#define _SAMD20G18U_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20G18U_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j14.h
new file mode 100644
index 0000000000..57aaa4b7b1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j14.h
@@ -0,0 +1,1022 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20J14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J14_PIO_
+#define _SAMD20J14_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PB30F_TC0_WO0                 62L  /**< \brief TC0 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TC0_WO0                  5L
+#define PINMUX_PB30F_TC0_WO0       ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)
+#define PORT_PB30F_TC0_WO0         (1ul << 30)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PB31F_TC0_WO1                 63L  /**< \brief TC0 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TC0_WO1                  5L
+#define PINMUX_PB31F_TC0_WO1       ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)
+#define PORT_PB31F_TC0_WO1         (1ul << 31)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02F_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux F */
+#define MUX_PB02F_TC6_WO0                  5L
+#define PINMUX_PB02F_TC6_WO0       ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)
+#define PORT_PB02F_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03F_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux F */
+#define MUX_PB03F_TC6_WO1                  5L
+#define PINMUX_PB03F_TC6_WO1       ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)
+#define PORT_PB03F_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PB00F_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux F */
+#define MUX_PB00F_TC7_WO0                  5L
+#define PINMUX_PB00F_TC7_WO0       ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)
+#define PORT_PB00F_TC7_WO0         (1ul <<  0)
+#define PIN_PB22F_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux F */
+#define MUX_PB22F_TC7_WO0                  5L
+#define PINMUX_PB22F_TC7_WO0       ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)
+#define PORT_PB22F_TC7_WO0         (1ul << 22)
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB01F_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux F */
+#define MUX_PB01F_TC7_WO1                  5L
+#define PINMUX_PB01F_TC7_WO1       ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)
+#define PORT_PB01F_TC7_WO1         (1ul <<  1)
+#define PIN_PB23F_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux F */
+#define MUX_PB23F_TC7_WO1                  5L
+#define PINMUX_PB23F_TC7_WO1       ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)
+#define PORT_PB23F_TC7_WO1         (1ul << 23)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20J14_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j15.h
new file mode 100644
index 0000000000..0aad5f6f0b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j15.h
@@ -0,0 +1,1022 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20J15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J15_PIO_
+#define _SAMD20J15_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PB30F_TC0_WO0                 62L  /**< \brief TC0 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TC0_WO0                  5L
+#define PINMUX_PB30F_TC0_WO0       ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)
+#define PORT_PB30F_TC0_WO0         (1ul << 30)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PB31F_TC0_WO1                 63L  /**< \brief TC0 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TC0_WO1                  5L
+#define PINMUX_PB31F_TC0_WO1       ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)
+#define PORT_PB31F_TC0_WO1         (1ul << 31)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02F_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux F */
+#define MUX_PB02F_TC6_WO0                  5L
+#define PINMUX_PB02F_TC6_WO0       ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)
+#define PORT_PB02F_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03F_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux F */
+#define MUX_PB03F_TC6_WO1                  5L
+#define PINMUX_PB03F_TC6_WO1       ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)
+#define PORT_PB03F_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PB00F_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux F */
+#define MUX_PB00F_TC7_WO0                  5L
+#define PINMUX_PB00F_TC7_WO0       ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)
+#define PORT_PB00F_TC7_WO0         (1ul <<  0)
+#define PIN_PB22F_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux F */
+#define MUX_PB22F_TC7_WO0                  5L
+#define PINMUX_PB22F_TC7_WO0       ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)
+#define PORT_PB22F_TC7_WO0         (1ul << 22)
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB01F_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux F */
+#define MUX_PB01F_TC7_WO1                  5L
+#define PINMUX_PB01F_TC7_WO1       ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)
+#define PORT_PB01F_TC7_WO1         (1ul <<  1)
+#define PIN_PB23F_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux F */
+#define MUX_PB23F_TC7_WO1                  5L
+#define PINMUX_PB23F_TC7_WO1       ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)
+#define PORT_PB23F_TC7_WO1         (1ul << 23)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20J15_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j16.h
new file mode 100644
index 0000000000..5534cd707d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j16.h
@@ -0,0 +1,1022 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20J16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J16_PIO_
+#define _SAMD20J16_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PB30F_TC0_WO0                 62L  /**< \brief TC0 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TC0_WO0                  5L
+#define PINMUX_PB30F_TC0_WO0       ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)
+#define PORT_PB30F_TC0_WO0         (1ul << 30)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PB31F_TC0_WO1                 63L  /**< \brief TC0 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TC0_WO1                  5L
+#define PINMUX_PB31F_TC0_WO1       ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)
+#define PORT_PB31F_TC0_WO1         (1ul << 31)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02F_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux F */
+#define MUX_PB02F_TC6_WO0                  5L
+#define PINMUX_PB02F_TC6_WO0       ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)
+#define PORT_PB02F_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03F_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux F */
+#define MUX_PB03F_TC6_WO1                  5L
+#define PINMUX_PB03F_TC6_WO1       ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)
+#define PORT_PB03F_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PB00F_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux F */
+#define MUX_PB00F_TC7_WO0                  5L
+#define PINMUX_PB00F_TC7_WO0       ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)
+#define PORT_PB00F_TC7_WO0         (1ul <<  0)
+#define PIN_PB22F_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux F */
+#define MUX_PB22F_TC7_WO0                  5L
+#define PINMUX_PB22F_TC7_WO0       ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)
+#define PORT_PB22F_TC7_WO0         (1ul << 22)
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB01F_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux F */
+#define MUX_PB01F_TC7_WO1                  5L
+#define PINMUX_PB01F_TC7_WO1       ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)
+#define PORT_PB01F_TC7_WO1         (1ul <<  1)
+#define PIN_PB23F_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux F */
+#define MUX_PB23F_TC7_WO1                  5L
+#define PINMUX_PB23F_TC7_WO1       ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)
+#define PORT_PB23F_TC7_WO1         (1ul << 23)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20J16_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j17.h
new file mode 100644
index 0000000000..aac517bde2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j17.h
@@ -0,0 +1,1022 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20J17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J17_PIO_
+#define _SAMD20J17_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PB30F_TC0_WO0                 62L  /**< \brief TC0 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TC0_WO0                  5L
+#define PINMUX_PB30F_TC0_WO0       ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)
+#define PORT_PB30F_TC0_WO0         (1ul << 30)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PB31F_TC0_WO1                 63L  /**< \brief TC0 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TC0_WO1                  5L
+#define PINMUX_PB31F_TC0_WO1       ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)
+#define PORT_PB31F_TC0_WO1         (1ul << 31)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02F_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux F */
+#define MUX_PB02F_TC6_WO0                  5L
+#define PINMUX_PB02F_TC6_WO0       ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)
+#define PORT_PB02F_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03F_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux F */
+#define MUX_PB03F_TC6_WO1                  5L
+#define PINMUX_PB03F_TC6_WO1       ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)
+#define PORT_PB03F_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PB00F_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux F */
+#define MUX_PB00F_TC7_WO0                  5L
+#define PINMUX_PB00F_TC7_WO0       ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)
+#define PORT_PB00F_TC7_WO0         (1ul <<  0)
+#define PIN_PB22F_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux F */
+#define MUX_PB22F_TC7_WO0                  5L
+#define PINMUX_PB22F_TC7_WO0       ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)
+#define PORT_PB22F_TC7_WO0         (1ul << 22)
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB01F_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux F */
+#define MUX_PB01F_TC7_WO1                  5L
+#define PINMUX_PB01F_TC7_WO1       ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)
+#define PORT_PB01F_TC7_WO1         (1ul <<  1)
+#define PIN_PB23F_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux F */
+#define MUX_PB23F_TC7_WO1                  5L
+#define PINMUX_PB23F_TC7_WO1       ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)
+#define PORT_PB23F_TC7_WO1         (1ul << 23)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20J17_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j18.h
new file mode 100644
index 0000000000..3c6ad2e417
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/pio/samd20j18.h
@@ -0,0 +1,1022 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD20J18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J18_PIO_
+#define _SAMD20J18_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04F_TC0_WO0                  4L  /**< \brief TC0 signal: WO0 on PA04 mux F */
+#define MUX_PA04F_TC0_WO0                  5L
+#define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
+#define PORT_PA04F_TC0_WO0         (1ul <<  4)
+#define PIN_PB30F_TC0_WO0                 62L  /**< \brief TC0 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TC0_WO0                  5L
+#define PINMUX_PB30F_TC0_WO0       ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)
+#define PORT_PB30F_TC0_WO0         (1ul << 30)
+#define PIN_PA08E_TC0_WO0                  8L  /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0                  4L
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0         (1ul <<  8)
+#define PIN_PA05F_TC0_WO1                  5L  /**< \brief TC0 signal: WO1 on PA05 mux F */
+#define MUX_PA05F_TC0_WO1                  5L
+#define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
+#define PORT_PA05F_TC0_WO1         (1ul <<  5)
+#define PIN_PB31F_TC0_WO1                 63L  /**< \brief TC0 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TC0_WO1                  5L
+#define PINMUX_PB31F_TC0_WO1       ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)
+#define PORT_PB31F_TC0_WO1         (1ul << 31)
+#define PIN_PA09E_TC0_WO1                  9L  /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1                  4L
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1         (1ul <<  9)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06F_TC1_WO0                  6L  /**< \brief TC1 signal: WO0 on PA06 mux F */
+#define MUX_PA06F_TC1_WO0                  5L
+#define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
+#define PORT_PA06F_TC1_WO0         (1ul <<  6)
+#define PIN_PA30F_TC1_WO0                 30L  /**< \brief TC1 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TC1_WO0                  5L
+#define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
+#define PORT_PA30F_TC1_WO0         (1ul << 30)
+#define PIN_PA10E_TC1_WO0                 10L  /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0                  4L
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0         (1ul << 10)
+#define PIN_PA07F_TC1_WO1                  7L  /**< \brief TC1 signal: WO1 on PA07 mux F */
+#define MUX_PA07F_TC1_WO1                  5L
+#define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
+#define PORT_PA07F_TC1_WO1         (1ul <<  7)
+#define PIN_PA31F_TC1_WO1                 31L  /**< \brief TC1 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TC1_WO1                  5L
+#define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
+#define PORT_PA31F_TC1_WO1         (1ul << 31)
+#define PIN_PA11E_TC1_WO1                 11L  /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1                  4L
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1         (1ul << 11)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA16F_TC2_WO0                 16L  /**< \brief TC2 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TC2_WO0                  5L
+#define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
+#define PORT_PA16F_TC2_WO0         (1ul << 16)
+#define PIN_PA12E_TC2_WO0                 12L  /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0                  4L
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0         (1ul << 12)
+#define PIN_PA00F_TC2_WO0                  0L  /**< \brief TC2 signal: WO0 on PA00 mux F */
+#define MUX_PA00F_TC2_WO0                  5L
+#define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
+#define PORT_PA00F_TC2_WO0         (1ul <<  0)
+#define PIN_PA17F_TC2_WO1                 17L  /**< \brief TC2 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TC2_WO1                  5L
+#define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
+#define PORT_PA17F_TC2_WO1         (1ul << 17)
+#define PIN_PA13E_TC2_WO1                 13L  /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1                  4L
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1         (1ul << 13)
+#define PIN_PA01F_TC2_WO1                  1L  /**< \brief TC2 signal: WO1 on PA01 mux F */
+#define MUX_PA01F_TC2_WO1                  5L
+#define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
+#define PORT_PA01F_TC2_WO1         (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18F_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux F */
+#define MUX_PA18F_TC3_WO0                  5L
+#define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
+#define PORT_PA18F_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19F_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux F */
+#define MUX_PA19F_TC3_WO1                  5L
+#define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
+#define PORT_PA19F_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22F_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux F */
+#define MUX_PA22F_TC4_WO0                  5L
+#define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
+#define PORT_PA22F_TC4_WO0         (1ul << 22)
+#define PIN_PB08F_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux F */
+#define MUX_PB08F_TC4_WO0                  5L
+#define PINMUX_PB08F_TC4_WO0       ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
+#define PORT_PB08F_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23F_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux F */
+#define MUX_PA23F_TC4_WO1                  5L
+#define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
+#define PORT_PA23F_TC4_WO1         (1ul << 23)
+#define PIN_PB09F_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux F */
+#define MUX_PB09F_TC4_WO1                  5L
+#define PINMUX_PB09F_TC4_WO1       ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
+#define PORT_PB09F_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24F_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TC5_WO0                  5L
+#define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
+#define PORT_PA24F_TC5_WO0         (1ul << 24)
+#define PIN_PB10F_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux F */
+#define MUX_PB10F_TC5_WO0                  5L
+#define PINMUX_PB10F_TC5_WO0       ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
+#define PORT_PB10F_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25F_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TC5_WO1                  5L
+#define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
+#define PORT_PA25F_TC5_WO1         (1ul << 25)
+#define PIN_PB11F_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux F */
+#define MUX_PB11F_TC5_WO1                  5L
+#define PINMUX_PB11F_TC5_WO1       ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
+#define PORT_PB11F_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02F_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux F */
+#define MUX_PB02F_TC6_WO0                  5L
+#define PINMUX_PB02F_TC6_WO0       ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)
+#define PORT_PB02F_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03F_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux F */
+#define MUX_PB03F_TC6_WO1                  5L
+#define PINMUX_PB03F_TC6_WO1       ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)
+#define PORT_PB03F_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PB00F_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux F */
+#define MUX_PB00F_TC7_WO0                  5L
+#define PINMUX_PB00F_TC7_WO0       ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)
+#define PORT_PB00F_TC7_WO0         (1ul <<  0)
+#define PIN_PB22F_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux F */
+#define MUX_PB22F_TC7_WO0                  5L
+#define PINMUX_PB22F_TC7_WO0       ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)
+#define PORT_PB22F_TC7_WO0         (1ul << 22)
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB01F_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux F */
+#define MUX_PB01F_TC7_WO1                  5L
+#define PINMUX_PB01F_TC7_WO1       ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)
+#define PORT_PB01F_TC7_WO1         (1ul <<  1)
+#define PIN_PB23F_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux F */
+#define MUX_PB23F_TC7_WO1                  5L
+#define PINMUX_PB23F_TC7_WO1       ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)
+#define PORT_PB23F_TC7_WO1         (1ul << 23)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+
+#endif /* _SAMD20J18_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20.h
new file mode 100644
index 0000000000..3d73b8c4ec
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20.h
@@ -0,0 +1,93 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20_
+#define _SAMD20_
+
+/**
+ * \defgroup SAMD20_definitions SAMD20 Device Definitions
+ * \brief SAMD20 CMSIS Definitions.
+ */
+
+#if defined(__SAMD20E14__) || defined(__ATSAMD20E14__)
+#include "samd20e14.h"
+#elif defined(__SAMD20E15__) || defined(__ATSAMD20E15__)
+#include "samd20e15.h"
+#elif defined(__SAMD20E16__) || defined(__ATSAMD20E16__)
+#include "samd20e16.h"
+#elif defined(__SAMD20E17__) || defined(__ATSAMD20E17__)
+#include "samd20e17.h"
+#elif defined(__SAMD20E18__) || defined(__ATSAMD20E18__)
+#include "samd20e18.h"
+#elif defined(__SAMD20G14__) || defined(__ATSAMD20G14__)
+#include "samd20g14.h"
+#elif defined(__SAMD20G15__) || defined(__ATSAMD20G15__)
+#include "samd20g15.h"
+#elif defined(__SAMD20G16__) || defined(__ATSAMD20G16__)
+#include "samd20g16.h"
+#elif defined(__SAMD20G17__) || defined(__ATSAMD20G17__)
+#include "samd20g17.h"
+#elif defined(__SAMD20G17U__) || defined(__ATSAMD20G17U__)
+#include "samd20g17u.h"
+#elif defined(__SAMD20G18__) || defined(__ATSAMD20G18__)
+#include "samd20g18.h"
+#elif defined(__SAMD20G18U__) || defined(__ATSAMD20G18U__)
+#include "samd20g18u.h"
+#elif defined(__SAMD20J14__) || defined(__ATSAMD20J14__)
+#include "samd20j14.h"
+#elif defined(__SAMD20J15__) || defined(__ATSAMD20J15__)
+#include "samd20j15.h"
+#elif defined(__SAMD20J16__) || defined(__ATSAMD20J16__)
+#include "samd20j16.h"
+#elif defined(__SAMD20J17__) || defined(__ATSAMD20J17__)
+#include "samd20j17.h"
+#elif defined(__SAMD20J18__) || defined(__ATSAMD20J18__)
+#include "samd20j18.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAMD20_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e14.h
new file mode 100644
index 0000000000..489f8b0460
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e14.h
@@ -0,0 +1,500 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20E14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E14_
+#define _SAMD20E14_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20E14_definitions SAMD20E14 definitions
+ * This file defines all structures and symbols for SAMD20E14:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20E14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E14_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20E14-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20E14 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20E14 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20E14 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20E14 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20E14 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20E14 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20E14 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20E14 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20E14 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20E14 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20E14 Serial Communication Interface 3 (SERCOM3) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20E14 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20E14 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20E14 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20E14 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20E14 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20E14 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20E14 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20E14 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20E14 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20E14 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnReserved11;
+  void* pfnReserved12;
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E14_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20E14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E14_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20E14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E14_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20E14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E14_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20E14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E14_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20e14.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20E14 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x4000UL /* 16 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     256
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x800UL /* 2 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x1000130EUL
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20E14 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20E14_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e15.h
new file mode 100644
index 0000000000..859e12c914
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e15.h
@@ -0,0 +1,500 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20E15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E15_
+#define _SAMD20E15_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20E15_definitions SAMD20E15 definitions
+ * This file defines all structures and symbols for SAMD20E15:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20E15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E15_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20E15-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20E15 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20E15 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20E15 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20E15 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20E15 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20E15 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20E15 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20E15 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20E15 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20E15 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20E15 Serial Communication Interface 3 (SERCOM3) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20E15 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20E15 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20E15 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20E15 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20E15 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20E15 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20E15 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20E15 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20E15 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20E15 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnReserved11;
+  void* pfnReserved12;
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E15_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20E15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E15_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20E15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E15_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20E15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E15_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20E15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E15_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20e15.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20E15 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x1000UL /* 4 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x1000130DUL
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20E15 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20E15_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e16.h
new file mode 100644
index 0000000000..94c5e1714b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e16.h
@@ -0,0 +1,500 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20E16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E16_
+#define _SAMD20E16_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20E16_definitions SAMD20E16 definitions
+ * This file defines all structures and symbols for SAMD20E16:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20E16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E16_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20E16-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20E16 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20E16 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20E16 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20E16 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20E16 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20E16 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20E16 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20E16 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20E16 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20E16 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20E16 Serial Communication Interface 3 (SERCOM3) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20E16 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20E16 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20E16 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20E16 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20E16 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20E16 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20E16 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20E16 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20E16 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20E16 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnReserved11;
+  void* pfnReserved12;
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E16_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20E16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E16_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20E16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E16_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20E16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E16_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20E16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E16_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20e16.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20E16 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x2000UL /* 8 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x1000130CUL
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20E16 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20E16_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e17.h
new file mode 100644
index 0000000000..263ed30de8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e17.h
@@ -0,0 +1,500 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20E17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E17_
+#define _SAMD20E17_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20E17_definitions SAMD20E17 definitions
+ * This file defines all structures and symbols for SAMD20E17:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20E17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E17_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20E17-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20E17 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20E17 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20E17 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20E17 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20E17 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20E17 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20E17 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20E17 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20E17 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20E17 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20E17 Serial Communication Interface 3 (SERCOM3) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20E17 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20E17 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20E17 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20E17 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20E17 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20E17 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20E17 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20E17 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20E17 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20E17 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnReserved11;
+  void* pfnReserved12;
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E17_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20E17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E17_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20E17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E17_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20E17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E17_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20E17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E17_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20e17.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20E17 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x4000UL /* 16 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x1000130BUL
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20E17 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20E17_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e18.h
new file mode 100644
index 0000000000..10c58da3d1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e18.h
@@ -0,0 +1,500 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20E18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20E18_
+#define _SAMD20E18_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20E18_definitions SAMD20E18 definitions
+ * This file defines all structures and symbols for SAMD20E18:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20E18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E18_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20E18-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20E18 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20E18 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20E18 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20E18 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20E18 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20E18 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20E18 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20E18 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20E18 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20E18 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20E18 Serial Communication Interface 3 (SERCOM3) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20E18 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20E18 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20E18 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20E18 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20E18 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20E18 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20E18 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20E18 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20E18 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20E18 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnReserved11;
+  void* pfnReserved12;
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E18_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20E18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E18_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20E18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E18_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20E18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E18_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20E18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20E18_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20e18.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20E18 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x8000UL /* 32 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x1000130AUL
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20E18 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20E18_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g14.h
new file mode 100644
index 0000000000..04043424b6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g14.h
@@ -0,0 +1,509 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20G14
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G14_
+#define _SAMD20G14_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20G14_definitions SAMD20G14 definitions
+ * This file defines all structures and symbols for SAMD20G14:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20G14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G14_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20G14-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20G14 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20G14 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20G14 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20G14 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20G14 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20G14 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20G14 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20G14 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20G14 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20G14 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20G14 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20G14 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20G14 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20G14 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20G14 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20G14 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20G14 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20G14 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20G14 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20G14 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20G14 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20G14 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20G14 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G14_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20G14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G14_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20G14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G14_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20G14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G14_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20G14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G14_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20g14.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20G14 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x4000UL /* 16 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     256
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x800UL /* 2 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001309UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20G14 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20G14_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g15.h
new file mode 100644
index 0000000000..795073e337
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g15.h
@@ -0,0 +1,509 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20G15
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G15_
+#define _SAMD20G15_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20G15_definitions SAMD20G15 definitions
+ * This file defines all structures and symbols for SAMD20G15:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20G15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G15_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20G15-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20G15 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20G15 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20G15 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20G15 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20G15 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20G15 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20G15 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20G15 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20G15 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20G15 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20G15 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20G15 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20G15 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20G15 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20G15 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20G15 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20G15 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20G15 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20G15 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20G15 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20G15 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20G15 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20G15 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G15_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20G15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G15_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20G15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G15_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20G15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G15_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20G15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G15_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20g15.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20G15 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x1000UL /* 4 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001308UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20G15 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20G15_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g16.h
new file mode 100644
index 0000000000..1e9a6410b1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g16.h
@@ -0,0 +1,509 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20G16
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G16_
+#define _SAMD20G16_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20G16_definitions SAMD20G16 definitions
+ * This file defines all structures and symbols for SAMD20G16:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20G16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G16_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20G16-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20G16 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20G16 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20G16 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20G16 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20G16 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20G16 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20G16 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20G16 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20G16 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20G16 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20G16 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20G16 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20G16 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20G16 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20G16 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20G16 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20G16 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20G16 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20G16 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20G16 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20G16 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20G16 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20G16 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G16_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20G16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G16_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20G16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G16_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20G16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G16_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20G16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G16_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20g16.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20G16 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x2000UL /* 8 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001307UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20G16 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20G16_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17.h
new file mode 100644
index 0000000000..2ae1b9cadd
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17.h
@@ -0,0 +1,509 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20G17
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G17_
+#define _SAMD20G17_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20G17_definitions SAMD20G17 definitions
+ * This file defines all structures and symbols for SAMD20G17:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20G17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20G17-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20G17 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20G17 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20G17 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20G17 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20G17 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20G17 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20G17 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20G17 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20G17 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20G17 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20G17 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20G17 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20G17 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20G17 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20G17 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20G17 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20G17 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20G17 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20G17 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20G17 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20G17 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20G17 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20G17 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20G17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20G17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20G17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20G17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20g17.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20G17 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x4000UL /* 16 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001306UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20G17 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20G17_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17u.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17u.h
new file mode 100644
index 0000000000..b3223c963a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17u.h
@@ -0,0 +1,509 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20G17U
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G17U_
+#define _SAMD20G17U_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20G17U_definitions SAMD20G17U definitions
+ * This file defines all structures and symbols for SAMD20G17U:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20G17U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17U_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20G17U-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20G17U Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20G17U System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20G17U Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20G17U Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20G17U External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20G17U Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20G17U Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20G17U Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20G17U Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20G17U Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20G17U Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20G17U Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20G17U Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20G17U Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20G17U Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20G17U Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20G17U Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20G17U Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20G17U Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20G17U Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20G17U Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20G17U Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20G17U Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G17U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17U_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20G17U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17U_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20G17U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17U_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20G17U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17U_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20G17U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G17U_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20g17u.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20G17U */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x4000UL /* 16 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001311UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20G17U */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20G17U_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18.h
new file mode 100644
index 0000000000..dda5bf7e6e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18.h
@@ -0,0 +1,509 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20G18
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G18_
+#define _SAMD20G18_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20G18_definitions SAMD20G18 definitions
+ * This file defines all structures and symbols for SAMD20G18:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20G18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20G18-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20G18 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20G18 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20G18 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20G18 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20G18 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20G18 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20G18 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20G18 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20G18 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20G18 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20G18 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20G18 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20G18 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20G18 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20G18 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20G18 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20G18 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20G18 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20G18 Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20G18 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20G18 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20G18 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20G18 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20G18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20G18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20G18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20G18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20g18.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20G18 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x8000UL /* 32 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001305UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20G18 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20G18_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18u.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18u.h
new file mode 100644
index 0000000000..ff9c56a560
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18u.h
@@ -0,0 +1,509 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20G18U
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD20G18U_
+#define _SAMD20G18U_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20G18U_definitions SAMD20G18U definitions
+ * This file defines all structures and symbols for SAMD20G18U:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20G18U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18U_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20G18U-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20G18U Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20G18U System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20G18U Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20G18U Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20G18U External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20G18U Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20G18U Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20G18U Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20G18U Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20G18U Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20G18U Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20G18U Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20G18U Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20G18U Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20G18U Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20G18U Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20G18U Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20G18U Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20G18U Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20G18U Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20G18U Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20G18U Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20G18U Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnReserved19;
+  void* pfnReserved20;
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G18U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18U_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20G18U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18U_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20G18U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18U_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20G18U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18U_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20G18U */
+/* ************************************************************************** */
+/** \defgroup SAMD20G18U_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20g18u.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20G18U */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x8000UL /* 32 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001310UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20G18U */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20G18U_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j14.h
new file mode 100644
index 0000000000..539c39890e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j14.h
@@ -0,0 +1,524 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20J14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J14_
+#define _SAMD20J14_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20J14_definitions SAMD20J14 definitions
+ * This file defines all structures and symbols for SAMD20J14:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20J14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J14_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20J14-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20J14 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20J14 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20J14 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20J14 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20J14 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20J14 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20J14 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20J14 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20J14 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20J14 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20J14 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20J14 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20J14 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20J14 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20J14 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20J14 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20J14 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20J14 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20J14 Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 19, /**< 19 SAMD20J14 Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 20, /**< 20 SAMD20J14 Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20J14 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20J14 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20J14 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20J14 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 19 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 20 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J14_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20J14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J14_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20J14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J14_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20J14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J14_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       8                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20J14 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J14_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20j14.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20J14 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x4000UL /* 16 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     256
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x800UL /* 2 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001304UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20J14 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20J14_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j15.h
new file mode 100644
index 0000000000..a03cc5cf23
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j15.h
@@ -0,0 +1,524 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20J15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J15_
+#define _SAMD20J15_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20J15_definitions SAMD20J15 definitions
+ * This file defines all structures and symbols for SAMD20J15:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20J15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J15_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20J15-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20J15 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20J15 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20J15 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20J15 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20J15 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20J15 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20J15 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20J15 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20J15 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20J15 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20J15 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20J15 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20J15 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20J15 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20J15 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20J15 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20J15 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20J15 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20J15 Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 19, /**< 19 SAMD20J15 Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 20, /**< 20 SAMD20J15 Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20J15 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20J15 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20J15 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20J15 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 19 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 20 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J15_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20J15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J15_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20J15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J15_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20J15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J15_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       8                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20J15 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J15_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20j15.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20J15 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x1000UL /* 4 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001303UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20J15 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20J15_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j16.h
new file mode 100644
index 0000000000..c78802e14d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j16.h
@@ -0,0 +1,524 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20J16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J16_
+#define _SAMD20J16_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20J16_definitions SAMD20J16 definitions
+ * This file defines all structures and symbols for SAMD20J16:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20J16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J16_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20J16-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20J16 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20J16 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20J16 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20J16 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20J16 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20J16 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20J16 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20J16 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20J16 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20J16 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20J16 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20J16 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20J16 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20J16 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20J16 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20J16 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20J16 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20J16 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20J16 Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 19, /**< 19 SAMD20J16 Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 20, /**< 20 SAMD20J16 Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20J16 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20J16 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20J16 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20J16 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 19 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 20 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J16_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20J16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J16_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20J16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J16_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20J16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J16_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       8                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20J16 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J16_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20j16.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20J16 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x2000UL /* 8 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001302UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20J16 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20J16_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j17.h
new file mode 100644
index 0000000000..b063819586
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j17.h
@@ -0,0 +1,524 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20J17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J17_
+#define _SAMD20J17_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20J17_definitions SAMD20J17 definitions
+ * This file defines all structures and symbols for SAMD20J17:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20J17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J17_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20J17-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20J17 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20J17 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20J17 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20J17 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20J17 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20J17 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20J17 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20J17 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20J17 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20J17 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20J17 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20J17 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20J17 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20J17 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20J17 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20J17 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20J17 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20J17 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20J17 Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 19, /**< 19 SAMD20J17 Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 20, /**< 20 SAMD20J17 Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20J17 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20J17 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20J17 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20J17 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 19 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 20 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J17_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20J17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J17_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20J17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J17_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20J17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J17_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       8                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20J17 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J17_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20j17.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20J17 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x4000UL /* 16 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001301UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20J17 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20J17_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j18.h
new file mode 100644
index 0000000000..57c7ef154d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j18.h
@@ -0,0 +1,524 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD20J18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD20J18_
+#define _SAMD20J18_
+
+/**
+ * \ingroup SAMD20_definitions
+ * \addtogroup SAMD20J18_definitions SAMD20J18 definitions
+ * This file defines all structures and symbols for SAMD20J18:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD20J18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J18_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD20J18-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD20J18 Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD20J18 System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD20J18 Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD20J18 Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD20J18 External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD20J18 Non-Volatile Memory Controller (NVMCTRL) */
+  EVSYS_IRQn               =  6, /**<  6 SAMD20J18 Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  7, /**<  7 SAMD20J18 Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             =  8, /**<  8 SAMD20J18 Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             =  9, /**<  9 SAMD20J18 Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 10, /**< 10 SAMD20J18 Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 11, /**< 11 SAMD20J18 Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 12, /**< 12 SAMD20J18 Serial Communication Interface 5 (SERCOM5) */
+  TC0_IRQn                 = 13, /**< 13 SAMD20J18 Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 14, /**< 14 SAMD20J18 Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 15, /**< 15 SAMD20J18 Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 16, /**< 16 SAMD20J18 Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 17, /**< 17 SAMD20J18 Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 18, /**< 18 SAMD20J18 Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 19, /**< 19 SAMD20J18 Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 20, /**< 20 SAMD20J18 Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 21, /**< 21 SAMD20J18 Analog Digital Converter (ADC) */
+  AC_IRQn                  = 22, /**< 22 SAMD20J18 Analog Comparators (AC) */
+  DAC_IRQn                 = 23, /**< 23 SAMD20J18 Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 24, /**< 24 SAMD20J18 Peripheral Touch Controller (PTC) */
+
+  PERIPH_COUNT_IRQn        = 25  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnReservedM12;
+  void* pfnReservedM11;
+  void* pfnReservedM10;
+  void* pfnReservedM9;
+  void* pfnReservedM8;
+  void* pfnReservedM7;
+  void* pfnReservedM6;
+  void* pfnSVC_Handler;
+  void* pfnReservedM4;
+  void* pfnReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnEVSYS_Handler;                 /*  6 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  7 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /*  8 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /*  9 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 10 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 11 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 12 Serial Communication Interface 5 */
+  void* pfnTC0_Handler;                   /* 13 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 14 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 15 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 16 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 17 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 18 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 19 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 20 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 21 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 22 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 23 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 24 Peripheral Touch Controller */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd20.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J18_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD20J18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J18_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD20J18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J18_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TC0           72 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           73 /**< \brief Basic Timer Counter 1 (TC1) */
+#define ID_TC2           74 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+
+#define ID_PERIPH_COUNT  84 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD20J18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J18_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC0                           (0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       27
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC0               ((Tc       *)0x42002000UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x42002400UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x42002800UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       8                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD20J18 */
+/* ************************************************************************** */
+/** \defgroup SAMD20J18_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd20j18.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD20J18 */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HRAMC0_SIZE           0x8000UL /* 32 kB */
+#define FLASH_ADDR            (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HRAMC0_ADDR           (0x20000000UL) /**< HRAMC0 base address */
+
+#define DSU_DID_RESETVALUE    0x10001300UL
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD20J18 */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD20J18_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/arm/startup_SAMD20.s b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/arm/startup_SAMD20.s
new file mode 100644
index 0000000000..5fd383673c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/arm/startup_SAMD20.s
@@ -0,0 +1,235 @@
+;/*****************************************************************************
+; * @file     startup_SAMD20.s
+; * @brief    CMSIS Cortex-M0+ Core Device Startup File
+; *           for the Atmel SSAMD20 Device Series
+; * @version  V1.01
+; * @date     26. March 2014
+; *
+; * @note
+; * Copyright (C) 2014 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     PM_Handler                ;  0 Power Manager
+                DCD     SYSCTRL_Handler           ;  1 System Control
+                DCD     WDT_Handler               ;  2 Watchdog Timer
+                DCD     RTC_Handler               ;  3 Real-Time Counter
+                DCD     EIC_Handler               ;  4 External Interrupt Controller
+                DCD     NVMCTRL_Handler           ;  5 Non-Volatile Memory Controller
+                DCD     EVSYS_Handler             ;  6 Event System Interface
+                DCD     SERCOM0_Handler           ;  7 Serial Communication Interface 0
+                DCD     SERCOM1_Handler           ;  8 Serial Communication Interface 1
+                DCD     SERCOM2_Handler           ;  9 Serial Communication Interface 2
+                DCD     SERCOM3_Handler           ; 10 Serial Communication Interface 3
+                DCD     SERCOM4_Handler           ; 11 Serial Communication Interface 4
+                DCD     SERCOM5_Handler           ; 12 Serial Communication Interface 5
+                DCD     TC0_Handler               ; 13 Basic Timer Counter 0
+                DCD     TC1_Handler               ; 14 Basic Timer Counter 1
+                DCD     TC2_Handler               ; 15 Basic Timer Counter 2
+                DCD     TC3_Handler               ; 16 Basic Timer Counter 3
+                DCD     TC4_Handler               ; 17 Basic Timer Counter 4
+                DCD     TC5_Handler               ; 18 Basic Timer Counter 5
+                DCD     TC6_Handler               ; 19 Basic Timer Counter 6
+                DCD     TC7_Handler               ; 20 Basic Timer Counter 7
+                DCD     ADC_Handler               ; 21 Analog Digital Converter
+                DCD     AC_Handler                ; 22 Analog Comparators
+                DCD     DAC_Handler               ; 23 Digital Analog Converter
+                DCD     PTC_Handler               ; 24 Peripheral Touch Controller
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  PM_Handler                [WEAK]
+                EXPORT  SYSCTRL_Handler           [WEAK]
+                EXPORT  WDT_Handler               [WEAK]
+                EXPORT  RTC_Handler               [WEAK]
+                EXPORT  EIC_Handler               [WEAK]
+                EXPORT  NVMCTRL_Handler           [WEAK]
+                EXPORT  EVSYS_Handler             [WEAK]
+                EXPORT  SERCOM0_Handler           [WEAK]
+                EXPORT  SERCOM1_Handler           [WEAK]
+                EXPORT  SERCOM2_Handler           [WEAK]
+                EXPORT  SERCOM3_Handler           [WEAK]
+                EXPORT  SERCOM4_Handler           [WEAK]
+                EXPORT  SERCOM5_Handler           [WEAK]
+                EXPORT  TC0_Handler               [WEAK]
+                EXPORT  TC1_Handler               [WEAK]
+                EXPORT  TC2_Handler               [WEAK]
+                EXPORT  TC3_Handler               [WEAK]
+                EXPORT  TC4_Handler               [WEAK]
+                EXPORT  TC5_Handler               [WEAK]
+                EXPORT  TC6_Handler               [WEAK]
+                EXPORT  TC7_Handler               [WEAK]
+                EXPORT  ADC_Handler               [WEAK]
+                EXPORT  AC_Handler                [WEAK]
+                EXPORT  DAC_Handler               [WEAK]
+                EXPORT  PTC_Handler               [WEAK]
+
+PM_Handler
+SYSCTRL_Handler
+WDT_Handler
+RTC_Handler
+EIC_Handler
+NVMCTRL_Handler
+EVSYS_Handler
+SERCOM0_Handler
+SERCOM1_Handler
+SERCOM2_Handler
+SERCOM3_Handler
+SERCOM4_Handler
+SERCOM5_Handler
+TC0_Handler
+TC1_Handler
+TC2_Handler
+TC3_Handler
+TC4_Handler
+TC5_Handler
+TC6_Handler
+TC7_Handler
+ADC_Handler
+AC_Handler
+DAC_Handler
+PTC_Handler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/gcc/startup_samd20.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/gcc/startup_samd20.c
new file mode 100644
index 0000000000..e2a10d926e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/gcc/startup_samd20.c
@@ -0,0 +1,249 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD20
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "samd20.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EVSYS_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SERCOM4
+void SERCOM4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_ADC
+void ADC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_DAC
+void DAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PTC
+void PTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        (void*) (&_estack),
+
+        (void*) Reset_Handler,
+        (void*) NMI_Handler,
+        (void*) HardFault_Handler,
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) SVC_Handler,
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) PendSV_Handler,
+        (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        (void*) PM_Handler,             /*  0 Power Manager */
+        (void*) SYSCTRL_Handler,        /*  1 System Control */
+        (void*) WDT_Handler,            /*  2 Watchdog Timer */
+        (void*) RTC_Handler,            /*  3 Real-Time Counter */
+        (void*) EIC_Handler,            /*  4 External Interrupt Controller */
+        (void*) NVMCTRL_Handler,        /*  5 Non-Volatile Memory Controller */
+        (void*) EVSYS_Handler,          /*  6 Event System Interface */
+        (void*) SERCOM0_Handler,        /*  7 Serial Communication Interface 0 */
+        (void*) SERCOM1_Handler,        /*  8 Serial Communication Interface 1 */
+        (void*) SERCOM2_Handler,        /*  9 Serial Communication Interface 2 */
+        (void*) SERCOM3_Handler,        /* 10 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+        (void*) SERCOM4_Handler,        /* 11 Serial Communication Interface 4 */
+#else
+        (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_SERCOM5
+        (void*) SERCOM5_Handler,        /* 12 Serial Communication Interface 5 */
+#else
+        (void*) (0UL), /* Reserved */
+#endif
+        (void*) TC0_Handler,            /* 13 Basic Timer Counter 0 */
+        (void*) TC1_Handler,            /* 14 Basic Timer Counter 1 */
+        (void*) TC2_Handler,            /* 15 Basic Timer Counter 2 */
+        (void*) TC3_Handler,            /* 16 Basic Timer Counter 3 */
+        (void*) TC4_Handler,            /* 17 Basic Timer Counter 4 */
+        (void*) TC5_Handler,            /* 18 Basic Timer Counter 5 */
+#ifdef ID_TC6
+        (void*) TC6_Handler,            /* 19 Basic Timer Counter 6 */
+#else
+        (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_TC7
+        (void*) TC7_Handler,            /* 20 Basic Timer Counter 7 */
+#else
+        (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_ADC
+        (void*) ADC_Handler,            /* 21 Analog Digital Converter */
+#else
+        (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_AC
+        (void*) AC_Handler,             /* 22 Analog Comparators */
+#else
+        (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_DAC
+        (void*) DAC_Handler,            /* 23 Digital Analog Converter */
+#else
+        (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_PTC
+        (void*) PTC_Handler             /* 24 Peripheral Touch Controller */
+#else
+        (void*) (0UL)  /* Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+        uint32_t *pSrc, *pDest;
+
+        /* Initialize the relocate segment */
+        pSrc = &_etext;
+        pDest = &_srelocate;
+
+        if (pSrc != pDest) {
+                for (; pDest < &_erelocate;) {
+                        *pDest++ = *pSrc++;
+                }
+        }
+
+        /* Clear the zero segment */
+        for (pDest = &_szero; pDest < &_ezero;) {
+                *pDest++ = 0;
+        }
+
+        /* Set the vector table base address */
+        pSrc = (uint32_t *) & _sfixed;
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+        /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+        NVMCTRL->CTRLB.bit.MANW = 1;
+
+        /* Initialize the C library */
+        __libc_init_array();
+
+        /* Branch to main function */
+        main();
+
+        /* Infinite loop */
+        while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/iar/startup_samd20.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/iar/startup_samd20.c
new file mode 100644
index 0000000000..2c66a7f83f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/iar/startup_samd20.c
@@ -0,0 +1,260 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "samd20.h"
+
+typedef void (*intfunc) (void);
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+void Dummy_Handler(void);
+void Reset_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler              ( void );
+void HardFault_Handler        ( void );
+void SVC_Handler              ( void );
+void PendSV_Handler           ( void );
+void SysTick_Handler          ( void );
+
+/* Peripherals handlers */
+void PM_Handler               ( void );
+void SYSCTRL_Handler          ( void );
+void WDT_Handler              ( void );
+void RTC_Handler              ( void );
+void EIC_Handler              ( void );
+void NVMCTRL_Handler          ( void );
+void EVSYS_Handler            ( void );
+void SERCOM0_Handler          ( void );
+void SERCOM1_Handler          ( void );
+void SERCOM2_Handler          ( void );
+void SERCOM3_Handler          ( void );
+void SERCOM4_Handler          ( void );
+void SERCOM5_Handler          ( void );
+void TC0_Handler              ( void );
+void TC1_Handler              ( void );
+void TC2_Handler              ( void );
+void TC3_Handler              ( void );
+void TC4_Handler              ( void );
+void TC5_Handler              ( void );
+void TC6_Handler              ( void );
+void TC7_Handler              ( void );
+void ADC_Handler              ( void );
+void AC_Handler               ( void );
+void DAC_Handler              ( void );
+void PTC_Handler              ( void );
+
+/* Cortex-M0+ core handlers */
+#pragma weak NMI_Handler              = Dummy_Handler
+#pragma weak HardFault_Handler        = Dummy_Handler
+#pragma weak SVC_Handler              = Dummy_Handler
+#pragma weak PendSV_Handler           = Dummy_Handler
+#pragma weak SysTick_Handler          = Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak PM_Handler               = Dummy_Handler
+#pragma weak SYSCTRL_Handler          = Dummy_Handler
+#pragma weak WDT_Handler              = Dummy_Handler
+#pragma weak RTC_Handler              = Dummy_Handler
+#pragma weak EIC_Handler              = Dummy_Handler
+#pragma weak NVMCTRL_Handler          = Dummy_Handler
+#pragma weak EVSYS_Handler            = Dummy_Handler
+#pragma weak SERCOM0_Handler          = Dummy_Handler
+#pragma weak SERCOM1_Handler          = Dummy_Handler
+#pragma weak SERCOM2_Handler          = Dummy_Handler
+#pragma weak SERCOM3_Handler          = Dummy_Handler
+#ifdef       ID_SERCOM4
+#pragma weak SERCOM4_Handler          = Dummy_Handler
+#endif
+#ifdef       ID_SERCOM5
+#pragma weak SERCOM5_Handler          = Dummy_Handler
+#endif
+#pragma weak TC0_Handler              = Dummy_Handler
+#pragma weak TC1_Handler              = Dummy_Handler
+#pragma weak TC2_Handler              = Dummy_Handler
+#pragma weak TC3_Handler              = Dummy_Handler
+#pragma weak TC4_Handler              = Dummy_Handler
+#pragma weak TC5_Handler              = Dummy_Handler
+#ifdef       ID_TC6
+#pragma weak TC6_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_TC7
+#pragma weak TC7_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_ADC
+#pragma weak ADC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_AC
+#pragma weak AC_Handler               = Dummy_Handler
+#endif
+#ifdef       ID_DAC
+#pragma weak DAC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_PTC
+#pragma weak PTC_Handler              = Dummy_Handler
+#endif
+
+/* Exception Table */
+#pragma language = extended
+#pragma segment  = "CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section  = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+        __sfe("CSTACK"),
+        (void*) Reset_Handler,
+        (void*) NMI_Handler,
+        (void*) HardFault_Handler,
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) SVC_Handler,
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) PendSV_Handler,
+        (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        (void*) PM_Handler,             /*  0 Power Manager */
+        (void*) SYSCTRL_Handler,        /*  1 System Control */
+        (void*) WDT_Handler,            /*  2 Watchdog Timer */
+        (void*) RTC_Handler,            /*  3 Real-Time Counter */
+        (void*) EIC_Handler,            /*  4 External Interrupt Controller */
+        (void*) NVMCTRL_Handler,        /*  5 Non-Volatile Memory Controller */
+        (void*) EVSYS_Handler,          /*  6 Event System Interface */
+        (void*) SERCOM0_Handler,        /*  7 Serial Communication Interface 0 */
+        (void*) SERCOM1_Handler,        /*  8 Serial Communication Interface 1 */
+        (void*) SERCOM2_Handler,        /*  9 Serial Communication Interface 2 */
+        (void*) SERCOM3_Handler,        /* 10 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+        (void*) SERCOM4_Handler,        /* 11 Serial Communication Interface 4 */
+#else
+        (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_SERCOM5
+        (void*) SERCOM5_Handler,        /* 12 Serial Communication Interface 5 */
+#else
+        (void*) (0UL), /* Reserved*/
+#endif
+        (void*) TC0_Handler,            /* 13 Basic Timer Counter 0 */
+        (void*) TC1_Handler,            /* 14 Basic Timer Counter 1 */
+        (void*) TC2_Handler,            /* 15 Basic Timer Counter 2 */
+        (void*) TC3_Handler,            /* 16 Basic Timer Counter 3 */
+        (void*) TC4_Handler,            /* 17 Basic Timer Counter 4 */
+        (void*) TC5_Handler,            /* 18 Basic Timer Counter 5 */
+#ifdef ID_TC6
+        (void*) TC6_Handler,            /* 19 Basic Timer Counter 6 */
+#else
+        (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_TC7
+        (void*) TC7_Handler,            /* 20 Basic Timer Counter 7 */
+#else
+        (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_ADC
+        (void*) ADC_Handler,            /* 21 Analog Digital Converter */
+#else
+        (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_AC
+        (void*) AC_Handler,             /* 22 Analog Comparators */
+#else
+        (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_DAC
+        (void*) DAC_Handler,            /* 23 Digital Analog Converter */
+#else
+        (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_PTC
+        (void*) PTC_Handler             /* 24 Peripheral Touch Controller */
+#else
+        (void*) (0UL)  /* Reserved*/
+#endif
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+        uint32_t *pSrc = __section_begin(".intvec");
+
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+        return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+        /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+        NVMCTRL->CTRLB.bit.MANW = 1;
+
+        __iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.c
new file mode 100644
index 0000000000..84d7ed7628
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.c
@@ -0,0 +1,81 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "samd20.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK    (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+	// Keep the default device state after reset
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+	// Not implemented
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.h
new file mode 100644
index 0000000000..dc796aa325
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.h
@@ -0,0 +1,65 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SYSTEM_SAMD20_H_INCLUDED_
+#define _SYSTEM_SAMD20_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;   /*!< System Clock Frequency (Core Clock)  */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMD20_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/ac.h
new file mode 100644
index 0000000000..9ede7e095e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/ac.h
@@ -0,0 +1,559 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_COMPONENT_
+#define _SAMD21_AC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2205
+#define REV_AC                      0x112
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  LPMUX:1;          /*!< bit:      7  Low-Power Mux                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE         0x00ul       /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST              (0x1ul << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE             (0x1ul << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_RUNSTDBY_Pos       2            /**< \brief (AC_CTRLA) Run in Standby */
+#define AC_CTRLA_RUNSTDBY_Msk       (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY(value)    (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
+#define AC_CTRLA_LPMUX_Pos          7            /**< \brief (AC_CTRLA) Low-Power Mux */
+#define AC_CTRLA_LPMUX              (0x1ul << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK               0x87ul       /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START0:1;         /*!< bit:      0  Comparator 0 Start Comparison      */
+    uint8_t  START1:1;         /*!< bit:      1  Comparator 1 Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  START:2;          /*!< bit:  0.. 1  Comparator x Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE         0x00ul       /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0             (1 << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1             (1 << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk          (0x3ul << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value)       (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK               0x03ul       /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMPEO0:1;        /*!< bit:      0  Comparator 0 Event Output Enable   */
+    uint16_t COMPEO1:1;        /*!< bit:      1  Comparator 1 Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO0:1;         /*!< bit:      4  Window 0 Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI0:1;        /*!< bit:      8  Comparator 0 Event Input           */
+    uint16_t COMPEI1:1;        /*!< bit:      9  Comparator 1 Event Input           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t COMPEO:2;         /*!< bit:  0.. 1  Comparator x Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO:1;          /*!< bit:      4  Window x Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI:2;         /*!< bit:  8.. 9  Comparator x Event Input           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0           (1 << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1           (1 << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk        (0x3ul << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value)     (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0            (1 << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk         (0x1ul << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value)      (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
+#define AC_EVCTRL_COMPEI0           (1 << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
+#define AC_EVCTRL_COMPEI1           (1 << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input */
+#define AC_EVCTRL_COMPEI_Msk        (0x3ul << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value)     (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_MASK              0x0313ul     /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0           (1 << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1           (1 << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk        (0x3ul << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value)     (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0            (1 << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk         (0x1ul << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value)      (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK            0x13ul       /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE      0x00ul       /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0           (1 << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1           (1 << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk        (0x3ul << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value)     (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0            (1 << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk         (0x1ul << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value)      (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK            0x13ul       /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
+    __I uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN0:1;           /*!< bit:      4  Window 0                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN:1;            /*!< bit:      4  Window x                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0            (1 << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1            (1 << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk         (0x3ul << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value)      (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0             (1 << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk          (0x1ul << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value)       (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK             0x13ul       /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/   8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET           0x08         /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE       0x00ul       /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0           (1 << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1           (1 << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk        (0x3ul << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value)     (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk      (0x3ul << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value)   (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define   AC_STATUSA_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSA) Signal is above window */
+#define   AC_STATUSA_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSA) Signal is inside window */
+#define   AC_STATUSA_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK             0x33ul       /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY0:1;         /*!< bit:      0  Comparator 0 Ready                 */
+    uint8_t  READY1:1;         /*!< bit:      1  Comparator 1 Ready                 */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  READY:2;          /*!< bit:  0.. 1  Comparator x Ready                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET           0x09         /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE       0x00ul       /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0           (1 << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1           (1 << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk        (0x3ul << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value)     (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_SYNCBUSY_Pos     7            /**< \brief (AC_STATUSB) Synchronization Busy */
+#define AC_STATUSB_SYNCBUSY         (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK             0x83ul       /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/   8) Status C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSC_OFFSET           0x0A         /**< \brief (AC_STATUSC offset) Status C */
+#define AC_STATUSC_RESETVALUE       0x00ul       /**< \brief (AC_STATUSC reset_value) Status C */
+
+#define AC_STATUSC_STATE0_Pos       0            /**< \brief (AC_STATUSC) Comparator 0 Current State */
+#define AC_STATUSC_STATE0           (1 << AC_STATUSC_STATE0_Pos)
+#define AC_STATUSC_STATE1_Pos       1            /**< \brief (AC_STATUSC) Comparator 1 Current State */
+#define AC_STATUSC_STATE1           (1 << AC_STATUSC_STATE1_Pos)
+#define AC_STATUSC_STATE_Pos        0            /**< \brief (AC_STATUSC) Comparator x Current State */
+#define AC_STATUSC_STATE_Msk        (0x3ul << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE(value)     (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
+#define AC_STATUSC_WSTATE0_Pos      4            /**< \brief (AC_STATUSC) Window 0 Current State */
+#define AC_STATUSC_WSTATE0_Msk      (0x3ul << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0(value)   (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
+#define   AC_STATUSC_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSC) Signal is above window */
+#define   AC_STATUSC_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSC) Signal is inside window */
+#define   AC_STATUSC_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSC) Signal is below window */
+#define AC_STATUSC_WSTATE0_ABOVE    (AC_STATUSC_WSTATE0_ABOVE_Val  << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_INSIDE   (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_BELOW    (AC_STATUSC_WSTATE0_BELOW_Val  << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_MASK             0x33ul       /**< \brief (AC_STATUSC) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W  8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WEN0:1;           /*!< bit:      0  Window 0 Mode Enable               */
+    uint8_t  WINTSEL0:2;       /*!< bit:  1.. 2  Window 0 Interrupt Selection       */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET           0x0C         /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE       0x00ul       /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0             (0x1ul << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk     (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value)  (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   0x0ul  /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  0x1ul  /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define   AC_WINCTRL_WINTSEL0_BELOW_Val   0x2ul  /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul  /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK             0x07ul       /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ENABLE:1;         /*!< bit:      0  Enable                             */
+    uint32_t SINGLE:1;         /*!< bit:      1  Single-Shot Mode                   */
+    uint32_t SPEED:2;          /*!< bit:  2.. 3  Speed Selection                    */
+    uint32_t :1;               /*!< bit:      4  Reserved                           */
+    uint32_t INTSEL:2;         /*!< bit:  5.. 6  Interrupt Selection                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MUXNEG:3;         /*!< bit:  8..10  Negative Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t MUXPOS:2;         /*!< bit: 12..13  Positive Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     14  Reserved                           */
+    uint32_t SWAP:1;           /*!< bit:     15  Swap Inputs and Invert             */
+    uint32_t OUT:2;            /*!< bit: 16..17  Output                             */
+    uint32_t :1;               /*!< bit:     18  Reserved                           */
+    uint32_t HYST:1;           /*!< bit:     19  Hysteresis Enable                  */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t FLEN:3;           /*!< bit: 24..26  Filter Length                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE      0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos      0            /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE          (0x1ul << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos      1            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE          (0x1ul << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SPEED_Pos       2            /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk       (0x3ul << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value)    (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define   AC_COMPCTRL_SPEED_LOW_Val       0x0ul  /**< \brief (AC_COMPCTRL) Low speed */
+#define   AC_COMPCTRL_SPEED_HIGH_Val      0x1ul  /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW       (AC_COMPCTRL_SPEED_LOW_Val     << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_INTSEL_Pos      5            /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk      (0x3ul << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value)   (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   0x0ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define   AC_COMPCTRL_INTSEL_RISING_Val   0x1ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define   AC_COMPCTRL_INTSEL_FALLING_Val  0x2ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define   AC_COMPCTRL_INTSEL_EOC_Val      0x3ul  /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk      (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value)   (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define   AC_COMPCTRL_MUXNEG_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXNEG_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXNEG_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXNEG_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXNEG_GND_Val      0x4ul  /**< \brief (AC_COMPCTRL) Ground */
+#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   0x5ul  /**< \brief (AC_COMPCTRL) VDD scaler */
+#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  0x6ul  /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define   AC_COMPCTRL_MUXNEG_DAC_Val      0x7ul  /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3     (AC_COMPCTRL_MUXNEG_PIN3_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND      (AC_COMPCTRL_MUXNEG_GND_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE   (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk      (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value)   (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define   AC_COMPCTRL_MUXPOS_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXPOS_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXPOS_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXPOS_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP            (0x1ul << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_OUT_Pos         16           /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk         (0x3ul << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value)      (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define   AC_COMPCTRL_OUT_OFF_Val         0x0ul  /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_ASYNC_Val       0x1ul  /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_SYNC_Val        0x2ul  /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_HYST_Pos        19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYST            (0x1ul << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk        (0x7ul << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value)     (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define   AC_COMPCTRL_FLEN_OFF_Val        0x0ul  /**< \brief (AC_COMPCTRL) No filtering */
+#define   AC_COMPCTRL_FLEN_MAJ3_Val       0x1ul  /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define   AC_COMPCTRL_FLEN_MAJ5_Val       0x2ul  /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_MASK            0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W  8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:6;          /*!< bit:  0.. 5  Scaler Value                       */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET            0x20         /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE        0x00ul       /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk         (0x3Ful << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value)      (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK              0x3Ful       /**< \brief (AC_SCALER) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO AC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __O  AC_CTRLB_Type             CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B */
+  __IO AC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x02 (R/W 16) Event Control */
+  __IO AC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO AC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO AC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __I  AC_STATUSA_Type           STATUSA;     /**< \brief Offset: 0x08 (R/   8) Status A */
+  __I  AC_STATUSB_Type           STATUSB;     /**< \brief Offset: 0x09 (R/   8) Status B */
+  __I  AC_STATUSC_Type           STATUSC;     /**< \brief Offset: 0x0A (R/   8) Status C */
+       RoReg8                    Reserved2[0x1];
+  __IO AC_WINCTRL_Type           WINCTRL;     /**< \brief Offset: 0x0C (R/W  8) Window Control */
+       RoReg8                    Reserved3[0x3];
+  __IO AC_COMPCTRL_Type          COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+       RoReg8                    Reserved4[0x8];
+  __IO AC_SCALER_Type            SCALER[2];   /**< \brief Offset: 0x20 (R/W  8) Scaler n */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_AC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/adc.h
new file mode 100644
index 0000000000..918051e1cb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/adc.h
@@ -0,0 +1,699 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_COMPONENT_
+#define _SAMD21_ADC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2204
+#define REV_ADC                     0x120
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE        0x00ul       /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST             (0x1ul << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE            (0x1ul << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY          (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK              0x07ul       /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W  8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  REFSEL:4;         /*!< bit:  0.. 3  Reference Selection                */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  REFCOMP:1;        /*!< bit:      7  Reference Buffer Offset Compensation Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET          0x01         /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk      (0xFul << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define   ADC_REFCTRL_REFSEL_INT1V_Val    0x0ul  /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  0x1ul  /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  0x2ul  /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define   ADC_REFCTRL_REFSEL_AREFA_Val    0x3ul  /**< \brief (ADC_REFCTRL) External reference */
+#define   ADC_REFCTRL_REFSEL_AREFB_Val    0x4ul  /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_INT1V    (ADC_REFCTRL_REFSEL_INT1V_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP         (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK            0x8Ful       /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W  8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLENUM:4;      /*!< bit:  0.. 3  Number of Samples to be Collected  */
+    uint8_t  ADJRES:3;         /*!< bit:  4.. 6  Adjusting Result / Division Coefficient */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET          0x02         /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk   (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define   ADC_AVGCTRL_SAMPLENUM_1_Val     0x0ul  /**< \brief (ADC_AVGCTRL) 1 sample */
+#define   ADC_AVGCTRL_SAMPLENUM_2_Val     0x1ul  /**< \brief (ADC_AVGCTRL) 2 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_4_Val     0x2ul  /**< \brief (ADC_AVGCTRL) 4 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_8_Val     0x3ul  /**< \brief (ADC_AVGCTRL) 8 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_16_Val    0x4ul  /**< \brief (ADC_AVGCTRL) 16 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_32_Val    0x5ul  /**< \brief (ADC_AVGCTRL) 32 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_64_Val    0x6ul  /**< \brief (ADC_AVGCTRL) 64 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_128_Val   0x7ul  /**< \brief (ADC_AVGCTRL) 128 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_256_Val   0x8ul  /**< \brief (ADC_AVGCTRL) 256 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_512_Val   0x9ul  /**< \brief (ADC_AVGCTRL) 512 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  0xAul  /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk      (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK            0x7Ful       /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W  8) Sampling Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLEN:6;        /*!< bit:  0.. 5  Sampling Time Length               */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET         0x03         /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE     0x00ul       /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk    (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_MASK           0x3Ful       /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DIFFMODE:1;       /*!< bit:      0  Differential Mode                  */
+    uint16_t LEFTADJ:1;        /*!< bit:      1  Left-Adjusted Result               */
+    uint16_t FREERUN:1;        /*!< bit:      2  Free Running Mode                  */
+    uint16_t CORREN:1;         /*!< bit:      3  Digital Correction Logic Enabled   */
+    uint16_t RESSEL:2;         /*!< bit:  4.. 5  Conversion Result Resolution       */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler Configuration            */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET            0x04         /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE        0x0000ul     /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_DIFFMODE_Pos      0            /**< \brief (ADC_CTRLB) Differential Mode */
+#define ADC_CTRLB_DIFFMODE          (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_LEFTADJ_Pos       1            /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ           (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos       2            /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN           (0x1ul << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos        3            /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
+#define ADC_CTRLB_CORREN            (0x1ul << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos        4            /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk        (0x3ul << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value)     (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
+#define   ADC_CTRLB_RESSEL_12BIT_Val      0x0ul  /**< \brief (ADC_CTRLB) 12-bit result */
+#define   ADC_CTRLB_RESSEL_16BIT_Val      0x1ul  /**< \brief (ADC_CTRLB) For averaging mode output */
+#define   ADC_CTRLB_RESSEL_10BIT_Val      0x2ul  /**< \brief (ADC_CTRLB) 10-bit result */
+#define   ADC_CTRLB_RESSEL_8BIT_Val       0x3ul  /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_PRESCALER_Pos     8            /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk     (0x7ul << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value)  (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
+#define   ADC_CTRLB_PRESCALER_DIV4_Val    0x0ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define   ADC_CTRLB_PRESCALER_DIV8_Val    0x1ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define   ADC_CTRLB_PRESCALER_DIV16_Val   0x2ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define   ADC_CTRLB_PRESCALER_DIV32_Val   0x3ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define   ADC_CTRLB_PRESCALER_DIV64_Val   0x4ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define   ADC_CTRLB_PRESCALER_DIV128_Val  0x5ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define   ADC_CTRLB_PRESCALER_DIV256_Val  0x6ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define   ADC_CTRLB_PRESCALER_DIV512_Val  0x7ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define ADC_CTRLB_PRESCALER_DIV4    (ADC_CTRLB_PRESCALER_DIV4_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8    (ADC_CTRLB_PRESCALER_DIV8_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16   (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32   (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64   (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128  (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256  (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV512  (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK              0x073Ful     /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W  8) Window Monitor Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WINMODE:3;        /*!< bit:  0.. 2  Window Monitor Mode                */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINCTRL_OFFSET          0x08         /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+
+#define ADC_WINCTRL_WINMODE_Pos     0            /**< \brief (ADC_WINCTRL) Window Monitor Mode */
+#define ADC_WINCTRL_WINMODE_Msk     (0x7ul << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE(value)  (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
+#define   ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul  /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define   ADC_WINCTRL_WINMODE_MODE1_Val   0x1ul  /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define   ADC_WINCTRL_WINMODE_MODE2_Val   0x2ul  /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE3_Val   0x3ul  /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE4_Val   0x4ul  /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE1   (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE2   (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE3   (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE4   (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_MASK            0x07ul       /**< \brief (ADC_WINCTRL) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W  8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLUSH:1;          /*!< bit:      0  ADC Conversion Flush               */
+    uint8_t  START:1;          /*!< bit:      1  ADC Start Conversion               */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET           0x0C         /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE       0x00ul       /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH            (0x1ul << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) ADC Start Conversion */
+#define ADC_SWTRIG_START            (0x1ul << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK             0x03ul       /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUXPOS:5;         /*!< bit:  0.. 4  Positive Mux Input Selection       */
+    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint32_t MUXNEG:5;         /*!< bit:  8..12  Negative Mux Input Selection       */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t INPUTSCAN:4;      /*!< bit: 16..19  Number of Input Channels Included in Scan */
+    uint32_t INPUTOFFSET:4;    /*!< bit: 20..23  Positive Mux Setting Offset        */
+    uint32_t GAIN:4;           /*!< bit: 24..27  Gain Factor Selection              */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET        0x10         /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE    0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk    (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define   ADC_INPUTCTRL_MUXPOS_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN8_Val   0x8ul  /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN9_Val   0x9ul  /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN10_Val  0xAul  /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN11_Val  0xBul  /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN12_Val  0xCul  /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN13_Val  0xDul  /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN14_Val  0xEul  /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN15_Val  0xFul  /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN16_Val  0x10ul  /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN17_Val  0x11ul  /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN18_Val  0x12ul  /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN19_Val  0x13ul  /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_TEMP_Val   0x18ul  /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul  /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled Core Supply */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled I/O Supply */
+#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    0x1Cul  /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PIN0   (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN1   (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN2   (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN3   (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN4   (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN5   (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN6   (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN7   (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN8   (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN9   (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN10  (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN11  (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN12  (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN13  (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN14  (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN15  (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN16  (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN17  (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN18  (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN19  (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP   (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk    (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define   ADC_INPUTCTRL_MUXNEG_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_GND_Val    0x18ul  /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define   ADC_INPUTCTRL_MUXNEG_IOGND_Val  0x19ul  /**< \brief (ADC_INPUTCTRL) I/O Ground */
+#define ADC_INPUTCTRL_MUXNEG_PIN0   (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN1   (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN2   (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN3   (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN4   (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN5   (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN6   (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN7   (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_IOGND  (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16           /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20           /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
+#define ADC_INPUTCTRL_GAIN_Pos      24           /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
+#define ADC_INPUTCTRL_GAIN_Msk      (0xFul << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN(value)   (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
+#define   ADC_INPUTCTRL_GAIN_1X_Val       0x0ul  /**< \brief (ADC_INPUTCTRL) 1x */
+#define   ADC_INPUTCTRL_GAIN_2X_Val       0x1ul  /**< \brief (ADC_INPUTCTRL) 2x */
+#define   ADC_INPUTCTRL_GAIN_4X_Val       0x2ul  /**< \brief (ADC_INPUTCTRL) 4x */
+#define   ADC_INPUTCTRL_GAIN_8X_Val       0x3ul  /**< \brief (ADC_INPUTCTRL) 8x */
+#define   ADC_INPUTCTRL_GAIN_16X_Val      0x4ul  /**< \brief (ADC_INPUTCTRL) 16x */
+#define   ADC_INPUTCTRL_GAIN_DIV2_Val     0xFul  /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define ADC_INPUTCTRL_GAIN_1X       (ADC_INPUTCTRL_GAIN_1X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_2X       (ADC_INPUTCTRL_GAIN_2X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_4X       (ADC_INPUTCTRL_GAIN_4X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_8X       (ADC_INPUTCTRL_GAIN_8X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_16X      (ADC_INPUTCTRL_GAIN_16X_Val    << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_DIV2     (ADC_INPUTCTRL_GAIN_DIV2_Val   << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_MASK          0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event In          */
+    uint8_t  SYNCEI:1;         /*!< bit:      1  Synchronization Event In           */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  RESRDYEO:1;       /*!< bit:      4  Result Ready Event Out             */
+    uint8_t  WINMONEO:1;       /*!< bit:      5  Window Monitor Event Out           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET           0x14         /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_STARTEI_Pos      0            /**< \brief (ADC_EVCTRL) Start Conversion Event In */
+#define ADC_EVCTRL_STARTEI          (0x1ul << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_SYNCEI_Pos       1            /**< \brief (ADC_EVCTRL) Synchronization Event In */
+#define ADC_EVCTRL_SYNCEI           (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO         (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO         (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK             0x33ul       /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET         0x16         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
+#define ADC_INTENCLR_RESRDY         (0x1ul << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
+#define ADC_INTENCLR_OVERRUN        (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
+#define ADC_INTENCLR_WINMON         (0x1ul << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_SYNCRDY_Pos    3            /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define ADC_INTENCLR_SYNCRDY        (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK           0x0Ful       /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET         0x17         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE     0x00ul       /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY         (0x1ul << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN        (0x1ul << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON         (0x1ul << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_SYNCRDY_Pos    3            /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
+#define ADC_INTENSET_SYNCRDY        (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK           0x0Ful       /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready                       */
+    __I uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun                            */
+    __I uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor                     */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
+    __I uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET          0x18         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready */
+#define ADC_INTFLAG_RESRDY          (0x1ul << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun */
+#define ADC_INTFLAG_OVERRUN         (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor */
+#define ADC_INTFLAG_WINMON          (0x1ul << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_SYNCRDY_Pos     3            /**< \brief (ADC_INTFLAG) Synchronization Ready */
+#define ADC_INTFLAG_SYNCRDY         (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK            0x0Ful       /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET           0x19         /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE       0x00ul       /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_SYNCBUSY_Pos     7            /**< \brief (ADC_STATUS) Synchronization Busy */
+#define ADC_STATUS_SYNCBUSY         (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK             0x80ul       /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/  16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESULT:16;        /*!< bit:  0..15  Result Conversion Value            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET           0x1A         /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE       0x0000ul     /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk       (0xFFFFul << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK             0xFFFFul     /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINLT:16;         /*!< bit:  0..15  Window Lower Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET            0x1C         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk         (0xFFFFul << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK              0xFFFFul     /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINUT:16;         /*!< bit:  0..15  Window Upper Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET            0x20         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk         (0xFFFFul << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK              0xFFFFul     /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GAINCORR:12;      /*!< bit:  0..11  Gain Correction Value              */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET         0x24         /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE     0x0000ul     /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk   (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK           0x0FFFul     /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t OFFSETCORR:12;    /*!< bit:  0..11  Offset Correction Value            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET       0x26         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE   0x0000ul     /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK         0x0FFFul     /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LINEARITY_CAL:8;  /*!< bit:  0.. 7  Linearity Calibration Value        */
+    uint16_t BIAS_CAL:3;       /*!< bit:  8..10  Bias Calibration Value             */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET            0x28         /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE        0x0000ul     /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_LINEARITY_CAL_Pos 0            /**< \brief (ADC_CALIB) Linearity Calibration Value */
+#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
+#define ADC_CALIB_BIAS_CAL_Pos      8            /**< \brief (ADC_CALIB) Bias Calibration Value */
+#define ADC_CALIB_BIAS_CAL_Msk      (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL(value)   (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
+#define ADC_CALIB_MASK              0x07FFul     /**< \brief (ADC_CALIB) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET          0x2A         /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN          (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK            0x01ul       /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO ADC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO ADC_REFCTRL_Type          REFCTRL;     /**< \brief Offset: 0x01 (R/W  8) Reference Control */
+  __IO ADC_AVGCTRL_Type          AVGCTRL;     /**< \brief Offset: 0x02 (R/W  8) Average Control */
+  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    /**< \brief Offset: 0x03 (R/W  8) Sampling Time Control */
+  __IO ADC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W 16) Control B */
+       RoReg8                    Reserved1[0x2];
+  __IO ADC_WINCTRL_Type          WINCTRL;     /**< \brief Offset: 0x08 (R/W  8) Window Monitor Control */
+       RoReg8                    Reserved2[0x3];
+  __IO ADC_SWTRIG_Type           SWTRIG;      /**< \brief Offset: 0x0C (R/W  8) Software Trigger */
+       RoReg8                    Reserved3[0x3];
+  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   /**< \brief Offset: 0x10 (R/W 32) Input Control */
+  __IO ADC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x14 (R/W  8) Event Control */
+       RoReg8                    Reserved4[0x1];
+  __IO ADC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x16 (R/W  8) Interrupt Enable Clear */
+  __IO ADC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x17 (R/W  8) Interrupt Enable Set */
+  __IO ADC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) Interrupt Flag Status and Clear */
+  __I  ADC_STATUS_Type           STATUS;      /**< \brief Offset: 0x19 (R/   8) Status */
+  __I  ADC_RESULT_Type           RESULT;      /**< \brief Offset: 0x1A (R/  16) Result */
+  __IO ADC_WINLT_Type            WINLT;       /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+       RoReg8                    Reserved5[0x2];
+  __IO ADC_WINUT_Type            WINUT;       /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+       RoReg8                    Reserved6[0x2];
+  __IO ADC_GAINCORR_Type         GAINCORR;    /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+  __IO ADC_CALIB_Type            CALIB;       /**< \brief Offset: 0x28 (R/W 16) Calibration */
+  __IO ADC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x2A (R/W  8) Debug Control */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_ADC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dac.h
new file mode 100644
index 0000000000..79cfe0ce68
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dac.h
@@ -0,0 +1,286 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_COMPONENT_
+#define _SAMD21_DAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DAC Digital Analog Converter */
+/*@{*/
+
+#define DAC_U2214
+#define REV_DAC                     0x110
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET            0x0          /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST             (0x1ul << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable */
+#define DAC_CTRLA_ENABLE            (0x1ul << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (DAC_CTRLA) Run in Standby */
+#define DAC_CTRLA_RUNSTDBY          (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK              0x07ul       /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EOEN:1;           /*!< bit:      0  External Output Enable             */
+    uint8_t  IOEN:1;           /*!< bit:      1  Internal Output Enable             */
+    uint8_t  LEFTADJ:1;        /*!< bit:      2  Left Adjusted Data                 */
+    uint8_t  VPD:1;            /*!< bit:      3  Voltage Pump Disable               */
+    uint8_t  BDWP:1;           /*!< bit:      4  Bypass DATABUF Write Protection    */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  REFSEL:2;         /*!< bit:  6.. 7  Reference Selection                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET            0x1          /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_EOEN_Pos          0            /**< \brief (DAC_CTRLB) External Output Enable */
+#define DAC_CTRLB_EOEN              (0x1ul << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_IOEN_Pos          1            /**< \brief (DAC_CTRLB) Internal Output Enable */
+#define DAC_CTRLB_IOEN              (0x1ul << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_LEFTADJ_Pos       2            /**< \brief (DAC_CTRLB) Left Adjusted Data */
+#define DAC_CTRLB_LEFTADJ           (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_VPD_Pos           3            /**< \brief (DAC_CTRLB) Voltage Pump Disable */
+#define DAC_CTRLB_VPD               (0x1ul << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_BDWP_Pos          4            /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
+#define DAC_CTRLB_BDWP              (0x1ul << DAC_CTRLB_BDWP_Pos)
+#define DAC_CTRLB_REFSEL_Pos        6            /**< \brief (DAC_CTRLB) Reference Selection */
+#define DAC_CTRLB_REFSEL_Msk        (0x3ul << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value)     (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define   DAC_CTRLB_REFSEL_INT1V_Val      0x0ul  /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define   DAC_CTRLB_REFSEL_AVCC_Val       0x1ul  /**< \brief (DAC_CTRLB) AVCC */
+#define   DAC_CTRLB_REFSEL_VREFP_Val      0x2ul  /**< \brief (DAC_CTRLB) External reference */
+#define DAC_CTRLB_REFSEL_INT1V      (DAC_CTRLB_REFSEL_INT1V_Val    << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_AVCC       (DAC_CTRLB_REFSEL_AVCC_Val     << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFP      (DAC_CTRLB_REFSEL_VREFP_Val    << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK              0xDFul       /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event Input       */
+    uint8_t  EMPTYEO:1;        /*!< bit:      1  Data Buffer Empty Event Output     */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET           0x2          /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
+#define DAC_EVCTRL_STARTEI          (0x1ul << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos      1            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
+#define DAC_EVCTRL_EMPTYEO          (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK             0x03ul       /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET         0x4          /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN       (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_EMPTY_Pos      1            /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY          (0x1ul << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_SYNCRDY_Pos    2            /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define DAC_INTENCLR_SYNCRDY        (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK           0x07ul       /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET         0x5          /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE     0x00ul       /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN       (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_EMPTY_Pos      1            /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY          (0x1ul << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_SYNCRDY_Pos    2            /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
+#define DAC_INTENSET_SYNCRDY        (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK           0x07ul       /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun                           */
+    __I uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty                  */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready              */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET          0x6          /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) Underrun */
+#define DAC_INTFLAG_UNDERRUN        (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_EMPTY_Pos       1            /**< \brief (DAC_INTFLAG) Data Buffer Empty */
+#define DAC_INTFLAG_EMPTY           (0x1ul << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_SYNCRDY_Pos     2            /**< \brief (DAC_INTFLAG) Synchronization Ready */
+#define DAC_INTFLAG_SYNCRDY         (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK            0x07ul       /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET           0x7          /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE       0x00ul       /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_SYNCBUSY_Pos     7            /**< \brief (DAC_STATUS) Synchronization Busy Status */
+#define DAC_STATUS_SYNCBUSY         (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK             0x80ul       /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:16;          /*!< bit:  0..15  Data value to be converted         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET             0x8          /**< \brief (DAC_DATA offset) Data */
+#define DAC_DATA_RESETVALUE         0x0000ul     /**< \brief (DAC_DATA reset_value) Data */
+
+#define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) Data value to be converted */
+#define DAC_DATA_DATA_Msk           (0xFFFFul << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value)        (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK               0xFFFFul     /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATABUF:16;       /*!< bit:  0..15  Data Buffer                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET          0xC          /**< \brief (DAC_DATABUF offset) Data Buffer */
+#define DAC_DATABUF_RESETVALUE      0x0000ul     /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk     (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value)  (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK            0xFFFFul     /**< \brief (DAC_DATABUF) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DAC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x0 (R/W  8) Control A */
+  __IO DAC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x1 (R/W  8) Control B */
+  __IO DAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x2 (R/W  8) Event Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO DAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO DAC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+  __I  DAC_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
+  __IO DAC_DATA_Type             DATA;        /**< \brief Offset: 0x8 (R/W 16) Data */
+       RoReg8                    Reserved2[0x2];
+  __IO DAC_DATABUF_Type          DATABUF;     /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DAC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dmac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dmac.h
new file mode 100644
index 0000000000..49430bb917
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dmac.h
@@ -0,0 +1,1087 @@
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_COMPONENT_
+#define _SAMD21_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2223
+#define REV_DMAC                    0x110
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t DMAENABLE:1;      /*!< bit:      1  DMA Enable                         */
+    uint16_t CRCENABLE:1;      /*!< bit:      2  CRC Enable                         */
+    uint16_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint16_t LVLEN0:1;         /*!< bit:      8  Priority Level 0 Enable            */
+    uint16_t LVLEN1:1;         /*!< bit:      9  Priority Level 1 Enable            */
+    uint16_t LVLEN2:1;         /*!< bit:     10  Priority Level 2 Enable            */
+    uint16_t LVLEN3:1;         /*!< bit:     11  Priority Level 3 Enable            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint16_t LVLEN:4;          /*!< bit:  8..11  Priority Level x Enable            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET            0x00         /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE        0x0000ul     /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos         0            /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST             (0x1ul << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos     1            /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE         (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_CRCENABLE_Pos     2            /**< \brief (DMAC_CTRL) CRC Enable */
+#define DMAC_CTRL_CRCENABLE         (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos        8            /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0            (1 << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos        9            /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1            (1 << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos        10           /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2            (1 << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos        11           /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3            (1 << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos         8            /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk         (0xFul << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value)      (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
+#define DMAC_CTRL_MASK              0x0F07ul     /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CRCBEATSIZE:2;    /*!< bit:  0.. 1  CRC Beat Size                      */
+    uint16_t CRCPOLY:2;        /*!< bit:  2.. 3  CRC Polynomial Type                */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t CRCSRC:6;         /*!< bit:  8..13  CRC Input Source                   */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET         0x02         /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE     0x0000ul     /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0            /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
+#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul  /**< \brief (DMAC_CRCCTRL) Byte bus access */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul  /**< \brief (DMAC_CRCCTRL) Half-word bus access */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul  /**< \brief (DMAC_CRCCTRL) Word bus access */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos    2            /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk    (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
+#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  0x0ul  /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  0x1ul  /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16  (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32  (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos     8            /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk     (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value)  (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
+#define   DMAC_CRCCTRL_CRCSRC_NOACT_Val   0x0ul  /**< \brief (DMAC_CRCCTRL) No action */
+#define   DMAC_CRCCTRL_CRCSRC_IO_Val      0x1ul  /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_NOACT   (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO      (DMAC_CRCCTRL_CRCSRC_IO_Val    << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_MASK           0x3F0Ful     /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CRCDATAIN:32;     /*!< bit:  0..31  CRC Data Input                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET       0x04         /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE   0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0            /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
+#define DMAC_CRCDATAIN_MASK         0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CRCCHKSUM:32;     /*!< bit:  0..31  CRC Checksum                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET       0x08         /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE   0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0            /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
+#define DMAC_CRCCHKSUM_MASK         0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W  8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCBUSY:1;        /*!< bit:      0  CRC Module Busy                    */
+    uint8_t  CRCZERO:1;        /*!< bit:      1  CRC Zero                           */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET       0x0C         /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE   0x00ul       /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos  0            /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY      (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos  1            /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO      (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_MASK         0x03ul       /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET         0x0D         /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE     0x00ul       /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN         (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK           0x01ul       /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W  8) QOS Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WRBQOS:2;         /*!< bit:  0.. 1  Write-Back Quality of Service      */
+    uint8_t  FQOS:2;           /*!< bit:  2.. 3  Fetch Quality of Service           */
+    uint8_t  DQOS:2;           /*!< bit:  4.. 5  Data Transfer Quality of Service   */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_QOSCTRL_OFFSET         0x0E         /**< \brief (DMAC_QOSCTRL offset) QOS Control */
+#define DMAC_QOSCTRL_RESETVALUE     0x15ul       /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
+
+#define DMAC_QOSCTRL_WRBQOS_Pos     0            /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
+#define DMAC_QOSCTRL_WRBQOS_Msk     (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS(value)  (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
+#define   DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_WRBQOS_LOW_Val     0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_WRBQOS_MEDIUM_Val  0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_WRBQOS_HIGH_Val    0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_LOW     (DMAC_QOSCTRL_WRBQOS_LOW_Val   << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM  (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_HIGH    (DMAC_QOSCTRL_WRBQOS_HIGH_Val  << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_Pos       2            /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
+#define DMAC_QOSCTRL_FQOS_Msk       (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS(value)    (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
+#define   DMAC_QOSCTRL_FQOS_DISABLE_Val   0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_FQOS_LOW_Val       0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_FQOS_MEDIUM_Val    0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_FQOS_HIGH_Val      0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_FQOS_DISABLE   (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_LOW       (DMAC_QOSCTRL_FQOS_LOW_Val     << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_MEDIUM    (DMAC_QOSCTRL_FQOS_MEDIUM_Val  << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_HIGH      (DMAC_QOSCTRL_FQOS_HIGH_Val    << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_Pos       4            /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
+#define DMAC_QOSCTRL_DQOS_Msk       (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS(value)    (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
+#define   DMAC_QOSCTRL_DQOS_DISABLE_Val   0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_DQOS_LOW_Val       0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_DQOS_MEDIUM_Val    0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_DQOS_HIGH_Val      0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_DQOS_DISABLE   (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_LOW       (DMAC_QOSCTRL_DQOS_LOW_Val     << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_MEDIUM    (DMAC_QOSCTRL_DQOS_MEDIUM_Val  << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_HIGH      (DMAC_QOSCTRL_DQOS_HIGH_Val    << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_MASK           0x3Ful       /**< \brief (DMAC_QOSCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWTRIG0:1;        /*!< bit:      0  Channel 0 Software Trigger         */
+    uint32_t SWTRIG1:1;        /*!< bit:      1  Channel 1 Software Trigger         */
+    uint32_t SWTRIG2:1;        /*!< bit:      2  Channel 2 Software Trigger         */
+    uint32_t SWTRIG3:1;        /*!< bit:      3  Channel 3 Software Trigger         */
+    uint32_t SWTRIG4:1;        /*!< bit:      4  Channel 4 Software Trigger         */
+    uint32_t SWTRIG5:1;        /*!< bit:      5  Channel 5 Software Trigger         */
+    uint32_t SWTRIG6:1;        /*!< bit:      6  Channel 6 Software Trigger         */
+    uint32_t SWTRIG7:1;        /*!< bit:      7  Channel 7 Software Trigger         */
+    uint32_t SWTRIG8:1;        /*!< bit:      8  Channel 8 Software Trigger         */
+    uint32_t SWTRIG9:1;        /*!< bit:      9  Channel 9 Software Trigger         */
+    uint32_t SWTRIG10:1;       /*!< bit:     10  Channel 10 Software Trigger        */
+    uint32_t SWTRIG11:1;       /*!< bit:     11  Channel 11 Software Trigger        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t SWTRIG:12;        /*!< bit:  0..11  Channel x Software Trigger         */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET      0x10         /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE  0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0            /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0     (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1            /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1     (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2            /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2     (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3            /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3     (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4            /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4     (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5            /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5     (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6            /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6     (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7            /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7     (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8            /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8     (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9            /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9     (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10           /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10    (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11           /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11    (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos  0            /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
+#define DMAC_SWTRIGCTRL_MASK        0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LVLPRI0:4;        /*!< bit:  0.. 3  Level 0 Channel Priority Number    */
+    uint32_t :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint32_t RRLVLEN0:1;       /*!< bit:      7  Level 0 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI1:4;        /*!< bit:  8..11  Level 1 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t RRLVLEN1:1;       /*!< bit:     15  Level 1 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI2:4;        /*!< bit: 16..19  Level 2 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 20..22  Reserved                           */
+    uint32_t RRLVLEN2:1;       /*!< bit:     23  Level 2 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI3:4;        /*!< bit: 24..27  Level 3 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 28..30  Reserved                           */
+    uint32_t RRLVLEN3:1;       /*!< bit:     31  Level 3 Round-Robin Scheduling Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET        0x14         /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE    0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos   0            /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
+#define DMAC_PRICTRL0_RRLVLEN0_Pos  7            /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0      (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos   8            /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
+#define DMAC_PRICTRL0_RRLVLEN1_Pos  15           /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1      (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos   16           /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
+#define DMAC_PRICTRL0_RRLVLEN2_Pos  23           /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2      (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos   24           /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
+#define DMAC_PRICTRL0_RRLVLEN3_Pos  31           /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3      (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK          0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:4;             /*!< bit:  0.. 3  Channel ID                         */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t TERR:1;           /*!< bit:      8  Transfer Error                     */
+    uint16_t TCMPL:1;          /*!< bit:      9  Transfer Complete                  */
+    uint16_t SUSP:1;           /*!< bit:     10  Channel Suspend                    */
+    uint16_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint16_t FERR:1;           /*!< bit:     13  Fetch Error                        */
+    uint16_t BUSY:1;           /*!< bit:     14  Busy                               */
+    uint16_t PEND:1;           /*!< bit:     15  Pending                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET         0x20         /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE     0x0000ul     /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos         0            /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk         (0xFul << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value)      (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
+#define DMAC_INTPEND_TERR_Pos       8            /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR           (0x1ul << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos      9            /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL          (0x1ul << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos       10           /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP           (0x1ul << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_FERR_Pos       13           /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR           (0x1ul << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos       14           /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY           (0x1ul << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos       15           /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND           (0x1ul << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK           0xE70Ful     /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/  32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
+    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
+    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
+    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
+    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
+    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
+    uint32_t CHINT6:1;         /*!< bit:      6  Channel 6 Pending Interrupt        */
+    uint32_t CHINT7:1;         /*!< bit:      7  Channel 7 Pending Interrupt        */
+    uint32_t CHINT8:1;         /*!< bit:      8  Channel 8 Pending Interrupt        */
+    uint32_t CHINT9:1;         /*!< bit:      9  Channel 9 Pending Interrupt        */
+    uint32_t CHINT10:1;        /*!< bit:     10  Channel 10 Pending Interrupt       */
+    uint32_t CHINT11:1;        /*!< bit:     11  Channel 11 Pending Interrupt       */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t CHINT:12;         /*!< bit:  0..11  Channel x Pending Interrupt        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET       0x24         /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE   0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos   0            /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0       (1 << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos   1            /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1       (1 << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos   2            /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2       (1 << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos   3            /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3       (1 << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos   4            /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4       (1 << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos   5            /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5       (1 << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos   6            /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6       (1 << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos   7            /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7       (1 << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos   8            /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8       (1 << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos   9            /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9       (1 << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos  10           /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10      (1 << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos  11           /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11      (1 << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos    0            /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk    (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
+#define DMAC_INTSTATUS_MASK         0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/  32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
+    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
+    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
+    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
+    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
+    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
+    uint32_t BUSYCH6:1;        /*!< bit:      6  Busy Channel 6                     */
+    uint32_t BUSYCH7:1;        /*!< bit:      7  Busy Channel 7                     */
+    uint32_t BUSYCH8:1;        /*!< bit:      8  Busy Channel 8                     */
+    uint32_t BUSYCH9:1;        /*!< bit:      9  Busy Channel 9                     */
+    uint32_t BUSYCH10:1;       /*!< bit:     10  Busy Channel 10                    */
+    uint32_t BUSYCH11:1;       /*!< bit:     11  Busy Channel 11                    */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t BUSYCH:12;        /*!< bit:  0..11  Busy Channel x                     */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET          0x28         /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE      0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos     0            /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0         (1 << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos     1            /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1         (1 << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos     2            /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2         (1 << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos     3            /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3         (1 << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos     4            /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4         (1 << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos     5            /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5         (1 << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos     6            /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6         (1 << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos     7            /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7         (1 << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos     8            /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8         (1 << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos     9            /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9         (1 << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos    10           /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10        (1 << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos    11           /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11        (1 << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos      0            /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk      (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value)   (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
+#define DMAC_BUSYCH_MASK            0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/  32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PENDCH0:1;        /*!< bit:      0  Pending Channel 0                  */
+    uint32_t PENDCH1:1;        /*!< bit:      1  Pending Channel 1                  */
+    uint32_t PENDCH2:1;        /*!< bit:      2  Pending Channel 2                  */
+    uint32_t PENDCH3:1;        /*!< bit:      3  Pending Channel 3                  */
+    uint32_t PENDCH4:1;        /*!< bit:      4  Pending Channel 4                  */
+    uint32_t PENDCH5:1;        /*!< bit:      5  Pending Channel 5                  */
+    uint32_t PENDCH6:1;        /*!< bit:      6  Pending Channel 6                  */
+    uint32_t PENDCH7:1;        /*!< bit:      7  Pending Channel 7                  */
+    uint32_t PENDCH8:1;        /*!< bit:      8  Pending Channel 8                  */
+    uint32_t PENDCH9:1;        /*!< bit:      9  Pending Channel 9                  */
+    uint32_t PENDCH10:1;       /*!< bit:     10  Pending Channel 10                 */
+    uint32_t PENDCH11:1;       /*!< bit:     11  Pending Channel 11                 */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t PENDCH:12;        /*!< bit:  0..11  Pending Channel x                  */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET          0x2C         /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE      0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos     0            /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0         (1 << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos     1            /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1         (1 << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos     2            /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2         (1 << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos     3            /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3         (1 << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos     4            /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4         (1 << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos     5            /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5         (1 << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos     6            /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6         (1 << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos     7            /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7         (1 << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos     8            /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8         (1 << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos     9            /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9         (1 << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos    10           /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10        (1 << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos    11           /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11        (1 << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH_Pos      0            /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk      (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value)   (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
+#define DMAC_PENDCH_MASK            0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/  32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LVLEX0:1;         /*!< bit:      0  Level 0 Channel Trigger Request Executing */
+    uint32_t LVLEX1:1;         /*!< bit:      1  Level 1 Channel Trigger Request Executing */
+    uint32_t LVLEX2:1;         /*!< bit:      2  Level 2 Channel Trigger Request Executing */
+    uint32_t LVLEX3:1;         /*!< bit:      3  Level 3 Channel Trigger Request Executing */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t ID:5;             /*!< bit:  8..12  Active Channel ID                  */
+    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
+    uint32_t ABUSY:1;          /*!< bit:     15  Active Channel Busy                */
+    uint32_t BTCNT:16;         /*!< bit: 16..31  Active Channel Block Transfer Count */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t LVLEX:4;          /*!< bit:  0.. 3  Level x Channel Trigger Request Executing */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET          0x30         /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE      0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos      0            /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0          (1 << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos      1            /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1          (1 << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos      2            /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2          (1 << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos      3            /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3          (1 << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos       0            /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk       (0xFul << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value)    (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
+#define DMAC_ACTIVE_ID_Pos          8            /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk          (0x1Ful << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value)       (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
+#define DMAC_ACTIVE_ABUSY_Pos       15           /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY           (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos       16           /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk       (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value)    (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
+#define DMAC_ACTIVE_MASK            0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BASEADDR:32;      /*!< bit:  0..31  Descriptor Memory Base Address     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET        0x34         /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE    0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos  0            /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk  (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
+#define DMAC_BASEADDR_MASK          0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WRBADDR:32;       /*!< bit:  0..31  Write-Back Memory Base Address     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET         0x38         /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE     0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos    0            /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk    (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
+#define DMAC_WRBADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W  8) Channel ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ID:4;             /*!< bit:  0.. 3  Channel ID                         */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHID_OFFSET            0x3F         /**< \brief (DMAC_CHID offset) Channel ID */
+#define DMAC_CHID_RESETVALUE        0x00ul       /**< \brief (DMAC_CHID reset_value) Channel ID */
+
+#define DMAC_CHID_ID_Pos            0            /**< \brief (DMAC_CHID) Channel ID */
+#define DMAC_CHID_ID_Msk            (0xFul << DMAC_CHID_ID_Pos)
+#define DMAC_CHID_ID(value)         (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
+#define DMAC_CHID_MASK              0x0Ful       /**< \brief (DMAC_CHID) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W  8) Channel Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Channel Software Reset             */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Channel Enable                     */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET         0x40         /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
+#define DMAC_CHCTRLA_RESETVALUE     0x00ul       /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos      0            /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST          (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos     1            /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE         (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_MASK           0x03ul       /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT:3;          /*!< bit:  0.. 2  Event Input Action                 */
+    uint32_t EVIE:1;           /*!< bit:      3  Channel Event Input Enable         */
+    uint32_t EVOE:1;           /*!< bit:      4  Channel Event Output Enable        */
+    uint32_t LVL:2;            /*!< bit:  5.. 6  Channel Arbitration Level          */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t TRIGSRC:6;        /*!< bit:  8..13  Peripheral Trigger Source          */
+    uint32_t :8;               /*!< bit: 14..21  Reserved                           */
+    uint32_t TRIGACT:2;        /*!< bit: 22..23  Trigger Action                     */
+    uint32_t CMD:2;            /*!< bit: 24..25  Software Command                   */
+    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET         0x44         /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
+#define DMAC_CHCTRLB_RESETVALUE     0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
+
+#define DMAC_CHCTRLB_EVACT_Pos      0            /**< \brief (DMAC_CHCTRLB) Event Input Action */
+#define DMAC_CHCTRLB_EVACT_Msk      (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT(value)   (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
+#define   DMAC_CHCTRLB_EVACT_NOACT_Val    0x0ul  /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_EVACT_TRIG_Val     0x1ul  /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
+#define   DMAC_CHCTRLB_EVACT_CTRIG_Val    0x2ul  /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
+#define   DMAC_CHCTRLB_EVACT_CBLOCK_Val   0x3ul  /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
+#define   DMAC_CHCTRLB_EVACT_SUSPEND_Val  0x4ul  /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_EVACT_RESUME_Val   0x5ul  /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define   DMAC_CHCTRLB_EVACT_SSKIP_Val    0x6ul  /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
+#define DMAC_CHCTRLB_EVACT_NOACT    (DMAC_CHCTRLB_EVACT_NOACT_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_TRIG     (DMAC_CHCTRLB_EVACT_TRIG_Val   << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CTRIG    (DMAC_CHCTRLB_EVACT_CTRIG_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CBLOCK   (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SUSPEND  (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_RESUME   (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SSKIP    (DMAC_CHCTRLB_EVACT_SSKIP_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVIE_Pos       3            /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
+#define DMAC_CHCTRLB_EVIE           (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
+#define DMAC_CHCTRLB_EVOE_Pos       4            /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
+#define DMAC_CHCTRLB_EVOE           (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
+#define DMAC_CHCTRLB_LVL_Pos        5            /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
+#define DMAC_CHCTRLB_LVL_Msk        (0x3ul << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL(value)     (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
+#define   DMAC_CHCTRLB_LVL_LVL0_Val       0x0ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
+#define   DMAC_CHCTRLB_LVL_LVL1_Val       0x1ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
+#define   DMAC_CHCTRLB_LVL_LVL2_Val       0x2ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
+#define   DMAC_CHCTRLB_LVL_LVL3_Val       0x3ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
+#define DMAC_CHCTRLB_LVL_LVL0       (DMAC_CHCTRLB_LVL_LVL0_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL1       (DMAC_CHCTRLB_LVL_LVL1_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL2       (DMAC_CHCTRLB_LVL_LVL2_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL3       (DMAC_CHCTRLB_LVL_LVL3_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_TRIGSRC_Pos    8            /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
+#define DMAC_CHCTRLB_TRIGSRC_Msk    (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
+#define   DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul  /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGACT_Pos    22           /**< \brief (DMAC_CHCTRLB) Trigger Action */
+#define DMAC_CHCTRLB_TRIGACT_Msk    (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
+#define   DMAC_CHCTRLB_TRIGACT_BLOCK_Val  0x0ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
+#define   DMAC_CHCTRLB_TRIGACT_BEAT_Val   0x2ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
+#define   DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
+#define DMAC_CHCTRLB_TRIGACT_BLOCK  (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_BEAT   (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_CMD_Pos        24           /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk        (0x3ul << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value)     (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
+#define   DMAC_CHCTRLB_CMD_NOACT_Val      0x0ul  /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    0x1ul  /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_CMD_RESUME_Val     0x2ul  /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT      (DMAC_CHCTRLB_CMD_NOACT_Val    << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND    (DMAC_CHCTRLB_CMD_SUSPEND_Val  << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME     (DMAC_CHCTRLB_CMD_RESUME_Val   << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK           0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W  8) Channel Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error Interrupt Enable    */
+    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete Interrupt Enable */
+    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET      0x4C         /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE  0x00ul       /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos    0            /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR        (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL       (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos    2            /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP        (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK        0x07ul       /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W  8) Channel Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error Interrupt Enable    */
+    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete Interrupt Enable */
+    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET      0x4D         /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE  0x00ul       /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos    0            /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR        (0x1ul << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL       (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos    2            /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP        (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK        0x07ul       /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) Channel Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TERR:1;           /*!< bit:      0  Transfer Error                     */
+    __I uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete                  */
+    __I uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend                    */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET       0x4E         /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE   0x00ul       /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos     0            /**< \brief (DMAC_CHINTFLAG) Transfer Error */
+#define DMAC_CHINTFLAG_TERR         (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos    1            /**< \brief (DMAC_CHINTFLAG) Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL        (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos     2            /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP         (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK         0x07ul       /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/   8) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PEND:1;           /*!< bit:      0  Channel Pending                    */
+    uint8_t  BUSY:1;           /*!< bit:      1  Channel Busy                       */
+    uint8_t  FERR:1;           /*!< bit:      2  Fetch Error                        */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET        0x4F         /**< \brief (DMAC_CHSTATUS offset) Channel Status */
+#define DMAC_CHSTATUS_RESETVALUE    0x00ul       /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
+
+#define DMAC_CHSTATUS_PEND_Pos      0            /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND          (0x1ul << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos      1            /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY          (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos      2            /**< \brief (DMAC_CHSTATUS) Fetch Error */
+#define DMAC_CHSTATUS_FERR          (0x1ul << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_MASK          0x07ul       /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t VALID:1;          /*!< bit:      0  Descriptor Valid                   */
+    uint16_t EVOSEL:2;         /*!< bit:  1.. 2  Event Output Selection             */
+    uint16_t BLOCKACT:2;       /*!< bit:  3.. 4  Block Action                       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t BEATSIZE:2;       /*!< bit:  8.. 9  Beat Size                          */
+    uint16_t SRCINC:1;         /*!< bit:     10  Source Address Increment Enable    */
+    uint16_t DSTINC:1;         /*!< bit:     11  Destination Address Increment Enable */
+    uint16_t STEPSEL:1;        /*!< bit:     12  Step Selection                     */
+    uint16_t STEPSIZE:3;       /*!< bit: 13..15  Address Increment Step Size        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET          0x00         /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE      0x0000ul     /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos       0            /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID           (0x1ul << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos      1            /**< \brief (DMAC_BTCTRL) Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk      (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value)   (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
+#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  0x0ul  /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    0x1ul  /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
+#define   DMAC_BTCTRL_EVOSEL_BEAT_Val     0x3ul  /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
+#define DMAC_BTCTRL_EVOSEL_DISABLE  (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK    (DMAC_BTCTRL_EVOSEL_BLOCK_Val  << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BEAT     (DMAC_BTCTRL_EVOSEL_BEAT_Val   << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos    3            /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk    (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
+#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  0x0ul  /**< \brief (DMAC_BTCTRL) No action */
+#define   DMAC_BTCTRL_BLOCKACT_INT_Val    0x1ul  /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
+#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul  /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   0x3ul  /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT  (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT    (DMAC_BTCTRL_BLOCKACT_INT_Val  << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH   (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos    8            /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk    (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
+#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   0x0ul  /**< \brief (DMAC_BTCTRL) 8-bit access */
+#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  0x1ul  /**< \brief (DMAC_BTCTRL) 16-bit access */
+#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   0x2ul  /**< \brief (DMAC_BTCTRL) 32-bit access */
+#define DMAC_BTCTRL_BEATSIZE_BYTE   (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD  (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD   (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos      10           /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC          (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos      11           /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC          (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos     12           /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL         (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
+#define   DMAC_BTCTRL_STEPSEL_DST_Val     0x0ul  /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define   DMAC_BTCTRL_STEPSEL_SRC_Val     0x1ul  /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST     (DMAC_BTCTRL_STEPSEL_DST_Val   << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC     (DMAC_BTCTRL_STEPSEL_SRC_Val   << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos    13           /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk    (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
+#define   DMAC_BTCTRL_STEPSIZE_X1_Val     0x0ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 1 */
+#define   DMAC_BTCTRL_STEPSIZE_X2_Val     0x1ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 2 */
+#define   DMAC_BTCTRL_STEPSIZE_X4_Val     0x2ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 4 */
+#define   DMAC_BTCTRL_STEPSIZE_X8_Val     0x3ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 8 */
+#define   DMAC_BTCTRL_STEPSIZE_X16_Val    0x4ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 16 */
+#define   DMAC_BTCTRL_STEPSIZE_X32_Val    0x5ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 32 */
+#define   DMAC_BTCTRL_STEPSIZE_X64_Val    0x6ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 64 */
+#define   DMAC_BTCTRL_STEPSIZE_X128_Val   0x7ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1     (DMAC_BTCTRL_STEPSIZE_X1_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2     (DMAC_BTCTRL_STEPSIZE_X2_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4     (DMAC_BTCTRL_STEPSIZE_X4_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8     (DMAC_BTCTRL_STEPSIZE_X8_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16    (DMAC_BTCTRL_STEPSIZE_X16_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32    (DMAC_BTCTRL_STEPSIZE_X32_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64    (DMAC_BTCTRL_STEPSIZE_X64_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128   (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK            0xFF1Ful     /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BTCNT:16;         /*!< bit:  0..15  Block Transfer Count               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET           0x02         /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos        0            /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk        (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value)     (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
+#define DMAC_BTCNT_MASK             0xFFFFul     /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRCADDR:32;       /*!< bit:  0..31  Transfer Source Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET         0x04         /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos    0            /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk    (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
+#define DMAC_SRCADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DSTADDR:32;       /*!< bit:  0..31  Transfer Destination Address       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET         0x08         /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */
+
+#define DMAC_DSTADDR_DSTADDR_Pos    0            /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk    (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
+#define DMAC_DSTADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DESCADDR:32;      /*!< bit:  0..31  Next Descriptor Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET        0x0C         /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos  0            /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk  (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
+#define DMAC_DESCADDR_MASK          0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_CTRL_Type            CTRL;        /**< \brief Offset: 0x00 (R/W 16) Control */
+  __IO DMAC_CRCCTRL_Type         CRCCTRL;     /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+  __IO DMAC_CRCDATAIN_Type       CRCDATAIN;   /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+  __IO DMAC_CRCCHKSUM_Type       CRCCHKSUM;   /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+  __IO DMAC_CRCSTATUS_Type       CRCSTATUS;   /**< \brief Offset: 0x0C (R/W  8) CRC Status */
+  __IO DMAC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0D (R/W  8) Debug Control */
+  __IO DMAC_QOSCTRL_Type         QOSCTRL;     /**< \brief Offset: 0x0E (R/W  8) QOS Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DMAC_SWTRIGCTRL_Type      SWTRIGCTRL;  /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+  __IO DMAC_PRICTRL0_Type        PRICTRL0;    /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+       RoReg8                    Reserved2[0x8];
+  __IO DMAC_INTPEND_Type         INTPEND;     /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+       RoReg8                    Reserved3[0x2];
+  __I  DMAC_INTSTATUS_Type       INTSTATUS;   /**< \brief Offset: 0x24 (R/  32) Interrupt Status */
+  __I  DMAC_BUSYCH_Type          BUSYCH;      /**< \brief Offset: 0x28 (R/  32) Busy Channels */
+  __I  DMAC_PENDCH_Type          PENDCH;      /**< \brief Offset: 0x2C (R/  32) Pending Channels */
+  __I  DMAC_ACTIVE_Type          ACTIVE;      /**< \brief Offset: 0x30 (R/  32) Active Channel and Levels */
+  __IO DMAC_BASEADDR_Type        BASEADDR;    /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+  __IO DMAC_WRBADDR_Type         WRBADDR;     /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+       RoReg8                    Reserved4[0x3];
+  __IO DMAC_CHID_Type            CHID;        /**< \brief Offset: 0x3F (R/W  8) Channel ID */
+  __IO DMAC_CHCTRLA_Type         CHCTRLA;     /**< \brief Offset: 0x40 (R/W  8) Channel Control A */
+       RoReg8                    Reserved5[0x3];
+  __IO DMAC_CHCTRLB_Type         CHCTRLB;     /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+       RoReg8                    Reserved6[0x4];
+  __IO DMAC_CHINTENCLR_Type      CHINTENCLR;  /**< \brief Offset: 0x4C (R/W  8) Channel Interrupt Enable Clear */
+  __IO DMAC_CHINTENSET_Type      CHINTENSET;  /**< \brief Offset: 0x4D (R/W  8) Channel Interrupt Enable Set */
+  __IO DMAC_CHINTFLAG_Type       CHINTFLAG;   /**< \brief Offset: 0x4E (R/W  8) Channel Interrupt Flag Status and Clear */
+  __I  DMAC_CHSTATUS_Type        CHSTATUS;    /**< \brief Offset: 0x4F (R/   8) Channel Status */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_BTCTRL_Type          BTCTRL;      /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+  __IO DMAC_BTCNT_Type           BTCNT;       /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+  __IO DMAC_SRCADDR_Type         SRCADDR;     /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
+  __IO DMAC_DSTADDR_Type         DSTADDR;     /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
+  __IO DMAC_DESCADDR_Type        DESCADDR;    /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+  __attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_DMAC_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAMD21_DMAC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dsu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dsu.h
new file mode 100644
index 0000000000..a65c86242b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dsu.h
@@ -0,0 +1,551 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_COMPONENT_
+#define _SAMD21_DSU_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2209
+#define REV_DSU                     0x203
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CRC:1;            /*!< bit:      2  32-bit Cyclic Redundancy Check     */
+    uint8_t  MBIST:1;          /*!< bit:      3  Memory Built-In Self-Test          */
+    uint8_t  CE:1;             /*!< bit:      4  Chip Erase                         */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE         0x00ul       /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST              (0x1ul << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
+#define DSU_CTRL_CRC                (0x1ul << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
+#define DSU_CTRL_MBIST              (0x1ul << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip Erase */
+#define DSU_CTRL_CE                 (0x1ul << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_MASK               0x1Dul       /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DONE:1;           /*!< bit:      0  Done                               */
+    uint8_t  CRSTEXT:1;        /*!< bit:      1  CPU Reset Phase Extension          */
+    uint8_t  BERR:1;           /*!< bit:      2  Bus Error                          */
+    uint8_t  FAIL:1;           /*!< bit:      3  Failure                            */
+    uint8_t  PERR:1;           /*!< bit:      4  Protection Error                   */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE      0x00ul       /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE            (0x1ul << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT         (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR            (0x1ul << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL            (0x1ul << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR            (0x1ul << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK            0x1Ful       /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PROT:1;           /*!< bit:      0  Protected                          */
+    uint8_t  DBGPRES:1;        /*!< bit:      1  Debugger Present                   */
+    uint8_t  DCCD0:1;          /*!< bit:      2  Debug Communication Channel 0 Dirty */
+    uint8_t  DCCD1:1;          /*!< bit:      3  Debug Communication Channel 1 Dirty */
+    uint8_t  HPE:1;            /*!< bit:      4  Hot-Plugging Enable                */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  DCCD:2;           /*!< bit:  2.. 3  Debug Communication Channel x Dirty */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE      0x10ul       /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT            (0x1ul << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES         (0x1ul << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0           (1 << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1           (1 << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk        (0x3ul << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value)     (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
+#define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE             (0x1ul << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK            0x1Ful       /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t ADDR:30;          /*!< bit:  2..31  Address                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE         0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk           (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value)        (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
+#define DSU_ADDR_MASK               0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t LENGTH:30;        /*!< bit:  2..31  Length                             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE       0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk       (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value)    (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
+#define DSU_LENGTH_MASK             0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE         0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk           (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value)        (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
+#define DSU_DATA_MASK               0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE          0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk            (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value)         (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
+#define DSU_DCC_MASK                0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DEVSEL:8;         /*!< bit:  0.. 7  Device Select                      */
+    uint32_t REVISION:4;       /*!< bit:  8..11  Revision                           */
+    uint32_t DIE:4;            /*!< bit: 12..15  Die Identification                 */
+    uint32_t SERIES:6;         /*!< bit: 16..21  Product Series                     */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t FAMILY:5;         /*!< bit: 23..27  Product Family                     */
+    uint32_t PROCESSOR:4;      /*!< bit: 28..31  Processor                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk          (0xFFul << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value)       (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
+#define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision */
+#define DSU_DID_REVISION_Msk        (0xFul << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value)     (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
+#define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Identification */
+#define DSU_DID_DIE_Msk             (0xFul << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value)          (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
+#define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Product Series */
+#define DSU_DID_SERIES_Msk          (0x3Ful << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value)       (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
+#define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Product Family */
+#define DSU_DID_FAMILY_Msk          (0x1Ful << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value)       (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
+#define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk       (0xFul << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value)    (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
+#define DSU_DID_MASK                0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/  32) Coresight ROM Table Entry n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EPRES:1;          /*!< bit:      0  Entry Present                      */
+    uint32_t FMT:1;            /*!< bit:      1  Format                             */
+    uint32_t :10;              /*!< bit:  2..11  Reserved                           */
+    uint32_t ADDOFF:20;        /*!< bit: 12..31  Address Offset                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ENTRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY_OFFSET            0x1000       /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
+#define DSU_ENTRY_RESETVALUE        0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
+
+#define DSU_ENTRY_EPRES_Pos         0            /**< \brief (DSU_ENTRY) Entry Present */
+#define DSU_ENTRY_EPRES             (0x1ul << DSU_ENTRY_EPRES_Pos)
+#define DSU_ENTRY_FMT_Pos           1            /**< \brief (DSU_ENTRY) Format */
+#define DSU_ENTRY_FMT               (0x1ul << DSU_ENTRY_FMT_Pos)
+#define DSU_ENTRY_ADDOFF_Pos        12           /**< \brief (DSU_ENTRY) Address Offset */
+#define DSU_ENTRY_ADDOFF_Msk        (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
+#define DSU_ENTRY_ADDOFF(value)     (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
+#define DSU_ENTRY_MASK              0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) Coresight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t END:32;           /*!< bit:  0..31  End Marker                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) Coresight ROM Table End */
+#define DSU_END_RESETVALUE          0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+
+#define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk             (0xFFFFFFFFul << DSU_END_END_Pos)
+#define DSU_END_END(value)          (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
+#define DSU_END_MASK                0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) Coresight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SMEMP:1;          /*!< bit:      0  System Memory Present              */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE      0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP           (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK            0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPCC:4;          /*!< bit:  0.. 3  JEP-106 Continuation Code          */
+    uint32_t FKBC:4;           /*!< bit:  4.. 7  4KB Count                          */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE         0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk          (0xFul << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value)       (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
+#define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB Count */
+#define DSU_PID4_FKBC_Msk           (0xFul << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value)        (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
+#define DSU_PID4_MASK               0x000000FFul /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBL:8;        /*!< bit:  0.. 7  Part Number Low                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE         0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk        (0xFFul << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value)     (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
+#define DSU_PID0_MASK               0x000000FFul /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBH:4;        /*!< bit:  0.. 3  Part Number High                   */
+    uint32_t JEPIDCL:4;        /*!< bit:  4.. 7  Low part of the JEP-106 Identity Code */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE         0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk        (0xFul << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value)     (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
+#define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk        (0xFul << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value)     (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
+#define DSU_PID1_MASK               0x000000FFul /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPIDCH:3;        /*!< bit:  0.. 2  JEP-106 Identity Code High         */
+    uint32_t JEPU:1;           /*!< bit:      3  JEP-106 Identity Code is used      */
+    uint32_t REVISION:4;       /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE         0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk        (0x7ul << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value)     (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
+#define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU               (0x1ul << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk       (0xFul << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value)    (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
+#define DSU_PID2_MASK               0x000000FFul /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CUSMOD:4;         /*!< bit:  0.. 3  ARM CUSMOD                         */
+    uint32_t REVAND:4;         /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE         0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk         (0xFul << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value)      (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
+#define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk         (0xFul << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value)      (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
+#define DSU_PID3_MASK               0x000000FFul /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB0:8;     /*!< bit:  0.. 7  Preamble Byte 0                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE         0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk     (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value)  (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
+#define DSU_CID0_MASK               0x000000FFul /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLE:4;       /*!< bit:  0.. 3  Preamble                           */
+    uint32_t CCLASS:4;         /*!< bit:  4.. 7  Component Class                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE         0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk       (0xFul << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value)    (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
+#define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk         (0xFul << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value)      (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
+#define DSU_CID1_MASK               0x000000FFul /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB2:8;     /*!< bit:  0.. 7  Preamble Byte 2                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE         0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk     (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value)  (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
+#define DSU_CID2_MASK               0x000000FFul /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB3:8;     /*!< bit:  0.. 7  Preamble Byte 3                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE         0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk     (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value)  (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
+#define DSU_CID3_MASK               0x000000FFul /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  DSU_CTRL_Type             CTRL;        /**< \brief Offset: 0x0000 ( /W  8) Control */
+  __IO DSU_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x0001 (R/W  8) Status A */
+  __I  DSU_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x0002 (R/   8) Status B */
+       RoReg8                    Reserved1[0x1];
+  __IO DSU_ADDR_Type             ADDR;        /**< \brief Offset: 0x0004 (R/W 32) Address */
+  __IO DSU_LENGTH_Type           LENGTH;      /**< \brief Offset: 0x0008 (R/W 32) Length */
+  __IO DSU_DATA_Type             DATA;        /**< \brief Offset: 0x000C (R/W 32) Data */
+  __IO DSU_DCC_Type              DCC[2];      /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+  __I  DSU_DID_Type              DID;         /**< \brief Offset: 0x0018 (R/  32) Device Identification */
+       RoReg8                    Reserved2[0xFE4];
+  __I  DSU_ENTRY_Type            ENTRY[2];    /**< \brief Offset: 0x1000 (R/  32) Coresight ROM Table Entry n */
+  __I  DSU_END_Type              END;         /**< \brief Offset: 0x1008 (R/  32) Coresight ROM Table End */
+       RoReg8                    Reserved3[0xFC0];
+  __I  DSU_MEMTYPE_Type          MEMTYPE;     /**< \brief Offset: 0x1FCC (R/  32) Coresight ROM Table Memory Type */
+  __I  DSU_PID4_Type             PID4;        /**< \brief Offset: 0x1FD0 (R/  32) Peripheral Identification 4 */
+       RoReg8                    Reserved4[0xC];
+  __I  DSU_PID0_Type             PID0;        /**< \brief Offset: 0x1FE0 (R/  32) Peripheral Identification 0 */
+  __I  DSU_PID1_Type             PID1;        /**< \brief Offset: 0x1FE4 (R/  32) Peripheral Identification 1 */
+  __I  DSU_PID2_Type             PID2;        /**< \brief Offset: 0x1FE8 (R/  32) Peripheral Identification 2 */
+  __I  DSU_PID3_Type             PID3;        /**< \brief Offset: 0x1FEC (R/  32) Peripheral Identification 3 */
+  __I  DSU_CID0_Type             CID0;        /**< \brief Offset: 0x1FF0 (R/  32) Component Identification 0 */
+  __I  DSU_CID1_Type             CID1;        /**< \brief Offset: 0x1FF4 (R/  32) Component Identification 1 */
+  __I  DSU_CID2_Type             CID2;        /**< \brief Offset: 0x1FF8 (R/  32) Component Identification 2 */
+  __I  DSU_CID3_Type             CID3;        /**< \brief Offset: 0x1FFC (R/  32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DSU_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/eic.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/eic.h
new file mode 100644
index 0000000000..5a9e85185c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/eic.h
@@ -0,0 +1,681 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_COMPONENT_
+#define _SAMD21_EIC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2217
+#define REV_EIC                     0x101
+
+/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRL_OFFSET             0x00         /**< \brief (EIC_CTRL offset) Control */
+#define EIC_CTRL_RESETVALUE         0x00ul       /**< \brief (EIC_CTRL reset_value) Control */
+
+#define EIC_CTRL_SWRST_Pos          0            /**< \brief (EIC_CTRL) Software Reset */
+#define EIC_CTRL_SWRST              (0x1ul << EIC_CTRL_SWRST_Pos)
+#define EIC_CTRL_ENABLE_Pos         1            /**< \brief (EIC_CTRL) Enable */
+#define EIC_CTRL_ENABLE             (0x1ul << EIC_CTRL_ENABLE_Pos)
+#define EIC_CTRL_MASK               0x03ul       /**< \brief (EIC_CTRL) MASK Register */
+
+/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_STATUS_OFFSET           0x01         /**< \brief (EIC_STATUS offset) Status */
+#define EIC_STATUS_RESETVALUE       0x00ul       /**< \brief (EIC_STATUS reset_value) Status */
+
+#define EIC_STATUS_SYNCBUSY_Pos     7            /**< \brief (EIC_STATUS) Synchronization Busy */
+#define EIC_STATUS_SYNCBUSY         (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
+#define EIC_STATUS_MASK             0x80ul       /**< \brief (EIC_STATUS) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W  8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMISENSE:3;       /*!< bit:  0.. 2  Non-Maskable Interrupt Sense       */
+    uint8_t  NMIFILTEN:1;      /*!< bit:      3  Non-Maskable Interrupt Filter Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET          0x02         /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE      0x00ul       /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
+#define EIC_NMICTRL_NMISENSE_Msk    (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
+#define   EIC_NMICTRL_NMISENSE_NONE_Val   0x0ul  /**< \brief (EIC_NMICTRL) No detection */
+#define   EIC_NMICTRL_NMISENSE_RISE_Val   0x1ul  /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define   EIC_NMICTRL_NMISENSE_FALL_Val   0x2ul  /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define   EIC_NMICTRL_NMISENSE_BOTH_Val   0x3ul  /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define   EIC_NMICTRL_NMISENSE_HIGH_Val   0x4ul  /**< \brief (EIC_NMICTRL) High-level detection */
+#define   EIC_NMICTRL_NMISENSE_LOW_Val    0x5ul  /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH   (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN       (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_MASK            0x0Ful       /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W  8) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMI:1;            /*!< bit:      0  Non-Maskable Interrupt             */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET          0x03         /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE      0x00ul       /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI             (0x1ul << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK            0x01ul       /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINTEO0:1;      /*!< bit:      0  External Interrupt 0 Event Output Enable */
+    uint32_t EXTINTEO1:1;      /*!< bit:      1  External Interrupt 1 Event Output Enable */
+    uint32_t EXTINTEO2:1;      /*!< bit:      2  External Interrupt 2 Event Output Enable */
+    uint32_t EXTINTEO3:1;      /*!< bit:      3  External Interrupt 3 Event Output Enable */
+    uint32_t EXTINTEO4:1;      /*!< bit:      4  External Interrupt 4 Event Output Enable */
+    uint32_t EXTINTEO5:1;      /*!< bit:      5  External Interrupt 5 Event Output Enable */
+    uint32_t EXTINTEO6:1;      /*!< bit:      6  External Interrupt 6 Event Output Enable */
+    uint32_t EXTINTEO7:1;      /*!< bit:      7  External Interrupt 7 Event Output Enable */
+    uint32_t EXTINTEO8:1;      /*!< bit:      8  External Interrupt 8 Event Output Enable */
+    uint32_t EXTINTEO9:1;      /*!< bit:      9  External Interrupt 9 Event Output Enable */
+    uint32_t EXTINTEO10:1;     /*!< bit:     10  External Interrupt 10 Event Output Enable */
+    uint32_t EXTINTEO11:1;     /*!< bit:     11  External Interrupt 11 Event Output Enable */
+    uint32_t EXTINTEO12:1;     /*!< bit:     12  External Interrupt 12 Event Output Enable */
+    uint32_t EXTINTEO13:1;     /*!< bit:     13  External Interrupt 13 Event Output Enable */
+    uint32_t EXTINTEO14:1;     /*!< bit:     14  External Interrupt 14 Event Output Enable */
+    uint32_t EXTINTEO15:1;     /*!< bit:     15  External Interrupt 15 Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINTEO:16;      /*!< bit:  0..15  External Interrupt x Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET           0x04         /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO0_Pos    0            /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO0        (1 << EIC_EVCTRL_EXTINTEO0_Pos)
+#define EIC_EVCTRL_EXTINTEO1_Pos    1            /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO1        (1 << EIC_EVCTRL_EXTINTEO1_Pos)
+#define EIC_EVCTRL_EXTINTEO2_Pos    2            /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO2        (1 << EIC_EVCTRL_EXTINTEO2_Pos)
+#define EIC_EVCTRL_EXTINTEO3_Pos    3            /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO3        (1 << EIC_EVCTRL_EXTINTEO3_Pos)
+#define EIC_EVCTRL_EXTINTEO4_Pos    4            /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO4        (1 << EIC_EVCTRL_EXTINTEO4_Pos)
+#define EIC_EVCTRL_EXTINTEO5_Pos    5            /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO5        (1 << EIC_EVCTRL_EXTINTEO5_Pos)
+#define EIC_EVCTRL_EXTINTEO6_Pos    6            /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO6        (1 << EIC_EVCTRL_EXTINTEO6_Pos)
+#define EIC_EVCTRL_EXTINTEO7_Pos    7            /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO7        (1 << EIC_EVCTRL_EXTINTEO7_Pos)
+#define EIC_EVCTRL_EXTINTEO8_Pos    8            /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO8        (1 << EIC_EVCTRL_EXTINTEO8_Pos)
+#define EIC_EVCTRL_EXTINTEO9_Pos    9            /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO9        (1 << EIC_EVCTRL_EXTINTEO9_Pos)
+#define EIC_EVCTRL_EXTINTEO10_Pos   10           /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO10       (1 << EIC_EVCTRL_EXTINTEO10_Pos)
+#define EIC_EVCTRL_EXTINTEO11_Pos   11           /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO11       (1 << EIC_EVCTRL_EXTINTEO11_Pos)
+#define EIC_EVCTRL_EXTINTEO12_Pos   12           /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO12       (1 << EIC_EVCTRL_EXTINTEO12_Pos)
+#define EIC_EVCTRL_EXTINTEO13_Pos   13           /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO13       (1 << EIC_EVCTRL_EXTINTEO13_Pos)
+#define EIC_EVCTRL_EXTINTEO14_Pos   14           /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO14       (1 << EIC_EVCTRL_EXTINTEO14_Pos)
+#define EIC_EVCTRL_EXTINTEO15_Pos   15           /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO15       (1 << EIC_EVCTRL_EXTINTEO15_Pos)
+#define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk     (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value)  (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
+#define EIC_EVCTRL_MASK             0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET         0x08         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT0_Pos    0            /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
+#define EIC_INTENCLR_EXTINT0        (1 << EIC_INTENCLR_EXTINT0_Pos)
+#define EIC_INTENCLR_EXTINT1_Pos    1            /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
+#define EIC_INTENCLR_EXTINT1        (1 << EIC_INTENCLR_EXTINT1_Pos)
+#define EIC_INTENCLR_EXTINT2_Pos    2            /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
+#define EIC_INTENCLR_EXTINT2        (1 << EIC_INTENCLR_EXTINT2_Pos)
+#define EIC_INTENCLR_EXTINT3_Pos    3            /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
+#define EIC_INTENCLR_EXTINT3        (1 << EIC_INTENCLR_EXTINT3_Pos)
+#define EIC_INTENCLR_EXTINT4_Pos    4            /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
+#define EIC_INTENCLR_EXTINT4        (1 << EIC_INTENCLR_EXTINT4_Pos)
+#define EIC_INTENCLR_EXTINT5_Pos    5            /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
+#define EIC_INTENCLR_EXTINT5        (1 << EIC_INTENCLR_EXTINT5_Pos)
+#define EIC_INTENCLR_EXTINT6_Pos    6            /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
+#define EIC_INTENCLR_EXTINT6        (1 << EIC_INTENCLR_EXTINT6_Pos)
+#define EIC_INTENCLR_EXTINT7_Pos    7            /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
+#define EIC_INTENCLR_EXTINT7        (1 << EIC_INTENCLR_EXTINT7_Pos)
+#define EIC_INTENCLR_EXTINT8_Pos    8            /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
+#define EIC_INTENCLR_EXTINT8        (1 << EIC_INTENCLR_EXTINT8_Pos)
+#define EIC_INTENCLR_EXTINT9_Pos    9            /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
+#define EIC_INTENCLR_EXTINT9        (1 << EIC_INTENCLR_EXTINT9_Pos)
+#define EIC_INTENCLR_EXTINT10_Pos   10           /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
+#define EIC_INTENCLR_EXTINT10       (1 << EIC_INTENCLR_EXTINT10_Pos)
+#define EIC_INTENCLR_EXTINT11_Pos   11           /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
+#define EIC_INTENCLR_EXTINT11       (1 << EIC_INTENCLR_EXTINT11_Pos)
+#define EIC_INTENCLR_EXTINT12_Pos   12           /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
+#define EIC_INTENCLR_EXTINT12       (1 << EIC_INTENCLR_EXTINT12_Pos)
+#define EIC_INTENCLR_EXTINT13_Pos   13           /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
+#define EIC_INTENCLR_EXTINT13       (1 << EIC_INTENCLR_EXTINT13_Pos)
+#define EIC_INTENCLR_EXTINT14_Pos   14           /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
+#define EIC_INTENCLR_EXTINT14       (1 << EIC_INTENCLR_EXTINT14_Pos)
+#define EIC_INTENCLR_EXTINT15_Pos   15           /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
+#define EIC_INTENCLR_EXTINT15       (1 << EIC_INTENCLR_EXTINT15_Pos)
+#define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
+#define EIC_INTENCLR_EXTINT_Msk     (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value)  (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
+#define EIC_INTENCLR_MASK           0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET         0x0C         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT0_Pos    0            /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
+#define EIC_INTENSET_EXTINT0        (1 << EIC_INTENSET_EXTINT0_Pos)
+#define EIC_INTENSET_EXTINT1_Pos    1            /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
+#define EIC_INTENSET_EXTINT1        (1 << EIC_INTENSET_EXTINT1_Pos)
+#define EIC_INTENSET_EXTINT2_Pos    2            /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
+#define EIC_INTENSET_EXTINT2        (1 << EIC_INTENSET_EXTINT2_Pos)
+#define EIC_INTENSET_EXTINT3_Pos    3            /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
+#define EIC_INTENSET_EXTINT3        (1 << EIC_INTENSET_EXTINT3_Pos)
+#define EIC_INTENSET_EXTINT4_Pos    4            /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
+#define EIC_INTENSET_EXTINT4        (1 << EIC_INTENSET_EXTINT4_Pos)
+#define EIC_INTENSET_EXTINT5_Pos    5            /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
+#define EIC_INTENSET_EXTINT5        (1 << EIC_INTENSET_EXTINT5_Pos)
+#define EIC_INTENSET_EXTINT6_Pos    6            /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
+#define EIC_INTENSET_EXTINT6        (1 << EIC_INTENSET_EXTINT6_Pos)
+#define EIC_INTENSET_EXTINT7_Pos    7            /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
+#define EIC_INTENSET_EXTINT7        (1 << EIC_INTENSET_EXTINT7_Pos)
+#define EIC_INTENSET_EXTINT8_Pos    8            /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
+#define EIC_INTENSET_EXTINT8        (1 << EIC_INTENSET_EXTINT8_Pos)
+#define EIC_INTENSET_EXTINT9_Pos    9            /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
+#define EIC_INTENSET_EXTINT9        (1 << EIC_INTENSET_EXTINT9_Pos)
+#define EIC_INTENSET_EXTINT10_Pos   10           /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
+#define EIC_INTENSET_EXTINT10       (1 << EIC_INTENSET_EXTINT10_Pos)
+#define EIC_INTENSET_EXTINT11_Pos   11           /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
+#define EIC_INTENSET_EXTINT11       (1 << EIC_INTENSET_EXTINT11_Pos)
+#define EIC_INTENSET_EXTINT12_Pos   12           /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
+#define EIC_INTENSET_EXTINT12       (1 << EIC_INTENSET_EXTINT12_Pos)
+#define EIC_INTENSET_EXTINT13_Pos   13           /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
+#define EIC_INTENSET_EXTINT13       (1 << EIC_INTENSET_EXTINT13_Pos)
+#define EIC_INTENSET_EXTINT14_Pos   14           /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
+#define EIC_INTENSET_EXTINT14       (1 << EIC_INTENSET_EXTINT14_Pos)
+#define EIC_INTENSET_EXTINT15_Pos   15           /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
+#define EIC_INTENSET_EXTINT15       (1 << EIC_INTENSET_EXTINT15_Pos)
+#define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt x Enable */
+#define EIC_INTENSET_EXTINT_Msk     (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value)  (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
+#define EIC_INTENSET_MASK           0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0               */
+    __I uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1               */
+    __I uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2               */
+    __I uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3               */
+    __I uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4               */
+    __I uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5               */
+    __I uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6               */
+    __I uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7               */
+    __I uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8               */
+    __I uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9               */
+    __I uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10              */
+    __I uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11              */
+    __I uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12              */
+    __I uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13              */
+    __I uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14              */
+    __I uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15              */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x               */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET          0x10         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT0_Pos     0            /**< \brief (EIC_INTFLAG) External Interrupt 0 */
+#define EIC_INTFLAG_EXTINT0         (1 << EIC_INTFLAG_EXTINT0_Pos)
+#define EIC_INTFLAG_EXTINT1_Pos     1            /**< \brief (EIC_INTFLAG) External Interrupt 1 */
+#define EIC_INTFLAG_EXTINT1         (1 << EIC_INTFLAG_EXTINT1_Pos)
+#define EIC_INTFLAG_EXTINT2_Pos     2            /**< \brief (EIC_INTFLAG) External Interrupt 2 */
+#define EIC_INTFLAG_EXTINT2         (1 << EIC_INTFLAG_EXTINT2_Pos)
+#define EIC_INTFLAG_EXTINT3_Pos     3            /**< \brief (EIC_INTFLAG) External Interrupt 3 */
+#define EIC_INTFLAG_EXTINT3         (1 << EIC_INTFLAG_EXTINT3_Pos)
+#define EIC_INTFLAG_EXTINT4_Pos     4            /**< \brief (EIC_INTFLAG) External Interrupt 4 */
+#define EIC_INTFLAG_EXTINT4         (1 << EIC_INTFLAG_EXTINT4_Pos)
+#define EIC_INTFLAG_EXTINT5_Pos     5            /**< \brief (EIC_INTFLAG) External Interrupt 5 */
+#define EIC_INTFLAG_EXTINT5         (1 << EIC_INTFLAG_EXTINT5_Pos)
+#define EIC_INTFLAG_EXTINT6_Pos     6            /**< \brief (EIC_INTFLAG) External Interrupt 6 */
+#define EIC_INTFLAG_EXTINT6         (1 << EIC_INTFLAG_EXTINT6_Pos)
+#define EIC_INTFLAG_EXTINT7_Pos     7            /**< \brief (EIC_INTFLAG) External Interrupt 7 */
+#define EIC_INTFLAG_EXTINT7         (1 << EIC_INTFLAG_EXTINT7_Pos)
+#define EIC_INTFLAG_EXTINT8_Pos     8            /**< \brief (EIC_INTFLAG) External Interrupt 8 */
+#define EIC_INTFLAG_EXTINT8         (1 << EIC_INTFLAG_EXTINT8_Pos)
+#define EIC_INTFLAG_EXTINT9_Pos     9            /**< \brief (EIC_INTFLAG) External Interrupt 9 */
+#define EIC_INTFLAG_EXTINT9         (1 << EIC_INTFLAG_EXTINT9_Pos)
+#define EIC_INTFLAG_EXTINT10_Pos    10           /**< \brief (EIC_INTFLAG) External Interrupt 10 */
+#define EIC_INTFLAG_EXTINT10        (1 << EIC_INTFLAG_EXTINT10_Pos)
+#define EIC_INTFLAG_EXTINT11_Pos    11           /**< \brief (EIC_INTFLAG) External Interrupt 11 */
+#define EIC_INTFLAG_EXTINT11        (1 << EIC_INTFLAG_EXTINT11_Pos)
+#define EIC_INTFLAG_EXTINT12_Pos    12           /**< \brief (EIC_INTFLAG) External Interrupt 12 */
+#define EIC_INTFLAG_EXTINT12        (1 << EIC_INTFLAG_EXTINT12_Pos)
+#define EIC_INTFLAG_EXTINT13_Pos    13           /**< \brief (EIC_INTFLAG) External Interrupt 13 */
+#define EIC_INTFLAG_EXTINT13        (1 << EIC_INTFLAG_EXTINT13_Pos)
+#define EIC_INTFLAG_EXTINT14_Pos    14           /**< \brief (EIC_INTFLAG) External Interrupt 14 */
+#define EIC_INTFLAG_EXTINT14        (1 << EIC_INTFLAG_EXTINT14_Pos)
+#define EIC_INTFLAG_EXTINT15_Pos    15           /**< \brief (EIC_INTFLAG) External Interrupt 15 */
+#define EIC_INTFLAG_EXTINT15        (1 << EIC_INTFLAG_EXTINT15_Pos)
+#define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt x */
+#define EIC_INTFLAG_EXTINT_Msk      (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value)   (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
+#define EIC_INTFLAG_MASK            0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAKEUPEN0:1;      /*!< bit:      0  External Interrupt 0 Wake-up Enable */
+    uint32_t WAKEUPEN1:1;      /*!< bit:      1  External Interrupt 1 Wake-up Enable */
+    uint32_t WAKEUPEN2:1;      /*!< bit:      2  External Interrupt 2 Wake-up Enable */
+    uint32_t WAKEUPEN3:1;      /*!< bit:      3  External Interrupt 3 Wake-up Enable */
+    uint32_t WAKEUPEN4:1;      /*!< bit:      4  External Interrupt 4 Wake-up Enable */
+    uint32_t WAKEUPEN5:1;      /*!< bit:      5  External Interrupt 5 Wake-up Enable */
+    uint32_t WAKEUPEN6:1;      /*!< bit:      6  External Interrupt 6 Wake-up Enable */
+    uint32_t WAKEUPEN7:1;      /*!< bit:      7  External Interrupt 7 Wake-up Enable */
+    uint32_t WAKEUPEN8:1;      /*!< bit:      8  External Interrupt 8 Wake-up Enable */
+    uint32_t WAKEUPEN9:1;      /*!< bit:      9  External Interrupt 9 Wake-up Enable */
+    uint32_t WAKEUPEN10:1;     /*!< bit:     10  External Interrupt 10 Wake-up Enable */
+    uint32_t WAKEUPEN11:1;     /*!< bit:     11  External Interrupt 11 Wake-up Enable */
+    uint32_t WAKEUPEN12:1;     /*!< bit:     12  External Interrupt 12 Wake-up Enable */
+    uint32_t WAKEUPEN13:1;     /*!< bit:     13  External Interrupt 13 Wake-up Enable */
+    uint32_t WAKEUPEN14:1;     /*!< bit:     14  External Interrupt 14 Wake-up Enable */
+    uint32_t WAKEUPEN15:1;     /*!< bit:     15  External Interrupt 15 Wake-up Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t WAKEUPEN:16;      /*!< bit:  0..15  External Interrupt x Wake-up Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_WAKEUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_WAKEUP_OFFSET           0x14         /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
+#define EIC_WAKEUP_RESETVALUE       0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
+
+#define EIC_WAKEUP_WAKEUPEN0_Pos    0            /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN0        (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
+#define EIC_WAKEUP_WAKEUPEN1_Pos    1            /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN1        (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
+#define EIC_WAKEUP_WAKEUPEN2_Pos    2            /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN2        (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
+#define EIC_WAKEUP_WAKEUPEN3_Pos    3            /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN3        (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
+#define EIC_WAKEUP_WAKEUPEN4_Pos    4            /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN4        (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
+#define EIC_WAKEUP_WAKEUPEN5_Pos    5            /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN5        (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
+#define EIC_WAKEUP_WAKEUPEN6_Pos    6            /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN6        (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
+#define EIC_WAKEUP_WAKEUPEN7_Pos    7            /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN7        (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
+#define EIC_WAKEUP_WAKEUPEN8_Pos    8            /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN8        (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
+#define EIC_WAKEUP_WAKEUPEN9_Pos    9            /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN9        (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
+#define EIC_WAKEUP_WAKEUPEN10_Pos   10           /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN10       (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
+#define EIC_WAKEUP_WAKEUPEN11_Pos   11           /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN11       (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
+#define EIC_WAKEUP_WAKEUPEN12_Pos   12           /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN12       (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
+#define EIC_WAKEUP_WAKEUPEN13_Pos   13           /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN13       (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
+#define EIC_WAKEUP_WAKEUPEN14_Pos   14           /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN14       (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
+#define EIC_WAKEUP_WAKEUPEN15_Pos   15           /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN15       (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
+#define EIC_WAKEUP_WAKEUPEN_Pos     0            /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN_Msk     (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
+#define EIC_WAKEUP_WAKEUPEN(value)  (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
+#define EIC_WAKEUP_MASK             0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SENSE0:3;         /*!< bit:  0.. 2  Input Sense 0 Configuration        */
+    uint32_t FILTEN0:1;        /*!< bit:      3  Filter 0 Enable                    */
+    uint32_t SENSE1:3;         /*!< bit:  4.. 6  Input Sense 1 Configuration        */
+    uint32_t FILTEN1:1;        /*!< bit:      7  Filter 1 Enable                    */
+    uint32_t SENSE2:3;         /*!< bit:  8..10  Input Sense 2 Configuration        */
+    uint32_t FILTEN2:1;        /*!< bit:     11  Filter 2 Enable                    */
+    uint32_t SENSE3:3;         /*!< bit: 12..14  Input Sense 3 Configuration        */
+    uint32_t FILTEN3:1;        /*!< bit:     15  Filter 3 Enable                    */
+    uint32_t SENSE4:3;         /*!< bit: 16..18  Input Sense 4 Configuration        */
+    uint32_t FILTEN4:1;        /*!< bit:     19  Filter 4 Enable                    */
+    uint32_t SENSE5:3;         /*!< bit: 20..22  Input Sense 5 Configuration        */
+    uint32_t FILTEN5:1;        /*!< bit:     23  Filter 5 Enable                    */
+    uint32_t SENSE6:3;         /*!< bit: 24..26  Input Sense 6 Configuration        */
+    uint32_t FILTEN6:1;        /*!< bit:     27  Filter 6 Enable                    */
+    uint32_t SENSE7:3;         /*!< bit: 28..30  Input Sense 7 Configuration        */
+    uint32_t FILTEN7:1;        /*!< bit:     31  Filter 7 Enable                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET           0x18         /**< \brief (EIC_CONFIG offset) Configuration n */
+#define EIC_CONFIG_RESETVALUE       0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
+
+#define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
+#define EIC_CONFIG_SENSE0_Msk       (0x7ul << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value)    (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
+#define   EIC_CONFIG_SENSE0_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE0_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising-edge detection */
+#define   EIC_CONFIG_SENSE0_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling-edge detection */
+#define   EIC_CONFIG_SENSE0_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both-edges detection */
+#define   EIC_CONFIG_SENSE0_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High-level detection */
+#define   EIC_CONFIG_SENSE0_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low-level detection */
+#define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH      (EIC_CONFIG_SENSE0_BOTH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter 0 Enable */
+#define EIC_CONFIG_FILTEN0          (0x1ul << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
+#define EIC_CONFIG_SENSE1_Msk       (0x7ul << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value)    (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
+#define   EIC_CONFIG_SENSE1_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE1_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE1_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE1_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE1_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE1_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH      (EIC_CONFIG_SENSE1_BOTH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter 1 Enable */
+#define EIC_CONFIG_FILTEN1          (0x1ul << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
+#define EIC_CONFIG_SENSE2_Msk       (0x7ul << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value)    (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
+#define   EIC_CONFIG_SENSE2_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE2_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE2_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE2_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE2_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE2_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH      (EIC_CONFIG_SENSE2_BOTH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter 2 Enable */
+#define EIC_CONFIG_FILTEN2          (0x1ul << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
+#define EIC_CONFIG_SENSE3_Msk       (0x7ul << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value)    (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
+#define   EIC_CONFIG_SENSE3_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE3_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE3_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE3_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE3_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE3_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH      (EIC_CONFIG_SENSE3_BOTH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter 3 Enable */
+#define EIC_CONFIG_FILTEN3          (0x1ul << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
+#define EIC_CONFIG_SENSE4_Msk       (0x7ul << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value)    (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
+#define   EIC_CONFIG_SENSE4_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE4_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE4_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE4_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE4_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE4_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH      (EIC_CONFIG_SENSE4_BOTH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter 4 Enable */
+#define EIC_CONFIG_FILTEN4          (0x1ul << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
+#define EIC_CONFIG_SENSE5_Msk       (0x7ul << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value)    (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
+#define   EIC_CONFIG_SENSE5_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE5_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE5_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE5_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE5_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE5_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH      (EIC_CONFIG_SENSE5_BOTH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter 5 Enable */
+#define EIC_CONFIG_FILTEN5          (0x1ul << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
+#define EIC_CONFIG_SENSE6_Msk       (0x7ul << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value)    (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
+#define   EIC_CONFIG_SENSE6_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE6_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE6_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE6_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE6_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE6_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH      (EIC_CONFIG_SENSE6_BOTH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter 6 Enable */
+#define EIC_CONFIG_FILTEN6          (0x1ul << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
+#define EIC_CONFIG_SENSE7_Msk       (0x7ul << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value)    (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
+#define   EIC_CONFIG_SENSE7_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE7_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE7_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE7_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE7_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE7_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH      (EIC_CONFIG_SENSE7_BOTH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter 7 Enable */
+#define EIC_CONFIG_FILTEN7          (0x1ul << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK             0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EIC_CTRL_Type             CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __I  EIC_STATUS_Type           STATUS;      /**< \brief Offset: 0x01 (R/   8) Status */
+  __IO EIC_NMICTRL_Type          NMICTRL;     /**< \brief Offset: 0x02 (R/W  8) Non-Maskable Interrupt Control */
+  __IO EIC_NMIFLAG_Type          NMIFLAG;     /**< \brief Offset: 0x03 (R/W  8) Non-Maskable Interrupt Flag Status and Clear */
+  __IO EIC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) Event Control */
+  __IO EIC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+  __IO EIC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+  __IO EIC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+  __IO EIC_WAKEUP_Type           WAKEUP;      /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+  __IO EIC_CONFIG_Type           CONFIG[2];   /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EIC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/evsys.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/evsys.h
new file mode 100644
index 0000000000..9253ef69b0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/evsys.h
@@ -0,0 +1,604 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_COMPONENT_
+#define _SAMD21_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2208
+#define REV_EVSYS                   0x101
+
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint8_t  GCLKREQ:1;        /*!< bit:      4  Generic Clock Requests             */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
+#define EVSYS_CTRL_RESETVALUE       0x00ul       /**< \brief (EVSYS_CTRL reset_value) Control */
+
+#define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
+#define EVSYS_CTRL_SWRST            (0x1ul << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
+#define EVSYS_CTRL_GCLKREQ          (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK             0x11ul       /**< \brief (EVSYS_CTRL) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL:4;        /*!< bit:  0.. 3  Channel Selection                  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t SWEVT:1;          /*!< bit:      8  Software Event                     */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t EVGEN:7;          /*!< bit: 16..22  Event Generator Selection          */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PATH:2;           /*!< bit: 24..25  Path Selection                     */
+    uint32_t EDGSEL:2;         /*!< bit: 26..27  Edge Detection Selection           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
+#define EVSYS_CHANNEL_RESETVALUE    0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+
+#define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
+#define EVSYS_CHANNEL_CHANNEL_Msk   (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
+#define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
+#define EVSYS_CHANNEL_SWEVT         (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk     (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk      (0x3ul << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk    (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul  /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_MASK          0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t USER:5;           /*!< bit:  0.. 4  User Multiplexer Selection         */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t CHANNEL:5;        /*!< bit:  8..12  Channel Event Selection            */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
+#define EVSYS_USER_RESETVALUE       0x0000ul     /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+
+#define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
+#define EVSYS_USER_USER_Msk         (0x1Ful << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER(value)      (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
+#define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk      (0x1Ful << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define   EVSYS_USER_CHANNEL_0_Val        0x0ul  /**< \brief (EVSYS_USER) No Channel Output Selected */
+#define EVSYS_USER_CHANNEL_0        (EVSYS_USER_CHANNEL_0_Val      << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_MASK             0x1F1Ful     /**< \brief (EVSYS_USER) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
+    uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
+    uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
+    uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
+    uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
+    uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
+    uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
+    uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
+    uint32_t CHBUSY0:1;        /*!< bit:      8  Channel 0 Busy                     */
+    uint32_t CHBUSY1:1;        /*!< bit:      9  Channel 1 Busy                     */
+    uint32_t CHBUSY2:1;        /*!< bit:     10  Channel 2 Busy                     */
+    uint32_t CHBUSY3:1;        /*!< bit:     11  Channel 3 Busy                     */
+    uint32_t CHBUSY4:1;        /*!< bit:     12  Channel 4 Busy                     */
+    uint32_t CHBUSY5:1;        /*!< bit:     13  Channel 5 Busy                     */
+    uint32_t CHBUSY6:1;        /*!< bit:     14  Channel 6 Busy                     */
+    uint32_t CHBUSY7:1;        /*!< bit:     15  Channel 7 Busy                     */
+    uint32_t USRRDY8:1;        /*!< bit:     16  Channel 8 User Ready               */
+    uint32_t USRRDY9:1;        /*!< bit:     17  Channel 9 User Ready               */
+    uint32_t USRRDY10:1;       /*!< bit:     18  Channel 10 User Ready              */
+    uint32_t USRRDY11:1;       /*!< bit:     19  Channel 11 User Ready              */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CHBUSY8:1;        /*!< bit:     24  Channel 8 Busy                     */
+    uint32_t CHBUSY9:1;        /*!< bit:     25  Channel 9 Busy                     */
+    uint32_t CHBUSY10:1;       /*!< bit:     26  Channel 10 Busy                    */
+    uint32_t CHBUSY11:1;       /*!< bit:     27  Channel 11 Busy                    */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t USRRDY:8;         /*!< bit:  0.. 7  Channel x User Ready               */
+    uint32_t CHBUSY:8;         /*!< bit:  8..15  Channel x Busy                     */
+    uint32_t USRRDYp8:4;       /*!< bit: 16..19  Channel x+8 User Ready             */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CHBUSYp8:4;       /*!< bit: 24..27  Channel x+8 Busy                   */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE   0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1      (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2      (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3      (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4      (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5      (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6      (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk   (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1      (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos  10           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2      (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos  11           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3      (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos  12           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4      (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos  13           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5      (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos  14           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6      (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk   (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
+#define EVSYS_CHSTATUS_USRRDY8_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
+#define EVSYS_CHSTATUS_USRRDY8      (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
+#define EVSYS_CHSTATUS_USRRDY9_Pos  17           /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
+#define EVSYS_CHSTATUS_USRRDY9      (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
+#define EVSYS_CHSTATUS_USRRDY10_Pos 18           /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
+#define EVSYS_CHSTATUS_USRRDY10     (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
+#define EVSYS_CHSTATUS_USRRDY11_Pos 19           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
+#define EVSYS_CHSTATUS_USRRDY11     (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8_Pos 16           /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
+#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
+#define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
+#define EVSYS_CHSTATUS_CHBUSY8      (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
+#define EVSYS_CHSTATUS_CHBUSY9_Pos  25           /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
+#define EVSYS_CHSTATUS_CHBUSY9      (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
+#define EVSYS_CHSTATUS_CHBUSY10_Pos 26           /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
+#define EVSYS_CHSTATUS_CHBUSY10     (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
+#define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
+#define EVSYS_CHSTATUS_CHBUSY11     (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24           /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
+#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
+#define EVSYS_CHSTATUS_MASK         0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1         (1 << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2         (1 << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3         (1 << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4         (1 << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5         (1 << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6         (1 << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk      (0xFFul << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value)   (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
+#define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1         (1 << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos     10           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2         (1 << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos     11           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3         (1 << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos     12           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4         (1 << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos     13           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5         (1 << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos     14           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6         (1 << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk      (0xFFul << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value)   (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
+#define EVSYS_INTENCLR_OVR8_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR8         (1 << EVSYS_INTENCLR_OVR8_Pos)
+#define EVSYS_INTENCLR_OVR9_Pos     17           /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR9         (1 << EVSYS_INTENCLR_OVR9_Pos)
+#define EVSYS_INTENCLR_OVR10_Pos    18           /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR10        (1 << EVSYS_INTENCLR_OVR10_Pos)
+#define EVSYS_INTENCLR_OVR11_Pos    19           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR11        (1 << EVSYS_INTENCLR_OVR11_Pos)
+#define EVSYS_INTENCLR_OVRp8_Pos    16           /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVRp8_Msk    (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
+#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
+#define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD8         (1 << EVSYS_INTENCLR_EVD8_Pos)
+#define EVSYS_INTENCLR_EVD9_Pos     25           /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD9         (1 << EVSYS_INTENCLR_EVD9_Pos)
+#define EVSYS_INTENCLR_EVD10_Pos    26           /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD10        (1 << EVSYS_INTENCLR_EVD10_Pos)
+#define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD11        (1 << EVSYS_INTENCLR_EVD11_Pos)
+#define EVSYS_INTENCLR_EVDp8_Pos    24           /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVDp8_Msk    (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
+#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
+#define EVSYS_INTENCLR_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1         (1 << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2         (1 << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3         (1 << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4         (1 << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5         (1 << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6         (1 << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk      (0xFFul << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value)   (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
+#define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1         (1 << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos     10           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2         (1 << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos     11           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3         (1 << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos     12           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4         (1 << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos     13           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5         (1 << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos     14           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6         (1 << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk      (0xFFul << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value)   (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
+#define EVSYS_INTENSET_OVR8_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR8         (1 << EVSYS_INTENSET_OVR8_Pos)
+#define EVSYS_INTENSET_OVR9_Pos     17           /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR9         (1 << EVSYS_INTENSET_OVR9_Pos)
+#define EVSYS_INTENSET_OVR10_Pos    18           /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR10        (1 << EVSYS_INTENSET_OVR10_Pos)
+#define EVSYS_INTENSET_OVR11_Pos    19           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR11        (1 << EVSYS_INTENSET_OVR11_Pos)
+#define EVSYS_INTENSET_OVRp8_Pos    16           /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVRp8_Msk    (0xFul << EVSYS_INTENSET_OVRp8_Pos)
+#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
+#define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD8         (1 << EVSYS_INTENSET_EVD8_Pos)
+#define EVSYS_INTENSET_EVD9_Pos     25           /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD9         (1 << EVSYS_INTENSET_EVD9_Pos)
+#define EVSYS_INTENSET_EVD10_Pos    26           /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD10        (1 << EVSYS_INTENSET_EVD10_Pos)
+#define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD11        (1 << EVSYS_INTENSET_EVD11_Pos)
+#define EVSYS_INTENSET_EVDp8_Pos    24           /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVDp8_Msk    (0xFul << EVSYS_INTENSET_EVDp8_Pos)
+#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
+#define EVSYS_INTENSET_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
+    __I uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
+    __I uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
+    __I uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
+    __I uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
+    __I uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
+    __I uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
+    __I uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
+    __I uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection          */
+    __I uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection          */
+    __I uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection          */
+    __I uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection          */
+    __I uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection          */
+    __I uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection          */
+    __I uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection          */
+    __I uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection          */
+    __I uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun                  */
+    __I uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun                  */
+    __I uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun                 */
+    __I uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun                 */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection          */
+    __I uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection          */
+    __I uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection         */
+    __I uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection         */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun                  */
+    __I uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection          */
+    __I uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun                */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection        */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE    0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1          (1 << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2          (1 << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3          (1 << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4          (1 << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5          (1 << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6          (1 << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk       (0xFFul << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value)    (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
+#define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1          (1 << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos      10           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2          (1 << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos      11           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3          (1 << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos      12           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4          (1 << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos      13           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5          (1 << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos      14           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6          (1 << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk       (0xFFul << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value)    (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
+#define EVSYS_INTFLAG_OVR8_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
+#define EVSYS_INTFLAG_OVR8          (1 << EVSYS_INTFLAG_OVR8_Pos)
+#define EVSYS_INTFLAG_OVR9_Pos      17           /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
+#define EVSYS_INTFLAG_OVR9          (1 << EVSYS_INTFLAG_OVR9_Pos)
+#define EVSYS_INTFLAG_OVR10_Pos     18           /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
+#define EVSYS_INTFLAG_OVR10         (1 << EVSYS_INTFLAG_OVR10_Pos)
+#define EVSYS_INTFLAG_OVR11_Pos     19           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
+#define EVSYS_INTFLAG_OVR11         (1 << EVSYS_INTFLAG_OVR11_Pos)
+#define EVSYS_INTFLAG_OVRp8_Pos     16           /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
+#define EVSYS_INTFLAG_OVRp8_Msk     (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
+#define EVSYS_INTFLAG_OVRp8(value)  (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
+#define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
+#define EVSYS_INTFLAG_EVD8          (1 << EVSYS_INTFLAG_EVD8_Pos)
+#define EVSYS_INTFLAG_EVD9_Pos      25           /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
+#define EVSYS_INTFLAG_EVD9          (1 << EVSYS_INTFLAG_EVD9_Pos)
+#define EVSYS_INTFLAG_EVD10_Pos     26           /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
+#define EVSYS_INTFLAG_EVD10         (1 << EVSYS_INTFLAG_EVD10_Pos)
+#define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
+#define EVSYS_INTFLAG_EVD11         (1 << EVSYS_INTFLAG_EVD11_Pos)
+#define EVSYS_INTFLAG_EVDp8_Pos     24           /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
+#define EVSYS_INTFLAG_EVDp8_Msk     (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
+#define EVSYS_INTFLAG_EVDp8(value)  (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
+#define EVSYS_INTFLAG_MASK          0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  EVSYS_CTRL_Type           CTRL;        /**< \brief Offset: 0x00 ( /W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x04 (R/W 32) Channel */
+  __IO EVSYS_USER_Type           USER;        /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+       RoReg8                    Reserved2[0x2];
+  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
+  __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+  __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+  __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EVSYS_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/gclk.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/gclk.h
new file mode 100644
index 0000000000..13b8989129
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/gclk.h
@@ -0,0 +1,310 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_COMPONENT_
+#define _SAMD21_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAMD21_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2102
+#define REV_GCLK                    0x210
+
+/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRL_OFFSET            0x0          /**< \brief (GCLK_CTRL offset) Control */
+#define GCLK_CTRL_RESETVALUE        0x00ul       /**< \brief (GCLK_CTRL reset_value) Control */
+
+#define GCLK_CTRL_SWRST_Pos         0            /**< \brief (GCLK_CTRL) Software Reset */
+#define GCLK_CTRL_SWRST             (0x1ul << GCLK_CTRL_SWRST_Pos)
+#define GCLK_CTRL_MASK              0x01ul       /**< \brief (GCLK_CTRL) MASK Register */
+
+/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_STATUS_OFFSET          0x1          /**< \brief (GCLK_STATUS offset) Status */
+#define GCLK_STATUS_RESETVALUE      0x00ul       /**< \brief (GCLK_STATUS reset_value) Status */
+
+#define GCLK_STATUS_SYNCBUSY_Pos    7            /**< \brief (GCLK_STATUS) Synchronization Busy Status */
+#define GCLK_STATUS_SYNCBUSY        (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
+#define GCLK_STATUS_MASK            0x80ul       /**< \brief (GCLK_STATUS) MASK Register */
+
+/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:6;             /*!< bit:  0.. 5  Generic Clock Selection ID         */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t GEN:4;            /*!< bit:  8..11  Generic Clock Generator            */
+    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint16_t CLKEN:1;          /*!< bit:     14  Clock Enable                       */
+    uint16_t WRTLOCK:1;        /*!< bit:     15  Write Lock                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} GCLK_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CLKCTRL_OFFSET         0x2          /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
+#define GCLK_CLKCTRL_RESETVALUE     0x0000ul     /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
+
+#define GCLK_CLKCTRL_ID_Pos         0            /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
+#define GCLK_CLKCTRL_ID_Msk         (0x3Ful << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID(value)      (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
+#define   GCLK_CLKCTRL_ID_DFLL48_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) DFLL48 */
+#define   GCLK_CLKCTRL_ID_FDPLL_Val       0x1ul  /**< \brief (GCLK_CLKCTRL) FDPLL */
+#define   GCLK_CLKCTRL_ID_FDPLL32K_Val    0x2ul  /**< \brief (GCLK_CLKCTRL) FDPLL32K */
+#define   GCLK_CLKCTRL_ID_WDT_Val         0x3ul  /**< \brief (GCLK_CLKCTRL) WDT */
+#define   GCLK_CLKCTRL_ID_RTC_Val         0x4ul  /**< \brief (GCLK_CLKCTRL) RTC */
+#define   GCLK_CLKCTRL_ID_EIC_Val         0x5ul  /**< \brief (GCLK_CLKCTRL) EIC */
+#define   GCLK_CLKCTRL_ID_USB_Val         0x6ul  /**< \brief (GCLK_CLKCTRL) USB */
+#define   GCLK_CLKCTRL_ID_EVSYS_0_Val     0x7ul  /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
+#define   GCLK_CLKCTRL_ID_EVSYS_1_Val     0x8ul  /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
+#define   GCLK_CLKCTRL_ID_EVSYS_2_Val     0x9ul  /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
+#define   GCLK_CLKCTRL_ID_EVSYS_3_Val     0xAul  /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
+#define   GCLK_CLKCTRL_ID_EVSYS_4_Val     0xBul  /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
+#define   GCLK_CLKCTRL_ID_EVSYS_5_Val     0xCul  /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
+#define   GCLK_CLKCTRL_ID_EVSYS_6_Val     0xDul  /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
+#define   GCLK_CLKCTRL_ID_EVSYS_7_Val     0xEul  /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
+#define   GCLK_CLKCTRL_ID_EVSYS_8_Val     0xFul  /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
+#define   GCLK_CLKCTRL_ID_EVSYS_9_Val     0x10ul  /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
+#define   GCLK_CLKCTRL_ID_EVSYS_10_Val    0x11ul  /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
+#define   GCLK_CLKCTRL_ID_EVSYS_11_Val    0x12ul  /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
+#define   GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul  /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
+#define   GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul  /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul  /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul  /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul  /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul  /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul  /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
+#define   GCLK_CLKCTRL_ID_TCC0_TCC1_Val   0x1Aul  /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
+#define   GCLK_CLKCTRL_ID_TCC2_TC3_Val    0x1Bul  /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
+#define   GCLK_CLKCTRL_ID_TC4_TC5_Val     0x1Cul  /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
+#define   GCLK_CLKCTRL_ID_TC6_TC7_Val     0x1Dul  /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
+#define   GCLK_CLKCTRL_ID_ADC_Val         0x1Eul  /**< \brief (GCLK_CLKCTRL) ADC */
+#define   GCLK_CLKCTRL_ID_AC_DIG_Val      0x1Ful  /**< \brief (GCLK_CLKCTRL) AC_DIG */
+#define   GCLK_CLKCTRL_ID_AC_ANA_Val      0x20ul  /**< \brief (GCLK_CLKCTRL) AC_ANA */
+#define   GCLK_CLKCTRL_ID_DAC_Val         0x21ul  /**< \brief (GCLK_CLKCTRL) DAC */
+#define   GCLK_CLKCTRL_ID_PTC_Val         0x22ul  /**< \brief (GCLK_CLKCTRL) PTC */
+#define   GCLK_CLKCTRL_ID_I2S_0_Val       0x23ul  /**< \brief (GCLK_CLKCTRL) I2S_0 */
+#define   GCLK_CLKCTRL_ID_I2S_1_Val       0x24ul  /**< \brief (GCLK_CLKCTRL) I2S_1 */
+#define GCLK_CLKCTRL_ID_DFLL48      (GCLK_CLKCTRL_ID_DFLL48_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL       (GCLK_CLKCTRL_ID_FDPLL_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL32K    (GCLK_CLKCTRL_ID_FDPLL32K_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_WDT         (GCLK_CLKCTRL_ID_WDT_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_RTC         (GCLK_CLKCTRL_ID_RTC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EIC         (GCLK_CLKCTRL_ID_EIC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_USB         (GCLK_CLKCTRL_ID_USB_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_0     (GCLK_CLKCTRL_ID_EVSYS_0_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_1     (GCLK_CLKCTRL_ID_EVSYS_1_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_2     (GCLK_CLKCTRL_ID_EVSYS_2_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_3     (GCLK_CLKCTRL_ID_EVSYS_3_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_4     (GCLK_CLKCTRL_ID_EVSYS_4_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_5     (GCLK_CLKCTRL_ID_EVSYS_5_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_6     (GCLK_CLKCTRL_ID_EVSYS_6_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_7     (GCLK_CLKCTRL_ID_EVSYS_7_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_8     (GCLK_CLKCTRL_ID_EVSYS_8_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_9     (GCLK_CLKCTRL_ID_EVSYS_9_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_10    (GCLK_CLKCTRL_ID_EVSYS_10_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_11    (GCLK_CLKCTRL_ID_EVSYS_11_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC0_TCC1   (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC2_TC3    (GCLK_CLKCTRL_ID_TCC2_TC3_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC4_TC5     (GCLK_CLKCTRL_ID_TC4_TC5_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC6_TC7     (GCLK_CLKCTRL_ID_TC6_TC7_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_ADC         (GCLK_CLKCTRL_ID_ADC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_DIG      (GCLK_CLKCTRL_ID_AC_DIG_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_ANA      (GCLK_CLKCTRL_ID_AC_ANA_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_DAC         (GCLK_CLKCTRL_ID_DAC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_PTC         (GCLK_CLKCTRL_ID_PTC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_0       (GCLK_CLKCTRL_ID_I2S_0_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_1       (GCLK_CLKCTRL_ID_I2S_1_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_GEN_Pos        8            /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
+#define GCLK_CLKCTRL_GEN_Msk        (0xFul << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN(value)     (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
+#define   GCLK_CLKCTRL_GEN_GCLK0_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
+#define   GCLK_CLKCTRL_GEN_GCLK1_Val      0x1ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
+#define   GCLK_CLKCTRL_GEN_GCLK2_Val      0x2ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
+#define   GCLK_CLKCTRL_GEN_GCLK3_Val      0x3ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
+#define   GCLK_CLKCTRL_GEN_GCLK4_Val      0x4ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
+#define   GCLK_CLKCTRL_GEN_GCLK5_Val      0x5ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
+#define   GCLK_CLKCTRL_GEN_GCLK6_Val      0x6ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
+#define   GCLK_CLKCTRL_GEN_GCLK7_Val      0x7ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
+#define GCLK_CLKCTRL_GEN_GCLK0      (GCLK_CLKCTRL_GEN_GCLK0_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK1      (GCLK_CLKCTRL_GEN_GCLK1_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK2      (GCLK_CLKCTRL_GEN_GCLK2_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK3      (GCLK_CLKCTRL_GEN_GCLK3_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK4      (GCLK_CLKCTRL_GEN_GCLK4_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK5      (GCLK_CLKCTRL_GEN_GCLK5_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK6      (GCLK_CLKCTRL_GEN_GCLK6_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK7      (GCLK_CLKCTRL_GEN_GCLK7_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_CLKEN_Pos      14           /**< \brief (GCLK_CLKCTRL) Clock Enable */
+#define GCLK_CLKCTRL_CLKEN          (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
+#define GCLK_CLKCTRL_WRTLOCK_Pos    15           /**< \brief (GCLK_CLKCTRL) Write Lock */
+#define GCLK_CLKCTRL_WRTLOCK        (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
+#define GCLK_CLKCTRL_MASK           0xCF3Ful     /**< \brief (GCLK_CLKCTRL) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t SRC:5;            /*!< bit:  8..12  Source Select                      */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t GENEN:1;          /*!< bit:     16  Generic Clock Generator Enable     */
+    uint32_t IDC:1;            /*!< bit:     17  Improve Duty Cycle                 */
+    uint32_t OOV:1;            /*!< bit:     18  Output Off Value                   */
+    uint32_t OE:1;             /*!< bit:     19  Output Enable                      */
+    uint32_t DIVSEL:1;         /*!< bit:     20  Divide Selection                   */
+    uint32_t RUNSTDBY:1;       /*!< bit:     21  Run in Standby                     */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET         0x4          /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE     0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_ID_Pos         0            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
+#define GCLK_GENCTRL_ID_Msk         (0xFul << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID(value)      (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
+#define GCLK_GENCTRL_SRC_Pos        8            /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk        (0x1Ful << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value)     (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define   GCLK_GENCTRL_SRC_XOSC_Val       0x0ul  /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define   GCLK_GENCTRL_SRC_GCLKIN_Val     0x1ul  /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   0x2ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  0x3ul  /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC32K_Val     0x4ul  /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val    0x5ul  /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC8M_Val      0x6ul  /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
+#define   GCLK_GENCTRL_SRC_DFLL48M_Val    0x7ul  /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define   GCLK_GENCTRL_SRC_FDPLL_Val      0x8ul  /**< \brief (GCLK_GENCTRL) FDPLL output */
+#define GCLK_GENCTRL_SRC_XOSC       (GCLK_GENCTRL_SRC_XOSC_Val     << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K  (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC32K     (GCLK_GENCTRL_SRC_OSC32K_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC8M      (GCLK_GENCTRL_SRC_OSC8M_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL48M    (GCLK_GENCTRL_SRC_DFLL48M_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_FDPLL      (GCLK_GENCTRL_SRC_FDPLL_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos      16           /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN          (0x1ul << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos        17           /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC            (0x1ul << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos        18           /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV            (0x1ul << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos         19           /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE             (0x1ul << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos     20           /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL         (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos   21           /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY       (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_MASK           0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t DIV:16;           /*!< bit:  8..23  Division Factor                    */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENDIV_OFFSET          0x8          /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
+#define GCLK_GENDIV_RESETVALUE      0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
+
+#define GCLK_GENDIV_ID_Pos          0            /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
+#define GCLK_GENDIV_ID_Msk          (0xFul << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID(value)       (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
+#define GCLK_GENDIV_DIV_Pos         8            /**< \brief (GCLK_GENDIV) Division Factor */
+#define GCLK_GENDIV_DIV_Msk         (0xFFFFul << GCLK_GENDIV_DIV_Pos)
+#define GCLK_GENDIV_DIV(value)      (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
+#define GCLK_GENDIV_MASK            0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO GCLK_CTRL_Type            CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+  __I  GCLK_STATUS_Type          STATUS;      /**< \brief Offset: 0x1 (R/   8) Status */
+  __IO GCLK_CLKCTRL_Type         CLKCTRL;     /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+  __IO GCLK_GENCTRL_Type         GENCTRL;     /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+  __IO GCLK_GENDIV_Type          GENDIV;      /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_GCLK_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/hmatrixb.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/hmatrixb.h
new file mode 100644
index 0000000000..5d151feaa7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/hmatrixb.h
@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief Component description for HMATRIXB
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_HMATRIXB_COMPONENT_
+#define _SAMD21_HMATRIXB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR HMATRIXB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
+/*@{*/
+
+#define HMATRIXB_I7638
+#define REV_HMATRIXB                0x212
+
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_PRAS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRAS_OFFSET        0x080        /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE    0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+
+#define HMATRIXB_PRAS_MASK          0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */
+
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_PRBS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRBS_OFFSET        0x084        /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE    0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+
+#define HMATRIXB_PRBS_MASK          0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */
+
+/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SFR:32;           /*!< bit:  0..31  Special Function Register          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_SFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_SFR_OFFSET         0x110        /**< \brief (HMATRIXB_SFR offset) Special Function */
+#define HMATRIXB_SFR_RESETVALUE     0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */
+
+#define HMATRIXB_SFR_SFR_Pos        0            /**< \brief (HMATRIXB_SFR) Special Function Register */
+#define HMATRIXB_SFR_SFR_Msk        (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos)
+#define HMATRIXB_SFR_SFR(value)     (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
+#define HMATRIXB_SFR_MASK           0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */
+
+/** \brief HmatrixbPrs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO HMATRIXB_PRAS_Type        PRAS;        /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+  __IO HMATRIXB_PRBS_Type        PRBS;        /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+} HmatrixbPrs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief HMATRIXB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       RoReg8                    Reserved1[0x80];
+       HmatrixbPrs               Prs[16];     /**< \brief Offset: 0x080 HmatrixbPrs groups */
+       RoReg8                    Reserved2[0x10];
+  __IO HMATRIXB_SFR_Type         SFR[16];     /**< \brief Offset: 0x110 (R/W 32) Special Function */
+} Hmatrixb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/i2s.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/i2s.h
new file mode 100644
index 0000000000..38866f83b7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/i2s.h
@@ -0,0 +1,639 @@
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_COMPONENT_
+#define _SAMD21_I2S_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S                     0x110
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable                */
+    uint8_t  CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable                */
+    uint8_t  SEREN0:1;         /*!< bit:      4  Serializer 0 Enable                */
+    uint8_t  SEREN1:1;         /*!< bit:      5  Serializer 1 Enable                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable                */
+    uint8_t  SEREN:2;          /*!< bit:  4.. 5  Serializer x Enable                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET            0x00         /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE        0x00ul       /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos         0            /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST             (0x1ul << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos        1            /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE            (0x1ul << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos         2            /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0             (1 << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos         3            /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1             (1 << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos          2            /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk          (0x3ul << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value)       (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
+#define I2S_CTRLA_SEREN0_Pos        4            /**< \brief (I2S_CTRLA) Serializer 0 Enable */
+#define I2S_CTRLA_SEREN0            (1 << I2S_CTRLA_SEREN0_Pos)
+#define I2S_CTRLA_SEREN1_Pos        5            /**< \brief (I2S_CTRLA) Serializer 1 Enable */
+#define I2S_CTRLA_SEREN1            (1 << I2S_CTRLA_SEREN1_Pos)
+#define I2S_CTRLA_SEREN_Pos         4            /**< \brief (I2S_CTRLA) Serializer x Enable */
+#define I2S_CTRLA_SEREN_Msk         (0x3ul << I2S_CTRLA_SEREN_Pos)
+#define I2S_CTRLA_SEREN(value)      (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))
+#define I2S_CTRLA_MASK              0x3Ful       /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SLOTSIZE:2;       /*!< bit:  0.. 1  Slot Size                          */
+    uint32_t NBSLOTS:3;        /*!< bit:  2.. 4  Number of Slots in Frame           */
+    uint32_t FSWIDTH:2;        /*!< bit:  5.. 6  Frame Sync Width                   */
+    uint32_t BITDELAY:1;       /*!< bit:      7  Data Delay from Frame Sync         */
+    uint32_t FSSEL:1;          /*!< bit:      8  Frame Sync Select                  */
+    uint32_t :2;               /*!< bit:  9..10  Reserved                           */
+    uint32_t FSINV:1;          /*!< bit:     11  Frame Sync Invert                  */
+    uint32_t SCKSEL:1;         /*!< bit:     12  Serial Clock Select                */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t MCKSEL:1;         /*!< bit:     16  Master Clock Select                */
+    uint32_t :1;               /*!< bit:     17  Reserved                           */
+    uint32_t MCKEN:1;          /*!< bit:     18  Master Clock Enable                */
+    uint32_t MCKDIV:5;         /*!< bit: 19..23  Master Clock Division Factor       */
+    uint32_t MCKOUTDIV:5;      /*!< bit: 24..28  Master Clock Output Division Factor */
+    uint32_t FSOUTINV:1;       /*!< bit:     29  Frame Sync Output Invert           */
+    uint32_t SCKOUTINV:1;      /*!< bit:     30  Serial Clock Output Invert         */
+    uint32_t MCKOUTINV:1;      /*!< bit:     31  Master Clock Output Invert         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET          0x04         /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE      0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos    0            /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk    (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
+#define   I2S_CLKCTRL_SLOTSIZE_8_Val      0x0ul  /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_16_Val     0x1ul  /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_24_Val     0x2ul  /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_32_Val     0x3ul  /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8      (I2S_CLKCTRL_SLOTSIZE_8_Val    << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16     (I2S_CLKCTRL_SLOTSIZE_16_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24     (I2S_CLKCTRL_SLOTSIZE_24_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32     (I2S_CLKCTRL_SLOTSIZE_32_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos     2            /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk     (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value)  (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
+#define I2S_CLKCTRL_FSWIDTH_Pos     5            /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk     (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value)  (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
+#define   I2S_CLKCTRL_FSWIDTH_SLOT_Val    0x0ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define   I2S_CLKCTRL_FSWIDTH_HALF_Val    0x1ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define   I2S_CLKCTRL_FSWIDTH_BIT_Val     0x2ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define   I2S_CLKCTRL_FSWIDTH_BURST_Val   0x3ul  /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT    (I2S_CLKCTRL_FSWIDTH_SLOT_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF    (I2S_CLKCTRL_FSWIDTH_HALF_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT     (I2S_CLKCTRL_FSWIDTH_BIT_Val   << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST   (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos    7            /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY        (0x1ul << I2S_CLKCTRL_BITDELAY_Pos)
+#define   I2S_CLKCTRL_BITDELAY_LJ_Val     0x0ul  /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define   I2S_CLKCTRL_BITDELAY_I2S_Val    0x1ul  /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ     (I2S_CLKCTRL_BITDELAY_LJ_Val   << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S    (I2S_CLKCTRL_BITDELAY_I2S_Val  << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos       8            /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL           (0x1ul << I2S_CLKCTRL_FSSEL_Pos)
+#define   I2S_CLKCTRL_FSSEL_SCKDIV_Val    0x0ul  /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define   I2S_CLKCTRL_FSSEL_FSPIN_Val     0x1ul  /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV    (I2S_CLKCTRL_FSSEL_SCKDIV_Val  << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN     (I2S_CLKCTRL_FSSEL_FSPIN_Val   << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos       11           /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV           (0x1ul << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos      12           /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL          (0x1ul << I2S_CLKCTRL_SCKSEL_Pos)
+#define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val   0x0ul  /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val   0x1ul  /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV   (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN   (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos      16           /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL          (0x1ul << I2S_CLKCTRL_MCKSEL_Pos)
+#define   I2S_CLKCTRL_MCKSEL_GCLK_Val     0x0ul  /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val   0x1ul  /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK     (I2S_CLKCTRL_MCKSEL_GCLK_Val   << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN   (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos       18           /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN           (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos      19           /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk      (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value)   (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos   24           /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk   (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
+#define I2S_CLKCTRL_FSOUTINV_Pos    29           /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV        (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos   30           /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV       (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos   31           /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV       (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MASK            0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
+    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
+    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
+    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
+    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET         0x0C         /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE     0x0000ul     /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos     0            /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0         (1 << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos     1            /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1         (1 << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos      0            /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk      (0x3ul << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value)   (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
+#define I2S_INTENCLR_RXOR0_Pos      4            /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0          (1 << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos      5            /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1          (1 << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos       4            /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk       (0x3ul << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value)    (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
+#define I2S_INTENCLR_TXRDY0_Pos     8            /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0         (1 << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos     9            /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1         (1 << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos      8            /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk      (0x3ul << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value)   (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
+#define I2S_INTENCLR_TXUR0_Pos      12           /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0          (1 << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos      13           /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1          (1 << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos       12           /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk       (0x3ul << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value)    (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
+#define I2S_INTENCLR_MASK           0x3333ul     /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
+    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
+    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
+    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
+    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET         0x10         /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE     0x0000ul     /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos     0            /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0         (1 << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos     1            /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1         (1 << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos      0            /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk      (0x3ul << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value)   (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
+#define I2S_INTENSET_RXOR0_Pos      4            /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0          (1 << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos      5            /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1          (1 << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos       4            /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk       (0x3ul << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value)    (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
+#define I2S_INTENSET_TXRDY0_Pos     8            /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0         (1 << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos     9            /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1         (1 << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos      8            /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk      (0x3ul << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value)   (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
+#define I2S_INTENSET_TXUR0_Pos      12           /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0          (1 << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos      13           /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1          (1 << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos       12           /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk       (0x3ul << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value)    (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
+#define I2S_INTENSET_MASK           0x3333ul     /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0                    */
+    __I uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1                    */
+    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0                  */
+    __I uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1                  */
+    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    __I uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0                   */
+    __I uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1                   */
+    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    __I uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0                */
+    __I uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1                */
+    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x                    */
+    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x                  */
+    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    __I uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x                   */
+    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    __I uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x                */
+    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET          0x14         /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE      0x0000ul     /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos      0            /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0          (1 << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos      1            /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1          (1 << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos       0            /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk       (0x3ul << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value)    (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
+#define I2S_INTFLAG_RXOR0_Pos       4            /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0           (1 << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos       5            /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1           (1 << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos        4            /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk        (0x3ul << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value)     (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
+#define I2S_INTFLAG_TXRDY0_Pos      8            /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0          (1 << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos      9            /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1          (1 << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos       8            /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk       (0x3ul << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value)    (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
+#define I2S_INTFLAG_TXUR0_Pos       12           /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0           (1 << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos       13           /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1           (1 << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos        12           /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk        (0x3ul << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value)     (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
+#define I2S_INTFLAG_MASK            0x3333ul     /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/  16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Status */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Status      */
+    uint16_t CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable Synchronization Status */
+    uint16_t CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable Synchronization Status */
+    uint16_t SEREN0:1;         /*!< bit:      4  Serializer 0 Enable Synchronization Status */
+    uint16_t SEREN1:1;         /*!< bit:      5  Serializer 1 Enable Synchronization Status */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t DATA0:1;          /*!< bit:      8  Data 0 Synchronization Status      */
+    uint16_t DATA1:1;          /*!< bit:      9  Data 1 Synchronization Status      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable Synchronization Status */
+    uint16_t SEREN:2;          /*!< bit:  4.. 5  Serializer x Enable Synchronization Status */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t DATA:2;           /*!< bit:  8.. 9  Data x Synchronization Status      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET         0x18         /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE     0x0000ul     /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos      0            /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST          (0x1ul << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos     1            /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE         (0x1ul << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos      2            /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0          (1 << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos      3            /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1          (1 << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos       2            /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk       (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value)    (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
+#define I2S_SYNCBUSY_SEREN0_Pos     4            /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN0         (1 << I2S_SYNCBUSY_SEREN0_Pos)
+#define I2S_SYNCBUSY_SEREN1_Pos     5            /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN1         (1 << I2S_SYNCBUSY_SEREN1_Pos)
+#define I2S_SYNCBUSY_SEREN_Pos      4            /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN_Msk      (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
+#define I2S_SYNCBUSY_SEREN(value)   (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))
+#define I2S_SYNCBUSY_DATA0_Pos      8            /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
+#define I2S_SYNCBUSY_DATA0          (1 << I2S_SYNCBUSY_DATA0_Pos)
+#define I2S_SYNCBUSY_DATA1_Pos      9            /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
+#define I2S_SYNCBUSY_DATA1          (1 << I2S_SYNCBUSY_DATA1_Pos)
+#define I2S_SYNCBUSY_DATA_Pos       8            /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
+#define I2S_SYNCBUSY_DATA_Msk       (0x3ul << I2S_SYNCBUSY_DATA_Pos)
+#define I2S_SYNCBUSY_DATA(value)    (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))
+#define I2S_SYNCBUSY_MASK           0x033Ful     /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SERMODE:2;        /*!< bit:  0.. 1  Serializer Mode                    */
+    uint32_t TXDEFAULT:2;      /*!< bit:  2.. 3  Line Default Line when Slot Disabled */
+    uint32_t TXSAME:1;         /*!< bit:      4  Transmit Data when Underrun        */
+    uint32_t CLKSEL:1;         /*!< bit:      5  Clock Unit Selection               */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t SLOTADJ:1;        /*!< bit:      7  Data Slot Formatting Adjust        */
+    uint32_t DATASIZE:3;       /*!< bit:  8..10  Data Word Size                     */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WORDADJ:1;        /*!< bit:     12  Data Word Formatting Adjust        */
+    uint32_t EXTEND:2;         /*!< bit: 13..14  Data Formatting Bit Extension      */
+    uint32_t BITREV:1;         /*!< bit:     15  Data Formatting Bit Reverse        */
+    uint32_t SLOTDIS0:1;       /*!< bit:     16  Slot 0 Disabled for this Serializer */
+    uint32_t SLOTDIS1:1;       /*!< bit:     17  Slot 1 Disabled for this Serializer */
+    uint32_t SLOTDIS2:1;       /*!< bit:     18  Slot 2 Disabled for this Serializer */
+    uint32_t SLOTDIS3:1;       /*!< bit:     19  Slot 3 Disabled for this Serializer */
+    uint32_t SLOTDIS4:1;       /*!< bit:     20  Slot 4 Disabled for this Serializer */
+    uint32_t SLOTDIS5:1;       /*!< bit:     21  Slot 5 Disabled for this Serializer */
+    uint32_t SLOTDIS6:1;       /*!< bit:     22  Slot 6 Disabled for this Serializer */
+    uint32_t SLOTDIS7:1;       /*!< bit:     23  Slot 7 Disabled for this Serializer */
+    uint32_t MONO:1;           /*!< bit:     24  Mono Mode                          */
+    uint32_t DMA:1;            /*!< bit:     25  Single or Multiple DMA Channels    */
+    uint32_t RXLOOP:1;         /*!< bit:     26  Loop-back Test Mode                */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t SLOTDIS:8;        /*!< bit: 16..23  Slot x Disabled for this Serializer */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_SERCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SERCTRL_OFFSET          0x20         /**< \brief (I2S_SERCTRL offset) Serializer n Control */
+#define I2S_SERCTRL_RESETVALUE      0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
+
+#define I2S_SERCTRL_SERMODE_Pos     0            /**< \brief (I2S_SERCTRL) Serializer Mode */
+#define I2S_SERCTRL_SERMODE_Msk     (0x3ul << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE(value)  (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))
+#define   I2S_SERCTRL_SERMODE_RX_Val      0x0ul  /**< \brief (I2S_SERCTRL) Receive */
+#define   I2S_SERCTRL_SERMODE_TX_Val      0x1ul  /**< \brief (I2S_SERCTRL) Transmit */
+#define   I2S_SERCTRL_SERMODE_PDM2_Val    0x2ul  /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_SERCTRL_SERMODE_RX      (I2S_SERCTRL_SERMODE_RX_Val    << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_TX      (I2S_SERCTRL_SERMODE_TX_Val    << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_PDM2    (I2S_SERCTRL_SERMODE_PDM2_Val  << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_TXDEFAULT_Pos   2            /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
+#define I2S_SERCTRL_TXDEFAULT_Msk   (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT(value) (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))
+#define   I2S_SERCTRL_TXDEFAULT_ZERO_Val  0x0ul  /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
+#define   I2S_SERCTRL_TXDEFAULT_ONE_Val   0x1ul  /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
+#define   I2S_SERCTRL_TXDEFAULT_HIZ_Val   0x3ul  /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
+#define I2S_SERCTRL_TXDEFAULT_ZERO  (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_ONE   (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_HIZ   (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXSAME_Pos      4            /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
+#define I2S_SERCTRL_TXSAME          (0x1ul << I2S_SERCTRL_TXSAME_Pos)
+#define   I2S_SERCTRL_TXSAME_ZERO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
+#define   I2S_SERCTRL_TXSAME_SAME_Val     0x1ul  /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_ZERO     (I2S_SERCTRL_TXSAME_ZERO_Val   << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_SAME     (I2S_SERCTRL_TXSAME_SAME_Val   << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_CLKSEL_Pos      5            /**< \brief (I2S_SERCTRL) Clock Unit Selection */
+#define I2S_SERCTRL_CLKSEL          (0x1ul << I2S_SERCTRL_CLKSEL_Pos)
+#define   I2S_SERCTRL_CLKSEL_CLK0_Val     0x0ul  /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
+#define   I2S_SERCTRL_CLKSEL_CLK1_Val     0x1ul  /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
+#define I2S_SERCTRL_CLKSEL_CLK0     (I2S_SERCTRL_CLKSEL_CLK0_Val   << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK1     (I2S_SERCTRL_CLKSEL_CLK1_Val   << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_SLOTADJ_Pos     7            /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
+#define I2S_SERCTRL_SLOTADJ         (0x1ul << I2S_SERCTRL_SLOTADJ_Pos)
+#define   I2S_SERCTRL_SLOTADJ_RIGHT_Val   0x0ul  /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
+#define   I2S_SERCTRL_SLOTADJ_LEFT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_RIGHT   (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_LEFT    (I2S_SERCTRL_SLOTADJ_LEFT_Val  << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_DATASIZE_Pos    8            /**< \brief (I2S_SERCTRL) Data Word Size */
+#define I2S_SERCTRL_DATASIZE_Msk    (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE(value) (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))
+#define   I2S_SERCTRL_DATASIZE_32_Val     0x0ul  /**< \brief (I2S_SERCTRL) 32 bits */
+#define   I2S_SERCTRL_DATASIZE_24_Val     0x1ul  /**< \brief (I2S_SERCTRL) 24 bits */
+#define   I2S_SERCTRL_DATASIZE_20_Val     0x2ul  /**< \brief (I2S_SERCTRL) 20 bits */
+#define   I2S_SERCTRL_DATASIZE_18_Val     0x3ul  /**< \brief (I2S_SERCTRL) 18 bits */
+#define   I2S_SERCTRL_DATASIZE_16_Val     0x4ul  /**< \brief (I2S_SERCTRL) 16 bits */
+#define   I2S_SERCTRL_DATASIZE_16C_Val    0x5ul  /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
+#define   I2S_SERCTRL_DATASIZE_8_Val      0x6ul  /**< \brief (I2S_SERCTRL) 8 bits */
+#define   I2S_SERCTRL_DATASIZE_8C_Val     0x7ul  /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_32     (I2S_SERCTRL_DATASIZE_32_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_24     (I2S_SERCTRL_DATASIZE_24_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_20     (I2S_SERCTRL_DATASIZE_20_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_18     (I2S_SERCTRL_DATASIZE_18_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16     (I2S_SERCTRL_DATASIZE_16_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16C    (I2S_SERCTRL_DATASIZE_16C_Val  << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8      (I2S_SERCTRL_DATASIZE_8_Val    << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8C     (I2S_SERCTRL_DATASIZE_8C_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_WORDADJ_Pos     12           /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
+#define I2S_SERCTRL_WORDADJ         (0x1ul << I2S_SERCTRL_WORDADJ_Pos)
+#define   I2S_SERCTRL_WORDADJ_RIGHT_Val   0x0ul  /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
+#define   I2S_SERCTRL_WORDADJ_LEFT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
+#define I2S_SERCTRL_WORDADJ_RIGHT   (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_LEFT    (I2S_SERCTRL_WORDADJ_LEFT_Val  << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_EXTEND_Pos      13           /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
+#define I2S_SERCTRL_EXTEND_Msk      (0x3ul << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND(value)   (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))
+#define   I2S_SERCTRL_EXTEND_ZERO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Extend with zeroes */
+#define   I2S_SERCTRL_EXTEND_ONE_Val      0x1ul  /**< \brief (I2S_SERCTRL) Extend with ones */
+#define   I2S_SERCTRL_EXTEND_MSBIT_Val    0x2ul  /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
+#define   I2S_SERCTRL_EXTEND_LSBIT_Val    0x3ul  /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
+#define I2S_SERCTRL_EXTEND_ZERO     (I2S_SERCTRL_EXTEND_ZERO_Val   << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_ONE      (I2S_SERCTRL_EXTEND_ONE_Val    << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_MSBIT    (I2S_SERCTRL_EXTEND_MSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_LSBIT    (I2S_SERCTRL_EXTEND_LSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_BITREV_Pos      15           /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
+#define I2S_SERCTRL_BITREV          (0x1ul << I2S_SERCTRL_BITREV_Pos)
+#define   I2S_SERCTRL_BITREV_MSBIT_Val    0x0ul  /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define   I2S_SERCTRL_BITREV_LSBIT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_SERCTRL_BITREV_MSBIT    (I2S_SERCTRL_BITREV_MSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_LSBIT    (I2S_SERCTRL_BITREV_LSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_SLOTDIS0_Pos    16           /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS0        (1 << I2S_SERCTRL_SLOTDIS0_Pos)
+#define I2S_SERCTRL_SLOTDIS1_Pos    17           /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS1        (1 << I2S_SERCTRL_SLOTDIS1_Pos)
+#define I2S_SERCTRL_SLOTDIS2_Pos    18           /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS2        (1 << I2S_SERCTRL_SLOTDIS2_Pos)
+#define I2S_SERCTRL_SLOTDIS3_Pos    19           /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS3        (1 << I2S_SERCTRL_SLOTDIS3_Pos)
+#define I2S_SERCTRL_SLOTDIS4_Pos    20           /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS4        (1 << I2S_SERCTRL_SLOTDIS4_Pos)
+#define I2S_SERCTRL_SLOTDIS5_Pos    21           /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS5        (1 << I2S_SERCTRL_SLOTDIS5_Pos)
+#define I2S_SERCTRL_SLOTDIS6_Pos    22           /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS6        (1 << I2S_SERCTRL_SLOTDIS6_Pos)
+#define I2S_SERCTRL_SLOTDIS7_Pos    23           /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS7        (1 << I2S_SERCTRL_SLOTDIS7_Pos)
+#define I2S_SERCTRL_SLOTDIS_Pos     16           /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS_Msk     (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
+#define I2S_SERCTRL_SLOTDIS(value)  (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))
+#define I2S_SERCTRL_MONO_Pos        24           /**< \brief (I2S_SERCTRL) Mono Mode */
+#define I2S_SERCTRL_MONO            (0x1ul << I2S_SERCTRL_MONO_Pos)
+#define   I2S_SERCTRL_MONO_STEREO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Normal mode */
+#define   I2S_SERCTRL_MONO_MONO_Val       0x1ul  /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
+#define I2S_SERCTRL_MONO_STEREO     (I2S_SERCTRL_MONO_STEREO_Val   << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_MONO       (I2S_SERCTRL_MONO_MONO_Val     << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_DMA_Pos         25           /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
+#define I2S_SERCTRL_DMA             (0x1ul << I2S_SERCTRL_DMA_Pos)
+#define   I2S_SERCTRL_DMA_SINGLE_Val      0x0ul  /**< \brief (I2S_SERCTRL) Single DMA channel */
+#define   I2S_SERCTRL_DMA_MULTIPLE_Val    0x1ul  /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
+#define I2S_SERCTRL_DMA_SINGLE      (I2S_SERCTRL_DMA_SINGLE_Val    << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_MULTIPLE    (I2S_SERCTRL_DMA_MULTIPLE_Val  << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_RXLOOP_Pos      26           /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
+#define I2S_SERCTRL_RXLOOP          (0x1ul << I2S_SERCTRL_RXLOOP_Pos)
+#define I2S_SERCTRL_MASK            0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */
+
+/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Sample Data                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_DATA_OFFSET             0x30         /**< \brief (I2S_DATA offset) Data n */
+#define I2S_DATA_RESETVALUE         0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */
+
+#define I2S_DATA_DATA_Pos           0            /**< \brief (I2S_DATA) Sample Data */
+#define I2S_DATA_DATA_Msk           (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
+#define I2S_DATA_DATA(value)        (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))
+#define I2S_DATA_MASK               0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO I2S_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x3];
+  __IO I2S_CLKCTRL_Type          CLKCTRL[2];  /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+  __IO I2S_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x2];
+  __IO I2S_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x2];
+  __IO I2S_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x2];
+  __I  I2S_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x18 (R/  16) Synchronization Status */
+       RoReg8                    Reserved5[0x6];
+  __IO I2S_SERCTRL_Type          SERCTRL[2];  /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
+       RoReg8                    Reserved6[0x8];
+  __IO I2S_DATA_Type             DATA[2];     /**< \brief Offset: 0x30 (R/W 32) Data n */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_I2S_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/mtb.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/mtb.h
new file mode 100644
index 0000000000..91986ad472
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/mtb.h
@@ -0,0 +1,396 @@
+/**
+ * \file
+ *
+ * \brief Component description for MTB
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_COMPONENT_
+#define _SAMD21_MTB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR MTB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
+/*@{*/
+
+#define MTB_U2002
+#define REV_MTB                     0x100
+
+/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t WRAP:1;           /*!< bit:      2  Pointer Value Wraps                */
+    uint32_t POINTER:29;       /*!< bit:  3..31  Trace Packet Location Pointer      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_POSITION_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_POSITION_OFFSET         0x000        /**< \brief (MTB_POSITION offset) MTB Position */
+
+#define MTB_POSITION_WRAP_Pos       2            /**< \brief (MTB_POSITION) Pointer Value Wraps */
+#define MTB_POSITION_WRAP           (0x1ul << MTB_POSITION_WRAP_Pos)
+#define MTB_POSITION_POINTER_Pos    3            /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
+#define MTB_POSITION_POINTER_Msk    (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
+#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
+#define MTB_POSITION_MASK           0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
+
+/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MASK:5;           /*!< bit:  0.. 4  Maximum Value of the Trace Buffer in SRAM */
+    uint32_t TSTARTEN:1;       /*!< bit:      5  Trace Start Input Enable           */
+    uint32_t TSTOPEN:1;        /*!< bit:      6  Trace Stop Input Enable            */
+    uint32_t SFRWPRIV:1;       /*!< bit:      7  Special Function Register Write Privilege */
+    uint32_t RAMPRIV:1;        /*!< bit:      8  SRAM Privilege                     */
+    uint32_t HALTREQ:1;        /*!< bit:      9  Halt Request                       */
+    uint32_t :21;              /*!< bit: 10..30  Reserved                           */
+    uint32_t EN:1;             /*!< bit:     31  Main Trace Enable                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_MASTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_MASTER_OFFSET           0x004        /**< \brief (MTB_MASTER offset) MTB Master */
+#define MTB_MASTER_RESETVALUE       0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
+
+#define MTB_MASTER_MASK_Pos         0            /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
+#define MTB_MASTER_MASK_Msk         (0x1Ful << MTB_MASTER_MASK_Pos)
+#define MTB_MASTER_MASK(value)      (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
+#define MTB_MASTER_TSTARTEN_Pos     5            /**< \brief (MTB_MASTER) Trace Start Input Enable */
+#define MTB_MASTER_TSTARTEN         (0x1ul << MTB_MASTER_TSTARTEN_Pos)
+#define MTB_MASTER_TSTOPEN_Pos      6            /**< \brief (MTB_MASTER) Trace Stop Input Enable */
+#define MTB_MASTER_TSTOPEN          (0x1ul << MTB_MASTER_TSTOPEN_Pos)
+#define MTB_MASTER_SFRWPRIV_Pos     7            /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
+#define MTB_MASTER_SFRWPRIV         (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
+#define MTB_MASTER_RAMPRIV_Pos      8            /**< \brief (MTB_MASTER) SRAM Privilege */
+#define MTB_MASTER_RAMPRIV          (0x1ul << MTB_MASTER_RAMPRIV_Pos)
+#define MTB_MASTER_HALTREQ_Pos      9            /**< \brief (MTB_MASTER) Halt Request */
+#define MTB_MASTER_HALTREQ          (0x1ul << MTB_MASTER_HALTREQ_Pos)
+#define MTB_MASTER_EN_Pos           31           /**< \brief (MTB_MASTER) Main Trace Enable */
+#define MTB_MASTER_EN               (0x1ul << MTB_MASTER_EN_Pos)
+#define MTB_MASTER_MASK_            0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
+
+/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t AUTOSTOP:1;       /*!< bit:      0  Auto Stop Tracing                  */
+    uint32_t AUTOHALT:1;       /*!< bit:      1  Auto Halt Request                  */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t WATERMARK:29;     /*!< bit:  3..31  Watermark value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_FLOW_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_FLOW_OFFSET             0x008        /**< \brief (MTB_FLOW offset) MTB Flow */
+#define MTB_FLOW_RESETVALUE         0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
+
+#define MTB_FLOW_AUTOSTOP_Pos       0            /**< \brief (MTB_FLOW) Auto Stop Tracing */
+#define MTB_FLOW_AUTOSTOP           (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
+#define MTB_FLOW_AUTOHALT_Pos       1            /**< \brief (MTB_FLOW) Auto Halt Request */
+#define MTB_FLOW_AUTOHALT           (0x1ul << MTB_FLOW_AUTOHALT_Pos)
+#define MTB_FLOW_WATERMARK_Pos      3            /**< \brief (MTB_FLOW) Watermark value */
+#define MTB_FLOW_WATERMARK_Msk      (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
+#define MTB_FLOW_WATERMARK(value)   (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
+#define MTB_FLOW_MASK               0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
+
+/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/  32) MTB Base -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_BASE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_BASE_OFFSET             0x00C        /**< \brief (MTB_BASE offset) MTB Base */
+#define MTB_BASE_MASK               0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
+
+/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_ITCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_ITCTRL_OFFSET           0xF00        /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
+#define MTB_ITCTRL_MASK             0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
+
+/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CLAIMSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMSET_OFFSET         0xFA0        /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
+#define MTB_CLAIMSET_MASK           0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
+
+/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CLAIMCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMCLR_OFFSET         0xFA4        /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
+#define MTB_CLAIMCLR_MASK           0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
+
+/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_LOCKACCESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKACCESS_OFFSET       0xFB0        /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
+#define MTB_LOCKACCESS_MASK         0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
+
+/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/  32) MTB Lock Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_LOCKSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKSTATUS_OFFSET       0xFB4        /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
+#define MTB_LOCKSTATUS_MASK         0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
+
+/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/  32) MTB Authentication Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_AUTHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_AUTHSTATUS_OFFSET       0xFB8        /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
+#define MTB_AUTHSTATUS_MASK         0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
+
+/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/  32) MTB Device Architecture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVARCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVARCH_OFFSET          0xFBC        /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
+#define MTB_DEVARCH_MASK            0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
+
+/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/  32) MTB Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVID_OFFSET            0xFC8        /**< \brief (MTB_DEVID offset) MTB Device Configuration */
+#define MTB_DEVID_MASK              0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
+
+/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/  32) MTB Device Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVTYPE_OFFSET          0xFCC        /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
+#define MTB_DEVTYPE_MASK            0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
+
+/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID4_OFFSET             0xFD0        /**< \brief (MTB_PID4 offset) CoreSight */
+#define MTB_PID4_MASK               0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
+
+/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID5_OFFSET             0xFD4        /**< \brief (MTB_PID5 offset) CoreSight */
+#define MTB_PID5_MASK               0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
+
+/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID6_OFFSET             0xFD8        /**< \brief (MTB_PID6 offset) CoreSight */
+#define MTB_PID6_MASK               0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
+
+/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID7_OFFSET             0xFDC        /**< \brief (MTB_PID7 offset) CoreSight */
+#define MTB_PID7_MASK               0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
+
+/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID0_OFFSET             0xFE0        /**< \brief (MTB_PID0 offset) CoreSight */
+#define MTB_PID0_MASK               0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
+
+/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID1_OFFSET             0xFE4        /**< \brief (MTB_PID1 offset) CoreSight */
+#define MTB_PID1_MASK               0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
+
+/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID2_OFFSET             0xFE8        /**< \brief (MTB_PID2 offset) CoreSight */
+#define MTB_PID2_MASK               0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
+
+/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID3_OFFSET             0xFEC        /**< \brief (MTB_PID3 offset) CoreSight */
+#define MTB_PID3_MASK               0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
+
+/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID0_OFFSET             0xFF0        /**< \brief (MTB_CID0 offset) CoreSight */
+#define MTB_CID0_MASK               0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
+
+/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID1_OFFSET             0xFF4        /**< \brief (MTB_CID1 offset) CoreSight */
+#define MTB_CID1_MASK               0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
+
+/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID2_OFFSET             0xFF8        /**< \brief (MTB_CID2 offset) CoreSight */
+#define MTB_CID2_MASK               0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
+
+/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID3_OFFSET             0xFFC        /**< \brief (MTB_CID3 offset) CoreSight */
+#define MTB_CID3_MASK               0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
+
+/** \brief MTB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO MTB_POSITION_Type         POSITION;    /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+  __IO MTB_MASTER_Type           MASTER;      /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+  __IO MTB_FLOW_Type             FLOW;        /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+  __I  MTB_BASE_Type             BASE;        /**< \brief Offset: 0x00C (R/  32) MTB Base */
+       RoReg8                    Reserved1[0xEF0];
+  __IO MTB_ITCTRL_Type           ITCTRL;      /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+       RoReg8                    Reserved2[0x9C];
+  __IO MTB_CLAIMSET_Type         CLAIMSET;    /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+  __IO MTB_CLAIMCLR_Type         CLAIMCLR;    /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+       RoReg8                    Reserved3[0x8];
+  __IO MTB_LOCKACCESS_Type       LOCKACCESS;  /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+  __I  MTB_LOCKSTATUS_Type       LOCKSTATUS;  /**< \brief Offset: 0xFB4 (R/  32) MTB Lock Status */
+  __I  MTB_AUTHSTATUS_Type       AUTHSTATUS;  /**< \brief Offset: 0xFB8 (R/  32) MTB Authentication Status */
+  __I  MTB_DEVARCH_Type          DEVARCH;     /**< \brief Offset: 0xFBC (R/  32) MTB Device Architecture */
+       RoReg8                    Reserved4[0x8];
+  __I  MTB_DEVID_Type            DEVID;       /**< \brief Offset: 0xFC8 (R/  32) MTB Device Configuration */
+  __I  MTB_DEVTYPE_Type          DEVTYPE;     /**< \brief Offset: 0xFCC (R/  32) MTB Device Type */
+  __I  MTB_PID4_Type             PID4;        /**< \brief Offset: 0xFD0 (R/  32) CoreSight */
+  __I  MTB_PID5_Type             PID5;        /**< \brief Offset: 0xFD4 (R/  32) CoreSight */
+  __I  MTB_PID6_Type             PID6;        /**< \brief Offset: 0xFD8 (R/  32) CoreSight */
+  __I  MTB_PID7_Type             PID7;        /**< \brief Offset: 0xFDC (R/  32) CoreSight */
+  __I  MTB_PID0_Type             PID0;        /**< \brief Offset: 0xFE0 (R/  32) CoreSight */
+  __I  MTB_PID1_Type             PID1;        /**< \brief Offset: 0xFE4 (R/  32) CoreSight */
+  __I  MTB_PID2_Type             PID2;        /**< \brief Offset: 0xFE8 (R/  32) CoreSight */
+  __I  MTB_PID3_Type             PID3;        /**< \brief Offset: 0xFEC (R/  32) CoreSight */
+  __I  MTB_CID0_Type             CID0;        /**< \brief Offset: 0xFF0 (R/  32) CoreSight */
+  __I  MTB_CID1_Type             CID1;        /**< \brief Offset: 0xFF4 (R/  32) CoreSight */
+  __I  MTB_CID2_Type             CID2;        /**< \brief Offset: 0xFF8 (R/  32) CoreSight */
+  __I  MTB_CID3_Type             CID3;        /**< \brief Offset: 0xFFC (R/  32) CoreSight */
+} Mtb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_MTB_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/nvmctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
new file mode 100644
index 0000000000..5d838b2682
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
@@ -0,0 +1,627 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_COMPONENT_
+#define _SAMD21_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL                 0x202
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE    0x0000ul     /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk       (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value)    (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
+#define   NVMCTRL_CTRLA_CMD_ER_Val        0x2ul  /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_WP_Val        0x4ul  /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_EAR_Val       0x5ul  /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_WAP_Val       0x6ul  /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_SF_Val        0xAul  /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define   NVMCTRL_CTRLA_CMD_WL_Val        0xFul  /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define   NVMCTRL_CTRLA_CMD_RWWEEER_Val   0x1Aul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_RWWEEWP_Val   0x1Cul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_LR_Val        0x40ul  /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_UR_Val        0x41ul  /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_SPRM_Val      0x42ul  /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_CPRM_Val      0x43ul  /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_PBC_Val       0x44ul  /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define   NVMCTRL_CTRLA_CMD_SSB_Val       0x45ul  /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define   NVMCTRL_CTRLA_CMD_INVALL_Val    0x46ul  /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP       (NVMCTRL_CTRLA_CMD_WAP_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF        (NVMCTRL_CTRLA_CMD_SF_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL        (NVMCTRL_CTRLA_CMD_WL_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_RWWEEER   (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_RWWEEWP   (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR        (NVMCTRL_CTRLA_CMD_LR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR        (NVMCTRL_CTRLA_CMD_UR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM      (NVMCTRL_CTRLA_CMD_SPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM      (NVMCTRL_CTRLA_CMD_CPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC       (NVMCTRL_CTRLA_CMD_PBC_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk     (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value)  (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
+#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     0xA5ul  /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK          0xFF7Ful     /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t RWS:4;            /*!< bit:  1.. 4  NVM Read Wait States               */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t MANW:1;           /*!< bit:      7  Manual Write                       */
+    uint32_t SLEEPPRM:2;       /*!< bit:  8.. 9  Power Reduction Mode during Sleep  */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t READMODE:2;       /*!< bit: 16..17  NVMCTRL Read Mode                  */
+    uint32_t CACHEDIS:1;       /*!< bit:     18  Cache Disable                      */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk       (0xFul << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value)    (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
+#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    0x0ul  /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_HALF_Val      0x1ul  /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_DUAL_Val      0x2ul  /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW          (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul  /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk  (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
+#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul  /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS      (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK          0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
+    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
+    uint32_t :1;               /*!< bit:     19  Reserved                           */
+    uint32_t RWWEEP:12;        /*!< bit: 20..31  RWW EEPROM Pages                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk      (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
+#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk       (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
+#define   NVMCTRL_PARAM_PSZ_8_Val         0x0ul  /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define   NVMCTRL_PARAM_PSZ_16_Val        0x1ul  /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define   NVMCTRL_PARAM_PSZ_32_Val        0x2ul  /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define   NVMCTRL_PARAM_PSZ_64_Val        0x3ul  /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define   NVMCTRL_PARAM_PSZ_128_Val       0x4ul  /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define   NVMCTRL_PARAM_PSZ_256_Val       0x5ul  /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define   NVMCTRL_PARAM_PSZ_512_Val       0x6ul  /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define   NVMCTRL_PARAM_PSZ_1024_Val      0x7ul  /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_RWWEEP_Pos    20           /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
+#define NVMCTRL_PARAM_RWWEEP_Msk    (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos)
+#define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
+#define NVMCTRL_PARAM_MASK          0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY      (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR      (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK       0x03ul       /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY      (0x1ul << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR      (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK       0x03ul       /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
+    __I uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE  0x00ul       /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY       (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR       (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK        0x03ul       /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PRM:1;            /*!< bit:      0  Power Reduction Mode               */
+    uint16_t LOAD:1;           /*!< bit:      1  NVM Page Buffer Active Loading     */
+    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Status           */
+    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Status                  */
+    uint16_t NVME:1;           /*!< bit:      4  NVM Error                          */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t SB:1;             /*!< bit:      8  Security Bit Status                */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE   0x0000ul     /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM          (0x1ul << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD         (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE        (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE        (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME         (0x1ul << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB           (0x1ul << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK         0x011Ful     /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:22;          /*!< bit:  0..21  NVM Address                        */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE     0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk       (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
+#define NVMCTRL_ADDR_MASK           0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LOCK:16;          /*!< bit:  0..15  Region Lock Bits                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk       (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value)    (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
+#define NVMCTRL_LOCK_MASK           0xFFFFul     /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+       RoReg8                    Reserved1[0x2];
+  __IO NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
+  __IO NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x3];
+  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x10 (R/W  8) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x3];
+  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x14 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x3];
+  __IO NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x18 (R/W 16) Status */
+       RoReg8                    Reserved5[0x2];
+  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x1C (R/W 32) Address */
+  __IO NVMCTRL_LOCK_Type         LOCK;        /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_NVMCTRL_AUX3
+
+#define SECTION_NVMCTRL_CAL
+
+#define SECTION_NVMCTRL_LOCKBIT
+
+#define SECTION_NVMCTRL_OTP1
+
+#define SECTION_NVMCTRL_OTP2
+
+#define SECTION_NVMCTRL_OTP4
+
+#define SECTION_NVMCTRL_TEMP_LOG
+
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCAL_ADDR      (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_BIASCAL_Pos       3            /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
+#define ADC_FUSES_BIASCAL_Msk       (0x7ul << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL(value)    (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
+
+#define ADC_FUSES_LINEARITY_0_ADDR  NVMCTRL_OTP4
+#define ADC_FUSES_LINEARITY_0_Pos   27           /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
+#define ADC_FUSES_LINEARITY_0_Msk   (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
+
+#define ADC_FUSES_LINEARITY_1_ADDR  (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_LINEARITY_1_Pos   0            /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
+#define ADC_FUSES_LINEARITY_1_Msk   (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
+
+#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk    (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
+
+#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk      (0x3ul << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
+
+#define FUSES_BOD33_EN_ADDR         NVMCTRL_USER
+#define FUSES_BOD33_EN_Pos          14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define FUSES_BOD33_EN_Msk          (0x1ul << FUSES_BOD33_EN_Pos)
+
+#define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
+#define FUSES_BOD33_HYST_Pos        8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk        (0x1ul << FUSES_BOD33_HYST_Pos)
+
+#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
+#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
+
+#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
+#define FUSES_DFLL48M_FINE_CAL_Pos  0            /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
+#define FUSES_DFLL48M_FINE_CAL_Msk  (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
+#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
+
+#define FUSES_HOT_ADC_VAL_ADDR      (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_Pos       20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define FUSES_HOT_ADC_VAL_Msk       (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
+#define FUSES_HOT_ADC_VAL(value)    (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
+
+#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk     (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk  (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk  (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
+
+#define FUSES_OSC32K_CAL_ADDR       (NVMCTRL_OTP4 + 4)
+#define FUSES_OSC32K_CAL_Pos        6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define FUSES_OSC32K_CAL_Msk        (0x7Ful << FUSES_OSC32K_CAL_Pos)
+#define FUSES_OSC32K_CAL(value)     (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
+
+#define FUSES_ROOM_ADC_VAL_ADDR     (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_Pos      8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define FUSES_ROOM_ADC_VAL_Msk      (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
+#define FUSES_ROOM_ADC_VAL(value)   (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk    (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
+
+#define FUSES_SERIAL_NUMBER_0_ADDR  (NVMCTRL_AUX3 + 64)
+#define FUSES_SERIAL_NUMBER_0_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 31:0 */
+#define FUSES_SERIAL_NUMBER_0_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_0_Pos)
+#define FUSES_SERIAL_NUMBER_0(value) (FUSES_SERIAL_NUMBER_0_Msk & ((value) << FUSES_SERIAL_NUMBER_0_Pos))
+
+#define FUSES_SERIAL_NUMBER_1_ADDR  (NVMCTRL_AUX3 + 68)
+#define FUSES_SERIAL_NUMBER_1_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 63:32 */
+#define FUSES_SERIAL_NUMBER_1_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_1_Pos)
+#define FUSES_SERIAL_NUMBER_1(value) (FUSES_SERIAL_NUMBER_1_Msk & ((value) << FUSES_SERIAL_NUMBER_1_Pos))
+
+#define FUSES_SERIAL_NUMBER_2_ADDR  (NVMCTRL_AUX3 + 72)
+#define FUSES_SERIAL_NUMBER_2_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 95:64 */
+#define FUSES_SERIAL_NUMBER_2_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_2_Pos)
+#define FUSES_SERIAL_NUMBER_2(value) (FUSES_SERIAL_NUMBER_2_Msk & ((value) << FUSES_SERIAL_NUMBER_2_Pos))
+
+#define FUSES_SERIAL_NUMBER_3_ADDR  (NVMCTRL_AUX3 + 12)
+#define FUSES_SERIAL_NUMBER_3_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number word 3 */
+#define FUSES_SERIAL_NUMBER_3_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_3_Pos)
+#define FUSES_SERIAL_NUMBER_3(value) (FUSES_SERIAL_NUMBER_3_Msk & ((value) << FUSES_SERIAL_NUMBER_3_Pos))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk  (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
+
+/* Compatible definition for previous driver (begin 1) */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
+/* Compatible definition for previous driver (end 1) */
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
+
+/* Compatible definition for previous driver (begin 2) */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
+
+#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)
+#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)
+#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_EN_Pos  14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define SYSCTRL_FUSES_BOD33_EN_Msk  (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)
+
+#define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
+#define SYSCTRL_FUSES_BOD33_HYST_Pos 8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
+
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
+
+#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
+#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
+/* Compatible definition for previous driver (end 2) */
+#define USB_FUSES_TRANSN_ADDR       (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSN_Pos        13           /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk        (0x1Ful << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
+
+#define USB_FUSES_TRANSP_ADDR       (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSP_Pos        18           /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk        (0x1Ful << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
+
+#define USB_FUSES_TRIM_ADDR         (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRIM_Pos          23           /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk          (0x7ul << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
+
+#define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos      26           /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk      (0x1ul << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos        25           /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk        (0x1ul << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos      3            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk      (0xFul << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
+
+#define WDT_FUSES_PER_ADDR          NVMCTRL_USER
+#define WDT_FUSES_PER_Pos           27           /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk           (0xFul << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
+
+#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos           7            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk           (0x1ul << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_0_ADDR     NVMCTRL_USER
+#define WDT_FUSES_WINDOW_0_Pos      31           /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
+#define WDT_FUSES_WINDOW_0_Msk      (0x1ul << WDT_FUSES_WINDOW_0_Pos)
+
+#define WDT_FUSES_WINDOW_1_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_1_Pos      0            /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
+#define WDT_FUSES_WINDOW_1_Msk      (0x7ul << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1(value)   (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
+
+/*@}*/
+
+#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pac.h
new file mode 100644
index 0000000000..2c01e2519e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pac.h
@@ -0,0 +1,104 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC_COMPONENT_
+#define _SAMD21_PAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2211
+#define REV_PAC                     0x101
+
+/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Clear             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WPCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPCLR_OFFSET            0x0          /**< \brief (PAC_WPCLR offset) Write Protection Clear */
+#define PAC_WPCLR_RESETVALUE        0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
+
+#define PAC_WPCLR_WP_Pos            1            /**< \brief (PAC_WPCLR) Write Protection Clear */
+#define PAC_WPCLR_WP_Msk            (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
+#define PAC_WPCLR_WP(value)         (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
+#define PAC_WPCLR_MASK              0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
+
+/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Set               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WPSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPSET_OFFSET            0x4          /**< \brief (PAC_WPSET offset) Write Protection Set */
+#define PAC_WPSET_RESETVALUE        0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */
+
+#define PAC_WPSET_WP_Pos            1            /**< \brief (PAC_WPSET) Write Protection Set */
+#define PAC_WPSET_WP_Msk            (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
+#define PAC_WPSET_WP(value)         (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
+#define PAC_WPSET_MASK              0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PAC_WPCLR_Type            WPCLR;       /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+  __IO PAC_WPSET_Type            WPSET;       /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PAC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pm.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pm.h
new file mode 100644
index 0000000000..216668a7a7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pm.h
@@ -0,0 +1,555 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_COMPONENT_
+#define _SAMD21_PM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PM Power Manager */
+/*@{*/
+
+#define PM_U2206
+#define REV_PM                      0x212
+
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRL_OFFSET              0x00         /**< \brief (PM_CTRL offset) Control */
+#define PM_CTRL_RESETVALUE          0x00ul       /**< \brief (PM_CTRL reset_value) Control */
+
+#define PM_CTRL_MASK                0x00ul       /**< \brief (PM_CTRL) MASK Register */
+
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W  8) Sleep Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  IDLE:2;           /*!< bit:  0.. 1  Idle Mode Configuration            */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_SLEEP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEP_OFFSET             0x01         /**< \brief (PM_SLEEP offset) Sleep Mode */
+#define PM_SLEEP_RESETVALUE         0x00ul       /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+
+#define PM_SLEEP_IDLE_Pos           0            /**< \brief (PM_SLEEP) Idle Mode Configuration */
+#define PM_SLEEP_IDLE_Msk           (0x3ul << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE(value)        (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
+#define   PM_SLEEP_IDLE_CPU_Val           0x0ul  /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define   PM_SLEEP_IDLE_AHB_Val           0x1ul  /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define   PM_SLEEP_IDLE_APB_Val           0x2ul  /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define PM_SLEEP_IDLE_CPU           (PM_SLEEP_IDLE_CPU_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_AHB           (PM_SLEEP_IDLE_AHB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_APB           (PM_SLEEP_IDLE_APB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_MASK               0x03ul       /**< \brief (PM_SLEEP) MASK Register */
+
+/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W  8) External Reset Controller -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SETDIS:1;         /*!< bit:      0  External Reset Disable             */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_EXTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_EXTCTRL_OFFSET           0x02         /**< \brief (PM_EXTCTRL offset) External Reset Controller */
+#define PM_EXTCTRL_RESETVALUE       0x00ul       /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */
+
+#define PM_EXTCTRL_SETDIS_Pos       0            /**< \brief (PM_EXTCTRL) External Reset Disable */
+#define PM_EXTCTRL_SETDIS           (0x1ul << PM_EXTCTRL_SETDIS_Pos)
+#define PM_EXTCTRL_MASK             0x01ul       /**< \brief (PM_EXTCTRL) MASK Register */
+
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W  8) CPU Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CPUDIV:3;         /*!< bit:  0.. 2  CPU Prescaler Selection            */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CPUSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CPUSEL_OFFSET            0x08         /**< \brief (PM_CPUSEL offset) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE        0x00ul       /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+
+#define PM_CPUSEL_CPUDIV_Pos        0            /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
+#define PM_CPUSEL_CPUDIV_Msk        (0x7ul << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV(value)     (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
+#define   PM_CPUSEL_CPUDIV_DIV1_Val       0x0ul  /**< \brief (PM_CPUSEL) Divide by 1 */
+#define   PM_CPUSEL_CPUDIV_DIV2_Val       0x1ul  /**< \brief (PM_CPUSEL) Divide by 2 */
+#define   PM_CPUSEL_CPUDIV_DIV4_Val       0x2ul  /**< \brief (PM_CPUSEL) Divide by 4 */
+#define   PM_CPUSEL_CPUDIV_DIV8_Val       0x3ul  /**< \brief (PM_CPUSEL) Divide by 8 */
+#define   PM_CPUSEL_CPUDIV_DIV16_Val      0x4ul  /**< \brief (PM_CPUSEL) Divide by 16 */
+#define   PM_CPUSEL_CPUDIV_DIV32_Val      0x5ul  /**< \brief (PM_CPUSEL) Divide by 32 */
+#define   PM_CPUSEL_CPUDIV_DIV64_Val      0x6ul  /**< \brief (PM_CPUSEL) Divide by 64 */
+#define   PM_CPUSEL_CPUDIV_DIV128_Val     0x7ul  /**< \brief (PM_CPUSEL) Divide by 128 */
+#define PM_CPUSEL_CPUDIV_DIV1       (PM_CPUSEL_CPUDIV_DIV1_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV2       (PM_CPUSEL_CPUDIV_DIV2_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV4       (PM_CPUSEL_CPUDIV_DIV4_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV8       (PM_CPUSEL_CPUDIV_DIV8_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV16      (PM_CPUSEL_CPUDIV_DIV16_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV32      (PM_CPUSEL_CPUDIV_DIV32_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV64      (PM_CPUSEL_CPUDIV_DIV64_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV128     (PM_CPUSEL_CPUDIV_DIV128_Val   << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_MASK              0x07ul       /**< \brief (PM_CPUSEL) MASK Register */
+
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W  8) APBA Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBADIV:3;        /*!< bit:  0.. 2  APBA Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBASEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBASEL_OFFSET           0x09         /**< \brief (PM_APBASEL offset) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE       0x00ul       /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+
+#define PM_APBASEL_APBADIV_Pos      0            /**< \brief (PM_APBASEL) APBA Prescaler Selection */
+#define PM_APBASEL_APBADIV_Msk      (0x7ul << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV(value)   (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
+#define   PM_APBASEL_APBADIV_DIV1_Val     0x0ul  /**< \brief (PM_APBASEL) Divide by 1 */
+#define   PM_APBASEL_APBADIV_DIV2_Val     0x1ul  /**< \brief (PM_APBASEL) Divide by 2 */
+#define   PM_APBASEL_APBADIV_DIV4_Val     0x2ul  /**< \brief (PM_APBASEL) Divide by 4 */
+#define   PM_APBASEL_APBADIV_DIV8_Val     0x3ul  /**< \brief (PM_APBASEL) Divide by 8 */
+#define   PM_APBASEL_APBADIV_DIV16_Val    0x4ul  /**< \brief (PM_APBASEL) Divide by 16 */
+#define   PM_APBASEL_APBADIV_DIV32_Val    0x5ul  /**< \brief (PM_APBASEL) Divide by 32 */
+#define   PM_APBASEL_APBADIV_DIV64_Val    0x6ul  /**< \brief (PM_APBASEL) Divide by 64 */
+#define   PM_APBASEL_APBADIV_DIV128_Val   0x7ul  /**< \brief (PM_APBASEL) Divide by 128 */
+#define PM_APBASEL_APBADIV_DIV1     (PM_APBASEL_APBADIV_DIV1_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV2     (PM_APBASEL_APBADIV_DIV2_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV4     (PM_APBASEL_APBADIV_DIV4_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV8     (PM_APBASEL_APBADIV_DIV8_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV16    (PM_APBASEL_APBADIV_DIV16_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV32    (PM_APBASEL_APBADIV_DIV32_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV64    (PM_APBASEL_APBADIV_DIV64_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV128   (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_MASK             0x07ul       /**< \brief (PM_APBASEL) MASK Register */
+
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W  8) APBB Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBBDIV:3;        /*!< bit:  0.. 2  APBB Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBBSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBSEL_OFFSET           0x0A         /**< \brief (PM_APBBSEL offset) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+
+#define PM_APBBSEL_APBBDIV_Pos      0            /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
+#define PM_APBBSEL_APBBDIV_Msk      (0x7ul << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV(value)   (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
+#define   PM_APBBSEL_APBBDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBBSEL) Divide by 1 */
+#define   PM_APBBSEL_APBBDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBBSEL) Divide by 2 */
+#define   PM_APBBSEL_APBBDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBBSEL) Divide by 4 */
+#define   PM_APBBSEL_APBBDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBBSEL) Divide by 8 */
+#define   PM_APBBSEL_APBBDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBBSEL) Divide by 16 */
+#define   PM_APBBSEL_APBBDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBBSEL) Divide by 32 */
+#define   PM_APBBSEL_APBBDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBBSEL) Divide by 64 */
+#define   PM_APBBSEL_APBBDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBBSEL) Divide by 128 */
+#define PM_APBBSEL_APBBDIV_DIV1     (PM_APBBSEL_APBBDIV_DIV1_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV2     (PM_APBBSEL_APBBDIV_DIV2_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV4     (PM_APBBSEL_APBBDIV_DIV4_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV8     (PM_APBBSEL_APBBDIV_DIV8_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV16    (PM_APBBSEL_APBBDIV_DIV16_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV32    (PM_APBBSEL_APBBDIV_DIV32_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV64    (PM_APBBSEL_APBBDIV_DIV64_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV128   (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_MASK             0x07ul       /**< \brief (PM_APBBSEL) MASK Register */
+
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W  8) APBC Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBCDIV:3;        /*!< bit:  0.. 2  APBC Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBCSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCSEL_OFFSET           0x0B         /**< \brief (PM_APBCSEL offset) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+
+#define PM_APBCSEL_APBCDIV_Pos      0            /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
+#define PM_APBCSEL_APBCDIV_Msk      (0x7ul << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV(value)   (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
+#define   PM_APBCSEL_APBCDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBCSEL) Divide by 1 */
+#define   PM_APBCSEL_APBCDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBCSEL) Divide by 2 */
+#define   PM_APBCSEL_APBCDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBCSEL) Divide by 4 */
+#define   PM_APBCSEL_APBCDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBCSEL) Divide by 8 */
+#define   PM_APBCSEL_APBCDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBCSEL) Divide by 16 */
+#define   PM_APBCSEL_APBCDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBCSEL) Divide by 32 */
+#define   PM_APBCSEL_APBCDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBCSEL) Divide by 64 */
+#define   PM_APBCSEL_APBCDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBCSEL) Divide by 128 */
+#define PM_APBCSEL_APBCDIV_DIV1     (PM_APBCSEL_APBCDIV_DIV1_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV2     (PM_APBCSEL_APBCDIV_DIV2_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV4     (PM_APBCSEL_APBCDIV_DIV4_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV8     (PM_APBCSEL_APBCDIV_DIV8_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV16    (PM_APBCSEL_APBCDIV_DIV16_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV32    (PM_APBCSEL_APBCDIV_DIV32_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV64    (PM_APBCSEL_APBCDIV_DIV64_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV128   (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_MASK             0x07ul       /**< \brief (PM_APBCSEL) MASK Register */
+
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
+    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
+    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
+    uint32_t DSU_:1;           /*!< bit:      3  DSU AHB Clock Mask                 */
+    uint32_t NVMCTRL_:1;       /*!< bit:      4  NVMCTRL AHB Clock Mask             */
+    uint32_t DMAC_:1;          /*!< bit:      5  DMAC AHB Clock Mask                */
+    uint32_t USB_:1;           /*!< bit:      6  USB AHB Clock Mask                 */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_AHBMASK_OFFSET           0x14         /**< \brief (PM_AHBMASK offset) AHB Mask */
+#define PM_AHBMASK_RESETVALUE       0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+
+#define PM_AHBMASK_HPB0_Pos         0            /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
+#define PM_AHBMASK_HPB0             (0x1ul << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB1_Pos         1            /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
+#define PM_AHBMASK_HPB1             (0x1ul << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB2_Pos         2            /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
+#define PM_AHBMASK_HPB2             (0x1ul << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_DSU_Pos          3            /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
+#define PM_AHBMASK_DSU              (0x1ul << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_NVMCTRL_Pos      4            /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
+#define PM_AHBMASK_NVMCTRL          (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_DMAC_Pos         5            /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
+#define PM_AHBMASK_DMAC             (0x1ul << PM_AHBMASK_DMAC_Pos)
+#define PM_AHBMASK_USB_Pos          6            /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
+#define PM_AHBMASK_USB              (0x1ul << PM_AHBMASK_USB_Pos)
+#define PM_AHBMASK_MASK             0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
+
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC0_:1;          /*!< bit:      0  PAC0 APB Clock Enable              */
+    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
+    uint32_t SYSCTRL_:1;       /*!< bit:      2  SYSCTRL APB Clock Enable           */
+    uint32_t GCLK_:1;          /*!< bit:      3  GCLK APB Clock Enable              */
+    uint32_t WDT_:1;           /*!< bit:      4  WDT APB Clock Enable               */
+    uint32_t RTC_:1;           /*!< bit:      5  RTC APB Clock Enable               */
+    uint32_t EIC_:1;           /*!< bit:      6  EIC APB Clock Enable               */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBAMASK_OFFSET          0x18         /**< \brief (PM_APBAMASK offset) APBA Mask */
+#define PM_APBAMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+
+#define PM_APBAMASK_PAC0_Pos        0            /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
+#define PM_APBAMASK_PAC0            (0x1ul << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PM_Pos          1            /**< \brief (PM_APBAMASK) PM APB Clock Enable */
+#define PM_APBAMASK_PM              (0x1ul << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_SYSCTRL_Pos     2            /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
+#define PM_APBAMASK_SYSCTRL         (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_GCLK_Pos        3            /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
+#define PM_APBAMASK_GCLK            (0x1ul << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_WDT_Pos         4            /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
+#define PM_APBAMASK_WDT             (0x1ul << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_RTC_Pos         5            /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
+#define PM_APBAMASK_RTC             (0x1ul << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_EIC_Pos         6            /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
+#define PM_APBAMASK_EIC             (0x1ul << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK            0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
+
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC1_:1;          /*!< bit:      0  PAC1 APB Clock Enable              */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
+    uint32_t PORT_:1;          /*!< bit:      3  PORT APB Clock Enable              */
+    uint32_t DMAC_:1;          /*!< bit:      4  DMAC APB Clock Enable              */
+    uint32_t USB_:1;           /*!< bit:      5  USB APB Clock Enable               */
+    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Clock Enable           */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBMASK_OFFSET          0x1C         /**< \brief (PM_APBBMASK offset) APBB Mask */
+#define PM_APBBMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+
+#define PM_APBBMASK_PAC1_Pos        0            /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
+#define PM_APBBMASK_PAC1            (0x1ul << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_DSU_Pos         1            /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
+#define PM_APBBMASK_DSU             (0x1ul << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_NVMCTRL_Pos     2            /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
+#define PM_APBBMASK_NVMCTRL         (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_PORT_Pos        3            /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
+#define PM_APBBMASK_PORT            (0x1ul << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_DMAC_Pos        4            /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
+#define PM_APBBMASK_DMAC            (0x1ul << PM_APBBMASK_DMAC_Pos)
+#define PM_APBBMASK_USB_Pos         5            /**< \brief (PM_APBBMASK) USB APB Clock Enable */
+#define PM_APBBMASK_USB             (0x1ul << PM_APBBMASK_USB_Pos)
+#define PM_APBBMASK_HMATRIX_Pos     6            /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
+#define PM_APBBMASK_HMATRIX         (0x1ul << PM_APBBMASK_HMATRIX_Pos)
+#define PM_APBBMASK_MASK            0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
+
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC2_:1;          /*!< bit:      0  PAC2 APB Clock Enable              */
+    uint32_t EVSYS_:1;         /*!< bit:      1  EVSYS APB Clock Enable             */
+    uint32_t SERCOM0_:1;       /*!< bit:      2  SERCOM0 APB Clock Enable           */
+    uint32_t SERCOM1_:1;       /*!< bit:      3  SERCOM1 APB Clock Enable           */
+    uint32_t SERCOM2_:1;       /*!< bit:      4  SERCOM2 APB Clock Enable           */
+    uint32_t SERCOM3_:1;       /*!< bit:      5  SERCOM3 APB Clock Enable           */
+    uint32_t SERCOM4_:1;       /*!< bit:      6  SERCOM4 APB Clock Enable           */
+    uint32_t SERCOM5_:1;       /*!< bit:      7  SERCOM5 APB Clock Enable           */
+    uint32_t TCC0_:1;          /*!< bit:      8  TCC0 APB Clock Enable              */
+    uint32_t TCC1_:1;          /*!< bit:      9  TCC1 APB Clock Enable              */
+    uint32_t TCC2_:1;          /*!< bit:     10  TCC2 APB Clock Enable              */
+    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Clock Enable               */
+    uint32_t TC4_:1;           /*!< bit:     12  TC4 APB Clock Enable               */
+    uint32_t TC5_:1;           /*!< bit:     13  TC5 APB Clock Enable               */
+    uint32_t TC6_:1;           /*!< bit:     14  TC6 APB Clock Enable               */
+    uint32_t TC7_:1;           /*!< bit:     15  TC7 APB Clock Enable               */
+    uint32_t ADC_:1;           /*!< bit:     16  ADC APB Clock Enable               */
+    uint32_t AC_:1;            /*!< bit:     17  AC APB Clock Enable                */
+    uint32_t DAC_:1;           /*!< bit:     18  DAC APB Clock Enable               */
+    uint32_t PTC_:1;           /*!< bit:     19  PTC APB Clock Enable               */
+    uint32_t I2S_:1;           /*!< bit:     20  I2S APB Clock Enable               */
+    uint32_t AC1_:1;           /*!< bit:     21  AC1 APB Clock Enable               */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCMASK_OFFSET          0x20         /**< \brief (PM_APBCMASK offset) APBC Mask */
+#define PM_APBCMASK_RESETVALUE      0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+
+#define PM_APBCMASK_PAC2_Pos        0            /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
+#define PM_APBCMASK_PAC2            (0x1ul << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_EVSYS_Pos       1            /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
+#define PM_APBCMASK_EVSYS           (0x1ul << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_SERCOM0_Pos     2            /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
+#define PM_APBCMASK_SERCOM0         (0x1ul << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM1_Pos     3            /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
+#define PM_APBCMASK_SERCOM1         (0x1ul << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM2_Pos     4            /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
+#define PM_APBCMASK_SERCOM2         (0x1ul << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM3_Pos     5            /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
+#define PM_APBCMASK_SERCOM3         (0x1ul << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM4_Pos     6            /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
+#define PM_APBCMASK_SERCOM4         (0x1ul << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM5_Pos     7            /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
+#define PM_APBCMASK_SERCOM5         (0x1ul << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_TCC0_Pos        8            /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
+#define PM_APBCMASK_TCC0            (0x1ul << PM_APBCMASK_TCC0_Pos)
+#define PM_APBCMASK_TCC1_Pos        9            /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
+#define PM_APBCMASK_TCC1            (0x1ul << PM_APBCMASK_TCC1_Pos)
+#define PM_APBCMASK_TCC2_Pos        10           /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
+#define PM_APBCMASK_TCC2            (0x1ul << PM_APBCMASK_TCC2_Pos)
+#define PM_APBCMASK_TC3_Pos         11           /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
+#define PM_APBCMASK_TC3             (0x1ul << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC4_Pos         12           /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
+#define PM_APBCMASK_TC4             (0x1ul << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC5_Pos         13           /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
+#define PM_APBCMASK_TC5             (0x1ul << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC6_Pos         14           /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
+#define PM_APBCMASK_TC6             (0x1ul << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC7_Pos         15           /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
+#define PM_APBCMASK_TC7             (0x1ul << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_ADC_Pos         16           /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
+#define PM_APBCMASK_ADC             (0x1ul << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_AC_Pos          17           /**< \brief (PM_APBCMASK) AC APB Clock Enable */
+#define PM_APBCMASK_AC              (0x1ul << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_DAC_Pos         18           /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
+#define PM_APBCMASK_DAC             (0x1ul << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_PTC_Pos         19           /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
+#define PM_APBCMASK_PTC             (0x1ul << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_I2S_Pos         20           /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
+#define PM_APBCMASK_I2S             (0x1ul << PM_APBCMASK_I2S_Pos)
+#define PM_APBCMASK_AC1_Pos         21           /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
+#define PM_APBCMASK_AC1             (0x1ul << PM_APBCMASK_AC1_Pos)
+#define PM_APBCMASK_MASK            0x003FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET          0x34         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE      0x00ul       /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_CKRDY_Pos       0            /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
+#define PM_INTENCLR_CKRDY           (0x1ul << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK            0x01ul       /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET          0x35         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE      0x00ul       /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_CKRDY_Pos       0            /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
+#define PM_INTENSET_CKRDY           (0x1ul << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK            0x01ul       /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET           0x36         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE       0x00ul       /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_CKRDY_Pos        0            /**< \brief (PM_INTFLAG) Clock Ready */
+#define PM_INTFLAG_CKRDY            (0x1ul << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK             0x01ul       /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/   8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
+    uint8_t  BOD12:1;          /*!< bit:      1  Brown Out 12 Detector Reset        */
+    uint8_t  BOD33:1;          /*!< bit:      2  Brown Out 33 Detector Reset        */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
+    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
+    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_RCAUSE_OFFSET            0x38         /**< \brief (PM_RCAUSE offset) Reset Cause */
+#define PM_RCAUSE_RESETVALUE        0x01ul       /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+
+#define PM_RCAUSE_POR_Pos           0            /**< \brief (PM_RCAUSE) Power On Reset */
+#define PM_RCAUSE_POR               (0x1ul << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_BOD12_Pos         1            /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
+#define PM_RCAUSE_BOD12             (0x1ul << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD33_Pos         2            /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
+#define PM_RCAUSE_BOD33             (0x1ul << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_EXT_Pos           4            /**< \brief (PM_RCAUSE) External Reset */
+#define PM_RCAUSE_EXT               (0x1ul << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_WDT_Pos           5            /**< \brief (PM_RCAUSE) Watchdog Reset */
+#define PM_RCAUSE_WDT               (0x1ul << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_SYST_Pos          6            /**< \brief (PM_RCAUSE) System Reset Request */
+#define PM_RCAUSE_SYST              (0x1ul << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK              0x77ul       /**< \brief (PM_RCAUSE) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PM_CTRL_Type              CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __IO PM_SLEEP_Type             SLEEP;       /**< \brief Offset: 0x01 (R/W  8) Sleep Mode */
+  __IO PM_EXTCTRL_Type           EXTCTRL;     /**< \brief Offset: 0x02 (R/W  8) External Reset Controller */
+       RoReg8                    Reserved1[0x5];
+  __IO PM_CPUSEL_Type            CPUSEL;      /**< \brief Offset: 0x08 (R/W  8) CPU Clock Select */
+  __IO PM_APBASEL_Type           APBASEL;     /**< \brief Offset: 0x09 (R/W  8) APBA Clock Select */
+  __IO PM_APBBSEL_Type           APBBSEL;     /**< \brief Offset: 0x0A (R/W  8) APBB Clock Select */
+  __IO PM_APBCSEL_Type           APBCSEL;     /**< \brief Offset: 0x0B (R/W  8) APBC Clock Select */
+       RoReg8                    Reserved2[0x8];
+  __IO PM_AHBMASK_Type           AHBMASK;     /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+  __IO PM_APBAMASK_Type          APBAMASK;    /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+  __IO PM_APBBMASK_Type          APBBMASK;    /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+  __IO PM_APBCMASK_Type          APBCMASK;    /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+       RoReg8                    Reserved3[0x10];
+  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x34 (R/W  8) Interrupt Enable Clear */
+  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x35 (R/W  8) Interrupt Enable Set */
+  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x36 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __I  PM_RCAUSE_Type            RCAUSE;      /**< \brief Offset: 0x38 (R/   8) Reset Cause */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PM_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/port.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/port.h
new file mode 100644
index 0000000000..6b4ebf1ee7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/port.h
@@ -0,0 +1,394 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_COMPONENT_
+#define _SAMD21_PORT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT                    0x100
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIR:32;           /*!< bit:  0..31  Port Data Direction                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET             0x00         /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE         0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos            0            /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk            (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value)         (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
+#define PORT_DIR_MASK               0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRCLR:32;        /*!< bit:  0..31  Port Data Direction Clear          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET          0x04         /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos      0            /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk      (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value)   (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRSET:32;        /*!< bit:  0..31  Port Data Direction Set            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET          0x08         /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos      0            /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk      (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value)   (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRTGL:32;        /*!< bit:  0..31  Port Data Direction Toggle         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET          0x0C         /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos      0            /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk      (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value)   (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUT:32;           /*!< bit:  0..31  Port Data Output Value             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET             0x10         /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE         0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos            0            /**< \brief (PORT_OUT) Port Data Output Value */
+#define PORT_OUT_OUT_Msk            (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value)         (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
+#define PORT_OUT_MASK               0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTCLR:32;        /*!< bit:  0..31  Port Data Output Value Clear       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET          0x14         /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos      0            /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk      (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value)   (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTSET:32;        /*!< bit:  0..31  Port Data Output Value Set         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET          0x18         /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos      0            /**< \brief (PORT_OUTSET) Port Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk      (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value)   (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTTGL:32;        /*!< bit:  0..31  Port Data Output Value Toggle      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET          0x1C         /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos      0            /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk      (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value)   (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/  32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t IN:32;            /*!< bit:  0..31  Port Data Input Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET              0x20         /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE          0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos              0            /**< \brief (PORT_IN) Port Data Input Value */
+#define PORT_IN_IN_Msk              (0xFFFFFFFFul << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value)           (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
+#define PORT_IN_MASK                0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SAMPLING:32;      /*!< bit:  0..31  Input Sampling Mode                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET            0x24         /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE        0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos      0            /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk      (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value)   (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_MASK              0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PINMASK:16;       /*!< bit:  0..15  Pin Mask for Multiple Pin Configuration */
+    uint32_t PMUXEN:1;         /*!< bit:     16  Peripheral Multiplexer Enable      */
+    uint32_t INEN:1;           /*!< bit:     17  Input Enable                       */
+    uint32_t PULLEN:1;         /*!< bit:     18  Pull Enable                        */
+    uint32_t :3;               /*!< bit: 19..21  Reserved                           */
+    uint32_t DRVSTR:1;         /*!< bit:     22  Output Driver Strength Selection   */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PMUX:4;           /*!< bit: 24..27  Peripheral Multiplexing            */
+    uint32_t WRPMUX:1;         /*!< bit:     28  Write PMUX                         */
+    uint32_t :1;               /*!< bit:     29  Reserved                           */
+    uint32_t WRPINCFG:1;       /*!< bit:     30  Write PINCFG                       */
+    uint32_t HWSEL:1;          /*!< bit:     31  Half-Word Select                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET        0x28         /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE    0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos   0            /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk   (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos    16           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN        (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos      17           /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN          (0x1ul << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos    18           /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN        (0x1ul << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos    22           /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR        (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos      24           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk      (0xFul << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value)   (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos    28           /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX        (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos  30           /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG      (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos     31           /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL         (0x1ul << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK          0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W  8) GROUP Peripheral Multiplexing n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXE:4;          /*!< bit:  0.. 3  Peripheral Multiplexing Even       */
+    uint8_t  PMUXO:4;          /*!< bit:  4.. 7  Peripheral Multiplexing Odd        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET            0x30         /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
+#define PORT_PMUX_RESETVALUE        0x00ul       /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
+
+#define PORT_PMUX_PMUXE_Pos         0            /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
+#define PORT_PMUX_PMUXE_Msk         (0xFul << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value)      (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define   PORT_PMUX_PMUXE_A_Val           0x0ul  /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define   PORT_PMUX_PMUXE_B_Val           0x1ul  /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define   PORT_PMUX_PMUXE_C_Val           0x2ul  /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define   PORT_PMUX_PMUXE_D_Val           0x3ul  /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define   PORT_PMUX_PMUXE_E_Val           0x4ul  /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define   PORT_PMUX_PMUXE_F_Val           0x5ul  /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define   PORT_PMUX_PMUXE_G_Val           0x6ul  /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define   PORT_PMUX_PMUXE_H_Val           0x7ul  /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXE_A           (PORT_PMUX_PMUXE_A_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_B           (PORT_PMUX_PMUXE_B_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_C           (PORT_PMUX_PMUXE_C_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_D           (PORT_PMUX_PMUXE_D_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_E           (PORT_PMUX_PMUXE_E_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_F           (PORT_PMUX_PMUXE_F_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_G           (PORT_PMUX_PMUXE_G_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_H           (PORT_PMUX_PMUXE_H_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXO_Pos         4            /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
+#define PORT_PMUX_PMUXO_Msk         (0xFul << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value)      (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define   PORT_PMUX_PMUXO_A_Val           0x0ul  /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define   PORT_PMUX_PMUXO_B_Val           0x1ul  /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define   PORT_PMUX_PMUXO_C_Val           0x2ul  /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define   PORT_PMUX_PMUXO_D_Val           0x3ul  /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define   PORT_PMUX_PMUXO_E_Val           0x4ul  /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define   PORT_PMUX_PMUXO_F_Val           0x5ul  /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define   PORT_PMUX_PMUXO_G_Val           0x6ul  /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define   PORT_PMUX_PMUXO_H_Val           0x7ul  /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXO_A           (PORT_PMUX_PMUXO_A_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_B           (PORT_PMUX_PMUXO_B_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_C           (PORT_PMUX_PMUXO_C_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_D           (PORT_PMUX_PMUXO_D_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_E           (PORT_PMUX_PMUXO_E_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_F           (PORT_PMUX_PMUXO_F_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_G           (PORT_PMUX_PMUXO_G_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_H           (PORT_PMUX_PMUXO_H_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_MASK              0xFFul       /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W  8) GROUP Pin Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXEN:1;         /*!< bit:      0  Peripheral Multiplexer Enable      */
+    uint8_t  INEN:1;           /*!< bit:      1  Input Enable                       */
+    uint8_t  PULLEN:1;         /*!< bit:      2  Pull Enable                        */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  DRVSTR:1;         /*!< bit:      6  Output Driver Strength Selection   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET          0x40         /**< \brief (PORT_PINCFG offset) Pin Configuration n */
+#define PORT_PINCFG_RESETVALUE      0x00ul       /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
+
+#define PORT_PINCFG_PMUXEN_Pos      0            /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN          (0x1ul << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos        1            /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN            (0x1ul << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos      2            /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN          (0x1ul << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos      6            /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR          (0x1ul << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK            0x47ul       /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PORT_DIR_Type             DIR;         /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+  __IO PORT_DIRCLR_Type          DIRCLR;      /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+  __IO PORT_DIRSET_Type          DIRSET;      /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+  __IO PORT_DIRTGL_Type          DIRTGL;      /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+  __IO PORT_OUT_Type             OUT;         /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+  __IO PORT_OUTCLR_Type          OUTCLR;      /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+  __IO PORT_OUTSET_Type          OUTSET;      /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+  __IO PORT_OUTTGL_Type          OUTTGL;      /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+  __I  PORT_IN_Type              IN;          /**< \brief Offset: 0x20 (R/  32) Data Input Value */
+  __IO PORT_CTRL_Type            CTRL;        /**< \brief Offset: 0x24 (R/W 32) Control */
+  __O  PORT_WRCONFIG_Type        WRCONFIG;    /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+       RoReg8                    Reserved1[0x4];
+  __IO PORT_PMUX_Type            PMUX[16];    /**< \brief Offset: 0x30 (R/W  8) Peripheral Multiplexing n */
+  __IO PORT_PINCFG_Type          PINCFG[32];  /**< \brief Offset: 0x40 (R/W  8) Pin Configuration n */
+       RoReg8                    Reserved2[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       PortGroup                 Group[2];    /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PORT_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/rtc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/rtc.h
new file mode 100644
index 0000000000..3f9f034b0e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/rtc.h
@@ -0,0 +1,1068 @@
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_COMPONENT_
+#define _SAMD21_RTC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2202
+#define REV_RTC                     0x101
+
+/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
+#define RTC_MODE0_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
+
+#define RTC_MODE0_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE0_CTRL) Software Reset */
+#define RTC_MODE0_CTRL_SWRST        (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
+#define RTC_MODE0_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE0_CTRL) Enable */
+#define RTC_MODE0_CTRL_ENABLE       (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
+#define RTC_MODE0_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE0_CTRL) Operating Mode */
+#define RTC_MODE0_CTRL_MODE_Msk     (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE(value)  (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
+#define   RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE0_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_CLOCK   (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE0_CTRL) Clear on Match */
+#define RTC_MODE0_CTRL_MATCHCLR     (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE0_CTRL) Prescaler */
+#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
+#define   RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_MASK         0x0F8Ful     /**< \brief (RTC_MODE0_CTRL) MASK Register */
+
+/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
+#define RTC_MODE1_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
+
+#define RTC_MODE1_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE1_CTRL) Software Reset */
+#define RTC_MODE1_CTRL_SWRST        (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
+#define RTC_MODE1_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE1_CTRL) Enable */
+#define RTC_MODE1_CTRL_ENABLE       (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
+#define RTC_MODE1_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE1_CTRL) Operating Mode */
+#define RTC_MODE1_CTRL_MODE_Msk     (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE(value)  (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
+#define   RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE1_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_CLOCK   (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE1_CTRL) Prescaler */
+#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
+#define   RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_MASK         0x0F0Ful     /**< \brief (RTC_MODE1_CTRL) MASK Register */
+
+/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint16_t CLKREP:1;         /*!< bit:      6  Clock Representation               */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
+#define RTC_MODE2_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
+
+#define RTC_MODE2_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE2_CTRL) Software Reset */
+#define RTC_MODE2_CTRL_SWRST        (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
+#define RTC_MODE2_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE2_CTRL) Enable */
+#define RTC_MODE2_CTRL_ENABLE       (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
+#define RTC_MODE2_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE2_CTRL) Operating Mode */
+#define RTC_MODE2_CTRL_MODE_Msk     (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE(value)  (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
+#define   RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE2_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_CLOCK   (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_CLKREP_Pos   6            /**< \brief (RTC_MODE2_CTRL) Clock Representation */
+#define RTC_MODE2_CTRL_CLKREP       (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
+#define RTC_MODE2_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE2_CTRL) Clear on Match */
+#define RTC_MODE2_CTRL_MATCHCLR     (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE2_CTRL) Prescaler */
+#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
+#define   RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_MASK         0x0FCFul     /**< \brief (RTC_MODE2_CTRL) MASK Register */
+
+/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ADDR:6;           /*!< bit:  0.. 5  Address                            */
+    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
+    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
+    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_READREQ_OFFSET          0x02         /**< \brief (RTC_READREQ offset) Read Request */
+#define RTC_READREQ_RESETVALUE      0x0010ul     /**< \brief (RTC_READREQ reset_value) Read Request */
+
+#define RTC_READREQ_ADDR_Pos        0            /**< \brief (RTC_READREQ) Address */
+#define RTC_READREQ_ADDR_Msk        (0x3Ful << RTC_READREQ_ADDR_Pos)
+#define RTC_READREQ_ADDR(value)     (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
+#define RTC_READREQ_RCONT_Pos       14           /**< \brief (RTC_READREQ) Read Continuously */
+#define RTC_READREQ_RCONT           (0x1ul << RTC_READREQ_RCONT_Pos)
+#define RTC_READREQ_RREQ_Pos        15           /**< \brief (RTC_READREQ) Read Request */
+#define RTC_READREQ_RREQ            (0x1ul << RTC_READREQ_RREQ_Pos)
+#define RTC_READREQ_MASK            0xC03Ful     /**< \brief (RTC_READREQ) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t CMPEO:1;          /*!< bit:      8  Compare x Event Output Enable      */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0     (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1     (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2     (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3     (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4     (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5     (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6     (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7     (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0     (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk  (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
+#define RTC_MODE0_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO      (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_MASK       0x81FFul     /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint16_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
+    uint16_t :5;               /*!< bit: 10..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t CMPEO:2;          /*!< bit:  8.. 9  Compare x Event Output Enable      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0     (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1     (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2     (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3     (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4     (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5     (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6     (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7     (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0     (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1     (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk  (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
+#define RTC_MODE1_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO      (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_MASK       0x83FFul     /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t ALARMEO0:1;       /*!< bit:      8  Alarm 0 Event Output Enable        */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t ALARMEO:1;        /*!< bit:      8  Alarm x Event Output Enable        */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0     (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1     (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2     (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3     (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4     (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5     (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6     (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7     (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0   (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
+#define RTC_MODE2_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO      (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_MASK       0x81FFul     /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0     (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk  (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
+#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF      (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK     0xC1ul       /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0     (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1     (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk  (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
+#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF      (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK     0xC3ul       /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0   (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
+#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF      (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK     0xC1ul       /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0     (1 << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk  (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
+#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENSET_SYNCRDY  (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF      (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK     0xC1ul       /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0     (1 << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1     (1 << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk  (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
+#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENSET_SYNCRDY  (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF      (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK     0xC3ul       /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0   (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
+#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENSET_SYNCRDY  (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF      (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK     0xC1ul       /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
+    __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  CMP:1;            /*!< bit:      0  Compare x                          */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0      (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk   (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
+#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
+#define RTC_MODE0_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF       (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK      0xC1ul       /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
+    __I uint8_t  CMP1:1;           /*!< bit:      1  Compare 1                          */
+    __I uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x                          */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0      (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos  1            /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1      (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk   (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
+#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
+#define RTC_MODE1_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF       (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK      0xC3ul       /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0                            */
+    __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  ALARM:1;          /*!< bit:      0  Alarm x                            */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0    (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
+#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
+#define RTC_MODE2_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF       (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK      0xC1ul       /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W  8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_STATUS_OFFSET           0x0A         /**< \brief (RTC_STATUS offset) Status */
+#define RTC_STATUS_RESETVALUE       0x00ul       /**< \brief (RTC_STATUS reset_value) Status */
+
+#define RTC_STATUS_SYNCBUSY_Pos     7            /**< \brief (RTC_STATUS) Synchronization Busy */
+#define RTC_STATUS_SYNCBUSY         (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
+#define RTC_STATUS_MASK             0x80ul       /**< \brief (RTC_STATUS) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET          0x0B         /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN          (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK            0x01ul       /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W  8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:7;          /*!< bit:  0.. 6  Correction Value                   */
+    uint8_t  SIGN:1;           /*!< bit:      7  Correction Sign                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET         0x0C         /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE     0x00ul       /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos      0            /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk      (0x7Ful << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value)   (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
+#define RTC_FREQCORR_SIGN_Pos       7            /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN           (0x1ul << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK           0xFFul       /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk   (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
+#define RTC_MODE0_COUNT_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE  0x0000ul     /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk   (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
+#define RTC_MODE1_COUNT_MASK        0xFFFFul     /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET      0x10         /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos  0            /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk  (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
+#define RTC_MODE2_CLOCK_MINUTE_Pos  6            /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk  (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
+#define RTC_MODE2_CLOCK_HOUR_Pos    12           /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk    (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
+#define   RTC_MODE2_CLOCK_HOUR_AM_Val     0x0ul  /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
+#define   RTC_MODE2_CLOCK_HOUR_PM_Val     0x10ul  /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
+#define RTC_MODE2_CLOCK_HOUR_AM     (RTC_MODE2_CLOCK_HOUR_AM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR_PM     (RTC_MODE2_CLOCK_HOUR_PM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos     17           /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk     (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value)  (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
+#define RTC_MODE2_CLOCK_MONTH_Pos   22           /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk   (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
+#define RTC_MODE2_CLOCK_YEAR_Pos    26           /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk    (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
+#define RTC_MODE2_CLOCK_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER:16;           /*!< bit:  0..15  Counter Period                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET        0x14         /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE    0x0000ul     /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos       0            /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk       (0xFFFFul << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value)    (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
+#define RTC_MODE1_PER_MASK          0xFFFFul     /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COMP:32;          /*!< bit:  0..31  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET       0x18         /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE   0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos     0            /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk     (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value)  (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
+#define RTC_MODE0_COMP_MASK         0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMP:16;          /*!< bit:  0..15  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET       0x18         /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos     0            /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk     (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value)  (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
+#define RTC_MODE1_COMP_MASK         0xFFFFul     /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET      0x18         /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos  0            /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk  (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
+#define RTC_MODE2_ALARM_MINUTE_Pos  6            /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk  (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
+#define RTC_MODE2_ALARM_HOUR_Pos    12           /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk    (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
+#define   RTC_MODE2_ALARM_HOUR_AM_Val     0x0ul  /**< \brief (RTC_MODE2_ALARM) Morning hour */
+#define   RTC_MODE2_ALARM_HOUR_PM_Val     0x10ul  /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
+#define RTC_MODE2_ALARM_HOUR_AM     (RTC_MODE2_ALARM_HOUR_AM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR_PM     (RTC_MODE2_ALARM_HOUR_PM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_DAY_Pos     17           /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk     (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value)  (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
+#define RTC_MODE2_ALARM_MONTH_Pos   22           /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk   (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
+#define RTC_MODE2_ALARM_YEAR_Pos    26           /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk    (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
+#define RTC_MODE2_ALARM_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W  8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SEL:3;            /*!< bit:  0.. 2  Alarm Mask Selection               */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET       0x1C         /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE   0x00ul       /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos      0            /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk      (0x7ul << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value)   (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
+#define   RTC_MODE2_MASK_SEL_OFF_Val      0x0ul  /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define   RTC_MODE2_MASK_SEL_SS_Val       0x1ul  /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define   RTC_MODE2_MASK_SEL_MMSS_Val     0x2ul  /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define   RTC_MODE2_MASK_SEL_HHMMSS_Val   0x3ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF      (RTC_MODE2_MASK_SEL_OFF_Val    << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS       (RTC_MODE2_MASK_SEL_SS_Val     << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS     (RTC_MODE2_MASK_SEL_MMSS_Val   << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS   (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK         0x07ul       /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO RTC_MODE2_ALARM_Type      ALARM;       /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+  __IO RTC_MODE2_MASK_Type       MASK;        /**< \brief Offset: 0x04 (R/W  8) MODE2_ALARM Alarm n Mask */
+       RoReg8                    Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+  __IO RTC_MODE0_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE0_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+  __IO RTC_MODE0_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE0 Interrupt Enable Clear */
+  __IO RTC_MODE0_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE0 Interrupt Enable Set */
+  __IO RTC_MODE0_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE0 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE0_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO RTC_MODE0_COMP_Type       COMP[1];     /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+  __IO RTC_MODE1_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE1_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+  __IO RTC_MODE1_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE1 Interrupt Enable Clear */
+  __IO RTC_MODE1_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE1 Interrupt Enable Set */
+  __IO RTC_MODE1_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE1 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE1_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+       RoReg8                    Reserved3[0x2];
+  __IO RTC_MODE1_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+       RoReg8                    Reserved4[0x2];
+  __IO RTC_MODE1_COMP_Type       COMP[2];     /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+  __IO RTC_MODE2_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE2_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+  __IO RTC_MODE2_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE2 Interrupt Enable Clear */
+  __IO RTC_MODE2_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE2 Interrupt Enable Set */
+  __IO RTC_MODE2_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE2 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE2_CLOCK_Type      CLOCK;       /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+       RoReg8                    Reserved3[0x4];
+       RtcMode2Alarm             Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       RtcMode0                  MODE0;       /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+       RtcMode1                  MODE1;       /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+       RtcMode2                  MODE2;       /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_RTC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sercom.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sercom.h
new file mode 100644
index 0000000000..8667a48b43
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sercom.h
@@ -0,0 +1,1508 @@
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM_COMPONENT_
+#define _SAMD21_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM                  0x220
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t MEXTTOEN:1;       /*!< bit:     22  Master SCL Low Extend Timeout      */
+    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
+    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
+    uint32_t INACTOUT:2;       /*!< bit: 28..29  Inactive Time-Out                  */
+    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST     (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE    (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk  (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
+#define   SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY  (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT    (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22           /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN  (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN  (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM     (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28           /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK      0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
+    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
+    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
+    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST     (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE    (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk  (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
+#define   SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY  (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT    (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN  (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM     (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK      0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t DOPO:2;           /*!< bit: 16..17  Data Out Pinout                    */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t DIPO:2;           /*!< bit: 20..21  Data In Pinout                     */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CPHA:1;           /*!< bit:     28  Clock Phase                        */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET     0x00         /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos  0            /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST      (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE     (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos   2            /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk   (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
+#define   SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
+#define   SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
+#define   SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY   (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos   8            /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON       (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos   16           /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk   (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
+#define SERCOM_SPI_CTRLA_DIPO_Pos   20           /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk   (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define SERCOM_SPI_CTRLA_FORM_Pos   24           /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk   (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
+#define SERCOM_SPI_CTRLA_CPHA_Pos   28           /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA       (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos   29           /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL       (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos   30           /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD       (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK       0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :4;               /*!< bit:  9..12  Reserved                           */
+    uint32_t SAMPR:3;          /*!< bit: 13..15  Sample                             */
+    uint32_t TXPO:2;           /*!< bit: 16..17  Transmit Data Pinout               */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t RXPO:2;           /*!< bit: 20..21  Receive Data Pinout                */
+    uint32_t SAMPA:2;          /*!< bit: 22..23  Sample Adjustment                  */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CMODE:1;          /*!< bit:     28  Communication Mode                 */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET   0x00         /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST    (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE   (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2            /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
+#define   SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
+#define   SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
+#define   SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8            /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON     (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13           /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16           /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20           /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22           /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
+#define SERCOM_USART_CTRLA_FORM_Pos 24           /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28           /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE    (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29           /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL     (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30           /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD     (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK     0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t QCEN:1;           /*!< bit:      9  Quick Command Enable               */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN      (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos  9            /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN      (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk   (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT    (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK      0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t GCMD:1;           /*!< bit:      9  PMBus Group Command                */
+    uint32_t AACKEN:1;         /*!< bit:     10  Automatic Address Acknowledge      */
+    uint32_t :3;               /*!< bit: 11..13  Reserved                           */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN      (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos  9            /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD      (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10           /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN    (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14           /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
+#define SERCOM_I2CS_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk   (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT    (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK      0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t PLOADEN:1;        /*!< bit:      6  Data Preload Enable                */
+    uint32_t :2;               /*!< bit:  7.. 8  Reserved                           */
+    uint32_t SSDE:1;           /*!< bit:      9  Slave Select Low Detect Enable     */
+    uint32_t :3;               /*!< bit: 10..12  Reserved                           */
+    uint32_t MSSEN:1;          /*!< bit:     13  Master Slave Select Enable         */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET     0x04         /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6            /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN    (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos   9            /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE       (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos  13           /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN      (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos  14           /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk  (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
+#define SERCOM_SPI_CTRLB_RXEN_Pos   17           /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN       (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK       0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t SBMODE:1;         /*!< bit:      6  Stop Bit Mode                      */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t COLDEN:1;         /*!< bit:      8  Collision Detection Enable         */
+    uint32_t SFDE:1;           /*!< bit:      9  Start of Frame Detection Enable    */
+    uint32_t ENC:1;            /*!< bit:     10  Encoding Format                    */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t PMODE:1;          /*!< bit:     13  Parity Mode                        */
+    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
+    uint32_t TXEN:1;           /*!< bit:     16  Transmitter Enable                 */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET   0x04         /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6            /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE   (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8            /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN   (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9            /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE     (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos  10           /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC      (0x1ul << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13           /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE    (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16           /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN     (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17           /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN     (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_MASK     0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
+    uint32_t BAUDLOW:8;        /*!< bit:  8..15  Baud Rate Value Low                */
+    uint32_t HSBAUD:8;         /*!< bit: 16..23  High Speed Baud Rate Value         */
+    uint32_t HSBAUDLOW:8;      /*!< bit: 24..31  High Speed Baud Rate Value Low     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET     0x0C         /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos   0            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk   (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_MASK       0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W  8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET      0x0C         /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE  0x00ul       /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos    0            /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk    (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
+#define SERCOM_SPI_BAUD_MASK        0xFFul       /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // FRAC mode
+    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
+    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
+  } FRAC;                      /*!< Structure used for FRAC                         */
+  struct { // FRACFP mode
+    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
+    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
+  } FRACFP;                    /*!< Structure used for FRACFP                       */
+  struct { // USARTFP mode
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
+  } USARTFP;                   /*!< Structure used for USARTFP                      */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET    0x0C         /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos  0            /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk  (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
+#define SERCOM_USART_BAUD_MASK      0xFFFFul     /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W  8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RXPL:8;           /*!< bit:  0.. 7  Receive Pulse Length               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET    0x0E         /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos  0            /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk  (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
+#define SERCOM_USART_RXPL_MASK      0xFFul       /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Disable    */
+    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Disable     */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB     (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB     (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR  (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK   0x83ul       /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Disable    */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Disable    */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Disable             */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC   (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY   (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR  (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK   0x87ul       /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
+    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Disable */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET  0x14         /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE     (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC     (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC     (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL     (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR   (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK    0x8Ful       /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Disable    */
+    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Disable */
+    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE   (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC   (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC   (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS   (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK  0xBFul       /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Enable     */
+    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Enable      */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB     (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB     (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR  (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK   0x83ul       /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Enable              */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC   (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY   (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR  (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK   0x87ul       /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W  8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Enable  */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET  0x16         /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE     (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC     (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC     (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL     (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR   (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK    0x8Ful       /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W  8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Enable     */
+    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Enable */
+    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Enable    */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE   (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC   (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC   (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS   (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK  0xBFul       /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt            */
+    __I uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt             */
+    __I uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos  0            /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB      (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos  1            /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB      (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR   (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK    0x83ul       /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt            */
+    __I uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt            */
+    __I uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt                     */
+    __I uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC    (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH  (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY    (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR   (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK    0x87ul       /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
+    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
+    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
+    __I uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Flag    */
+    __I uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET   0x18         /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos  0            /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE      (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos  1            /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC      (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos  2            /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC      (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos  3            /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL      (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR    (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK     0x8Ful       /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
+    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
+    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
+    __I uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt            */
+    __I uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt */
+    __I uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt           */
+    __I uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18         /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0            /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE    (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1            /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC    (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2            /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC    (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3            /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS    (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC  (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK  (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR  (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK   0xBFul       /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t ARBLOST:1;        /*!< bit:      1  Arbitration Lost                   */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t BUSSTATE:2;       /*!< bit:  4.. 5  Bus State                          */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t MEXTTOUT:1;       /*!< bit:      8  Master SCL Low Extend Timeout      */
+    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
+    uint16_t LENERR:1;         /*!< bit:     10  Length Error                       */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR   (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1            /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST  (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK   (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4            /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT  (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD  (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8            /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10           /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR   (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK     0x07F7ul     /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t COLL:1;           /*!< bit:      1  Transmit Collision                 */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t DIR:1;            /*!< bit:      3  Read/Write Direction               */
+    uint16_t SR:1;             /*!< bit:      4  Repeated Start                     */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t :1;               /*!< bit:      8  Reserved                           */
+    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
+    uint16_t HS:1;             /*!< bit:     10  High Speed                         */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR   (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1            /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL     (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK   (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos  3            /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR      (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos   4            /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR       (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT  (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD  (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos   10           /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS       (0x1ul << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_MASK     0x06DFul     /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t :13;              /*!< bit:  3..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET    0x1A         /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF    (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_MASK      0x0004ul     /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PERR:1;           /*!< bit:      0  Parity Error                       */
+    uint16_t FERR:1;           /*!< bit:      1  Frame Error                        */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t CTS:1;            /*!< bit:      3  Clear To Send                      */
+    uint16_t ISF:1;            /*!< bit:      4  Inconsistent Sync Field            */
+    uint16_t COLL:1;           /*!< bit:      5  Collision Detected                 */
+    uint16_t :10;              /*!< bit:  6..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET  0x1A         /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0            /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR    (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1            /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR    (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF  (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3            /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS     (0x1ul << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4            /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF     (0x1ul << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5            /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL    (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_MASK    0x003Ful     /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CM I2CM Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t SYSOP:1;          /*!< bit:      2  System Operation Synchronization Busy */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST  (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2            /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP  (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK   0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CS I2CS Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST  (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK   0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) SPI SPI Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET  0x1C         /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST   (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE  (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB   (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK    0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) USART USART Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK  0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:11;          /*!< bit:  0..10  Address Value                      */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t LENEN:1;          /*!< bit:     13  Length Enable                      */
+    uint32_t HS:1;             /*!< bit:     14  High Speed Mode                    */
+    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
+    uint32_t LEN:8;            /*!< bit: 16..23  Length                             */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos   0            /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk   (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
+#define SERCOM_I2CM_ADDR_LENEN_Pos  13           /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN      (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos     14           /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS         (0x1ul << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN   (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos    16           /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk    (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
+#define SERCOM_I2CM_ADDR_MASK       0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GENCEN:1;         /*!< bit:      0  General Call Address Enable        */
+    uint32_t ADDR:10;          /*!< bit:  1..10  Address Value                      */
+    uint32_t :4;               /*!< bit: 11..14  Reserved                           */
+    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t ADDRMASK:10;      /*!< bit: 17..26  Address Mask                       */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0            /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN     (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos   1            /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk   (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN   (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17           /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
+#define SERCOM_I2CS_ADDR_MASK       0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:8;           /*!< bit:  0.. 7  Address Value                      */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t ADDRMASK:8;       /*!< bit: 16..23  Address Mask                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET      0x24         /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE  0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos    0            /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk    (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16           /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPI_ADDR_MASK        0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W  8) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk   (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
+#define SERCOM_I2CM_DATA_MASK       0xFFul       /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W  8) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk   (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
+#define SERCOM_I2CS_DATA_MASK       0xFFul       /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:9;           /*!< bit:  0.. 8  Data Value                         */
+    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET      0x28         /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE  0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos    0            /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk    (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
+#define SERCOM_SPI_DATA_MASK        0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:9;           /*!< bit:  0.. 8  Data Value                         */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET    0x28         /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos  0            /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk  (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
+#define SERCOM_USART_DATA_MASK      0x01FFul     /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET  0x30         /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK    0x01ul       /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET   0x30         /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP  (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK     0x01ul       /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30         /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK   0x01ul       /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+  __IO SERCOM_I2CM_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+  __IO SERCOM_I2CM_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_I2CM_BAUD_Type     BAUD;        /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+       RoReg8                    Reserved2[0x4];
+  __IO SERCOM_I2CM_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_I2CM_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_I2CM_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_I2CM_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+  __I  SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CM Synchronization Busy */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_I2CM_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+  __IO SERCOM_I2CM_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W  8) I2CM Data */
+       RoReg8                    Reserved7[0x7];
+  __IO SERCOM_I2CM_DBGCTRL_Type  DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+  __IO SERCOM_I2CS_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+  __IO SERCOM_I2CS_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+       RoReg8                    Reserved1[0xC];
+  __IO SERCOM_I2CS_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_I2CS_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_I2CS_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_I2CS_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+  __I  SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CS Synchronization Busy */
+       RoReg8                    Reserved5[0x4];
+  __IO SERCOM_I2CS_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+  __IO SERCOM_I2CS_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W  8) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+  __IO SERCOM_SPI_CTRLA_Type     CTRLA;       /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+  __IO SERCOM_SPI_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_SPI_BAUD_Type      BAUD;        /**< \brief Offset: 0x0C (R/W  8) SPI Baud Rate */
+       RoReg8                    Reserved2[0x7];
+  __IO SERCOM_SPI_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) SPI Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_SPI_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x16 (R/W  8) SPI Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_SPI_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) SPI Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_SPI_STATUS_Type    STATUS;      /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+  __I  SERCOM_SPI_SYNCBUSY_Type  SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) SPI Synchronization Busy */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_SPI_ADDR_Type      ADDR;        /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+  __IO SERCOM_SPI_DATA_Type      DATA;        /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+       RoReg8                    Reserved7[0x4];
+  __IO SERCOM_SPI_DBGCTRL_Type   DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+  __IO SERCOM_USART_CTRLA_Type   CTRLA;       /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+  __IO SERCOM_USART_CTRLB_Type   CTRLB;       /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_USART_BAUD_Type    BAUD;        /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+  __IO SERCOM_USART_RXPL_Type    RXPL;        /**< \brief Offset: 0x0E (R/W  8) USART Receive Pulse Length */
+       RoReg8                    Reserved2[0x5];
+  __IO SERCOM_USART_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) USART Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_USART_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) USART Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_USART_INTFLAG_Type INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) USART Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_USART_STATUS_Type  STATUS;      /**< \brief Offset: 0x1A (R/W 16) USART Status */
+  __I  SERCOM_USART_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) USART Synchronization Busy */
+       RoReg8                    Reserved6[0x8];
+  __IO SERCOM_USART_DATA_Type    DATA;        /**< \brief Offset: 0x28 (R/W 16) USART Data */
+       RoReg8                    Reserved7[0x6];
+  __IO SERCOM_USART_DBGCTRL_Type DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       SercomI2cm                I2CM;        /**< \brief Offset: 0x00 I2C Master Mode */
+       SercomI2cs                I2CS;        /**< \brief Offset: 0x00 I2C Slave Mode */
+       SercomSpi                 SPI;         /**< \brief Offset: 0x00 SPI Mode */
+       SercomUsart               USART;       /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SERCOM_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sysctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sysctrl.h
new file mode 100644
index 0000000000..4a41633941
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sysctrl.h
@@ -0,0 +1,948 @@
+/**
+ * \file
+ *
+ * \brief Component description for SYSCTRL
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_COMPONENT_
+#define _SAMD21_SYSCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SYSCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SYSCTRL System Control */
+/*@{*/
+
+#define SYSCTRL_U2100
+#define REV_SYSCTRL                 0x201
+
+/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready Interrupt Enable     */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready Interrupt Enable      */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready Interrupt Enable       */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready Interrupt Enable       */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection Interrupt Enable   */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready Interrupt Enable */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise Interrupt Enable    */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall Interrupt Enable    */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout Interrupt Enable */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENCLR_OFFSET     0x00         /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSCRDY    (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos)
+#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC32KRDY  (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC8MRDY   (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRDY    (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLOOB    (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKF   (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKC   (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
+#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRCS    (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos)
+#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33RDY   (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos)
+#define SYSCTRL_INTENCLR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33DET   (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos)
+#define SYSCTRL_INTENCLR_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_B33SRDY    (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKR   (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKF   (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLTO    (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos)
+#define SYSCTRL_INTENCLR_MASK       0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */
+
+/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready Interrupt Enable     */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready Interrupt Enable      */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready Interrupt Enable       */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready Interrupt Enable       */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection Interrupt Enable   */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready Interrupt Enable */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise Interrupt Enable    */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall Interrupt Enable    */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout Interrupt Enable */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENSET_OFFSET     0x04         /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
+#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define SYSCTRL_INTENSET_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSCRDY    (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos)
+#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC32KRDY  (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC8MRDY   (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRDY    (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLOOB    (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKF   (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKC   (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos)
+#define SYSCTRL_INTENSET_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRCS    (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos)
+#define SYSCTRL_INTENSET_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33RDY   (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos)
+#define SYSCTRL_INTENSET_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33DET   (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos)
+#define SYSCTRL_INTENSET_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_B33SRDY    (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKR   (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKF   (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLTO    (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos)
+#define SYSCTRL_INTENSET_MASK       0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */
+
+/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    __I uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    __I uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    __I uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    __I uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    __I uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    __I uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    __I uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    __I uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    __I uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    __I uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    __I uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    __I uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    __I uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise                     */
+    __I uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall                     */
+    __I uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout                  */
+    __I uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTFLAG_OFFSET      0x08         /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SYSCTRL_INTFLAG_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
+#define SYSCTRL_INTFLAG_XOSCRDY     (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos)
+#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
+#define SYSCTRL_INTFLAG_XOSC32KRDY  (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
+#define SYSCTRL_INTFLAG_OSC32KRDY   (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
+#define SYSCTRL_INTFLAG_OSC8MRDY    (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
+#define SYSCTRL_INTFLAG_DFLLRDY     (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
+#define SYSCTRL_INTFLAG_DFLLOOB     (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
+#define SYSCTRL_INTFLAG_DFLLLCKF    (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
+#define SYSCTRL_INTFLAG_DFLLLCKC    (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
+#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTFLAG_DFLLRCS     (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos)
+#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
+#define SYSCTRL_INTFLAG_BOD33RDY    (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos)
+#define SYSCTRL_INTFLAG_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
+#define SYSCTRL_INTFLAG_BOD33DET    (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos)
+#define SYSCTRL_INTFLAG_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
+#define SYSCTRL_INTFLAG_B33SRDY     (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
+#define SYSCTRL_INTFLAG_DPLLLCKR    (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
+#define SYSCTRL_INTFLAG_DPLLLCKF    (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
+#define SYSCTRL_INTFLAG_DPLLLTO     (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos)
+#define SYSCTRL_INTFLAG_MASK        0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */
+
+/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise                     */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall                     */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout                  */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_PCLKSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_PCLKSR_OFFSET       0x0C         /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
+#define SYSCTRL_PCLKSR_RESETVALUE   0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
+
+#define SYSCTRL_PCLKSR_XOSCRDY_Pos  0            /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
+#define SYSCTRL_PCLKSR_XOSCRDY      (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos)
+#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
+#define SYSCTRL_PCLKSR_XOSC32KRDY   (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
+#define SYSCTRL_PCLKSR_OSC32KRDY    (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
+#define SYSCTRL_PCLKSR_OSC8MRDY     (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLRDY_Pos  4            /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
+#define SYSCTRL_PCLKSR_DFLLRDY      (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLOOB_Pos  5            /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
+#define SYSCTRL_PCLKSR_DFLLOOB      (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
+#define SYSCTRL_PCLKSR_DFLLLCKF     (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
+#define SYSCTRL_PCLKSR_DFLLLCKC     (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
+#define SYSCTRL_PCLKSR_DFLLRCS_Pos  8            /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
+#define SYSCTRL_PCLKSR_DFLLRCS      (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos)
+#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
+#define SYSCTRL_PCLKSR_BOD33RDY     (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos)
+#define SYSCTRL_PCLKSR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
+#define SYSCTRL_PCLKSR_BOD33DET     (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos)
+#define SYSCTRL_PCLKSR_B33SRDY_Pos  11           /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
+#define SYSCTRL_PCLKSR_B33SRDY      (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
+#define SYSCTRL_PCLKSR_DPLLLCKR     (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
+#define SYSCTRL_PCLKSR_DPLLLCKF     (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DPLLLTO_Pos  17           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
+#define SYSCTRL_PCLKSR_DPLLLTO      (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos)
+#define SYSCTRL_PCLKSR_MASK         0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */
+
+/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t GAIN:3;           /*!< bit:  8..10  Oscillator Gain                    */
+    uint16_t AMPGC:1;          /*!< bit:     11  Automatic Amplitude Gain Control   */
+    uint16_t STARTUP:4;        /*!< bit: 12..15  Start-Up Time                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_XOSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC_OFFSET         0x10         /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define SYSCTRL_XOSC_RESETVALUE     0x0080ul     /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
+
+#define SYSCTRL_XOSC_ENABLE_Pos     1            /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
+#define SYSCTRL_XOSC_ENABLE         (0x1ul << SYSCTRL_XOSC_ENABLE_Pos)
+#define SYSCTRL_XOSC_XTALEN_Pos     2            /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC_XTALEN         (0x1ul << SYSCTRL_XOSC_XTALEN_Pos)
+#define SYSCTRL_XOSC_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_XOSC) Run in Standby */
+#define SYSCTRL_XOSC_RUNSTDBY       (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC_ONDEMAND_Pos   7            /**< \brief (SYSCTRL_XOSC) On Demand Control */
+#define SYSCTRL_XOSC_ONDEMAND       (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
+#define SYSCTRL_XOSC_GAIN_Pos       8            /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
+#define SYSCTRL_XOSC_GAIN_Msk       (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN(value)    (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos))
+#define   SYSCTRL_XOSC_GAIN_0_Val         0x0ul  /**< \brief (SYSCTRL_XOSC) 2MHz */
+#define   SYSCTRL_XOSC_GAIN_1_Val         0x1ul  /**< \brief (SYSCTRL_XOSC) 4MHz */
+#define   SYSCTRL_XOSC_GAIN_2_Val         0x2ul  /**< \brief (SYSCTRL_XOSC) 8MHz */
+#define   SYSCTRL_XOSC_GAIN_3_Val         0x3ul  /**< \brief (SYSCTRL_XOSC) 16MHz */
+#define   SYSCTRL_XOSC_GAIN_4_Val         0x4ul  /**< \brief (SYSCTRL_XOSC) 30MHz */
+#define SYSCTRL_XOSC_GAIN_0         (SYSCTRL_XOSC_GAIN_0_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_1         (SYSCTRL_XOSC_GAIN_1_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_2         (SYSCTRL_XOSC_GAIN_2_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_3         (SYSCTRL_XOSC_GAIN_3_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_4         (SYSCTRL_XOSC_GAIN_4_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_AMPGC_Pos      11           /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
+#define SYSCTRL_XOSC_AMPGC          (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
+#define SYSCTRL_XOSC_STARTUP_Pos    12           /**< \brief (SYSCTRL_XOSC) Start-Up Time */
+#define SYSCTRL_XOSC_STARTUP_Msk    (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
+#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos))
+#define SYSCTRL_XOSC_MASK           0xFFC6ul     /**< \brief (SYSCTRL_XOSC) MASK Register */
+
+/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t EN32K:1;          /*!< bit:      3  32kHz Output Enable                */
+    uint16_t EN1K:1;           /*!< bit:      4  1kHz Output Enable                 */
+    uint16_t AAMPEN:1;         /*!< bit:      5  Automatic Amplitude Control Enable */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC32K_OFFSET      0x14         /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define SYSCTRL_XOSC32K_RESETVALUE  0x0080ul     /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define SYSCTRL_XOSC32K_ENABLE_Pos  1            /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
+#define SYSCTRL_XOSC32K_ENABLE      (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos)
+#define SYSCTRL_XOSC32K_XTALEN_Pos  2            /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC32K_XTALEN      (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos)
+#define SYSCTRL_XOSC32K_EN32K_Pos   3            /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN32K       (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos)
+#define SYSCTRL_XOSC32K_EN1K_Pos    4            /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN1K        (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos)
+#define SYSCTRL_XOSC32K_AAMPEN_Pos  5            /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
+#define SYSCTRL_XOSC32K_AAMPEN      (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos)
+#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
+#define SYSCTRL_XOSC32K_RUNSTDBY    (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
+#define SYSCTRL_XOSC32K_ONDEMAND    (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
+#define SYSCTRL_XOSC32K_STARTUP_Pos 8            /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
+#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos))
+#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12           /**< \brief (SYSCTRL_XOSC32K) Write Lock */
+#define SYSCTRL_XOSC32K_WRTLOCK     (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
+#define SYSCTRL_XOSC32K_MASK        0x17FEul     /**< \brief (SYSCTRL_XOSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t EN32K:1;          /*!< bit:      2  32kHz Output Enable                */
+    uint32_t EN1K:1;           /*!< bit:      3  1kHz Output Enable                 */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t CALIB:7;          /*!< bit: 16..22  Oscillator Calibration             */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_OSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC32K_OFFSET       0x18         /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
+#define SYSCTRL_OSC32K_RESETVALUE   0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
+
+#define SYSCTRL_OSC32K_ENABLE_Pos   1            /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
+#define SYSCTRL_OSC32K_ENABLE       (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos)
+#define SYSCTRL_OSC32K_EN32K_Pos    2            /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
+#define SYSCTRL_OSC32K_EN32K        (0x1ul << SYSCTRL_OSC32K_EN32K_Pos)
+#define SYSCTRL_OSC32K_EN1K_Pos     3            /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
+#define SYSCTRL_OSC32K_EN1K         (0x1ul << SYSCTRL_OSC32K_EN1K_Pos)
+#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_OSC32K) Run in Standby */
+#define SYSCTRL_OSC32K_RUNSTDBY     (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_OSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_OSC32K) On Demand Control */
+#define SYSCTRL_OSC32K_ONDEMAND     (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
+#define SYSCTRL_OSC32K_STARTUP_Pos  8            /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_OSC32K_STARTUP_Msk  (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
+#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos))
+#define SYSCTRL_OSC32K_WRTLOCK_Pos  12           /**< \brief (SYSCTRL_OSC32K) Write Lock */
+#define SYSCTRL_OSC32K_WRTLOCK      (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
+#define SYSCTRL_OSC32K_CALIB_Pos    16           /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
+#define SYSCTRL_OSC32K_CALIB_Msk    (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
+#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos))
+#define SYSCTRL_OSC32K_MASK         0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W  8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CALIB:5;          /*!< bit:  0.. 4  Oscillator Calibration             */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  WRTLOCK:1;        /*!< bit:      7  Write Lock                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSCULP32K_OFFSET    0x1C         /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful       /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define SYSCTRL_OSCULP32K_CALIB_Pos 0            /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
+#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
+#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos))
+#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7            /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
+#define SYSCTRL_OSCULP32K_WRTLOCK   (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
+#define SYSCTRL_OSCULP32K_MASK      0x9Ful       /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
+
+/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t PRESC:2;          /*!< bit:  8.. 9  Oscillator Prescaler               */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CALIB:12;         /*!< bit: 16..27  Oscillator Calibration             */
+    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
+    uint32_t FRANGE:2;         /*!< bit: 30..31  Oscillator Frequency Range         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_OSC8M_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC8M_OFFSET        0x20         /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
+#define SYSCTRL_OSC8M_RESETVALUE    0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
+
+#define SYSCTRL_OSC8M_ENABLE_Pos    1            /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
+#define SYSCTRL_OSC8M_ENABLE        (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos)
+#define SYSCTRL_OSC8M_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_OSC8M) Run in Standby */
+#define SYSCTRL_OSC8M_RUNSTDBY      (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos)
+#define SYSCTRL_OSC8M_ONDEMAND_Pos  7            /**< \brief (SYSCTRL_OSC8M) On Demand Control */
+#define SYSCTRL_OSC8M_ONDEMAND      (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
+#define SYSCTRL_OSC8M_PRESC_Pos     8            /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
+#define SYSCTRL_OSC8M_PRESC_Msk     (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC(value)  (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos))
+#define   SYSCTRL_OSC8M_PRESC_0_Val       0x0ul  /**< \brief (SYSCTRL_OSC8M) 1 */
+#define   SYSCTRL_OSC8M_PRESC_1_Val       0x1ul  /**< \brief (SYSCTRL_OSC8M) 2 */
+#define   SYSCTRL_OSC8M_PRESC_2_Val       0x2ul  /**< \brief (SYSCTRL_OSC8M) 4 */
+#define   SYSCTRL_OSC8M_PRESC_3_Val       0x3ul  /**< \brief (SYSCTRL_OSC8M) 8 */
+#define SYSCTRL_OSC8M_PRESC_0       (SYSCTRL_OSC8M_PRESC_0_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_1       (SYSCTRL_OSC8M_PRESC_1_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_2       (SYSCTRL_OSC8M_PRESC_2_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_3       (SYSCTRL_OSC8M_PRESC_3_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_CALIB_Pos     16           /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
+#define SYSCTRL_OSC8M_CALIB_Msk     (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
+#define SYSCTRL_OSC8M_CALIB(value)  (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos))
+#define SYSCTRL_OSC8M_FRANGE_Pos    30           /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
+#define SYSCTRL_OSC8M_FRANGE_Msk    (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos))
+#define   SYSCTRL_OSC8M_FRANGE_0_Val      0x0ul  /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
+#define   SYSCTRL_OSC8M_FRANGE_1_Val      0x1ul  /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
+#define   SYSCTRL_OSC8M_FRANGE_2_Val      0x2ul  /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
+#define   SYSCTRL_OSC8M_FRANGE_3_Val      0x3ul  /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
+#define SYSCTRL_OSC8M_FRANGE_0      (SYSCTRL_OSC8M_FRANGE_0_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_1      (SYSCTRL_OSC8M_FRANGE_1_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_2      (SYSCTRL_OSC8M_FRANGE_2_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_3      (SYSCTRL_OSC8M_FRANGE_3_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_MASK          0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */
+
+/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  DFLL Enable                        */
+    uint16_t MODE:1;           /*!< bit:      2  Operating Mode Selection           */
+    uint16_t STABLE:1;         /*!< bit:      3  Stable DFLL Frequency              */
+    uint16_t LLAW:1;           /*!< bit:      4  Lose Lock After Wake               */
+    uint16_t USBCRM:1;         /*!< bit:      5  USB Clock Recovery Mode            */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t CCDIS:1;          /*!< bit:      8  Chill Cycle Disable                */
+    uint16_t QLDIS:1;          /*!< bit:      9  Quick Lock Disable                 */
+    uint16_t BPLCKC:1;         /*!< bit:     10  Bypass Coarse Lock                 */
+    uint16_t WAITLOCK:1;       /*!< bit:     11  Wait Lock                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLCTRL_OFFSET     0x24         /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
+#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul     /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
+
+#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1            /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
+#define SYSCTRL_DFLLCTRL_ENABLE     (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos)
+#define SYSCTRL_DFLLCTRL_MODE_Pos   2            /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
+#define SYSCTRL_DFLLCTRL_MODE       (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos)
+#define SYSCTRL_DFLLCTRL_STABLE_Pos 3            /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
+#define SYSCTRL_DFLLCTRL_STABLE     (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos)
+#define SYSCTRL_DFLLCTRL_LLAW_Pos   4            /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
+#define SYSCTRL_DFLLCTRL_LLAW       (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos)
+#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5            /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
+#define SYSCTRL_DFLLCTRL_USBCRM     (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos)
+#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
+#define SYSCTRL_DFLLCTRL_RUNSTDBY   (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
+#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
+#define SYSCTRL_DFLLCTRL_ONDEMAND   (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
+#define SYSCTRL_DFLLCTRL_CCDIS_Pos  8            /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
+#define SYSCTRL_DFLLCTRL_CCDIS      (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos)
+#define SYSCTRL_DFLLCTRL_QLDIS_Pos  9            /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
+#define SYSCTRL_DFLLCTRL_QLDIS      (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos)
+#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10           /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
+#define SYSCTRL_DFLLCTRL_BPLCKC     (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
+#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11           /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
+#define SYSCTRL_DFLLCTRL_WAITLOCK   (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
+#define SYSCTRL_DFLLCTRL_MASK       0x0FFEul     /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
+
+/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FINE:10;          /*!< bit:  0.. 9  Fine Value                         */
+    uint32_t COARSE:6;         /*!< bit: 10..15  Coarse Value                       */
+    uint32_t DIFF:16;          /*!< bit: 16..31  Multiplication Ratio Difference    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLVAL_OFFSET      0x28         /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
+#define SYSCTRL_DFLLVAL_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define SYSCTRL_DFLLVAL_FINE_Pos    0            /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
+#define SYSCTRL_DFLLVAL_FINE_Msk    (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
+#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos))
+#define SYSCTRL_DFLLVAL_COARSE_Pos  10           /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
+#define SYSCTRL_DFLLVAL_COARSE_Msk  (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
+#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos))
+#define SYSCTRL_DFLLVAL_DIFF_Pos    16           /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define SYSCTRL_DFLLVAL_DIFF_Msk    (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
+#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos))
+#define SYSCTRL_DFLLVAL_MASK        0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
+
+/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUL:16;           /*!< bit:  0..15  DFLL Multiply Factor               */
+    uint32_t FSTEP:10;         /*!< bit: 16..25  Fine Maximum Step                  */
+    uint32_t CSTEP:6;          /*!< bit: 26..31  Coarse Maximum Step                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLMUL_OFFSET      0x2C         /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define SYSCTRL_DFLLMUL_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define SYSCTRL_DFLLMUL_MUL_Pos     0            /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
+#define SYSCTRL_DFLLMUL_MUL_Msk     (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
+#define SYSCTRL_DFLLMUL_MUL(value)  (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos))
+#define SYSCTRL_DFLLMUL_FSTEP_Pos   16           /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
+#define SYSCTRL_DFLLMUL_FSTEP_Msk   (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
+#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos))
+#define SYSCTRL_DFLLMUL_CSTEP_Pos   26           /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
+#define SYSCTRL_DFLLMUL_CSTEP_Msk   (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
+#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos))
+#define SYSCTRL_DFLLMUL_MASK        0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
+
+/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W  8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  READREQ:1;        /*!< bit:      7  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLSYNC_OFFSET     0x30         /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul       /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define SYSCTRL_DFLLSYNC_READREQ_Pos 7            /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
+#define SYSCTRL_DFLLSYNC_READREQ    (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos)
+#define SYSCTRL_DFLLSYNC_MASK       0x80ul       /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
+
+/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t HYST:1;           /*!< bit:      2  Hysteresis                         */
+    uint32_t ACTION:2;         /*!< bit:  3.. 4  BOD33 Action                       */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MODE:1;           /*!< bit:      8  Operation Mode                     */
+    uint32_t CEN:1;            /*!< bit:      9  Clock Enable                       */
+    uint32_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint32_t PSEL:4;           /*!< bit: 12..15  Prescaler Select                   */
+    uint32_t LEVEL:6;          /*!< bit: 16..21  BOD33 Threshold Level              */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_BOD33_OFFSET        0x34         /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
+#define SYSCTRL_BOD33_RESETVALUE    0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
+
+#define SYSCTRL_BOD33_ENABLE_Pos    1            /**< \brief (SYSCTRL_BOD33) Enable */
+#define SYSCTRL_BOD33_ENABLE        (0x1ul << SYSCTRL_BOD33_ENABLE_Pos)
+#define SYSCTRL_BOD33_HYST_Pos      2            /**< \brief (SYSCTRL_BOD33) Hysteresis */
+#define SYSCTRL_BOD33_HYST          (0x1ul << SYSCTRL_BOD33_HYST_Pos)
+#define SYSCTRL_BOD33_ACTION_Pos    3            /**< \brief (SYSCTRL_BOD33) BOD33 Action */
+#define SYSCTRL_BOD33_ACTION_Msk    (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos))
+#define   SYSCTRL_BOD33_ACTION_NONE_Val   0x0ul  /**< \brief (SYSCTRL_BOD33) No action */
+#define   SYSCTRL_BOD33_ACTION_RESET_Val  0x1ul  /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
+#define   SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul  /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
+#define SYSCTRL_BOD33_ACTION_NONE   (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_RESET  (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_BOD33) Run in Standby */
+#define SYSCTRL_BOD33_RUNSTDBY      (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos)
+#define SYSCTRL_BOD33_MODE_Pos      8            /**< \brief (SYSCTRL_BOD33) Operation Mode */
+#define SYSCTRL_BOD33_MODE          (0x1ul << SYSCTRL_BOD33_MODE_Pos)
+#define SYSCTRL_BOD33_CEN_Pos       9            /**< \brief (SYSCTRL_BOD33) Clock Enable */
+#define SYSCTRL_BOD33_CEN           (0x1ul << SYSCTRL_BOD33_CEN_Pos)
+#define SYSCTRL_BOD33_PSEL_Pos      12           /**< \brief (SYSCTRL_BOD33) Prescaler Select */
+#define SYSCTRL_BOD33_PSEL_Msk      (0xFul << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL(value)   (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos))
+#define   SYSCTRL_BOD33_PSEL_DIV2_Val     0x0ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
+#define   SYSCTRL_BOD33_PSEL_DIV4_Val     0x1ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
+#define   SYSCTRL_BOD33_PSEL_DIV8_Val     0x2ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
+#define   SYSCTRL_BOD33_PSEL_DIV16_Val    0x3ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
+#define   SYSCTRL_BOD33_PSEL_DIV32_Val    0x4ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
+#define   SYSCTRL_BOD33_PSEL_DIV64_Val    0x5ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
+#define   SYSCTRL_BOD33_PSEL_DIV128_Val   0x6ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
+#define   SYSCTRL_BOD33_PSEL_DIV256_Val   0x7ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
+#define   SYSCTRL_BOD33_PSEL_DIV512_Val   0x8ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
+#define   SYSCTRL_BOD33_PSEL_DIV1K_Val    0x9ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
+#define   SYSCTRL_BOD33_PSEL_DIV2K_Val    0xAul  /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
+#define   SYSCTRL_BOD33_PSEL_DIV4K_Val    0xBul  /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
+#define   SYSCTRL_BOD33_PSEL_DIV8K_Val    0xCul  /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
+#define   SYSCTRL_BOD33_PSEL_DIV16K_Val   0xDul  /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
+#define   SYSCTRL_BOD33_PSEL_DIV32K_Val   0xEul  /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
+#define   SYSCTRL_BOD33_PSEL_DIV64K_Val   0xFul  /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
+#define SYSCTRL_BOD33_PSEL_DIV2     (SYSCTRL_BOD33_PSEL_DIV2_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4     (SYSCTRL_BOD33_PSEL_DIV4_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8     (SYSCTRL_BOD33_PSEL_DIV8_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16    (SYSCTRL_BOD33_PSEL_DIV16_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32    (SYSCTRL_BOD33_PSEL_DIV32_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64    (SYSCTRL_BOD33_PSEL_DIV64_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV128   (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV256   (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV512   (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV1K    (SYSCTRL_BOD33_PSEL_DIV1K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV2K    (SYSCTRL_BOD33_PSEL_DIV2K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4K    (SYSCTRL_BOD33_PSEL_DIV4K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8K    (SYSCTRL_BOD33_PSEL_DIV8K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16K   (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32K   (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64K   (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_LEVEL_Pos     16           /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
+#define SYSCTRL_BOD33_LEVEL_Msk     (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
+#define SYSCTRL_BOD33_LEVEL(value)  (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos))
+#define SYSCTRL_BOD33_MASK          0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
+
+/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t :6;               /*!< bit:  7..12  Reserved                           */
+    uint16_t FORCELDO:1;       /*!< bit:     13  Force LDO Voltage Regulator        */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREG_OFFSET         0x3C         /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
+#define SYSCTRL_VREG_RESETVALUE     0x0000ul     /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
+
+#define SYSCTRL_VREG_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_VREG) Run in Standby */
+#define SYSCTRL_VREG_RUNSTDBY       (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
+#define SYSCTRL_VREG_FORCELDO_Pos   13           /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
+#define SYSCTRL_VREG_FORCELDO       (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
+#define SYSCTRL_VREG_MASK           0x2040ul     /**< \brief (SYSCTRL_VREG) MASK Register */
+
+/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t TSEN:1;           /*!< bit:      1  Temperature Sensor Enable          */
+    uint32_t BGOUTEN:1;        /*!< bit:      2  Bandgap Output Enable              */
+    uint32_t :13;              /*!< bit:  3..15  Reserved                           */
+    uint32_t CALIB:11;         /*!< bit: 16..26  Bandgap Voltage Generator Calibration */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREF_OFFSET         0x40         /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
+#define SYSCTRL_VREF_RESETVALUE     0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
+
+#define SYSCTRL_VREF_TSEN_Pos       1            /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
+#define SYSCTRL_VREF_TSEN           (0x1ul << SYSCTRL_VREF_TSEN_Pos)
+#define SYSCTRL_VREF_BGOUTEN_Pos    2            /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
+#define SYSCTRL_VREF_BGOUTEN        (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
+#define SYSCTRL_VREF_CALIB_Pos      16           /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
+#define SYSCTRL_VREF_CALIB_Msk      (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
+#define SYSCTRL_VREF_CALIB(value)   (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos))
+#define SYSCTRL_VREF_MASK           0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W  8) DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  DPLL Enable                        */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Clock Activation         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLA_OFFSET    0x44         /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
+#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul       /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1            /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
+#define SYSCTRL_DPLLCTRLA_ENABLE    (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY  (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
+#define SYSCTRL_DPLLCTRLA_ONDEMAND  (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define SYSCTRL_DPLLCTRLA_MASK      0xC2ul       /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LDR:12;           /*!< bit:  0..11  Loop Divider Ratio                 */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t LDRFRAC:4;        /*!< bit: 16..19  Loop Divider Ratio Fractional Part */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLRATIO_OFFSET    0x48         /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define SYSCTRL_DPLLRATIO_LDR_Pos   0            /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
+#define SYSCTRL_DPLLRATIO_LDR_Msk   (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
+#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos))
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16           /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define SYSCTRL_DPLLRATIO_MASK      0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FILTER:2;         /*!< bit:  0.. 1  Proportional Integral Filter Selection */
+    uint32_t LPEN:1;           /*!< bit:      2  Low-Power Enable                   */
+    uint32_t WUF:1;            /*!< bit:      3  Wake Up Fast                       */
+    uint32_t REFCLK:2;         /*!< bit:  4.. 5  Reference Clock Selection          */
+    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint32_t LTIME:3;          /*!< bit:  8..10  Lock Time                          */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t LBYPASS:1;        /*!< bit:     12  Lock Bypass                        */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DIV:11;           /*!< bit: 16..26  Clock Divider                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLB_OFFSET    0x4C         /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
+#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0            /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos))
+#define   SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
+#define   SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul  /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
+#define   SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul  /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
+#define   SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul  /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_LPEN_Pos  2            /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
+#define SYSCTRL_DPLLCTRLB_LPEN      (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos)
+#define SYSCTRL_DPLLCTRLB_WUF_Pos   3            /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
+#define SYSCTRL_DPLLCTRLB_WUF       (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4            /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
+#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos))
+#define   SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
+#define   SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul  /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
+#define   SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul  /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8            /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
+#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos))
+#define   SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
+#define   SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12           /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
+#define SYSCTRL_DPLLCTRLB_LBYPASS   (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV_Pos   16           /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
+#define SYSCTRL_DPLLCTRLB_DIV_Msk   (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos))
+#define SYSCTRL_DPLLCTRLB_MASK      0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/   8) DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  LOCK:1;           /*!< bit:      0  DPLL Lock Status                   */
+    uint8_t  CLKRDY:1;         /*!< bit:      1  Output Clock Ready                 */
+    uint8_t  ENABLE:1;         /*!< bit:      2  DPLL Enable                        */
+    uint8_t  DIV:1;            /*!< bit:      3  Divider Enable                     */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLSTATUS_OFFSET   0x50         /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
+#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul       /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0            /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
+#define SYSCTRL_DPLLSTATUS_LOCK     (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos)
+#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1            /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
+#define SYSCTRL_DPLLSTATUS_CLKRDY   (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2            /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
+#define SYSCTRL_DPLLSTATUS_ENABLE   (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
+#define SYSCTRL_DPLLSTATUS_DIV_Pos  3            /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
+#define SYSCTRL_DPLLSTATUS_DIV      (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos)
+#define SYSCTRL_DPLLSTATUS_MASK     0x0Ful       /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief SYSCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO SYSCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+  __IO SYSCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+  __IO SYSCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+  __I  SYSCTRL_PCLKSR_Type       PCLKSR;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
+  __IO SYSCTRL_XOSC_Type         XOSC;        /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+       RoReg8                    Reserved1[0x2];
+  __IO SYSCTRL_XOSC32K_Type      XOSC32K;     /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+       RoReg8                    Reserved2[0x2];
+  __IO SYSCTRL_OSC32K_Type       OSC32K;      /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+  __IO SYSCTRL_OSCULP32K_Type    OSCULP32K;   /**< \brief Offset: 0x1C (R/W  8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+       RoReg8                    Reserved3[0x3];
+  __IO SYSCTRL_OSC8M_Type        OSC8M;       /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+  __IO SYSCTRL_DFLLCTRL_Type     DFLLCTRL;    /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+       RoReg8                    Reserved4[0x2];
+  __IO SYSCTRL_DFLLVAL_Type      DFLLVAL;     /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+  __IO SYSCTRL_DFLLMUL_Type      DFLLMUL;     /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+  __IO SYSCTRL_DFLLSYNC_Type     DFLLSYNC;    /**< \brief Offset: 0x30 (R/W  8) DFLL48M Synchronization */
+       RoReg8                    Reserved5[0x3];
+  __IO SYSCTRL_BOD33_Type        BOD33;       /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+       RoReg8                    Reserved6[0x4];
+  __IO SYSCTRL_VREG_Type         VREG;        /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+       RoReg8                    Reserved7[0x2];
+  __IO SYSCTRL_VREF_Type         VREF;        /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+  __IO SYSCTRL_DPLLCTRLA_Type    DPLLCTRLA;   /**< \brief Offset: 0x44 (R/W  8) DPLL Control A */
+       RoReg8                    Reserved8[0x3];
+  __IO SYSCTRL_DPLLRATIO_Type    DPLLRATIO;   /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+  __IO SYSCTRL_DPLLCTRLB_Type    DPLLCTRLB;   /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+  __I  SYSCTRL_DPLLSTATUS_Type   DPLLSTATUS;  /**< \brief Offset: 0x50 (R/   8) DPLL Status */
+} Sysctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tc.h
new file mode 100644
index 0000000000..c4b11d3470
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tc.h
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC_COMPONENT_
+#define _SAMD21_TC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2212
+#define REV_TC                      0x131
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  TC Mode                            */
+    uint16_t :1;               /*!< bit:      4  Reserved                           */
+    uint16_t WAVEGEN:2;        /*!< bit:  5.. 6  Waveform Generation Operation      */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint16_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint16_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET             0x00         /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE         0x0000ul     /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos          0            /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST              (0x1ul << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos         1            /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE             (0x1ul << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos           2            /**< \brief (TC_CTRLA) TC Mode */
+#define TC_CTRLA_MODE_Msk           (0x3ul << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value)        (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
+#define   TC_CTRLA_MODE_COUNT16_Val       0x0ul  /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define   TC_CTRLA_MODE_COUNT8_Val        0x1ul  /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define   TC_CTRLA_MODE_COUNT32_Val       0x2ul  /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16       (TC_CTRLA_MODE_COUNT16_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8        (TC_CTRLA_MODE_COUNT8_Val      << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32       (TC_CTRLA_MODE_COUNT32_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_WAVEGEN_Pos        5            /**< \brief (TC_CTRLA) Waveform Generation Operation */
+#define TC_CTRLA_WAVEGEN_Msk        (0x3ul << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN(value)     (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
+#define   TC_CTRLA_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_MPWM_Val       0x3ul  /**< \brief (TC_CTRLA)  */
+#define TC_CTRLA_WAVEGEN_NFRQ       (TC_CTRLA_WAVEGEN_NFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MFRQ       (TC_CTRLA_WAVEGEN_MFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_NPWM       (TC_CTRLA_WAVEGEN_NPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MPWM       (TC_CTRLA_WAVEGEN_MPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_PRESCALER_Pos      8            /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk      (0x7ul << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value)   (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
+#define   TC_CTRLA_PRESCALER_DIV1_Val     0x0ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define   TC_CTRLA_PRESCALER_DIV2_Val     0x1ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define   TC_CTRLA_PRESCALER_DIV4_Val     0x2ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define   TC_CTRLA_PRESCALER_DIV8_Val     0x3ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define   TC_CTRLA_PRESCALER_DIV16_Val    0x4ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define   TC_CTRLA_PRESCALER_DIV64_Val    0x5ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define   TC_CTRLA_PRESCALER_DIV256_Val   0x6ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define   TC_CTRLA_PRESCALER_DIV1024_Val  0x7ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1     (TC_CTRLA_PRESCALER_DIV1_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2     (TC_CTRLA_PRESCALER_DIV2_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4     (TC_CTRLA_PRESCALER_DIV4_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8     (TC_CTRLA_PRESCALER_DIV8_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16    (TC_CTRLA_PRESCALER_DIV16_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64    (TC_CTRLA_PRESCALER_DIV64_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256   (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024  (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos       11           /**< \brief (TC_CTRLA) Run in Standby */
+#define TC_CTRLA_RUNSTDBY           (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos      12           /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk      (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value)   (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
+#define   TC_CTRLA_PRESCSYNC_GCLK_Val     0x0ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define   TC_CTRLA_PRESCSYNC_PRESC_Val    0x1ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define   TC_CTRLA_PRESCSYNC_RESYNC_Val   0x2ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK     (TC_CTRLA_PRESCSYNC_GCLK_Val   << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC    (TC_CTRLA_PRESCSYNC_PRESC_Val  << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC   (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_MASK               0x3F6Ful     /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ADDR:5;           /*!< bit:  0.. 4  Address                            */
+    uint16_t :9;               /*!< bit:  5..13  Reserved                           */
+    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
+    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_READREQ_OFFSET           0x02         /**< \brief (TC_READREQ offset) Read Request */
+#define TC_READREQ_RESETVALUE       0x0000ul     /**< \brief (TC_READREQ reset_value) Read Request */
+
+#define TC_READREQ_ADDR_Pos         0            /**< \brief (TC_READREQ) Address */
+#define TC_READREQ_ADDR_Msk         (0x1Ful << TC_READREQ_ADDR_Pos)
+#define TC_READREQ_ADDR(value)      (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
+#define TC_READREQ_RCONT_Pos        14           /**< \brief (TC_READREQ) Read Continuously */
+#define TC_READREQ_RCONT            (0x1ul << TC_READREQ_RCONT_Pos)
+#define TC_READREQ_RREQ_Pos         15           /**< \brief (TC_READREQ) Read Request */
+#define TC_READREQ_RREQ             (0x1ul << TC_READREQ_RREQ_Pos)
+#define TC_READREQ_MASK             0xC01Ful     /**< \brief (TC_READREQ) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET          0x04         /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE      0x02ul       /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos         0            /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR             (0x1ul << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos     2            /**< \brief (TC_CTRLBCLR) One-Shot */
+#define TC_CTRLBCLR_ONESHOT         (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos         6            /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk         (0x3ul << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value)      (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
+#define   TC_CTRLBCLR_CMD_NONE_Val        0x0ul  /**< \brief (TC_CTRLBCLR) No action */
+#define   TC_CTRLBCLR_CMD_RETRIGGER_Val   0x1ul  /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define   TC_CTRLBCLR_CMD_STOP_Val        0x2ul  /**< \brief (TC_CTRLBCLR) Force a stop */
+#define TC_CTRLBCLR_CMD_NONE        (TC_CTRLBCLR_CMD_NONE_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER   (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP        (TC_CTRLBCLR_CMD_STOP_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK            0xC5ul       /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET          0x05         /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE      0x00ul       /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos         0            /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR             (0x1ul << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos     2            /**< \brief (TC_CTRLBSET) One-Shot */
+#define TC_CTRLBSET_ONESHOT         (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos         6            /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk         (0x3ul << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value)      (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
+#define   TC_CTRLBSET_CMD_NONE_Val        0x0ul  /**< \brief (TC_CTRLBSET) No action */
+#define   TC_CTRLBSET_CMD_RETRIGGER_Val   0x1ul  /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define   TC_CTRLBSET_CMD_STOP_Val        0x2ul  /**< \brief (TC_CTRLBSET) Force a stop */
+#define TC_CTRLBSET_CMD_NONE        (TC_CTRLBSET_CMD_NONE_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER   (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP        (TC_CTRLBSET_CMD_STOP_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK            0xC5ul       /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W  8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  INVEN0:1;         /*!< bit:      0  Output Waveform 0 Invert Enable    */
+    uint8_t  INVEN1:1;         /*!< bit:      1  Output Waveform 1 Invert Enable    */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CPTEN0:1;         /*!< bit:      4  Capture Channel 0 Enable           */
+    uint8_t  CPTEN1:1;         /*!< bit:      5  Capture Channel 1 Enable           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  INVEN:2;          /*!< bit:  0.. 1  Output Waveform x Invert Enable    */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CPTEN:2;          /*!< bit:  4.. 5  Capture Channel x Enable           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLC_OFFSET             0x06         /**< \brief (TC_CTRLC offset) Control C */
+#define TC_CTRLC_RESETVALUE         0x00ul       /**< \brief (TC_CTRLC reset_value) Control C */
+
+#define TC_CTRLC_INVEN0_Pos         0            /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
+#define TC_CTRLC_INVEN0             (1 << TC_CTRLC_INVEN0_Pos)
+#define TC_CTRLC_INVEN1_Pos         1            /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
+#define TC_CTRLC_INVEN1             (1 << TC_CTRLC_INVEN1_Pos)
+#define TC_CTRLC_INVEN_Pos          0            /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
+#define TC_CTRLC_INVEN_Msk          (0x3ul << TC_CTRLC_INVEN_Pos)
+#define TC_CTRLC_INVEN(value)       (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
+#define TC_CTRLC_CPTEN0_Pos         4            /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
+#define TC_CTRLC_CPTEN0             (1 << TC_CTRLC_CPTEN0_Pos)
+#define TC_CTRLC_CPTEN1_Pos         5            /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
+#define TC_CTRLC_CPTEN1             (1 << TC_CTRLC_CPTEN1_Pos)
+#define TC_CTRLC_CPTEN_Pos          4            /**< \brief (TC_CTRLC) Capture Channel x Enable */
+#define TC_CTRLC_CPTEN_Msk          (0x3ul << TC_CTRLC_CPTEN_Pos)
+#define TC_CTRLC_CPTEN(value)       (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
+#define TC_CTRLC_MASK               0x33ul       /**< \brief (TC_CTRLC) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run Mode                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET           0x08         /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE       0x00ul       /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (TC_DBGCTRL) Debug Run Mode */
+#define TC_DBGCTRL_DBGRUN           (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK             0x01ul       /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EVACT:3;          /*!< bit:  0.. 2  Event Action                       */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t TCINV:1;          /*!< bit:      4  TC Inverted Event Input            */
+    uint16_t TCEI:1;           /*!< bit:      5  TC Event Input                     */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Event Output Enable */
+    uint16_t :3;               /*!< bit:  9..11  Reserved                           */
+    uint16_t MCEO0:1;          /*!< bit:     12  Match or Capture Channel 0 Event Output Enable */
+    uint16_t MCEO1:1;          /*!< bit:     13  Match or Capture Channel 1 Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint16_t MCEO:2;           /*!< bit: 12..13  Match or Capture Channel x Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET            0x0A         /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos         0            /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk         (0x7ul << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value)      (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
+#define   TC_EVCTRL_EVACT_OFF_Val         0x0ul  /**< \brief (TC_EVCTRL) Event action disabled */
+#define   TC_EVCTRL_EVACT_RETRIGGER_Val   0x1ul  /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define   TC_EVCTRL_EVACT_COUNT_Val       0x2ul  /**< \brief (TC_EVCTRL) Count on event */
+#define   TC_EVCTRL_EVACT_START_Val       0x3ul  /**< \brief (TC_EVCTRL) Start TC on event */
+#define   TC_EVCTRL_EVACT_PPW_Val         0x5ul  /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
+#define   TC_EVCTRL_EVACT_PWP_Val         0x6ul  /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
+#define TC_EVCTRL_EVACT_OFF         (TC_EVCTRL_EVACT_OFF_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER   (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT       (TC_EVCTRL_EVACT_COUNT_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START       (TC_EVCTRL_EVACT_START_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW         (TC_EVCTRL_EVACT_PPW_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP         (TC_EVCTRL_EVACT_PWP_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos         4            /**< \brief (TC_EVCTRL) TC Inverted Event Input */
+#define TC_EVCTRL_TCINV             (0x1ul << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos          5            /**< \brief (TC_EVCTRL) TC Event Input */
+#define TC_EVCTRL_TCEI              (0x1ul << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos         8            /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
+#define TC_EVCTRL_OVFEO             (0x1ul << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos         12           /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TC_EVCTRL_MCEO0             (1 << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos         13           /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TC_EVCTRL_MCEO1             (1 << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos          12           /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TC_EVCTRL_MCEO_Msk          (0x3ul << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value)       (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
+#define TC_EVCTRL_MASK              0x3137ul     /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET          0x0C         /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos         0            /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
+#define TC_INTENCLR_OVF             (0x1ul << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos         1            /**< \brief (TC_INTENCLR) Error Interrupt Enable */
+#define TC_INTENCLR_ERR             (0x1ul << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_SYNCRDY_Pos     3            /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define TC_INTENCLR_SYNCRDY         (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
+#define TC_INTENCLR_MC0_Pos         4            /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENCLR_MC0             (1 << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos         5            /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENCLR_MC1             (1 << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos          4            /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENCLR_MC_Msk          (0x3ul << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value)       (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
+#define TC_INTENCLR_MASK            0x3Bul       /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET          0x0D         /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE      0x00ul       /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos         0            /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
+#define TC_INTENSET_OVF             (0x1ul << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos         1            /**< \brief (TC_INTENSET) Error Interrupt Enable */
+#define TC_INTENSET_ERR             (0x1ul << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_SYNCRDY_Pos     3            /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
+#define TC_INTENSET_SYNCRDY         (0x1ul << TC_INTENSET_SYNCRDY_Pos)
+#define TC_INTENSET_MC0_Pos         4            /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENSET_MC0             (1 << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos         5            /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENSET_MC1             (1 << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos          4            /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENSET_MC_Msk          (0x3ul << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value)       (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
+#define TC_INTENSET_MASK            0x3Bul       /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint8_t  ERR:1;            /*!< bit:      1  Error                              */
+    __I uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
+    __I uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0         */
+    __I uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1         */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    __I uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x         */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET           0x0E         /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos          0            /**< \brief (TC_INTFLAG) Overflow */
+#define TC_INTFLAG_OVF              (0x1ul << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos          1            /**< \brief (TC_INTFLAG) Error */
+#define TC_INTFLAG_ERR              (0x1ul << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_SYNCRDY_Pos      3            /**< \brief (TC_INTFLAG) Synchronization Ready */
+#define TC_INTFLAG_SYNCRDY          (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
+#define TC_INTFLAG_MC0_Pos          4            /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
+#define TC_INTFLAG_MC0              (1 << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos          5            /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
+#define TC_INTFLAG_MC1              (1 << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos           4            /**< \brief (TC_INTFLAG) Match or Capture Channel x */
+#define TC_INTFLAG_MC_Msk           (0x3ul << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value)        (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
+#define TC_INTFLAG_MASK             0x3Bul       /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0F) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :3;               /*!< bit:  0.. 2  Reserved                           */
+    uint8_t  STOP:1;           /*!< bit:      3  Stop                               */
+    uint8_t  SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET            0x0F         /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE        0x08ul       /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos          3            /**< \brief (TC_STATUS) Stop */
+#define TC_STATUS_STOP              (0x1ul << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos         4            /**< \brief (TC_STATUS) Slave */
+#define TC_STATUS_SLAVE             (0x1ul << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_SYNCBUSY_Pos      7            /**< \brief (TC_STATUS) Synchronization Busy */
+#define TC_STATUS_SYNCBUSY          (0x1ul << TC_STATUS_SYNCBUSY_Pos)
+#define TC_STATUS_MASK              0x98ul       /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Count Value                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
+#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul     /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
+
+#define TC_COUNT16_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT16_COUNT) Count Value */
+#define TC_COUNT16_COUNT_COUNT_Msk  (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
+#define TC_COUNT16_COUNT_MASK       0xFFFFul     /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Count Value                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
+#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
+
+#define TC_COUNT32_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT32_COUNT) Count Value */
+#define TC_COUNT32_COUNT_COUNT_Msk  (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
+#define TC_COUNT32_COUNT_MASK       0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W  8) COUNT8 COUNT8 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COUNT:8;          /*!< bit:  0.. 7  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET      0x10         /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
+#define TC_COUNT8_COUNT_RESETVALUE  0x00ul       /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
+
+#define TC_COUNT8_COUNT_COUNT_Pos   0            /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk   (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
+#define TC_COUNT8_COUNT_MASK        0xFFul       /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W  8) COUNT8 COUNT8 Period Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:8;            /*!< bit:  0.. 7  Period Value                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET        0x14         /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
+#define TC_COUNT8_PER_RESETVALUE    0xFFul       /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
+
+#define TC_COUNT8_PER_PER_Pos       0            /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk       (0xFFul << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value)    (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
+#define TC_COUNT8_PER_MASK          0xFFul       /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CC:16;            /*!< bit:  0..15  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET        0x18         /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
+#define TC_COUNT16_CC_RESETVALUE    0x0000ul     /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
+
+#define TC_COUNT16_CC_CC_Pos        0            /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
+#define TC_COUNT16_CC_CC_Msk        (0xFFFFul << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value)     (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
+#define TC_COUNT16_CC_MASK          0xFFFFul     /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CC:32;            /*!< bit:  0..31  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET        0x18         /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
+#define TC_COUNT32_CC_RESETVALUE    0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
+
+#define TC_COUNT32_CC_CC_Pos        0            /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
+#define TC_COUNT32_CC_CC_Msk        (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value)     (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
+#define TC_COUNT32_CC_MASK          0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W  8) COUNT8 COUNT8 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CC:8;             /*!< bit:  0.. 7  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET         0x18         /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
+#define TC_COUNT8_CC_RESETVALUE     0x00ul       /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
+
+#define TC_COUNT8_CC_CC_Pos         0            /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
+#define TC_COUNT8_CC_CC_Msk         (0xFFul << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value)      (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
+#define TC_COUNT8_CC_MASK           0xFFul       /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT8_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W  8) COUNT8 Counter Value */
+       RoReg8                    Reserved3[0x3];
+  __IO TC_COUNT8_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W  8) COUNT8 Period Value */
+       RoReg8                    Reserved4[0x3];
+  __IO TC_COUNT8_CC_Type         CC[2];       /**< \brief Offset: 0x18 (R/W  8) COUNT8 Compare/Capture */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT16_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+       RoReg8                    Reserved3[0x6];
+  __IO TC_COUNT16_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT32_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO TC_COUNT32_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       TcCount8                  COUNT8;      /**< \brief Offset: 0x00 8-bit Counter Mode */
+       TcCount16                 COUNT16;     /**< \brief Offset: 0x00 16-bit Counter Mode */
+       TcCount32                 COUNT32;     /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc.h
new file mode 100644
index 0000000000..2f92425338
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc.h
@@ -0,0 +1,1838 @@
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC                     0x122
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
+    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
+    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
+    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
+    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
+    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
+    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
+    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE        0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST             (0x1ul << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE            (0x1ul << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk    (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define   TCC_CTRLA_RESOLUTION_NONE_Val   0x0ul  /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define   TCC_CTRLA_RESOLUTION_DITH4_Val  0x1ul  /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH5_Val  0x2ul  /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH6_Val  0x3ul  /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk     (0x7ul << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define   TCC_CTRLA_PRESCALER_DIV1_Val    0x0ul  /**< \brief (TCC_CTRLA) No division */
+#define   TCC_CTRLA_PRESCALER_DIV2_Val    0x1ul  /**< \brief (TCC_CTRLA) Divide by 2 */
+#define   TCC_CTRLA_PRESCALER_DIV4_Val    0x2ul  /**< \brief (TCC_CTRLA) Divide by 4 */
+#define   TCC_CTRLA_PRESCALER_DIV8_Val    0x3ul  /**< \brief (TCC_CTRLA) Divide by 8 */
+#define   TCC_CTRLA_PRESCALER_DIV16_Val   0x4ul  /**< \brief (TCC_CTRLA) Divide by 16 */
+#define   TCC_CTRLA_PRESCALER_DIV64_Val   0x5ul  /**< \brief (TCC_CTRLA) Divide by 64 */
+#define   TCC_CTRLA_PRESCALER_DIV256_Val  0x6ul  /**< \brief (TCC_CTRLA) Divide by 256 */
+#define   TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul  /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY          (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk     (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    0x0ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   0x1ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  0x2ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK             (0x1ul << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk         (0xFul << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK              0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR            (0x1ul << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD           (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT        (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk     (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBCLR_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk        (0x7ul << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define   TCC_CTRLBCLR_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBCLR) No action */
+#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define   TCC_CTRLBCLR_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBCLR) Force stop */
+#define   TCC_CTRLBCLR_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define   TCC_CTRLBCLR_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK           0xFFul       /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR            (0x1ul << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD           (0x1ul << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT        (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk     (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBSET_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk        (0x7ul << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define   TCC_CTRLBSET_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBSET) No action */
+#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define   TCC_CTRLBSET_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBSET) Force stop */
+#define   TCC_CTRLBSET_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
+#define   TCC_CTRLBSET_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK           0xFFul       /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
+    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
+    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
+    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
+    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
+    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
+    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
+    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
+    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
+    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
+    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
+    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
+    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
+    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
+    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
+    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
+    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
+    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
+    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE     0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST          (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE         (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB          (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS         (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT          (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT           (0x1ul << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE           (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER            (0x1ul << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk         (0xFul << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB          (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB          (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB           (0x1ul << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk        (0xFul << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
+#define TCC_SYNCBUSY_MASK           0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk          (0x3ul << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define   TCC_FCTRLA_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define   TCC_FCTRLA_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP             (0x1ul << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL             (0x1ul << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk        (0x3ul << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define   TCC_FCTRLA_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
+#define   TCC_FCTRLA_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_START      (TCC_FCTRLA_BLANK_START_Val    << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART          (0x1ul << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk         (0x3ul << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define   TCC_FCTRLA_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define   TCC_FCTRLA_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define   TCC_FCTRLA_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLA) Software halt action */
+#define   TCC_FCTRLA_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk        (0x3ul << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define   TCC_FCTRLA_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define   TCC_FCTRLA_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define   TCC_FCTRLA_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define   TCC_FCTRLA_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk      (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLA) No capture */
+#define   TCC_FCTRLA_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLA) Capture on fault */
+#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLA) Minimum capture */
+#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLA) Maximum capture */
+#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
+#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk     (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk    (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk          (0x3ul << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define   TCC_FCTRLB_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define   TCC_FCTRLB_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP             (0x1ul << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL             (0x1ul << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk        (0x3ul << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define   TCC_FCTRLB_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
+#define   TCC_FCTRLB_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_START      (TCC_FCTRLB_BLANK_START_Val    << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART          (0x1ul << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk         (0x3ul << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define   TCC_FCTRLB_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define   TCC_FCTRLB_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define   TCC_FCTRLB_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLB) Software halt action */
+#define   TCC_FCTRLB_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk        (0x3ul << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define   TCC_FCTRLB_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define   TCC_FCTRLB_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define   TCC_FCTRLB_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define   TCC_FCTRLB_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk      (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLB) No capture */
+#define   TCC_FCTRLB_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLB) Capture on fault */
+#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLB) Minimum capture */
+#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLB) Maximum capture */
+#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
+#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk     (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk    (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
+    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
+    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
+    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
+    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk        (0x3ul << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk       (0xFul << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk        (0xFFul << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk        (0xFFul << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK            0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
+    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
+    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
+    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
+    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
+    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
+    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
+    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
+    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
+    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
+    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
+    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
+    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
+    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
+    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
+    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
+    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
+    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
+    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
+    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
+    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
+    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
+    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
+    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
+    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
+    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
+    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
+    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk         (0xFFul << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk         (0xFFul << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk       (0xFFul << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK            0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN          (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD           (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK            0x05ul       /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
+    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
+    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
+    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
+    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
+    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
+    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
+    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
+    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
+    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
+    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
+    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
+    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
+    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
+    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
+    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
+    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
+    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk       (0x7ul << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define   TCC_EVCTRL_EVACT0_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   0x2ul  /**< \brief (TCC_EVCTRL) Count on event */
+#define   TCC_EVCTRL_EVACT0_START_Val     0x3ul  /**< \brief (TCC_EVCTRL) Start counter on event */
+#define   TCC_EVCTRL_EVACT0_INC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNT_Val     0x5ul  /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define   TCC_EVCTRL_EVACT0_STAMP_Val     0x6ul  /**< \brief (TCC_EVCTRL) Stamp capture */
+#define   TCC_EVCTRL_EVACT0_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_STAMP     (TCC_EVCTRL_EVACT0_STAMP_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk       (0x7ul << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define   TCC_EVCTRL_EVACT1_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT1_DIR_Val       0x2ul  /**< \brief (TCC_EVCTRL) Direction control */
+#define   TCC_EVCTRL_EVACT1_STOP_Val      0x3ul  /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define   TCC_EVCTRL_EVACT1_DEC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define   TCC_EVCTRL_EVACT1_PPW_Val       0x5ul  /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define   TCC_EVCTRL_EVACT1_PWP_Val       0x6ul  /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define   TCC_EVCTRL_EVACT1_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk       (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define   TCC_EVCTRL_CNTSEL_START_Val     0x0ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define   TCC_EVCTRL_CNTSEL_END_Val       0x1ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   0x2ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  0x3ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO            (0x1ul << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO            (0x1ul << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO            (0x1ul << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk        (0x3ul << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk         (0x3ul << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk         (0xFul << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk         (0xFul << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK             0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF            (0x1ul << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG            (0x1ul << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT            (0x1ul << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR            (0x1ul << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_UFS_Pos        10           /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENCLR_UFS            (0x1ul << TCC_INTENCLR_UFS_Pos)
+#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS            (0x1ul << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA         (0x1ul << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB         (0x1ul << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0         (0x1ul << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1         (0x1ul << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk         (0xFul << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK           0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF            (0x1ul << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG            (0x1ul << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT            (0x1ul << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR            (0x1ul << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_UFS_Pos        10           /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENSET_UFS            (0x1ul << TCC_INTENSET_UFS_Pos)
+#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS            (0x1ul << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA         (0x1ul << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB         (0x1ul << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0         (0x1ul << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1         (0x1ul << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk         (0xFul << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK           0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
+    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
+    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
+    __I uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    __I uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault       */
+    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
+    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
+    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
+    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
+    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
+    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
+    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
+    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
+    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF             (0x1ul << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG             (0x1ul << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT             (0x1ul << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR             (0x1ul << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_UFS_Pos         10           /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
+#define TCC_INTFLAG_UFS             (0x1ul << TCC_INTFLAG_UFS_Pos)
+#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS             (0x1ul << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA          (0x1ul << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB          (0x1ul << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0          (0x1ul << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1          (0x1ul << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk          (0xFul << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK            0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
+    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
+    uint32_t UFS:1;            /*!< bit:      2  Non-Recoverable Update Fault State */
+    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
+    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
+    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
+    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
+    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
+    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
+    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
+    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
+    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
+    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
+    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
+    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
+    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
+    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
+    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE       0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP             (0x1ul << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX              (0x1ul << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_UFS_Pos          2            /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */
+#define TCC_STATUS_UFS              (0x1ul << TCC_STATUS_UFS_Pos)
+#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS              (0x1ul << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE            (0x1ul << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV           (0x1ul << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV           (0x1ul << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV            (0x1ul << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN         (0x1ul << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN         (0x1ul << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN         (0x1ul << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN         (0x1ul << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA           (0x1ul << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB           (0x1ul << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0           (0x1ul << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1           (0x1ul << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk         (0xFul << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
+#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk          (0xFul << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK             0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK        0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk         (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK              0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
+    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
+    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
+    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
+    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
+    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
+    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
+    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
+    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
+    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
+    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
+    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
+    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
+    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
+    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
+    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
+    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE         0x0000ul     /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk            (0xFFul << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk            (0xFFul << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK               0xFFFFul     /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
+    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
+    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
+    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
+    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
+    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
+    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
+    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
+    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
+    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
+    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE         0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk        (0x7ul << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define   TCC_WAVE_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TCC_WAVE) Normal frequency */
+#define   TCC_WAVE_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TCC_WAVE) Match frequency */
+#define   TCC_WAVE_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TCC_WAVE) Normal PWM */
+#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVE) Dual-slope critical */
+#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   0x5ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     0x6ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVE_WAVEGEN_DSTOP_Val      0x7ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk           (0x3ul << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define   TCC_WAVE_RAMP_RAMP1_Val         0x0ul  /**< \brief (TCC_WAVE) RAMP1 operation */
+#define   TCC_WAVE_RAMP_RAMP2A_Val        0x1ul  /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2_Val         0x2ul  /**< \brief (TCC_WAVE) RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2C_Val        0x3ul  /**< \brief (TCC_WAVE) Critical RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN            (0x1ul << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk         (0xFul << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk            (0xFul << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk           (0xFul << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK               0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
+#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
+#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk       (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
+#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
+#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk       (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
+#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
+#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk       (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk             (0xFFFFFFul << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK                0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
+#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
+#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk         (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
+#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
+#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk         (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
+#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
+#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk         (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk               (0xFFFFFFul << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK                 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
+    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
+    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
+    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
+    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
+    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
+    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
+    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
+    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
+    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
+    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
+    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
+    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
+    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
+    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
+    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
+    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE        0x0000ul     /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk          (0xFFul << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
+#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk          (0xFFul << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
+#define TCC_PATTB_MASK              0xFFFFul     /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
+    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
+    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
+    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
+    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
+    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
+    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
+    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
+    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
+    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
+    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE        0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk      (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
+#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     0x0ul  /**< \brief (TCC_WAVEB) Normal frequency */
+#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     0x1ul  /**< \brief (TCC_WAVEB) Match frequency */
+#define   TCC_WAVEB_WAVEGENB_NPWM_Val     0x2ul  /**< \brief (TCC_WAVEB) Normal PWM */
+#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVEB) Dual-slope critical */
+#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   0x6ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    0x7ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk         (0x3ul << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
+#define   TCC_WAVEB_RAMPB_RAMP1_Val       0x0ul  /**< \brief (TCC_WAVEB) RAMP1 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2A_Val      0x1ul  /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2_Val       0x2ul  /**< \brief (TCC_WAVEB) RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2C_Val      0x3ul  /**< \brief (TCC_WAVEB) Critical RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2C      (TCC_WAVEB_RAMPB_RAMP2C_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB          (0x1ul << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk       (0xFul << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
+#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk          (0xFul << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
+#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk         (0xFul << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
+#define TCC_WAVEB_MASK              0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
+#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
+#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
+#define TCC_PERB_DITH4_PERB_Msk     (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
+#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
+#define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
+#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
+#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
+#define TCC_PERB_DITH5_PERB_Msk     (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
+#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
+#define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
+#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
+#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
+#define TCC_PERB_DITH6_PERB_Msk     (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
+#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
+#define TCC_PERB_DITH6_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
+
+#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
+#define TCC_PERB_PERB_Msk           (0xFFFFFFul << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
+#define TCC_PERB_MASK               0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
+#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
+#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH4_CCB_Msk       (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
+#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
+#define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
+#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
+#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH5_CCB_Msk       (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
+#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
+#define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
+#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
+#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH6_CCB_Msk       (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
+#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
+#define TCC_CCB_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
+
+#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_CCB_Msk             (0xFFFFFFul << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
+#define TCC_CCB_MASK                0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+       RoReg8                    Reserved1[0x2];
+  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+       RoReg8                    Reserved2[0x2];
+  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x1];
+  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
+  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
+  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
+  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
+       RoReg8                    Reserved4[0x2];
+  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
+  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+       RoReg8                    Reserved5[0x10];
+  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+       RoReg8                    Reserved6[0x2];
+  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h
new file mode 100644
index 0000000000..2f92425338
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h
@@ -0,0 +1,1838 @@
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC                     0x122
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
+    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
+    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
+    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
+    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
+    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
+    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
+    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE        0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST             (0x1ul << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE            (0x1ul << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk    (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define   TCC_CTRLA_RESOLUTION_NONE_Val   0x0ul  /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define   TCC_CTRLA_RESOLUTION_DITH4_Val  0x1ul  /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH5_Val  0x2ul  /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH6_Val  0x3ul  /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk     (0x7ul << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define   TCC_CTRLA_PRESCALER_DIV1_Val    0x0ul  /**< \brief (TCC_CTRLA) No division */
+#define   TCC_CTRLA_PRESCALER_DIV2_Val    0x1ul  /**< \brief (TCC_CTRLA) Divide by 2 */
+#define   TCC_CTRLA_PRESCALER_DIV4_Val    0x2ul  /**< \brief (TCC_CTRLA) Divide by 4 */
+#define   TCC_CTRLA_PRESCALER_DIV8_Val    0x3ul  /**< \brief (TCC_CTRLA) Divide by 8 */
+#define   TCC_CTRLA_PRESCALER_DIV16_Val   0x4ul  /**< \brief (TCC_CTRLA) Divide by 16 */
+#define   TCC_CTRLA_PRESCALER_DIV64_Val   0x5ul  /**< \brief (TCC_CTRLA) Divide by 64 */
+#define   TCC_CTRLA_PRESCALER_DIV256_Val  0x6ul  /**< \brief (TCC_CTRLA) Divide by 256 */
+#define   TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul  /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY          (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk     (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    0x0ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   0x1ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  0x2ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK             (0x1ul << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk         (0xFul << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK              0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR            (0x1ul << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD           (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT        (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk     (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBCLR_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk        (0x7ul << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define   TCC_CTRLBCLR_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBCLR) No action */
+#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define   TCC_CTRLBCLR_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBCLR) Force stop */
+#define   TCC_CTRLBCLR_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define   TCC_CTRLBCLR_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK           0xFFul       /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR            (0x1ul << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD           (0x1ul << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT        (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk     (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBSET_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk        (0x7ul << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define   TCC_CTRLBSET_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBSET) No action */
+#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define   TCC_CTRLBSET_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBSET) Force stop */
+#define   TCC_CTRLBSET_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
+#define   TCC_CTRLBSET_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK           0xFFul       /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
+    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
+    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
+    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
+    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
+    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
+    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
+    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
+    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
+    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
+    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
+    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
+    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
+    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
+    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
+    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
+    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
+    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
+    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE     0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST          (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE         (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB          (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS         (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT          (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT           (0x1ul << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE           (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER            (0x1ul << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk         (0xFul << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB          (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB          (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB           (0x1ul << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk        (0xFul << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
+#define TCC_SYNCBUSY_MASK           0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk          (0x3ul << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define   TCC_FCTRLA_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define   TCC_FCTRLA_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP             (0x1ul << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL             (0x1ul << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk        (0x3ul << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define   TCC_FCTRLA_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
+#define   TCC_FCTRLA_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_START      (TCC_FCTRLA_BLANK_START_Val    << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART          (0x1ul << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk         (0x3ul << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define   TCC_FCTRLA_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define   TCC_FCTRLA_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define   TCC_FCTRLA_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLA) Software halt action */
+#define   TCC_FCTRLA_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk        (0x3ul << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define   TCC_FCTRLA_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define   TCC_FCTRLA_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define   TCC_FCTRLA_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define   TCC_FCTRLA_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk      (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLA) No capture */
+#define   TCC_FCTRLA_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLA) Capture on fault */
+#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLA) Minimum capture */
+#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLA) Maximum capture */
+#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
+#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk     (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk    (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk          (0x3ul << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define   TCC_FCTRLB_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define   TCC_FCTRLB_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP             (0x1ul << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL             (0x1ul << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk        (0x3ul << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define   TCC_FCTRLB_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
+#define   TCC_FCTRLB_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_START      (TCC_FCTRLB_BLANK_START_Val    << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART          (0x1ul << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk         (0x3ul << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define   TCC_FCTRLB_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define   TCC_FCTRLB_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define   TCC_FCTRLB_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLB) Software halt action */
+#define   TCC_FCTRLB_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk        (0x3ul << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define   TCC_FCTRLB_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define   TCC_FCTRLB_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define   TCC_FCTRLB_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define   TCC_FCTRLB_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk      (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLB) No capture */
+#define   TCC_FCTRLB_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLB) Capture on fault */
+#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLB) Minimum capture */
+#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLB) Maximum capture */
+#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
+#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk     (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk    (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
+    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
+    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
+    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
+    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk        (0x3ul << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk       (0xFul << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk        (0xFFul << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk        (0xFFul << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK            0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
+    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
+    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
+    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
+    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
+    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
+    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
+    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
+    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
+    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
+    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
+    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
+    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
+    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
+    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
+    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
+    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
+    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
+    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
+    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
+    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
+    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
+    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
+    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
+    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
+    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
+    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
+    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk         (0xFFul << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk         (0xFFul << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk       (0xFFul << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK            0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN          (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD           (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK            0x05ul       /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
+    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
+    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
+    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
+    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
+    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
+    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
+    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
+    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
+    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
+    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
+    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
+    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
+    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
+    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
+    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
+    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
+    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk       (0x7ul << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define   TCC_EVCTRL_EVACT0_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   0x2ul  /**< \brief (TCC_EVCTRL) Count on event */
+#define   TCC_EVCTRL_EVACT0_START_Val     0x3ul  /**< \brief (TCC_EVCTRL) Start counter on event */
+#define   TCC_EVCTRL_EVACT0_INC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNT_Val     0x5ul  /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define   TCC_EVCTRL_EVACT0_STAMP_Val     0x6ul  /**< \brief (TCC_EVCTRL) Stamp capture */
+#define   TCC_EVCTRL_EVACT0_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_STAMP     (TCC_EVCTRL_EVACT0_STAMP_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk       (0x7ul << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define   TCC_EVCTRL_EVACT1_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT1_DIR_Val       0x2ul  /**< \brief (TCC_EVCTRL) Direction control */
+#define   TCC_EVCTRL_EVACT1_STOP_Val      0x3ul  /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define   TCC_EVCTRL_EVACT1_DEC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define   TCC_EVCTRL_EVACT1_PPW_Val       0x5ul  /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define   TCC_EVCTRL_EVACT1_PWP_Val       0x6ul  /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define   TCC_EVCTRL_EVACT1_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk       (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define   TCC_EVCTRL_CNTSEL_START_Val     0x0ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define   TCC_EVCTRL_CNTSEL_END_Val       0x1ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   0x2ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  0x3ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO            (0x1ul << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO            (0x1ul << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO            (0x1ul << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk        (0x3ul << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk         (0x3ul << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk         (0xFul << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk         (0xFul << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK             0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF            (0x1ul << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG            (0x1ul << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT            (0x1ul << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR            (0x1ul << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_UFS_Pos        10           /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENCLR_UFS            (0x1ul << TCC_INTENCLR_UFS_Pos)
+#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS            (0x1ul << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA         (0x1ul << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB         (0x1ul << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0         (0x1ul << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1         (0x1ul << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk         (0xFul << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK           0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF            (0x1ul << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG            (0x1ul << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT            (0x1ul << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR            (0x1ul << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_UFS_Pos        10           /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENSET_UFS            (0x1ul << TCC_INTENSET_UFS_Pos)
+#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS            (0x1ul << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA         (0x1ul << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB         (0x1ul << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0         (0x1ul << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1         (0x1ul << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk         (0xFul << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK           0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
+    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
+    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
+    __I uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    __I uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault       */
+    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
+    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
+    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
+    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
+    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
+    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
+    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
+    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
+    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF             (0x1ul << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG             (0x1ul << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT             (0x1ul << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR             (0x1ul << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_UFS_Pos         10           /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
+#define TCC_INTFLAG_UFS             (0x1ul << TCC_INTFLAG_UFS_Pos)
+#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS             (0x1ul << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA          (0x1ul << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB          (0x1ul << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0          (0x1ul << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1          (0x1ul << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk          (0xFul << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK            0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
+    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
+    uint32_t UFS:1;            /*!< bit:      2  Non-Recoverable Update Fault State */
+    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
+    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
+    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
+    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
+    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
+    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
+    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
+    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
+    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
+    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
+    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
+    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
+    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
+    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
+    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE       0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP             (0x1ul << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX              (0x1ul << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_UFS_Pos          2            /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */
+#define TCC_STATUS_UFS              (0x1ul << TCC_STATUS_UFS_Pos)
+#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS              (0x1ul << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE            (0x1ul << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV           (0x1ul << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV           (0x1ul << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV            (0x1ul << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN         (0x1ul << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN         (0x1ul << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN         (0x1ul << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN         (0x1ul << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA           (0x1ul << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB           (0x1ul << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0           (0x1ul << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1           (0x1ul << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk         (0xFul << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
+#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk          (0xFul << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK             0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK        0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk         (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK              0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
+    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
+    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
+    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
+    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
+    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
+    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
+    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
+    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
+    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
+    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
+    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
+    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
+    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
+    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
+    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
+    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE         0x0000ul     /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk            (0xFFul << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk            (0xFFul << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK               0xFFFFul     /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
+    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
+    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
+    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
+    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
+    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
+    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
+    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
+    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
+    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
+    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE         0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk        (0x7ul << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define   TCC_WAVE_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TCC_WAVE) Normal frequency */
+#define   TCC_WAVE_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TCC_WAVE) Match frequency */
+#define   TCC_WAVE_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TCC_WAVE) Normal PWM */
+#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVE) Dual-slope critical */
+#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   0x5ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     0x6ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVE_WAVEGEN_DSTOP_Val      0x7ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk           (0x3ul << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define   TCC_WAVE_RAMP_RAMP1_Val         0x0ul  /**< \brief (TCC_WAVE) RAMP1 operation */
+#define   TCC_WAVE_RAMP_RAMP2A_Val        0x1ul  /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2_Val         0x2ul  /**< \brief (TCC_WAVE) RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2C_Val        0x3ul  /**< \brief (TCC_WAVE) Critical RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN            (0x1ul << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk         (0xFul << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk            (0xFul << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk           (0xFul << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK               0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
+#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
+#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk       (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
+#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
+#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk       (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
+#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
+#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk       (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk             (0xFFFFFFul << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK                0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
+#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
+#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk         (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
+#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
+#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk         (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
+#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
+#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk         (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk               (0xFFFFFFul << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK                 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
+    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
+    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
+    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
+    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
+    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
+    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
+    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
+    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
+    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
+    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
+    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
+    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
+    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
+    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
+    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
+    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE        0x0000ul     /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk          (0xFFul << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
+#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk          (0xFFul << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
+#define TCC_PATTB_MASK              0xFFFFul     /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
+    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
+    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
+    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
+    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
+    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
+    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
+    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
+    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
+    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
+    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE        0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk      (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
+#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     0x0ul  /**< \brief (TCC_WAVEB) Normal frequency */
+#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     0x1ul  /**< \brief (TCC_WAVEB) Match frequency */
+#define   TCC_WAVEB_WAVEGENB_NPWM_Val     0x2ul  /**< \brief (TCC_WAVEB) Normal PWM */
+#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVEB) Dual-slope critical */
+#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   0x6ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    0x7ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk         (0x3ul << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
+#define   TCC_WAVEB_RAMPB_RAMP1_Val       0x0ul  /**< \brief (TCC_WAVEB) RAMP1 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2A_Val      0x1ul  /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2_Val       0x2ul  /**< \brief (TCC_WAVEB) RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2C_Val      0x3ul  /**< \brief (TCC_WAVEB) Critical RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2C      (TCC_WAVEB_RAMPB_RAMP2C_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB          (0x1ul << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk       (0xFul << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
+#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk          (0xFul << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
+#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk         (0xFul << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
+#define TCC_WAVEB_MASK              0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
+#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
+#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
+#define TCC_PERB_DITH4_PERB_Msk     (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
+#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
+#define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
+#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
+#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
+#define TCC_PERB_DITH5_PERB_Msk     (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
+#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
+#define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
+#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
+#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
+#define TCC_PERB_DITH6_PERB_Msk     (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
+#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
+#define TCC_PERB_DITH6_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
+
+#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
+#define TCC_PERB_PERB_Msk           (0xFFFFFFul << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
+#define TCC_PERB_MASK               0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
+#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
+#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH4_CCB_Msk       (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
+#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
+#define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
+#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
+#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH5_CCB_Msk       (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
+#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
+#define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
+#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
+#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH6_CCB_Msk       (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
+#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
+#define TCC_CCB_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
+
+#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_CCB_Msk             (0xFFFFFFul << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
+#define TCC_CCB_MASK                0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+       RoReg8                    Reserved1[0x2];
+  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+       RoReg8                    Reserved2[0x2];
+  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x1];
+  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
+  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
+  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
+  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
+       RoReg8                    Reserved4[0x2];
+  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
+  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+       RoReg8                    Reserved5[0x10];
+  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+       RoReg8                    Reserved6[0x2];
+  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/usb.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/usb.h
new file mode 100644
index 0000000000..7a3ad226b3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/usb.h
@@ -0,0 +1,1805 @@
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_COMPONENT_
+#define _SAMD21_USB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB                     0x103
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby Mode                */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  MODE:1;           /*!< bit:      7  Operating Mode                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET            0x000        /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE        0x00ul       /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos         0            /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST             (0x1ul << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos        1            /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE            (0x1ul << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos      2            /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY          (0x1ul << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos          7            /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE              (0x1ul << USB_CTRLA_MODE_Pos)
+#define   USB_CTRLA_MODE_DEVICE_Val       0x0ul  /**< \brief (USB_CTRLA) Device Mode */
+#define   USB_CTRLA_MODE_HOST_Val         0x1ul  /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE       (USB_CTRLA_MODE_DEVICE_Val     << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST         (USB_CTRLA_MODE_HOST_Val       << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK              0x87ul       /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/   8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET         0x002        /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE     0x00ul       /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos      0            /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST          (0x1ul << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos     1            /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE         (0x1ul << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK           0x03ul       /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W  8) USB Quality Of Service -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CQOS:2;           /*!< bit:  0.. 1  Configuration Quality of Service   */
+    uint8_t  DQOS:2;           /*!< bit:  2.. 3  Data Quality of Service            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_QOSCTRL_OFFSET          0x003        /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
+#define USB_QOSCTRL_RESETVALUE      0x05ul       /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
+
+#define USB_QOSCTRL_CQOS_Pos        0            /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
+#define USB_QOSCTRL_CQOS_Msk        (0x3ul << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS(value)     (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
+#define   USB_QOSCTRL_CQOS_DISABLE_Val    0x0ul  /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define   USB_QOSCTRL_CQOS_LOW_Val        0x1ul  /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define   USB_QOSCTRL_CQOS_MEDIUM_Val     0x2ul  /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define   USB_QOSCTRL_CQOS_HIGH_Val       0x3ul  /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_CQOS_DISABLE    (USB_QOSCTRL_CQOS_DISABLE_Val  << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_LOW        (USB_QOSCTRL_CQOS_LOW_Val      << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_MEDIUM     (USB_QOSCTRL_CQOS_MEDIUM_Val   << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_HIGH       (USB_QOSCTRL_CQOS_HIGH_Val     << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_DQOS_Pos        2            /**< \brief (USB_QOSCTRL) Data Quality of Service */
+#define USB_QOSCTRL_DQOS_Msk        (0x3ul << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS(value)     (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
+#define   USB_QOSCTRL_DQOS_DISABLE_Val    0x0ul  /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define   USB_QOSCTRL_DQOS_LOW_Val        0x1ul  /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define   USB_QOSCTRL_DQOS_MEDIUM_Val     0x2ul  /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define   USB_QOSCTRL_DQOS_HIGH_Val       0x3ul  /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_DQOS_DISABLE    (USB_QOSCTRL_DQOS_DISABLE_Val  << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_LOW        (USB_QOSCTRL_DQOS_LOW_Val      << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_MEDIUM     (USB_QOSCTRL_DQOS_MEDIUM_Val   << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_HIGH       (USB_QOSCTRL_DQOS_HIGH_Val     << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_MASK            0x0Ful       /**< \brief (USB_QOSCTRL) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DETACH:1;         /*!< bit:      0  Detach                             */
+    uint16_t UPRSM:1;          /*!< bit:      1  Upstream Resume                    */
+    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration                */
+    uint16_t NREPLY:1;         /*!< bit:      4  No Reply                           */
+    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
+    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
+    uint16_t TSTPCKT:1;        /*!< bit:      7  Test packet mode                   */
+    uint16_t OPMODE2:1;        /*!< bit:      8  Specific Operational Mode          */
+    uint16_t GNAK:1;           /*!< bit:      9  Global NAK                         */
+    uint16_t LPMHDSK:2;        /*!< bit: 10..11  Link Power Management Handshake    */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET     0x008        /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul     /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0            /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH     (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos  1            /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM      (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2            /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
+#define   USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul  /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define   USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul  /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define   USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul  /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define   USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul  /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4            /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY     (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos   5            /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ       (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos   6            /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK       (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7            /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT    (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8            /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2    (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos   9            /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK       (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10           /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
+#define   USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul  /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define   USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul  /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define   USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul  /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define   USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul  /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK       0x0FFFul     /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t RESUME:1;         /*!< bit:      1  Send USB Resume                    */
+    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration for Host       */
+    uint16_t :1;               /*!< bit:      4  Reserved                           */
+    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
+    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t SOFE:1;           /*!< bit:      8  Start of Frame Generation Enable   */
+    uint16_t BUSRESET:1;       /*!< bit:      9  Send USB Reset                     */
+    uint16_t VBUSOK:1;         /*!< bit:     10  VBUS is OK                         */
+    uint16_t L1RESUME:1;       /*!< bit:     11  Send L1 Resume                     */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET       0x008        /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE   0x0000ul     /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos   1            /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME       (0x1ul << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos  2            /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk  (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
+#define   USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul  /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
+#define   USB_HOST_CTRLB_SPDCONF_FS_Val   0x3ul  /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_FS   (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos     5            /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ         (0x1ul << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos     6            /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK         (0x1ul << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos     8            /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE         (0x1ul << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9            /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET     (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos   10           /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK       (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11           /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME     (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK         0x0F6Eul     /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DADD:7;           /*!< bit:  0.. 6  Device Address                     */
+    uint8_t  ADDEN:1;          /*!< bit:      7  Device Address Enable              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET      0x00A        /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE  0x00ul       /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos    0            /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk    (0x7Ful << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
+#define USB_DEVICE_DADD_ADDEN_Pos   7            /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN       (0x1ul << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK        0xFFul       /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W  8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLENC:4;          /*!< bit:  0.. 3  Frame Length Control               */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  FLENCE:1;         /*!< bit:      7  Frame Length Control Enable        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET       0x00A        /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE   0x00ul       /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos    0            /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk    (0xFul << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
+#define USB_HOST_HSOFC_FLENCE_Pos   7            /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE       (0x1ul << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK         0x8Ful       /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/   8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET    0x00C        /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE 0x40ul       /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2            /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
+#define   USB_DEVICE_STATUS_SPEED_FS_Val  0x0ul  /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define   USB_DEVICE_STATUS_SPEED_HS_Val  0x1ul  /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define   USB_DEVICE_STATUS_SPEED_LS_Val  0x2ul  /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define USB_DEVICE_STATUS_SPEED_FS  (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_HS  (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_LS  (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6            /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
+#define   USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul  /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define   USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul  /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define   USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul  /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK      0xCCul       /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W  8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET      0x00C        /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE  0x00ul       /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos   2            /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk   (0x3ul << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
+#define USB_HOST_STATUS_LINESTATE_Pos 6            /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
+#define USB_HOST_STATUS_MASK        0xCCul       /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/   8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FSMSTATE:7;       /*!< bit:  0.. 6  Fine State Machine Status          */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET        0x00D        /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE    0x01ul       /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos  0            /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk  (0x7Ful << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
+#define   USB_FSMSTATUS_FSMSTATE_OFF_Val  0x1ul  /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define   USB_FSMSTATUS_FSMSTATE_ON_Val   0x2ul  /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define   USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul  /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define   USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul  /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define   USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul  /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define   USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul  /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define   USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul  /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_OFF  (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_ON   (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK          0x7Ful       /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/  16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
+    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
+    uint16_t :1;               /*!< bit:     14  Reserved                           */
+    uint16_t FNCERR:1;         /*!< bit:     15  Frame Number CRC Error             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET      0x010        /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE  0x0000ul     /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos   0            /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk   (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
+#define USB_DEVICE_FNUM_FNUM_Pos    3            /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk    (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
+#define USB_DEVICE_FNUM_FNCERR_Pos  15           /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR      (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK        0xBFFFul     /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
+    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET        0x010        /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE    0x0000ul     /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos     0            /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk     (0x7ul << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value)  (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
+#define USB_HOST_FNUM_FNUM_Pos      3            /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk      (0x7FFul << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value)   (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
+#define USB_HOST_FNUM_MASK          0x3FFFul     /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/   8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLENHIGH:8;       /*!< bit:  0.. 7  Frame Length                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET    0x012        /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul       /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0            /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
+#define USB_HOST_FLENHIGH_MASK      0xFFul       /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
+    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
+    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
+    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
+    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET  0x014        /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF    (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF     (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST   (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP  (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM   (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM   (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK    0x03FFul     /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Disable */
+    uint16_t RST:1;            /*!< bit:      3  BUS Reset Interrupt Disable        */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Disable          */
+    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to Device Interrupt Disable */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from Device Interrupt Disable */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Disable       */
+    uint16_t DCONN:1;          /*!< bit:      8  Device Connection Interrupt Disable */
+    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Disable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET    0x014        /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos  2            /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF      (0x1ul << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos   3            /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST       (0x1ul << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP    (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM     (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM     (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER   (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8            /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN     (0x1ul << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9            /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC     (0x1ul << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK      0x03FCul     /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
+    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
+    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
+    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
+    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET  0x018        /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF    (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF     (0x1ul << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST   (0x1ul << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP  (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM   (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM   (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK    0x03FFul     /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Enable */
+    uint16_t RST:1;            /*!< bit:      3  Bus Reset Interrupt Enable         */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to the Device Interrupt Enable */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume fromthe device Interrupt Enable */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t DCONN:1;          /*!< bit:      8  Link Power Management Interrupt Enable */
+    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET    0x018        /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos  2            /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF      (0x1ul << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos   3            /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST       (0x1ul << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP    (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM     (0x1ul << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM     (0x1ul << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER   (0x1ul << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8            /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN     (0x1ul << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9            /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC     (0x1ul << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK      0x03FCul     /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t SUSPEND:1;        /*!< bit:      0  Suspend                            */
+    __I uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame in High Speed Mode */
+    __I uint16_t SOF:1;            /*!< bit:      2  Start Of Frame                     */
+    __I uint16_t EORST:1;          /*!< bit:      3  End of Reset                       */
+    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
+    __I uint16_t EORSM:1;          /*!< bit:      5  End Of Resume                      */
+    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume                    */
+    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
+    __I uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet      */
+    __I uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend      */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET   0x01C        /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND  (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF     (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos  2            /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF      (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3            /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST    (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP   (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM    (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM    (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER  (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET  (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP  (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK     0x03FFul     /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    __I uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame                */
+    __I uint16_t RST:1;            /*!< bit:      3  Bus Reset                          */
+    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
+    __I uint16_t DNRSM:1;          /*!< bit:      5  Downstream                         */
+    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from the Device    */
+    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
+    __I uint16_t DCONN:1;          /*!< bit:      8  Device Connection                  */
+    __I uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection               */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET     0x01C        /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos   2            /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF       (0x1ul << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos    3            /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST        (0x1ul << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP     (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos  5            /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM      (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos  6            /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM      (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER    (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos  8            /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN      (0x1ul << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos  9            /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC      (0x1ul << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK       0x03FCul     /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/  16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EPINT0:1;         /*!< bit:      0  End Point 0 Interrupt              */
+    uint16_t EPINT1:1;         /*!< bit:      1  End Point 1 Interrupt              */
+    uint16_t EPINT2:1;         /*!< bit:      2  End Point 2 Interrupt              */
+    uint16_t EPINT3:1;         /*!< bit:      3  End Point 3 Interrupt              */
+    uint16_t EPINT4:1;         /*!< bit:      4  End Point 4 Interrupt              */
+    uint16_t EPINT5:1;         /*!< bit:      5  End Point 5 Interrupt              */
+    uint16_t EPINT6:1;         /*!< bit:      6  End Point 6 Interrupt              */
+    uint16_t EPINT7:1;         /*!< bit:      7  End Point 7 Interrupt              */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t EPINT:8;          /*!< bit:  0.. 7  End Point x Interrupt              */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020        /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
+#define USB_DEVICE_EPINTSMRY_MASK   0x00FFul     /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/  16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EPINT0:1;         /*!< bit:      0  Pipe 0 Interrupt                   */
+    uint16_t EPINT1:1;         /*!< bit:      1  Pipe 1 Interrupt                   */
+    uint16_t EPINT2:1;         /*!< bit:      2  Pipe 2 Interrupt                   */
+    uint16_t EPINT3:1;         /*!< bit:      3  Pipe 3 Interrupt                   */
+    uint16_t EPINT4:1;         /*!< bit:      4  Pipe 4 Interrupt                   */
+    uint16_t EPINT5:1;         /*!< bit:      5  Pipe 5 Interrupt                   */
+    uint16_t EPINT6:1;         /*!< bit:      6  Pipe 6 Interrupt                   */
+    uint16_t EPINT7:1;         /*!< bit:      7  Pipe 7 Interrupt                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t EPINT:8;          /*!< bit:  0.. 7  Pipe x Interrupt                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET    0x020        /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0    (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1            /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1    (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2            /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2    (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3            /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3    (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4            /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4    (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5            /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5    (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6            /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6    (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7            /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7    (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
+#define USB_HOST_PINTSMRY_MASK      0x00FFul     /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DESCADD:32;       /*!< bit:  0..31  Descriptor Address Value           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET          0x024        /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE      0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos     0            /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk     (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value)  (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
+#define USB_DESCADD_MASK            0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t TRANSP:5;         /*!< bit:  0.. 4  USB Pad Transp calibration         */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t TRANSN:5;         /*!< bit:  6..10  USB Pad Transn calibration         */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t TRIM:3;           /*!< bit: 12..14  USB Pad Trim calibration           */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET           0x028        /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE       0x0000ul     /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos       0            /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk       (0x1Ful << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value)    (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
+#define USB_PADCAL_TRANSN_Pos       6            /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk       (0x1Ful << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value)    (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
+#define USB_PADCAL_TRIM_Pos         12           /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk         (0x7ul << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value)      (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
+#define USB_PADCAL_MASK             0x77DFul     /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EPTYPE0:3;        /*!< bit:  0.. 2  End Point Type0                    */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EPTYPE1:3;        /*!< bit:  4.. 6  End Point Type1                    */
+    uint8_t  NYETDIS:1;        /*!< bit:      7  NYET Token Disable                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET     0x100        /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0            /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4            /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7            /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS    (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK       0xF7ul       /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W  8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PTOKEN:2;         /*!< bit:  0.. 1  Pipe Token                         */
+    uint8_t  BK:1;             /*!< bit:      2  Pipe Bank                          */
+    uint8_t  PTYPE:3;          /*!< bit:  3.. 5  Pipe Type                          */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET        0x100        /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE    0x00ul       /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos    0            /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk    (0x3ul << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
+#define USB_HOST_PCFG_BK_Pos        2            /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK            (0x1ul << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos     3            /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk     (0x7ul << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value)  (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
+#define USB_HOST_PCFG_MASK          0x3Ful       /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W  8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BITINTERVAL:8;    /*!< bit:  0.. 7  Bit Interval                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET   0x103        /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul       /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0            /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
+#define USB_HOST_BINTERVAL_MASK     0xFFul       /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Clear              */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Clear               */
+    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank Clear                  */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Clear              */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Clear              */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Clear              */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104        /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul       /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W  8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle clear                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank clear                  */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Clear                  */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET  0x104        /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL    (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK   (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY  (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY  (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK    0xD5ul       /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Set                */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Set                 */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Set                */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Set                */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Set                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105        /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul       /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W  8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle Set                    */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Set                    */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET  0x105        /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL    (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK   (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY  (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY  (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK    0xD5ul       /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/   8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle Out                    */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle In                     */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request                    */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request                    */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request                    */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET  0x106        /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN  (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK   (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY  (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY  (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK    0xF7ul       /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/   8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle                        */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze                        */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET     0x106        /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos   0            /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL       (0x1ul << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos  2            /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK      (0x1ul << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE    (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY     (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY     (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK       0xD5ul       /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0                */
+    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1                */
+    __I uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0                       */
+    __I uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1                       */
+    __I uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup                     */
+    __I uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out                     */
+    __I uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out                     */
+    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x                */
+    __I uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x                       */
+    __I uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    __I uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out                     */
+    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107        /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP  (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
+#define USB_DEVICE_EPINTFLAG_MASK   0x7Ful       /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Flag */
+    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Flag */
+    __I uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Flag          */
+    __I uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Flag          */
+    __I uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Flag     */
+    __I uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Flag               */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Flag */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET    0x107        /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0    (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1    (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL    (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos  3            /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR      (0x1ul << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTFLAG) Transmit  Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP     (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5            /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL     (0x1ul << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK      0x3Ful       /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Disable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Disable */
+    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Disable     */
+    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Disable     */
+    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Disable   */
+    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/Out Interrupt Disable   */
+    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/Out Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Disable */
+    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Disable     */
+    uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/Out Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108        /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
+#define USB_DEVICE_EPINTENCLR_MASK  0x7Ful       /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Disable        */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Disable        */
+    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Disable       */
+    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Disable       */
+    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Disable  */
+    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Disable            */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Disable        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET   0x108        /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0   (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1   (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL   (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3            /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR     (0x1ul << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENCLR) Transmit  Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP    (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5            /**< \brief (USB_HOST_PINTENCLR) Stall Interrupt Disable */
+#define USB_HOST_PINTENCLR_STALL    (0x1ul << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK     0x3Ful       /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
+    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Enable      */
+    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Enable      */
+    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Enable    */
+    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out Interrupt enable    */
+    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out Interrupt enable    */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
+    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Enable      */
+    uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out Interrupt enable    */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109        /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
+#define USB_DEVICE_EPINTENSET_MASK  0x7Ful       /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
+    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Enable        */
+    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Enable        */
+    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Enable   */
+    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Enable             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET   0x109        /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0   (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1   (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL   (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3            /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR     (0x1ul << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENSET) Transmit  Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP    (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5            /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL    (0x1ul << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK     0x3Ful       /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET      0x000        /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos    0            /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk    (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
+#define USB_DEVICE_ADDR_MASK        0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET        0x000        /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos      0            /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk      (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value)   (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
+#define USB_HOST_ADDR_MASK          0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
+    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
+    uint32_t SIZE:3;           /*!< bit: 28..30  Enpoint size                       */
+    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET   0x004        /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28           /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK     0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
+    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
+    uint32_t SIZE:3;           /*!< bit: 28..30  Pipe size                          */
+    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET     0x004        /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_HOST_PCKSIZE_SIZE_Pos   28           /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk   (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP   (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK       0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
+    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET    0x008        /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0            /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
+#define USB_DEVICE_EXTREG_MASK      0x7FFFul     /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
+    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET      0x008        /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos  0            /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk  (0xFul << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
+#define USB_HOST_EXTREG_MASK        0x7FFFul     /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
+    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A        /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK   0x03ul       /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W  8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
+    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET   0x00A        /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR   (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK     0x03ul       /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PDADDR:7;         /*!< bit:  0.. 6  Pipe Device Adress                 */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t PEPNUM:4;         /*!< bit:  8..11  Pipe Endpoint Number               */
+    uint16_t PERMAX:4;         /*!< bit: 12..15  Pipe Error Max Number              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET   0x00C        /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12           /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
+#define USB_HOST_CTRL_PIPE_MASK     0xFF7Ful     /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DTGLER:1;         /*!< bit:      0  Data Toggle Error                  */
+    uint16_t DAPIDER:1;        /*!< bit:      1  Data PID Error                     */
+    uint16_t PIDER:1;          /*!< bit:      2  PID Error                          */
+    uint16_t TOUTER:1;         /*!< bit:      3  Time Out Error                     */
+    uint16_t CRC16ER:1;        /*!< bit:      4  CRC16 Error                        */
+    uint16_t ERCNT:3;          /*!< bit:  5.. 7  Pipe Error Count                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E        /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0            /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1            /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2            /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER  (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3            /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4            /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5            /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
+#define USB_HOST_STATUS_PIPE_MASK   0x00FFul     /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_DEVICE_ADDR_Type      ADDR;        /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+  __IO USB_DEVICE_PCKSIZE_Type   PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+  __IO USB_DEVICE_EXTREG_Type    EXTREG;      /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+  __IO USB_DEVICE_STATUS_BK_Type STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+       RoReg8                    Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_HOST_ADDR_Type        ADDR;        /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+  __IO USB_HOST_PCKSIZE_Type     PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+  __IO USB_HOST_EXTREG_Type      EXTREG;      /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+  __IO USB_HOST_STATUS_BK_Type   STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) HOST_DESC_BANK Host Bank, Status of Bank */
+       RoReg8                    Reserved1[0x1];
+  __IO USB_HOST_CTRL_PIPE_Type   CTRL_PIPE;   /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+  __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_DEVICE_EPCFG_Type     EPCFG;       /**< \brief Offset: 0x000 (R/W  8) DEVICE_ENDPOINT End Point Configuration */
+       RoReg8                    Reserved1[0x3];
+  __O  USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+  __O  USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Set */
+  __I  USB_DEVICE_EPSTATUS_Type  EPSTATUS;    /**< \brief Offset: 0x006 (R/   8) DEVICE_ENDPOINT End Point Pipe Status */
+  __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG;   /**< \brief Offset: 0x007 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Flag */
+  __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR;  /**< \brief Offset: 0x008 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+  __IO USB_DEVICE_EPINTENSET_Type EPINTENSET;  /**< \brief Offset: 0x009 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+       RoReg8                    Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_HOST_PCFG_Type        PCFG;        /**< \brief Offset: 0x000 (R/W  8) HOST_PIPE End Point Configuration */
+       RoReg8                    Reserved1[0x2];
+  __IO USB_HOST_BINTERVAL_Type   BINTERVAL;   /**< \brief Offset: 0x003 (R/W  8) HOST_PIPE Bus Access Period of Pipe */
+  __O  USB_HOST_PSTATUSCLR_Type  PSTATUSCLR;  /**< \brief Offset: 0x004 ( /W  8) HOST_PIPE End Point Pipe Status Clear */
+  __O  USB_HOST_PSTATUSSET_Type  PSTATUSSET;  /**< \brief Offset: 0x005 ( /W  8) HOST_PIPE End Point Pipe Status Set */
+  __I  USB_HOST_PSTATUS_Type     PSTATUS;     /**< \brief Offset: 0x006 (R/   8) HOST_PIPE End Point Pipe Status */
+  __IO USB_HOST_PINTFLAG_Type    PINTFLAG;    /**< \brief Offset: 0x007 (R/W  8) HOST_PIPE Pipe Interrupt Flag */
+  __IO USB_HOST_PINTENCLR_Type   PINTENCLR;   /**< \brief Offset: 0x008 (R/W  8) HOST_PIPE Pipe Interrupt Flag Clear */
+  __IO USB_HOST_PINTENSET_Type   PINTENSET;   /**< \brief Offset: 0x009 (R/W  8) HOST_PIPE Pipe Interrupt Flag Set */
+       RoReg8                    Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x1];
+  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
+  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
+       RoReg8                    Reserved2[0x4];
+  __IO USB_DEVICE_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+  __IO USB_DEVICE_DADD_Type      DADD;        /**< \brief Offset: 0x00A (R/W  8) DEVICE Device Address */
+       RoReg8                    Reserved3[0x1];
+  __I  USB_DEVICE_STATUS_Type    STATUS;      /**< \brief Offset: 0x00C (R/   8) DEVICE Status */
+  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
+       RoReg8                    Reserved4[0x2];
+  __I  USB_DEVICE_FNUM_Type      FNUM;        /**< \brief Offset: 0x010 (R/  16) DEVICE Device Frame Number */
+       RoReg8                    Reserved5[0x2];
+  __IO USB_DEVICE_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+       RoReg8                    Reserved6[0x2];
+  __IO USB_DEVICE_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+       RoReg8                    Reserved7[0x2];
+  __IO USB_DEVICE_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+       RoReg8                    Reserved8[0x2];
+  __I  USB_DEVICE_EPINTSMRY_Type EPINTSMRY;   /**< \brief Offset: 0x020 (R/  16) DEVICE End Point Interrupt Summary */
+       RoReg8                    Reserved9[0x2];
+  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+       RoReg8                    Reserved10[0xD6];
+       UsbDeviceEndpoint         DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x1];
+  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
+  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
+       RoReg8                    Reserved2[0x4];
+  __IO USB_HOST_CTRLB_Type       CTRLB;       /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+  __IO USB_HOST_HSOFC_Type       HSOFC;       /**< \brief Offset: 0x00A (R/W  8) HOST Host Start Of Frame Control */
+       RoReg8                    Reserved3[0x1];
+  __IO USB_HOST_STATUS_Type      STATUS;      /**< \brief Offset: 0x00C (R/W  8) HOST Status */
+  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
+       RoReg8                    Reserved4[0x2];
+  __IO USB_HOST_FNUM_Type        FNUM;        /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+  __I  USB_HOST_FLENHIGH_Type    FLENHIGH;    /**< \brief Offset: 0x012 (R/   8) HOST Host Frame Length */
+       RoReg8                    Reserved5[0x1];
+  __IO USB_HOST_INTENCLR_Type    INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+       RoReg8                    Reserved6[0x2];
+  __IO USB_HOST_INTENSET_Type    INTENSET;    /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+       RoReg8                    Reserved7[0x2];
+  __IO USB_HOST_INTFLAG_Type     INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+       RoReg8                    Reserved8[0x2];
+  __I  USB_HOST_PINTSMRY_Type    PINTSMRY;    /**< \brief Offset: 0x020 (R/  16) HOST Pipe Interrupt Summary */
+       RoReg8                    Reserved9[0x2];
+  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+       RoReg8                    Reserved10[0xD6];
+       UsbHostPipe               HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+       UsbDeviceDescBank         DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+       UsbHostDescBank           HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       UsbDevice                 DEVICE;      /**< \brief Offset: 0x000 USB is Device */
+       UsbHost                   HOST;        /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_USB_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/wdt.h
new file mode 100644
index 0000000000..89f4796c6d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/wdt.h
@@ -0,0 +1,303 @@
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_COMPONENT_
+#define _SAMD21_WDT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2203
+#define REV_WDT                     0x200
+
+/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  WEN:1;            /*!< bit:      2  Watchdog Timer Window Mode Enable  */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ALWAYSON:1;       /*!< bit:      7  Always-On                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRL_OFFSET             0x0          /**< \brief (WDT_CTRL offset) Control */
+#define WDT_CTRL_RESETVALUE         0x00ul       /**< \brief (WDT_CTRL reset_value) Control */
+
+#define WDT_CTRL_ENABLE_Pos         1            /**< \brief (WDT_CTRL) Enable */
+#define WDT_CTRL_ENABLE             (0x1ul << WDT_CTRL_ENABLE_Pos)
+#define WDT_CTRL_WEN_Pos            2            /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
+#define WDT_CTRL_WEN                (0x1ul << WDT_CTRL_WEN_Pos)
+#define WDT_CTRL_ALWAYSON_Pos       7            /**< \brief (WDT_CTRL) Always-On */
+#define WDT_CTRL_ALWAYSON           (0x1ul << WDT_CTRL_ALWAYSON_Pos)
+#define WDT_CTRL_MASK               0x86ul       /**< \brief (WDT_CTRL) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W  8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:4;            /*!< bit:  0.. 3  Time-Out Period                    */
+    uint8_t  WINDOW:4;         /*!< bit:  4.. 7  Window Mode Time-Out Period        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET           0x1          /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE       0xBBul       /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos          0            /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk          (0xFul << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value)       (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
+#define   WDT_CONFIG_PER_8_Val            0x0ul  /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_PER_16_Val           0x1ul  /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_PER_32_Val           0x2ul  /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_PER_64_Val           0x3ul  /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_PER_128_Val          0x4ul  /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_PER_256_Val          0x5ul  /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_PER_512_Val          0x6ul  /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_PER_1K_Val           0x7ul  /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_PER_2K_Val           0x8ul  /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_PER_4K_Val           0x9ul  /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_PER_8K_Val           0xAul  /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_PER_16K_Val          0xBul  /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_8            (WDT_CONFIG_PER_8_Val          << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16           (WDT_CONFIG_PER_16_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_32           (WDT_CONFIG_PER_32_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_64           (WDT_CONFIG_PER_64_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_128          (WDT_CONFIG_PER_128_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_256          (WDT_CONFIG_PER_256_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_512          (WDT_CONFIG_PER_512_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_1K           (WDT_CONFIG_PER_1K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_2K           (WDT_CONFIG_PER_2K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_4K           (WDT_CONFIG_PER_4K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_8K           (WDT_CONFIG_PER_8K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16K          (WDT_CONFIG_PER_16K_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos       4            /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk       (0xFul << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value)    (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
+#define   WDT_CONFIG_WINDOW_8_Val         0x0ul  /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_WINDOW_16_Val        0x1ul  /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_WINDOW_32_Val        0x2ul  /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_WINDOW_64_Val        0x3ul  /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_WINDOW_128_Val       0x4ul  /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_WINDOW_256_Val       0x5ul  /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_WINDOW_512_Val       0x6ul  /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_WINDOW_1K_Val        0x7ul  /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_WINDOW_2K_Val        0x8ul  /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_WINDOW_4K_Val        0x9ul  /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_WINDOW_8K_Val        0xAul  /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_WINDOW_16K_Val       0xBul  /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_8         (WDT_CONFIG_WINDOW_8_Val       << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16        (WDT_CONFIG_WINDOW_16_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_32        (WDT_CONFIG_WINDOW_32_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_64        (WDT_CONFIG_WINDOW_64_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_128       (WDT_CONFIG_WINDOW_128_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_256       (WDT_CONFIG_WINDOW_256_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_512       (WDT_CONFIG_WINDOW_512_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_1K        (WDT_CONFIG_WINDOW_1K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_2K        (WDT_CONFIG_WINDOW_2K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_4K        (WDT_CONFIG_WINDOW_4K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_8K        (WDT_CONFIG_WINDOW_8K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16K       (WDT_CONFIG_WINDOW_16K_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK             0xFFul       /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W  8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EWOFFSET:4;       /*!< bit:  0.. 3  Early Warning Interrupt Time Offset */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET           0x2          /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE       0x0Bul       /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos     0            /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk     (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value)  (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
+#define   WDT_EWCTRL_EWOFFSET_8_Val       0x0ul  /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_16_Val      0x1ul  /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_32_Val      0x2ul  /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_64_Val      0x3ul  /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_128_Val     0x4ul  /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_256_Val     0x5ul  /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_512_Val     0x6ul  /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_1K_Val      0x7ul  /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_2K_Val      0x8ul  /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_4K_Val      0x9ul  /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_8K_Val      0xAul  /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_16K_Val     0xBul  /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8       (WDT_EWCTRL_EWOFFSET_8_Val     << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16      (WDT_EWCTRL_EWOFFSET_16_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_32      (WDT_EWCTRL_EWOFFSET_32_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_64      (WDT_EWCTRL_EWOFFSET_64_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_128     (WDT_EWCTRL_EWOFFSET_128_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_256     (WDT_EWCTRL_EWOFFSET_256_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_512     (WDT_EWCTRL_EWOFFSET_512_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_1K      (WDT_EWCTRL_EWOFFSET_1K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_2K      (WDT_EWCTRL_EWOFFSET_2K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_4K      (WDT_EWCTRL_EWOFFSET_4K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_8K      (WDT_EWCTRL_EWOFFSET_8K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16K     (WDT_EWCTRL_EWOFFSET_16K_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK             0x0Ful       /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET         0x4          /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE     0x00ul       /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos         0            /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW             (0x1ul << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK           0x01ul       /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET         0x5          /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE     0x00ul       /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos         0            /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW             (0x1ul << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK           0x01ul       /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  EW:1;             /*!< bit:      0  Early Warning                      */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET          0x6          /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE      0x00ul       /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos          0            /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW              (0x1ul << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK            0x01ul       /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_STATUS_OFFSET           0x7          /**< \brief (WDT_STATUS offset) Status */
+#define WDT_STATUS_RESETVALUE       0x00ul       /**< \brief (WDT_STATUS reset_value) Status */
+
+#define WDT_STATUS_SYNCBUSY_Pos     7            /**< \brief (WDT_STATUS) Synchronization Busy */
+#define WDT_STATUS_SYNCBUSY         (0x1ul << WDT_STATUS_SYNCBUSY_Pos)
+#define WDT_STATUS_MASK             0x80ul       /**< \brief (WDT_STATUS) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W  8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CLEAR:8;          /*!< bit:  0.. 7  Watchdog Clear                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET            0x8          /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE        0x00ul       /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos         0            /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk         (0xFFul << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value)      (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
+#define   WDT_CLEAR_CLEAR_KEY_Val         0xA5ul  /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY         (WDT_CLEAR_CLEAR_KEY_Val       << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK              0xFFul       /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO WDT_CTRL_Type             CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+  __IO WDT_CONFIG_Type           CONFIG;      /**< \brief Offset: 0x1 (R/W  8) Configuration */
+  __IO WDT_EWCTRL_Type           EWCTRL;      /**< \brief Offset: 0x2 (R/W  8) Early Warning Interrupt Control */
+       RoReg8                    Reserved1[0x1];
+  __IO WDT_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO WDT_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO WDT_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+  __I  WDT_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
+  __O  WDT_CLEAR_Type            CLEAR;       /**< \brief Offset: 0x8 ( /W  8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_WDT_COMPONENT_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac.h
new file mode 100644
index 0000000000..d4ea692e12
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_INSTANCE_
+#define _SAMD21_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA               (0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC             (0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL             (0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0           (0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0             (0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (0x42004421U) /**< \brief (AC) Scaler 1 */
+#else
+#define REG_AC_CTRLA               (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC             (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL             (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0           (*(RwReg  *)0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (*(RwReg  *)0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0             (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_CMP_NUM                  2        // Number of comparators
+#define AC_GCLK_ID_ANA              32       // Index of Generic Clock for analog
+#define AC_GCLK_ID_DIG              31       // Index of Generic Clock for digital
+#define AC_NUM_CMP                  2       
+#define AC_PAIRS                    1        // Number of pairs of comparators
+
+#endif /* _SAMD21_AC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac1.h
new file mode 100644
index 0000000000..02631053a1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac1.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AC1
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC1_INSTANCE_
+#define _SAMD21_AC1_INSTANCE_
+
+/* ========== Register definition for AC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC1_CTRLA              (0x42005400U) /**< \brief (AC1) Control A */
+#define REG_AC1_CTRLB              (0x42005401U) /**< \brief (AC1) Control B */
+#define REG_AC1_EVCTRL             (0x42005402U) /**< \brief (AC1) Event Control */
+#define REG_AC1_INTENCLR           (0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */
+#define REG_AC1_INTENSET           (0x42005405U) /**< \brief (AC1) Interrupt Enable Set */
+#define REG_AC1_INTFLAG            (0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */
+#define REG_AC1_STATUSA            (0x42005408U) /**< \brief (AC1) Status A */
+#define REG_AC1_STATUSB            (0x42005409U) /**< \brief (AC1) Status B */
+#define REG_AC1_STATUSC            (0x4200540AU) /**< \brief (AC1) Status C */
+#define REG_AC1_WINCTRL            (0x4200540CU) /**< \brief (AC1) Window Control */
+#define REG_AC1_COMPCTRL0          (0x42005410U) /**< \brief (AC1) Comparator Control 0 */
+#define REG_AC1_COMPCTRL1          (0x42005414U) /**< \brief (AC1) Comparator Control 1 */
+#define REG_AC1_SCALER0            (0x42005420U) /**< \brief (AC1) Scaler 0 */
+#define REG_AC1_SCALER1            (0x42005421U) /**< \brief (AC1) Scaler 1 */
+#else
+#define REG_AC1_CTRLA              (*(RwReg8 *)0x42005400U) /**< \brief (AC1) Control A */
+#define REG_AC1_CTRLB              (*(WoReg8 *)0x42005401U) /**< \brief (AC1) Control B */
+#define REG_AC1_EVCTRL             (*(RwReg16*)0x42005402U) /**< \brief (AC1) Event Control */
+#define REG_AC1_INTENCLR           (*(RwReg8 *)0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */
+#define REG_AC1_INTENSET           (*(RwReg8 *)0x42005405U) /**< \brief (AC1) Interrupt Enable Set */
+#define REG_AC1_INTFLAG            (*(RwReg8 *)0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */
+#define REG_AC1_STATUSA            (*(RoReg8 *)0x42005408U) /**< \brief (AC1) Status A */
+#define REG_AC1_STATUSB            (*(RoReg8 *)0x42005409U) /**< \brief (AC1) Status B */
+#define REG_AC1_STATUSC            (*(RoReg8 *)0x4200540AU) /**< \brief (AC1) Status C */
+#define REG_AC1_WINCTRL            (*(RwReg8 *)0x4200540CU) /**< \brief (AC1) Window Control */
+#define REG_AC1_COMPCTRL0          (*(RwReg  *)0x42005410U) /**< \brief (AC1) Comparator Control 0 */
+#define REG_AC1_COMPCTRL1          (*(RwReg  *)0x42005414U) /**< \brief (AC1) Comparator Control 1 */
+#define REG_AC1_SCALER0            (*(RwReg8 *)0x42005420U) /**< \brief (AC1) Scaler 0 */
+#define REG_AC1_SCALER1            (*(RwReg8 *)0x42005421U) /**< \brief (AC1) Scaler 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC1 peripheral ========== */
+#define AC1_CMP_NUM                 2        // Number of comparators
+#define AC1_GCLK_ID_ANA             32       // Index of Generic Clock for analog
+#define AC1_GCLK_ID_DIG             31       // Index of Generic Clock for digital
+#define AC1_NUM_CMP                 2       
+#define AC1_PAIRS                   1        // Number of pairs of comparators
+
+#endif /* _SAMD21_AC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/adc.h
new file mode 100644
index 0000000000..d80c035c44
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/adc.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_INSTANCE_
+#define _SAMD21_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CTRLA              (0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL            (0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL            (0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL           (0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB              (0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL            (0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG             (0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL          (0x42004010U) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL             (0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR           (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET           (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG            (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS             (0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT             (0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT              (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT              (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR           (0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR         (0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB              (0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL            (0x4200402AU) /**< \brief (ADC) Debug Control */
+#else
+#define REG_ADC_CTRLA              (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL            (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL            (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL           (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB              (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL            (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG             (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL          (*(RwReg  *)0x42004010U) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL             (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR           (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET           (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG            (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS             (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT             (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT              (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT              (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR           (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR         (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB              (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL            (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC peripheral ========== */
+#define ADC_DMAC_ID_RESRDY          39       // Index of DMA RESRDY trigger
+#define ADC_EXTCHANNEL_MSB          19       // Number of external channels
+#define ADC_GCLK_ID                 30       // Index of Generic Clock
+#define ADC_RESULT_BITS             16       // Size of RESULT.RESULT bitfield
+#define ADC_RESULT_MSB              15       // Size of Result
+
+#endif /* _SAMD21_ADC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dac.h
new file mode 100644
index 0000000000..dad52f7a1a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dac.h
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DAC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_INSTANCE_
+#define _SAMD21_DAC_INSTANCE_
+
+/* ========== Register definition for DAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DAC_CTRLA              (0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA               (0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF            (0x4200480CU) /**< \brief (DAC) Data Buffer */
+#else
+#define REG_DAC_CTRLA              (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA               (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF            (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DAC peripheral ========== */
+#define DAC_DMAC_ID_EMPTY           40       // Index of DMAC EMPTY trigger
+#define DAC_GCLK_ID                 33       // Index of Generic Clock
+
+#endif /* _SAMD21_DAC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dmac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dmac.h
new file mode 100644
index 0000000000..efa83a506e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dmac.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DMAC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_INSTANCE_
+#define _SAMD21_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_CTRL              (0x41004800U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL           (0x41004802U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN         (0x41004804U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM         (0x41004808U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS         (0x4100480CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL           (0x4100480DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_QOSCTRL           (0x4100480EU) /**< \brief (DMAC) QOS Control */
+#define REG_DMAC_SWTRIGCTRL        (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0          (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND           (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS         (0x41004824U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH            (0x41004828U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH            (0x4100482CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE            (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR          (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR           (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID              (0x4100483FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA           (0x41004840U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB           (0x41004844U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR        (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET        (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG         (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS          (0x4100484FU) /**< \brief (DMAC) Channel Status */
+#else
+#define REG_DMAC_CTRL              (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL           (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN         (*(RwReg  *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM         (*(RwReg  *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS         (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL           (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_QOSCTRL           (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */
+#define REG_DMAC_SWTRIGCTRL        (*(RwReg  *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0          (*(RwReg  *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND           (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS         (*(RoReg  *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH            (*(RoReg  *)0x41004828U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH            (*(RoReg  *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE            (*(RoReg  *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR          (*(RwReg  *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR           (*(RwReg  *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID              (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA           (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB           (*(RwReg  *)0x41004844U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR        (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET        (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG         (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS          (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DMAC peripheral ========== */
+#define DMAC_CH_BITS                4        // Number of bits to select channel
+#define DMAC_CH_NUM                 12       // Number of channels
+#define DMAC_CLK_AHB_ID             5        // AHB clock index
+#define DMAC_EVIN_NUM               4        // Number of input events
+#define DMAC_EVOUT_NUM              4        // Number of output events
+#define DMAC_LVL_BITS               2        // Number of bit to select level priority
+#define DMAC_LVL_NUM                4        // Enable priority level number
+#define DMAC_TRIG_BITS              6        // Number of bits to select trigger source
+#define DMAC_TRIG_NUM               45       // Number of peripheral triggers
+
+#endif /* _SAMD21_DMAC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dsu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dsu.h
new file mode 100644
index 0000000000..79395ceba4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dsu.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_INSTANCE_
+#define _SAMD21_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL               (0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0             (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END                (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE            (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4               (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0               (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL               (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (*(RwReg  *)0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (*(RwReg  *)0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (*(RwReg  *)0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (*(RwReg  *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (*(RwReg  *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (*(RoReg  *)0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0             (*(RoReg  *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (*(RoReg  *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END                (*(RoReg  *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE            (*(RoReg  *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4               (*(RoReg  *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0               (*(RoReg  *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (*(RoReg  *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (*(RoReg  *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (*(RoReg  *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (*(RoReg  *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (*(RoReg  *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (*(RoReg  *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (*(RoReg  *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_HSB_ID              3        // Index of AHB clock in PM.AHBMASK register
+
+#endif /* _SAMD21_DSU_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/eic.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/eic.h
new file mode 100644
index 0000000000..ed8fd65974
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/eic.h
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_INSTANCE_
+#define _SAMD21_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRL               (0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS             (0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL            (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL             (0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP             (0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0            (0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1            (0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#else
+#define REG_EIC_CTRL               (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS             (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL            (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL             (*(RwReg  *)0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (*(RwReg  *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (*(RwReg  *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (*(RwReg  *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP             (*(RwReg  *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0            (*(RwReg  *)0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1            (*(RwReg  *)0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_CONFIG_NUM              2        // Number of CONFIG registers
+#define EIC_GCLK_ID                 5        // Index of Generic Clock
+
+#endif /* _SAMD21_EIC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/evsys.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/evsys.h
new file mode 100644
index 0000000000..85573b7891
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/evsys.h
@@ -0,0 +1,202 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_INSTANCE_
+#define _SAMD21_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRL             (0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#else
+#define REG_EVSYS_CTRL             (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (*(RwReg  *)0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (*(RoReg  *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (*(RwReg  *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (*(RwReg  *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (*(RwReg  *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_CHANNELS              12       // Number of Channels
+#define EVSYS_CHANNELS_BITS         4        // Number of bits to select Channel
+#define EVSYS_CHANNELS_MSB          11       // Number of Channels - 1
+#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
+#define EVSYS_GCLK_ID_0             7
+#define EVSYS_GCLK_ID_1             8
+#define EVSYS_GCLK_ID_2             9
+#define EVSYS_GCLK_ID_3             10
+#define EVSYS_GCLK_ID_4             11
+#define EVSYS_GCLK_ID_5             12
+#define EVSYS_GCLK_ID_6             13
+#define EVSYS_GCLK_ID_7             14
+#define EVSYS_GCLK_ID_8             15
+#define EVSYS_GCLK_ID_9             16
+#define EVSYS_GCLK_ID_10            17
+#define EVSYS_GCLK_ID_11            18
+#define EVSYS_GCLK_ID_LSB           7
+#define EVSYS_GCLK_ID_MSB           18
+#define EVSYS_GCLK_ID_SIZE          12
+#define EVSYS_GENERATORS            76       // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
+#define EVSYS_USERS                 31       // Total Number of Event Users
+#define EVSYS_USERS_BITS            5        // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_RTC_CMP_0      1
+#define EVSYS_ID_GEN_RTC_CMP_1      2
+#define EVSYS_ID_GEN_RTC_OVF        3
+#define EVSYS_ID_GEN_RTC_PER_0      4
+#define EVSYS_ID_GEN_RTC_PER_1      5
+#define EVSYS_ID_GEN_RTC_PER_2      6
+#define EVSYS_ID_GEN_RTC_PER_3      7
+#define EVSYS_ID_GEN_RTC_PER_4      8
+#define EVSYS_ID_GEN_RTC_PER_5      9
+#define EVSYS_ID_GEN_RTC_PER_6      10
+#define EVSYS_ID_GEN_RTC_PER_7      11
+#define EVSYS_ID_GEN_EIC_EXTINT_0   12
+#define EVSYS_ID_GEN_EIC_EXTINT_1   13
+#define EVSYS_ID_GEN_EIC_EXTINT_2   14
+#define EVSYS_ID_GEN_EIC_EXTINT_3   15
+#define EVSYS_ID_GEN_EIC_EXTINT_4   16
+#define EVSYS_ID_GEN_EIC_EXTINT_5   17
+#define EVSYS_ID_GEN_EIC_EXTINT_6   18
+#define EVSYS_ID_GEN_EIC_EXTINT_7   19
+#define EVSYS_ID_GEN_EIC_EXTINT_8   20
+#define EVSYS_ID_GEN_EIC_EXTINT_9   21
+#define EVSYS_ID_GEN_EIC_EXTINT_10  22
+#define EVSYS_ID_GEN_EIC_EXTINT_11  23
+#define EVSYS_ID_GEN_EIC_EXTINT_12  24
+#define EVSYS_ID_GEN_EIC_EXTINT_13  25
+#define EVSYS_ID_GEN_EIC_EXTINT_14  26
+#define EVSYS_ID_GEN_EIC_EXTINT_15  27
+#define EVSYS_ID_GEN_EIC_EXTINT_16  28
+#define EVSYS_ID_GEN_EIC_EXTINT_17  29
+#define EVSYS_ID_GEN_DMAC_CH_0      30
+#define EVSYS_ID_GEN_DMAC_CH_1      31
+#define EVSYS_ID_GEN_DMAC_CH_2      32
+#define EVSYS_ID_GEN_DMAC_CH_3      33
+#define EVSYS_ID_GEN_TCC0_OVF       34
+#define EVSYS_ID_GEN_TCC0_TRG       35
+#define EVSYS_ID_GEN_TCC0_CNT       36
+#define EVSYS_ID_GEN_TCC0_MCX_0     37
+#define EVSYS_ID_GEN_TCC0_MCX_1     38
+#define EVSYS_ID_GEN_TCC0_MCX_2     39
+#define EVSYS_ID_GEN_TCC0_MCX_3     40
+#define EVSYS_ID_GEN_TCC1_OVF       41
+#define EVSYS_ID_GEN_TCC1_TRG       42
+#define EVSYS_ID_GEN_TCC1_CNT       43
+#define EVSYS_ID_GEN_TCC1_MCX_0     44
+#define EVSYS_ID_GEN_TCC1_MCX_1     45
+#define EVSYS_ID_GEN_TCC2_OVF       46
+#define EVSYS_ID_GEN_TCC2_TRG       47
+#define EVSYS_ID_GEN_TCC2_CNT       48
+#define EVSYS_ID_GEN_TCC2_MCX_0     49
+#define EVSYS_ID_GEN_TCC2_MCX_1     50
+#define EVSYS_ID_GEN_TC3_OVF        51
+#define EVSYS_ID_GEN_TC3_MCX_0      52
+#define EVSYS_ID_GEN_TC3_MCX_1      53
+#define EVSYS_ID_GEN_TC4_OVF        54
+#define EVSYS_ID_GEN_TC4_MCX_0      55
+#define EVSYS_ID_GEN_TC4_MCX_1      56
+#define EVSYS_ID_GEN_TC5_OVF        57
+#define EVSYS_ID_GEN_TC5_MCX_0      58
+#define EVSYS_ID_GEN_TC5_MCX_1      59
+#define EVSYS_ID_GEN_TC6_OVF        60
+#define EVSYS_ID_GEN_TC6_MCX_0      61
+#define EVSYS_ID_GEN_TC6_MCX_1      62
+#define EVSYS_ID_GEN_TC7_OVF        63
+#define EVSYS_ID_GEN_TC7_MCX_0      64
+#define EVSYS_ID_GEN_TC7_MCX_1      65
+#define EVSYS_ID_GEN_ADC_RESRDY     66
+#define EVSYS_ID_GEN_ADC_WINMON     67
+#define EVSYS_ID_GEN_AC_COMP_0      68
+#define EVSYS_ID_GEN_AC_COMP_1      69
+#define EVSYS_ID_GEN_AC_WIN_0       70
+#define EVSYS_ID_GEN_DAC_EMPTY      71
+#define EVSYS_ID_GEN_PTC_EOC        72
+#define EVSYS_ID_GEN_PTC_WCOMP      73
+#define EVSYS_ID_GEN_AC1_COMP_0     74
+#define EVSYS_ID_GEN_AC1_COMP_1     75
+#define EVSYS_ID_GEN_AC1_WIN_0      76
+
+// USERS
+#define EVSYS_ID_USER_DMAC_CH_0     0
+#define EVSYS_ID_USER_DMAC_CH_1     1
+#define EVSYS_ID_USER_DMAC_CH_2     2
+#define EVSYS_ID_USER_DMAC_CH_3     3
+#define EVSYS_ID_USER_TCC0_EV_0     4
+#define EVSYS_ID_USER_TCC0_EV_1     5
+#define EVSYS_ID_USER_TCC0_MC_0     6
+#define EVSYS_ID_USER_TCC0_MC_1     7
+#define EVSYS_ID_USER_TCC0_MC_2     8
+#define EVSYS_ID_USER_TCC0_MC_3     9
+#define EVSYS_ID_USER_TCC1_EV_0     10
+#define EVSYS_ID_USER_TCC1_EV_1     11
+#define EVSYS_ID_USER_TCC1_MC_0     12
+#define EVSYS_ID_USER_TCC1_MC_1     13
+#define EVSYS_ID_USER_TCC2_EV_0     14
+#define EVSYS_ID_USER_TCC2_EV_1     15
+#define EVSYS_ID_USER_TCC2_MC_0     16
+#define EVSYS_ID_USER_TCC2_MC_1     17
+#define EVSYS_ID_USER_TC3_EVU       18
+#define EVSYS_ID_USER_TC4_EVU       19
+#define EVSYS_ID_USER_TC5_EVU       20
+#define EVSYS_ID_USER_TC6_EVU       21
+#define EVSYS_ID_USER_TC7_EVU       22
+#define EVSYS_ID_USER_ADC_START     23
+#define EVSYS_ID_USER_ADC_SYNC      24
+#define EVSYS_ID_USER_AC_SOC_0      25
+#define EVSYS_ID_USER_AC_SOC_1      26
+#define EVSYS_ID_USER_DAC_START     27
+#define EVSYS_ID_USER_PTC_STCONV    28
+#define EVSYS_ID_USER_AC1_SOC_0     29
+#define EVSYS_ID_USER_AC1_SOC_1     30
+
+#endif /* _SAMD21_EVSYS_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/gclk.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/gclk.h
new file mode 100644
index 0000000000..e76ddf1e9f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/gclk.h
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_INSTANCE_
+#define _SAMD21_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRL              (0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS            (0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL           (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL           (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV            (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#else
+#define REG_GCLK_CTRL              (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS            (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL           (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL           (*(RwReg  *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV            (*(RwReg  *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENDIV_BITS            16      
+#define GCLK_GEN_NUM                9        // Number of Generic Clock Generators
+#define GCLK_GEN_NUM_MSB            8        // Number of Generic Clock Generators - 1
+#define GCLK_GEN_SOURCE_NUM_MSB     8        // Number of Generic Clock Sources - 1
+#define GCLK_NUM                    37       // Number of Generic Clock Users
+#define GCLK_SOURCE_DFLL48M         7        // DFLL48M output
+#define GCLK_SOURCE_FDPLL           8        // FDPLL output
+#define GCLK_SOURCE_GCLKGEN1        2        // Generic clock generator 1 output
+#define GCLK_SOURCE_GCLKIN          1        // Generator input pad
+#define GCLK_SOURCE_NUM             9        // Number of Generic Clock Sources
+#define GCLK_SOURCE_OSCULP32K       3        // OSCULP32K oscillator output
+#define GCLK_SOURCE_OSC8M           6        // OSC8M oscillator output
+#define GCLK_SOURCE_OSC32K          4        // OSC32K oscillator outpur
+#define GCLK_SOURCE_XOSC            0        // XOSC oscillator output
+#define GCLK_SOURCE_XOSC32K         5        // XOSC32K oscillator output
+
+#endif /* _SAMD21_GCLK_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/i2s.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/i2s.h
new file mode 100644
index 0000000000..d299a86f7c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/i2s.h
@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief Instance description for I2S
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_INSTANCE_
+#define _SAMD21_I2S_INSTANCE_
+
+/* ========== Register definition for I2S peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_I2S_CTRLA              (0x42005000U) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0           (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1           (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR           (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET           (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG            (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY           (0x42005018U) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0           (0x42005020U) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1           (0x42005024U) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0              (0x42005030U) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1              (0x42005034U) /**< \brief (I2S) Data 1 */
+#else
+#define REG_I2S_CTRLA              (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0           (*(RwReg  *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1           (*(RwReg  *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR           (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET           (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG            (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY           (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0           (*(RwReg  *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1           (*(RwReg  *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0              (*(RwReg  *)0x42005030U) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1              (*(RwReg  *)0x42005034U) /**< \brief (I2S) Data 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for I2S peripheral ========== */
+#define I2S_CLK_NUM                 2        // Number of clock units
+#define I2S_DMAC_ID_RX_0            41
+#define I2S_DMAC_ID_RX_1            42
+#define I2S_DMAC_ID_RX_LSB          41
+#define I2S_DMAC_ID_RX_MSB          42
+#define I2S_DMAC_ID_RX_SIZE         2
+#define I2S_DMAC_ID_TX_0            43
+#define I2S_DMAC_ID_TX_1            44
+#define I2S_DMAC_ID_TX_LSB          43
+#define I2S_DMAC_ID_TX_MSB          44
+#define I2S_DMAC_ID_TX_SIZE         2
+#define I2S_GCLK_ID_0               35
+#define I2S_GCLK_ID_1               36
+#define I2S_GCLK_ID_LSB             35
+#define I2S_GCLK_ID_MSB             36
+#define I2S_GCLK_ID_SIZE            2
+#define I2S_MAX_SLOTS               8        // Max number of data slots in frame
+#define I2S_SER_NUM                 2        // Number of serializers
+
+#endif /* _SAMD21_I2S_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/mtb.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/mtb.h
new file mode 100644
index 0000000000..9b5a72f1ac
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/mtb.h
@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief Instance description for MTB
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_INSTANCE_
+#define _SAMD21_MTB_INSTANCE_
+
+/* ========== Register definition for MTB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MTB_POSITION           (0x41006000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER             (0x41006004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW               (0x41006008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE               (0x4100600CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL             (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET           (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR           (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS         (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS         (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS         (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH            (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID              (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE            (0x41006FCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4               (0x41006FD0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5               (0x41006FD4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6               (0x41006FD8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7               (0x41006FDCU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0               (0x41006FE0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1               (0x41006FE4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2               (0x41006FE8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3               (0x41006FECU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0               (0x41006FF0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1               (0x41006FF4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2               (0x41006FF8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3               (0x41006FFCU) /**< \brief (MTB) CoreSight */
+#else
+#define REG_MTB_POSITION           (*(RwReg  *)0x41006000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER             (*(RwReg  *)0x41006004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW               (*(RwReg  *)0x41006008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE               (*(RoReg  *)0x4100600CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL             (*(RwReg  *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET           (*(RwReg  *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR           (*(RwReg  *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS         (*(RwReg  *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS         (*(RoReg  *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS         (*(RoReg  *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH            (*(RoReg  *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID              (*(RoReg  *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE            (*(RoReg  *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4               (*(RoReg  *)0x41006FD0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5               (*(RoReg  *)0x41006FD4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6               (*(RoReg  *)0x41006FD8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7               (*(RoReg  *)0x41006FDCU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0               (*(RoReg  *)0x41006FE0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1               (*(RoReg  *)0x41006FE4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2               (*(RoReg  *)0x41006FE8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3               (*(RoReg  *)0x41006FECU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0               (*(RoReg  *)0x41006FF0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1               (*(RoReg  *)0x41006FF4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2               (*(RoReg  *)0x41006FF8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3               (*(RoReg  *)0x41006FFCU) /**< \brief (MTB) CoreSight */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAMD21_MTB_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
new file mode 100644
index 0000000000..152f2d5ec2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
@@ -0,0 +1,92 @@
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_INSTANCE_
+#define _SAMD21_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA          (0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#else
+#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (*(RwReg  *)0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (*(RwReg  *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_AUX0_ADDRESS        0x00804000
+#define NVMCTRL_AUX1_ADDRESS        0x00806000
+#define NVMCTRL_AUX2_ADDRESS        0x00808000
+#define NVMCTRL_AUX3_ADDRESS        0x0080A000
+#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
+#define NVMCTRL_FLASH_SIZE          65536   
+#define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
+#define NVMCTRL_PAGE_HW             32      
+#define NVMCTRL_PAGE_SIZE           64      
+#define NVMCTRL_PAGE_W              16      
+#define NVMCTRL_PMSB                3       
+#define NVMCTRL_PSZ_BITS            6       
+#define NVMCTRL_ROW_PAGES           4       
+#define NVMCTRL_ROW_SIZE            256     
+#define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
+#define NVMCTRL_USER_PAGE_OFFSET    0x00800000
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
+#define NVMCTRL_RWWEE_PAGES         32       // Page size
+#define NVMCTRL_RWW_EEPROM_ADDR     0x00400000 // Start address of the RWW EEPROM area
+
+#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac0.h
new file mode 100644
index 0000000000..8af8b0e624
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac0.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC0
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC0_INSTANCE_
+#define _SAMD21_PAC0_INSTANCE_
+
+/* ========== Register definition for PAC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC0_WPCLR             (0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET             (0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#else
+#define REG_PAC0_WPCLR             (*(RwReg  *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET             (*(RwReg  *)0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC0 peripheral ========== */
+#define PAC0_WPROT_DEFAULT_VAL      0x00000000 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac1.h
new file mode 100644
index 0000000000..1b2b6a039f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac1.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC1
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC1_INSTANCE_
+#define _SAMD21_PAC1_INSTANCE_
+
+/* ========== Register definition for PAC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC1_WPCLR             (0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET             (0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#else
+#define REG_PAC1_WPCLR             (*(RwReg  *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET             (*(RwReg  *)0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC1 peripheral ========== */
+#define PAC1_WPROT_DEFAULT_VAL      0x00000002 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac2.h
new file mode 100644
index 0000000000..32443eec73
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac2.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC2
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC2_INSTANCE_
+#define _SAMD21_PAC2_INSTANCE_
+
+/* ========== Register definition for PAC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC2_WPCLR             (0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET             (0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#else
+#define REG_PAC2_WPCLR             (*(RwReg  *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET             (*(RwReg  *)0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC2 peripheral ========== */
+#define PAC2_WPROT_DEFAULT_VAL      0x00800000 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pm.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pm.h
new file mode 100644
index 0000000000..0190be611f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pm.h
@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_INSTANCE_
+#define _SAMD21_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRL                (0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP               (0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_EXTCTRL             (0x40000402U) /**< \brief (PM) External Reset Controller */
+#define REG_PM_CPUSEL              (0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL             (0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL             (0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL             (0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK             (0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK            (0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK            (0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK            (0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR            (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE              (0x40000438U) /**< \brief (PM) Reset Cause */
+#else
+#define REG_PM_CTRL                (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP               (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_EXTCTRL             (*(RwReg8 *)0x40000402U) /**< \brief (PM) External Reset Controller */
+#define REG_PM_CPUSEL              (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL             (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL             (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL             (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK             (*(RwReg  *)0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK            (*(RwReg  *)0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK            (*(RwReg  *)0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK            (*(RwReg  *)0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR            (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE              (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_CTRL_MCSEL_DFLL48M       3       
+#define PM_CTRL_MCSEL_GCLK          0       
+#define PM_CTRL_MCSEL_OSC8M         1       
+#define PM_CTRL_MCSEL_XOSC          2       
+#define PM_PM_CLK_APB_NUM           2       
+
+#endif /* _SAMD21_PM_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/port.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/port.h
new file mode 100644
index 0000000000..026730734f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/port.h
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_INSTANCE_
+#define _SAMD21_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0              (0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#else
+#define REG_PORT_DIR0              (*(RwReg  *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (*(RwReg  *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (*(RwReg  *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (*(RwReg  *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (*(RoReg  *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (*(RwReg  *)0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (*(RwReg  *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (*(RwReg  *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (*(RwReg  *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (*(RwReg  *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (*(RwReg  *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (*(RwReg  *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (*(RoReg  *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (*(RwReg  *)0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (*(RwReg  *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (*(RwReg  *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS                   64       // Number of PORT pins
+#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
+#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
+#define PORT_DRVSTR                 1        // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
+#define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
+#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
+#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
+#define PORT_ODRAIN                 0        // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
+#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
+#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
+#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
+#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
+#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
+#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
+#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
+#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
+#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
+#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF7, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
+#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
+#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
+#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
+#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
+#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
+#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
+#define PORT_SLEWLIM                0        // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
+#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+
+#endif /* _SAMD21_PORT_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/rtc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/rtc.h
new file mode 100644
index 0000000000..36f16449c7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/rtc.h
@@ -0,0 +1,117 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_INSTANCE_
+#define _SAMD21_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_READREQ            (0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS             (0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL            (0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL         (0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT        (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL         (0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT        (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL         (0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK        (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#else
+#define REG_RTC_READREQ            (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS             (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL            (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT        (*(RwReg  *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (*(RwReg  *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT        (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK        (*(RwReg  *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg  *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (*(RwReg  *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_ALARM_NUM               1        // Number of Alarms
+#define RTC_COMP16_NUM              2        // Number of 16-bit Comparators
+#define RTC_COMP32_NUM              1        // Number of 32-bit Comparators
+#define RTC_GCLK_ID                 4        // Index of Generic Clock
+#define RTC_NUM_OF_ALARMS           1        // Number of Alarms (obsolete)
+#define RTC_NUM_OF_COMP16           2        // Number of 16-bit Comparators (obsolete)
+#define RTC_NUM_OF_COMP32           1        // Number of 32-bit Comparators (obsolete)
+
+#endif /* _SAMD21_RTC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h
new file mode 100644
index 0000000000..fa9d0b8499
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h
@@ -0,0 +1,165 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SBMATRIX
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SBMATRIX_INSTANCE_
+#define _SAMD21_SBMATRIX_INSTANCE_
+
+/* ========== Register definition for SBMATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SBMATRIX_PRAS0         (0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */
+#define REG_SBMATRIX_PRBS0         (0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */
+#define REG_SBMATRIX_PRAS1         (0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */
+#define REG_SBMATRIX_PRBS1         (0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */
+#define REG_SBMATRIX_PRAS2         (0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */
+#define REG_SBMATRIX_PRBS2         (0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */
+#define REG_SBMATRIX_PRAS3         (0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */
+#define REG_SBMATRIX_PRBS3         (0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */
+#define REG_SBMATRIX_PRAS4         (0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */
+#define REG_SBMATRIX_PRBS4         (0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */
+#define REG_SBMATRIX_PRAS5         (0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */
+#define REG_SBMATRIX_PRBS5         (0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */
+#define REG_SBMATRIX_PRAS6         (0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */
+#define REG_SBMATRIX_PRBS6         (0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */
+#define REG_SBMATRIX_PRAS7         (0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */
+#define REG_SBMATRIX_PRBS7         (0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */
+#define REG_SBMATRIX_PRAS8         (0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */
+#define REG_SBMATRIX_PRBS8         (0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */
+#define REG_SBMATRIX_PRAS9         (0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */
+#define REG_SBMATRIX_PRBS9         (0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */
+#define REG_SBMATRIX_PRAS10        (0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */
+#define REG_SBMATRIX_PRBS10        (0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */
+#define REG_SBMATRIX_PRAS11        (0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */
+#define REG_SBMATRIX_PRBS11        (0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */
+#define REG_SBMATRIX_PRAS12        (0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */
+#define REG_SBMATRIX_PRBS12        (0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */
+#define REG_SBMATRIX_PRAS13        (0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */
+#define REG_SBMATRIX_PRBS13        (0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */
+#define REG_SBMATRIX_PRAS14        (0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */
+#define REG_SBMATRIX_PRBS14        (0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */
+#define REG_SBMATRIX_PRAS15        (0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */
+#define REG_SBMATRIX_PRBS15        (0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */
+#define REG_SBMATRIX_SFR0          (0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */
+#define REG_SBMATRIX_SFR1          (0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */
+#define REG_SBMATRIX_SFR2          (0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */
+#define REG_SBMATRIX_SFR3          (0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */
+#define REG_SBMATRIX_SFR4          (0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */
+#define REG_SBMATRIX_SFR5          (0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */
+#define REG_SBMATRIX_SFR6          (0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */
+#define REG_SBMATRIX_SFR7          (0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */
+#define REG_SBMATRIX_SFR8          (0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */
+#define REG_SBMATRIX_SFR9          (0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */
+#define REG_SBMATRIX_SFR10         (0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */
+#define REG_SBMATRIX_SFR11         (0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */
+#define REG_SBMATRIX_SFR12         (0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */
+#define REG_SBMATRIX_SFR13         (0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */
+#define REG_SBMATRIX_SFR14         (0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */
+#define REG_SBMATRIX_SFR15         (0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */
+#else
+#define REG_SBMATRIX_PRAS0         (*(RwReg  *)0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */
+#define REG_SBMATRIX_PRBS0         (*(RwReg  *)0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */
+#define REG_SBMATRIX_PRAS1         (*(RwReg  *)0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */
+#define REG_SBMATRIX_PRBS1         (*(RwReg  *)0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */
+#define REG_SBMATRIX_PRAS2         (*(RwReg  *)0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */
+#define REG_SBMATRIX_PRBS2         (*(RwReg  *)0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */
+#define REG_SBMATRIX_PRAS3         (*(RwReg  *)0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */
+#define REG_SBMATRIX_PRBS3         (*(RwReg  *)0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */
+#define REG_SBMATRIX_PRAS4         (*(RwReg  *)0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */
+#define REG_SBMATRIX_PRBS4         (*(RwReg  *)0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */
+#define REG_SBMATRIX_PRAS5         (*(RwReg  *)0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */
+#define REG_SBMATRIX_PRBS5         (*(RwReg  *)0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */
+#define REG_SBMATRIX_PRAS6         (*(RwReg  *)0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */
+#define REG_SBMATRIX_PRBS6         (*(RwReg  *)0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */
+#define REG_SBMATRIX_PRAS7         (*(RwReg  *)0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */
+#define REG_SBMATRIX_PRBS7         (*(RwReg  *)0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */
+#define REG_SBMATRIX_PRAS8         (*(RwReg  *)0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */
+#define REG_SBMATRIX_PRBS8         (*(RwReg  *)0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */
+#define REG_SBMATRIX_PRAS9         (*(RwReg  *)0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */
+#define REG_SBMATRIX_PRBS9         (*(RwReg  *)0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */
+#define REG_SBMATRIX_PRAS10        (*(RwReg  *)0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */
+#define REG_SBMATRIX_PRBS10        (*(RwReg  *)0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */
+#define REG_SBMATRIX_PRAS11        (*(RwReg  *)0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */
+#define REG_SBMATRIX_PRBS11        (*(RwReg  *)0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */
+#define REG_SBMATRIX_PRAS12        (*(RwReg  *)0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */
+#define REG_SBMATRIX_PRBS12        (*(RwReg  *)0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */
+#define REG_SBMATRIX_PRAS13        (*(RwReg  *)0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */
+#define REG_SBMATRIX_PRBS13        (*(RwReg  *)0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */
+#define REG_SBMATRIX_PRAS14        (*(RwReg  *)0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */
+#define REG_SBMATRIX_PRBS14        (*(RwReg  *)0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */
+#define REG_SBMATRIX_PRAS15        (*(RwReg  *)0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */
+#define REG_SBMATRIX_PRBS15        (*(RwReg  *)0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */
+#define REG_SBMATRIX_SFR0          (*(RwReg  *)0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */
+#define REG_SBMATRIX_SFR1          (*(RwReg  *)0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */
+#define REG_SBMATRIX_SFR2          (*(RwReg  *)0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */
+#define REG_SBMATRIX_SFR3          (*(RwReg  *)0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */
+#define REG_SBMATRIX_SFR4          (*(RwReg  *)0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */
+#define REG_SBMATRIX_SFR5          (*(RwReg  *)0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */
+#define REG_SBMATRIX_SFR6          (*(RwReg  *)0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */
+#define REG_SBMATRIX_SFR7          (*(RwReg  *)0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */
+#define REG_SBMATRIX_SFR8          (*(RwReg  *)0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */
+#define REG_SBMATRIX_SFR9          (*(RwReg  *)0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */
+#define REG_SBMATRIX_SFR10         (*(RwReg  *)0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */
+#define REG_SBMATRIX_SFR11         (*(RwReg  *)0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */
+#define REG_SBMATRIX_SFR12         (*(RwReg  *)0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */
+#define REG_SBMATRIX_SFR13         (*(RwReg  *)0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */
+#define REG_SBMATRIX_SFR14         (*(RwReg  *)0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */
+#define REG_SBMATRIX_SFR15         (*(RwReg  *)0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SBMATRIX peripheral ========== */
+#define SBMATRIX_DEFINED                    
+/* ========== Instance parameters for SBMATRIX ========== */
+#define SBMATRIX_SLAVE_FLASH        0
+#define SBMATRIX_SLAVE_HPB0         1
+#define SBMATRIX_SLAVE_HPB1         2
+#define SBMATRIX_SLAVE_HPB2         3
+#define SBMATRIX_SLAVE_HMCRAMC0     4
+#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5
+#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6
+#define SBMATRIX_SLAVE_NUM          7
+
+#define SBMATRIX_MASTER_CM0PLUS     0
+#define SBMATRIX_MASTER_DSU         1
+#define SBMATRIX_MASTER_DMAC        2
+#define SBMATRIX_MASTER_NUM         3
+
+#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom0.h
new file mode 100644
index 0000000000..275ce8c1fc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom0.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM0_INSTANCE_
+#define _SAMD21_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA     (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD      (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY  (0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR      (0x42000824U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (0x42000828U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL   (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA     (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR  (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY  (0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_ADDR      (0x42000824U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (0x42000828U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD       (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (0x4200081AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY   (0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_ADDR       (0x42000824U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (0x42000828U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL    (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA    (0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD     (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL     (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (0x4200081AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_DATA     (0x42000828U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL  (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
+#else
+#define REG_SERCOM0_I2CM_CTRLA     (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD      (*(RwReg  *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY  (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR      (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL   (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA     (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR  (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY  (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_ADDR      (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD       (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY   (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_ADDR       (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (*(RwReg  *)0x42000828U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL    (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA    (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD     (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL     (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_DATA     (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL  (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_DMAC_ID_RX          1        // Index of DMA RX trigger
+#define SERCOM0_DMAC_ID_TX          2        // Index of DMA TX trigger
+#define SERCOM0_GCLK_ID_CORE        20       // Index of Generic Clock for Core
+#define SERCOM0_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM0_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom1.h
new file mode 100644
index 0000000000..c661025b25
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom1.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM1_INSTANCE_
+#define _SAMD21_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA     (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD      (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY  (0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR      (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL   (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA     (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR  (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY  (0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_ADDR      (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD       (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY   (0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_ADDR       (0x42000C24U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (0x42000C28U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL    (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA    (0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD     (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL     (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (0x42000C1AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_DATA     (0x42000C28U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL  (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
+#else
+#define REG_SERCOM1_I2CM_CTRLA     (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD      (*(RwReg  *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY  (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR      (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL   (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA     (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR  (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY  (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_ADDR      (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD       (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY   (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_ADDR       (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (*(RwReg  *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL    (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA    (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD     (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL     (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_DATA     (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL  (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_DMAC_ID_RX          3        // Index of DMA RX trigger
+#define SERCOM1_DMAC_ID_TX          4        // Index of DMA TX trigger
+#define SERCOM1_GCLK_ID_CORE        21       // Index of Generic Clock for Core
+#define SERCOM1_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM1_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom2.h
new file mode 100644
index 0000000000..3dc3043a04
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom2.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM2_INSTANCE_
+#define _SAMD21_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA     (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD      (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY  (0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR      (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL   (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA     (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR  (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY  (0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_ADDR      (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD       (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY   (0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_ADDR       (0x42001024U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (0x42001028U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL    (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA    (0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD     (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL     (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (0x4200101AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_DATA     (0x42001028U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL  (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
+#else
+#define REG_SERCOM2_I2CM_CTRLA     (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD      (*(RwReg  *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY  (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR      (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL   (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA     (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR  (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY  (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_ADDR      (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD       (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY   (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_ADDR       (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (*(RwReg  *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL    (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA    (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD     (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL     (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_DATA     (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL  (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_DMAC_ID_RX          5        // Index of DMA RX trigger
+#define SERCOM2_DMAC_ID_TX          6        // Index of DMA TX trigger
+#define SERCOM2_GCLK_ID_CORE        22       // Index of Generic Clock for Core
+#define SERCOM2_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM2_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom3.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom3.h
new file mode 100644
index 0000000000..9aef259334
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom3.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM3_INSTANCE_
+#define _SAMD21_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA     (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD      (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY  (0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR      (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL   (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA     (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR  (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY  (0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_ADDR      (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD       (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY   (0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_ADDR       (0x42001424U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (0x42001428U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL    (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA    (0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD     (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL     (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (0x4200141AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_DATA     (0x42001428U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL  (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
+#else
+#define REG_SERCOM3_I2CM_CTRLA     (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD      (*(RwReg  *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY  (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR      (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL   (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA     (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR  (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY  (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_ADDR      (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD       (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY   (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_ADDR       (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (*(RwReg  *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL    (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA    (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD     (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL     (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_DATA     (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL  (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_DMAC_ID_RX          7        // Index of DMA RX trigger
+#define SERCOM3_DMAC_ID_TX          8        // Index of DMA TX trigger
+#define SERCOM3_GCLK_ID_CORE        23       // Index of Generic Clock for Core
+#define SERCOM3_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM3_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM3_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom4.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom4.h
new file mode 100644
index 0000000000..daf636de3b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom4.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM4_INSTANCE_
+#define _SAMD21_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA     (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD      (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY  (0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR      (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL   (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA     (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR  (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY  (0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_ADDR      (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD       (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY   (0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_ADDR       (0x42001824U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (0x42001828U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL    (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA    (0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD     (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL     (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (0x4200181AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_DATA     (0x42001828U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL  (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
+#else
+#define REG_SERCOM4_I2CM_CTRLA     (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD      (*(RwReg  *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY  (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR      (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL   (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA     (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR  (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY  (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_ADDR      (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD       (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY   (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_ADDR       (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (*(RwReg  *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL    (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA    (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD     (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL     (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_DATA     (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL  (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_DMAC_ID_RX          9        // Index of DMA RX trigger
+#define SERCOM4_DMAC_ID_TX          10       // Index of DMA TX trigger
+#define SERCOM4_GCLK_ID_CORE        24       // Index of Generic Clock for Core
+#define SERCOM4_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM4_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM4_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom5.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom5.h
new file mode 100644
index 0000000000..86386c78fc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom5.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM5_INSTANCE_
+#define _SAMD21_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA     (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD      (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY  (0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR      (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL   (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA     (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR  (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY  (0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_ADDR      (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD       (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY   (0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_ADDR       (0x42001C24U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (0x42001C28U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL    (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA    (0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD     (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL     (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (0x42001C1AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_DATA     (0x42001C28U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL  (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
+#else
+#define REG_SERCOM5_I2CM_CTRLA     (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD      (*(RwReg  *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY  (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR      (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL   (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA     (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR  (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY  (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_ADDR      (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD       (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY   (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_ADDR       (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (*(RwReg  *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL    (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA    (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD     (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL     (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_DATA     (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL  (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_DMAC_ID_RX          11       // Index of DMA RX trigger
+#define SERCOM5_DMAC_ID_TX          12       // Index of DMA TX trigger
+#define SERCOM5_GCLK_ID_CORE        25       // Index of Generic Clock for Core
+#define SERCOM5_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM5_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM5_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sysctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
new file mode 100644
index 0000000000..0c38eccb63
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
@@ -0,0 +1,121 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SYSCTRL
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_INSTANCE_
+#define _SAMD21_SYSCTRL_INSTANCE_
+
+/* ========== Register definition for SYSCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SYSCTRL_INTENCLR       (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET       (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG        (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR         (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC           (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K        (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K         (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K      (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M          (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL       (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL        (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL        (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC       (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33          (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG           (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF           (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA      (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO      (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB      (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS     (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
+#else
+#define REG_SYSCTRL_INTENCLR       (*(RwReg  *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET       (*(RwReg  *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG        (*(RwReg  *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR         (*(RoReg  *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC           (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K        (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K         (*(RwReg  *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K      (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M          (*(RwReg  *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL       (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL        (*(RwReg  *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL        (*(RwReg  *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC       (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33          (*(RwReg  *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG           (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF           (*(RwReg  *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA      (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO      (*(RwReg  *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB      (*(RwReg  *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS     (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SYSCTRL peripheral ========== */
+#define SYSCTRL_BGAP_CALIB_MSB      11      
+#define SYSCTRL_BOD33_CALIB_MSB     5       
+#define SYSCTRL_DFLL48M_COARSE_MSB  5       
+#define SYSCTRL_DFLL48M_FINE_MSB    9       
+#define SYSCTRL_GCLK_ID_DFLL48      0        // Index of Generic Clock for DFLL48
+#define SYSCTRL_GCLK_ID_FDPLL       1        // Index of Generic Clock for DPLL
+#define SYSCTRL_GCLK_ID_FDPLL32K    2        // Index of Generic Clock for DPLL 32K
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6       
+#define SYSCTRL_POR33_ENTEST_MSB    1       
+#define SYSCTRL_SYSTEM_CLOCK        1000000  // Initial system clock frequency
+#define SYSCTRL_ULPVREF_DIVLEV_MSB  3       
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1       
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2       
+#define SYSCTRL_VREF_CONTROL_MSB    48      
+#define SYSCTRL_VREF_STATUS_MSB     7       
+#define SYSCTRL_VREG_LEVEL_MSB      2       
+#define SYSCTRL_BOD12_VERSION       0x112   
+#define SYSCTRL_BOD33_VERSION       0x112   
+#define SYSCTRL_DFLL48M_VERSION     0x301   
+#define SYSCTRL_FDPLL_VERSION       0x111   
+#define SYSCTRL_OSCULP32K_VERSION   0x111   
+#define SYSCTRL_OSC8M_VERSION       0x120   
+#define SYSCTRL_OSC32K_VERSION      0x112   
+#define SYSCTRL_VREF_VERSION        0x201   
+#define SYSCTRL_VREG_VERSION        0x201   
+#define SYSCTRL_XOSC_VERSION        0x114   
+#define SYSCTRL_XOSC32K_VERSION     0x113   
+
+#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc3.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc3.h
new file mode 100644
index 0000000000..b5b100854d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc3.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC3_INSTANCE_
+#define _SAMD21_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA              (0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ            (0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR           (0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC              (0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL             (0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT      (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0        (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1        (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT      (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0        (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1        (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT       (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER         (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0         (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1         (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC3_CTRLA              (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ            (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR           (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC              (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL             (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT      (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0        (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1        (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT      (*(RwReg  *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0        (*(RwReg  *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1        (*(RwReg  *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT       (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER         (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0         (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1         (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC3_CC16_NUM                2        // Number of 16-bit Counters
+#define TC3_CC32_NUM                2        // Number of 32-bit Counters
+#define TC3_DITHERING_EXT           0        // Dithering feature implemented
+#define TC3_DMAC_ID_MC_0            25
+#define TC3_DMAC_ID_MC_1            26
+#define TC3_DMAC_ID_MC_LSB          25
+#define TC3_DMAC_ID_MC_MSB          26
+#define TC3_DMAC_ID_MC_SIZE         2
+#define TC3_DMAC_ID_OVF             24       // Indexes of DMA Overflow trigger
+#define TC3_GCLK_ID                 27       // Index of Generic Clock
+#define TC3_MASTER                  0       
+#define TC3_OW_NUM                  2        // Number of Output Waveforms
+#define TC3_PERIOD_EXT              0        // Period feature implemented
+#define TC3_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC3_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc4.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc4.h
new file mode 100644
index 0000000000..51d3f19e76
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc4.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC4
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC4_INSTANCE_
+#define _SAMD21_TC4_INSTANCE_
+
+/* ========== Register definition for TC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC4_CTRLA              (0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ            (0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR           (0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC              (0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL             (0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT      (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0        (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1        (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT      (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0        (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1        (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT       (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER         (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0         (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1         (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC4_CTRLA              (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ            (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR           (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC              (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL             (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT      (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0        (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1        (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT      (*(RwReg  *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0        (*(RwReg  *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1        (*(RwReg  *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT       (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER         (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0         (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1         (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC4 peripheral ========== */
+#define TC4_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC4_CC16_NUM                2        // Number of 16-bit Counters
+#define TC4_CC32_NUM                2        // Number of 32-bit Counters
+#define TC4_DITHERING_EXT           0        // Dithering feature implemented
+#define TC4_DMAC_ID_MC_0            28
+#define TC4_DMAC_ID_MC_1            29
+#define TC4_DMAC_ID_MC_LSB          28
+#define TC4_DMAC_ID_MC_MSB          29
+#define TC4_DMAC_ID_MC_SIZE         2
+#define TC4_DMAC_ID_OVF             27       // Indexes of DMA Overflow trigger
+#define TC4_GCLK_ID                 28       // Index of Generic Clock
+#define TC4_MASTER                  1       
+#define TC4_OW_NUM                  2        // Number of Output Waveforms
+#define TC4_PERIOD_EXT              0        // Period feature implemented
+#define TC4_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC4_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc5.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc5.h
new file mode 100644
index 0000000000..1e819163e7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc5.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC5
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC5_INSTANCE_
+#define _SAMD21_TC5_INSTANCE_
+
+/* ========== Register definition for TC5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC5_CTRLA              (0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ            (0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR           (0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC              (0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL             (0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT      (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0        (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1        (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT      (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0        (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1        (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT       (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER         (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0         (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1         (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC5_CTRLA              (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ            (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR           (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC              (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL             (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT      (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0        (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1        (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT      (*(RwReg  *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0        (*(RwReg  *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1        (*(RwReg  *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT       (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER         (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0         (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1         (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC5 peripheral ========== */
+#define TC5_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC5_CC16_NUM                2        // Number of 16-bit Counters
+#define TC5_CC32_NUM                2        // Number of 32-bit Counters
+#define TC5_DITHERING_EXT           0        // Dithering feature implemented
+#define TC5_DMAC_ID_MC_0            31
+#define TC5_DMAC_ID_MC_1            32
+#define TC5_DMAC_ID_MC_LSB          31
+#define TC5_DMAC_ID_MC_MSB          32
+#define TC5_DMAC_ID_MC_SIZE         2
+#define TC5_DMAC_ID_OVF             30       // Indexes of DMA Overflow trigger
+#define TC5_GCLK_ID                 28       // Index of Generic Clock
+#define TC5_MASTER                  0       
+#define TC5_OW_NUM                  2        // Number of Output Waveforms
+#define TC5_PERIOD_EXT              0        // Period feature implemented
+#define TC5_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC5_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc6.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc6.h
new file mode 100644
index 0000000000..b53e9ff087
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc6.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC6
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC6_INSTANCE_
+#define _SAMD21_TC6_INSTANCE_
+
+/* ========== Register definition for TC6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC6_CTRLA              (0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ            (0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR           (0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC              (0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL             (0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT      (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0        (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1        (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT      (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0        (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1        (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT       (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER         (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0         (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1         (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC6_CTRLA              (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ            (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR           (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC              (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL             (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT      (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0        (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1        (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT      (*(RwReg  *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0        (*(RwReg  *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1        (*(RwReg  *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT       (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER         (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0         (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1         (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC6 peripheral ========== */
+#define TC6_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC6_CC16_NUM                2        // Number of 16-bit Counters
+#define TC6_CC32_NUM                2        // Number of 32-bit Counters
+#define TC6_DITHERING_EXT           0        // Dithering feature implemented
+#define TC6_DMAC_ID_MC_0            34
+#define TC6_DMAC_ID_MC_1            35
+#define TC6_DMAC_ID_MC_LSB          34
+#define TC6_DMAC_ID_MC_MSB          35
+#define TC6_DMAC_ID_MC_SIZE         2
+#define TC6_DMAC_ID_OVF             33       // Indexes of DMA Overflow trigger
+#define TC6_GCLK_ID                 29       // Index of Generic Clock
+#define TC6_MASTER                  1       
+#define TC6_OW_NUM                  2        // Number of Output Waveforms
+#define TC6_PERIOD_EXT              0        // Period feature implemented
+#define TC6_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC6_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc7.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc7.h
new file mode 100644
index 0000000000..40fd453b4c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc7.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC7
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC7_INSTANCE_
+#define _SAMD21_TC7_INSTANCE_
+
+/* ========== Register definition for TC7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC7_CTRLA              (0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ            (0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR           (0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC              (0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL             (0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT      (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0        (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1        (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT      (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0        (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1        (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT       (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER         (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0         (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1         (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC7_CTRLA              (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ            (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR           (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC              (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL             (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT      (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0        (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1        (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT      (*(RwReg  *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0        (*(RwReg  *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1        (*(RwReg  *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT       (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER         (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0         (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1         (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC7 peripheral ========== */
+#define TC7_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC7_CC16_NUM                2        // Number of 16-bit Counters
+#define TC7_CC32_NUM                2        // Number of 32-bit Counters
+#define TC7_DITHERING_EXT           0        // Dithering feature implemented
+#define TC7_DMAC_ID_MC_0            37
+#define TC7_DMAC_ID_MC_1            38
+#define TC7_DMAC_ID_MC_LSB          37
+#define TC7_DMAC_ID_MC_MSB          38
+#define TC7_DMAC_ID_MC_SIZE         2
+#define TC7_DMAC_ID_OVF             36       // Indexes of DMA Overflow trigger
+#define TC7_GCLK_ID                 29       // Index of Generic Clock
+#define TC7_MASTER                  0       
+#define TC7_OW_NUM                  2        // Number of Output Waveforms
+#define TC7_PERIOD_EXT              0        // Period feature implemented
+#define TC7_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC7_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc0.h
new file mode 100644
index 0000000000..7e26234a5b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc0.h
@@ -0,0 +1,132 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC0
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC0_INSTANCE_
+#define _SAMD21_TCC0_INSTANCE_
+
+/* ========== Register definition for TCC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC0_CTRLA             (0x42002000U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR          (0x42002004U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET          (0x42002005U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY          (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA            (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB            (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL           (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL           (0x42002018U) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL           (0x4200201EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL            (0x42002020U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR          (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET          (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG           (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS            (0x42002030U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT             (0x42002034U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT              (0x42002038U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE              (0x4200203CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER               (0x42002040U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0               (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1               (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2               (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3               (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB             (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB             (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB              (0x4200206CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0              (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1              (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2              (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3              (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC0_CTRLA             (*(RwReg  *)0x42002000U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR          (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET          (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY          (*(RoReg  *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA            (*(RwReg  *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB            (*(RwReg  *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL           (*(RwReg  *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL           (*(RwReg  *)0x42002018U) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL           (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL            (*(RwReg  *)0x42002020U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR          (*(RwReg  *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET          (*(RwReg  *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG           (*(RwReg  *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS            (*(RwReg  *)0x42002030U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT             (*(RwReg  *)0x42002034U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT              (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE              (*(RwReg  *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER               (*(RwReg  *)0x42002040U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0               (*(RwReg  *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1               (*(RwReg  *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2               (*(RwReg  *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3               (*(RwReg  *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB             (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB             (*(RwReg  *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB              (*(RwReg  *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0              (*(RwReg  *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1              (*(RwReg  *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2              (*(RwReg  *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3              (*(RwReg  *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC0 peripheral ========== */
+#define TCC0_CC_NUM                 4        // Number of Compare/Capture units
+#define TCC0_DITHERING              1        // Dithering feature implemented
+#define TCC0_DMAC_ID_MC_0           14
+#define TCC0_DMAC_ID_MC_1           15
+#define TCC0_DMAC_ID_MC_2           16
+#define TCC0_DMAC_ID_MC_3           17
+#define TCC0_DMAC_ID_MC_LSB         14
+#define TCC0_DMAC_ID_MC_MSB         17
+#define TCC0_DMAC_ID_MC_SIZE        4
+#define TCC0_DMAC_ID_OVF            13       // DMA overflow/underflow/retrigger trigger
+#define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented
+#define TCC0_EXT                    31       // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
+#define TCC0_GCLK_ID                26       // Index of Generic Clock
+#define TCC0_MASTER                 0       
+#define TCC0_OTMX                   1        // Output Matrix feature implemented
+#define TCC0_OW_NUM                 8        // Number of Output Waveforms
+#define TCC0_PG                     1        // Pattern Generation feature implemented
+#define TCC0_SIZE                   24      
+#define TCC0_SWAP                   1        // DTI outputs swap feature implemented
+#define TCC0_TYPE                   1        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc1.h
new file mode 100644
index 0000000000..fdf00b3ceb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc1.h
@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC1
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC1_INSTANCE_
+#define _SAMD21_TCC1_INSTANCE_
+
+/* ========== Register definition for TCC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC1_CTRLA             (0x42002400U) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR          (0x42002404U) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET          (0x42002405U) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY          (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA            (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB            (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_DRVCTRL           (0x42002418U) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL           (0x4200241EU) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL            (0x42002420U) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR          (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET          (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG           (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS            (0x42002430U) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT             (0x42002434U) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT              (0x42002438U) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE              (0x4200243CU) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER               (0x42002440U) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0               (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1               (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB             (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB             (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB              (0x4200246CU) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0              (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1              (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC1_CTRLA             (*(RwReg  *)0x42002400U) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR          (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET          (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY          (*(RoReg  *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA            (*(RwReg  *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB            (*(RwReg  *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_DRVCTRL           (*(RwReg  *)0x42002418U) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL           (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL            (*(RwReg  *)0x42002420U) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR          (*(RwReg  *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET          (*(RwReg  *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG           (*(RwReg  *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS            (*(RwReg  *)0x42002430U) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT             (*(RwReg  *)0x42002434U) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT              (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE              (*(RwReg  *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER               (*(RwReg  *)0x42002440U) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0               (*(RwReg  *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1               (*(RwReg  *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB             (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB             (*(RwReg  *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB              (*(RwReg  *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0              (*(RwReg  *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1              (*(RwReg  *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC1 peripheral ========== */
+#define TCC1_CC_NUM                 2        // Number of Compare/Capture units
+#define TCC1_DITHERING              1        // Dithering feature implemented
+#define TCC1_DMAC_ID_MC_0           19
+#define TCC1_DMAC_ID_MC_1           20
+#define TCC1_DMAC_ID_MC_LSB         19
+#define TCC1_DMAC_ID_MC_MSB         20
+#define TCC1_DMAC_ID_MC_SIZE        2
+#define TCC1_DMAC_ID_OVF            18       // DMA overflow/underflow/retrigger trigger
+#define TCC1_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC1_EXT                    24       // Coding of implemented extended features
+#define TCC1_GCLK_ID                26       // Index of Generic Clock
+#define TCC1_MASTER                 1       
+#define TCC1_OTMX                   0        // Output Matrix feature implemented
+#define TCC1_OW_NUM                 4        // Number of Output Waveforms
+#define TCC1_PG                     1        // Pattern Generation feature implemented
+#define TCC1_SIZE                   24      
+#define TCC1_SWAP                   0        // DTI outputs swap feature implemented
+#define TCC1_TYPE                   2        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc2.h
new file mode 100644
index 0000000000..9a29007104
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc2.h
@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC2
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC2_INSTANCE_
+#define _SAMD21_TCC2_INSTANCE_
+
+/* ========== Register definition for TCC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC2_CTRLA             (0x42002800U) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR          (0x42002804U) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET          (0x42002805U) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY          (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA            (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB            (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_DRVCTRL           (0x42002818U) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL           (0x4200281EU) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL            (0x42002820U) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR          (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET          (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG           (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS            (0x42002830U) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT             (0x42002834U) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE              (0x4200283CU) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER               (0x42002840U) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0               (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1               (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB             (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB              (0x4200286CU) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0              (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1              (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC2_CTRLA             (*(RwReg  *)0x42002800U) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR          (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET          (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY          (*(RoReg  *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA            (*(RwReg  *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB            (*(RwReg  *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_DRVCTRL           (*(RwReg  *)0x42002818U) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL           (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL            (*(RwReg  *)0x42002820U) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR          (*(RwReg  *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET          (*(RwReg  *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG           (*(RwReg  *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS            (*(RwReg  *)0x42002830U) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT             (*(RwReg  *)0x42002834U) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE              (*(RwReg  *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER               (*(RwReg  *)0x42002840U) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0               (*(RwReg  *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1               (*(RwReg  *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB             (*(RwReg  *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB              (*(RwReg  *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0              (*(RwReg  *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1              (*(RwReg  *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC2 peripheral ========== */
+#define TCC2_CC_NUM                 2        // Number of Compare/Capture units
+#define TCC2_DITHERING              0        // Dithering feature implemented
+#define TCC2_DMAC_ID_MC_0           22
+#define TCC2_DMAC_ID_MC_1           23
+#define TCC2_DMAC_ID_MC_LSB         22
+#define TCC2_DMAC_ID_MC_MSB         23
+#define TCC2_DMAC_ID_MC_SIZE        2
+#define TCC2_DMAC_ID_OVF            21       // DMA overflow/underflow/retrigger trigger
+#define TCC2_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC2_EXT                    0        // Coding of implemented extended features
+#define TCC2_GCLK_ID                27       // Index of Generic Clock
+#define TCC2_MASTER                 0       
+#define TCC2_OTMX                   0        // Output Matrix feature implemented
+#define TCC2_OW_NUM                 2        // Number of Output Waveforms
+#define TCC2_PG                     0        // Pattern Generation feature implemented
+#define TCC2_SIZE                   16      
+#define TCC2_SWAP                   0        // DTI outputs swap feature implemented
+#define TCC2_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/usb.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/usb.h
new file mode 100644
index 0000000000..13b08bfbcd
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/usb.h
@@ -0,0 +1,344 @@
+/**
+ * \file
+ *
+ * \brief Instance description for USB
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_INSTANCE_
+#define _SAMD21_USB_INSTANCE_
+
+/* ========== Register definition for USB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USB_CTRLA              (0x41005000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY           (0x41005002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL            (0x41005003U) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS          (0x4100500DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD            (0x41005024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL             (0x41005028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB       (0x41005008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD        (0x4100500AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS      (0x4100500CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM        (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR    (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET    (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG     (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY   (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB         (0x41005008U) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC         (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS        (0x4100500CU) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM          (0x41005010U) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH      (0x41005012U) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR      (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET      (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG       (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY      (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0    (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1    (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2    (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3    (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4    (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5    (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6    (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7    (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#else
+#define REG_USB_CTRLA              (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY           (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL            (*(RwReg8 *)0x41005003U) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS          (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD            (*(RwReg  *)0x41005024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL             (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB       (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD        (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS      (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM        (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR    (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET    (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG     (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY   (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB         (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC         (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS        (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM          (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH      (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR      (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET      (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG       (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY      (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0    (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1    (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2    (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3    (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4    (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5    (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6    (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7    (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for USB peripheral ========== */
+#define USB_EPT_NBR                 8        // Number of USB end points (obsolete)
+#define USB_EPT_NUM                 8        // Number of USB end points
+#define USB_GCLK_ID                 6        // Index of Generic Clock
+#define USB_PIPE_NUM                8        // Number of USB pipes
+
+#endif /* _SAMD21_USB_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/wdt.h
new file mode 100644
index 0000000000..c8ee0e89b7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/wdt.h
@@ -0,0 +1,71 @@
+/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_INSTANCE_
+#define _SAMD21_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRL               (0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS             (0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR              (0x40001008U) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRL               (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS             (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR              (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for WDT peripheral ========== */
+#define WDT_GCLK_ID                 3        // Index of Generic Clock
+
+#endif /* _SAMD21_WDT_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h
new file mode 100644
index 0000000000..152aaa0d06
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h
@@ -0,0 +1,644 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21E15A_PIO_
+#define _SAMD21E15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E15A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h
new file mode 100644
index 0000000000..1ab51260fc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h
@@ -0,0 +1,641 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15B_PIO_
+#define _SAMD21E15B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E15B_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h
new file mode 100644
index 0000000000..7fdf91adbf
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h
@@ -0,0 +1,641 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15BU_PIO_
+#define _SAMD21E15BU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E15BU_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h
new file mode 100644
index 0000000000..3938fd62b2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h
@@ -0,0 +1,620 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15L_PIO_
+#define _SAMD21E15L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+
+#endif /* _SAMD21E15L_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h
new file mode 100644
index 0000000000..8ebe8bbed7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h
@@ -0,0 +1,644 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21E16A_PIO_
+#define _SAMD21E16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E16A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h
new file mode 100644
index 0000000000..0a12729b39
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h
@@ -0,0 +1,641 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16B_PIO_
+#define _SAMD21E16B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E16B_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h
new file mode 100644
index 0000000000..ab890b5cc6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h
@@ -0,0 +1,641 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16BU_PIO_
+#define _SAMD21E16BU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E16BU_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h
new file mode 100644
index 0000000000..85ac1e76eb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h
@@ -0,0 +1,620 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16L_PIO_
+#define _SAMD21E16L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+
+#endif /* _SAMD21E16L_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h
new file mode 100644
index 0000000000..cced9bdc93
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h
@@ -0,0 +1,644 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21E17A_PIO_
+#define _SAMD21E17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E17A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h
new file mode 100644
index 0000000000..fa4b94953a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h
@@ -0,0 +1,644 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21E18A_PIO_
+#define _SAMD21E18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E18A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h
new file mode 100644
index 0000000000..9c29c035bf
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h
@@ -0,0 +1,918 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21G15A_PIO_
+#define _SAMD21G15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G15A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h
new file mode 100644
index 0000000000..be61191bb5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h
@@ -0,0 +1,915 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15B_PIO_
+#define _SAMD21G15B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G15B_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h
new file mode 100644
index 0000000000..2a3133ca71
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h
@@ -0,0 +1,904 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15L_PIO_
+#define _SAMD21G15L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+
+#endif /* _SAMD21G15L_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h
new file mode 100644
index 0000000000..c5781d9119
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h
@@ -0,0 +1,918 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21G16A_PIO_
+#define _SAMD21G16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G16A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h
new file mode 100644
index 0000000000..0c86fcc9b3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h
@@ -0,0 +1,915 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16B_PIO_
+#define _SAMD21G16B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G16B_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h
new file mode 100644
index 0000000000..e46e4132c0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h
@@ -0,0 +1,904 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16L_PIO_
+#define _SAMD21G16L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+
+#endif /* _SAMD21G16L_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h
new file mode 100644
index 0000000000..6bf8421f8a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h
@@ -0,0 +1,918 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21G17A_PIO_
+#define _SAMD21G17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G17A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h
new file mode 100644
index 0000000000..4515df0625
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h
@@ -0,0 +1,866 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21G17AU_PIO_
+#define _SAMD21G17AU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G17AU_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h
new file mode 100644
index 0000000000..06605fadf9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h
@@ -0,0 +1,918 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21G18A_PIO_
+#define _SAMD21G18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G18A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h
new file mode 100644
index 0000000000..f4ff76b1d9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h
@@ -0,0 +1,866 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21G18AU_PIO_
+#define _SAMD21G18AU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G18AU_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h
new file mode 100644
index 0000000000..e113f94d7c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h
@@ -0,0 +1,1192 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21J15A_PIO_
+#define _SAMD21J15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J15A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h
new file mode 100644
index 0000000000..d0056e08b4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h
@@ -0,0 +1,1189 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15B_PIO_
+#define _SAMD21J15B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J15B_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h
new file mode 100644
index 0000000000..fe330c4dff
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h
@@ -0,0 +1,1192 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21J16A_PIO_
+#define _SAMD21J16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J16A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h
new file mode 100644
index 0000000000..1628f5b2a7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h
@@ -0,0 +1,1189 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16B_PIO_
+#define _SAMD21J16B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J16B_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h
new file mode 100644
index 0000000000..990f75fef4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h
@@ -0,0 +1,1192 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21J17A_PIO_
+#define _SAMD21J17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J17A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
new file mode 100644
index 0000000000..4ca3810cb2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
@@ -0,0 +1,1192 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21J18A_PIO_
+#define _SAMD21J18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J18A_PIO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21.h
new file mode 100644
index 0000000000..2e615135aa
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Top header file for SAMD21
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMD21_
+#define _SAMD21_
+
+/**
+ * \defgroup SAMD21_definitions SAMD21 Device Definitions
+ * \brief SAMD21 CMSIS Definitions.
+ */
+
+#if   defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
+  #include "samd21e15a.h"
+#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
+  #include "samd21e16a.h"
+#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
+  #include "samd21e17a.h"
+#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
+  #include "samd21e18a.h"
+#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
+  #include "samd21g15a.h"
+#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
+  #include "samd21g16a.h"
+#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
+  #include "samd21g17a.h"
+#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
+  #include "samd21g17au.h"
+#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
+  #include "samd21g18a.h"
+#elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
+  #include "samd21g18au.h"
+#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
+  #include "samd21j15a.h"
+#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
+  #include "samd21j16a.h"
+#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
+  #include "samd21j17a.h"
+#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
+  #include "samd21j18a.h"
+#elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__)
+  #include "samd21e15b.h"
+#elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__)
+  #include "samd21e15bu.h"
+#elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__)
+  #include "samd21e15l.h"
+#elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__)
+  #include "samd21e16b.h"
+#elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__)
+  #include "samd21e16bu.h"
+#elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__)
+  #include "samd21e16l.h"
+#elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__)
+  #include "samd21g15b.h"
+#elif defined(__SAMD21G15L__) || defined(__ATSAMD21G15L__)
+  #include "samd21g15l.h"
+#elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__)
+  #include "samd21g16b.h"
+#elif defined(__SAMD21G16L__) || defined(__ATSAMD21G16L__)
+  #include "samd21g16l.h"
+#elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__)
+  #include "samd21j15b.h"
+#elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__)
+  #include "samd21j16b.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAMD21_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15a.h
new file mode 100644
index 0000000000..405627e39b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15a.h
@@ -0,0 +1,557 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15A_
+#define _SAMD21E15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions
+ * This file defines all structures and symbols for SAMD21E15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000DUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15b.h
new file mode 100644
index 0000000000..e0d7f89b8b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15b.h
@@ -0,0 +1,561 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15B
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15B_
+#define _SAMD21E15B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15B_definitions SAMD21E15B definitions
+ * This file defines all structures and symbols for SAMD21E15B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E15B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011427UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15B_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15bu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15bu.h
new file mode 100644
index 0000000000..712124e8c7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15bu.h
@@ -0,0 +1,561 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15BU
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15BU_
+#define _SAMD21E15BU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15BU_definitions SAMD21E15BU definitions
+ * This file defines all structures and symbols for SAMD21E15BU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15BU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15BU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15BU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15BU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15BU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15BU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E15BU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15BU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15BU Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15bu.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011456UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15BU_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15l.h
new file mode 100644
index 0000000000..63d45a8e6c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15l.h
@@ -0,0 +1,540 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15L
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15L_
+#define _SAMD21E15L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15L_definitions SAMD21E15L definitions
+ * This file defines all structures and symbols for SAMD21E15L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+
+#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001143FUL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15L_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16a.h
new file mode 100644
index 0000000000..355a9f70ad
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16a.h
@@ -0,0 +1,557 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_
+#define _SAMD21E16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions
+ * This file defines all structures and symbols for SAMD21E16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000CUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16b.h
new file mode 100644
index 0000000000..1d9f1b72c7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16b.h
@@ -0,0 +1,561 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16B
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16B_
+#define _SAMD21E16B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16B_definitions SAMD21E16B definitions
+ * This file defines all structures and symbols for SAMD21E16B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E16B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011426UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16B_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16bu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16bu.h
new file mode 100644
index 0000000000..19b75a0b77
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16bu.h
@@ -0,0 +1,561 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16BU
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16BU_
+#define _SAMD21E16BU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16BU_definitions SAMD21E16BU definitions
+ * This file defines all structures and symbols for SAMD21E16BU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16BU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16BU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16BU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16BU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16BU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16BU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E16BU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16BU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16BU Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16bu.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011455UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16BU_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16l.h
new file mode 100644
index 0000000000..ea3e71e4a7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16l.h
@@ -0,0 +1,540 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16L
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16L_
+#define _SAMD21E16L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16L_definitions SAMD21E16L definitions
+ * This file defines all structures and symbols for SAMD21E16L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+
+#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001143EUL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16L_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e17a.h
new file mode 100644
index 0000000000..e4eb4badff
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e17a.h
@@ -0,0 +1,557 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_
+#define _SAMD21E17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions
+ * This file defines all structures and symbols for SAMD21E17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000BUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e18a.h
new file mode 100644
index 0000000000..08c0f0c672
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e18a.h
@@ -0,0 +1,557 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E18A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_
+#define _SAMD21E18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions
+ * This file defines all structures and symbols for SAMD21E18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000AUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E18A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15a.h
new file mode 100644
index 0000000000..7b280b6c0f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15a.h
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_
+#define _SAMD21G15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions
+ * This file defines all structures and symbols for SAMD21G15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010008UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15b.h
new file mode 100644
index 0000000000..0d490fe5dc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15b.h
@@ -0,0 +1,573 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15B
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15B_
+#define _SAMD21G15B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15B_definitions SAMD21G15B definitions
+ * This file defines all structures and symbols for SAMD21G15B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G15B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G15B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G15B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G15B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G15B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G15B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G15B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G15B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G15B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011424UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15B_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15l.h
new file mode 100644
index 0000000000..d0d9d06a98
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15l.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15L
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15L_
+#define _SAMD21G15L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15L_definitions SAMD21G15L definitions
+ * This file defines all structures and symbols for SAMD21G15L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G15L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G15L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G15L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G15L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G15L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G15L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G15L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15L Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15L Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15L Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G15L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G15L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G15L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G15L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G15L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G15L Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G15L Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G15L Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G15L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G15L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G15L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21G15L Analog Comparators 1 (AC1) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+
+#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011458UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15L_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16a.h
new file mode 100644
index 0000000000..c09b6eb0c2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16a.h
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_
+#define _SAMD21G16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions
+ * This file defines all structures and symbols for SAMD21G16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010007UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16b.h
new file mode 100644
index 0000000000..19220f35f0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16b.h
@@ -0,0 +1,573 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16B
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16B_
+#define _SAMD21G16B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16B_definitions SAMD21G16B definitions
+ * This file defines all structures and symbols for SAMD21G16B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G16B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G16B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G16B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G16B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G16B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G16B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G16B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G16B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G16B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011423UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16B_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16l.h
new file mode 100644
index 0000000000..833345ce98
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16l.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16L
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16L_
+#define _SAMD21G16L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16L_definitions SAMD21G16L definitions
+ * This file defines all structures and symbols for SAMD21G16L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G16L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G16L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G16L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G16L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G16L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G16L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G16L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16L Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16L Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16L Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G16L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G16L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G16L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G16L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G16L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G16L Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G16L Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G16L Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G16L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G16L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G16L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21G16L Analog Comparators 1 (AC1) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+
+#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011457UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16L_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17a.h
new file mode 100644
index 0000000000..2f8573e5fb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17a.h
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_
+#define _SAMD21G17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions
+ * This file defines all structures and symbols for SAMD21G17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010006UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17au.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17au.h
new file mode 100644
index 0000000000..7741063f22
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17au.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17AU
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17AU_
+#define _SAMD21G17AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions
+ * This file defines all structures and symbols for SAMD21G17AU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G17AU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G17AU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17AU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G17AU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G17AU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G17AU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G17AU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G17AU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010010UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17AU_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18a.h
new file mode 100644
index 0000000000..b6b2c5b8f5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18a.h
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_
+#define _SAMD21G18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
+ * This file defines all structures and symbols for SAMD21G18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010005UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18au.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18au.h
new file mode 100644
index 0000000000..e111aa7f20
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18au.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18AU
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18AU_
+#define _SAMD21G18AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions
+ * This file defines all structures and symbols for SAMD21G18AU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G18AU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G18AU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G18AU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G18AU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G18AU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G18AU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G18AU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G18AU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000FUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18AU_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15a.h
new file mode 100644
index 0000000000..8e582fbc42
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15a.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J15A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_
+#define _SAMD21J15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
+ * This file defines all structures and symbols for SAMD21J15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010003UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J15A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15b.h
new file mode 100644
index 0000000000..d60dfdce5d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15b.h
@@ -0,0 +1,585 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J15B
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15B_
+#define _SAMD21J15B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J15B_definitions SAMD21J15B definitions
+ * This file defines all structures and symbols for SAMD21J15B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J15B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J15B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J15B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J15B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J15B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J15B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J15B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J15B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J15B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J15B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j15b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011421UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J15B_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16a.h
new file mode 100644
index 0000000000..8cbf537709
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16a.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J16A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_
+#define _SAMD21J16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions
+ * This file defines all structures and symbols for SAMD21J16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010002UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J16A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16b.h
new file mode 100644
index 0000000000..97388d8ec3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16b.h
@@ -0,0 +1,585 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J16B
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16B_
+#define _SAMD21J16B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J16B_definitions SAMD21J16B definitions
+ * This file defines all structures and symbols for SAMD21J16B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J16B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J16B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J16B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J16B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J16B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J16B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J16B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J16B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J16B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J16B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j16b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011420UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J16B_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j17a.h
new file mode 100644
index 0000000000..e6397a1ea7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j17a.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J17A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_
+#define _SAMD21J17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
+ * This file defines all structures and symbols for SAMD21J17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010001UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J17A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j18a.h
new file mode 100644
index 0000000000..b23bd6bd69
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j18a.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J18A
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_
+#define _SAMD21J18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions
+ * This file defines all structures and symbols for SAMD21J18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010000UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J18A_H */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/arm/startup_SAMD21.s b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/arm/startup_SAMD21.s
new file mode 100644
index 0000000000..3e54e2dc6c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/arm/startup_SAMD21.s
@@ -0,0 +1,247 @@
+;/*****************************************************************************
+; * @file     startup_SAMD21.s
+; * @brief    CMSIS Cortex-M0+ Core Device Startup File for
+; *           Atmel SAMD21 Device Series
+; * @version  V1.01
+; * @date     25. March 2015
+; *
+; * @note
+; * Copyright (C) 2014 - 2015 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     PM_Handler                ;  0 Power Manager
+                DCD     SYSCTRL_Handler           ;  1 System Control
+                DCD     WDT_Handler               ;  2 Watchdog Timer
+                DCD     RTC_Handler               ;  3 Real-Time Counter
+                DCD     EIC_Handler               ;  4 External Interrupt Controller
+                DCD     NVMCTRL_Handler           ;  5 Non-Volatile Memory Controller
+                DCD     DMAC_Handler              ;  6 Direct Memory Access Controller
+                DCD     USB_Handler               ;  7 Universal Serial Bus
+                DCD     EVSYS_Handler             ;  8 Event System Interface
+                DCD     SERCOM0_Handler           ;  9 Serial Communication Interface 0
+                DCD     SERCOM1_Handler           ; 10 Serial Communication Interface 1
+                DCD     SERCOM2_Handler           ; 11 Serial Communication Interface 2
+                DCD     SERCOM3_Handler           ; 12 Serial Communication Interface 3
+                DCD     SERCOM4_Handler           ; 13 Serial Communication Interface 4
+                DCD     SERCOM5_Handler           ; 14 Serial Communication Interface 5
+                DCD     TCC0_Handler              ; 15 Timer Counter Control 0
+                DCD     TCC1_Handler              ; 16 Timer Counter Control 1
+                DCD     TCC2_Handler              ; 17 Timer Counter Control 2
+                DCD     TC3_Handler               ; 18 Basic Timer Counter 0
+                DCD     TC4_Handler               ; 19 Basic Timer Counter 1
+                DCD     TC5_Handler               ; 20 Basic Timer Counter 2
+                DCD     TC6_Handler               ; 21 Basic Timer Counter 3
+                DCD     TC7_Handler               ; 22 Basic Timer Counter 4
+                DCD     ADC_Handler               ; 23 Analog Digital Converter
+                DCD     AC_Handler                ; 24 Analog Comparators
+                DCD     DAC_Handler               ; 25 Digital Analog Converter
+                DCD     PTC_Handler               ; 26 Peripheral Touch Controller
+                DCD     I2S_Handler               ; 27 Inter-IC Sound Interface
+                DCD     AC1_Handler               ; 28 Analog Comparators 1
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  PM_Handler                [WEAK]
+                EXPORT  PM_Handler                [WEAK]
+                EXPORT  SYSCTRL_Handler           [WEAK]
+                EXPORT  WDT_Handler               [WEAK]
+                EXPORT  RTC_Handler               [WEAK]
+                EXPORT  EIC_Handler               [WEAK]
+                EXPORT  NVMCTRL_Handler           [WEAK]
+                EXPORT  DMAC_Handler              [WEAK]
+                EXPORT  USB_Handler               [WEAK]
+                EXPORT  EVSYS_Handler             [WEAK]
+                EXPORT  SERCOM0_Handler           [WEAK]
+                EXPORT  SERCOM1_Handler           [WEAK]
+                EXPORT  SERCOM2_Handler           [WEAK]
+                EXPORT  SERCOM3_Handler           [WEAK]
+                EXPORT  SERCOM4_Handler           [WEAK]
+                EXPORT  SERCOM5_Handler           [WEAK]
+                EXPORT  TCC0_Handler              [WEAK]
+                EXPORT  TCC1_Handler              [WEAK]
+                EXPORT  TCC2_Handler              [WEAK]
+                EXPORT  TC3_Handler               [WEAK]
+                EXPORT  TC4_Handler               [WEAK]
+                EXPORT  TC5_Handler               [WEAK]
+                EXPORT  TC6_Handler               [WEAK]
+                EXPORT  TC7_Handler               [WEAK]
+                EXPORT  ADC_Handler               [WEAK]
+                EXPORT  AC_Handler                [WEAK]
+                EXPORT  DAC_Handler               [WEAK]
+                EXPORT  PTC_Handler               [WEAK]
+                EXPORT  I2S_Handler               [WEAK]
+                EXPORT  AC1_Handler               [WEAK]
+
+PM_Handler
+SYSCTRL_Handler
+WDT_Handler
+RTC_Handler
+EIC_Handler
+NVMCTRL_Handler
+DMAC_Handler
+USB_Handler
+EVSYS_Handler
+SERCOM0_Handler
+SERCOM1_Handler
+SERCOM2_Handler
+SERCOM3_Handler
+SERCOM4_Handler
+SERCOM5_Handler
+TCC0_Handler
+TCC1_Handler
+TCC2_Handler
+TC3_Handler
+TC4_Handler
+TC5_Handler
+TC6_Handler
+TC7_Handler
+ADC_Handler
+AC_Handler
+DAC_Handler
+PTC_Handler
+I2S_Handler
+AC1_Handler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
new file mode 100644
index 0000000000..d2611b3d57
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
@@ -0,0 +1,282 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD21
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_USB
+void USB_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void EVSYS_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SERCOM4
+void SERCOM4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_ADC
+void ADC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_DAC
+void DAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PTC
+void PTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC1
+void AC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&_estack),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNMI_Handler         = (void*) NMI_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pvReservedM12          = (void*) (0UL), /* Reserved */
+        .pvReservedM11          = (void*) (0UL), /* Reserved */
+        .pvReservedM10          = (void*) (0UL), /* Reserved */
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVC_Handler         = (void*) SVC_Handler,
+        .pvReservedM4           = (void*) (0UL), /* Reserved */
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnSYSCTRL_Handler     = (void*) SYSCTRL_Handler,        /*  1 System Control */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /*  2 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /*  3 Real-Time Counter */
+        .pfnEIC_Handler         = (void*) EIC_Handler,            /*  4 External Interrupt Controller */
+        .pfnNVMCTRL_Handler     = (void*) NVMCTRL_Handler,        /*  5 Non-Volatile Memory Controller */
+        .pfnDMAC_Handler        = (void*) DMAC_Handler,           /*  6 Direct Memory Access Controller */
+#ifdef ID_USB
+        .pfnUSB_Handler         = (void*) USB_Handler,            /*  7 Universal Serial Bus */
+#else
+        .pvReserved7            = (void*) (0UL),                  /*  7 Reserved */
+#endif
+        .pfnEVSYS_Handler       = (void*) EVSYS_Handler,          /*  8 Event System Interface */
+        .pfnSERCOM0_Handler     = (void*) SERCOM0_Handler,        /*  9 Serial Communication Interface 0 */
+        .pfnSERCOM1_Handler     = (void*) SERCOM1_Handler,        /* 10 Serial Communication Interface 1 */
+        .pfnSERCOM2_Handler     = (void*) SERCOM2_Handler,        /* 11 Serial Communication Interface 2 */
+        .pfnSERCOM3_Handler     = (void*) SERCOM3_Handler,        /* 12 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_Handler     = (void*) SERCOM4_Handler,        /* 13 Serial Communication Interface 4 */
+#else
+        .pvReserved13           = (void*) (0UL),                  /* 13 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_Handler     = (void*) SERCOM5_Handler,        /* 14 Serial Communication Interface 5 */
+#else
+        .pvReserved14           = (void*) (0UL),                  /* 14 Reserved */
+#endif
+        .pfnTCC0_Handler        = (void*) TCC0_Handler,           /* 15 Timer Counter Control 0 */
+        .pfnTCC1_Handler        = (void*) TCC1_Handler,           /* 16 Timer Counter Control 1 */
+        .pfnTCC2_Handler        = (void*) TCC2_Handler,           /* 17 Timer Counter Control 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 18 Basic Timer Counter 0 */
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 19 Basic Timer Counter 1 */
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 20 Basic Timer Counter 2 */
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 21 Basic Timer Counter 3 */
+#else
+        .pvReserved21           = (void*) (0UL),                  /* 21 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 22 Basic Timer Counter 4 */
+#else
+        .pvReserved22           = (void*) (0UL),                  /* 22 Reserved */
+#endif
+#ifdef ID_ADC
+        .pfnADC_Handler         = (void*) ADC_Handler,            /* 23 Analog Digital Converter */
+#else
+        .pvReserved23           = (void*) (0UL),                  /* 23 Reserved */
+#endif
+#ifdef ID_AC
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 24 Analog Comparators 0 */
+#else
+        .pvReserved24           = (void*) (0UL),                  /* 24 Reserved */
+#endif
+#ifdef ID_DAC
+        .pfnDAC_Handler         = (void*) DAC_Handler,            /* 25 Digital Analog Converter */
+#else
+        .pvReserved25           = (void*) (0UL),                  /* 25 Reserved */
+#endif
+#ifdef ID_PTC
+        .pfnPTC_Handler         = (void*) PTC_Handler,            /* 26 Peripheral Touch Controller */
+#else
+        .pvReserved26           = (void*) (0UL),                  /* 26 Reserved */
+#endif
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 27 Inter-IC Sound Interface */
+#else
+        .pvReserved27           = (void*) (0UL),                  /* 27 Reserved */
+#endif
+#ifdef ID_AC1
+        .pfnAC1_Handler         = (void*) AC1_Handler             /* 28 Analog Comparators 1 */
+#else
+        .pvReserved28           = (void*) (0UL)                   /* 28 Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+        uint32_t *pSrc, *pDest;
+
+        /* Initialize the relocate segment */
+        pSrc = &_etext;
+        pDest = &_srelocate;
+
+        if (pSrc != pDest) {
+                for (; pDest < &_erelocate;) {
+                        *pDest++ = *pSrc++;
+                }
+        }
+
+        /* Clear the zero segment */
+        for (pDest = &_szero; pDest < &_ezero;) {
+                *pDest++ = 0;
+        }
+
+        /* Set the vector table base address */
+        pSrc = (uint32_t *) & _sfixed;
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+        /* Change default QOS values to have the best performance and correct USB behaviour */
+        SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+#if defined(ID_USB)
+        USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+        USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+#endif
+        DMAC->QOSCTRL.bit.DQOS = 2;
+        DMAC->QOSCTRL.bit.FQOS = 2;
+        DMAC->QOSCTRL.bit.WRBQOS = 2;
+
+        /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+        NVMCTRL->CTRLB.bit.MANW = 1;
+
+        /* Initialize the C library */
+        __libc_init_array();
+
+        /* Branch to main function */
+        main();
+
+        /* Infinite loop */
+        while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c
new file mode 100644
index 0000000000..2e8aae7d83
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c
@@ -0,0 +1,259 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+typedef void (*intfunc) (void);
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+#pragma weak NMI_Handler              = Dummy_Handler
+#pragma weak HardFault_Handler        = Dummy_Handler
+#pragma weak SVC_Handler              = Dummy_Handler
+#pragma weak PendSV_Handler           = Dummy_Handler
+#pragma weak SysTick_Handler          = Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak PM_Handler               = Dummy_Handler
+#pragma weak SYSCTRL_Handler          = Dummy_Handler
+#pragma weak WDT_Handler              = Dummy_Handler
+#pragma weak RTC_Handler              = Dummy_Handler
+#pragma weak EIC_Handler              = Dummy_Handler
+#pragma weak NVMCTRL_Handler          = Dummy_Handler
+#pragma weak DMAC_Handler             = Dummy_Handler
+#ifdef       ID_USB
+#pragma weak USB_Handler              = Dummy_Handler
+#endif
+#pragma weak EVSYS_Handler            = Dummy_Handler
+#pragma weak SERCOM0_Handler          = Dummy_Handler
+#pragma weak SERCOM1_Handler          = Dummy_Handler
+#pragma weak SERCOM2_Handler          = Dummy_Handler
+#pragma weak SERCOM3_Handler          = Dummy_Handler
+#ifdef       ID_SERCOM4
+#pragma weak SERCOM4_Handler          = Dummy_Handler
+#endif
+#ifdef       ID_SERCOM5
+#pragma weak SERCOM5_Handler          = Dummy_Handler
+#endif
+#pragma weak TCC0_Handler             = Dummy_Handler
+#pragma weak TCC1_Handler             = Dummy_Handler
+#pragma weak TCC2_Handler             = Dummy_Handler
+#pragma weak TC3_Handler              = Dummy_Handler
+#pragma weak TC4_Handler              = Dummy_Handler
+#pragma weak TC5_Handler              = Dummy_Handler
+#ifdef       ID_TC6
+#pragma weak TC6_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_TC7
+#pragma weak TC7_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_ADC
+#pragma weak ADC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_AC
+#pragma weak AC_Handler               = Dummy_Handler
+#endif
+#ifdef       ID_DAC
+#pragma weak DAC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_PTC
+#pragma weak PTC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_I2S
+#pragma weak I2S_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_AC1
+#pragma weak AC1_Handler              = Dummy_Handler
+#endif
+
+/* Exception Table */
+#pragma language = extended
+#pragma segment  = "CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section  = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+        (void*) __sfe("CSTACK"),
+        (void*) Reset_Handler,
+        (void*) NMI_Handler,
+        (void*) HardFault_Handler,
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) SVC_Handler,
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) PendSV_Handler,
+        (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        (void*) PM_Handler,             /*  0 Power Manager */
+        (void*) SYSCTRL_Handler,        /*  1 System Control */
+        (void*) WDT_Handler,            /*  2 Watchdog Timer */
+        (void*) RTC_Handler,            /*  3 Real-Time Counter */
+        (void*) EIC_Handler,            /*  4 External Interrupt Controller */
+        (void*) NVMCTRL_Handler,        /*  5 Non-Volatile Memory Controller */
+        (void*) DMAC_Handler,           /*  6 Direct Memory Access Controller */
+#ifdef ID_USB
+        (void*) USB_Handler,            /*  7 Universal Serial Bus */
+#else
+        (void*) (0UL),                  /*  7 Reserved */
+#endif
+        (void*) EVSYS_Handler,          /*  8 Event System Interface */
+        (void*) SERCOM0_Handler,        /*  9 Serial Communication Interface 0 */
+        (void*) SERCOM1_Handler,        /* 10 Serial Communication Interface 1 */
+        (void*) SERCOM2_Handler,        /* 11 Serial Communication Interface 2 */
+        (void*) SERCOM3_Handler,        /* 12 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+        (void*) SERCOM4_Handler,        /* 13 Serial Communication Interface 4 */
+#else
+        (void*) (0UL),                  /* 13 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        (void*) SERCOM5_Handler,        /* 14 Serial Communication Interface 5 */
+#else
+        (void*) (0UL),                  /* 14 Reserved */
+#endif
+        (void*) TCC0_Handler,           /* 15 Timer Counter Control 0 */
+        (void*) TCC1_Handler,           /* 16 Timer Counter Control 1 */
+        (void*) TCC2_Handler,           /* 17 Timer Counter Control 2 */
+        (void*) TC3_Handler,            /* 18 Basic Timer Counter 0 */
+        (void*) TC4_Handler,            /* 19 Basic Timer Counter 1 */
+        (void*) TC5_Handler,            /* 20 Basic Timer Counter 2 */
+#ifdef ID_TC6
+        (void*) TC6_Handler,            /* 21 Basic Timer Counter 3 */
+#else
+        (void*) (0UL),                  /* 21 Reserved */
+#endif
+#ifdef ID_TC7
+        (void*) TC7_Handler,            /* 22 Basic Timer Counter 4 */
+#else
+        (void*) (0UL),                  /* 22 Reserved */
+#endif
+#ifdef ID_ADC
+        (void*) ADC_Handler,            /* 23 Analog Digital Converter */
+#else
+        (void*) (0UL),                  /* 23 Reserved */
+#endif
+#ifdef ID_AC
+        (void*) AC_Handler,             /* 24 Analog Comparators 0 */
+#else
+        (void*) (0UL),                  /* 24 Reserved */
+#endif
+#ifdef ID_DAC
+        (void*) DAC_Handler,            /* 25 Digital Analog Converter */
+#else
+        (void*) (0UL),                  /* 25 Reserved */
+#endif
+#ifdef ID_PTC
+        (void*) PTC_Handler,            /* 26 Peripheral Touch Controller */
+#else
+        (void*) (0UL),                  /* 26 Reserved */
+#endif
+#ifdef ID_I2S
+        (void*) I2S_Handler,            /* 27 Inter-IC Sound Interface */
+#else
+        (void*) (0UL),                  /* 27 Reserved */
+#endif
+#ifdef ID_AC1
+        (void*) AC1_Handler             /* 28 Analog Comparators 1 */
+#else
+        (void*) (0UL)                   /* 28 Reserved */
+#endif
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+        uint32_t *pSrc = __section_begin(".intvec");
+
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+        return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+        /* Change default QOS values to have the best performance and correct USB behaviour */
+        SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+#if defined(ID_USB)
+        USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+        USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+#endif
+        DMAC->QOSCTRL.bit.DQOS = 2;
+        DMAC->QOSCTRL.bit.FQOS = 2;
+        DMAC->QOSCTRL.bit.WRBQOS = 2;
+
+        /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+        NVMCTRL->CTRLB.bit.MANW = 1;
+
+        __iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.c
new file mode 100644
index 0000000000..f3ebdc8b76
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.c
@@ -0,0 +1,81 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "samd21.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK    (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+	// Keep the default device state after reset
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+	// Not implemented
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.h
new file mode 100644
index 0000000000..564f47f359
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.h
@@ -0,0 +1,65 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SYSTEM_SAMD21_H_INCLUDED_
+#define _SYSTEM_SAMD21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;   /*!< System Clock Frequency (Core Clock)  */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMD21_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/compiler.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/compiler.h
new file mode 100644
index 0000000000..ca488dce9b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/compiler.h
@@ -0,0 +1,1174 @@
+/**
+ * \file
+ *
+ * \brief Commonly used includes, types and macros.
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef UTILS_COMPILER_H_INCLUDED
+#define UTILS_COMPILER_H_INCLUDED
+
+/**
+ * \defgroup group_sam0_utils Compiler abstraction layer and code utilities
+ *
+ * Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices.
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.
+ *
+ * @{
+ */
+
+#if (defined __ICCARM__)
+#  include <intrinsics.h>
+#endif
+
+#include <stddef.h>
+#include <parts.h>
+#include <status_codes.h>
+#include <preprocessor.h>
+#include <io.h>
+
+#ifndef __ASSEMBLY__
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * \def UNUSED
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define UNUSED(v)          (void)(v)
+
+/**
+ * \def barrier
+ * \brief Memory barrier
+ */
+#ifdef __GNUC__
+#  define barrier()        asm volatile("" ::: "memory")
+#else
+#  define barrier()        asm ("")
+#endif
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param[in] arg  The pragma directive as it would appear after \e \#pragma
+ *             (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg)          _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment)  COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union definitions.
+ */
+#define COMPILER_PACK_RESET()         COMPILER_PRAGMA(pack())
+
+
+/**
+ * \brief Set aligned boundary.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define COMPILER_ALIGNED(a)        __attribute__((__aligned__(a)))
+#elif (defined __ICCARM__)
+#   define COMPILER_ALIGNED(a)        COMPILER_PRAGMA(data_alignment = a)
+#endif
+
+/**
+ * \brief Set word-aligned boundary.
+ */
+#if (defined __GNUC__) || defined(__CC_ARM)
+#define COMPILER_WORD_ALIGNED         __attribute__((__aligned__(4)))
+#elif (defined __ICCARM__)
+#define COMPILER_WORD_ALIGNED         COMPILER_PRAGMA(data_alignment = 4)
+#endif
+
+/**
+ * \def __always_inline
+ * \brief The function should always be inlined.
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and inline the function no matter how big it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+#  define __always_inline             __forceinline
+#elif (defined __GNUC__)
+#  define __always_inline             __attribute__((__always_inline__))
+#elif (defined __ICCARM__)
+#  define __always_inline             _Pragma("inline=forced")
+#endif
+
+/**
+ * \def __no_inline
+ * \brief The function should never be inlined
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and not inline the function no matter how small it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+#  define __no_inline                 __attribute__((noinline))
+#elif (defined __GNUC__)
+#  define __no_inline                 __attribute__((noinline))
+#elif (defined __ICCARM__)
+#  define __no_inline                 _Pragma("inline=never")
+#endif
+
+
+/** \brief This macro is used to test fatal errors.
+ *
+ * The macro tests if the expression is false. If it is, a fatal error is
+ * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO
+ * is defined, a unit test version of the macro is used, to allow execution
+ * of further tests after a false expression.
+ *
+ * \param[in] expr  Expression to evaluate and supposed to be nonzero.
+ */
+#if defined(_ASSERT_ENABLE_)
+#  if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
+#    include "unit_test/suite.h"
+#  else
+#    undef TEST_SUITE_DEFINE_ASSERT_MACRO
+#    define Assert(expr) \
+        {\
+           if (!(expr)) asm("BKPT #0");\
+        }
+#  endif
+#else
+#  define Assert(expr) ((void) 0)
+#endif
+
+/* Define WEAK attribute */
+#if defined   ( __CC_ARM   )
+#   define WEAK __attribute__ ((weak))
+#elif defined ( __ICCARM__ )
+#   define WEAK __weak
+#elif defined (  __GNUC__  )
+#   define WEAK __attribute__ ((weak))
+#endif
+
+/* Define NO_INIT attribute */
+#if defined   ( __CC_ARM   )
+#   define NO_INIT __attribute__((zero_init))
+#elif defined ( __ICCARM__ )
+#   define NO_INIT __no_init
+#elif defined (  __GNUC__  )
+#   define NO_INIT __attribute__((section(".no_init")))
+#endif
+
+#include "interrupt.h"
+
+/** \name Usual Types
+ * @{ */
+#ifndef __cplusplus
+#  if !defined(__bool_true_false_are_defined)
+typedef unsigned char           bool;
+#  endif
+#endif
+typedef uint16_t                le16_t;
+typedef uint16_t                be16_t;
+typedef uint32_t                le32_t;
+typedef uint32_t                be32_t;
+typedef uint32_t                iram_size_t;
+/** @} */
+
+/** \name Aliasing Aggregate Types
+ * @{ */
+
+/** 16-bit union. */
+typedef union
+{
+  int16_t  s16;
+  uint16_t u16;
+  int8_t   s8[2];
+  uint8_t  u8[2];
+} Union16;
+
+/** 32-bit union. */
+typedef union
+{
+  int32_t  s32;
+  uint32_t u32;
+  int16_t  s16[2];
+  uint16_t u16[2];
+  int8_t   s8[4];
+  uint8_t  u8[4];
+} Union32;
+
+/** 64-bit union. */
+typedef union
+{
+  int64_t  s64;
+  uint64_t u64;
+  int32_t  s32[2];
+  uint32_t u32[2];
+  int16_t  s16[4];
+  uint16_t u16[4];
+  int8_t   s8[8];
+  uint8_t  u8[8];
+} Union64;
+
+/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+  int64_t  *s64ptr;
+  uint64_t *u64ptr;
+  int32_t  *s32ptr;
+  uint32_t *u32ptr;
+  int16_t  *s16ptr;
+  uint16_t *u16ptr;
+  int8_t   *s8ptr;
+  uint8_t  *u8ptr;
+} UnionPtr;
+
+/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+  volatile int64_t  *s64ptr;
+  volatile uint64_t *u64ptr;
+  volatile int32_t  *s32ptr;
+  volatile uint32_t *u32ptr;
+  volatile int16_t  *s16ptr;
+  volatile uint16_t *u16ptr;
+  volatile int8_t   *s8ptr;
+  volatile uint8_t  *u8ptr;
+} UnionVPtr;
+
+/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+  const int64_t  *s64ptr;
+  const uint64_t *u64ptr;
+  const int32_t  *s32ptr;
+  const uint32_t *u32ptr;
+  const int16_t  *s16ptr;
+  const uint16_t *u16ptr;
+  const int8_t   *s8ptr;
+  const uint8_t  *u8ptr;
+} UnionCPtr;
+
+/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+  const volatile int64_t  *s64ptr;
+  const volatile uint64_t *u64ptr;
+  const volatile int32_t  *s32ptr;
+  const volatile uint32_t *u32ptr;
+  const volatile int16_t  *s16ptr;
+  const volatile uint16_t *u16ptr;
+  const volatile int8_t   *s8ptr;
+  const volatile uint8_t  *u8ptr;
+} UnionCVPtr;
+
+/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+  int64_t  *s64ptr;
+  uint64_t *u64ptr;
+  int32_t  *s32ptr;
+  uint32_t *u32ptr;
+  int16_t  *s16ptr;
+  uint16_t *u16ptr;
+  int8_t   *s8ptr;
+  uint8_t  *u8ptr;
+} StructPtr;
+
+/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+  volatile int64_t  *s64ptr;
+  volatile uint64_t *u64ptr;
+  volatile int32_t  *s32ptr;
+  volatile uint32_t *u32ptr;
+  volatile int16_t  *s16ptr;
+  volatile uint16_t *u16ptr;
+  volatile int8_t   *s8ptr;
+  volatile uint8_t  *u8ptr;
+} StructVPtr;
+
+/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+  const int64_t  *s64ptr;
+  const uint64_t *u64ptr;
+  const int32_t  *s32ptr;
+  const uint32_t *u32ptr;
+  const int16_t  *s16ptr;
+  const uint16_t *u16ptr;
+  const int8_t   *s8ptr;
+  const uint8_t  *u8ptr;
+} StructCPtr;
+
+/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+  const volatile int64_t  *s64ptr;
+  const volatile uint64_t *u64ptr;
+  const volatile int32_t  *s32ptr;
+  const volatile uint32_t *u32ptr;
+  const volatile int16_t  *s16ptr;
+  const volatile uint16_t *u16ptr;
+  const volatile int8_t   *s8ptr;
+  const volatile uint8_t  *u8ptr;
+} StructCVPtr;
+
+/** @} */
+
+#endif  /* #ifndef __ASSEMBLY__ */
+
+/** \name Usual Constants
+ * @{ */
+#define DISABLE   0
+#define ENABLE    1
+
+#ifndef __cplusplus
+#  if !defined(__bool_true_false_are_defined)
+#    define false     0
+#    define true      1
+#  endif
+#endif
+/** @} */
+
+#ifndef __ASSEMBLY__
+
+/** \name Optimization Control
+ * @{ */
+
+/**
+ * \def likely(exp)
+ * \brief The expression \a exp is likely to be true
+ */
+#if !defined(likely) || defined(__DOXYGEN__)
+#   define likely(exp)    (exp)
+#endif
+
+/**
+ * \def unlikely(exp)
+ * \brief The expression \a exp is unlikely to be true
+ */
+#if !defined(unlikely) || defined(__DOXYGEN__)
+#   define unlikely(exp)  (exp)
+#endif
+
+/**
+ * \def is_constant(exp)
+ * \brief Determine if an expression evaluates to a constant value.
+ *
+ * \param[in] exp Any expression
+ *
+ * \return true if \a exp is constant, false otherwise.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define is_constant(exp)       __builtin_constant_p(exp)
+#else
+#   define is_constant(exp)       (0)
+#endif
+
+/** @} */
+
+/** \name Bit-Field Handling
+ * @{ */
+
+/** \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value to read bits from.
+ * \param[in] mask  Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask)        ((value) & (mask))
+
+/** \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue  C lvalue to write bits to.
+ * \param[in] mask    Bit-mask indicating bits to write.
+ * \param[in] bits    Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits)  ((lvalue) = ((lvalue) & ~(mask)) |\
+                                                 ((bits  ) &  (mask)))
+
+/** \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value of which to test bits.
+ * \param[in] mask  Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask)  (Rd_bits(value, mask) != 0)
+
+/** \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue  C lvalue of which to clear bits.
+ * \param[in] mask    Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask)  ((lvalue) &= ~(mask))
+
+/** \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue  C lvalue of which to set bits.
+ * \param[in] mask    Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask)  ((lvalue) |=  (mask))
+
+/** \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue  C lvalue of which to toggle bits.
+ * \param[in] mask    Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask)  ((lvalue) ^=  (mask))
+
+/** \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value to read a bit-field from.
+ * \param[in] mask  Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask)           (Rd_bits( value, mask) >> ctz(mask))
+
+/** \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue    C lvalue to write a bit-field to.
+ * \param[in] mask      Bit-mask indicating the bit-field to write.
+ * \param[in] bitfield  Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask)))
+
+/** @} */
+
+
+/** \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ *
+ * @{ */
+
+/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define clz(u)              ((u) ? __builtin_clz(u) : 32)
+#else
+#   define clz(u)              (((u) == 0)          ? 32 : \
+                                ((u) & (1ul << 31)) ?  0 : \
+                                ((u) & (1ul << 30)) ?  1 : \
+                                ((u) & (1ul << 29)) ?  2 : \
+                                ((u) & (1ul << 28)) ?  3 : \
+                                ((u) & (1ul << 27)) ?  4 : \
+                                ((u) & (1ul << 26)) ?  5 : \
+                                ((u) & (1ul << 25)) ?  6 : \
+                                ((u) & (1ul << 24)) ?  7 : \
+                                ((u) & (1ul << 23)) ?  8 : \
+                                ((u) & (1ul << 22)) ?  9 : \
+                                ((u) & (1ul << 21)) ? 10 : \
+                                ((u) & (1ul << 20)) ? 11 : \
+                                ((u) & (1ul << 19)) ? 12 : \
+                                ((u) & (1ul << 18)) ? 13 : \
+                                ((u) & (1ul << 17)) ? 14 : \
+                                ((u) & (1ul << 16)) ? 15 : \
+                                ((u) & (1ul << 15)) ? 16 : \
+                                ((u) & (1ul << 14)) ? 17 : \
+                                ((u) & (1ul << 13)) ? 18 : \
+                                ((u) & (1ul << 12)) ? 19 : \
+                                ((u) & (1ul << 11)) ? 20 : \
+                                ((u) & (1ul << 10)) ? 21 : \
+                                ((u) & (1ul <<  9)) ? 22 : \
+                                ((u) & (1ul <<  8)) ? 23 : \
+                                ((u) & (1ul <<  7)) ? 24 : \
+                                ((u) & (1ul <<  6)) ? 25 : \
+                                ((u) & (1ul <<  5)) ? 26 : \
+                                ((u) & (1ul <<  4)) ? 27 : \
+                                ((u) & (1ul <<  3)) ? 28 : \
+                                ((u) & (1ul <<  2)) ? 29 : \
+                                ((u) & (1ul <<  1)) ? 30 : \
+                                31)
+#endif
+
+/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define ctz(u)              ((u) ? __builtin_ctz(u) : 32)
+#else
+#   define ctz(u)              ((u) & (1ul <<  0) ?  0 : \
+                                (u) & (1ul <<  1) ?  1 : \
+                                (u) & (1ul <<  2) ?  2 : \
+                                (u) & (1ul <<  3) ?  3 : \
+                                (u) & (1ul <<  4) ?  4 : \
+                                (u) & (1ul <<  5) ?  5 : \
+                                (u) & (1ul <<  6) ?  6 : \
+                                (u) & (1ul <<  7) ?  7 : \
+                                (u) & (1ul <<  8) ?  8 : \
+                                (u) & (1ul <<  9) ?  9 : \
+                                (u) & (1ul << 10) ? 10 : \
+                                (u) & (1ul << 11) ? 11 : \
+                                (u) & (1ul << 12) ? 12 : \
+                                (u) & (1ul << 13) ? 13 : \
+                                (u) & (1ul << 14) ? 14 : \
+                                (u) & (1ul << 15) ? 15 : \
+                                (u) & (1ul << 16) ? 16 : \
+                                (u) & (1ul << 17) ? 17 : \
+                                (u) & (1ul << 18) ? 18 : \
+                                (u) & (1ul << 19) ? 19 : \
+                                (u) & (1ul << 20) ? 20 : \
+                                (u) & (1ul << 21) ? 21 : \
+                                (u) & (1ul << 22) ? 22 : \
+                                (u) & (1ul << 23) ? 23 : \
+                                (u) & (1ul << 24) ? 24 : \
+                                (u) & (1ul << 25) ? 25 : \
+                                (u) & (1ul << 26) ? 26 : \
+                                (u) & (1ul << 27) ? 27 : \
+                                (u) & (1ul << 28) ? 28 : \
+                                (u) & (1ul << 29) ? 29 : \
+                                (u) & (1ul << 30) ? 30 : \
+                                (u) & (1ul << 31) ? 31 : \
+                                32)
+#endif
+
+/** @} */
+
+
+/** \name Bit Reversing
+ * @{ */
+
+/** \brief Reverses the bits of \a u8.
+ *
+ * \param[in] u8  U8 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u8 with reversed bits.
+ */
+#define bit_reverse8(u8)    ((U8)(bit_reverse32((U8)(u8)) >> 24))
+
+/** \brief Reverses the bits of \a u16.
+ *
+ * \param[in] u16 U16 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u16 with reversed bits.
+ */
+#define bit_reverse16(u16)  ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16))
+
+/** \brief Reverses the bits of \a u32.
+ *
+ * \param[in] u32 U32 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u32 with reversed bits.
+ */
+#define bit_reverse32(u32)   __RBIT(u32)
+
+/** \brief Reverses the bits of \a u64.
+ *
+ * \param[in] u64 U64 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u64 with reversed bits.
+ */
+#define bit_reverse64(u64)  ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) |\
+                                   ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32)))
+
+/** @} */
+
+
+/** \name Alignment
+ * @{ */
+
+/** \brief Tests alignment of the number \a val with the \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n   Boundary.
+ *
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
+ */
+#define Test_align(val, n) (!Tst_bits( val, (n) - 1     )   )
+
+/** \brief Gets alignment of the number \a val with respect to the \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n   Boundary.
+ *
+ * \return Alignment of the number \a val with respect to the \a n boundary.
+ */
+#define Get_align(val, n) (  Rd_bits( val, (n) - 1     )   )
+
+/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
+ *
+ * \param[in] lval  Input/output lvalue.
+ * \param[in] n     Boundary.
+ * \param[in] alg   Alignment.
+ *
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
+ */
+#define Set_align(lval, n, alg) (  Wr_bits(lval, (n) - 1, alg)   )
+
+/** \brief Aligns the number \a val with the upper \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n   Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.
+ */
+#define Align_up(  val, n) (((val) + ((n) - 1)) & ~((n) - 1))
+
+/** \brief Aligns the number \a val with the lower \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n   Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.
+ */
+#define Align_down(val, n) ( (val)              & ~((n) - 1))
+
+/** @} */
+
+
+/** \name Mathematics
+ *
+ * The same considerations as for clz and ctz apply here but GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ *   - Abs, Min and Max to apply to constant expressions (values known at
+ *     compile time);
+ *   - abs, min and max to apply to non-constant expressions (values unknown at
+ *     compile time), abs is found in stdlib.h.
+ *
+ * @{ */
+
+/** \brief Takes the absolute value of \a a.
+ *
+ * \param[in] a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a)              (((a) <  0 ) ? -(a) : (a))
+
+#ifndef __cplusplus
+/** \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b)           (((a) < (b)) ?  (a) : (b))
+
+/** \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b)           (((a) > (b)) ?  (a) : (b))
+
+/** \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define min(a, b)   Min(a, b)
+
+/** \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define max(a, b)   Max(a, b)
+#endif
+
+/** @} */
+
+
+/** \brief Calls the routine at address \a addr.
+ *
+ * It generates a long call opcode.
+ *
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
+ * it is invoked from the CPU supervisor mode.
+ *
+ * \param[in] addr  Address of the routine to call.
+ *
+ * \note It may be used as a long jump opcode in some special cases.
+ */
+#define Long_call(addr)                   ((*(void (*)(void))(addr))())
+
+
+/** \name MCU Endianism Handling
+ *  ARM is MCU little endian.
+ *
+ * @{ */
+#define  BE16(x)        swap16(x)
+#define  LE16(x)        (x)
+
+#define  le16_to_cpu(x) (x)
+#define  cpu_to_le16(x) (x)
+#define  LE16_TO_CPU(x) (x)
+#define  CPU_TO_LE16(x) (x)
+
+#define  be16_to_cpu(x) swap16(x)
+#define  cpu_to_be16(x) swap16(x)
+#define  BE16_TO_CPU(x) swap16(x)
+#define  CPU_TO_BE16(x) swap16(x)
+
+#define  le32_to_cpu(x) (x)
+#define  cpu_to_le32(x) (x)
+#define  LE32_TO_CPU(x) (x)
+#define  CPU_TO_LE32(x) (x)
+
+#define  be32_to_cpu(x) swap32(x)
+#define  cpu_to_be32(x) swap32(x)
+#define  BE32_TO_CPU(x) swap32(x)
+#define  CPU_TO_BE32(x) swap32(x)
+/** @} */
+
+
+/** \name Endianism Conversion
+ *
+ * The same considerations as for clz and ctz apply here but GCC's
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
+ * applied to constant expressions, so two sets of macros are defined here:
+ *   - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
+ *     at compile time);
+ *   - swap16, swap32 and swap64 to apply to non-constant expressions (values
+ *     unknown at compile time).
+ *
+ * @{ */
+
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param[in] u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) |\
+                           ((uint16_t)(u16) << 8)))
+
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param[in] u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) |\
+                           ((uint32_t)Swap16((uint32_t)(u32)) << 16)))
+
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param[in] u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) |\
+                           ((uint64_t)Swap32((uint64_t)(u64)) << 32)))
+
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param[in] u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define swap16(u16) Swap16(u16)
+
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param[in] u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+#  define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32)))
+#else
+#  define swap32(u32) Swap32(u32)
+#endif
+
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param[in] u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+#  define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64)))
+#else
+#  define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) |\
+                         ((uint64_t)swap32((uint64_t)(u64)) << 32)))
+#endif
+
+/** @} */
+
+
+/** \name Target Abstraction
+ *
+ * @{ */
+
+#define _GLOBEXT_           extern      /**< extern storage-class specifier. */
+#define _CONST_TYPE_        const       /**< const type qualifier. */
+#define _MEM_TYPE_SLOW_                 /**< Slow memory type. */
+#define _MEM_TYPE_MEDFAST_              /**< Fairly fast memory type. */
+#define _MEM_TYPE_FAST_                 /**< Fast memory type. */
+
+#define memcmp_ram2ram      memcmp      /**< Target-specific memcmp of RAM to RAM. */
+#define memcmp_code2ram     memcmp      /**< Target-specific memcmp of RAM to NVRAM. */
+#define memcpy_ram2ram      memcpy      /**< Target-specific memcpy from RAM to RAM. */
+#define memcpy_code2ram     memcpy      /**< Target-specific memcpy from NVRAM to RAM. */
+
+/** @} */
+
+/**
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
+ * integer arithmetic.
+ *
+ * \param[in] a An integer
+ * \param[in] b Another integer
+ *
+ * \return (\a a / \a b) rounded up to the nearest integer.
+ */
+#define div_ceil(a, b)      (((a) + (b) - 1) / (b))
+
+#endif  /* #ifndef __ASSEMBLY__ */
+#ifdef __ICCARM__
+/** \name Compiler Keywords
+ *
+ * Port of some keywords from GCC to IAR Embedded Workbench.
+ *
+ * @{ */
+
+#define __asm__             asm
+#define __inline__          inline
+#define __volatile__
+
+/** @} */
+
+#endif
+
+#define FUNC_PTR                            void *
+/**
+ * \def unused
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define unused(v)          do { (void)(v); } while(0)
+
+/* Define RAMFUNC attribute */
+#if defined   ( __CC_ARM   ) /* Keil uVision 4 */
+#   define RAMFUNC __attribute__ ((section(".ramfunc")))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+#   define RAMFUNC __ramfunc
+#elif defined (  __GNUC__  ) /* GCC CS3 2009q3-68 */
+#   define RAMFUNC __attribute__ ((section(".ramfunc")))
+#endif
+
+/* Define OPTIMIZE_HIGH attribute */
+#if defined   ( __CC_ARM   ) /* Keil uVision 4 */
+#   define OPTIMIZE_HIGH _Pragma("O3")
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+#   define OPTIMIZE_HIGH _Pragma("optimize=high")
+#elif defined (  __GNUC__  ) /* GCC CS3 2009q3-68 */
+#   define OPTIMIZE_HIGH __attribute__((optimize("s")))
+#endif
+#define PASS      0
+#define FAIL      1
+#define LOW       0
+#define HIGH      1
+
+typedef int8_t                  S8 ;  //!< 8-bit signed integer.
+typedef uint8_t                 U8 ;  //!< 8-bit unsigned integer.
+typedef int16_t                 S16;  //!< 16-bit signed integer.
+typedef uint16_t                U16;  //!< 16-bit unsigned integer.
+typedef int32_t                 S32;  //!< 32-bit signed integer.
+typedef uint32_t                U32;  //!< 32-bit unsigned integer.
+typedef int64_t                 S64;  //!< 64-bit signed integer.
+typedef uint64_t                U64;  //!< 64-bit unsigned integer.
+typedef float                   F32;  //!< 32-bit floating-point number.
+typedef double                  F64;  //!< 64-bit floating-point number.
+
+#define  MSB(u16)       (((U8  *)&(u16))[1]) //!< Most significant byte of \a u16.
+#define  LSB(u16)       (((U8  *)&(u16))[0]) //!< Least significant byte of \a u16.
+
+#define  MSH(u32)       (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
+#define  LSH(u32)       (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
+#define  MSB0W(u32)     (((U8  *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
+#define  MSB1W(u32)     (((U8  *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
+#define  MSB2W(u32)     (((U8  *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
+#define  MSB3W(u32)     (((U8  *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
+#define  LSB3W(u32)     MSB0W(u32)           //!< Least significant byte of 4th rank of \a u32.
+#define  LSB2W(u32)     MSB1W(u32)           //!< Least significant byte of 3rd rank of \a u32.
+#define  LSB1W(u32)     MSB2W(u32)           //!< Least significant byte of 2nd rank of \a u32.
+#define  LSB0W(u32)     MSB3W(u32)           //!< Least significant byte of 1st rank of \a u32.
+
+#define  MSW(u64)       (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
+#define  LSW(u64)       (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
+#define  MSH0(u64)      (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
+#define  MSH1(u64)      (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
+#define  MSH2(u64)      (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
+#define  MSH3(u64)      (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
+#define  LSH3(u64)      MSH0(u64)            //!< Least significant half-word of 4th rank of \a u64.
+#define  LSH2(u64)      MSH1(u64)            //!< Least significant half-word of 3rd rank of \a u64.
+#define  LSH1(u64)      MSH2(u64)            //!< Least significant half-word of 2nd rank of \a u64.
+#define  LSH0(u64)      MSH3(u64)            //!< Least significant half-word of 1st rank of \a u64.
+#define  MSB0D(u64)     (((U8  *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
+#define  MSB1D(u64)     (((U8  *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
+#define  MSB2D(u64)     (((U8  *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
+#define  MSB3D(u64)     (((U8  *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
+#define  MSB4D(u64)     (((U8  *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
+#define  MSB5D(u64)     (((U8  *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
+#define  MSB6D(u64)     (((U8  *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
+#define  MSB7D(u64)     (((U8  *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
+#define  LSB7D(u64)     MSB0D(u64)           //!< Least significant byte of 8th rank of \a u64.
+#define  LSB6D(u64)     MSB1D(u64)           //!< Least significant byte of 7th rank of \a u64.
+#define  LSB5D(u64)     MSB2D(u64)           //!< Least significant byte of 6th rank of \a u64.
+#define  LSB4D(u64)     MSB3D(u64)           //!< Least significant byte of 5th rank of \a u64.
+#define  LSB3D(u64)     MSB4D(u64)           //!< Least significant byte of 4th rank of \a u64.
+#define  LSB2D(u64)     MSB5D(u64)           //!< Least significant byte of 3rd rank of \a u64.
+#define  LSB1D(u64)     MSB6D(u64)           //!< Least significant byte of 2nd rank of \a u64.
+#define  LSB0D(u64)     MSB7D(u64)           //!< Least significant byte of 1st rank of \a u64.
+
+#define LSB0(u32)           LSB0W(u32)  //!< Least significant byte of 1st rank of \a u32.
+#define LSB1(u32)           LSB1W(u32)  //!< Least significant byte of 2nd rank of \a u32.
+#define LSB2(u32)           LSB2W(u32)  //!< Least significant byte of 3rd rank of \a u32.
+#define LSB3(u32)           LSB3W(u32)  //!< Least significant byte of 4th rank of \a u32.
+#define MSB3(u32)           MSB3W(u32)  //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32)           MSB2W(u32)  //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32)           MSB1W(u32)  //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32)           MSB0W(u32)  //!< Most significant byte of 1st rank of \a u32.
+
+#if defined(__ICCARM__)
+#define SHORTENUM           __packed
+#elif defined(__GNUC__)
+#define SHORTENUM           __attribute__((packed))
+#endif
+
+/* No operation */
+#if defined(__ICCARM__)
+#define nop()               __no_operation()
+#elif defined(__GNUC__)
+#define nop()               (__NOP())
+#endif
+
+#define FLASH_DECLARE(x)  const x
+#define FLASH_EXTERN(x) extern const x
+#define PGM_READ_BYTE(x) *(x)
+#define PGM_READ_WORD(x) *(x)
+#define MEMCPY_ENDIAN memcpy
+#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
+
+/*Defines the Flash Storage for the request and response of MAC*/
+#define CMD_ID_OCTET    (0)
+
+/* Converting of values from CPU endian to little endian. */
+#define CPU_ENDIAN_TO_LE16(x)   (x)
+#define CPU_ENDIAN_TO_LE32(x)   (x)
+#define CPU_ENDIAN_TO_LE64(x)   (x)
+
+/* Converting of values from little endian to CPU endian. */
+#define LE16_TO_CPU_ENDIAN(x)   (x)
+#define LE32_TO_CPU_ENDIAN(x)   (x)
+#define LE64_TO_CPU_ENDIAN(x)   (x)
+
+/* Converting of constants from little endian to CPU endian. */
+#define CLE16_TO_CPU_ENDIAN(x)  (x)
+#define CLE32_TO_CPU_ENDIAN(x)  (x)
+#define CLE64_TO_CPU_ENDIAN(x)  (x)
+
+/* Converting of constants from CPU endian to little endian. */
+#define CCPU_ENDIAN_TO_LE16(x)  (x)
+#define CCPU_ENDIAN_TO_LE32(x)  (x)
+#define CCPU_ENDIAN_TO_LE64(x)  (x)
+
+#define ADDR_COPY_DST_SRC_16(dst, src)  ((dst) = (src))
+#define ADDR_COPY_DST_SRC_64(dst, src)  ((dst) = (src))
+
+/**
+ * @brief Converts a 64-Bit value into  a 8 Byte array
+ *
+ * @param[in] value 64-Bit value
+ * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
+{
+    uint8_t index = 0;
+
+    while (index < 8)
+    {
+        data[index++] = value & 0xFF;
+        value = value >> 8;
+    }
+}
+
+/**
+ * @brief Converts a 16-Bit value into  a 2 Byte array
+ *
+ * @param[in] value 16-Bit value
+ * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+    data[0] = value & 0xFF;
+    data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+    data[0] = value & 0xFF;
+    data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)
+{
+    data[0] = value & 0xFF;
+    data[1] = (value >> 8) & 0xFF;
+}
+
+/*
+ * @brief Converts a 2 Byte array into a 16-Bit value
+ *
+ * @param data Specifies the pointer to the 2 Byte array
+ *
+ * @return 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
+{
+    return (data[0] | ((uint16_t)data[1] << 8));
+}
+
+/* Converts a 4 Byte array into a 32-Bit value */
+static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
+{
+	union
+	{
+		uint32_t u32;
+		uint8_t u8[4];
+	}long_addr;
+	uint8_t index;
+	for (index = 0; index < 4; index++)
+	{
+		long_addr.u8[index] = *data++;
+	}
+	return long_addr.u32;
+}
+
+/**
+ * @brief Converts a 8 Byte array into a 64-Bit value
+ *
+ * @param data Specifies the pointer to the 8 Byte array
+ *
+ * @return 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
+{
+    union
+    {
+        uint64_t u64;
+        uint8_t u8[8];
+    } long_addr;
+
+    uint8_t index;
+
+    for (index = 0; index < 8; index++)
+    {
+        long_addr.u8[index] = *data++;
+    }
+
+    return long_addr.u64;
+}
+
+/** @} */
+
+#endif /* UTILS_COMPILER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/header_files/io.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/header_files/io.h
new file mode 100644
index 0000000000..2baefbaf51
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/header_files/io.h
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief Arch file for SAM0.
+ *
+ * This file defines common SAM0 series.
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAM_IO_
+#define _SAM_IO_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/* SAM D20 family */
+#if (SAMD20)
+#  include "samd20.h"
+#endif
+
+#if (SAMD21)
+#  include "samd21.h"
+#endif
+
+#if (SAMR21)
+#  include "samr21.h"
+#endif
+
+#if (SAMD09)
+#  include "samd09.h"
+#endif
+
+#if (SAMD10)
+#  include "samd10.h"
+#endif
+
+#if (SAMD11)
+#  include "samd11.h"
+#endif
+
+#if (SAML21)
+#  include "saml21.h"
+#endif
+
+#if (SAMR30)
+#  include "samr30.h"
+#endif
+
+#if (SAML22)
+#  include "saml22.h"
+#endif
+
+#if (SAMDA1)
+#  include "samda1.h"
+#endif
+
+#if (SAMC20)
+#  include "samc20.h"
+#endif
+
+#if (SAMC21)
+#  include "samc21.h"
+#endif
+
+#if (SAMHA1)
+#  include "samha1.h"
+#endif
+
+#if (SAMB11)
+#  include "samb11.h"
+#endif
+
+#endif /* _SAM_IO_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e14_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e14_flash.ld
new file mode 100644
index 0000000000..50c1305bc2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e14_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00004000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00000800
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x200;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e14_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e14_sram.ld
new file mode 100644
index 0000000000..0f604df547
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e14_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00000800
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x200;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e15_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e15_flash.ld
new file mode 100644
index 0000000000..7eb5518ae4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e15_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e15_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e15_sram.ld
new file mode 100644
index 0000000000..9b291dd0d2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e15_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e16_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e16_flash.ld
new file mode 100644
index 0000000000..c54c1708e1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e16_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e16_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e16_sram.ld
new file mode 100644
index 0000000000..bff1f2d135
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e16_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e17_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e17_flash.ld
new file mode 100644
index 0000000000..71ec13b719
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e17_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e17_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e17_sram.ld
new file mode 100644
index 0000000000..02e55e35c7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e17_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e18_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e18_flash.ld
new file mode 100644
index 0000000000..50765c3073
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e18_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e18_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e18_sram.ld
new file mode 100644
index 0000000000..a7f97e99b3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20e18_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g14_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g14_flash.ld
new file mode 100644
index 0000000000..df5187410f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g14_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00004000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00000800
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x200;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g14_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g14_sram.ld
new file mode 100644
index 0000000000..5bd7f4269c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g14_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00000800
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x200;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g15_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g15_flash.ld
new file mode 100644
index 0000000000..ed484ce2dc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g15_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g15_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g15_sram.ld
new file mode 100644
index 0000000000..16d6c29172
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g15_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g16_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g16_flash.ld
new file mode 100644
index 0000000000..de943b3c81
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g16_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g16_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g16_sram.ld
new file mode 100644
index 0000000000..9e73da9aa5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g16_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17_flash.ld
new file mode 100644
index 0000000000..18f98dd0b8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17_sram.ld
new file mode 100644
index 0000000000..53f0160b63
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17u_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17u_flash.ld
new file mode 100644
index 0000000000..cefbbe4b1e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17u_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G17U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17u_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17u_sram.ld
new file mode 100644
index 0000000000..f3acec58ce
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g17u_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G17U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18_flash.ld
new file mode 100644
index 0000000000..a4e5ee6af9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18_sram.ld
new file mode 100644
index 0000000000..10ac623225
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18u_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18u_flash.ld
new file mode 100644
index 0000000000..562c5f862c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18u_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G18U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18u_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18u_sram.ld
new file mode 100644
index 0000000000..f179062022
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20g18u_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G18U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j14_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j14_flash.ld
new file mode 100644
index 0000000000..f6ace0f773
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j14_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00004000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00000800
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x200;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j14_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j14_sram.ld
new file mode 100644
index 0000000000..80049de10f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j14_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00000800
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x200;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j15_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j15_flash.ld
new file mode 100644
index 0000000000..56e91b2565
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j15_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j15_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j15_sram.ld
new file mode 100644
index 0000000000..04c73139b8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j15_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j16_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j16_flash.ld
new file mode 100644
index 0000000000..daff4b0541
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j16_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j16_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j16_sram.ld
new file mode 100644
index 0000000000..333821a467
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j16_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j17_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j17_flash.ld
new file mode 100644
index 0000000000..42e2c107fd
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j17_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j17_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j17_sram.ld
new file mode 100644
index 0000000000..8d3add76b1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j17_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j18_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j18_flash.ld
new file mode 100644
index 0000000000..6a96f0afa7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j18_flash.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom    (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j18_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j18_sram.ld
new file mode 100644
index 0000000000..cabc8d6f2f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/gcc/samd20j18_sram.ld
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e14_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e14_flash.icf
new file mode 100644
index 0000000000..97192a5871
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e14_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x200007FF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x200;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e14_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e14_sram.icf
new file mode 100644
index 0000000000..adb37a5675
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e14_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x200007FF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x200;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e15_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e15_flash.icf
new file mode 100644
index 0000000000..857353ab94
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e15_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e15_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e15_sram.icf
new file mode 100644
index 0000000000..1713b35081
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e15_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e16_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e16_flash.icf
new file mode 100644
index 0000000000..377e59eaf3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e16_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e16_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e16_sram.icf
new file mode 100644
index 0000000000..8506ca936b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e16_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e17_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e17_flash.icf
new file mode 100644
index 0000000000..004ae5694c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e17_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e17_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e17_sram.icf
new file mode 100644
index 0000000000..b9ab80046f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e17_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf
new file mode 100644
index 0000000000..b7499054a9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf
new file mode 100644
index 0000000000..ebe618f943
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g14_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g14_flash.icf
new file mode 100644
index 0000000000..72fe72f165
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g14_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x200007FF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x200;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g14_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g14_sram.icf
new file mode 100644
index 0000000000..7254a2984f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g14_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x200007FF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x200;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g15_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g15_flash.icf
new file mode 100644
index 0000000000..2f6d0f57db
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g15_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g15_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g15_sram.icf
new file mode 100644
index 0000000000..2948c98f7c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g15_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g16_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g16_flash.icf
new file mode 100644
index 0000000000..605d5ee462
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g16_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g16_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g16_sram.icf
new file mode 100644
index 0000000000..3f729da6da
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g16_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17_flash.icf
new file mode 100644
index 0000000000..49af2975d2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17_sram.icf
new file mode 100644
index 0000000000..dfa515039d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf
new file mode 100644
index 0000000000..bbbfad223e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G17U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf
new file mode 100644
index 0000000000..7118d0745b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G17U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18_flash.icf
new file mode 100644
index 0000000000..afcc80e147
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18_sram.icf
new file mode 100644
index 0000000000..f75229896d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf
new file mode 100644
index 0000000000..fdde4065aa
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G18U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf
new file mode 100644
index 0000000000..9b9d2a518b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G18U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j14_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j14_flash.icf
new file mode 100644
index 0000000000..682380d861
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j14_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x200007FF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x200;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j14_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j14_sram.icf
new file mode 100644
index 0000000000..b5ed4f9b95
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j14_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J14
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x200007FF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x200;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j15_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j15_flash.icf
new file mode 100644
index 0000000000..354aea29af
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j15_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j15_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j15_sram.icf
new file mode 100644
index 0000000000..a71b4de6f3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j15_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J15
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j16_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j16_flash.icf
new file mode 100644
index 0000000000..9dc724868a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j16_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j16_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j16_sram.icf
new file mode 100644
index 0000000000..c1cca6b744
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j16_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J16
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j17_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j17_flash.icf
new file mode 100644
index 0000000000..517c4610dc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j17_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j17_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j17_sram.icf
new file mode 100644
index 0000000000..70389a5996
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j17_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J17
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j18_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j18_flash.icf
new file mode 100644
index 0000000000..3f601ac34f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j18_flash.icf
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20J18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j18_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j18_sram.icf
new file mode 100644
index 0000000000..8741b3ddf7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20j18_sram.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20J18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15a_flash.ld
new file mode 100644
index 0000000000..07d717c7af
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15a_sram.ld
new file mode 100644
index 0000000000..2e5d71664c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15b_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15b_flash.ld
new file mode 100644
index 0000000000..506972cb88
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15b_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15b_sram.ld
new file mode 100644
index 0000000000..c30d8ab2fc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15bu_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15bu_flash.ld
new file mode 100644
index 0000000000..0684c0d191
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15bu_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15bu_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15bu_sram.ld
new file mode 100644
index 0000000000..4d2305d3a4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15bu_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15l_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15l_flash.ld
new file mode 100644
index 0000000000..c77321fb18
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15l_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15l_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15l_sram.ld
new file mode 100644
index 0000000000..fa3b178c5d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e15l_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16a_flash.ld
new file mode 100644
index 0000000000..5d67169d5e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16a_sram.ld
new file mode 100644
index 0000000000..f2a17cac31
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16b_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16b_flash.ld
new file mode 100644
index 0000000000..f235ce0c67
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16b_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16b_sram.ld
new file mode 100644
index 0000000000..4d382d6a0a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16bu_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16bu_flash.ld
new file mode 100644
index 0000000000..20cad4f362
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16bu_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16bu_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16bu_sram.ld
new file mode 100644
index 0000000000..f129d2ea71
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16bu_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16l_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16l_flash.ld
new file mode 100644
index 0000000000..405d36ae0b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16l_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16l_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16l_sram.ld
new file mode 100644
index 0000000000..2a162d58d1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e16l_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e17a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e17a_flash.ld
new file mode 100644
index 0000000000..68013eaf6a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e17a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e17a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e17a_sram.ld
new file mode 100644
index 0000000000..60be1d2eb4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e17a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e18a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e18a_flash.ld
new file mode 100644
index 0000000000..8aba435e81
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e18a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e18a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e18a_sram.ld
new file mode 100644
index 0000000000..44d8c4b808
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21e18a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15a_flash.ld
new file mode 100644
index 0000000000..8b84491d5f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15a_sram.ld
new file mode 100644
index 0000000000..f19477df4e
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15b_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15b_flash.ld
new file mode 100644
index 0000000000..6d676186f3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15b_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15b_sram.ld
new file mode 100644
index 0000000000..02feaa25c9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15l_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15l_flash.ld
new file mode 100644
index 0000000000..b90239f0d7
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15l_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15l_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15l_sram.ld
new file mode 100644
index 0000000000..76f23bb6e4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g15l_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16a_flash.ld
new file mode 100644
index 0000000000..19a336d0d4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16a_sram.ld
new file mode 100644
index 0000000000..ae01f3b68f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16b_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16b_flash.ld
new file mode 100644
index 0000000000..36afda3182
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16b_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16b_sram.ld
new file mode 100644
index 0000000000..2f34e8dcca
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16l_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16l_flash.ld
new file mode 100644
index 0000000000..e03ed73876
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16l_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16l_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16l_sram.ld
new file mode 100644
index 0000000000..f62ff606dc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g16l_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17a_flash.ld
new file mode 100644
index 0000000000..7fe329142d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17a_sram.ld
new file mode 100644
index 0000000000..484799a4f0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17au_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17au_flash.ld
new file mode 100644
index 0000000000..446635f7e5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17au_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17au_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17au_sram.ld
new file mode 100644
index 0000000000..19be3614d5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g17au_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18a_flash.ld
new file mode 100644
index 0000000000..53466dd1cd
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18a_sram.ld
new file mode 100644
index 0000000000..f447b91907
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18au_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18au_flash.ld
new file mode 100644
index 0000000000..ad5966bd09
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18au_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18au_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18au_sram.ld
new file mode 100644
index 0000000000..03959a01e0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21g18au_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15a_flash.ld
new file mode 100644
index 0000000000..a8e30588ce
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15a_sram.ld
new file mode 100644
index 0000000000..84e78e9d86
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15b_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15b_flash.ld
new file mode 100644
index 0000000000..34688c65f2
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15b_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15b_sram.ld
new file mode 100644
index 0000000000..3457997b38
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j15b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16a_flash.ld
new file mode 100644
index 0000000000..0104b5debb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16a_sram.ld
new file mode 100644
index 0000000000..f49738d69d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16b_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16b_flash.ld
new file mode 100644
index 0000000000..dbb6b2be78
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16b_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16b_sram.ld
new file mode 100644
index 0000000000..337a3116a6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j16b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j17a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j17a_flash.ld
new file mode 100644
index 0000000000..924d444494
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j17a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j17a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j17a_sram.ld
new file mode 100644
index 0000000000..060e733584
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j17a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
new file mode 100644
index 0000000000..5be24c93bc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_sram.ld b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_sram.ld
new file mode 100644
index 0000000000..044ceefebb
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15a_flash.icf
new file mode 100644
index 0000000000..f7e0d2197a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15a_sram.icf
new file mode 100644
index 0000000000..9957dfd473
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf
new file mode 100644
index 0000000000..c0f9fa5ce9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf
new file mode 100644
index 0000000000..a4cd4d1777
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf
new file mode 100644
index 0000000000..1df26bf7e1
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf
new file mode 100644
index 0000000000..998c94a680
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf
new file mode 100644
index 0000000000..8c7d6cdc1c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf
new file mode 100644
index 0000000000..7bf9184da8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16a_flash.icf
new file mode 100644
index 0000000000..76802c2c41
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16a_sram.icf
new file mode 100644
index 0000000000..6ed1bd8a17
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf
new file mode 100644
index 0000000000..bb14fd7ef0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf
new file mode 100644
index 0000000000..f608892d1b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf
new file mode 100644
index 0000000000..a0dfd30410
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf
new file mode 100644
index 0000000000..1d49c0ed4c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf
new file mode 100644
index 0000000000..343b46fb3b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf
new file mode 100644
index 0000000000..cc2524f0c3
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e17a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e17a_flash.icf
new file mode 100644
index 0000000000..7cdf2d5996
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e17a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e17a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e17a_sram.icf
new file mode 100644
index 0000000000..31995c7b38
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e17a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf
new file mode 100644
index 0000000000..e0cd4f40ed
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf
new file mode 100644
index 0000000000..a46e7c87d0
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf
new file mode 100644
index 0000000000..4bba7c0c7a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf
new file mode 100644
index 0000000000..2b42ca0d8f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf
new file mode 100644
index 0000000000..c2ef3389e9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf
new file mode 100644
index 0000000000..b8dbdaae9b
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf
new file mode 100644
index 0000000000..161d96c214
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf
new file mode 100644
index 0000000000..fe382e12b6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16a_flash.icf
new file mode 100644
index 0000000000..6a5417398c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16a_sram.icf
new file mode 100644
index 0000000000..e7199d63aa
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf
new file mode 100644
index 0000000000..c5de64da26
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf
new file mode 100644
index 0000000000..22bb2eaa10
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf
new file mode 100644
index 0000000000..a6807c1227
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf
new file mode 100644
index 0000000000..e8b76d4dd5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17a_flash.icf
new file mode 100644
index 0000000000..9394624ce5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17a_sram.icf
new file mode 100644
index 0000000000..e747ba5bc5
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf
new file mode 100644
index 0000000000..300b38d563
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf
new file mode 100644
index 0000000000..c48c77daf9
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18a_flash.icf
new file mode 100644
index 0000000000..27f8fbe4de
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18a_sram.icf
new file mode 100644
index 0000000000..e0fe47a307
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf
new file mode 100644
index 0000000000..403160016c
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf
new file mode 100644
index 0000000000..34bfdb06e4
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf
new file mode 100644
index 0000000000..63eaab0f55
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf
new file mode 100644
index 0000000000..778ea6dcef
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf
new file mode 100644
index 0000000000..82d992b66a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf
new file mode 100644
index 0000000000..49cf464df6
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16a_flash.icf
new file mode 100644
index 0000000000..a03e1b2035
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16a_sram.icf
new file mode 100644
index 0000000000..2ff99fbe93
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J16A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf
new file mode 100644
index 0000000000..d7f04148e8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf
new file mode 100644
index 0000000000..05dfb6888a
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j17a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j17a_flash.icf
new file mode 100644
index 0000000000..a7920d87d8
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j17a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j17a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j17a_sram.icf
new file mode 100644
index 0000000000..77f4c9b775
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j17a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J17A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j18a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j18a_flash.icf
new file mode 100644
index 0000000000..9327241600
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j18a_flash.icf
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j18a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j18a_sram.icf
new file mode 100644
index 0000000000..880f68d1cf
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j18a_sram.icf
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/make/Makefile.sam.in b/bsp/samd21/sam_d2x_asflib/sam0/utils/make/Makefile.sam.in
new file mode 100644
index 0000000000..d07e471899
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/make/Makefile.sam.in
@@ -0,0 +1,502 @@
+# List of available make goals:
+#
+# all                     Default target, builds the project
+# clean                   Clean up the project
+# rebuild                 Rebuild the project
+# debug_flash             Builds the project and debug in flash
+# debug_sram              Builds the project and debug in sram
+#
+# doc                     Build the documentation
+# cleandoc                Clean up the documentation
+# rebuilddoc              Rebuild the documentation
+#
+# \file
+#
+# Copyright (c) 2011 - 2014 Atmel Corporation. All rights reserved.
+#
+# \asf_license_start
+#
+# \page License
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+#    this list of conditions and the following disclaimer in the documentation
+#    and/or other materials provided with the distribution.
+#
+# 3. The name of Atmel may not be used to endorse or promote products derived
+#    from this software without specific prior written permission.
+#
+# 4. This software may only be redistributed and used in connection with an
+#    Atmel microcontroller product.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+# \asf_license_stop
+#
+
+# Include the config.mk file from the current working path, e.g., where the
+# user called make.
+include config.mk
+
+# Tool to use to generate documentation from the source code
+DOCGEN          ?= doxygen
+
+# Look for source files relative to the top-level source directory
+VPATH           := $(PRJ_PATH)
+
+# Output target file
+project_type    := $(PROJECT_TYPE)
+
+# Output target file
+ifeq ($(project_type),flash)
+target          := $(TARGET_FLASH)
+linker_script   := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)
+debug_script    := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)
+else
+target          := $(TARGET_SRAM)
+linker_script   := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)
+debug_script    := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)
+endif
+
+# Output project name (target name minus suffix)
+project         := $(basename $(target))
+
+# Output target file (typically ELF or static library)
+ifeq ($(suffix $(target)),.a)
+target_type     := lib
+else
+ifeq ($(suffix $(target)),.elf)
+target_type     := elf
+else
+$(error "Target type $(target_type) is not supported")
+endif
+endif
+
+# Allow override of operating system detection. The user can add OS=Linux or
+# OS=Windows on the command line to explicit set the host OS.
+#
+# This allows to work around broken uname utility on certain systems.
+ifdef OS
+  ifeq ($(strip $(OS)), Linux)
+    os_type     := Linux
+  endif
+  ifeq ($(strip $(OS)), Windows)
+    os_type     := windows32_64
+  endif
+endif
+
+os_type         ?= $(strip $(shell uname))
+
+ifeq ($(os_type),windows32)
+os              := Windows
+else
+ifeq ($(os_type),windows64)
+os              := Windows
+else
+ifeq ($(os_type),windows32_64)
+os              ?= Windows
+else
+ifeq ($(os_type),)
+os              := Windows
+else
+# Default to Linux style operating system. Both Cygwin and mingw are fully
+# compatible (for this Makefile) with Linux.
+os              := Linux
+endif
+endif
+endif
+endif
+
+# Output documentation directory and configuration file.
+docdir          := ../doxygen/html
+doccfg          := ../doxygen/doxyfile.doxygen
+
+CROSS           ?= arm-none-eabi-
+AR              := $(CROSS)ar
+AS              := $(CROSS)as
+CC              := $(CROSS)gcc
+CPP             := $(CROSS)gcc -E
+CXX             := $(CROSS)g++
+LD              := $(CROSS)g++
+NM              := $(CROSS)nm
+OBJCOPY         := $(CROSS)objcopy
+OBJDUMP         := $(CROSS)objdump
+SIZE            := $(CROSS)size
+GDB             := $(CROSS)gdb
+
+RM              := rm
+ifeq ($(os),Windows)
+RMDIR           := rmdir /S /Q
+else
+RMDIR           := rmdir -p --ignore-fail-on-non-empty
+endif
+
+# On Windows, we need to override the shell to force the use of cmd.exe
+ifeq ($(os),Windows)
+SHELL           := cmd
+endif
+
+# Strings for beautifying output
+MSG_CLEAN_FILES         = "RM      *.o *.d"
+MSG_CLEAN_DIRS          = "RMDIR   $(strip $(clean-dirs))"
+MSG_CLEAN_DOC           = "RMDIR   $(docdir)"
+MSG_MKDIR               = "MKDIR   $(dir $@)"
+
+MSG_INFO                = "INFO    "
+MSG_PREBUILD            = "PREBUILD  $(PREBUILD_CMD)"
+MSG_POSTBUILD           = "POSTBUILD $(POSTBUILD_CMD)"
+
+MSG_ARCHIVING           = "AR      $@"
+MSG_ASSEMBLING          = "AS      $@"
+MSG_BINARY_IMAGE        = "OBJCOPY $@"
+MSG_COMPILING           = "CC      $@"
+MSG_COMPILING_CXX       = "CXX     $@"
+MSG_EXTENDED_LISTING    = "OBJDUMP $@"
+MSG_IHEX_IMAGE          = "OBJCOPY $@"
+MSG_LINKING             = "LN      $@"
+MSG_PREPROCESSING       = "CPP     $@"
+MSG_SIZE                = "SIZE    $@"
+MSG_SYMBOL_TABLE        = "NM      $@"
+
+MSG_GENERATING_DOC      = "DOXYGEN $(docdir)"
+
+# Don't use make's built-in rules and variables
+MAKEFLAGS       += -rR
+
+# Don't print 'Entering directory ...'
+MAKEFLAGS       += --no-print-directory
+
+# Function for reversing the order of a list
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))
+
+# Hide command output by default, but allow the user to override this
+# by adding V=1 on the command line.
+#
+# This is inspired by the Kbuild system used by the Linux kernel.
+ifdef V
+  ifeq ("$(origin V)", "command line")
+    VERBOSE = $(V)
+  endif
+endif
+ifndef VERBOSE
+  VERBOSE = 0
+endif
+
+ifeq ($(VERBOSE), 1)
+  Q =
+else
+  Q = @
+endif
+
+arflags-gnu-y           := $(ARFLAGS)
+asflags-gnu-y           := $(ASFLAGS)
+cflags-gnu-y            := $(CFLAGS)
+cxxflags-gnu-y          := $(CXXFLAGS)
+cppflags-gnu-y          := $(CPPFLAGS)
+cpuflags-gnu-y          :=
+dbgflags-gnu-y          := $(DBGFLAGS)
+libflags-gnu-y          := $(foreach LIB,$(LIBS),-l$(LIB))
+ldflags-gnu-y           := $(LDFLAGS)
+flashflags-gnu-y        :=
+clean-files             :=
+clean-dirs              :=
+
+clean-files             += $(wildcard $(target) $(project).map)
+clean-files             += $(wildcard $(project).hex $(project).bin)
+clean-files             += $(wildcard $(project).lss $(project).sym)
+clean-files             += $(wildcard $(build))
+
+# Use pipes instead of temporary files for communication between processes
+cflags-gnu-y    += -pipe
+asflags-gnu-y   += -pipe
+ldflags-gnu-y   += -pipe
+
+# Archiver flags.
+arflags-gnu-y   += rcs
+
+# Always enable warnings. And be very careful about implicit
+# declarations.
+cflags-gnu-y    += -Wall -Wstrict-prototypes -Wmissing-prototypes
+cflags-gnu-y    += -Werror-implicit-function-declaration
+cxxflags-gnu-y  += -Wall
+# IAR doesn't allow arithmetic on void pointers, so warn about that.
+cflags-gnu-y    += -Wpointer-arith
+cxxflags-gnu-y  += -Wpointer-arith
+
+# Preprocessor flags.
+cppflags-gnu-y  += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))
+asflags-gnu-y   += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')
+
+# CPU specific flags.
+cpuflags-gnu-y  += -mcpu=$(ARCH) -mthumb -D=__$(PART)__
+
+# Dependency file flags.
+depflags        = -MD -MP -MQ $@
+
+# Debug specific flags.
+ifdef BUILD_DEBUG_LEVEL
+dbgflags-gnu-y  += -g$(BUILD_DEBUG_LEVEL)
+else
+dbgflags-gnu-y  += -g3
+endif
+
+# Optimization specific flags.
+ifdef BUILD_OPTIMIZATION
+optflags-gnu-y  = -O$(BUILD_OPTIMIZATION)
+else
+optflags-gnu-y  = $(OPTIMIZATION)
+endif
+
+# Always preprocess assembler files.
+asflags-gnu-y   += -x assembler-with-cpp
+# Compile C files using the GNU99 standard.
+cflags-gnu-y    += -std=gnu99
+# Compile C++ files using the GNU++98 standard.
+cxxflags-gnu-y  += -std=gnu++98
+
+# Don't use strict aliasing (very common in embedded applications).
+cflags-gnu-y    += -fno-strict-aliasing
+cxxflags-gnu-y  += -fno-strict-aliasing
+
+# Separate each function and data into its own separate section to allow
+# garbage collection of unused sections.
+cflags-gnu-y    += -ffunction-sections -fdata-sections
+cxxflags-gnu-y  += -ffunction-sections -fdata-sections
+
+# Various cflags.
+cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+cflags-gnu-y += -Wmain -Wparentheses
+cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings
+cflags-gnu-y += -Wsign-compare -Waggregate-return
+cflags-gnu-y += -Wmissing-declarations
+cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long
+cflags-gnu-y += -Wunreachable-code
+cflags-gnu-y += -Wcast-align
+cflags-gnu-y += --param max-inline-insns-single=500
+
+# To reduce application size use only integer printf function.
+cflags-gnu-y += -Dprintf=iprintf
+
+# Use newlib-nano to reduce application size
+ldflags-gnu-y   += --specs=nano.specs
+
+# Garbage collect unreferred sections when linking.
+ldflags-gnu-y   += -Wl,--gc-sections
+
+# Use the linker script if provided by the project.
+ifneq ($(strip $(linker_script)),)
+ldflags-gnu-y   += -Wl,-T $(linker_script)
+endif
+
+# Output a link map file and a cross reference table
+ldflags-gnu-y   += -Wl,-Map=$(project).map,--cref
+
+# Add library search paths relative to the top level directory.
+ldflags-gnu-y   += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))
+
+a_flags  = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__
+c_flags  = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)
+l_flags  = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)
+ar_flags = $(arflags-gnu-y)
+
+# Source files list and part informations must already be included before
+# running this makefile
+
+# If a custom build directory is specified, use it -- force trailing / in directory name.
+ifdef BUILD_DIR
+	build-dir       := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)
+else
+	build-dir        =
+endif
+
+# Create object files list from source files list.
+obj-y                   := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))
+# Create dependency files list from source files list.
+dep-files               := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))
+
+clean-files             += $(wildcard $(obj-y))
+clean-files             += $(dep-files)
+
+clean-dirs              += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))
+
+# Default target.
+.PHONY: all
+ifeq ($(project_type),all)
+all:
+	$(MAKE) all PROJECT_TYPE=flash
+	$(MAKE) all PROJECT_TYPE=sram
+else
+ifeq ($(target_type),lib)
+all: $(target) $(project).lss $(project).sym
+else
+ifeq ($(target_type),elf)
+all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild
+endif
+endif
+endif
+
+prebuild:
+ifneq ($(strip $(PREBUILD_CMD)),)
+	@echo $(MSG_PREBUILD)
+	$(Q)$(PREBUILD_CMD)
+endif
+
+postbuild:
+ifneq ($(strip $(POSTBUILD_CMD)),)
+	@echo $(MSG_POSTBUILD)
+	$(Q)$(POSTBUILD_CMD)
+endif
+
+# Clean up the project.
+.PHONY: clean
+clean:
+	@$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))
+	$(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)
+	@$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))
+# Remove created directories, and make sure we only remove existing
+# directories, since recursive rmdir might help us a bit on the way.
+ifeq ($(os),Windows)
+	$(Q)$(if $(strip $(clean-dirs)),                        \
+			$(RMDIR) $(strip $(subst /,\,$(clean-dirs))))
+else
+	$(Q)$(if $(strip $(clean-dirs)),                        \
+		for directory in $(strip $(clean-dirs)); do     \
+			if [ -d "$$directory" ]; then           \
+				$(RMDIR) $$directory;           \
+			fi                                      \
+		done                                            \
+	)
+endif
+
+# Rebuild the project.
+.PHONY: rebuild
+rebuild: clean all
+
+# Debug the project in flash.
+.PHONY: debug_flash
+debug_flash: all
+	$(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)
+
+# Debug the project in sram.
+.PHONY: debug_sram
+debug_sram: all
+	$(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)
+
+.PHONY: objfiles
+objfiles: $(obj-y)
+
+# Create object files from C source files.
+$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_COMPILING)
+	$(Q)$(CC) $(c_flags) -c $< -o $@
+
+# Create object files from C++ source files.
+$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_COMPILING_CXX)
+	$(Q)$(CXX) $(cxx_flags) -c $< -o $@
+
+# Preprocess and assemble: create object files from assembler source files.
+$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_ASSEMBLING)
+	$(Q)$(CC) $(a_flags) -c $< -o $@
+
+# Include all dependency files to add depedency to all header files in use.
+include $(dep-files)
+
+ifeq ($(target_type),lib)
+# Archive object files into an archive
+$(target): $(MAKEFILE_PATH) config.mk $(obj-y)
+	@echo $(MSG_ARCHIVING)
+	$(Q)$(AR) $(ar_flags) $@ $(obj-y)
+	@echo $(MSG_SIZE)
+	$(Q)$(SIZE) -Bxt $@
+else
+ifeq ($(target_type),elf)
+# Link the object files into an ELF file. Also make sure the target is rebuilt
+# if the common Makefile.sam.in or project config.mk is changed.
+$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y)
+	@echo $(MSG_LINKING)
+	$(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@
+	@echo $(MSG_SIZE)
+	$(Q)$(SIZE) -Ax $@
+	$(Q)$(SIZE) -Bx $@
+endif
+endif
+
+# Create extended function listing from target output file.
+%.lss: $(target)
+	@echo $(MSG_EXTENDED_LISTING)
+	$(Q)$(OBJDUMP) -h -S $< > $@
+
+# Create symbol table from target output file.
+%.sym: $(target)
+	@echo $(MSG_SYMBOL_TABLE)
+	$(Q)$(NM) -n $< > $@
+
+# Create Intel HEX image from ELF output file.
+%.hex: $(target)
+	@echo $(MSG_IHEX_IMAGE)
+	$(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y)  $< $@
+
+# Create binary image from ELF output file.
+%.bin: $(target)
+	@echo $(MSG_BINARY_IMAGE)
+	$(Q)$(OBJCOPY) -O binary $< $@
+
+# Provide information about the detected host operating system.
+.SECONDARY: info-os
+info-os:
+	@echo $(MSG_INFO)$(os) build host detected
+
+# Build Doxygen generated documentation.
+.PHONY: doc
+doc:
+	@echo $(MSG_GENERATING_DOC)
+	$(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))
+
+# Clean Doxygen generated documentation.
+.PHONY: cleandoc
+cleandoc:
+	@$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))
+	$(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))
+
+# Rebuild the Doxygen generated documentation.
+.PHONY: rebuilddoc
+rebuilddoc: cleandoc doc
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrecursion.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrecursion.h
new file mode 100644
index 0000000000..84feda5a9f
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrecursion.h
@@ -0,0 +1,598 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor macro recursion utils.
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _MRECURSION_H_
+#define _MRECURSION_H_
+
+/**
+ * \defgroup group_sam0_utils_mrecursion Preprocessor - Macro Recursion
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+#define DEC_256                                   255
+#define DEC_255                                   254
+#define DEC_254                                   253
+#define DEC_253                                   252
+#define DEC_252                                   251
+#define DEC_251                                   250
+#define DEC_250                                   249
+#define DEC_249                                   248
+#define DEC_248                                   247
+#define DEC_247                                   246
+#define DEC_246                                   245
+#define DEC_245                                   244
+#define DEC_244                                   243
+#define DEC_243                                   242
+#define DEC_242                                   241
+#define DEC_241                                   240
+#define DEC_240                                   239
+#define DEC_239                                   238
+#define DEC_238                                   237
+#define DEC_237                                   236
+#define DEC_236                                   235
+#define DEC_235                                   234
+#define DEC_234                                   233
+#define DEC_233                                   232
+#define DEC_232                                   231
+#define DEC_231                                   230
+#define DEC_230                                   229
+#define DEC_229                                   228
+#define DEC_228                                   227
+#define DEC_227                                   226
+#define DEC_226                                   225
+#define DEC_225                                   224
+#define DEC_224                                   223
+#define DEC_223                                   222
+#define DEC_222                                   221
+#define DEC_221                                   220
+#define DEC_220                                   219
+#define DEC_219                                   218
+#define DEC_218                                   217
+#define DEC_217                                   216
+#define DEC_216                                   215
+#define DEC_215                                   214
+#define DEC_214                                   213
+#define DEC_213                                   212
+#define DEC_212                                   211
+#define DEC_211                                   210
+#define DEC_210                                   209
+#define DEC_209                                   208
+#define DEC_208                                   207
+#define DEC_207                                   206
+#define DEC_206                                   205
+#define DEC_205                                   204
+#define DEC_204                                   203
+#define DEC_203                                   202
+#define DEC_202                                   201
+#define DEC_201                                   200
+#define DEC_200                                   199
+#define DEC_199                                   198
+#define DEC_198                                   197
+#define DEC_197                                   196
+#define DEC_196                                   195
+#define DEC_195                                   194
+#define DEC_194                                   193
+#define DEC_193                                   192
+#define DEC_192                                   191
+#define DEC_191                                   190
+#define DEC_190                                   189
+#define DEC_189                                   188
+#define DEC_188                                   187
+#define DEC_187                                   186
+#define DEC_186                                   185
+#define DEC_185                                   184
+#define DEC_184                                   183
+#define DEC_183                                   182
+#define DEC_182                                   181
+#define DEC_181                                   180
+#define DEC_180                                   179
+#define DEC_179                                   178
+#define DEC_178                                   177
+#define DEC_177                                   176
+#define DEC_176                                   175
+#define DEC_175                                   174
+#define DEC_174                                   173
+#define DEC_173                                   172
+#define DEC_172                                   171
+#define DEC_171                                   170
+#define DEC_170                                   169
+#define DEC_169                                   168
+#define DEC_168                                   167
+#define DEC_167                                   166
+#define DEC_166                                   165
+#define DEC_165                                   164
+#define DEC_164                                   163
+#define DEC_163                                   162
+#define DEC_162                                   161
+#define DEC_161                                   160
+#define DEC_160                                   159
+#define DEC_159                                   158
+#define DEC_158                                   157
+#define DEC_157                                   156
+#define DEC_156                                   155
+#define DEC_155                                   154
+#define DEC_154                                   153
+#define DEC_153                                   152
+#define DEC_152                                   151
+#define DEC_151                                   150
+#define DEC_150                                   149
+#define DEC_149                                   148
+#define DEC_148                                   147
+#define DEC_147                                   146
+#define DEC_146                                   145
+#define DEC_145                                   144
+#define DEC_144                                   143
+#define DEC_143                                   142
+#define DEC_142                                   141
+#define DEC_141                                   140
+#define DEC_140                                   139
+#define DEC_139                                   138
+#define DEC_138                                   137
+#define DEC_137                                   136
+#define DEC_136                                   135
+#define DEC_135                                   134
+#define DEC_134                                   133
+#define DEC_133                                   132
+#define DEC_132                                   131
+#define DEC_131                                   130
+#define DEC_130                                   129
+#define DEC_129                                   128
+#define DEC_128                                   127
+#define DEC_127                                   126
+#define DEC_126                                   125
+#define DEC_125                                   124
+#define DEC_124                                   123
+#define DEC_123                                   122
+#define DEC_122                                   121
+#define DEC_121                                   120
+#define DEC_120                                   119
+#define DEC_119                                   118
+#define DEC_118                                   117
+#define DEC_117                                   116
+#define DEC_116                                   115
+#define DEC_115                                   114
+#define DEC_114                                   113
+#define DEC_113                                   112
+#define DEC_112                                   111
+#define DEC_111                                   110
+#define DEC_110                                   109
+#define DEC_109                                   108
+#define DEC_108                                   107
+#define DEC_107                                   106
+#define DEC_106                                   105
+#define DEC_105                                   104
+#define DEC_104                                   103
+#define DEC_103                                   102
+#define DEC_102                                   101
+#define DEC_101                                   100
+#define DEC_100                                    99
+#define DEC_99                                     98
+#define DEC_98                                     97
+#define DEC_97                                     96
+#define DEC_96                                     95
+#define DEC_95                                     94
+#define DEC_94                                     93
+#define DEC_93                                     92
+#define DEC_92                                     91
+#define DEC_91                                     90
+#define DEC_90                                     89
+#define DEC_89                                     88
+#define DEC_88                                     87
+#define DEC_87                                     86
+#define DEC_86                                     85
+#define DEC_85                                     84
+#define DEC_84                                     83
+#define DEC_83                                     82
+#define DEC_82                                     81
+#define DEC_81                                     80
+#define DEC_80                                     79
+#define DEC_79                                     78
+#define DEC_78                                     77
+#define DEC_77                                     76
+#define DEC_76                                     75
+#define DEC_75                                     74
+#define DEC_74                                     73
+#define DEC_73                                     72
+#define DEC_72                                     71
+#define DEC_71                                     70
+#define DEC_70                                     69
+#define DEC_69                                     68
+#define DEC_68                                     67
+#define DEC_67                                     66
+#define DEC_66                                     65
+#define DEC_65                                     64
+#define DEC_64                                     63
+#define DEC_63                                     62
+#define DEC_62                                     61
+#define DEC_61                                     60
+#define DEC_60                                     59
+#define DEC_59                                     58
+#define DEC_58                                     57
+#define DEC_57                                     56
+#define DEC_56                                     55
+#define DEC_55                                     54
+#define DEC_54                                     53
+#define DEC_53                                     52
+#define DEC_52                                     51
+#define DEC_51                                     50
+#define DEC_50                                     49
+#define DEC_49                                     48
+#define DEC_48                                     47
+#define DEC_47                                     46
+#define DEC_46                                     45
+#define DEC_45                                     44
+#define DEC_44                                     43
+#define DEC_43                                     42
+#define DEC_42                                     41
+#define DEC_41                                     40
+#define DEC_40                                     39
+#define DEC_39                                     38
+#define DEC_38                                     37
+#define DEC_37                                     36
+#define DEC_36                                     35
+#define DEC_35                                     34
+#define DEC_34                                     33
+#define DEC_33                                     32
+#define DEC_32                                     31
+#define DEC_31                                     30
+#define DEC_30                                     29
+#define DEC_29                                     28
+#define DEC_28                                     27
+#define DEC_27                                     26
+#define DEC_26                                     25
+#define DEC_25                                     24
+#define DEC_24                                     23
+#define DEC_23                                     22
+#define DEC_22                                     21
+#define DEC_21                                     20
+#define DEC_20                                     19
+#define DEC_19                                     18
+#define DEC_18                                     17
+#define DEC_17                                     16
+#define DEC_16                                     15
+#define DEC_15                                     14
+#define DEC_14                                     13
+#define DEC_13                                     12
+#define DEC_12                                     11
+#define DEC_11                                     10
+#define DEC_10                                      9
+#define DEC_9                                       8
+#define DEC_8                                       7
+#define DEC_7                                       6
+#define DEC_6                                       5
+#define DEC_5                                       4
+#define DEC_4                                       3
+#define DEC_3                                       2
+#define DEC_2                                       1
+#define DEC_1                                       0
+#define DEC_(n)                                     DEC_##n
+
+
+/** Maximal number of repetitions supported by MRECURSION. */
+#define MRECURSION_LIMIT   256
+
+/** \brief Macro recursion.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count  The number of repetitious calls to macro. Valid values
+ *                   range from 0 to MRECURSION_LIMIT.
+ * \param[in] macro  A binary operation of the form macro(data, n).  This macro
+ *                   is expanded by MRECURSION with the current repetition number
+ *                   and the auxiliary data argument.
+ * \param[in] data   A recursive threshold, building on this to decline by times 
+ *                   defined with param count.
+ *
+ * \return       <tt>macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1)</tt>
+ */
+#define MRECURSION(count, macro, data) TPASTE2(MRECURSION, count) (macro, data)
+
+#define MRECURSION0(  macro, data)
+#define MRECURSION1(  macro, data)    MRECURSION0(  macro, DEC_(data))   macro(data, 0)
+#define MRECURSION2(  macro, data)    MRECURSION1(  macro, DEC_(data))   macro(data, 1)
+#define MRECURSION3(  macro, data)    MRECURSION2(  macro, DEC_(data))   macro(data, 2)
+#define MRECURSION4(  macro, data)    MRECURSION3(  macro, DEC_(data))   macro(data, 3)
+#define MRECURSION5(  macro, data)    MRECURSION4(  macro, DEC_(data))   macro(data, 4)
+#define MRECURSION6(  macro, data)    MRECURSION5(  macro, DEC_(data))   macro(data, 5)
+#define MRECURSION7(  macro, data)    MRECURSION6(  macro, DEC_(data))   macro(data, 6)
+#define MRECURSION8(  macro, data)    MRECURSION7(  macro, DEC_(data))   macro(data, 7)
+#define MRECURSION9(  macro, data)    MRECURSION8(  macro, DEC_(data))   macro(data, 8)
+#define MRECURSION10( macro, data)    MRECURSION9(  macro, DEC_(data))   macro(data, 9)
+#define MRECURSION11( macro, data)    MRECURSION10(  macro, DEC_(data))   macro(data, 10)
+#define MRECURSION12( macro, data)    MRECURSION11(  macro, DEC_(data))   macro(data, 11)
+#define MRECURSION13( macro, data)    MRECURSION12(  macro, DEC_(data))   macro(data, 12)
+#define MRECURSION14( macro, data)    MRECURSION13(  macro, DEC_(data))   macro(data, 13)
+#define MRECURSION15( macro, data)    MRECURSION14(  macro, DEC_(data))   macro(data, 14)
+#define MRECURSION16( macro, data)    MRECURSION15(  macro, DEC_(data))   macro(data, 15)
+#define MRECURSION17( macro, data)    MRECURSION16(  macro, DEC_(data))   macro(data, 16)
+#define MRECURSION18( macro, data)    MRECURSION17(  macro, DEC_(data))   macro(data, 17)
+#define MRECURSION19( macro, data)    MRECURSION18(  macro, DEC_(data))   macro(data, 18)
+#define MRECURSION20( macro, data)    MRECURSION19(  macro, DEC_(data))   macro(data, 19)
+#define MRECURSION21( macro, data)    MRECURSION20(  macro, DEC_(data))   macro(data, 20)
+#define MRECURSION22( macro, data)    MRECURSION21(  macro, DEC_(data))   macro(data, 21)
+#define MRECURSION23( macro, data)    MRECURSION22(  macro, DEC_(data))   macro(data, 22)
+#define MRECURSION24( macro, data)    MRECURSION23(  macro, DEC_(data))   macro(data, 23)
+#define MRECURSION25( macro, data)    MRECURSION24(  macro, DEC_(data))   macro(data, 24)
+#define MRECURSION26( macro, data)    MRECURSION25(  macro, DEC_(data))   macro(data, 25)
+#define MRECURSION27( macro, data)    MRECURSION26(  macro, DEC_(data))   macro(data, 26)
+#define MRECURSION28( macro, data)    MRECURSION27(  macro, DEC_(data))   macro(data, 27)
+#define MRECURSION29( macro, data)    MRECURSION28(  macro, DEC_(data))   macro(data, 28)
+#define MRECURSION30( macro, data)    MRECURSION29(  macro, DEC_(data))   macro(data, 29)
+#define MRECURSION31( macro, data)    MRECURSION30(  macro, DEC_(data))   macro(data, 30)
+#define MRECURSION32( macro, data)    MRECURSION31(  macro, DEC_(data))   macro(data, 31)
+#define MRECURSION33( macro, data)    MRECURSION32(  macro, DEC_(data))   macro(data, 32)
+#define MRECURSION34( macro, data)    MRECURSION33(  macro, DEC_(data))   macro(data, 33)
+#define MRECURSION35( macro, data)    MRECURSION34(  macro, DEC_(data))   macro(data, 34)
+#define MRECURSION36( macro, data)    MRECURSION35(  macro, DEC_(data))   macro(data, 35)
+#define MRECURSION37( macro, data)    MRECURSION36(  macro, DEC_(data))   macro(data, 36)
+#define MRECURSION38( macro, data)    MRECURSION37(  macro, DEC_(data))   macro(data, 37)
+#define MRECURSION39( macro, data)    MRECURSION38(  macro, DEC_(data))   macro(data, 38)
+#define MRECURSION40( macro, data)    MRECURSION39(  macro, DEC_(data))   macro(data, 39)
+#define MRECURSION41( macro, data)    MRECURSION40(  macro, DEC_(data))   macro(data, 40)
+#define MRECURSION42( macro, data)    MRECURSION41(  macro, DEC_(data))   macro(data, 41)
+#define MRECURSION43( macro, data)    MRECURSION42(  macro, DEC_(data))   macro(data, 42)
+#define MRECURSION44( macro, data)    MRECURSION43(  macro, DEC_(data))   macro(data, 43)
+#define MRECURSION45( macro, data)    MRECURSION44(  macro, DEC_(data))   macro(data, 44)
+#define MRECURSION46( macro, data)    MRECURSION45(  macro, DEC_(data))   macro(data, 45)
+#define MRECURSION47( macro, data)    MRECURSION46(  macro, DEC_(data))   macro(data, 46)
+#define MRECURSION48( macro, data)    MRECURSION47(  macro, DEC_(data))   macro(data, 47)
+#define MRECURSION49( macro, data)    MRECURSION48(  macro, DEC_(data))   macro(data, 48)
+#define MRECURSION50( macro, data)    MRECURSION49(  macro, DEC_(data))   macro(data, 49)
+#define MRECURSION51( macro, data)    MRECURSION50(  macro, DEC_(data))   macro(data, 50)
+#define MRECURSION52( macro, data)    MRECURSION51(  macro, DEC_(data))   macro(data, 51)
+#define MRECURSION53( macro, data)    MRECURSION52(  macro, DEC_(data))   macro(data, 52)
+#define MRECURSION54( macro, data)    MRECURSION53(  macro, DEC_(data))   macro(data, 53)
+#define MRECURSION55( macro, data)    MRECURSION54(  macro, DEC_(data))   macro(data, 54)
+#define MRECURSION56( macro, data)    MRECURSION55(  macro, DEC_(data))   macro(data, 55)
+#define MRECURSION57( macro, data)    MRECURSION56(  macro, DEC_(data))   macro(data, 56)
+#define MRECURSION58( macro, data)    MRECURSION57(  macro, DEC_(data))   macro(data, 57)
+#define MRECURSION59( macro, data)    MRECURSION58(  macro, DEC_(data))   macro(data, 58)
+#define MRECURSION60( macro, data)    MRECURSION59(  macro, DEC_(data))   macro(data, 59)
+#define MRECURSION61( macro, data)    MRECURSION60(  macro, DEC_(data))   macro(data, 60)
+#define MRECURSION62( macro, data)    MRECURSION61(  macro, DEC_(data))   macro(data, 61)
+#define MRECURSION63( macro, data)    MRECURSION62(  macro, DEC_(data))   macro(data, 62)
+#define MRECURSION64( macro, data)    MRECURSION63(  macro, DEC_(data))   macro(data, 63)
+#define MRECURSION65( macro, data)    MRECURSION64(  macro, DEC_(data))   macro(data, 64)
+#define MRECURSION66( macro, data)    MRECURSION65(  macro, DEC_(data))   macro(data, 65)
+#define MRECURSION67( macro, data)    MRECURSION66(  macro, DEC_(data))   macro(data, 66)
+#define MRECURSION68( macro, data)    MRECURSION67(  macro, DEC_(data))   macro(data, 67)
+#define MRECURSION69( macro, data)    MRECURSION68(  macro, DEC_(data))   macro(data, 68)
+#define MRECURSION70( macro, data)    MRECURSION69(  macro, DEC_(data))   macro(data, 69)
+#define MRECURSION71( macro, data)    MRECURSION70(  macro, DEC_(data))   macro(data, 70)
+#define MRECURSION72( macro, data)    MRECURSION71(  macro, DEC_(data))   macro(data, 71)
+#define MRECURSION73( macro, data)    MRECURSION72(  macro, DEC_(data))   macro(data, 72)
+#define MRECURSION74( macro, data)    MRECURSION73(  macro, DEC_(data))   macro(data, 73)
+#define MRECURSION75( macro, data)    MRECURSION74(  macro, DEC_(data))   macro(data, 74)
+#define MRECURSION76( macro, data)    MRECURSION75(  macro, DEC_(data))   macro(data, 75)
+#define MRECURSION77( macro, data)    MRECURSION76(  macro, DEC_(data))   macro(data, 76)
+#define MRECURSION78( macro, data)    MRECURSION77(  macro, DEC_(data))   macro(data, 77)
+#define MRECURSION79( macro, data)    MRECURSION78(  macro, DEC_(data))   macro(data, 78)
+#define MRECURSION80( macro, data)    MRECURSION79(  macro, DEC_(data))   macro(data, 79)
+#define MRECURSION81( macro, data)    MRECURSION80(  macro, DEC_(data))   macro(data, 80)
+#define MRECURSION82( macro, data)    MRECURSION81(  macro, DEC_(data))   macro(data, 81)
+#define MRECURSION83( macro, data)    MRECURSION82(  macro, DEC_(data))   macro(data, 82)
+#define MRECURSION84( macro, data)    MRECURSION83(  macro, DEC_(data))   macro(data, 83)
+#define MRECURSION85( macro, data)    MRECURSION84(  macro, DEC_(data))   macro(data, 84)
+#define MRECURSION86( macro, data)    MRECURSION85(  macro, DEC_(data))   macro(data, 85)
+#define MRECURSION87( macro, data)    MRECURSION86(  macro, DEC_(data))   macro(data, 86)
+#define MRECURSION88( macro, data)    MRECURSION87(  macro, DEC_(data))   macro(data, 87)
+#define MRECURSION89( macro, data)    MRECURSION88(  macro, DEC_(data))   macro(data, 88)
+#define MRECURSION90( macro, data)    MRECURSION89(  macro, DEC_(data))   macro(data, 89)
+#define MRECURSION91( macro, data)    MRECURSION90(  macro, DEC_(data))   macro(data, 90)
+#define MRECURSION92( macro, data)    MRECURSION91(  macro, DEC_(data))   macro(data, 91)
+#define MRECURSION93( macro, data)    MRECURSION92(  macro, DEC_(data))   macro(data, 92)
+#define MRECURSION94( macro, data)    MRECURSION93(  macro, DEC_(data))   macro(data, 93)
+#define MRECURSION95( macro, data)    MRECURSION94(  macro, DEC_(data))   macro(data, 94)
+#define MRECURSION96( macro, data)    MRECURSION95(  macro, DEC_(data))   macro(data, 95)
+#define MRECURSION97( macro, data)    MRECURSION96(  macro, DEC_(data))   macro(data, 96)
+#define MRECURSION98( macro, data)    MRECURSION97(  macro, DEC_(data))   macro(data, 97)
+#define MRECURSION99( macro, data)    MRECURSION98(  macro, DEC_(data))   macro(data, 98)
+#define MRECURSION100(macro, data)    MRECURSION99(  macro, DEC_(data))   macro(data, 99)
+#define MRECURSION101(macro, data)    MRECURSION100(  macro, DEC_(data))   macro(data, 100)
+#define MRECURSION102(macro, data)    MRECURSION101(  macro, DEC_(data))   macro(data, 101)
+#define MRECURSION103(macro, data)    MRECURSION102(  macro, DEC_(data))   macro(data, 102)
+#define MRECURSION104(macro, data)    MRECURSION103(  macro, DEC_(data))   macro(data, 103)
+#define MRECURSION105(macro, data)    MRECURSION104(  macro, DEC_(data))   macro(data, 104)
+#define MRECURSION106(macro, data)    MRECURSION105(  macro, DEC_(data))   macro(data, 105)
+#define MRECURSION107(macro, data)    MRECURSION106(  macro, DEC_(data))   macro(data, 106)
+#define MRECURSION108(macro, data)    MRECURSION107(  macro, DEC_(data))   macro(data, 107)
+#define MRECURSION109(macro, data)    MRECURSION108(  macro, DEC_(data))   macro(data, 108)
+#define MRECURSION110(macro, data)    MRECURSION109(  macro, DEC_(data))   macro(data, 109)
+#define MRECURSION111(macro, data)    MRECURSION110(  macro, DEC_(data))   macro(data, 110)
+#define MRECURSION112(macro, data)    MRECURSION111(  macro, DEC_(data))   macro(data, 111)
+#define MRECURSION113(macro, data)    MRECURSION112(  macro, DEC_(data))   macro(data, 112)
+#define MRECURSION114(macro, data)    MRECURSION113(  macro, DEC_(data))   macro(data, 113)
+#define MRECURSION115(macro, data)    MRECURSION114(  macro, DEC_(data))   macro(data, 114)
+#define MRECURSION116(macro, data)    MRECURSION115(  macro, DEC_(data))   macro(data, 115)
+#define MRECURSION117(macro, data)    MRECURSION116(  macro, DEC_(data))   macro(data, 116)
+#define MRECURSION118(macro, data)    MRECURSION117(  macro, DEC_(data))   macro(data, 117)
+#define MRECURSION119(macro, data)    MRECURSION118(  macro, DEC_(data))   macro(data, 118)
+#define MRECURSION120(macro, data)    MRECURSION119(  macro, DEC_(data))   macro(data, 119)
+#define MRECURSION121(macro, data)    MRECURSION120(  macro, DEC_(data))   macro(data, 120)
+#define MRECURSION122(macro, data)    MRECURSION121(  macro, DEC_(data))   macro(data, 121)
+#define MRECURSION123(macro, data)    MRECURSION122(  macro, DEC_(data))   macro(data, 122)
+#define MRECURSION124(macro, data)    MRECURSION123(  macro, DEC_(data))   macro(data, 123)
+#define MRECURSION125(macro, data)    MRECURSION124(  macro, DEC_(data))   macro(data, 124)
+#define MRECURSION126(macro, data)    MRECURSION125(  macro, DEC_(data))   macro(data, 125)
+#define MRECURSION127(macro, data)    MRECURSION126(  macro, DEC_(data))   macro(data, 126)
+#define MRECURSION128(macro, data)    MRECURSION127(  macro, DEC_(data))   macro(data, 127)
+#define MRECURSION129(macro, data)    MRECURSION128(  macro, DEC_(data))   macro(data, 128)
+#define MRECURSION130(macro, data)    MRECURSION129(  macro, DEC_(data))   macro(data, 129)
+#define MRECURSION131(macro, data)    MRECURSION130(  macro, DEC_(data))   macro(data, 130)
+#define MRECURSION132(macro, data)    MRECURSION131(  macro, DEC_(data))   macro(data, 131)
+#define MRECURSION133(macro, data)    MRECURSION132(  macro, DEC_(data))   macro(data, 132)
+#define MRECURSION134(macro, data)    MRECURSION133(  macro, DEC_(data))   macro(data, 133)
+#define MRECURSION135(macro, data)    MRECURSION134(  macro, DEC_(data))   macro(data, 134)
+#define MRECURSION136(macro, data)    MRECURSION135(  macro, DEC_(data))   macro(data, 135)
+#define MRECURSION137(macro, data)    MRECURSION136(  macro, DEC_(data))   macro(data, 136)
+#define MRECURSION138(macro, data)    MRECURSION137(  macro, DEC_(data))   macro(data, 137)
+#define MRECURSION139(macro, data)    MRECURSION138(  macro, DEC_(data))   macro(data, 138)
+#define MRECURSION140(macro, data)    MRECURSION139(  macro, DEC_(data))   macro(data, 139)
+#define MRECURSION141(macro, data)    MRECURSION140(  macro, DEC_(data))   macro(data, 140)
+#define MRECURSION142(macro, data)    MRECURSION141(  macro, DEC_(data))   macro(data, 141)
+#define MRECURSION143(macro, data)    MRECURSION142(  macro, DEC_(data))   macro(data, 142)
+#define MRECURSION144(macro, data)    MRECURSION143(  macro, DEC_(data))   macro(data, 143)
+#define MRECURSION145(macro, data)    MRECURSION144(  macro, DEC_(data))   macro(data, 144)
+#define MRECURSION146(macro, data)    MRECURSION145(  macro, DEC_(data))   macro(data, 145)
+#define MRECURSION147(macro, data)    MRECURSION146(  macro, DEC_(data))   macro(data, 146)
+#define MRECURSION148(macro, data)    MRECURSION147(  macro, DEC_(data))   macro(data, 147)
+#define MRECURSION149(macro, data)    MRECURSION148(  macro, DEC_(data))   macro(data, 148)
+#define MRECURSION150(macro, data)    MRECURSION149(  macro, DEC_(data))   macro(data, 149)
+#define MRECURSION151(macro, data)    MRECURSION150(  macro, DEC_(data))   macro(data, 150)
+#define MRECURSION152(macro, data)    MRECURSION151(  macro, DEC_(data))   macro(data, 151)
+#define MRECURSION153(macro, data)    MRECURSION152(  macro, DEC_(data))   macro(data, 152)
+#define MRECURSION154(macro, data)    MRECURSION153(  macro, DEC_(data))   macro(data, 153)
+#define MRECURSION155(macro, data)    MRECURSION154(  macro, DEC_(data))   macro(data, 154)
+#define MRECURSION156(macro, data)    MRECURSION155(  macro, DEC_(data))   macro(data, 155)
+#define MRECURSION157(macro, data)    MRECURSION156(  macro, DEC_(data))   macro(data, 156)
+#define MRECURSION158(macro, data)    MRECURSION157(  macro, DEC_(data))   macro(data, 157)
+#define MRECURSION159(macro, data)    MRECURSION158(  macro, DEC_(data))   macro(data, 158)
+#define MRECURSION160(macro, data)    MRECURSION159(  macro, DEC_(data))   macro(data, 159)
+#define MRECURSION161(macro, data)    MRECURSION160(  macro, DEC_(data))   macro(data, 160)
+#define MRECURSION162(macro, data)    MRECURSION161(  macro, DEC_(data))   macro(data, 161)
+#define MRECURSION163(macro, data)    MRECURSION162(  macro, DEC_(data))   macro(data, 162)
+#define MRECURSION164(macro, data)    MRECURSION163(  macro, DEC_(data))   macro(data, 163)
+#define MRECURSION165(macro, data)    MRECURSION164(  macro, DEC_(data))   macro(data, 164)
+#define MRECURSION166(macro, data)    MRECURSION165(  macro, DEC_(data))   macro(data, 165)
+#define MRECURSION167(macro, data)    MRECURSION166(  macro, DEC_(data))   macro(data, 166)
+#define MRECURSION168(macro, data)    MRECURSION167(  macro, DEC_(data))   macro(data, 167)
+#define MRECURSION169(macro, data)    MRECURSION168(  macro, DEC_(data))   macro(data, 168)
+#define MRECURSION170(macro, data)    MRECURSION169(  macro, DEC_(data))   macro(data, 169)
+#define MRECURSION171(macro, data)    MRECURSION170(  macro, DEC_(data))   macro(data, 170)
+#define MRECURSION172(macro, data)    MRECURSION171(  macro, DEC_(data))   macro(data, 171)
+#define MRECURSION173(macro, data)    MRECURSION172(  macro, DEC_(data))   macro(data, 172)
+#define MRECURSION174(macro, data)    MRECURSION173(  macro, DEC_(data))   macro(data, 173)
+#define MRECURSION175(macro, data)    MRECURSION174(  macro, DEC_(data))   macro(data, 174)
+#define MRECURSION176(macro, data)    MRECURSION175(  macro, DEC_(data))   macro(data, 175)
+#define MRECURSION177(macro, data)    MRECURSION176(  macro, DEC_(data))   macro(data, 176)
+#define MRECURSION178(macro, data)    MRECURSION177(  macro, DEC_(data))   macro(data, 177)
+#define MRECURSION179(macro, data)    MRECURSION178(  macro, DEC_(data))   macro(data, 178)
+#define MRECURSION180(macro, data)    MRECURSION179(  macro, DEC_(data))   macro(data, 179)
+#define MRECURSION181(macro, data)    MRECURSION180(  macro, DEC_(data))   macro(data, 180)
+#define MRECURSION182(macro, data)    MRECURSION181(  macro, DEC_(data))   macro(data, 181)
+#define MRECURSION183(macro, data)    MRECURSION182(  macro, DEC_(data))   macro(data, 182)
+#define MRECURSION184(macro, data)    MRECURSION183(  macro, DEC_(data))   macro(data, 183)
+#define MRECURSION185(macro, data)    MRECURSION184(  macro, DEC_(data))   macro(data, 184)
+#define MRECURSION186(macro, data)    MRECURSION185(  macro, DEC_(data))   macro(data, 185)
+#define MRECURSION187(macro, data)    MRECURSION186(  macro, DEC_(data))   macro(data, 186)
+#define MRECURSION188(macro, data)    MRECURSION187(  macro, DEC_(data))   macro(data, 187)
+#define MRECURSION189(macro, data)    MRECURSION188(  macro, DEC_(data))   macro(data, 188)
+#define MRECURSION190(macro, data)    MRECURSION189(  macro, DEC_(data))   macro(data, 189)
+#define MRECURSION191(macro, data)    MRECURSION190(  macro, DEC_(data))   macro(data, 190)
+#define MRECURSION192(macro, data)    MRECURSION191(  macro, DEC_(data))   macro(data, 191)
+#define MRECURSION193(macro, data)    MRECURSION192(  macro, DEC_(data))   macro(data, 192)
+#define MRECURSION194(macro, data)    MRECURSION193(  macro, DEC_(data))   macro(data, 193)
+#define MRECURSION195(macro, data)    MRECURSION194(  macro, DEC_(data))   macro(data, 194)
+#define MRECURSION196(macro, data)    MRECURSION195(  macro, DEC_(data))   macro(data, 195)
+#define MRECURSION197(macro, data)    MRECURSION196(  macro, DEC_(data))   macro(data, 196)
+#define MRECURSION198(macro, data)    MRECURSION197(  macro, DEC_(data))   macro(data, 197)
+#define MRECURSION199(macro, data)    MRECURSION198(  macro, DEC_(data))   macro(data, 198)
+#define MRECURSION200(macro, data)    MRECURSION199(  macro, DEC_(data))   macro(data, 199)
+#define MRECURSION201(macro, data)    MRECURSION200(  macro, DEC_(data))   macro(data, 200)
+#define MRECURSION202(macro, data)    MRECURSION201(  macro, DEC_(data))   macro(data, 201)
+#define MRECURSION203(macro, data)    MRECURSION202(  macro, DEC_(data))   macro(data, 202)
+#define MRECURSION204(macro, data)    MRECURSION203(  macro, DEC_(data))   macro(data, 203)
+#define MRECURSION205(macro, data)    MRECURSION204(  macro, DEC_(data))   macro(data, 204)
+#define MRECURSION206(macro, data)    MRECURSION205(  macro, DEC_(data))   macro(data, 205)
+#define MRECURSION207(macro, data)    MRECURSION206(  macro, DEC_(data))   macro(data, 206)
+#define MRECURSION208(macro, data)    MRECURSION207(  macro, DEC_(data))   macro(data, 207)
+#define MRECURSION209(macro, data)    MRECURSION208(  macro, DEC_(data))   macro(data, 208)
+#define MRECURSION210(macro, data)    MRECURSION209(  macro, DEC_(data))   macro(data, 209)
+#define MRECURSION211(macro, data)    MRECURSION210(  macro, DEC_(data))   macro(data, 210)
+#define MRECURSION212(macro, data)    MRECURSION211(  macro, DEC_(data))   macro(data, 211)
+#define MRECURSION213(macro, data)    MRECURSION212(  macro, DEC_(data))   macro(data, 212)
+#define MRECURSION214(macro, data)    MRECURSION213(  macro, DEC_(data))   macro(data, 213)
+#define MRECURSION215(macro, data)    MRECURSION214(  macro, DEC_(data))   macro(data, 214)
+#define MRECURSION216(macro, data)    MRECURSION215(  macro, DEC_(data))   macro(data, 215)
+#define MRECURSION217(macro, data)    MRECURSION216(  macro, DEC_(data))   macro(data, 216)
+#define MRECURSION218(macro, data)    MRECURSION217(  macro, DEC_(data))   macro(data, 217)
+#define MRECURSION219(macro, data)    MRECURSION218(  macro, DEC_(data))   macro(data, 218)
+#define MRECURSION220(macro, data)    MRECURSION219(  macro, DEC_(data))   macro(data, 219)
+#define MRECURSION221(macro, data)    MRECURSION220(  macro, DEC_(data))   macro(data, 220)
+#define MRECURSION222(macro, data)    MRECURSION221(  macro, DEC_(data))   macro(data, 221)
+#define MRECURSION223(macro, data)    MRECURSION222(  macro, DEC_(data))   macro(data, 222)
+#define MRECURSION224(macro, data)    MRECURSION223(  macro, DEC_(data))   macro(data, 223)
+#define MRECURSION225(macro, data)    MRECURSION224(  macro, DEC_(data))   macro(data, 224)
+#define MRECURSION226(macro, data)    MRECURSION225(  macro, DEC_(data))   macro(data, 225)
+#define MRECURSION227(macro, data)    MRECURSION226(  macro, DEC_(data))   macro(data, 226)
+#define MRECURSION228(macro, data)    MRECURSION227(  macro, DEC_(data))   macro(data, 227)
+#define MRECURSION229(macro, data)    MRECURSION228(  macro, DEC_(data))   macro(data, 228)
+#define MRECURSION230(macro, data)    MRECURSION229(  macro, DEC_(data))   macro(data, 229)
+#define MRECURSION231(macro, data)    MRECURSION230(  macro, DEC_(data))   macro(data, 230)
+#define MRECURSION232(macro, data)    MRECURSION231(  macro, DEC_(data))   macro(data, 231)
+#define MRECURSION233(macro, data)    MRECURSION232(  macro, DEC_(data))   macro(data, 232)
+#define MRECURSION234(macro, data)    MRECURSION233(  macro, DEC_(data))   macro(data, 233)
+#define MRECURSION235(macro, data)    MRECURSION234(  macro, DEC_(data))   macro(data, 234)
+#define MRECURSION236(macro, data)    MRECURSION235(  macro, DEC_(data))   macro(data, 235)
+#define MRECURSION237(macro, data)    MRECURSION236(  macro, DEC_(data))   macro(data, 236)
+#define MRECURSION238(macro, data)    MRECURSION237(  macro, DEC_(data))   macro(data, 237)
+#define MRECURSION239(macro, data)    MRECURSION238(  macro, DEC_(data))   macro(data, 238)
+#define MRECURSION240(macro, data)    MRECURSION239(  macro, DEC_(data))   macro(data, 239)
+#define MRECURSION241(macro, data)    MRECURSION240(  macro, DEC_(data))   macro(data, 240)
+#define MRECURSION242(macro, data)    MRECURSION241(  macro, DEC_(data))   macro(data, 241)
+#define MRECURSION243(macro, data)    MRECURSION242(  macro, DEC_(data))   macro(data, 242)
+#define MRECURSION244(macro, data)    MRECURSION243(  macro, DEC_(data))   macro(data, 243)
+#define MRECURSION245(macro, data)    MRECURSION244(  macro, DEC_(data))   macro(data, 244)
+#define MRECURSION246(macro, data)    MRECURSION245(  macro, DEC_(data))   macro(data, 245)
+#define MRECURSION247(macro, data)    MRECURSION246(  macro, DEC_(data))   macro(data, 246)
+#define MRECURSION248(macro, data)    MRECURSION247(  macro, DEC_(data))   macro(data, 247)
+#define MRECURSION249(macro, data)    MRECURSION248(  macro, DEC_(data))   macro(data, 248)
+#define MRECURSION250(macro, data)    MRECURSION249(  macro, DEC_(data))   macro(data, 249)
+#define MRECURSION251(macro, data)    MRECURSION250(  macro, DEC_(data))   macro(data, 250)
+#define MRECURSION252(macro, data)    MRECURSION251(  macro, DEC_(data))   macro(data, 251)
+#define MRECURSION253(macro, data)    MRECURSION252(  macro, DEC_(data))   macro(data, 252)
+#define MRECURSION254(macro, data)    MRECURSION253(  macro, DEC_(data))   macro(data, 253)
+#define MRECURSION255(macro, data)    MRECURSION254(  macro, DEC_(data))   macro(data, 254)
+#define MRECURSION256(macro, data)    MRECURSION255(  macro, DEC_(data))   macro(data, 255)
+
+/** @} */
+
+#endif  /* _MRECURSION_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrepeat.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrepeat.h
new file mode 100644
index 0000000000..b8c08c89dc
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrepeat.h
@@ -0,0 +1,338 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor macro repeating utils.
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _MREPEAT_H_
+#define _MREPEAT_H_
+
+/**
+ * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+/** Maximal number of repetitions supported by MREPEAT. */
+#define MREPEAT_LIMIT   256
+
+/** \brief Macro repeat.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count  The number of repetitious calls to macro. Valid values
+ *                   range from 0 to MREPEAT_LIMIT.
+ * \param[in] macro  A binary operation of the form macro(n, data). This macro
+ *                   is expanded by MREPEAT with the current repetition number
+ *                   and the auxiliary data argument.
+ * \param[in] data   Auxiliary data passed to macro.
+ *
+ * \return       <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
+ */
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data)
+
+#define MREPEAT0(  macro, data)
+#define MREPEAT1(  macro, data)    MREPEAT0(  macro, data)   macro(  0, data)
+#define MREPEAT2(  macro, data)    MREPEAT1(  macro, data)   macro(  1, data)
+#define MREPEAT3(  macro, data)    MREPEAT2(  macro, data)   macro(  2, data)
+#define MREPEAT4(  macro, data)    MREPEAT3(  macro, data)   macro(  3, data)
+#define MREPEAT5(  macro, data)    MREPEAT4(  macro, data)   macro(  4, data)
+#define MREPEAT6(  macro, data)    MREPEAT5(  macro, data)   macro(  5, data)
+#define MREPEAT7(  macro, data)    MREPEAT6(  macro, data)   macro(  6, data)
+#define MREPEAT8(  macro, data)    MREPEAT7(  macro, data)   macro(  7, data)
+#define MREPEAT9(  macro, data)    MREPEAT8(  macro, data)   macro(  8, data)
+#define MREPEAT10( macro, data)    MREPEAT9(  macro, data)   macro(  9, data)
+#define MREPEAT11( macro, data)    MREPEAT10( macro, data)   macro( 10, data)
+#define MREPEAT12( macro, data)    MREPEAT11( macro, data)   macro( 11, data)
+#define MREPEAT13( macro, data)    MREPEAT12( macro, data)   macro( 12, data)
+#define MREPEAT14( macro, data)    MREPEAT13( macro, data)   macro( 13, data)
+#define MREPEAT15( macro, data)    MREPEAT14( macro, data)   macro( 14, data)
+#define MREPEAT16( macro, data)    MREPEAT15( macro, data)   macro( 15, data)
+#define MREPEAT17( macro, data)    MREPEAT16( macro, data)   macro( 16, data)
+#define MREPEAT18( macro, data)    MREPEAT17( macro, data)   macro( 17, data)
+#define MREPEAT19( macro, data)    MREPEAT18( macro, data)   macro( 18, data)
+#define MREPEAT20( macro, data)    MREPEAT19( macro, data)   macro( 19, data)
+#define MREPEAT21( macro, data)    MREPEAT20( macro, data)   macro( 20, data)
+#define MREPEAT22( macro, data)    MREPEAT21( macro, data)   macro( 21, data)
+#define MREPEAT23( macro, data)    MREPEAT22( macro, data)   macro( 22, data)
+#define MREPEAT24( macro, data)    MREPEAT23( macro, data)   macro( 23, data)
+#define MREPEAT25( macro, data)    MREPEAT24( macro, data)   macro( 24, data)
+#define MREPEAT26( macro, data)    MREPEAT25( macro, data)   macro( 25, data)
+#define MREPEAT27( macro, data)    MREPEAT26( macro, data)   macro( 26, data)
+#define MREPEAT28( macro, data)    MREPEAT27( macro, data)   macro( 27, data)
+#define MREPEAT29( macro, data)    MREPEAT28( macro, data)   macro( 28, data)
+#define MREPEAT30( macro, data)    MREPEAT29( macro, data)   macro( 29, data)
+#define MREPEAT31( macro, data)    MREPEAT30( macro, data)   macro( 30, data)
+#define MREPEAT32( macro, data)    MREPEAT31( macro, data)   macro( 31, data)
+#define MREPEAT33( macro, data)    MREPEAT32( macro, data)   macro( 32, data)
+#define MREPEAT34( macro, data)    MREPEAT33( macro, data)   macro( 33, data)
+#define MREPEAT35( macro, data)    MREPEAT34( macro, data)   macro( 34, data)
+#define MREPEAT36( macro, data)    MREPEAT35( macro, data)   macro( 35, data)
+#define MREPEAT37( macro, data)    MREPEAT36( macro, data)   macro( 36, data)
+#define MREPEAT38( macro, data)    MREPEAT37( macro, data)   macro( 37, data)
+#define MREPEAT39( macro, data)    MREPEAT38( macro, data)   macro( 38, data)
+#define MREPEAT40( macro, data)    MREPEAT39( macro, data)   macro( 39, data)
+#define MREPEAT41( macro, data)    MREPEAT40( macro, data)   macro( 40, data)
+#define MREPEAT42( macro, data)    MREPEAT41( macro, data)   macro( 41, data)
+#define MREPEAT43( macro, data)    MREPEAT42( macro, data)   macro( 42, data)
+#define MREPEAT44( macro, data)    MREPEAT43( macro, data)   macro( 43, data)
+#define MREPEAT45( macro, data)    MREPEAT44( macro, data)   macro( 44, data)
+#define MREPEAT46( macro, data)    MREPEAT45( macro, data)   macro( 45, data)
+#define MREPEAT47( macro, data)    MREPEAT46( macro, data)   macro( 46, data)
+#define MREPEAT48( macro, data)    MREPEAT47( macro, data)   macro( 47, data)
+#define MREPEAT49( macro, data)    MREPEAT48( macro, data)   macro( 48, data)
+#define MREPEAT50( macro, data)    MREPEAT49( macro, data)   macro( 49, data)
+#define MREPEAT51( macro, data)    MREPEAT50( macro, data)   macro( 50, data)
+#define MREPEAT52( macro, data)    MREPEAT51( macro, data)   macro( 51, data)
+#define MREPEAT53( macro, data)    MREPEAT52( macro, data)   macro( 52, data)
+#define MREPEAT54( macro, data)    MREPEAT53( macro, data)   macro( 53, data)
+#define MREPEAT55( macro, data)    MREPEAT54( macro, data)   macro( 54, data)
+#define MREPEAT56( macro, data)    MREPEAT55( macro, data)   macro( 55, data)
+#define MREPEAT57( macro, data)    MREPEAT56( macro, data)   macro( 56, data)
+#define MREPEAT58( macro, data)    MREPEAT57( macro, data)   macro( 57, data)
+#define MREPEAT59( macro, data)    MREPEAT58( macro, data)   macro( 58, data)
+#define MREPEAT60( macro, data)    MREPEAT59( macro, data)   macro( 59, data)
+#define MREPEAT61( macro, data)    MREPEAT60( macro, data)   macro( 60, data)
+#define MREPEAT62( macro, data)    MREPEAT61( macro, data)   macro( 61, data)
+#define MREPEAT63( macro, data)    MREPEAT62( macro, data)   macro( 62, data)
+#define MREPEAT64( macro, data)    MREPEAT63( macro, data)   macro( 63, data)
+#define MREPEAT65( macro, data)    MREPEAT64( macro, data)   macro( 64, data)
+#define MREPEAT66( macro, data)    MREPEAT65( macro, data)   macro( 65, data)
+#define MREPEAT67( macro, data)    MREPEAT66( macro, data)   macro( 66, data)
+#define MREPEAT68( macro, data)    MREPEAT67( macro, data)   macro( 67, data)
+#define MREPEAT69( macro, data)    MREPEAT68( macro, data)   macro( 68, data)
+#define MREPEAT70( macro, data)    MREPEAT69( macro, data)   macro( 69, data)
+#define MREPEAT71( macro, data)    MREPEAT70( macro, data)   macro( 70, data)
+#define MREPEAT72( macro, data)    MREPEAT71( macro, data)   macro( 71, data)
+#define MREPEAT73( macro, data)    MREPEAT72( macro, data)   macro( 72, data)
+#define MREPEAT74( macro, data)    MREPEAT73( macro, data)   macro( 73, data)
+#define MREPEAT75( macro, data)    MREPEAT74( macro, data)   macro( 74, data)
+#define MREPEAT76( macro, data)    MREPEAT75( macro, data)   macro( 75, data)
+#define MREPEAT77( macro, data)    MREPEAT76( macro, data)   macro( 76, data)
+#define MREPEAT78( macro, data)    MREPEAT77( macro, data)   macro( 77, data)
+#define MREPEAT79( macro, data)    MREPEAT78( macro, data)   macro( 78, data)
+#define MREPEAT80( macro, data)    MREPEAT79( macro, data)   macro( 79, data)
+#define MREPEAT81( macro, data)    MREPEAT80( macro, data)   macro( 80, data)
+#define MREPEAT82( macro, data)    MREPEAT81( macro, data)   macro( 81, data)
+#define MREPEAT83( macro, data)    MREPEAT82( macro, data)   macro( 82, data)
+#define MREPEAT84( macro, data)    MREPEAT83( macro, data)   macro( 83, data)
+#define MREPEAT85( macro, data)    MREPEAT84( macro, data)   macro( 84, data)
+#define MREPEAT86( macro, data)    MREPEAT85( macro, data)   macro( 85, data)
+#define MREPEAT87( macro, data)    MREPEAT86( macro, data)   macro( 86, data)
+#define MREPEAT88( macro, data)    MREPEAT87( macro, data)   macro( 87, data)
+#define MREPEAT89( macro, data)    MREPEAT88( macro, data)   macro( 88, data)
+#define MREPEAT90( macro, data)    MREPEAT89( macro, data)   macro( 89, data)
+#define MREPEAT91( macro, data)    MREPEAT90( macro, data)   macro( 90, data)
+#define MREPEAT92( macro, data)    MREPEAT91( macro, data)   macro( 91, data)
+#define MREPEAT93( macro, data)    MREPEAT92( macro, data)   macro( 92, data)
+#define MREPEAT94( macro, data)    MREPEAT93( macro, data)   macro( 93, data)
+#define MREPEAT95( macro, data)    MREPEAT94( macro, data)   macro( 94, data)
+#define MREPEAT96( macro, data)    MREPEAT95( macro, data)   macro( 95, data)
+#define MREPEAT97( macro, data)    MREPEAT96( macro, data)   macro( 96, data)
+#define MREPEAT98( macro, data)    MREPEAT97( macro, data)   macro( 97, data)
+#define MREPEAT99( macro, data)    MREPEAT98( macro, data)   macro( 98, data)
+#define MREPEAT100(macro, data)    MREPEAT99( macro, data)   macro( 99, data)
+#define MREPEAT101(macro, data)    MREPEAT100(macro, data)   macro(100, data)
+#define MREPEAT102(macro, data)    MREPEAT101(macro, data)   macro(101, data)
+#define MREPEAT103(macro, data)    MREPEAT102(macro, data)   macro(102, data)
+#define MREPEAT104(macro, data)    MREPEAT103(macro, data)   macro(103, data)
+#define MREPEAT105(macro, data)    MREPEAT104(macro, data)   macro(104, data)
+#define MREPEAT106(macro, data)    MREPEAT105(macro, data)   macro(105, data)
+#define MREPEAT107(macro, data)    MREPEAT106(macro, data)   macro(106, data)
+#define MREPEAT108(macro, data)    MREPEAT107(macro, data)   macro(107, data)
+#define MREPEAT109(macro, data)    MREPEAT108(macro, data)   macro(108, data)
+#define MREPEAT110(macro, data)    MREPEAT109(macro, data)   macro(109, data)
+#define MREPEAT111(macro, data)    MREPEAT110(macro, data)   macro(110, data)
+#define MREPEAT112(macro, data)    MREPEAT111(macro, data)   macro(111, data)
+#define MREPEAT113(macro, data)    MREPEAT112(macro, data)   macro(112, data)
+#define MREPEAT114(macro, data)    MREPEAT113(macro, data)   macro(113, data)
+#define MREPEAT115(macro, data)    MREPEAT114(macro, data)   macro(114, data)
+#define MREPEAT116(macro, data)    MREPEAT115(macro, data)   macro(115, data)
+#define MREPEAT117(macro, data)    MREPEAT116(macro, data)   macro(116, data)
+#define MREPEAT118(macro, data)    MREPEAT117(macro, data)   macro(117, data)
+#define MREPEAT119(macro, data)    MREPEAT118(macro, data)   macro(118, data)
+#define MREPEAT120(macro, data)    MREPEAT119(macro, data)   macro(119, data)
+#define MREPEAT121(macro, data)    MREPEAT120(macro, data)   macro(120, data)
+#define MREPEAT122(macro, data)    MREPEAT121(macro, data)   macro(121, data)
+#define MREPEAT123(macro, data)    MREPEAT122(macro, data)   macro(122, data)
+#define MREPEAT124(macro, data)    MREPEAT123(macro, data)   macro(123, data)
+#define MREPEAT125(macro, data)    MREPEAT124(macro, data)   macro(124, data)
+#define MREPEAT126(macro, data)    MREPEAT125(macro, data)   macro(125, data)
+#define MREPEAT127(macro, data)    MREPEAT126(macro, data)   macro(126, data)
+#define MREPEAT128(macro, data)    MREPEAT127(macro, data)   macro(127, data)
+#define MREPEAT129(macro, data)    MREPEAT128(macro, data)   macro(128, data)
+#define MREPEAT130(macro, data)    MREPEAT129(macro, data)   macro(129, data)
+#define MREPEAT131(macro, data)    MREPEAT130(macro, data)   macro(130, data)
+#define MREPEAT132(macro, data)    MREPEAT131(macro, data)   macro(131, data)
+#define MREPEAT133(macro, data)    MREPEAT132(macro, data)   macro(132, data)
+#define MREPEAT134(macro, data)    MREPEAT133(macro, data)   macro(133, data)
+#define MREPEAT135(macro, data)    MREPEAT134(macro, data)   macro(134, data)
+#define MREPEAT136(macro, data)    MREPEAT135(macro, data)   macro(135, data)
+#define MREPEAT137(macro, data)    MREPEAT136(macro, data)   macro(136, data)
+#define MREPEAT138(macro, data)    MREPEAT137(macro, data)   macro(137, data)
+#define MREPEAT139(macro, data)    MREPEAT138(macro, data)   macro(138, data)
+#define MREPEAT140(macro, data)    MREPEAT139(macro, data)   macro(139, data)
+#define MREPEAT141(macro, data)    MREPEAT140(macro, data)   macro(140, data)
+#define MREPEAT142(macro, data)    MREPEAT141(macro, data)   macro(141, data)
+#define MREPEAT143(macro, data)    MREPEAT142(macro, data)   macro(142, data)
+#define MREPEAT144(macro, data)    MREPEAT143(macro, data)   macro(143, data)
+#define MREPEAT145(macro, data)    MREPEAT144(macro, data)   macro(144, data)
+#define MREPEAT146(macro, data)    MREPEAT145(macro, data)   macro(145, data)
+#define MREPEAT147(macro, data)    MREPEAT146(macro, data)   macro(146, data)
+#define MREPEAT148(macro, data)    MREPEAT147(macro, data)   macro(147, data)
+#define MREPEAT149(macro, data)    MREPEAT148(macro, data)   macro(148, data)
+#define MREPEAT150(macro, data)    MREPEAT149(macro, data)   macro(149, data)
+#define MREPEAT151(macro, data)    MREPEAT150(macro, data)   macro(150, data)
+#define MREPEAT152(macro, data)    MREPEAT151(macro, data)   macro(151, data)
+#define MREPEAT153(macro, data)    MREPEAT152(macro, data)   macro(152, data)
+#define MREPEAT154(macro, data)    MREPEAT153(macro, data)   macro(153, data)
+#define MREPEAT155(macro, data)    MREPEAT154(macro, data)   macro(154, data)
+#define MREPEAT156(macro, data)    MREPEAT155(macro, data)   macro(155, data)
+#define MREPEAT157(macro, data)    MREPEAT156(macro, data)   macro(156, data)
+#define MREPEAT158(macro, data)    MREPEAT157(macro, data)   macro(157, data)
+#define MREPEAT159(macro, data)    MREPEAT158(macro, data)   macro(158, data)
+#define MREPEAT160(macro, data)    MREPEAT159(macro, data)   macro(159, data)
+#define MREPEAT161(macro, data)    MREPEAT160(macro, data)   macro(160, data)
+#define MREPEAT162(macro, data)    MREPEAT161(macro, data)   macro(161, data)
+#define MREPEAT163(macro, data)    MREPEAT162(macro, data)   macro(162, data)
+#define MREPEAT164(macro, data)    MREPEAT163(macro, data)   macro(163, data)
+#define MREPEAT165(macro, data)    MREPEAT164(macro, data)   macro(164, data)
+#define MREPEAT166(macro, data)    MREPEAT165(macro, data)   macro(165, data)
+#define MREPEAT167(macro, data)    MREPEAT166(macro, data)   macro(166, data)
+#define MREPEAT168(macro, data)    MREPEAT167(macro, data)   macro(167, data)
+#define MREPEAT169(macro, data)    MREPEAT168(macro, data)   macro(168, data)
+#define MREPEAT170(macro, data)    MREPEAT169(macro, data)   macro(169, data)
+#define MREPEAT171(macro, data)    MREPEAT170(macro, data)   macro(170, data)
+#define MREPEAT172(macro, data)    MREPEAT171(macro, data)   macro(171, data)
+#define MREPEAT173(macro, data)    MREPEAT172(macro, data)   macro(172, data)
+#define MREPEAT174(macro, data)    MREPEAT173(macro, data)   macro(173, data)
+#define MREPEAT175(macro, data)    MREPEAT174(macro, data)   macro(174, data)
+#define MREPEAT176(macro, data)    MREPEAT175(macro, data)   macro(175, data)
+#define MREPEAT177(macro, data)    MREPEAT176(macro, data)   macro(176, data)
+#define MREPEAT178(macro, data)    MREPEAT177(macro, data)   macro(177, data)
+#define MREPEAT179(macro, data)    MREPEAT178(macro, data)   macro(178, data)
+#define MREPEAT180(macro, data)    MREPEAT179(macro, data)   macro(179, data)
+#define MREPEAT181(macro, data)    MREPEAT180(macro, data)   macro(180, data)
+#define MREPEAT182(macro, data)    MREPEAT181(macro, data)   macro(181, data)
+#define MREPEAT183(macro, data)    MREPEAT182(macro, data)   macro(182, data)
+#define MREPEAT184(macro, data)    MREPEAT183(macro, data)   macro(183, data)
+#define MREPEAT185(macro, data)    MREPEAT184(macro, data)   macro(184, data)
+#define MREPEAT186(macro, data)    MREPEAT185(macro, data)   macro(185, data)
+#define MREPEAT187(macro, data)    MREPEAT186(macro, data)   macro(186, data)
+#define MREPEAT188(macro, data)    MREPEAT187(macro, data)   macro(187, data)
+#define MREPEAT189(macro, data)    MREPEAT188(macro, data)   macro(188, data)
+#define MREPEAT190(macro, data)    MREPEAT189(macro, data)   macro(189, data)
+#define MREPEAT191(macro, data)    MREPEAT190(macro, data)   macro(190, data)
+#define MREPEAT192(macro, data)    MREPEAT191(macro, data)   macro(191, data)
+#define MREPEAT193(macro, data)    MREPEAT192(macro, data)   macro(192, data)
+#define MREPEAT194(macro, data)    MREPEAT193(macro, data)   macro(193, data)
+#define MREPEAT195(macro, data)    MREPEAT194(macro, data)   macro(194, data)
+#define MREPEAT196(macro, data)    MREPEAT195(macro, data)   macro(195, data)
+#define MREPEAT197(macro, data)    MREPEAT196(macro, data)   macro(196, data)
+#define MREPEAT198(macro, data)    MREPEAT197(macro, data)   macro(197, data)
+#define MREPEAT199(macro, data)    MREPEAT198(macro, data)   macro(198, data)
+#define MREPEAT200(macro, data)    MREPEAT199(macro, data)   macro(199, data)
+#define MREPEAT201(macro, data)    MREPEAT200(macro, data)   macro(200, data)
+#define MREPEAT202(macro, data)    MREPEAT201(macro, data)   macro(201, data)
+#define MREPEAT203(macro, data)    MREPEAT202(macro, data)   macro(202, data)
+#define MREPEAT204(macro, data)    MREPEAT203(macro, data)   macro(203, data)
+#define MREPEAT205(macro, data)    MREPEAT204(macro, data)   macro(204, data)
+#define MREPEAT206(macro, data)    MREPEAT205(macro, data)   macro(205, data)
+#define MREPEAT207(macro, data)    MREPEAT206(macro, data)   macro(206, data)
+#define MREPEAT208(macro, data)    MREPEAT207(macro, data)   macro(207, data)
+#define MREPEAT209(macro, data)    MREPEAT208(macro, data)   macro(208, data)
+#define MREPEAT210(macro, data)    MREPEAT209(macro, data)   macro(209, data)
+#define MREPEAT211(macro, data)    MREPEAT210(macro, data)   macro(210, data)
+#define MREPEAT212(macro, data)    MREPEAT211(macro, data)   macro(211, data)
+#define MREPEAT213(macro, data)    MREPEAT212(macro, data)   macro(212, data)
+#define MREPEAT214(macro, data)    MREPEAT213(macro, data)   macro(213, data)
+#define MREPEAT215(macro, data)    MREPEAT214(macro, data)   macro(214, data)
+#define MREPEAT216(macro, data)    MREPEAT215(macro, data)   macro(215, data)
+#define MREPEAT217(macro, data)    MREPEAT216(macro, data)   macro(216, data)
+#define MREPEAT218(macro, data)    MREPEAT217(macro, data)   macro(217, data)
+#define MREPEAT219(macro, data)    MREPEAT218(macro, data)   macro(218, data)
+#define MREPEAT220(macro, data)    MREPEAT219(macro, data)   macro(219, data)
+#define MREPEAT221(macro, data)    MREPEAT220(macro, data)   macro(220, data)
+#define MREPEAT222(macro, data)    MREPEAT221(macro, data)   macro(221, data)
+#define MREPEAT223(macro, data)    MREPEAT222(macro, data)   macro(222, data)
+#define MREPEAT224(macro, data)    MREPEAT223(macro, data)   macro(223, data)
+#define MREPEAT225(macro, data)    MREPEAT224(macro, data)   macro(224, data)
+#define MREPEAT226(macro, data)    MREPEAT225(macro, data)   macro(225, data)
+#define MREPEAT227(macro, data)    MREPEAT226(macro, data)   macro(226, data)
+#define MREPEAT228(macro, data)    MREPEAT227(macro, data)   macro(227, data)
+#define MREPEAT229(macro, data)    MREPEAT228(macro, data)   macro(228, data)
+#define MREPEAT230(macro, data)    MREPEAT229(macro, data)   macro(229, data)
+#define MREPEAT231(macro, data)    MREPEAT230(macro, data)   macro(230, data)
+#define MREPEAT232(macro, data)    MREPEAT231(macro, data)   macro(231, data)
+#define MREPEAT233(macro, data)    MREPEAT232(macro, data)   macro(232, data)
+#define MREPEAT234(macro, data)    MREPEAT233(macro, data)   macro(233, data)
+#define MREPEAT235(macro, data)    MREPEAT234(macro, data)   macro(234, data)
+#define MREPEAT236(macro, data)    MREPEAT235(macro, data)   macro(235, data)
+#define MREPEAT237(macro, data)    MREPEAT236(macro, data)   macro(236, data)
+#define MREPEAT238(macro, data)    MREPEAT237(macro, data)   macro(237, data)
+#define MREPEAT239(macro, data)    MREPEAT238(macro, data)   macro(238, data)
+#define MREPEAT240(macro, data)    MREPEAT239(macro, data)   macro(239, data)
+#define MREPEAT241(macro, data)    MREPEAT240(macro, data)   macro(240, data)
+#define MREPEAT242(macro, data)    MREPEAT241(macro, data)   macro(241, data)
+#define MREPEAT243(macro, data)    MREPEAT242(macro, data)   macro(242, data)
+#define MREPEAT244(macro, data)    MREPEAT243(macro, data)   macro(243, data)
+#define MREPEAT245(macro, data)    MREPEAT244(macro, data)   macro(244, data)
+#define MREPEAT246(macro, data)    MREPEAT245(macro, data)   macro(245, data)
+#define MREPEAT247(macro, data)    MREPEAT246(macro, data)   macro(246, data)
+#define MREPEAT248(macro, data)    MREPEAT247(macro, data)   macro(247, data)
+#define MREPEAT249(macro, data)    MREPEAT248(macro, data)   macro(248, data)
+#define MREPEAT250(macro, data)    MREPEAT249(macro, data)   macro(249, data)
+#define MREPEAT251(macro, data)    MREPEAT250(macro, data)   macro(250, data)
+#define MREPEAT252(macro, data)    MREPEAT251(macro, data)   macro(251, data)
+#define MREPEAT253(macro, data)    MREPEAT252(macro, data)   macro(252, data)
+#define MREPEAT254(macro, data)    MREPEAT253(macro, data)   macro(253, data)
+#define MREPEAT255(macro, data)    MREPEAT254(macro, data)   macro(254, data)
+#define MREPEAT256(macro, data)    MREPEAT255(macro, data)   macro(255, data)
+
+/** @} */
+
+#endif  /* _MREPEAT_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/preprocessor.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/preprocessor.h
new file mode 100644
index 0000000000..8576e1e473
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/preprocessor.h
@@ -0,0 +1,55 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor utils.
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _PREPROCESSOR_H_
+#define _PREPROCESSOR_H_
+
+#include "tpaste.h"
+#include "stringz.h"
+#include "mrepeat.h"
+#include "mrecursion.h"
+
+#endif  // _PREPROCESSOR_H_
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/stringz.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/stringz.h
new file mode 100644
index 0000000000..3406048440
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/stringz.h
@@ -0,0 +1,84 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor stringizing utils.
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _STRINGZ_H_
+#define _STRINGZ_H_
+
+/**
+ * \defgroup group_sam0_utils_stringz Preprocessor - Stringize
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \brief Stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * May be used only within macros with the token passed as an argument if the
+ * token is \#defined.
+ *
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
+ * writing "A0".
+ */
+#define STRINGZ(x)                                #x
+
+/** \brief Absolute stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * No restriction of use if the token is \#defined.
+ *
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
+ * equivalent to writing "A0".
+ */
+#define ASTRINGZ(x)                               STRINGZ(x)
+
+/** @} */
+
+#endif  // _STRINGZ_H_
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/tpaste.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/tpaste.h
new file mode 100644
index 0000000000..b1c77c623d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/tpaste.h
@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor token pasting utils.
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _TPASTE_H_
+#define _TPASTE_H_
+
+/**
+ * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
+ * equivalent to writing U32.
+ *
+ * @{ */
+#define TPASTE2( a, b)                            a##b
+#define TPASTE3( a, b, c)                         a##b##c
+#define TPASTE4( a, b, c, d)                      a##b##c##d
+#define TPASTE5( a, b, c, d, e)                   a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f)                a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g)             a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h)          a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i)       a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j)    a##b##c##d##e##f##g##h##i##j
+/** @} */
+
+/** \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * No restriction of use if the tokens are \#defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
+ * as 32 is equivalent to writing U32.
+ *
+ * @{ */
+#define ATPASTE2( a, b)                           TPASTE2( a, b)
+#define ATPASTE3( a, b, c)                        TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d)                     TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e)                  TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f)               TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g)            TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h)         TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i)      TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j)   TPASTE10(a, b, c, d, e, f, g, h, i, j)
+/** @} */
+
+/** @} */
+
+#endif  // _TPASTE_H_
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/status_codes.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/status_codes.h
new file mode 100644
index 0000000000..6501e7e474
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/status_codes.h
@@ -0,0 +1,158 @@
+/**
+ * \file
+ *
+ * \brief Status code definitions.
+ *
+ * This file defines various status codes returned by functions,
+ * indicating success or failure as well as what kind of failure.
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef STATUS_CODES_H_INCLUDED
+#define STATUS_CODES_H_INCLUDED
+
+#include <stdint.h>
+
+/**
+ * \defgroup group_sam0_utils_status_codes Status Codes
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** Mask to retrieve the error category of a status code. */
+#define STATUS_CATEGORY_MASK  0xF0
+
+/** Mask to retrieve the error code within the category of a status code. */
+#define STATUS_ERROR_MASK     0x0F
+
+/** Status code error categories. */
+enum status_categories {
+	STATUS_CATEGORY_OK                = 0x00,
+	STATUS_CATEGORY_COMMON            = 0x10,
+	STATUS_CATEGORY_ANALOG            = 0x30,
+	STATUS_CATEGORY_COM               = 0x40,
+	STATUS_CATEGORY_IO                = 0x50,
+};
+
+/**
+ * Status code that may be returned by shell commands and protocol
+ * implementations.
+ *
+ * \note Any change to these status codes and the corresponding
+ * message strings is strictly forbidden. New codes can be added,
+ * however, but make sure that any message string tables are updated
+ * at the same time.
+ */
+enum status_code {
+	STATUS_OK                         = STATUS_CATEGORY_OK     | 0x00,
+	STATUS_VALID_DATA                 = STATUS_CATEGORY_OK     | 0x01,
+	STATUS_NO_CHANGE                  = STATUS_CATEGORY_OK     | 0x02,
+	STATUS_ABORTED                    = STATUS_CATEGORY_OK     | 0x04,
+	STATUS_BUSY                       = STATUS_CATEGORY_OK     | 0x05,
+	STATUS_SUSPEND                    = STATUS_CATEGORY_OK     | 0x06,
+
+	STATUS_ERR_IO                     = STATUS_CATEGORY_COMMON | 0x00,
+	STATUS_ERR_REQ_FLUSHED            = STATUS_CATEGORY_COMMON | 0x01,
+	STATUS_ERR_TIMEOUT                = STATUS_CATEGORY_COMMON | 0x02,
+	STATUS_ERR_BAD_DATA               = STATUS_CATEGORY_COMMON | 0x03,
+	STATUS_ERR_NOT_FOUND              = STATUS_CATEGORY_COMMON | 0x04,
+	STATUS_ERR_UNSUPPORTED_DEV        = STATUS_CATEGORY_COMMON | 0x05,
+	STATUS_ERR_NO_MEMORY              = STATUS_CATEGORY_COMMON | 0x06,
+	STATUS_ERR_INVALID_ARG            = STATUS_CATEGORY_COMMON | 0x07,
+	STATUS_ERR_BAD_ADDRESS            = STATUS_CATEGORY_COMMON | 0x08,
+	STATUS_ERR_BAD_FORMAT             = STATUS_CATEGORY_COMMON | 0x0A,
+	STATUS_ERR_BAD_FRQ                = STATUS_CATEGORY_COMMON | 0x0B,
+	STATUS_ERR_DENIED                 = STATUS_CATEGORY_COMMON | 0x0c,
+	STATUS_ERR_ALREADY_INITIALIZED    = STATUS_CATEGORY_COMMON | 0x0d,
+	STATUS_ERR_OVERFLOW               = STATUS_CATEGORY_COMMON | 0x0e,
+	STATUS_ERR_NOT_INITIALIZED        = STATUS_CATEGORY_COMMON | 0x0f,
+
+	STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
+	STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
+
+	STATUS_ERR_BAUDRATE_UNAVAILABLE   = STATUS_CATEGORY_COM    | 0x00,
+	STATUS_ERR_PACKET_COLLISION       = STATUS_CATEGORY_COM    | 0x01,
+	STATUS_ERR_PROTOCOL               = STATUS_CATEGORY_COM    | 0x02,
+
+	STATUS_ERR_PIN_MUX_INVALID        = STATUS_CATEGORY_IO     | 0x00,
+};
+typedef enum status_code status_code_genare_t;
+
+/**
+  Status codes used by MAC stack.
+ */
+enum status_code_wireless {
+	//STATUS_OK               =  0, //!< Success
+	ERR_IO_ERROR            =  -1, //!< I/O error
+	ERR_FLUSHED             =  -2, //!< Request flushed from queue
+	ERR_TIMEOUT             =  -3, //!< Operation timed out
+	ERR_BAD_DATA            =  -4, //!< Data integrity check failed
+	ERR_PROTOCOL            =  -5, //!< Protocol error
+	ERR_UNSUPPORTED_DEV     =  -6, //!< Unsupported device
+	ERR_NO_MEMORY           =  -7, //!< Insufficient memory
+	ERR_INVALID_ARG         =  -8, //!< Invalid argument
+	ERR_BAD_ADDRESS         =  -9, //!< Bad address
+	ERR_BUSY                =  -10, //!< Resource is busy
+	ERR_BAD_FORMAT          =  -11, //!< Data format not recognized
+	ERR_NO_TIMER            =  -12, //!< No timer available
+	ERR_TIMER_ALREADY_RUNNING   =  -13, //!< Timer already running
+	ERR_TIMER_NOT_RUNNING   =  -14, //!< Timer not running
+
+	/**
+	 * \brief Operation in progress
+	 *
+	 * This status code is for driver-internal use when an operation
+	 * is currently being performed.
+	 *
+	 * \note Drivers should never return this status code to any
+	 * callers. It is strictly for internal use.
+	 */
+	OPERATION_IN_PROGRESS	= -128,
+};
+
+typedef enum status_code_wireless status_code_t;
+
+/** @} */
+
+#endif /* STATUS_CODES_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/read.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/read.c
new file mode 100644
index 0000000000..77c7cbd63d
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/read.c
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief System-specific implementation of the \ref _read function used by
+ *         the standard library.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "compiler.h"
+
+/**
+ * \defgroup group_common_utils_stdio Standard I/O (stdio)
+ *
+ * Common standard I/O driver that implements the stdio
+ * read and write functions on AVR and SAM devices.
+ *
+ * \{
+ */
+
+extern volatile void *volatile stdio_base;
+void (*ptr_get)(void volatile*, char*);
+
+
+// IAR common implementation
+#if ( defined(__ICCARM__) )
+
+#include <yfuns.h>
+
+_STD_BEGIN
+
+#pragma module_name = "?__read"
+
+/*! \brief Reads a number of bytes, at most \a size, into the memory area
+ *         pointed to by \a buffer.
+ *
+ * \param handle File handle to read from.
+ * \param buffer Pointer to buffer to write read bytes to.
+ * \param size Number of bytes to read.
+ *
+ * \return The number of bytes read, \c 0 at the end of the file, or
+ *         \c _LLIO_ERROR on failure.
+ */
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+	int nChars = 0;
+	// This implementation only reads from stdin.
+	// For all other file handles, it returns failure.
+	if (handle != _LLIO_STDIN) {
+		return _LLIO_ERROR;
+	}
+	for (; size > 0; --size) {
+		ptr_get(stdio_base, (char*)buffer);
+		buffer++;
+		nChars++;
+	}
+	return nChars;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+int __close(int handle)
+{
+	UNUSED(handle);
+	return 0;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+int remove(const char* val)
+{
+	UNUSED(val);
+	return 0;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+long __lseek(int handle, long val, int val2)
+{
+	UNUSED(handle);
+	UNUSED(val2);
+	return val;
+}
+
+_STD_END
+
+// GCC implementation
+#elif (defined(__GNUC__))
+
+int __attribute__((weak))
+_read (int file, char * ptr, int len); // Remove GCC compiler warning
+
+int __attribute__((weak))
+_read (int file, char * ptr, int len)
+{
+	int nChars = 0;
+
+	if (file != 0) {
+		return -1;
+	}
+
+	for (; len > 0; --len) {
+		ptr_get(stdio_base, ptr);
+		ptr++;
+		nChars++;
+	}
+	return nChars;
+}
+
+#endif
+
+/**
+ * \}
+ */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/stdio_serial/stdio_serial.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/stdio_serial/stdio_serial.h
new file mode 100644
index 0000000000..bf8c4f5eee
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/stdio_serial/stdio_serial.h
@@ -0,0 +1,150 @@
+/**
+ *
+ * \file
+ *
+ * \brief Common Standard I/O Serial Management.
+ *
+ * This file defines a useful set of functions for the Stdio Serial interface on
+ * SAM0 devices.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef STDIO_SERIAL_H_INCLUDED
+#define STDIO_SERIAL_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio)
+ * \ingroup group_common_utils_stdio
+ *
+ * Common standard serial I/O management driver that
+ * implements a stdio serial interface on AVR and SAM devices.
+ *
+ * @{
+ */
+
+#include <serial.h>
+#include <stdio.h>
+#include <compiler.h>
+
+/** Pointer to the base of the USART module instance to use for stdio. */
+extern volatile void *volatile stdio_base;
+
+/** Pointer to the external low level write function. */
+extern int (*ptr_put)(void volatile*, char);
+
+/** Pointer to the external low level read function. */
+extern void (*ptr_get)(void volatile*, char*);
+
+#if SAM0
+/** \brief Initializes the stdio in Serial Mode.
+ *
+ * \param module       Software USART instance to associate with the hardware.
+ * \param hw           Base address of the USART hardware instance.
+ * \param config       USART configuration parameters for the STDIO stream.
+ *
+ */
+static inline void stdio_serial_init(
+		struct usart_module *const module,
+		usart_inst_t const hw,
+		const struct usart_config *const config)
+{
+	stdio_base = (void *)module;
+	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+
+	usart_serial_init(module, hw, config);
+# if defined(__GNUC__)
+	// Specify that stdout and stdin should not be buffered.
+	setbuf(stdout, NULL);
+	setbuf(stdin, NULL);
+	// Note: Already the case in IAR's Normal DLIB default configuration
+	// and AVR GCC library:
+	// - printf() emits one character at a time.
+	// - getchar() requests only 1 byte to exit.
+#  endif
+}
+#endif
+
+#if SAMB
+/** \brief Initializes the stdio in Serial Mode.
+ *
+ * \param module       Software UART instance to associate with the hardware.
+ * \param hw           Base address of the UART hardware instance.
+ * \param config       UART configuration parameters for the STDIO stream.
+ *
+ */
+static inline void stdio_serial_init(
+		struct uart_module *const module,
+		Uart * const hw,
+		const struct uart_config *const config)
+{
+	stdio_base = (void *)module;
+	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+
+	usart_serial_init(module, hw, config);
+# if defined(__GNUC__)
+	// Specify that stdout and stdin should not be buffered.
+	setbuf(stdout, NULL);
+	setbuf(stdin, NULL);
+	// Note: Already the case in IAR's Normal DLIB default configuration
+	// and AVR GCC library:
+	// - printf() emits one character at a time.
+	// - getchar() requests only 1 byte to exit.
+#  endif
+}
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _STDIO_SERIAL_H_
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/write.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/write.c
new file mode 100644
index 0000000000..9ef442a423
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/write.c
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief System-specific implementation of the \ref _write function used by
+ *         the standard library.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "compiler.h"
+
+/**
+ * \addtogroup group_common_utils_stdio
+ *
+ * \{
+ */
+
+volatile void *volatile stdio_base;
+int (*ptr_put)(void volatile*, char);
+
+
+#if ( defined(__ICCARM__))
+
+#include <yfuns.h>
+
+_STD_BEGIN
+
+#pragma module_name = "?__write"
+
+/*! \brief Writes a number of bytes, at most \a size, from the memory area
+ *         pointed to by \a buffer.
+ *
+ * If \a buffer is zero then \ref __write performs flushing of internal buffers,
+ * if any. In this case, \a handle can be \c -1 to indicate that all handles
+ * should be flushed.
+ *
+ * \param handle File handle to write to.
+ * \param buffer Pointer to buffer to read bytes to write from.
+ * \param size Number of bytes to write.
+ *
+ * \return The number of bytes written, or \c _LLIO_ERROR on failure.
+ */
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+	size_t nChars = 0;
+
+	if (buffer == 0) {
+		// This means that we should flush internal buffers.
+		return 0;
+	}
+
+	// This implementation only writes to stdout and stderr.
+	// For all other file handles, it returns failure.
+	if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) {
+		return _LLIO_ERROR;
+	}
+
+	for (; size != 0; --size) {
+		if (ptr_put(stdio_base, *buffer++) < 0) {
+			return _LLIO_ERROR;
+		}
+		++nChars;
+	}
+	return nChars;
+}
+
+_STD_END
+
+
+#elif (defined(__GNUC__))
+
+int __attribute__((weak))
+_write (int file, char * ptr, int len);
+
+int __attribute__((weak))
+_write (int file, char * ptr, int len)
+{
+	int nChars = 0;
+
+	if ((file != 1) && (file != 2) && (file!=3)) {
+		return -1;
+	}
+
+	for (; len != 0; --len) {
+		if (ptr_put(stdio_base, *ptr++) < 0) {
+			return -1;
+		}
+		++nChars;
+	}
+	return nChars;
+}
+
+#endif
+
+/**
+ * \}
+ */
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/syscalls/gcc/syscalls.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/syscalls/gcc/syscalls.c
new file mode 100644
index 0000000000..d3e2fbf071
--- /dev/null
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/syscalls/gcc/syscalls.c
@@ -0,0 +1,130 @@
+/**
+ * \file
+ *
+ * \brief Syscalls for SAM0 (GCC).
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#undef errno
+extern int errno;
+extern int _end;
+
+extern caddr_t _sbrk(int incr);
+extern int link(char *old, char *new);
+extern int _close(int file);
+extern int _fstat(int file, struct stat *st);
+extern int _isatty(int file);
+extern int _lseek(int file, int ptr, int dir);
+extern void _exit(int status);
+extern void _kill(int pid, int sig);
+extern int _getpid(void);
+
+extern caddr_t _sbrk(int incr)
+{
+	static unsigned char *heap = NULL;
+	unsigned char *prev_heap;
+
+	if (heap == NULL) {
+		heap = (unsigned char *)&_end;
+	}
+	prev_heap = heap;
+
+	heap += incr;
+
+	return (caddr_t) prev_heap;
+}
+
+extern int link(char *old, char *new)
+{
+	return -1;
+}
+
+extern int _close(int file)
+{
+	return -1;
+}
+
+extern int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+
+	return 0;
+}
+
+extern int _isatty(int file)
+{
+	return 1;
+}
+
+extern int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+extern void _exit(int status)
+{
+	asm("BKPT #0");
+	for (;;);
+}
+
+extern void _kill(int pid, int sig)
+{
+	return;
+}
+
+extern int _getpid(void)
+{
+	return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/samd21/template.uvprojx b/bsp/samd21/template.uvprojx
new file mode 100644
index 0000000000..c24557ae33
--- /dev/null
+++ b/bsp/samd21/template.uvprojx
@@ -0,0 +1,386 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>RT-Thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ATSAMD21J18A</Device>
+          <Vendor>Atmel</Vendor>
+          <PackID>Keil.SAMD21_DFP.1.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ATSAMD21_256 -FS00 -FL040000 -FP0($$Device:ATSAMD21J18A$Flash\ATSAMD21_256.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ATSAMD21J18A$Device\SAMD21\Include\samd21.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ATSAMD21J18A$SVD\SAMD21\ATSAMD21J18A.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>RT-Thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>
diff --git a/bsp/stm32f107/drivers/stm32_eth.c b/bsp/stm32f107/drivers/stm32_eth.c
index d9d1ef9e53..13ddb8deb7 100644
--- a/bsp/stm32f107/drivers/stm32_eth.c
+++ b/bsp/stm32f107/drivers/stm32_eth.c
@@ -3206,7 +3206,12 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
     {
         rt_err_t result;
         result = rt_sem_take(&tx_buf_free, 2);
-        if (result != RT_EOK) return -RT_ERROR;
+        if (result != RT_EOK)
+        {
+            ETH_FlushTransmitFIFO();  // clear fifo
+            ETH_ResumeDMATransmission();	 //	resume dma	
+            return -RT_ERROR;
+        }
     }
 
     offset = 0;
diff --git a/bsp/stm32f429-apollo/drivers/drv_sdio_sd.c b/bsp/stm32f429-apollo/drivers/drv_sdio_sd.c
index 5e160ae669..e1716be0de 100644
--- a/bsp/stm32f429-apollo/drivers/drv_sdio_sd.c
+++ b/bsp/stm32f429-apollo/drivers/drv_sdio_sd.c
@@ -242,10 +242,10 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
     {
         /* non-aligned. */
         uint32_t i;
-        rt_size_t sector_adr;
+        uint64_t sector_adr;
         uint8_t* copy_buffer;
 
-        sector_adr = pos*SECTOR_SIZE;
+        sector_adr = (uint64_t)pos*SECTOR_SIZE;
         copy_buffer = (uint8_t*)buffer;
 
         for(i=0; i<size; i++)
@@ -263,9 +263,9 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
     else
     {
         #if (SD_DMA_MODE==1) 
-        status=SD_ReadBlocks_DMA(buffer,pos*SECTOR_SIZE,size);//通过DMA写SD卡一个扇区
+        status=SD_ReadBlocks_DMA(buffer,(uint64_t)pos*SECTOR_SIZE,size);//通过DMA写SD卡一个扇区
         #else
-        SD_ReadBlocks(buffer,pos*SECTOR_SIZE,size);
+        SD_ReadBlocks(buffer,(uint64_t)pos*SECTOR_SIZE,size);
         #endif
     }
 
@@ -286,10 +286,10 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
     {
         /* non-aligned. */
         uint32_t i;
-        rt_size_t sector_adr;
+        uint64_t sector_adr;
         uint8_t* copy_buffer;
 
-        sector_adr = pos*SECTOR_SIZE;
+        sector_adr = (uint64_t)pos*SECTOR_SIZE;
         copy_buffer = (uint8_t*)buffer;
 
         for(i=0; i<size; i++)
@@ -308,9 +308,9 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
     else
     {
         #if (SD_DMA_MODE==1)   
-        status=SD_WriteBlocks_DMA((uint32_t*)buffer,pos*SECTOR_SIZE,size);
+        status=SD_WriteBlocks_DMA((uint32_t*)buffer,(uint64_t)pos*SECTOR_SIZE,size);
         #else
-        status=SD_WriteBlocks((uint32_t*)buffer,pos*SECTOR_SIZE,size);
+        status=SD_WriteBlocks((uint32_t*)buffer,(uint64_t)pos*SECTOR_SIZE,size);
         #endif
     }
 	// }
diff --git a/components/cplusplus/crt_init.c b/components/cplusplus/crt_init.c
index ebcc4af37d..12c92dc6fb 100755
--- a/components/cplusplus/crt_init.c
+++ b/components/cplusplus/crt_init.c
@@ -44,11 +44,11 @@ void _fini()
 {
 }
 
-WEAK void *__dso_handle = 0;
+RT_WEAK void *__dso_handle = 0;
 
 #endif
 
-WEAK
+RT_WEAK
 int cplusplus_system_init(void)
 {
 #if defined(__GNUC__) && !defined(__CC_ARM)
diff --git a/components/dfs/filesystems/romfs/romfs.c b/components/dfs/filesystems/romfs/romfs.c
index ff4b353059..a571c36ec6 100644
--- a/components/dfs/filesystems/romfs/romfs.c
+++ b/components/dfs/filesystems/romfs/romfs.c
@@ -39,13 +39,13 @@ const static unsigned char _dummy_txt[] =
     0x74,0x68,0x69,0x73,0x20,0x69,0x73,0x20,0x61,0x20,0x66,0x69,0x6c,0x65,0x21,0x0d,0x0a,
 };
 
-const struct romfs_dirent WEAK _root_dirent[] =
+const struct romfs_dirent RT_WEAK _root_dirent[] =
 {
     {ROMFS_DIRENT_DIR, "dummy", (rt_uint8_t *)_dummy, sizeof(_dummy)/sizeof(_dummy[0])},
     {ROMFS_DIRENT_FILE, "dummy.txt", _dummy_txt, sizeof(_dummy_txt)},
 };
 
-const struct romfs_dirent WEAK romfs_root =
+const struct romfs_dirent RT_WEAK romfs_root =
 {
     ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_root_dirent, sizeof(_root_dirent)/sizeof(_root_dirent[0])
 };
diff --git a/components/drivers/KConfig b/components/drivers/KConfig
index 7679ea4493..663b35c188 100644
--- a/components/drivers/KConfig
+++ b/components/drivers/KConfig
@@ -45,6 +45,23 @@ config RT_USING_SPI
     default n
 
     if RT_USING_SPI
+        config RT_USING_SFUD
+            bool "Using Serial Flash Universal Driver"
+            default n
+            if RT_USING_SFUD            
+                config RT_SFUD_USING_SFDP
+                bool "Using auto probe flash JEDEC SFDP parameter"
+                default y
+                
+                config RT_SFUD_USING_FLASH_INFO_TABLE
+                bool "Using defined supported flash chip information table"
+                default y
+                
+                config RT_SFUD_DEBUG
+                bool "Show more SFUD debug information"
+                default n
+            endif
+    
         config RT_USING_W25QXX
             bool "Using W25QXX SPI NorFlash"
             default n
diff --git a/components/drivers/spi/sfud/README.md b/components/drivers/spi/sfud/README.md
index 13ef219154..4ad5f0ee44 100644
--- a/components/drivers/spi/sfud/README.md
+++ b/components/drivers/spi/sfud/README.md
@@ -37,14 +37,16 @@
 |[MX25L3206E](http://www.macronix.com/Lists/DataSheet/Attachments/3199/MX25L3206E,%203V,%2032Mb,%20v1.5.pdf)|Macronix|32Mb|86MHz|鏀寔||
 |[KH25L3206E](http://www.macronix.com.hk/Lists/Datasheet/Attachments/131/KH25L3206E.pdf)|Macronix|32Mb|86Mhz|鏀寔||
 |[SST25VF016B](http://ww1.microchip.com/downloads/en/DeviceDoc/20005044C.pdf)|Microchip|16Mb|50MHz|涓嶆敮鎸亅 SST 宸茶 Microchip 鏀惰喘|
+|[M25P40](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p40.pdf)|Micron|4Mb|75Mhz|涓嶆敮鎸亅 by [redocCheng](https://github.com/redocCheng)|
+|[M25P80](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p80.pdf)|Micron|8Mb|75Mhz|涓嶆敮鎸亅 by [redocCheng](https://github.com/redocCheng)|
 |[M25P32](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p32.pdf)|Micron|32Mb|75Mhz|涓嶆敮鎸亅|
 |[EN25Q32B](http://www.kean.com.au/oshw/WR703N/teardown/EN25Q32B%2032Mbit%20SPI%20Flash.pdf)|EON|32Mb|104MHz|涓嶆敮鎸亅|
-|[GD25Q64B](http://www.gigadevice.com/product/detail/5/364.html)|GigaDevice|64Mb|120Mhz|涓嶆敮鎸亅|
 |[GD25Q16B](http://www.gigadevice.com/product/detail/5/410.html)|GigaDevice|16Mb|120Mhz|涓嶆敮鎸亅 by [TanekLiang](https://github.com/TanekLiang) |
+|[GD25Q64B](http://www.gigadevice.com/product/detail/5/364.html)|GigaDevice|64Mb|120Mhz|涓嶆敮鎸亅|
 |[S25FL216K](http://www.cypress.com/file/197346/download)|Cypress|16Mb|65Mhz|涓嶆敮鎸亅|
 |[S25FL164K](http://www.cypress.com/file/196886/download)|Cypress|64Mb|108Mhz|鏀寔||
-|[A25LQ64](http://www.amictechnology.com/datasheets/A25LQ64.pdf)|AMIC|64Mb|104Mhz|鏀寔||
 |[A25L080](http://www.amictechnology.com/datasheets/A25L080.pdf)|AMIC|8Mb|100Mhz|涓嶆敮鎸亅|
+|[A25LQ64](http://www.amictechnology.com/datasheets/A25LQ64.pdf)|AMIC|64Mb|104Mhz|鏀寔||
 |[F25L004](http://www.esmt.com.tw/db/manager/upload/f25l004.pdf)|ESMT|4Mb|100Mhz|涓嶆敮鎸亅|
 |[PCT25VF016B](http://pctgroup.com.tw/attachments/files/files/248_25VF016B-P.pdf)|PCT|16Mb|80Mhz|涓嶆敮鎸亅SST 鎺堟潈璁稿彲锛屼細琚瘑鍒负 SST25VF016B|
 |[AT45DB161E](http://www.adestotech.com/wp-content/uploads/doc8782.pdf)|ADESTO|16Mb|85MHz|涓嶆敮鎸亅ADESTO 鏀惰喘 Atmel 涓茶闂瓨浜у搧绾縷
diff --git a/components/drivers/spi/sfud/inc/sfud_def.h b/components/drivers/spi/sfud/inc/sfud_def.h
index cc38c3fa1a..1b5636c1b4 100644
--- a/components/drivers/spi/sfud/inc/sfud_def.h
+++ b/components/drivers/spi/sfud/inc/sfud_def.h
@@ -77,7 +77,7 @@ if (!(EXPR))                                                                   \
     else {if (__delay_temp) {__delay_temp();} retry --;}
 
 /* software version number */
-#define SFUD_SW_VERSION                             "1.0.1"
+#define SFUD_SW_VERSION                             "1.0.2"
 /*
  * all defined supported command
  */
diff --git a/components/drivers/spi/sfud/inc/sfud_flash_def.h b/components/drivers/spi/sfud/inc/sfud_flash_def.h
index 06c95b775a..26b5ace3b4 100644
--- a/components/drivers/spi/sfud/inc/sfud_flash_def.h
+++ b/components/drivers/spi/sfud/inc/sfud_flash_def.h
@@ -113,6 +113,8 @@ typedef struct {
     {"W25Q40BV", SFUD_MF_ID_WINBOND, 0x40, 0x13, 512*1024, SFUD_WM_PAGE_256B, 4096, 0x20},                       \
     {"SST25VF016B", SFUD_MF_ID_SST, 0x25, 0x41, 2*1024*1024, SFUD_WM_BYTE|SFUD_WM_AAI, 4096, 0x20},              \
     {"M25P32", SFUD_MF_ID_MICRON, 0x20, 0x16, 4*1024*1024, SFUD_WM_PAGE_256B, 64*1024, 0xD8},                    \
+    {"M25P80", SFUD_MF_ID_MICRON, 0x20, 0x14, 1*1024*1024, SFUD_WM_PAGE_256B, 64*1024, 0xD8},                    \
+    {"M25P40", SFUD_MF_ID_MICRON, 0x20, 0x13, 512*1024, SFUD_WM_PAGE_256B, 64*1024, 0xD8},                       \
     {"EN25Q32B", SFUD_MF_ID_EON, 0x30, 0x16, 4*1024*1024, SFUD_WM_PAGE_256B, 4096, 0x20},                        \
     {"GD25Q64B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x17, 8*1024*1024, SFUD_WM_PAGE_256B, 4096, 0x20},                 \
     {"GD25Q16B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x15, 2*1024*1024, SFUD_WM_PAGE_256B, 4096, 0x20},                 \
diff --git a/components/net/lwip-2.0.0/src/arch/sys_arch.c b/components/net/lwip-2.0.0/src/arch/sys_arch.c
index 7db873f130..c5b4dbbf47 100644
--- a/components/net/lwip-2.0.0/src/arch/sys_arch.c
+++ b/components/net/lwip-2.0.0/src/arch/sys_arch.c
@@ -600,7 +600,7 @@ u32_t sys_now(void)
     return rt_tick_get() * (1000 / RT_TICK_PER_SECOND);
 }
 
-WEAK
+RT_WEAK
 void mem_init(void)
 {
 }
diff --git a/components/net/lwip-2.0.2/src/arch/sys_arch.c b/components/net/lwip-2.0.2/src/arch/sys_arch.c
index cd76a73abe..bb809ac6ad 100644
--- a/components/net/lwip-2.0.2/src/arch/sys_arch.c
+++ b/components/net/lwip-2.0.2/src/arch/sys_arch.c
@@ -177,7 +177,7 @@ int lwip_system_init(void)
 
 	return 0;
 }
-//INIT_COMPONENT_EXPORT(lwip_system_init);
+INIT_COMPONENT_EXPORT(lwip_system_init);
 
 void sys_init(void)
 {
@@ -602,7 +602,7 @@ u32_t sys_now(void)
 }
 
 
-WEAK
+RT_WEAK
 void mem_init(void)
 {
 }
diff --git a/components/net/lwip-2.0.2/src/netif/ethernetif.c b/components/net/lwip-2.0.2/src/netif/ethernetif.c
index c648dcf1a9..5b82649662 100644
--- a/components/net/lwip-2.0.2/src/netif/ethernetif.c
+++ b/components/net/lwip-2.0.2/src/netif/ethernetif.c
@@ -451,7 +451,7 @@ int eth_system_device_init(void)
 
     return (int)result;
 }
-//INIT_DEVICE_EXPORT(eth_system_device_init);
+INIT_DEVICE_EXPORT(eth_system_device_init);
 
 #ifdef RT_USING_FINSH
 #include <finsh.h>
diff --git a/examples/test/device_test.c b/examples/test/device_test.c
index 337eb0dbd0..c1902fe919 100644
--- a/examples/test/device_test.c
+++ b/examples/test/device_test.c
@@ -90,7 +90,7 @@ static rt_err_t _block_device_test(rt_device_t device)
 
         /* step 3:  R/W test */
         {
-            rt_uint32_t i,err_count, sector_no;
+            rt_uint32_t i, err_count, sector_no;
             rt_uint8_t * data_point;
 
             i = rt_device_read(device, 0, read_buffer, 1);
@@ -449,11 +449,13 @@ static rt_err_t _block_device_test(rt_device_t device)
             }
         } /* step 5: multiple sector speed test */
 
+        rt_device_close(device);
         return RT_EOK;
     }// device can read and write.
     else
     {
         // device read only
+        rt_device_close(device);
         return RT_EOK;
     }// device read only
 
@@ -466,6 +468,7 @@ __return:
     {
         rt_free(write_buffer);
     }
+    rt_device_close(device);
     return RT_ERROR;
 }
 
diff --git a/include/rtdef.h b/include/rtdef.h
index 9c6cd8207f..e44f39fdd8 100644
--- a/include/rtdef.h
+++ b/include/rtdef.h
@@ -97,7 +97,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define RT_UNUSED                   __attribute__((unused))
     #define RT_USED                     __attribute__((used))
     #define ALIGN(n)                    __attribute__((aligned(n)))
-    #define WEAK						__weak
+    #define RT_WEAK                     __weak
     #define rt_inline                   static __inline
     /* module compiling */
     #ifdef RT_USING_MODULE
@@ -113,7 +113,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define RT_USED                     __root
     #define PRAGMA(x)                   _Pragma(#x)
     #define ALIGN(n)                    PRAGMA(data_alignment=n)
-    #define WEAK                        __weak
+    #define RT_WEAK                     __weak
     #define rt_inline                   static inline
     #define RTT_API
 
@@ -121,7 +121,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #ifdef RT_USING_NEWLIB
         #include <stdarg.h>
     #else
-		/* the version of GNU GCC must be greater than 4.x */
+        /* the version of GNU GCC must be greater than 4.x */
         typedef __builtin_va_list   __gnuc_va_list;
         typedef __gnuc_va_list      va_list;
         #define va_start(v,l)       __builtin_va_start(v,l)
@@ -133,7 +133,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define RT_UNUSED                   __attribute__((unused))
     #define RT_USED                     __attribute__((used))
     #define ALIGN(n)                    __attribute__((aligned(n)))
-    #define WEAK                        __attribute__((weak))
+    #define RT_WEAK                     __attribute__((weak))
     #define rt_inline                   static __inline
     #define RTT_API
 #elif defined (__ADSPBLACKFIN__)        /* for VisualDSP++ Compiler */
@@ -142,7 +142,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define RT_UNUSED                   __attribute__((unused))
     #define RT_USED                     __attribute__((used))
     #define ALIGN(n)                    __attribute__((aligned(n)))
-	#define WEAK                        __attribute__((weak))
+    #define RT_WEAK                     __attribute__((weak))
     #define rt_inline                   static inline
     #define RTT_API
 #elif defined (_MSC_VER)
@@ -151,7 +151,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define RT_UNUSED
     #define RT_USED
     #define ALIGN(n)                    __declspec(align(n))
-	#define WEAK
+    #define RT_WEAK
     #define rt_inline                   static __inline
     #define RTT_API
 #elif defined (__TI_COMPILER_VERSION__)
@@ -164,7 +164,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define RT_USED
     #define PRAGMA(x)                   _Pragma(#x)
     #define ALIGN(n)
-    #define WEAK
+    #define RT_WEAK
     #define rt_inline                   static inline
     #define RTT_API
 #else
@@ -177,20 +177,20 @@ typedef int (*init_fn_t)(void);
 #ifdef _MSC_VER /* we do not support MS VC++ compiler */
     #define INIT_EXPORT(fn, level)
 #else
-	#if RT_DEBUG_INIT
-		struct rt_init_desc
-		{
-			const char* fn_name;
-			const init_fn_t fn;
-		};
-		#define INIT_EXPORT(fn, level)  		\
-			const char __rti_##fn##_name[] = #fn; \
-			const struct rt_init_desc __rt_init_desc_##fn SECTION(".rti_fn."level) = \
-			{ __rti_##fn##_name, fn};
-	#else
-    	#define INIT_EXPORT(fn, level)  \
-        	const init_fn_t __rt_init_##fn SECTION(".rti_fn."level) = fn
-	#endif
+    #if RT_DEBUG_INIT
+        struct rt_init_desc
+        {
+            const char* fn_name;
+            const init_fn_t fn;
+        };
+        #define INIT_EXPORT(fn, level)          \
+            const char __rti_##fn##_name[] = #fn; \
+            const struct rt_init_desc __rt_init_desc_##fn SECTION(".rti_fn."level) = \
+            { __rti_##fn##_name, fn};
+    #else
+        #define INIT_EXPORT(fn, level)  \
+            const init_fn_t __rt_init_##fn SECTION(".rti_fn."level) = fn
+    #endif
 #endif
 #else
 #define INIT_EXPORT(fn, level)
@@ -206,7 +206,7 @@ typedef int (*init_fn_t)(void);
 /* file system initialization (dfs-elm, dfs-rom, ...) */
 #define INIT_FS_EXPORT(fn)              INIT_EXPORT(fn, "4")
 /* environment initialization (mount disk, ...) */
-#define INIT_ENV_EXPORT(fn)				INIT_EXPORT(fn, "5")
+#define INIT_ENV_EXPORT(fn)             INIT_EXPORT(fn, "5")
 /* appliation initialization (rtgui application etc ...) */
 #define INIT_APP_EXPORT(fn)             INIT_EXPORT(fn, "6")
 
@@ -759,8 +759,8 @@ enum rt_device_class_type
     RT_Device_Class_Pipe,                               /**< Pipe device */
     RT_Device_Class_Portal,                             /**< Portal device */
     RT_Device_Class_Timer,                              /**< Timer device */
-	RT_Device_Class_Miscellaneous,                      /**< Miscellaneous device */
-	RT_Device_Class_Unknown                             /**< unknown device */
+    RT_Device_Class_Miscellaneous,                      /**< Miscellaneous device */
+    RT_Device_Class_Unknown                             /**< unknown device */
 };
 
 /**
@@ -778,9 +778,9 @@ enum rt_device_class_type
 #define RT_DEVICE_FLAG_SUSPENDED        0x020           /**< device is suspended */
 #define RT_DEVICE_FLAG_STREAM           0x040           /**< stream mode */
 
-#define RT_DEVICE_CTRL_CONFIG           0x03    	/* configure device */
-#define RT_DEVICE_CTRL_SET_INT          0x10    	/* enable receive irq */
-#define RT_DEVICE_CTRL_CLR_INT          0x11    	/* disable receive irq */
+#define RT_DEVICE_CTRL_CONFIG           0x03            /* configure device */
+#define RT_DEVICE_CTRL_SET_INT          0x10            /* enable receive irq */
+#define RT_DEVICE_CTRL_CLR_INT          0x11            /* disable receive irq */
 #define RT_DEVICE_CTRL_GET_INT          0x12
 
 #define RT_DEVICE_FLAG_INT_RX           0x100           /**< INT mode on Rx */
@@ -969,15 +969,15 @@ struct rt_module
 {
     struct rt_object             parent;                /**< inherit from object */
 
-    rt_uint32_t                  vstart_addr;            /**< VMA base address for the
+    rt_uint32_t                  vstart_addr;           /**< VMA base address for the
                                                           first LOAD segment. */
     rt_uint8_t                  *module_space;          /**< module memory space */
 
     void                        *module_entry;          /**< the entry address of module */
     rt_thread_t                  module_thread;         /**< the main thread of module */
 
-	rt_uint8_t*                  module_cmd_line;		/**< module command line */
-	rt_uint32_t                  module_cmd_size;		/**< the size of module command line */
+    rt_uint8_t                  *module_cmd_line;       /**< module command line */
+    rt_uint32_t                  module_cmd_size;       /**< the size of module command line */
 
 #ifdef RT_USING_SLAB
     /* module memory allocator */
diff --git a/include/rtthread.h b/include/rtthread.h
index f67bab997f..38fb895702 100644
--- a/include/rtthread.h
+++ b/include/rtthread.h
@@ -262,8 +262,8 @@ rt_err_t rt_memheap_init(struct rt_memheap *memheap,
                          void              *start_addr,
                          rt_uint32_t        size);
 rt_err_t rt_memheap_detach(struct rt_memheap *heap);
-void* rt_memheap_alloc(struct rt_memheap *heap, rt_uint32_t size);
-void *rt_memheap_realloc(struct rt_memheap* heap, void* ptr, rt_size_t newsize);
+void *rt_memheap_alloc(struct rt_memheap *heap, rt_uint32_t size);
+void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize);
 void rt_memheap_free(void *ptr);
 #endif
 
@@ -429,7 +429,7 @@ rt_module_t rt_module_load(const char *name, void *module_ptr);
 rt_err_t rt_module_unload(rt_module_t module);
 #ifdef RT_USING_DFS
 rt_module_t rt_module_open(const char *filename);
-rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int size);
+rt_module_t rt_module_exec_cmd(const char *path, const char *cmd_line, int size);
 #endif
 void *rt_module_malloc(rt_size_t size);
 void *rt_module_realloc(void *ptr, rt_size_t size);
@@ -496,7 +496,7 @@ void rt_kputs(const char *str);
 #endif
 rt_int32_t rt_vsprintf(char *dest, const char *format, va_list arg_ptr);
 rt_int32_t rt_vsnprintf(char *buf, rt_size_t size, const char *fmt, va_list args);
-rt_int32_t rt_sprintf(char *buf ,const char *format, ...);
+rt_int32_t rt_sprintf(char *buf, const char *format, ...);
 rt_int32_t rt_snprintf(char *buf, rt_size_t size, const char *format, ...);
 
 #if defined(RT_USING_DEVICE) && defined(RT_USING_CONSOLE)
@@ -517,8 +517,8 @@ void *rt_memset(void *src, int c, rt_ubase_t n);
 void *rt_memcpy(void *dest, const void *src, rt_ubase_t n);
 
 rt_int32_t rt_strncmp(const char *cs, const char *ct, rt_ubase_t count);
-rt_int32_t rt_strcmp (const char *cs, const char *ct);
-rt_size_t rt_strlen (const char *src);
+rt_int32_t rt_strcmp(const char *cs, const char *ct);
+rt_size_t rt_strlen(const char *src);
 char *rt_strdup(const char *s);
 
 char *rt_strstr(const char *str1, const char *str2);
@@ -531,10 +531,10 @@ rt_uint32_t rt_strcasecmp(const char *a, const char *b);
 void rt_show_version(void);
 
 #ifdef RT_DEBUG
-extern void (*rt_assert_hook)(const char* ex, const char* func, rt_size_t line);
-void rt_assert_set_hook(void (*hook)(const char* ex, const char* func, rt_size_t line));
+extern void (*rt_assert_hook)(const char *ex, const char *func, rt_size_t line);
+void rt_assert_set_hook(void (*hook)(const char *ex, const char *func, rt_size_t line));
 
-void rt_assert_handler(const char* ex, const char* func, rt_size_t line);
+void rt_assert_handler(const char *ex, const char *func, rt_size_t line);
 #endif /* RT_DEBUG */
 
 /**@}*/
diff --git a/libcpu/mips/loongson_1c/stackframe_fpu.h b/libcpu/mips/loongson_1c/stackframe_fpu.h
index 58e9271833..93b8ef10c3 100644
--- a/libcpu/mips/loongson_1c/stackframe_fpu.h
+++ b/libcpu/mips/loongson_1c/stackframe_fpu.h
@@ -37,6 +37,7 @@
     .macro SAVE_FPU
     .set push
     .set noreorder
+#ifdef RT_USING_FPU
     move k1, sp                     /* 保存现场 */
     and k0, k1, 0xFFFFFFF8          /* 8字节对齐 */    
     PTR_SUBU sp, k0, PT_FPU_SIZE    /* 计算栈底 */
@@ -57,6 +58,7 @@
     s.d $f28, PT_FPU_R28(sp)
     s.d $f30, PT_FPU_R30(sp)
     move sp, k1                     /* 恢复现场 */
+#endif
     .set reorder
     .set pop
     .endm
@@ -65,6 +67,7 @@
     .macro RESTORE_FPU
     .set push
     .set noreorder
+#ifdef RT_USING_FPU
     move k1, sp                     /* 保存现场 */
     and k0, k1, 0xFFFFFFF8          /* 8字节对齐 */
     PTR_SUBU sp, k0, PT_FPU_SIZE    /* 计算栈底*/
@@ -85,6 +88,7 @@
     l.d $f28, PT_FPU_R28(sp)
     l.d $f30, PT_FPU_R30(sp)
     move sp, k1                     /* 恢复现场 */
+#endif
     .set reorder
     .set pop
     .endm
diff --git a/src/KConfig b/src/KConfig
index 8c2b73f396..a794389448 100644
--- a/src/KConfig
+++ b/src/KConfig
@@ -38,8 +38,8 @@ config RT_USING_OVERFLOW_CHECK
         Enable thread stack overflow checking. The stack overflow is checking when each thread switch.
 
 config RT_DEBUG_INIT
-    bool "Enable system initialization informat print"
-    default n
+    int "Enable system initialization informat print"
+    default 1
     help
         print the procedure name of initialization
 
diff --git a/src/components.c b/src/components.c
index 2e0d8c0994..13a3822ed3 100644
--- a/src/components.c
+++ b/src/components.c
@@ -41,7 +41,7 @@
 
 #ifdef RT_USING_COMPONENTS_INIT
 /*
- * Components Initialization will initialize some driver and components as following 
+ * Components Initialization will initialize some driver and components as following
  * order:
  * rti_start         --> 0
  * BOARD_EXPORT      --> 1
@@ -51,17 +51,17 @@
  * COMPONENT_EXPORT  --> 3
  * FS_EXPORT         --> 4
  * ENV_EXPORT        --> 5
- * APP_EXPORT        --> 6 
- * 
+ * APP_EXPORT        --> 6
+ *
  * rti_end           --> 6.end
  *
- * These automatically initializaiton, the driver or component initial function must 
+ * These automatically initializaiton, the driver or component initial function must
  * be defined with:
  * INIT_BOARD_EXPORT(fn);
  * INIT_DEVICE_EXPORT(fn);
  * ...
  * INIT_APP_EXPORT(fn);
- * etc. 
+ * etc.
  */
 static int rti_start(void)
 {
@@ -155,11 +155,11 @@ int $Sub$$main(void)
 #elif defined(__ICCARM__)
 extern int main(void);
 /* __low_level_init will auto called by IAR cstartup */
-extern void __iar_data_init3( void );
+extern void __iar_data_init3(void);
 int __low_level_init(void)
 {
-	// call IAR table copy function.
-	__iar_data_init3();
+    // call IAR table copy function.
+    __iar_data_init3();
     rt_hw_interrupt_disable();
     rtthread_startup();
     return 0;
@@ -221,7 +221,7 @@ void rt_application_init(void)
 
 int rtthread_startup(void)
 {
-	rt_hw_interrupt_disable();
+    rt_hw_interrupt_disable();
 
     /* board level initalization
      * NOTE: please initialize heap inside board initialization.
diff --git a/src/idle.c b/src/idle.c
index db87baa484..e268c085a7 100644
--- a/src/idle.c
+++ b/src/idle.c
@@ -55,7 +55,7 @@ static void (*rt_thread_idle_hook)();
 
 /**
  * @ingroup Hook
- * This function sets a hook function to idle thread loop. When the system performs 
+ * This function sets a hook function to idle thread loop. When the system performs
  * idle loop, this hook function should be invoked.
  *
  * @param hook the specified hook function
@@ -77,7 +77,7 @@ rt_inline int _has_defunct_thread(void)
      * into a "if".
      *
      * So add the volatile qualifier here. */
-    const volatile rt_list_t *l = (const volatile rt_list_t*)&rt_thread_defunct;
+    const volatile rt_list_t *l = (const volatile rt_list_t *)&rt_thread_defunct;
 
     return l->next != l;
 }
@@ -155,8 +155,8 @@ void rt_thread_idle_excute(void)
             rt_module_free((rt_module_t)thread->module_id, thread->stack_addr);
         else
 #endif
-        /* release thread's stack */
-        RT_KERNEL_FREE(thread->stack_addr);
+            /* release thread's stack */
+            RT_KERNEL_FREE(thread->stack_addr);
         /* delete thread object */
         rt_object_delete((rt_object_t)thread);
 #endif
@@ -185,12 +185,12 @@ static void rt_thread_idle_entry(void *parameter)
 {
     while (1)
     {
-    #ifdef RT_USING_IDLE_HOOK
+#ifdef RT_USING_IDLE_HOOK
         if (rt_thread_idle_hook != RT_NULL)
         {
             rt_thread_idle_hook();
         }
-    #endif
+#endif
 
         rt_thread_idle_excute();
     }
diff --git a/src/ipc.c b/src/ipc.c
index 9ecd602099..8bdfc93db6 100644
--- a/src/ipc.c
+++ b/src/ipc.c
@@ -644,16 +644,17 @@ rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time)
     register rt_base_t temp;
     struct rt_thread *thread;
 
-    /* this function must not be used in interrupt even if time = 0 */
-    RT_DEBUG_IN_THREAD_CONTEXT;
-
     RT_ASSERT(mutex != RT_NULL);
 
-    /* disable interrupt */
-    temp = rt_hw_interrupt_disable();
-
     /* get current thread */
     thread = rt_thread_self();
+    if (!thread) return RT_EOK; /* return directory if scheduler not started */
+
+    /* this function must not be used in interrupt even if time = 0 */
+    RT_DEBUG_IN_THREAD_CONTEXT;
+
+    /* disable interrupt */
+    temp = rt_hw_interrupt_disable();
 
     RT_OBJECT_HOOK_CALL(rt_object_trytake_hook, (&(mutex->parent.parent)));
 
@@ -777,11 +778,12 @@ rt_err_t rt_mutex_release(rt_mutex_t mutex)
 
     need_schedule = RT_FALSE;
 
-    /* only thread could release mutex because we need test the ownership */
-    RT_DEBUG_IN_THREAD_CONTEXT;
-
     /* get current thread */
     thread = rt_thread_self();
+    if (!thread) return RT_EOK;
+
+    /* only thread could release mutex because we need test the ownership */
+    RT_DEBUG_IN_THREAD_CONTEXT;
 
     /* disable interrupt */
     temp = rt_hw_interrupt_disable();
@@ -1382,8 +1384,8 @@ rt_err_t rt_mb_delete(rt_mailbox_t mb)
     else
 #endif
 
-    /* free mailbox pool */
-    RT_KERNEL_FREE(mb->msg_pool);
+        /* free mailbox pool */
+        RT_KERNEL_FREE(mb->msg_pool);
 
     /* delete mailbox object */
     rt_object_delete(&(mb->parent.parent));
@@ -1775,7 +1777,7 @@ rt_err_t rt_mq_init(rt_mq_t     mq,
     for (temp = 0; temp < mq->max_msgs; temp ++)
     {
         head = (struct rt_mq_message *)((rt_uint8_t *)mq->msg_pool +
-            temp * (mq->msg_size + sizeof(struct rt_mq_message)));
+                                        temp * (mq->msg_size + sizeof(struct rt_mq_message)));
         head->next = mq->msg_queue_free;
         mq->msg_queue_free = head;
     }
@@ -1849,7 +1851,7 @@ rt_mq_t rt_mq_create(const char *name,
     mq->max_msgs = max_msgs;
 
     /* allocate message pool */
-    mq->msg_pool = RT_KERNEL_MALLOC((mq->msg_size + sizeof(struct rt_mq_message))* mq->max_msgs);
+    mq->msg_pool = RT_KERNEL_MALLOC((mq->msg_size + sizeof(struct rt_mq_message)) * mq->max_msgs);
     if (mq->msg_pool == RT_NULL)
     {
         rt_mq_delete(mq);
@@ -1866,7 +1868,7 @@ rt_mq_t rt_mq_create(const char *name,
     for (temp = 0; temp < mq->max_msgs; temp ++)
     {
         head = (struct rt_mq_message *)((rt_uint8_t *)mq->msg_pool +
-               temp * (mq->msg_size + sizeof(struct rt_mq_message)));
+                                        temp * (mq->msg_size + sizeof(struct rt_mq_message)));
         head->next = mq->msg_queue_free;
         mq->msg_queue_free = head;
     }
@@ -1902,8 +1904,8 @@ rt_err_t rt_mq_delete(rt_mq_t mq)
     else
 #endif
 
-    /* free message queue pool */
-    RT_KERNEL_FREE(mq->msg_pool);
+        /* free message queue pool */
+        RT_KERNEL_FREE(mq->msg_pool);
 
     /* delete message queue object */
     rt_object_delete(&(mq->parent.parent));
@@ -1942,7 +1944,7 @@ rt_err_t rt_mq_send(rt_mq_t mq, void *buffer, rt_size_t size)
     temp = rt_hw_interrupt_disable();
 
     /* get a free list, there must be an empty item */
-    msg = (struct rt_mq_message*)mq->msg_queue_free;
+    msg = (struct rt_mq_message *)mq->msg_queue_free;
     /* message queue is full */
     if (msg == RT_NULL)
     {
diff --git a/src/kservice.c b/src/kservice.c
index 123c852971..4ffccaf341 100644
--- a/src/kservice.c
+++ b/src/kservice.c
@@ -118,7 +118,7 @@ int *_rt_errno(void)
 
     tid = rt_thread_self();
     if (tid != RT_NULL)
-        return (int *)&(tid->error);
+        return (int *) & (tid->error);
 
     return (int *)&_errno;
 }
@@ -464,9 +464,9 @@ rt_int32_t rt_strcmp(const char *cs, const char *ct)
 RTM_EXPORT(rt_strcmp);
 /**
  * The  strnlen()  function  returns the number of characters in the
- * string pointed to by s, excluding the terminating null byte ('\0'), 
- * but at most maxlen.  In doing this, strnlen() looks only at the 
- * first maxlen characters in the string pointed to by s and never 
+ * string pointed to by s, excluding the terminating null byte ('\0'),
+ * but at most maxlen.  In doing this, strnlen() looks only at the
+ * first maxlen characters in the string pointed to by s and never
  * beyond s+maxlen.
  *
  * @param s the string
@@ -547,13 +547,13 @@ rt_inline rt_int32_t divide(rt_int32_t *n, rt_int32_t base)
     /* optimized for processor which does not support divide instructions. */
     if (base == 10)
     {
-        res = ((rt_uint32_t)*n) % 10U;
-        *n = ((rt_uint32_t)*n) / 10U;
+        res = ((rt_uint32_t) * n) % 10U;
+        *n = ((rt_uint32_t) * n) / 10U;
     }
     else
     {
-        res = ((rt_uint32_t)*n) % 16U;
-        *n = ((rt_uint32_t)*n) / 16U;
+        res = ((rt_uint32_t) * n) % 16U;
+        *n = ((rt_uint32_t) * n) / 16U;
     }
 
     return res;
@@ -561,7 +561,7 @@ rt_inline rt_int32_t divide(rt_int32_t *n, rt_int32_t base)
 
 rt_inline int skip_atoi(const char **s)
 {
-    register int i=0;
+    register int i = 0;
     while (isdigit(**s))
         i = i * 10 + *((*s)++) - '0';
 
@@ -640,7 +640,7 @@ static char *print_number(char *buf,
 
     i = 0;
     if (num == 0)
-        tmp[i++]='0';
+        tmp[i++] = '0';
     else
     {
         while (num != 0)
@@ -655,12 +655,12 @@ static char *print_number(char *buf,
     size -= i;
 #endif
 
-    if (!(type&(ZEROPAD | LEFT)))
+    if (!(type & (ZEROPAD | LEFT)))
     {
-        if ((sign)&&(size>0))
+        if ((sign) && (size > 0))
             size--;
 
-        while (size-->0)
+        while (size-- > 0)
         {
             if (buf <= end)
                 *buf = ' ';
@@ -681,7 +681,7 @@ static char *print_number(char *buf,
 #ifdef RT_PRINTF_SPECIAL
     if (type & SPECIAL)
     {
-        if (base==8)
+        if (base == 8)
         {
             if (buf <= end)
                 *buf = '0';
@@ -694,7 +694,7 @@ static char *print_number(char *buf,
             ++ buf;
             if (buf <= end)
             {
-                *buf = type & LARGE? 'X' : 'x';
+                *buf = type & LARGE ? 'X' : 'x';
             }
             ++ buf;
         }
@@ -768,7 +768,7 @@ rt_int32_t rt_vsnprintf(char       *buf,
     /* Make sure end is always >= buf */
     if (end < buf)
     {
-        end  = ((char *)-1);
+        end  = ((char *) - 1);
         size = end - buf;
     }
 
@@ -929,7 +929,7 @@ rt_int32_t rt_vsnprintf(char       *buf,
             ++ str;
             continue;
 
-            /* integer number formats - set up the flags and "break" */
+        /* integer number formats - set up the flags and "break" */
         case 'o':
             base = 8;
             break;
@@ -1028,7 +1028,7 @@ RTM_EXPORT(rt_snprintf);
  */
 rt_int32_t rt_vsprintf(char *buf, const char *format, va_list arg_ptr)
 {
-    return rt_vsnprintf(buf, (rt_size_t) -1, format, arg_ptr);
+    return rt_vsnprintf(buf, (rt_size_t) - 1, format, arg_ptr);
 }
 RTM_EXPORT(rt_vsprintf);
 
@@ -1044,7 +1044,7 @@ rt_int32_t rt_sprintf(char *buf, const char *format, ...)
     va_list arg_ptr;
 
     va_start(arg_ptr, format);
-    n = rt_vsprintf(buf ,format, arg_ptr);
+    n = rt_vsprintf(buf, format, arg_ptr);
     va_end(arg_ptr);
 
     return n;
@@ -1101,7 +1101,7 @@ rt_device_t rt_console_set_device(const char *name)
 RTM_EXPORT(rt_console_set_device);
 #endif
 
-WEAK void rt_hw_console_output(const char *str)
+RT_WEAK void rt_hw_console_output(const char *str)
 {
     /* empty console output */
 }
@@ -1183,7 +1183,7 @@ RTM_EXPORT(rt_kprintf);
  *
  * @return the allocated memory block on successful, otherwise returns RT_NULL
  */
-void* rt_malloc_align(rt_size_t size, rt_size_t align)
+void *rt_malloc_align(rt_size_t size, rt_size_t align)
 {
     void *align_ptr;
     void *ptr;
@@ -1198,7 +1198,7 @@ void* rt_malloc_align(rt_size_t size, rt_size_t align)
     ptr = rt_malloc(align_size);
     if (ptr != RT_NULL)
     {
-         /* the allocated memory block is aligned */
+        /* the allocated memory block is aligned */
         if (((rt_uint32_t)ptr & (align - 1)) == 0)
         {
             align_ptr = (void *)((rt_uint32_t)ptr + align);
@@ -1228,7 +1228,7 @@ void rt_free_align(void *ptr)
 {
     void *real_ptr;
 
-    real_ptr = (void *)*(rt_uint32_t *)((rt_uint32_t)ptr - sizeof(void *));
+    real_ptr = (void *) * (rt_uint32_t *)((rt_uint32_t)ptr - sizeof(void *));
     rt_free(real_ptr);
 }
 RTM_EXPORT(rt_free_align);
@@ -1284,13 +1284,14 @@ rt_ubase_t __rt_ffs(rt_ubase_t value)
 
 #ifdef RT_DEBUG
 /* RT_ASSERT(EX)'s hook */
-void (*rt_assert_hook)(const char* ex, const char* func, rt_size_t line);
+void (*rt_assert_hook)(const char *ex, const char *func, rt_size_t line);
 /**
  * This function will set a hook function to RT_ASSERT(EX). It will run when the expression is false.
  *
  * @param hook the hook function
  */
-void rt_assert_set_hook(void (*hook)(const char* ex, const char* func, rt_size_t line)) {
+void rt_assert_set_hook(void (*hook)(const char *ex, const char *func, rt_size_t line))
+{
     rt_assert_hook = hook;
 }
 
@@ -1301,30 +1302,30 @@ void rt_assert_set_hook(void (*hook)(const char* ex, const char* func, rt_size_t
  * @param func the function name when assertion.
  * @param line the file line number when assertion.
  */
-void rt_assert_handler(const char* ex_string, const char* func, rt_size_t line)
+void rt_assert_handler(const char *ex_string, const char *func, rt_size_t line)
 {
     volatile char dummy = 0;
 
     if (rt_assert_hook == RT_NULL)
     {
 #ifdef RT_USING_MODULE
-		if (rt_module_self() != RT_NULL)
-		{
-			/* unload assertion module */
-			rt_module_unload(rt_module_self());
+        if (rt_module_self() != RT_NULL)
+        {
+            /* unload assertion module */
+            rt_module_unload(rt_module_self());
 
-			/* re-schedule */
-			rt_schedule();
-		}
-		else
+            /* re-schedule */
+            rt_schedule();
+        }
+        else
 #endif
-		{
-	        rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line);
-	        while (dummy == 0);
-		}
+        {
+            rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line);
+            while (dummy == 0);
+        }
     }
-	else
-	{
+    else
+    {
         rt_assert_hook(ex_string, func, line);
     }
 }
@@ -1339,7 +1340,7 @@ void *memmove(void *dest, const void *src, size_t n) __attribute__((weak, alias(
 int   memcmp(const void *s1, const void *s2, size_t n) __attribute__((weak, alias("rt_memcmp")));
 
 size_t strlen(const char *s) __attribute__((weak, alias("rt_strlen")));
-char *strstr(const char *s1,const char *s2) __attribute__((weak, alias("rt_strstr")));
+char *strstr(const char *s1, const char *s2) __attribute__((weak, alias("rt_strstr")));
 int strcasecmp(const char *a, const char *b) __attribute__((weak, alias("rt_strcasecmp")));
 char *strncpy(char *dest, const char *src, size_t n) __attribute__((weak, alias("rt_strncpy")));
 int strncmp(const char *cs, const char *ct, size_t count) __attribute__((weak, alias("rt_strncmp")));
diff --git a/src/mem.c b/src/mem.c
index 94e9474f7c..92c85385ab 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -335,7 +335,7 @@ void *rt_malloc(rt_size_t size)
                  */
                 mem->used = 1;
 #ifdef RT_MEM_STATS
-                used_mem += mem->next - ((rt_uint8_t*)mem - heap_ptr);
+                used_mem += mem->next - ((rt_uint8_t *)mem - heap_ptr);
                 if (max_mem < used_mem)
                     max_mem = used_mem;
 #endif
@@ -355,7 +355,7 @@ void *rt_malloc(rt_size_t size)
             rt_sem_release(&heap_sem);
             RT_ASSERT((rt_uint32_t)mem + SIZEOF_STRUCT_MEM + size <= (rt_uint32_t)heap_end);
             RT_ASSERT((rt_uint32_t)((rt_uint8_t *)mem + SIZEOF_STRUCT_MEM) % RT_ALIGN_SIZE == 0);
-            RT_ASSERT((((rt_uint32_t)mem) & (RT_ALIGN_SIZE-1)) == 0);
+            RT_ASSERT((((rt_uint32_t)mem) & (RT_ALIGN_SIZE - 1)) == 0);
 
             RT_DEBUG_LOG(RT_DEBUG_MEM,
                          ("allocate memory at 0x%x, size: %d\n",
@@ -443,7 +443,7 @@ void *rt_realloc(void *rmem, rt_size_t newsize)
 
         ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
         mem2 = (struct heap_mem *)&heap_ptr[ptr2];
-        mem2->magic= HEAP_MAGIC;
+        mem2->magic = HEAP_MAGIC;
         mem2->used = 0;
         mem2->next = mem->next;
         mem2->prev = ptr;
@@ -516,7 +516,7 @@ void rt_free(void *rmem)
 
     if (rmem == RT_NULL)
         return;
-    RT_ASSERT((((rt_uint32_t)rmem) & (RT_ALIGN_SIZE-1)) == 0);
+    RT_ASSERT((((rt_uint32_t)rmem) & (RT_ALIGN_SIZE - 1)) == 0);
     RT_ASSERT((rt_uint8_t *)rmem >= (rt_uint8_t *)heap_ptr &&
               (rt_uint8_t *)rmem < (rt_uint8_t *)heap_end);
 
@@ -556,7 +556,7 @@ void rt_free(void *rmem)
     }
 
 #ifdef RT_MEM_STATS
-    used_mem -= (mem->next - ((rt_uint8_t*)mem - heap_ptr));
+    used_mem -= (mem->next - ((rt_uint8_t *)mem - heap_ptr));
 #endif
 
     /* finally, see if prev or next are free also */
diff --git a/src/memheap.c b/src/memheap.c
index 86e4461675..8b7588a068 100644
--- a/src/memheap.c
+++ b/src/memheap.c
@@ -96,7 +96,7 @@ rt_err_t rt_memheap_init(struct rt_memheap *memheap,
     item->prev_free = item;
 
     item->next = (struct rt_memheap_item *)
-        ((rt_uint8_t *)item + memheap->available_size + RT_MEMHEAP_SIZE);
+                 ((rt_uint8_t *)item + memheap->available_size + RT_MEMHEAP_SIZE);
     item->prev = item->next;
 
     /* block list header */
@@ -315,10 +315,10 @@ void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize)
     header_ptr = (struct rt_memheap_item *)
                  ((rt_uint8_t *)ptr - RT_MEMHEAP_SIZE);
     oldsize = MEMITEM_SIZE(header_ptr);
-     /* re-allocate memory */
+    /* re-allocate memory */
     if (newsize > oldsize)
     {
-        void* new_ptr;
+        void *new_ptr;
         struct rt_memheap_item *next_ptr;
 
         /* lock memheap */
@@ -371,7 +371,7 @@ void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize)
                 next_ptr->prev->next = next_ptr->next;
 
                 /* build a new one on the right place */
-                next_ptr = (struct rt_memheap_item*)((char*)ptr + newsize);
+                next_ptr = (struct rt_memheap_item *)((char *)ptr + newsize);
 
                 RT_DEBUG_LOG(RT_DEBUG_MEMHEAP,
                              ("new free block: block[0x%08x] nextm[0x%08x] prevm[0x%08x]",
@@ -410,7 +410,7 @@ void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize)
         rt_sem_release(&(heap->lock));
 
         /* re-allocate a memory block */
-        new_ptr = (void*)rt_memheap_alloc(heap, newsize);
+        new_ptr = (void *)rt_memheap_alloc(heap, newsize);
         if (new_ptr != RT_NULL)
         {
             rt_memcpy(new_ptr, ptr, oldsize < newsize ? oldsize : newsize);
@@ -503,8 +503,8 @@ void rt_memheap_free(void *ptr)
     struct rt_memheap_item *header_ptr, *new_ptr;
     rt_uint32_t insert_header;
 
-	/* NULL check */
-	if (ptr == RT_NULL) return;
+    /* NULL check */
+    if (ptr == RT_NULL) return;
 
     /* set initial status as OK */
     insert_header = 1;
@@ -610,7 +610,7 @@ void rt_system_heap_init(void *begin_addr, void *end_addr)
 
 void *rt_malloc(rt_size_t size)
 {
-    void* ptr;
+    void *ptr;
 
     /* try to allocate in system heap */
     ptr = rt_memheap_alloc(&_heap, size);
diff --git a/src/mempool.c b/src/mempool.c
index a01e2145c3..3de2d5fd7f 100644
--- a/src/mempool.c
+++ b/src/mempool.c
@@ -299,8 +299,8 @@ rt_err_t rt_mp_delete(rt_mp_t mp)
     else
 #endif
 
-    /* release allocated room */
-    rt_free(mp->start_address);
+        /* release allocated room */
+        rt_free(mp->start_address);
 
     /* detach object */
     rt_object_delete(&(mp->parent));
diff --git a/src/module.c b/src/module.c
index 888701930d..524eeac263 100644
--- a/src/module.c
+++ b/src/module.c
@@ -138,7 +138,7 @@ void list_symbol(void)
          index != _rt_module_symtab_end;
          index ++)
     {
-    	rt_kprintf("%s\n", index->name);
+        rt_kprintf("%s\n", index->name);
     }
 
     return ;
@@ -259,10 +259,10 @@ static int rt_module_arm_relocate(struct rt_module *module,
         j1     = (lower >> 13) & 1;
         j2     = (lower >> 11) & 1;
         offset = (sign << 24) |
-            ((~(j1 ^ sign) & 1) << 23) |
-            ((~(j2 ^ sign) & 1) << 22) |
-            ((upper & 0x03ff) << 12) |
-            ((lower & 0x07ff) << 1);
+                 ((~(j1 ^ sign) & 1) << 23) |
+                 ((~(j2 ^ sign) & 1) << 22) |
+                 ((upper & 0x03ff) << 12) |
+                 ((lower & 0x07ff) << 1);
         if (offset & 0x01000000)
             offset -= 0x02000000;
         offset += sym_val - (Elf32_Addr)where;
@@ -517,7 +517,7 @@ static struct rt_module *_load_shared_object(const char *name,
 
     /* set module entry */
     module->module_entry = module->module_space
-        + elf_module->e_entry - vstart_addr;
+                           + elf_module->e_entry - vstart_addr;
 
     /* handle relocation section */
     for (index = 0; index < elf_module->e_shnum; index ++)
@@ -538,7 +538,7 @@ static struct rt_module *_load_shared_object(const char *name,
         symtab = (Elf32_Sym *)((rt_uint8_t *)module_ptr +
                                shdr[shdr[index].sh_link].sh_offset);
         strtab = (rt_uint8_t *)module_ptr +
-            shdr[shdr[shdr[index].sh_link].sh_link].sh_offset;
+                 shdr[shdr[shdr[index].sh_link].sh_link].sh_offset;
         nr_reloc = (rt_uint32_t)(shdr[index].sh_size / sizeof(Elf32_Rel));
 
         /* relocate every items */
@@ -555,7 +555,7 @@ static struct rt_module *_load_shared_object(const char *name,
 #ifdef MODULE_USING_386
                 || ( (ELF_ST_BIND(sym->st_info) == STB_GLOBAL) && (ELF_ST_TYPE(sym->st_info) == STT_OBJECT) )
 #endif
-				)
+               )
             {
                 rt_module_arm_relocate(module, rel,
                                        (Elf32_Addr)(module->module_space
@@ -597,7 +597,7 @@ static struct rt_module *_load_shared_object(const char *name,
         /* find .dynsym section */
         rt_uint8_t *shstrab;
         shstrab = (rt_uint8_t *)module_ptr +
-            shdr[elf_module->e_shstrndx].sh_offset;
+                  shdr[elf_module->e_shstrndx].sh_offset;
         if (rt_strcmp((const char *)(shstrab + shdr[index].sh_name), ELF_DYNSYM) == 0)
             break;
     }
@@ -609,10 +609,10 @@ static struct rt_module *_load_shared_object(const char *name,
         Elf32_Sym  *symtab = RT_NULL;
         rt_uint8_t *strtab = RT_NULL;
 
-        symtab =(Elf32_Sym *)((rt_uint8_t *)module_ptr + shdr[index].sh_offset);
+        symtab = (Elf32_Sym *)((rt_uint8_t *)module_ptr + shdr[index].sh_offset);
         strtab = (rt_uint8_t *)module_ptr + shdr[shdr[index].sh_link].sh_offset;
 
-        for (i = 0; i < shdr[index].sh_size/sizeof(Elf32_Sym); i++)
+        for (i = 0; i < shdr[index].sh_size / sizeof(Elf32_Sym); i++)
         {
             if ((ELF_ST_BIND(symtab[i].st_info) == STB_GLOBAL) &&
                 (ELF_ST_TYPE(symtab[i].st_info) == STT_FUNC))
@@ -620,9 +620,9 @@ static struct rt_module *_load_shared_object(const char *name,
         }
 
         module->symtab = (struct rt_module_symtab *)rt_malloc
-            (count * sizeof(struct rt_module_symtab));
+                         (count * sizeof(struct rt_module_symtab));
         module->nsym = count;
-        for (i = 0, count = 0; i < shdr[index].sh_size/sizeof(Elf32_Sym); i++)
+        for (i = 0, count = 0; i < shdr[index].sh_size / sizeof(Elf32_Sym); i++)
         {
             rt_size_t length;
 
@@ -686,7 +686,7 @@ static struct rt_module* _load_relocated_object(const char *name,
 
     /* allocate module */
     module = (struct rt_module *)
-        rt_object_allocate(RT_Object_Class_Module, (const char *)name);
+             rt_object_allocate(RT_Object_Class_Module, (const char *)name);
     if (module == RT_NULL)
         return RT_NULL;
 
@@ -777,9 +777,9 @@ static struct rt_module* _load_relocated_object(const char *name,
         symtab   = (Elf32_Sym *)((rt_uint8_t *)module_ptr +
                                  shdr[shdr[index].sh_link].sh_offset);
         strtab   = (rt_uint8_t *)module_ptr +
-            shdr[shdr[shdr[index].sh_link].sh_link].sh_offset;
+                   shdr[shdr[shdr[index].sh_link].sh_link].sh_offset;
         shstrab  = (rt_uint8_t *)module_ptr +
-            shdr[elf_module->e_shstrndx].sh_offset;
+                   shdr[elf_module->e_shstrndx].sh_offset;
         nr_reloc = (rt_uint32_t)(shdr[index].sh_size / sizeof(Elf32_Rel));
 
         /* relocate every items */
@@ -803,7 +803,7 @@ static struct rt_module* _load_relocated_object(const char *name,
                         rt_module_arm_relocate(module, rel,
                                                (Elf32_Addr)(rodata_addr + sym->st_value));
                     }
-                    else if (rt_strncmp((const char*)
+                    else if (rt_strncmp((const char *)
                                         (shstrab + shdr[sym->st_shndx].sh_name), ELF_BSS, 5) == 0)
                     {
                         /* relocate bss section */
@@ -854,7 +854,7 @@ static struct rt_module* _load_relocated_object(const char *name,
                 else
                 {
                     rt_module_arm_relocate(module, rel,
-                                           (Elf32_Addr)((rt_uint8_t*)
+                                           (Elf32_Addr)((rt_uint8_t *)
                                                         module->module_space
                                                         - module_addr
                                                         + sym->st_value));
@@ -868,7 +868,7 @@ static struct rt_module* _load_relocated_object(const char *name,
 }
 
 #define RT_MODULE_ARG_MAX    8
-static int _rt_module_split_arg(char* cmd, rt_size_t length, char* argv[])
+static int _rt_module_split_arg(char *cmd, rt_size_t length, char *argv[])
 {
     int argc = 0;
     char *ptr = cmd;
@@ -876,10 +876,10 @@ static int _rt_module_split_arg(char* cmd, rt_size_t length, char* argv[])
     while ((ptr - cmd) < length)
     {
         /* strip bank and tab */
-        while ((*ptr == ' ' || *ptr == '\t') && (ptr -cmd)< length)
+        while ((*ptr == ' ' || *ptr == '\t') && (ptr - cmd) < length)
             *ptr++ = '\0';
         /* check whether it's the end of line */
-        if ((ptr - cmd)>= length) break;
+        if ((ptr - cmd) >= length) break;
 
         /* handle string with quote */
         if (*ptr == '"')
@@ -887,7 +887,7 @@ static int _rt_module_split_arg(char* cmd, rt_size_t length, char* argv[])
             argv[argc++] = ++ptr;
 
             /* skip this string */
-            while (*ptr != '"' && (ptr-cmd) < length)
+            while (*ptr != '"' && (ptr - cmd) < length)
                 if (*ptr ++ == '\\')  ptr ++;
             if ((ptr - cmd) >= length) break;
 
@@ -908,11 +908,11 @@ static int _rt_module_split_arg(char* cmd, rt_size_t length, char* argv[])
 }
 
 /* module main thread entry */
-static void module_main_entry(void* parameter)
+static void module_main_entry(void *parameter)
 {
     int argc;
     char *argv[RT_MODULE_ARG_MAX];
-    typedef int (*main_func_t)(int argc, char** argv);
+    typedef int (*main_func_t)(int argc, char **argv);
 
     rt_module_t module = (rt_module_t) parameter;
     if (module == RT_NULL)
@@ -934,7 +934,7 @@ static void module_main_entry(void* parameter)
     }
 
     rt_memset(argv, 0x00, sizeof(argv));
-    argc = _rt_module_split_arg((char*)module->module_cmd_line,
+    argc = _rt_module_split_arg((char *)module->module_cmd_line,
                                 module->module_cmd_size, argv);
     if (argc == 0)
         return;
@@ -948,19 +948,19 @@ static void module_main_entry(void* parameter)
 }
 
 /**
- * This function will load a module with a main function from memory and create a 
+ * This function will load a module with a main function from memory and create a
  * main thread for it
  *
  * @param name the name of module, which shall be unique
  * @param module_ptr the memory address of module image
  * @argc the count of argument
- * @argd the argument data, which should be a 
+ * @argd the argument data, which should be a
  *
  * @return the module object
  */
 rt_module_t rt_module_do_main(const char *name,
                               void *module_ptr,
-                              const char* cmd_line,
+                              const char *cmd_line,
                               int line_size)
 {
     rt_module_t module;
@@ -1010,7 +1010,7 @@ rt_module_t rt_module_do_main(const char *name,
     if (line_size && cmd_line)
     {
         /* set module argument */
-        module->module_cmd_line = (rt_uint8_t*)rt_malloc(line_size + 1);
+        module->module_cmd_line = (rt_uint8_t *)rt_malloc(line_size + 1);
         if (module->module_cmd_line)
         {
             rt_memcpy(module->module_cmd_line, cmd_line, line_size);
@@ -1088,7 +1088,7 @@ rt_module_t rt_module_load(const char *name, void *module_ptr)
 #ifdef RT_USING_DFS
 #include <dfs_posix.h>
 
-static char* _module_name(const char *path)
+static char *_module_name(const char *path)
 {
     const char *first, *end, *ptr;
     char *name;
@@ -1136,7 +1136,7 @@ rt_module_t rt_module_open(const char *path)
     /* check parameters */
     RT_ASSERT(path != RT_NULL);
 
-    if (stat(path, &s) !=0)
+    if (stat(path, &s) != 0)
     {
         rt_kprintf("Module: access %s failed\n", path);
 
@@ -1197,7 +1197,7 @@ rt_module_t rt_module_open(const char *path)
  *
  * @return the module object
  */
-rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int size)
+rt_module_t rt_module_exec_cmd(const char *path, const char *cmd_line, int size)
 {
     struct stat s;
     int fd, length;
@@ -1212,7 +1212,7 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int size)
     RT_ASSERT(path != RT_NULL);
 
     /* get file size */
-    if (stat(path, &s) !=0)
+    if (stat(path, &s) != 0)
     {
         rt_kprintf("Module: access %s failed\n", path);
         goto __exit;
@@ -1649,7 +1649,7 @@ static void rt_module_free_page(rt_module_t module,
             }
             else if (page[i].npage == npages)
             {
-                for (index = i; index < module->page_cnt-1; index ++)
+                for (index = i; index < module->page_cnt - 1; index ++)
                 {
                     page[index].page_ptr = page[index + 1].page_ptr;
                     page[index].npage    = page[index + 1].npage;
@@ -1688,8 +1688,8 @@ void *rt_module_malloc(rt_size_t size)
     RT_DEBUG_NOT_IN_INTERRUPT;
 
     nunits = (size + sizeof(struct rt_mem_head) - 1) /
-        sizeof(struct rt_mem_head)
-        + 1;
+             sizeof(struct rt_mem_head)
+             + 1;
 
     RT_ASSERT(size != 0);
     RT_ASSERT(nunits != 0);
@@ -1732,7 +1732,7 @@ void *rt_module_malloc(rt_size_t size)
 
     /* allocate pages from system heap */
     npage = (size + sizeof(struct rt_mem_head) + RT_MM_PAGE_SIZE - 1) /
-        RT_MM_PAGE_SIZE;
+            RT_MM_PAGE_SIZE;
     if ((up = (struct rt_mem_head *)rt_module_malloc_page(npage)) == RT_NULL)
         return RT_NULL;
 
@@ -1765,7 +1765,7 @@ void rt_module_free(rt_module_t module, void *addr)
     RT_DEBUG_NOT_IN_INTERRUPT;
 
     RT_ASSERT(addr);
-    RT_ASSERT((((rt_uint32_t)addr) & (sizeof(struct rt_mem_head) -1)) == 0);
+    RT_ASSERT((((rt_uint32_t)addr) & (sizeof(struct rt_mem_head) - 1)) == 0);
 
     RT_DEBUG_LOG(RT_DEBUG_MODULE, ("rt_module_free 0x%x\n", addr));
 
@@ -1798,8 +1798,8 @@ void rt_module_free(rt_module_t module, void *addr)
                     if ((b->size * sizeof(struct rt_page_info) % RT_MM_PAGE_SIZE) != 0)
                     {
                         rt_size_t nunits = npage *
-                            RT_MM_PAGE_SIZE /
-                            sizeof(struct rt_mem_head);
+                                           RT_MM_PAGE_SIZE /
+                                           sizeof(struct rt_mem_head);
                         /* split memory */
                         r       = b + nunits;
                         r->next = b->next;
@@ -1835,8 +1835,8 @@ void rt_module_free(rt_module_t module, void *addr)
                     if ((n->size * sizeof(struct rt_page_info) % RT_MM_PAGE_SIZE) != 0)
                     {
                         rt_size_t nunits = npage *
-                            RT_MM_PAGE_SIZE /
-                            sizeof(struct rt_mem_head);
+                                           RT_MM_PAGE_SIZE /
+                                           sizeof(struct rt_mem_head);
                         /* split memory */
                         r       = n + nunits;
                         r->next = n->next;
@@ -1921,8 +1921,8 @@ void *rt_module_realloc(void *ptr, rt_size_t size)
     }
 
     nunits = (size + sizeof(struct rt_mem_head) - 1) /
-        sizeof(struct rt_mem_head)
-        +1;
+             sizeof(struct rt_mem_head)
+             + 1;
     b = (struct rt_mem_head *)ptr - 1;
 
     if (nunits <= b->size)
@@ -1984,7 +1984,7 @@ void *rt_module_realloc(void *ptr, rt_size_t size)
         {
             if ((p = rt_module_malloc(size)) == RT_NULL)
                 return RT_NULL;
-            rt_memmove(p, (b+1), ((b->size) * sizeof(struct rt_mem_head)));
+            rt_memmove(p, (b + 1), ((b->size) * sizeof(struct rt_mem_head)));
             rt_module_free(self_module, (void *)(b + 1));
 
             return (void *)(p);
diff --git a/src/object.c b/src/object.c
index d71f792b5d..4fb8bf1db8 100644
--- a/src/object.c
+++ b/src/object.c
@@ -211,7 +211,7 @@ void rt_object_init(struct rt_object         *object,
 #ifdef RT_USING_MODULE
     /* get module object information */
     information = (rt_module_self() != RT_NULL) ?
-        &rt_module_self()->module_object[type] : &rt_object_container[type];
+                  &rt_module_self()->module_object[type] : &rt_object_container[type];
 #else
     /* get object information */
     information = &rt_object_container[type];
@@ -362,8 +362,8 @@ void rt_object_delete(rt_object_t object)
     else
 #endif
 
-    /* free the memory of object */
-    RT_KERNEL_FREE(object);
+        /* free the memory of object */
+        RT_KERNEL_FREE(object);
 }
 #endif
 
@@ -424,7 +424,7 @@ rt_object_t rt_object_find(const char *name, rt_uint8_t type)
 
         if (*name_ptr == '/')
         {
-            struct rt_module* module = RT_NULL;
+            struct rt_module *module = RT_NULL;
 
             /* get the name length of module */
             module_name_length = name_ptr - name;
@@ -435,15 +435,15 @@ rt_object_t rt_object_find(const char *name, rt_uint8_t type)
             /* find module */
             information = &rt_object_container[RT_Object_Class_Module];
             for (node = information->object_list.next;
-                node != &(information->object_list);
-                node  = node->next)
+                 node != &(information->object_list);
+                 node  = node->next)
             {
                 object = rt_list_entry(node, struct rt_object, list);
                 if ((rt_strncmp(object->name, name, module_name_length) == 0) &&
                     (module_name_length == RT_NAME_MAX || object->name[module_name_length] == '\0'))
                 {
                     /* get module */
-                    module = (struct rt_module*)object;
+                    module = (struct rt_module *)object;
                     break;
                 }
             }
diff --git a/src/scheduler.c b/src/scheduler.c
index 186d20e55b..e3e200efc7 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -90,19 +90,19 @@ static void _rt_scheduler_stack_check(struct rt_thread *thread)
     RT_ASSERT(thread != RT_NULL);
 
     if (*((rt_uint8_t *)thread->stack_addr) != '#' ||
-	(rt_uint32_t)thread->sp <= (rt_uint32_t)thread->stack_addr ||
+        (rt_uint32_t)thread->sp <= (rt_uint32_t)thread->stack_addr ||
         (rt_uint32_t)thread->sp >
         (rt_uint32_t)thread->stack_addr + (rt_uint32_t)thread->stack_size)
     {
         rt_uint32_t level;
 
         rt_kprintf("thread:%s stack overflow\n", thread->name);
-        #ifdef RT_USING_FINSH
+#ifdef RT_USING_FINSH
         {
             extern long list_thread(void);
             list_thread();
         }
-        #endif
+#endif
         level = rt_hw_interrupt_disable();
         while (level);
     }
diff --git a/src/slab.c b/src/slab.c
index d1093a7a93..14a2c784b5 100644
--- a/src/slab.c
+++ b/src/slab.c
@@ -222,8 +222,8 @@ static int zone_page_cnt;
 #define PAGE_TYPE_LARGE     0x02
 struct memusage
 {
-    rt_uint32_t type:2 ;        /* page type */
-    rt_uint32_t size:30;        /* pages allocated or offset from zone */
+    rt_uint32_t type: 2 ;       /* page type */
+    rt_uint32_t size: 30;       /* pages allocated or offset from zone */
 };
 static struct memusage *memusage = RT_NULL;
 #define btokup(addr)    \
@@ -238,7 +238,7 @@ struct rt_page_head
     rt_size_t page;                 /* number of page  */
 
     /* dummy */
-    char dummy[RT_MM_PAGE_SIZE - (sizeof(struct rt_page_head*) + sizeof (rt_size_t))];
+    char dummy[RT_MM_PAGE_SIZE - (sizeof(struct rt_page_head *) + sizeof(rt_size_t))];
 };
 static struct rt_page_head *rt_page_list;
 static struct rt_semaphore heap_sem;
@@ -248,7 +248,7 @@ void *rt_page_alloc(rt_size_t npages)
     struct rt_page_head *b, *n;
     struct rt_page_head **prev;
 
-    if(npages == 0)
+    if (npages == 0)
         return RT_NULL;
 
     /* lock heap */
@@ -383,7 +383,7 @@ void rt_system_heap_init(void *begin_addr, void *end_addr)
 
     /* calculate zone size */
     zone_size = ZALLOC_MIN_ZONE_SIZE;
-    while (zone_size < ZALLOC_MAX_ZONE_SIZE && (zone_size << 1) < (limsize/1024))
+    while (zone_size < ZALLOC_MAX_ZONE_SIZE && (zone_size << 1) < (limsize / 1024))
         zone_size <<= 1;
 
     zone_limit = zone_size / 4;
@@ -398,7 +398,7 @@ void rt_system_heap_init(void *begin_addr, void *end_addr)
     /* allocate memusage array */
     limsize  = npages * sizeof(struct memusage);
     limsize  = RT_ALIGN(limsize, RT_MM_PAGE_SIZE);
-    memusage = rt_page_alloc(limsize/RT_MM_PAGE_SIZE);
+    memusage = rt_page_alloc(limsize / RT_MM_PAGE_SIZE);
 
     RT_DEBUG_LOG(RT_DEBUG_SLAB, ("memusage 0x%x, size 0x%x\n",
                                  (rt_uint32_t)memusage, limsize));
@@ -411,20 +411,20 @@ void rt_system_heap_init(void *begin_addr, void *end_addr)
 rt_inline int zoneindex(rt_uint32_t *bytes)
 {
     /* unsigned for shift opt */
-    rt_uint32_t n = (rt_uint32_t)*bytes;
+    rt_uint32_t n = (rt_uint32_t) * bytes;
 
     if (n < 128)
     {
         *bytes = n = (n + 7) & ~7;
 
         /* 8 byte chunks, 16 zones */
-        return(n / 8 - 1);
+        return (n / 8 - 1);
     }
     if (n < 256)
     {
         *bytes = n = (n + 15) & ~15;
 
-        return(n / 16 + 7);
+        return (n / 16 + 7);
     }
     if (n < 8192)
     {
@@ -432,35 +432,35 @@ rt_inline int zoneindex(rt_uint32_t *bytes)
         {
             *bytes = n = (n + 31) & ~31;
 
-            return(n / 32 + 15);
+            return (n / 32 + 15);
         }
         if (n < 1024)
         {
             *bytes = n = (n + 63) & ~63;
 
-            return(n / 64 + 23);
+            return (n / 64 + 23);
         }
         if (n < 2048)
         {
             *bytes = n = (n + 127) & ~127;
 
-            return(n / 128 + 31);
+            return (n / 128 + 31);
         }
         if (n < 4096)
         {
             *bytes = n = (n + 255) & ~255;
 
-            return(n / 256 + 39);
+            return (n / 256 + 39);
         }
         *bytes = n = (n + 511) & ~511;
 
-        return(n / 512 + 47);
+        return (n / 512 + 47);
     }
     if (n < 16384)
     {
         *bytes = n = (n + 1023) & ~1023;
 
-        return(n / 1024 + 55);
+        return (n / 1024 + 55);
     }
 
     rt_kprintf("Unexpected byte count %d", n);
@@ -737,7 +737,7 @@ void *rt_realloc(void *ptr, rt_size_t size)
 
         zoneindex(&size);
         if (z->z_chunksize == size)
-            return(ptr); /* same chunk */
+            return (ptr); /* same chunk */
 
         /*
          * Allocate memory for the new request size.  Note that zoneindex has
@@ -803,7 +803,7 @@ void rt_free(void *ptr)
     RT_OBJECT_HOOK_CALL(rt_free_hook, (ptr));
 
 #ifdef RT_USING_MODULE
-    if(rt_module_self() != RT_NULL)
+    if (rt_module_self() != RT_NULL)
     {
         rt_module_free(rt_module_self(), ptr);
 
diff --git a/src/thread.c b/src/thread.c
index e67fbe0485..0048261e96 100644
--- a/src/thread.c
+++ b/src/thread.c
@@ -55,7 +55,7 @@ static void (*rt_thread_inited_hook) (rt_thread_t thread);
 
 /**
  * @ingroup Hook
- * This function sets a hook function when the system suspend a thread. 
+ * This function sets a hook function when the system suspend a thread.
  *
  * @param hook the specified hook function
  *
@@ -68,7 +68,7 @@ void rt_thread_suspend_sethook(void (*hook)(rt_thread_t thread))
 
 /**
  * @ingroup Hook
- * This function sets a hook function when the system resume a thread. 
+ * This function sets a hook function when the system resume a thread.
  *
  * @param hook the specified hook function
  *
@@ -81,13 +81,13 @@ void rt_thread_resume_sethook(void (*hook)(rt_thread_t thread))
 
 /**
  * @ingroup Hook
- * This function sets a hook function when a thread is initialized. 
+ * This function sets a hook function when a thread is initialized.
  *
  * @param hook the specified hook function
  */
 void rt_thread_inited_sethook(void (*hook)(rt_thread_t thread))
 {
-	rt_thread_inited_hook = hook;
+    rt_thread_inited_hook = hook;
 }
 
 #endif
@@ -151,8 +151,8 @@ static rt_err_t _rt_thread_init(struct rt_thread *thread,
     /* init thread stack */
     rt_memset(thread->stack_addr, '#', thread->stack_size);
     thread->sp = (void *)rt_hw_stack_init(thread->entry, thread->parameter,
-        (void *)((char *)thread->stack_addr + thread->stack_size - 4),
-        (void *)rt_thread_exit);
+                                          (void *)((char *)thread->stack_addr + thread->stack_size - 4),
+                                          (void *)rt_thread_exit);
 
     /* priority init */
     RT_ASSERT(priority < RT_THREAD_PRIORITY_MAX);
@@ -185,7 +185,7 @@ static rt_err_t _rt_thread_init(struct rt_thread *thread,
                   0,
                   RT_TIMER_FLAG_ONE_SHOT);
 
-    RT_OBJECT_HOOK_CALL(rt_thread_inited_hook,(thread));
+    RT_OBJECT_HOOK_CALL(rt_thread_inited_hook, (thread));
 
     return RT_EOK;
 }
@@ -643,7 +643,7 @@ rt_err_t rt_thread_suspend(rt_thread_t thread)
     /* enable interrupt */
     rt_hw_interrupt_enable(temp);
 
-    RT_OBJECT_HOOK_CALL(rt_thread_suspend_hook,(thread));
+    RT_OBJECT_HOOK_CALL(rt_thread_suspend_hook, (thread));
     return RT_EOK;
 }
 RTM_EXPORT(rt_thread_suspend);
@@ -686,7 +686,7 @@ rt_err_t rt_thread_resume(rt_thread_t thread)
     /* insert to schedule ready list */
     rt_schedule_insert_thread(thread);
 
-    RT_OBJECT_HOOK_CALL(rt_thread_resume_hook,(thread));
+    RT_OBJECT_HOOK_CALL(rt_thread_resume_hook, (thread));
     return RT_EOK;
 }
 RTM_EXPORT(rt_thread_resume);
diff --git a/src/timer.c b/src/timer.c
index e34d229be4..1543870aa4 100644
--- a/src/timer.c
+++ b/src/timer.c
@@ -28,7 +28,7 @@
  * 2010-05-12     Bernard      fix the timer check bug.
  * 2010-11-02     Charlie      re-implement tick overflow issue
  * 2012-12-15     Bernard      fix the next timeout issue in soft timer
- * 2014-07-12     Bernard      does not lock scheduler when invoking soft-timer 
+ * 2014-07-12     Bernard      does not lock scheduler when invoking soft-timer
  *                             timeout function.
  */
 
@@ -147,13 +147,13 @@ void rt_timer_dump(rt_list_t timer_heads[])
 {
     rt_list_t *list;
 
-    for (list = timer_heads[RT_TIMER_SKIP_LIST_LEVEL-1].next;
-         list != &timer_heads[RT_TIMER_SKIP_LIST_LEVEL-1];
+    for (list = timer_heads[RT_TIMER_SKIP_LIST_LEVEL - 1].next;
+         list != &timer_heads[RT_TIMER_SKIP_LIST_LEVEL - 1];
          list = list->next)
     {
         struct rt_timer *timer = rt_list_entry(list,
                                                struct rt_timer,
-                                               row[RT_TIMER_SKIP_LIST_LEVEL-1]);
+                                               row[RT_TIMER_SKIP_LIST_LEVEL - 1]);
         rt_kprintf("%d", rt_timer_count_height(timer));
     }
     rt_kprintf("\n");
@@ -303,9 +303,9 @@ rt_err_t rt_timer_start(rt_timer_t timer)
     /* timer check */
     RT_ASSERT(timer != RT_NULL);
 
-	/* stop timer firstly */
-	level = rt_hw_interrupt_disable();
-	/* remove timer from list */
+    /* stop timer firstly */
+    level = rt_hw_interrupt_disable();
+    /* remove timer from list */
     _rt_timer_remove(timer);
     /* change status of timer */
     timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED;
@@ -339,7 +339,7 @@ rt_err_t rt_timer_start(rt_timer_t timer)
     row_head[0]  = &timer_list[0];
     for (row_lvl = 0; row_lvl < RT_TIMER_SKIP_LIST_LEVEL; row_lvl++)
     {
-        for (;row_head[row_lvl] != timer_list[row_lvl].prev;
+        for (; row_head[row_lvl] != timer_list[row_lvl].prev;
              row_head[row_lvl]  = row_head[row_lvl]->next)
         {
             struct rt_timer *t;
@@ -363,7 +363,7 @@ rt_err_t rt_timer_start(rt_timer_t timer)
             }
         }
         if (row_lvl != RT_TIMER_SKIP_LIST_LEVEL - 1)
-            row_head[row_lvl+1] = row_head[row_lvl]+1;
+            row_head[row_lvl + 1] = row_head[row_lvl] + 1;
     }
 
     /* Interestingly, this super simple timer insert counter works very very
@@ -373,8 +373,8 @@ rt_err_t rt_timer_start(rt_timer_t timer)
     random_nr++;
     tst_nr = random_nr;
 
-    rt_list_insert_after(row_head[RT_TIMER_SKIP_LIST_LEVEL-1],
-                         &(timer->row[RT_TIMER_SKIP_LIST_LEVEL-1]));
+    rt_list_insert_after(row_head[RT_TIMER_SKIP_LIST_LEVEL - 1],
+                         &(timer->row[RT_TIMER_SKIP_LIST_LEVEL - 1]));
     for (row_lvl = 2; row_lvl <= RT_TIMER_SKIP_LIST_LEVEL; row_lvl++)
     {
         if (!(tst_nr & RT_TIMER_SKIP_LIST_MASK))
@@ -384,7 +384,7 @@ rt_err_t rt_timer_start(rt_timer_t timer)
             break;
         /* Shift over the bits we have tested. Works well with 1 bit and 2
          * bits. */
-        tst_nr >>= (RT_TIMER_SKIP_LIST_MASK+1)>>1;
+        tst_nr >>= (RT_TIMER_SKIP_LIST_MASK + 1) >> 1;
     }
 
     timer->parent.flag |= RT_TIMER_FLAG_ACTIVATED;
@@ -498,7 +498,7 @@ void rt_timer_check(void)
     /* disable interrupt */
     level = rt_hw_interrupt_disable();
 
-    while (!rt_list_isempty(&rt_timer_list[RT_TIMER_SKIP_LIST_LEVEL-1]))
+    while (!rt_list_isempty(&rt_timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1]))
     {
         t = rt_list_entry(rt_timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1].next,
                           struct rt_timer, row[RT_TIMER_SKIP_LIST_LEVEL - 1]);
@@ -507,7 +507,7 @@ void rt_timer_check(void)
          * It supposes that the new tick shall less than the half duration of
          * tick max.
          */
-        if ((current_tick - t->timeout_tick) < RT_TICK_MAX/2)
+        if ((current_tick - t->timeout_tick) < RT_TICK_MAX / 2)
         {
             RT_OBJECT_HOOK_CALL(rt_timer_timeout_hook, (t));
 
@@ -570,13 +570,13 @@ void rt_soft_timer_check(void)
 
     current_tick = rt_tick_get();
 
-	/* lock scheduler */
-	rt_enter_critical();
+    /* lock scheduler */
+    rt_enter_critical();
 
-    for (n = rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL-1].next;
-         n != &(rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL-1]);)
+    for (n = rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1].next;
+         n != &(rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1]);)
     {
-        t = rt_list_entry(n, struct rt_timer, row[RT_TIMER_SKIP_LIST_LEVEL-1]);
+        t = rt_list_entry(n, struct rt_timer, row[RT_TIMER_SKIP_LIST_LEVEL - 1]);
 
         /*
          * It supposes that the new tick shall less than the half duration of
@@ -592,8 +592,8 @@ void rt_soft_timer_check(void)
             /* remove timer from timer list firstly */
             _rt_timer_remove(t);
 
-			/* not lock scheduler when performing timeout function */
-			rt_exit_critical();
+            /* not lock scheduler when performing timeout function */
+            rt_exit_critical();
             /* call timeout function */
             t->timeout_func(t->parameter);
 
@@ -602,8 +602,8 @@ void rt_soft_timer_check(void)
 
             RT_DEBUG_LOG(RT_DEBUG_TIMER, ("current tick: %d\n", current_tick));
 
-			/* lock scheduler */
-			rt_enter_critical();
+            /* lock scheduler */
+            rt_enter_critical();
 
             if ((t->parent.flag & RT_TIMER_FLAG_PERIODIC) &&
                 (t->parent.flag & RT_TIMER_FLAG_ACTIVATED))
@@ -621,8 +621,8 @@ void rt_soft_timer_check(void)
         else break; /* not check anymore */
     }
 
-	/* unlock scheduler */
-	rt_exit_critical();
+    /* unlock scheduler */
+    rt_exit_critical();
 
     RT_DEBUG_LOG(RT_DEBUG_TIMER, ("software timer check leave\n"));
 }
@@ -649,7 +649,7 @@ static void rt_thread_timer_entry(void *parameter)
             /* get current tick */
             current_tick = rt_tick_get();
 
-            if ((next_timeout - current_tick) < RT_TICK_MAX/2)
+            if ((next_timeout - current_tick) < RT_TICK_MAX / 2)
             {
                 /* get the delta timeout tick */
                 next_timeout = next_timeout - current_tick;
@@ -672,9 +672,9 @@ void rt_system_timer_init(void)
 {
     int i;
 
-    for (i = 0; i < sizeof(rt_timer_list)/sizeof(rt_timer_list[0]); i++)
+    for (i = 0; i < sizeof(rt_timer_list) / sizeof(rt_timer_list[0]); i++)
     {
-        rt_list_init(rt_timer_list+i);
+        rt_list_init(rt_timer_list + i);
     }
 }
 
@@ -689,10 +689,10 @@ void rt_system_timer_thread_init(void)
     int i;
 
     for (i = 0;
-         i < sizeof(rt_soft_timer_list)/sizeof(rt_soft_timer_list[0]);
+         i < sizeof(rt_soft_timer_list) / sizeof(rt_soft_timer_list[0]);
          i++)
     {
-        rt_list_init(rt_soft_timer_list+i);
+        rt_list_init(rt_soft_timer_list + i);
     }
 
     /* start software timer thread */